README.txt

   1 # sim openocd test
   2
   3 in the soc directory, create the verilog file
   4
   5     "python issuer_verilog.py libresoc.v"
   6
   7 copy to libresoc/ directory and open a second terminal
   8
   9 terminal 1:
  10
  11     ./sim.py
  12
  13 terminal 2:
  14
  15     openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
  16
  17 # ecp5 build
  18
  19 same thing: first build libresoc.v and copy it to the libresoc/ directory
  20
  21     ./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
  22     ./versa_ecp5.py --sys-clk-freq=55e6 --load
  23
  24 ulx3s:
  25
  26     ./versa_ecp5.py --sys-clk-freq=12.5e6 --build --fpga=ulx3s85f \
  27                     --yosys-nowidelut
  28     ./versa_ecp5.py --sys-clk-freq=12.5e6 --load --fpga=ulx3s85f
  29
  30 # arty a7 build
  31
  32     export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
  33     ./versa_ecp5.py --sys-clk-freq=25e6 --build  --fpga=artya7100t \
  34                         --toolchain=symbiflow
  35     ./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t  \
  36                         --toolchain=symbiflow
  37