litex/soc/cores/cpu/blackparrot/core.py

   1 # BlackParrot Chip core support for the LiteX SoC.
   2 #
   3 # Authors: Sadullah Canakci & Cansu Demirkiran  <{scanakci,cansu}@bu.edu>
   4 # Copyright (c) 2019, Boston University
   5 # All rights reserved.
   6 #
   7 # Redistribution and use in source and binary forms, with or without
   8 # modification, are permitted provided that the following conditions are
   9 # met:
  10 #
  11 #     * Redistributions of source code must retain the above copyright
  12 #       notice, this list of conditions and the following disclaimer.
  13 #
  14 #     * Redistributions in binary form must reproduce the above
  15 #       copyright notice, this list of conditions and the following
  16 #       disclaimer in the documentation and/or other materials provided
  17 #       with the distribution.
  18 #
  19 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  22 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  23 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  25 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  29 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30
  31 import os
  32 import sys
  33 from migen import *
  34
  35 from litex import get_data_mod
  36 from litex.soc.interconnect import axi
  37 from litex.soc.interconnect import wishbone
  38 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
  39
  40 CPU_VARIANTS = ["standard", "sim"]
  41
  42 GCC_FLAGS = {
  43     "standard": "-march=rv64ima -mabi=lp64 ",
  44     "sim":      "-march=rv64ima -mabi=lp64 ",
  45 }
  46
  47 class BlackParrotRV64(CPU):
  48     name                 = "blackparrot"
  49     human_name           = "BlackParrotRV64[ia]"
  50     variants             = CPU_VARIANTS
  51     data_width           = 64
  52     endianness           = "little"
  53     gcc_triple           = CPU_GCC_TRIPLE_RISCV64
  54     linker_output_format = "elf64-littleriscv"
  55     nop                  = "nop"
  56     io_regions           = {0x50000000: 0x10000000} # origin, length
  57
  58     @property
  59     def mem_map(self):
  60         return {
  61             "csr"      : 0x50000000,
  62             "rom"      : 0x70000000,
  63             "sram"     : 0x71000000,
  64             "main_ram" : 0x80000000,
  65         }
  66
  67     @property
  68     def gcc_flags(self):
  69         flags =  "-mno-save-restore "
  70         flags += GCC_FLAGS[self.variant]
  71         flags += "-D__blackparrot__ "
  72         return flags
  73
  74     def __init__(self, platform, variant="standard"):
  75         self.platform     = platform
  76         self.variant      = variant
  77         self.reset        = Signal()
  78         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
  79         self.periph_buses = [idbus]
  80         self.memory_buses = []
  81
  82         self.cpu_params = dict(
  83             # Clock / Reset
  84             i_clk_i = ClockSignal(),
  85             i_reset_i = ResetSignal() | self.reset,
  86
  87             # Wishbone (I/D)
  88             i_wbm_dat_i  = idbus.dat_r,
  89             o_wbm_dat_o  = idbus.dat_w,
  90             i_wbm_ack_i  = idbus.ack,
  91             i_wbm_err_i  = idbus.err,
  92             #i_wbm_rty_i = 0,
  93             o_wbm_adr_o  = idbus.adr,
  94             o_wbm_stb_o  = idbus.stb,
  95             o_wbm_cyc_o  = idbus.cyc,
  96             o_wbm_sel_o  = idbus.sel,
  97             o_wbm_we_o   = idbus.we,
  98             o_wbm_cti_o  = idbus.cti,
  99             o_wbm_bte_o  = idbus.bte,
 100         )
 101
 102         # Add verilog sources
 103         try:
 104             os.environ["BP"]
 105             os.environ["LITEX"]
 106             self.add_sources(platform, variant)
 107         except:
 108             RED = '\033[91m'
 109             print(RED + "Please set environment variables first, refer to readme file under litex/soc/cores/cpu/blackparrot for details!")
 110             sys.exit(1)
 111
 112
 113     def set_reset_address(self, reset_address):
 114         assert not hasattr(self, "reset_address")
 115         self.reset_address = reset_address
 116         assert reset_address == 0x70000000, "cpu_reset_addr hardcoded to 7x00000000!"
 117
 118     @staticmethod
 119     def add_sources(platform, variant="standard"):
 120         vdir = os.path.abspath(os.path.dirname(__file__))
 121         bp_litex_dir = os.path.join(vdir,"bp_litex")
 122         filename = os.path.join(bp_litex_dir, {
 123             "standard": "flist.fpga",
 124             "sim"     : "flist.verilator"
 125         }[variant])
 126         with open(filename) as openfileobject:
 127             for line in openfileobject:
 128                 temp = line
 129                 if (temp[0] == '/' and temp[1] == '/'):
 130                     continue
 131                 elif ("+incdir+" in temp) :
 132                     s1 = line.find('$')
 133                     s2 = line.find('/')
 134                     dir_ = line[s1:s2]
 135                     a = os.popen('echo '+ str(dir_))
 136                     dir_start = a.read()
 137                     vdir = dir_start[:-1] + line[s2:-1]
 138                     platform.add_verilog_include_path(vdir)
 139                 elif (temp[0]=='$') :
 140                     s2 = line.find('/')
 141                     dir_ = line[0:s2]
 142                     a = os.popen('echo '+ str(dir_))
 143                     dir_start = a.read()
 144                     vdir = dir_start[:-1]+ line[s2:-1]
 145                     platform.add_source(vdir, "systemverilog")
 146                 elif (temp[0] == '/'):
 147                     assert("No support for absolute path for now")
 148
 149     def do_finalize(self):
 150         assert hasattr(self, "reset_address")
 151         self.specials += Instance("ExampleBlackParrotSystem", **self.cpu_params)