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(parent: ee7c816) | patch
up the delay-time on ddr3 reset, put loop around dram init just for fun
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 Apr 2022 14:53:29 +0000 (15:53 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 Apr 2022 14:53:29 +0000 (15:53 +0100)
commit6caa3ae50178425def860b5942817c3228d44e77
tree9c288feae49903584072f56b5bc3aac9aef9de0etree
parentee7c8169a31609628dfc6cac25b0227aecc2febbcommit | diff
up the delay-time on ddr3 reset, put loop around dram init just for fun
coldboot/Makefile diff | blob | history
coldboot/coldboot.c diff | blob | history
src/ls2.py diff | blob | history