src/amd/addrlib/core/addrlib.h

   1 /*
   2  * Copyright © 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 /**
  28 ****************************************************************************************************
  29 * @file  addrlib.h
  30 * @brief Contains the Addr::Lib base class definition.
  31 ****************************************************************************************************
  32 */
  33
  34 #ifndef __ADDR_LIB_H__
  35 #define __ADDR_LIB_H__
  36
  37 #include "addrinterface.h"
  38 #include "addrobject.h"
  39 #include "addrelemlib.h"
  40
  41 #if BRAHMA_BUILD
  42 #include "amdgpu_id.h"
  43 #else
  44 #include "atiid.h"
  45 #endif
  46
  47 #ifndef CIASICIDGFXENGINE_R600
  48 #define CIASICIDGFXENGINE_R600 0x00000006
  49 #endif
  50
  51 #ifndef CIASICIDGFXENGINE_R800
  52 #define CIASICIDGFXENGINE_R800 0x00000008
  53 #endif
  54
  55 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  56 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  57 #endif
  58
  59 namespace Addr
  60 {
  61
  62 /**
  63 ****************************************************************************************************
  64 * @brief Neutral enums that define pipeinterleave
  65 ****************************************************************************************************
  66 */
  67 enum PipeInterleave
  68 {
  69     ADDR_PIPEINTERLEAVE_256B = 256,
  70     ADDR_PIPEINTERLEAVE_512B = 512,
  71 };
  72
  73 /**
  74 ****************************************************************************************************
  75 * @brief Neutral enums that define DRAM row size
  76 ****************************************************************************************************
  77 */
  78 enum RowSize
  79 {
  80     ADDR_ROWSIZE_1KB = 1024,
  81     ADDR_ROWSIZE_2KB = 2048,
  82     ADDR_ROWSIZE_4KB = 4096,
  83     ADDR_ROWSIZE_8KB = 8192,
  84 };
  85
  86 /**
  87 ****************************************************************************************************
  88 * @brief Neutral enums that define bank interleave
  89 ****************************************************************************************************
  90 */
  91 enum BankInterleave
  92 {
  93     ADDR_BANKINTERLEAVE_1 = 1,
  94     ADDR_BANKINTERLEAVE_2 = 2,
  95     ADDR_BANKINTERLEAVE_4 = 4,
  96     ADDR_BANKINTERLEAVE_8 = 8,
  97 };
  98
  99 /**
 100 ****************************************************************************************************
 101 * @brief Neutral enums that define shader engine tile size
 102 ****************************************************************************************************
 103 */
 104 enum ShaderEngineTileSize
 105 {
 106     ADDR_SE_TILESIZE_16 = 16,
 107     ADDR_SE_TILESIZE_32 = 32,
 108 };
 109
 110 /**
 111 ****************************************************************************************************
 112 * @brief Neutral enums that define bank swap size
 113 ****************************************************************************************************
 114 */
 115 enum BankSwapSize
 116 {
 117     ADDR_BANKSWAP_128B = 128,
 118     ADDR_BANKSWAP_256B = 256,
 119     ADDR_BANKSWAP_512B = 512,
 120     ADDR_BANKSWAP_1KB = 1024,
 121 };
 122
 123 /**
 124 ****************************************************************************************************
 125 * @brief This class contains asic independent address lib functionalities
 126 ****************************************************************************************************
 127 */
 128 class Lib : public Object
 129 {
 130 public:
 131     virtual ~Lib();
 132
 133     static ADDR_E_RETURNCODE Create(
 134         const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
 135
 136     /// Pair of Create
 137     VOID Destroy()
 138     {
 139         delete this;
 140     }
 141
 142     static Lib* GetLib(ADDR_HANDLE hLib);
 143
 144     /// Returns AddrLib version (from compiled binary instead include file)
 145     UINT_32 GetVersion()
 146     {
 147         return m_version;
 148     }
 149
 150     /// Returns asic chip family name defined by AddrLib
 151     ChipFamily GetChipFamily()
 152     {
 153         return m_chipFamily;
 154     }
 155
 156     ADDR_E_RETURNCODE Flt32ToDepthPixel(
 157         const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
 158         ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
 159
 160     ADDR_E_RETURNCODE Flt32ToColorPixel(
 161         const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
 162         ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
 163
 164     BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
 165
 166     ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
 167
 168 protected:
 169     Lib();  // Constructor is protected
 170     Lib(const Client* pClient);
 171
 172     /// Pure virtual function to get max alignments
 173     virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const = 0;
 174
 175     //
 176     // Initialization
 177     //
 178     /// Pure Virtual function for Hwl computing internal global parameters from h/w registers
 179     virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0;
 180
 181     /// Pure Virtual function for Hwl converting chip family
 182     virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
 183
 184     /// Get equation table pointer and number of equations
 185     virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
 186     {
 187         *ppEquationTable = NULL;
 188
 189         return 0;
 190     }
 191
 192     //
 193     // Misc helper
 194     //
 195     static UINT_32 Bits2Number(UINT_32 bitNum, ...);
 196
 197     static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
 198     {
 199         return (numFrags != 0) ? numFrags : Max(1u, numSamples);
 200     }
 201
 202     /// Returns pointer of ElemLib
 203     ElemLib* GetElemLib() const
 204     {
 205         return m_pElemLib;
 206     }
 207
 208     /// Returns fillSizeFields flag
 209     UINT_32 GetFillSizeFieldsFlags() const
 210     {
 211         return m_configFlags.fillSizeFields;
 212     }
 213
 214 private:
 215     // Disallow the copy constructor
 216     Lib(const Lib& a);
 217
 218     // Disallow the assignment operator
 219     Lib& operator=(const Lib& a);
 220
 221     VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
 222
 223     VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
 224
 225 protected:
 226     LibClass    m_class;        ///< Store class type (HWL type)
 227
 228     ChipFamily  m_chipFamily;   ///< Chip family translated from the one in atiid.h
 229
 230     UINT_32     m_chipRevision; ///< Revision id from xxx_id.h
 231
 232     UINT_32     m_version;      ///< Current version
 233
 234     //
 235     // Global parameters
 236     //
 237     ConfigFlags m_configFlags;          ///< Global configuration flags. Note this is setup by
 238                                         ///  AddrLib instead of Client except forceLinearAligned
 239
 240     UINT_32     m_pipes;                ///< Number of pipes
 241     UINT_32     m_banks;                ///< Number of banks
 242                                         ///  For r800 this is MC_ARB_RAMCFG.NOOFBANK
 243                                         ///  Keep it here to do default parameter calculation
 244
 245     UINT_32     m_pipeInterleaveBytes;
 246                                         ///< Specifies the size of contiguous address space
 247                                         ///  within each tiling pipe when making linear
 248                                         ///  accesses. (Formerly Group Size)
 249
 250     UINT_32     m_rowSize;              ///< DRAM row size, in bytes
 251
 252     UINT_32     m_minPitchAlignPixels;  ///< Minimum pitch alignment in pixels
 253     UINT_32     m_maxSamples;           ///< Max numSamples
 254 private:
 255     ElemLib*    m_pElemLib;             ///< Element Lib pointer
 256 };
 257
 258 Lib* SiHwlInit  (const Client* pClient);
 259 Lib* CiHwlInit  (const Client* pClient);
 260
 261 } // Addr
 262
 263 #endif