amdgpu/addrlib: Refine the PRT tile mode selection
[mesa.git] / src / amd / addrlib / r800 / ciaddrlib.h
1 /*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ***************************************************************************************************
29 * @file ciaddrlib.h
30 * @brief Contains the CiAddrLib class definition.
31 ***************************************************************************************************
32 */
33
34 #ifndef __CI_ADDR_LIB_H__
35 #define __CI_ADDR_LIB_H__
36
37 #include "addrlib1.h"
38 #include "siaddrlib.h"
39
40 /**
41 ***************************************************************************************************
42 * @brief CI specific settings structure.
43 ***************************************************************************************************
44 */
45 struct CIChipSettings
46 {
47 struct
48 {
49 UINT_32 isSeaIsland : 1;
50 UINT_32 isBonaire : 1;
51 UINT_32 isKaveri : 1;
52 UINT_32 isSpectre : 1;
53 UINT_32 isSpooky : 1;
54 UINT_32 isKalindi : 1;
55 // Hawaii is GFXIP 7.2, similar with CI (Bonaire)
56 UINT_32 isHawaii : 1;
57
58 // VI
59 UINT_32 isVolcanicIslands : 1;
60 UINT_32 isIceland : 1;
61 UINT_32 isTonga : 1;
62 UINT_32 isFiji : 1;
63 UINT_32 isPolaris10 : 1;
64 UINT_32 isPolaris11 : 1;
65 UINT_32 isPolaris12 : 1;
66 // VI fusion (Carrizo)
67 UINT_32 isCarrizo : 1;
68 };
69 };
70
71 /**
72 ***************************************************************************************************
73 * @brief This class is the CI specific address library
74 * function set.
75 ***************************************************************************************************
76 */
77 class CiAddrLib : public SiAddrLib
78 {
79 public:
80 /// Creates CiAddrLib object
81 static AddrLib* CreateObj(const AddrClient* pClient)
82 {
83 return new(pClient) CiAddrLib(pClient);
84 }
85
86 private:
87 CiAddrLib(const AddrClient* pClient);
88 virtual ~CiAddrLib();
89
90 protected:
91
92 // Hwl interface - defined in AddrLib1
93 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
94 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
95 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
96
97 virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
98 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
99 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
100
101 virtual AddrChipFamily HwlConvertChipFamily(
102 UINT_32 uChipFamily, UINT_32 uChipRevision);
103
104 virtual BOOL_32 HwlInitGlobalParams(
105 const ADDR_CREATE_INPUT* pCreateIn);
106
107 virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
108 INT_32 index, INT_32 macroModeIndex, ADDR_TILEINFO* pInfo,
109 AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
110
111 virtual VOID HwlComputeTileDataWidthAndHeightLinear(
112 UINT_32* pMacroWidth, UINT_32* pMacroHeight,
113 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
114
115 virtual INT_32 HwlComputeMacroModeIndex(
116 INT_32 tileIndex, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
117 ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL
118 ) const;
119
120 // Sub-hwl interface - defined in EgBasedAddrLib
121 virtual VOID HwlSetupTileInfo(
122 AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
123 UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
124 ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
125 AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
126
127 virtual INT_32 HwlPostCheckTileIndex(
128 const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
129 INT curIndex = TileIndexInvalid) const;
130
131 virtual VOID HwlFmaskPreThunkSurfInfo(
132 const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
133 const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
134 ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
135 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
136
137 virtual VOID HwlFmaskPostThunkSurfInfo(
138 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
139 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
140
141 virtual AddrTileMode HwlDegradeThickTileMode(
142 AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
143
144 virtual BOOL_32 HwlOverrideTileMode(
145 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
146 AddrTileMode* pTileMode,
147 AddrTileType* pTileType) const;
148
149 virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
150 const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
151 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
152
153 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
154 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
155 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
156
157 virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
158
159 virtual VOID HwlPadDimensions(
160 AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
161 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
162 UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
163 UINT_32* pSlices, UINT_32 sliceAlign) const;
164
165 private:
166 VOID ReadGbTileMode(
167 UINT_32 regValue, ADDR_TILECONFIG* pCfg) const;
168
169 VOID ReadGbMacroTileCfg(
170 UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
171
172 BOOL_32 InitTileSettingTable(
173 const UINT_32 *pSetting, UINT_32 noOfEntries);
174
175 BOOL_32 InitMacroTileCfgTable(
176 const UINT_32 *pSetting, UINT_32 noOfEntries);
177
178 UINT_64 HwlComputeMetadataNibbleAddress(
179 UINT_64 uncompressedDataByteAddress,
180 UINT_64 dataBaseByteAddress,
181 UINT_64 metadataBaseByteAddress,
182 UINT_32 metadataBitSize,
183 UINT_32 elementBitSize,
184 UINT_32 blockByteSize,
185 UINT_32 pipeInterleaveBytes,
186 UINT_32 numOfPipes,
187 UINT_32 numOfBanks,
188 UINT_32 numOfSamplesPerSplit) const;
189
190 static const UINT_32 MacroTileTableSize = 16;
191 ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
192 UINT_32 m_noOfMacroEntries;
193 BOOL_32 m_allowNonDispThickModes;
194
195 CIChipSettings m_settings;
196 };
197
198 #endif
199
200