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amd/addrlib: update Mesa's copy of addrlib
[mesa.git] / src / amd / addrlib / src / gfx9 / gfx9addrlib.h
1 /*
2 * Copyright © 2007-2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ************************************************************************************************************************
29 * @file gfx9addrlib.h
30 * @brief Contgfx9ns the Gfx9Lib class definition.
31 ************************************************************************************************************************
32 */
33
34 #ifndef __GFX9_ADDR_LIB_H__
35 #define __GFX9_ADDR_LIB_H__
36
37 #include "addrlib2.h"
38 #include "coord.h"
39
40 namespace Addr
41 {
42 namespace V2
43 {
44
45 /**
46 ************************************************************************************************************************
47 * @brief GFX9 specific settings structure.
48 ************************************************************************************************************************
49 */
50 struct Gfx9ChipSettings
51 {
52 struct
53 {
54 // Asic/Generation name
55 UINT_32 isArcticIsland : 1;
56 UINT_32 isVega10 : 1;
57 UINT_32 isRaven : 1;
58 UINT_32 isVega12 : 1;
59 UINT_32 isVega20 : 1;
60 UINT_32 reserved0 : 27;
61
62 // Display engine IP version name
63 UINT_32 isDce12 : 1;
64 UINT_32 isDcn1 : 1;
65
66 // Misc configuration bits
67 UINT_32 metaBaseAlignFix : 1;
68 UINT_32 depthPipeXorDisable : 1;
69 UINT_32 htileAlignFix : 1;
70 UINT_32 applyAliasFix : 1;
71 UINT_32 htileCacheRbConflict: 1;
72 UINT_32 reserved2 : 27;
73 };
74 };
75
76 /**
77 ************************************************************************************************************************
78 * @brief GFX9 data surface type.
79 ************************************************************************************************************************
80 */
81 enum Gfx9DataType
82 {
83 Gfx9DataColor,
84 Gfx9DataDepthStencil,
85 Gfx9DataFmask
86 };
87
88 const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR);
89
90 const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
91 (1u << ADDR_SW_256B_D) |
92 (1u << ADDR_SW_256B_R);
93
94 const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) |
95 (1u << ADDR_SW_4KB_S) |
96 (1u << ADDR_SW_4KB_D) |
97 (1u << ADDR_SW_4KB_R) |
98 (1u << ADDR_SW_4KB_Z_X) |
99 (1u << ADDR_SW_4KB_S_X) |
100 (1u << ADDR_SW_4KB_D_X) |
101 (1u << ADDR_SW_4KB_R_X);
102
103 const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) |
104 (1u << ADDR_SW_64KB_S) |
105 (1u << ADDR_SW_64KB_D) |
106 (1u << ADDR_SW_64KB_R) |
107 (1u << ADDR_SW_64KB_Z_T) |
108 (1u << ADDR_SW_64KB_S_T) |
109 (1u << ADDR_SW_64KB_D_T) |
110 (1u << ADDR_SW_64KB_R_T) |
111 (1u << ADDR_SW_64KB_Z_X) |
112 (1u << ADDR_SW_64KB_S_X) |
113 (1u << ADDR_SW_64KB_D_X) |
114 (1u << ADDR_SW_64KB_R_X);
115
116 const UINT_32 Gfx9BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z) |
117 (1u << ADDR_SW_VAR_S) |
118 (1u << ADDR_SW_VAR_D) |
119 (1u << ADDR_SW_VAR_R) |
120 (1u << ADDR_SW_VAR_Z_X) |
121 (1u << ADDR_SW_VAR_S_X) |
122 (1u << ADDR_SW_VAR_D_X) |
123 (1u << ADDR_SW_VAR_R_X);
124
125 const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) |
126 (1u << ADDR_SW_64KB_Z) |
127 (1u << ADDR_SW_VAR_Z) |
128 (1u << ADDR_SW_64KB_Z_T) |
129 (1u << ADDR_SW_4KB_Z_X) |
130 (1u << ADDR_SW_64KB_Z_X) |
131 (1u << ADDR_SW_VAR_Z_X);
132
133 const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) |
134 (1u << ADDR_SW_4KB_S) |
135 (1u << ADDR_SW_64KB_S) |
136 (1u << ADDR_SW_VAR_S) |
137 (1u << ADDR_SW_64KB_S_T) |
138 (1u << ADDR_SW_4KB_S_X) |
139 (1u << ADDR_SW_64KB_S_X) |
140 (1u << ADDR_SW_VAR_S_X);
141
142 const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
143 (1u << ADDR_SW_4KB_D) |
144 (1u << ADDR_SW_64KB_D) |
145 (1u << ADDR_SW_VAR_D) |
146 (1u << ADDR_SW_64KB_D_T) |
147 (1u << ADDR_SW_4KB_D_X) |
148 (1u << ADDR_SW_64KB_D_X) |
149 (1u << ADDR_SW_VAR_D_X);
150
151 const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) |
152 (1u << ADDR_SW_4KB_R) |
153 (1u << ADDR_SW_64KB_R) |
154 (1u << ADDR_SW_VAR_R) |
155 (1u << ADDR_SW_64KB_R_T) |
156 (1u << ADDR_SW_4KB_R_X) |
157 (1u << ADDR_SW_64KB_R_X) |
158 (1u << ADDR_SW_VAR_R_X);
159
160 const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) |
161 (1u << ADDR_SW_4KB_S_X) |
162 (1u << ADDR_SW_4KB_D_X) |
163 (1u << ADDR_SW_4KB_R_X) |
164 (1u << ADDR_SW_64KB_Z_X) |
165 (1u << ADDR_SW_64KB_S_X) |
166 (1u << ADDR_SW_64KB_D_X) |
167 (1u << ADDR_SW_64KB_R_X) |
168 (1u << ADDR_SW_VAR_Z_X) |
169 (1u << ADDR_SW_VAR_S_X) |
170 (1u << ADDR_SW_VAR_D_X) |
171 (1u << ADDR_SW_VAR_R_X);
172
173 const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) |
174 (1u << ADDR_SW_64KB_S_T) |
175 (1u << ADDR_SW_64KB_D_T) |
176 (1u << ADDR_SW_64KB_R_T);
177
178 const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask |
179 Gfx9TSwModeMask;
180
181 const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask |
182 Gfx9ZSwModeMask |
183 Gfx9StandardSwModeMask |
184 Gfx9DisplaySwModeMask |
185 Gfx9RotateSwModeMask;
186
187 const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask;
188
189 const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask;
190
191 const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask;
192
193 const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask;
194
195 const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask;
196
197 const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask;
198
199 const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask;
200
201 const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) |
202 (1u << ADDR_SW_4KB_D) |
203 (1u << ADDR_SW_4KB_R) |
204 (1u << ADDR_SW_64KB_D) |
205 (1u << ADDR_SW_64KB_R) |
206 (1u << ADDR_SW_VAR_D) |
207 (1u << ADDR_SW_VAR_R) |
208 (1u << ADDR_SW_4KB_D_X) |
209 (1u << ADDR_SW_4KB_R_X) |
210 (1u << ADDR_SW_64KB_D_X) |
211 (1u << ADDR_SW_64KB_R_X) |
212 (1u << ADDR_SW_VAR_D_X) |
213 (1u << ADDR_SW_VAR_R_X);
214
215 const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) |
216 (1u << ADDR_SW_256B_R) |
217 Dce12NonBpp32SwModeMask;
218
219 const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
220 (1u << ADDR_SW_4KB_S) |
221 (1u << ADDR_SW_64KB_S) |
222 (1u << ADDR_SW_VAR_S) |
223 (1u << ADDR_SW_64KB_S_T) |
224 (1u << ADDR_SW_4KB_S_X) |
225 (1u << ADDR_SW_64KB_S_X) |
226 (1u << ADDR_SW_VAR_S_X);
227
228 const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) |
229 (1u << ADDR_SW_64KB_D) |
230 (1u << ADDR_SW_VAR_D) |
231 (1u << ADDR_SW_64KB_D_T) |
232 (1u << ADDR_SW_4KB_D_X) |
233 (1u << ADDR_SW_64KB_D_X) |
234 (1u << ADDR_SW_VAR_D_X) |
235 Dcn1NonBpp64SwModeMask;
236
237 /**
238 ************************************************************************************************************************
239 * @brief GFX9 meta equation parameters
240 ************************************************************************************************************************
241 */
242 struct MetaEqParams
243 {
244 UINT_32 maxMip;
245 UINT_32 elementBytesLog2;
246 UINT_32 numSamplesLog2;
247 ADDR2_META_FLAGS metaFlag;
248 Gfx9DataType dataSurfaceType;
249 AddrSwizzleMode swizzleMode;
250 AddrResourceType resourceType;
251 UINT_32 metaBlkWidthLog2;
252 UINT_32 metaBlkHeightLog2;
253 UINT_32 metaBlkDepthLog2;
254 UINT_32 compBlkWidthLog2;
255 UINT_32 compBlkHeightLog2;
256 UINT_32 compBlkDepthLog2;
257 };
258
259 /**
260 ************************************************************************************************************************
261 * @brief This class is the GFX9 specific address library
262 * function set.
263 ************************************************************************************************************************
264 */
265 class Gfx9Lib : public Lib
266 {
267 public:
268 /// Creates Gfx9Lib object
269 static Addr::Lib* CreateObj(const Client* pClient)
270 {
271 VOID* pMem = Object::ClientAlloc(sizeof(Gfx9Lib), pClient);
272 return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL;
273 }
274
275 virtual BOOL_32 IsValidDisplaySwizzleMode(
276 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
277
278 protected:
279 Gfx9Lib(const Client* pClient);
280 virtual ~Gfx9Lib();
281
282 virtual BOOL_32 HwlIsStandardSwizzle(
283 AddrResourceType resourceType,
284 AddrSwizzleMode swizzleMode) const
285 {
286 return m_swizzleModeTable[swizzleMode].isStd ||
287 (IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp);
288 }
289
290 virtual BOOL_32 HwlIsDisplaySwizzle(
291 AddrResourceType resourceType,
292 AddrSwizzleMode swizzleMode) const
293 {
294 return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp;
295 }
296
297 virtual BOOL_32 HwlIsThin(
298 AddrResourceType resourceType,
299 AddrSwizzleMode swizzleMode) const
300 {
301 return ((IsTex2d(resourceType) == TRUE) ||
302 ((IsTex3d(resourceType) == TRUE) &&
303 (m_swizzleModeTable[swizzleMode].isZ == FALSE) &&
304 (m_swizzleModeTable[swizzleMode].isStd == FALSE)));
305 }
306
307 virtual BOOL_32 HwlIsThick(
308 AddrResourceType resourceType,
309 AddrSwizzleMode swizzleMode) const
310 {
311 return (IsTex3d(resourceType) &&
312 (m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd));
313 }
314
315 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
316 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
317 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
318
319 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
320 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
321 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
322
323 virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
324 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
325 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
326
327 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
328 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
329 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
330
331 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
332 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
333 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
334
335 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
336 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
337 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
338
339 virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
340 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
341 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
342
343 virtual UINT_32 HwlGetEquationIndex(
344 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
345 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
346
347 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation(
348 AddrResourceType rsrcType,
349 AddrSwizzleMode swMode,
350 UINT_32 elementBytesLog2,
351 ADDR_EQUATION* pEquation) const;
352
353 virtual ADDR_E_RETURNCODE HwlComputeThinEquation(
354 AddrResourceType rsrcType,
355 AddrSwizzleMode swMode,
356 UINT_32 elementBytesLog2,
357 ADDR_EQUATION* pEquation) const;
358
359 virtual ADDR_E_RETURNCODE HwlComputeThickEquation(
360 AddrResourceType rsrcType,
361 AddrSwizzleMode swMode,
362 UINT_32 elementBytesLog2,
363 ADDR_EQUATION* pEquation) const;
364
365 // Get equation table pointer and number of equations
366 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
367 {
368 *ppEquationTable = m_equationTable;
369
370 return m_numEquations;
371 }
372
373 virtual BOOL_32 IsEquationSupported(
374 AddrResourceType rsrcType,
375 AddrSwizzleMode swMode,
376 UINT_32 elementBytesLog2) const;
377
378 UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const
379 {
380 UINT_32 baseAlign;
381
382 if (IsXor(swizzleMode))
383 {
384 baseAlign = GetBlockSize(swizzleMode);
385 }
386 else
387 {
388 baseAlign = 256;
389 }
390
391 return baseAlign;
392 }
393
394 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
395 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
396 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const;
397
398 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
399 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
400 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const;
401
402 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
403 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
404 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const;
405
406 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
407 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
408 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
409
410 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
411 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
412
413 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
414 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
415 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
416
417 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
418 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
419 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
420
421 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
422 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
423 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
424
425 // Initialize equation table
426 VOID InitEquationTable();
427
428 ADDR_E_RETURNCODE ComputeStereoInfo(
429 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
430 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
431 UINT_32* pHeightAlign) const;
432
433 UINT_32 GetMipChainInfo(
434 AddrResourceType resourceType,
435 AddrSwizzleMode swizzleMode,
436 UINT_32 bpp,
437 UINT_32 mip0Width,
438 UINT_32 mip0Height,
439 UINT_32 mip0Depth,
440 UINT_32 blockWidth,
441 UINT_32 blockHeight,
442 UINT_32 blockDepth,
443 UINT_32 numMipLevel,
444 ADDR2_MIP_INFO* pMipInfo) const;
445
446 VOID GetMetaMiptailInfo(
447 ADDR2_META_MIP_INFO* pInfo,
448 Dim3d mipCoord,
449 UINT_32 numMipInTail,
450 Dim3d* pMetaBlkDim) const;
451
452 Dim3d GetMipStartPos(
453 AddrResourceType resourceType,
454 AddrSwizzleMode swizzleMode,
455 UINT_32 width,
456 UINT_32 height,
457 UINT_32 depth,
458 UINT_32 blockWidth,
459 UINT_32 blockHeight,
460 UINT_32 blockDepth,
461 UINT_32 mipId,
462 UINT_32 log2ElementBytes,
463 UINT_32* pMipTailBytesOffset) const;
464
465 AddrMajorMode GetMajorMode(
466 AddrResourceType resourceType,
467 AddrSwizzleMode swizzleMode,
468 UINT_32 mip0WidthInBlk,
469 UINT_32 mip0HeightInBlk,
470 UINT_32 mip0DepthInBlk) const
471 {
472 BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk);
473 BOOL_32 xMajor = (yMajor == FALSE);
474
475 if (IsThick(resourceType, swizzleMode))
476 {
477 yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk);
478 xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk);
479 }
480
481 AddrMajorMode majorMode;
482 if (xMajor)
483 {
484 majorMode = ADDR_MAJOR_X;
485 }
486 else if (yMajor)
487 {
488 majorMode = ADDR_MAJOR_Y;
489 }
490 else
491 {
492 majorMode = ADDR_MAJOR_Z;
493 }
494
495 return majorMode;
496 }
497
498 Dim3d GetDccCompressBlk(
499 AddrResourceType resourceType,
500 AddrSwizzleMode swizzleMode,
501 UINT_32 bpp) const
502 {
503 UINT_32 index = Log2(bpp >> 3);
504 Dim3d compressBlkDim;
505
506 if (IsThin(resourceType, swizzleMode))
507 {
508 compressBlkDim.w = Block256_2d[index].w;
509 compressBlkDim.h = Block256_2d[index].h;
510 compressBlkDim.d = 1;
511 }
512 else if (IsStandardSwizzle(resourceType, swizzleMode))
513 {
514 compressBlkDim = Block256_3dS[index];
515 }
516 else
517 {
518 compressBlkDim = Block256_3dZ[index];
519 }
520
521 return compressBlkDim;
522 }
523
524 static const UINT_32 MaxSeLog2 = 3;
525 static const UINT_32 MaxRbPerSeLog2 = 2;
526
527 static const Dim3d Block256_3dS[MaxNumOfBpp];
528 static const Dim3d Block256_3dZ[MaxNumOfBpp];
529
530 static const UINT_32 MipTailOffset256B[];
531
532 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
533
534 // Max number of swizzle mode supported for equation
535 static const UINT_32 MaxSwMode = 32;
536 // Max number of resource type (2D/3D) supported for equation
537 static const UINT_32 MaxRsrcType = 2;
538 // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)
539 static const UINT_32 MaxElementBytesLog2 = 5;
540 // Almost all swizzle mode + resource type support equation
541 static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwMode * MaxRsrcType;
542 // Equation table
543 ADDR_EQUATION m_equationTable[EquationTableSize];
544
545 // Number of equation entries in the table
546 UINT_32 m_numEquations;
547 // Equation lookup table according to bpp and tile index
548 UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwMode][MaxElementBytesLog2];
549
550 static const UINT_32 MaxCachedMetaEq = 2;
551
552 private:
553 virtual UINT_32 HwlComputeMaxBaseAlignments() const;
554
555 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
556
557 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
558
559 VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const;
560
561 VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType,
562 AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
563 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2) const;
564
565 VOID GetPipeEquation(CoordEq* pPipeEq, CoordEq* pDataEq,
566 UINT_32 pipeInterleaveLog2, UINT_32 numPipesLog2,
567 UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType,
568 AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const;
569
570 VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip,
571 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2,
572 ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType,
573 AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
574 UINT_32 metaBlkWidthLog2, UINT_32 metaBlkHeightLog2,
575 UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2,
576 UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const;
577
578 const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams);
579
580 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
581
582 VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim,
583 BOOL_32 dataThick, ADDR2_META_MIP_INFO* pInfo,
584 UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
585 UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
586
587 ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
588 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
589 UINT_32* pMipmap0PaddedWidth,
590 UINT_32* pSlice0PaddedHeight,
591 ADDR2_MIP_INFO* pMipInfo = NULL) const;
592
593 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet)
594 {
595 ADDR2_BLOCK_SET allowedBlockSet = {};
596
597 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE;
598 allowedBlockSet.macro4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE;
599 allowedBlockSet.macro64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE;
600 allowedBlockSet.var = (allowedSwModeSet.value & Gfx9BlkVarSwModeMask) ? TRUE : FALSE;
601 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE;
602
603 return allowedBlockSet;
604 }
605
606 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
607 {
608 ADDR2_SWTYPE_SET allowedSwSet = {};
609
610 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE;
611 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE;
612 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE;
613 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE;
614
615 return allowedSwSet;
616 }
617
618 Gfx9ChipSettings m_settings;
619
620 CoordEq m_cachedMetaEq[MaxCachedMetaEq];
621 MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq];
622 UINT_32 m_metaEqOverrideIndex;
623 };
624
625 } // V2
626 } // Addr
627
628 #endif
629