src/amd/common/ac_binary.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "ac_binary.h"
  25
  26 #include "util/u_math.h"
  27 #include "util/u_memory.h"
  28
  29 #include <gelf.h>
  30 #include <libelf.h>
  31 #include <stdio.h>
  32
  33 #include <sid.h>
  34
  35 #define SPILLED_SGPRS                                     0x4
  36 #define SPILLED_VGPRS                                     0x8
  37
  38 /* Parse configuration data in .AMDGPU.config section format. */
  39 void ac_parse_shader_binary_config(const char *data, size_t nbytes,
  40                                    unsigned wave_size,
  41                                    bool really_needs_scratch,
  42                                    struct ac_shader_config *conf)
  43 {
  44         uint32_t scratch_size = 0;
  45
  46         for (size_t i = 0; i < nbytes; i += 8) {
  47                 unsigned reg = util_le32_to_cpu(*(uint32_t*)(data + i));
  48                 unsigned value = util_le32_to_cpu(*(uint32_t*)(data + i + 4));
  49                 switch (reg) {
  50                 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
  51                 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
  52                 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
  53                 case R_00B848_COMPUTE_PGM_RSRC1:
  54                 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
  55                         if (wave_size == 32)
  56                                 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
  57                         else
  58                                 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
  59
  60                         conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
  61                         /* TODO: LLVM doesn't set FLOAT_MODE for non-compute shaders */
  62                         conf->float_mode =  G_00B028_FLOAT_MODE(value);
  63                         conf->rsrc1 = value;
  64                         break;
  65                 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
  66                         conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
  67                         /* TODO: LLVM doesn't set SHARED_VGPR_CNT for all shader types */
  68                         conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
  69                         conf->rsrc2 = value;
  70                         break;
  71                 case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
  72                         conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
  73                         conf->rsrc2 = value;
  74                         break;
  75                 case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
  76                         conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
  77                         conf->rsrc2 = value;
  78                         break;
  79                 case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
  80                         conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
  81                         conf->rsrc2 = value;
  82                         break;
  83                 case R_00B84C_COMPUTE_PGM_RSRC2:
  84                         conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
  85                         conf->rsrc2 = value;
  86                         break;
  87                 case R_00B8A0_COMPUTE_PGM_RSRC3:
  88                         conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
  89                         conf->rsrc3 = value;
  90                         break;
  91                 case R_0286CC_SPI_PS_INPUT_ENA:
  92                         conf->spi_ps_input_ena = value;
  93                         break;
  94                 case R_0286D0_SPI_PS_INPUT_ADDR:
  95                         conf->spi_ps_input_addr = value;
  96                         break;
  97                 case R_0286E8_SPI_TMPRING_SIZE:
  98                 case R_00B860_COMPUTE_TMPRING_SIZE:
  99                         /* WAVESIZE is in units of 256 dwords. */
 100                         scratch_size = value;
 101                         break;
 102                 case SPILLED_SGPRS:
 103                         conf->spilled_sgprs = value;
 104                         break;
 105                 case SPILLED_VGPRS:
 106                         conf->spilled_vgprs = value;
 107                         break;
 108                 default:
 109                         {
 110                                 static bool printed;
 111
 112                                 if (!printed) {
 113                                         fprintf(stderr, "Warning: LLVM emitted unknown "
 114                                                 "config register: 0x%x\n", reg);
 115                                         printed = true;
 116                                 }
 117                         }
 118                         break;
 119                 }
 120         }
 121
 122         if (!conf->spi_ps_input_addr)
 123                 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
 124
 125         if (really_needs_scratch) {
 126                 /* sgprs spills aren't spilling */
 127                 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(scratch_size) * 256 * 4;
 128         }
 129
 130         /* Enable 64-bit and 16-bit denormals, because there is no performance
 131          * cost.
 132          *
 133          * Don't enable denormals for 32-bit floats, because:
 134          * - denormals disable output modifiers
 135          * - denormals break v_mad_f32
 136          * - GFX6 & GFX7 would be very slow
 137          */
 138         conf->float_mode &= ~V_00B028_FP_ALL_DENORMS;
 139         conf->float_mode |= V_00B028_FP_64_DENORMS;
 140 }