radeonsi: remove unused field in the PCI ID table
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "sid.h"
28 #include "gfx9d.h"
29
30 #include "util/u_math.h"
31
32 #include <stdio.h>
33
34 #include <xf86drm.h>
35 #include <amdgpu_drm.h>
36
37 #include <amdgpu.h>
38
39 #define CIK_TILE_MODE_COLOR_2D 14
40
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
56
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
58 {
59 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
60
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
63 return 2;
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
68 return 4;
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
76 return 8;
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
79 return 16;
80 default:
81 fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
83 return 2;
84 }
85 }
86
87 static bool has_syncobj(int fd)
88 {
89 uint64_t value;
90 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
91 return false;
92 return value ? true : false;
93 }
94
95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
96 struct radeon_info *info,
97 struct amdgpu_gpu_info *amdinfo)
98 {
99 struct amdgpu_buffer_size_alignments alignment_info = {};
100 struct amdgpu_heap_info vram, vram_vis, gtt;
101 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {};
102 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
103 int r, i, j;
104 drmDevicePtr devinfo;
105
106 /* Get PCI info. */
107 r = drmGetDevice2(fd, 0, &devinfo);
108 if (r) {
109 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
110 return false;
111 }
112 info->pci_domain = devinfo->businfo.pci->domain;
113 info->pci_bus = devinfo->businfo.pci->bus;
114 info->pci_dev = devinfo->businfo.pci->dev;
115 info->pci_func = devinfo->businfo.pci->func;
116 drmFreeDevice(&devinfo);
117
118 /* Query hardware and driver information. */
119 r = amdgpu_query_gpu_info(dev, amdinfo);
120 if (r) {
121 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
122 return false;
123 }
124
125 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
126 if (r) {
127 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
128 return false;
129 }
130
131 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
132 if (r) {
133 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
134 return false;
135 }
136
137 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
138 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
139 &vram_vis);
140 if (r) {
141 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
142 return false;
143 }
144
145 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
146 if (r) {
147 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
148 return false;
149 }
150
151 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
152 if (r) {
153 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
154 return false;
155 }
156
157 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
158 if (r) {
159 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
160 return false;
161 }
162
163 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
164 if (r) {
165 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
166 return false;
167 }
168
169 if (info->drm_major == 3 && info->drm_minor >= 17) {
170 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
171 if (r) {
172 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
173 return false;
174 }
175 }
176
177 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
178 &info->me_fw_version,
179 &info->me_fw_feature);
180 if (r) {
181 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
182 return false;
183 }
184
185 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
186 &info->pfp_fw_version,
187 &info->pfp_fw_feature);
188 if (r) {
189 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
190 return false;
191 }
192
193 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
194 &info->ce_fw_version,
195 &info->ce_fw_feature);
196 if (r) {
197 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
198 return false;
199 }
200
201 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
202 &uvd_version, &uvd_feature);
203 if (r) {
204 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
205 return false;
206 }
207
208 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
209 if (r) {
210 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
211 return false;
212 }
213
214 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
215 &vce_version, &vce_feature);
216 if (r) {
217 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
218 return false;
219 }
220
221 /* Set chip identification. */
222 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
223 info->vce_harvest_config = amdinfo->vce_harvest_config;
224
225 switch (info->pci_id) {
226 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
227 #include "pci_ids/radeonsi_pci_ids.h"
228 #undef CHIPSET
229
230 default:
231 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
232 return false;
233 }
234
235 if (info->family >= CHIP_VEGA10)
236 info->chip_class = GFX9;
237 else if (info->family >= CHIP_TONGA)
238 info->chip_class = VI;
239 else if (info->family >= CHIP_BONAIRE)
240 info->chip_class = CIK;
241 else if (info->family >= CHIP_TAHITI)
242 info->chip_class = SI;
243 else {
244 fprintf(stderr, "amdgpu: Unknown family.\n");
245 return false;
246 }
247
248 /* Set which chips have dedicated VRAM. */
249 info->has_dedicated_vram =
250 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
251
252 /* Set hardware information. */
253 info->gart_size = gtt.heap_size;
254 info->vram_size = vram.heap_size;
255 info->vram_vis_size = vram_vis.heap_size;
256 /* The kernel can split large buffers in VRAM but not in GTT, so large
257 * allocations can fail or cause buffer movement failures in the kernel.
258 */
259 info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
260 /* convert the shader clock from KHz to MHz */
261 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
262 info->max_se = amdinfo->num_shader_engines;
263 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
264 info->has_hw_decode =
265 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
266 info->uvd_fw_version =
267 uvd.available_rings ? uvd_version : 0;
268 info->vce_fw_version =
269 vce.available_rings ? vce_version : 0;
270 info->has_userptr = true;
271 info->has_syncobj = has_syncobj(fd);
272 info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
273 info->has_ctx_priority = info->drm_minor >= 22;
274 info->num_render_backends = amdinfo->rb_pipes;
275 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
276 if (!info->clock_crystal_freq) {
277 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
278 info->clock_crystal_freq = 1;
279 }
280 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
281 if (info->chip_class == GFX9) {
282 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
283 info->pipe_interleave_bytes =
284 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
285 } else {
286 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
287 info->pipe_interleave_bytes =
288 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
289 }
290 info->has_virtual_memory = true;
291
292 assert(util_is_power_of_two(dma.available_rings + 1));
293 assert(util_is_power_of_two(compute.available_rings + 1));
294
295 info->num_sdma_rings = util_bitcount(dma.available_rings);
296 info->num_compute_rings = util_bitcount(compute.available_rings);
297
298 /* Get the number of good compute units. */
299 info->num_good_compute_units = 0;
300 for (i = 0; i < info->max_se; i++)
301 for (j = 0; j < info->max_sh_per_se; j++)
302 info->num_good_compute_units +=
303 util_bitcount(amdinfo->cu_bitmap[i][j]);
304
305 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
306 sizeof(amdinfo->gb_tile_mode));
307 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
308
309 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
310 sizeof(amdinfo->gb_macro_tile_mode));
311
312 info->pte_fragment_size = alignment_info.size_local;
313 info->gart_page_size = alignment_info.size_remote;
314
315 if (info->chip_class == SI)
316 info->gfx_ib_pad_with_type2 = TRUE;
317
318 return true;
319 }
320
321 void ac_compute_driver_uuid(char *uuid, size_t size)
322 {
323 char amd_uuid[] = "AMD-MESA-DRV";
324
325 assert(size >= sizeof(amd_uuid));
326
327 memset(uuid, 0, size);
328 strncpy(uuid, amd_uuid, size);
329 }
330
331 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
332 {
333 uint32_t *uint_uuid = (uint32_t*)uuid;
334
335 assert(size >= sizeof(uint32_t)*4);
336
337 /**
338 * Use the device info directly instead of using a sha1. GL/VK UUIDs
339 * are 16 byte vs 20 byte for sha1, and the truncation that would be
340 * required would get rid of part of the little entropy we have.
341 * */
342 memset(uuid, 0, size);
343 uint_uuid[0] = info->pci_domain;
344 uint_uuid[1] = info->pci_bus;
345 uint_uuid[2] = info->pci_dev;
346 uint_uuid[3] = info->pci_func;
347 }