src/amd/common/ac_gpu_info.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_GPU_INFO_H
  27 #define AC_GPU_INFO_H
  28
  29 #include <stddef.h>
  30 #include <stdint.h>
  31 #include <stdbool.h>
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 /* Prior to C11 the following may trigger a typedef redeclaration warning */
  39 typedef struct amdgpu_device *amdgpu_device_handle;
  40 struct amdgpu_gpu_info;
  41
  42 struct radeon_info {
  43         /* PCI info: domain:bus:dev:func */
  44         uint32_t                    pci_domain;
  45         uint32_t                    pci_bus;
  46         uint32_t                    pci_dev;
  47         uint32_t                    pci_func;
  48
  49         /* Device info. */
  50         uint32_t                    pci_id;
  51         enum radeon_family          family;
  52         enum chip_class             chip_class;
  53         uint32_t                    num_compute_rings;
  54         uint32_t                    num_sdma_rings;
  55         uint32_t                    clock_crystal_freq;
  56         uint32_t                    tcc_cache_line_size;
  57
  58         /* Memory info. */
  59         uint32_t                    pte_fragment_size;
  60         uint32_t                    gart_page_size;
  61         uint64_t                    gart_size;
  62         uint64_t                    vram_size;
  63         uint64_t                    vram_vis_size;
  64         unsigned                    gds_size;
  65         unsigned                    gds_gfx_partition_size;
  66         uint64_t                    max_alloc_size;
  67         uint32_t                    min_alloc_size;
  68         uint32_t                    address32_hi;
  69         bool                        has_dedicated_vram;
  70         bool                        r600_has_virtual_memory;
  71
  72         /* CP info. */
  73         bool                        gfx_ib_pad_with_type2;
  74         unsigned                    ib_start_alignment;
  75         uint32_t                    me_fw_version;
  76         uint32_t                    me_fw_feature;
  77         uint32_t                    pfp_fw_version;
  78         uint32_t                    pfp_fw_feature;
  79         uint32_t                    ce_fw_version;
  80         uint32_t                    ce_fw_feature;
  81
  82         /* Multimedia info. */
  83         bool                        has_hw_decode;
  84         bool                        uvd_enc_supported;
  85         uint32_t                    uvd_fw_version;
  86         uint32_t                    vce_fw_version;
  87         uint32_t                    vce_harvest_config;
  88
  89         /* Kernel & winsys capabilities. */
  90         uint32_t                    drm_major; /* version */
  91         uint32_t                    drm_minor;
  92         uint32_t                    drm_patchlevel;
  93         bool                        has_userptr;
  94         bool                        has_syncobj;
  95         bool                        has_syncobj_wait_for_submit;
  96         bool                        has_fence_to_handle;
  97         bool                        has_ctx_priority;
  98         bool                        has_local_buffers;
  99         bool                        kernel_flushes_hdp_before_ib;
 100         bool                        htile_cmask_support_1d_tiling;
 101         bool                        si_TA_CS_BC_BASE_ADDR_allowed;
 102         bool                        has_bo_metadata;
 103         bool                        has_gpu_reset_status_query;
 104         bool                        has_gpu_reset_counter_query;
 105         bool                        has_eqaa_surface_allocator;
 106         bool                        has_format_bc1_through_bc7;
 107         bool                        kernel_flushes_tc_l2_after_ib;
 108         bool                        has_indirect_compute_dispatch;
 109         bool                        has_unaligned_shader_loads;
 110         bool                        has_sparse_vm_mappings;
 111         bool                        has_2d_tiling;
 112
 113         /* Shader cores. */
 114         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 115         uint32_t                    max_shader_clock;
 116         uint32_t                    num_good_compute_units;
 117         uint32_t                    max_se; /* shader engines */
 118         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 119
 120         /* Render backends (color + depth blocks). */
 121         uint32_t                    r300_num_gb_pipes;
 122         uint32_t                    r300_num_z_pipes;
 123         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 124         bool                        r600_gb_backend_map_valid;
 125         uint32_t                    r600_num_banks;
 126         uint32_t                    gb_addr_config;
 127         uint32_t                    num_render_backends;
 128         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 129         uint32_t                    pipe_interleave_bytes;
 130         uint32_t                    enabled_rb_mask; /* GCN harvest config */
 131         uint64_t                    max_alignment; /* from addrlib */
 132
 133         /* Tile modes. */
 134         uint32_t                    si_tile_mode_array[32];
 135         uint32_t                    cik_macrotile_mode_array[16];
 136 };
 137
 138 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 139                        struct radeon_info *info,
 140                        struct amdgpu_gpu_info *amdinfo);
 141
 142 void ac_compute_driver_uuid(char *uuid, size_t size);
 143
 144 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 145 void ac_print_gpu_info(struct radeon_info *info);
 146 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
 147 void ac_get_raster_config(struct radeon_info *info,
 148                           uint32_t *raster_config_p,
 149                           uint32_t *raster_config_1_p);
 150 void ac_get_harvested_configs(struct radeon_info *info,
 151                               unsigned raster_config,
 152                               unsigned *cik_raster_config_1_p,
 153                               unsigned *raster_config_se);
 154
 155 static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
 156 {
 157
 158         switch (family) {
 159         /* These always have 8 waves: */
 160         case CHIP_POLARIS10:
 161         case CHIP_POLARIS11:
 162         case CHIP_POLARIS12:
 163         case CHIP_VEGAM:
 164                 return 8;
 165         default:
 166                 return 10;
 167         }
 168 }
 169
 170 #ifdef __cplusplus
 171 }
 172 #endif
 173
 174 #endif /* AC_GPU_INFO_H */