ac/registers: use better names for disambiguated definitions
[mesa.git] / src / amd / common / ac_llvm_util.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
26 #include "ac_llvm_util.h"
27 #include "ac_llvm_build.h"
28 #include "util/bitscan.h"
29 #include <llvm-c/Core.h>
30 #include <llvm-c/Support.h>
31 #include <llvm-c/Transforms/IPO.h>
32 #include <llvm-c/Transforms/Scalar.h>
33 #include <llvm-c/Transforms/Utils.h>
34 #include "c11/threads.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_math.h"
37
38 #include <assert.h>
39 #include <stdio.h>
40 #include <string.h>
41
42 static void ac_init_llvm_target()
43 {
44 LLVMInitializeAMDGPUTargetInfo();
45 LLVMInitializeAMDGPUTarget();
46 LLVMInitializeAMDGPUTargetMC();
47 LLVMInitializeAMDGPUAsmPrinter();
48
49 /* For inline assembly. */
50 LLVMInitializeAMDGPUAsmParser();
51
52 /* Workaround for bug in llvm 4.0 that causes image intrinsics
53 * to disappear.
54 * https://reviews.llvm.org/D26348
55 *
56 * "mesa" is the prefix for error messages.
57 *
58 * -global-isel-abort=2 is a no-op unless global isel has been enabled.
59 * This option tells the backend to fall-back to SelectionDAG and print
60 * a diagnostic message if global isel fails.
61 */
62 const char *argv[] = { "mesa", "-simplifycfg-sink-common=false", "-global-isel-abort=2" };
63 LLVMParseCommandLineOptions(ARRAY_SIZE(argv), argv, NULL);
64 }
65
66 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
67
68 void ac_init_llvm_once(void)
69 {
70 call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
71 }
72
73 static LLVMTargetRef ac_get_llvm_target(const char *triple)
74 {
75 LLVMTargetRef target = NULL;
76 char *err_message = NULL;
77
78 if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
79 fprintf(stderr, "Cannot find target for triple %s ", triple);
80 if (err_message) {
81 fprintf(stderr, "%s\n", err_message);
82 }
83 LLVMDisposeMessage(err_message);
84 return NULL;
85 }
86 return target;
87 }
88
89 const char *ac_get_llvm_processor_name(enum radeon_family family)
90 {
91 switch (family) {
92 case CHIP_TAHITI:
93 return "tahiti";
94 case CHIP_PITCAIRN:
95 return "pitcairn";
96 case CHIP_VERDE:
97 return "verde";
98 case CHIP_OLAND:
99 return "oland";
100 case CHIP_HAINAN:
101 return "hainan";
102 case CHIP_BONAIRE:
103 return "bonaire";
104 case CHIP_KABINI:
105 return "kabini";
106 case CHIP_KAVERI:
107 return "kaveri";
108 case CHIP_HAWAII:
109 return "hawaii";
110 case CHIP_TONGA:
111 return "tonga";
112 case CHIP_ICELAND:
113 return "iceland";
114 case CHIP_CARRIZO:
115 return "carrizo";
116 case CHIP_FIJI:
117 return "fiji";
118 case CHIP_STONEY:
119 return "stoney";
120 case CHIP_POLARIS10:
121 return "polaris10";
122 case CHIP_POLARIS11:
123 case CHIP_POLARIS12:
124 case CHIP_VEGAM:
125 return "polaris11";
126 case CHIP_VEGA10:
127 return "gfx900";
128 case CHIP_RAVEN:
129 return "gfx902";
130 case CHIP_VEGA12:
131 return "gfx904";
132 case CHIP_VEGA20:
133 return "gfx906";
134 case CHIP_RAVEN2:
135 return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
136 default:
137 return "";
138 }
139 }
140
141 static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
142 enum ac_target_machine_options tm_options,
143 LLVMCodeGenOptLevel level,
144 const char **out_triple)
145 {
146 assert(family >= CHIP_TAHITI);
147 char features[256];
148 const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
149 LLVMTargetRef target = ac_get_llvm_target(triple);
150
151 snprintf(features, sizeof(features),
152 "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
153 HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
154 tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
155 tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
156 tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
157 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
158 tm_options & AC_TM_NO_LOAD_STORE_OPT ? ",-load-store-opt" : "");
159
160 LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
161 target,
162 triple,
163 ac_get_llvm_processor_name(family),
164 features,
165 level,
166 LLVMRelocDefault,
167 LLVMCodeModelDefault);
168
169 if (out_triple)
170 *out_triple = triple;
171 if (tm_options & AC_TM_ENABLE_GLOBAL_ISEL)
172 ac_enable_global_isel(tm);
173 return tm;
174 }
175
176 static LLVMPassManagerRef ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info,
177 bool check_ir)
178 {
179 LLVMPassManagerRef passmgr = LLVMCreatePassManager();
180 if (!passmgr)
181 return NULL;
182
183 if (target_library_info)
184 LLVMAddTargetLibraryInfo(target_library_info,
185 passmgr);
186
187 if (check_ir)
188 LLVMAddVerifierPass(passmgr);
189 LLVMAddAlwaysInlinerPass(passmgr);
190 /* Normally, the pass manager runs all passes on one function before
191 * moving onto another. Adding a barrier no-op pass forces the pass
192 * manager to run the inliner on all functions first, which makes sure
193 * that the following passes are only run on the remaining non-inline
194 * function, so it removes useless work done on dead inline functions.
195 */
196 ac_llvm_add_barrier_noop_pass(passmgr);
197 /* This pass should eliminate all the load and store instructions. */
198 LLVMAddPromoteMemoryToRegisterPass(passmgr);
199 LLVMAddScalarReplAggregatesPass(passmgr);
200 LLVMAddLICMPass(passmgr);
201 LLVMAddAggressiveDCEPass(passmgr);
202 LLVMAddCFGSimplificationPass(passmgr);
203 /* This is recommended by the instruction combining pass. */
204 LLVMAddEarlyCSEMemSSAPass(passmgr);
205 LLVMAddInstructionCombiningPass(passmgr);
206 return passmgr;
207 }
208
209 static const char *attr_to_str(enum ac_func_attr attr)
210 {
211 switch (attr) {
212 case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
213 case AC_FUNC_ATTR_INREG: return "inreg";
214 case AC_FUNC_ATTR_NOALIAS: return "noalias";
215 case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
216 case AC_FUNC_ATTR_READNONE: return "readnone";
217 case AC_FUNC_ATTR_READONLY: return "readonly";
218 case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
219 case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
220 case AC_FUNC_ATTR_CONVERGENT: return "convergent";
221 default:
222 fprintf(stderr, "Unhandled function attribute: %x\n", attr);
223 return 0;
224 }
225 }
226
227 void
228 ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
229 int attr_idx, enum ac_func_attr attr)
230 {
231 const char *attr_name = attr_to_str(attr);
232 unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
233 strlen(attr_name));
234 LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(ctx, kind_id, 0);
235
236 if (LLVMIsAFunction(function))
237 LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
238 else
239 LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
240 }
241
242 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
243 unsigned attrib_mask)
244 {
245 attrib_mask |= AC_FUNC_ATTR_NOUNWIND;
246 attrib_mask &= ~AC_FUNC_ATTR_LEGACY;
247
248 while (attrib_mask) {
249 enum ac_func_attr attr = 1u << u_bit_scan(&attrib_mask);
250 ac_add_function_attr(ctx, function, -1, attr);
251 }
252 }
253
254 void
255 ac_dump_module(LLVMModuleRef module)
256 {
257 char *str = LLVMPrintModuleToString(module);
258 fprintf(stderr, "%s", str);
259 LLVMDisposeMessage(str);
260 }
261
262 void
263 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
264 const char *name, unsigned value)
265 {
266 char str[16];
267
268 snprintf(str, sizeof(str), "0x%x", value);
269 LLVMAddTargetDependentFunctionAttr(F, name, str);
270 }
271
272 void ac_llvm_set_workgroup_size(LLVMValueRef F, unsigned size)
273 {
274 if (!size)
275 return;
276
277 char str[32];
278 snprintf(str, sizeof(str), "%u,%u", size, size);
279 LLVMAddTargetDependentFunctionAttr(F, "amdgpu-flat-work-group-size", str);
280 }
281
282 unsigned
283 ac_count_scratch_private_memory(LLVMValueRef function)
284 {
285 unsigned private_mem_vgprs = 0;
286
287 /* Process all LLVM instructions. */
288 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(function);
289 while (bb) {
290 LLVMValueRef next = LLVMGetFirstInstruction(bb);
291
292 while (next) {
293 LLVMValueRef inst = next;
294 next = LLVMGetNextInstruction(next);
295
296 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
297 continue;
298
299 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
300 /* No idea why LLVM aligns allocas to 4 elements. */
301 unsigned alignment = LLVMGetAlignment(inst);
302 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
303 private_mem_vgprs += dw_size;
304 }
305 bb = LLVMGetNextBasicBlock(bb);
306 }
307
308 return private_mem_vgprs;
309 }
310
311 bool
312 ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
313 enum radeon_family family,
314 enum ac_target_machine_options tm_options)
315 {
316 const char *triple;
317 memset(compiler, 0, sizeof(*compiler));
318
319 compiler->tm = ac_create_target_machine(family, tm_options,
320 LLVMCodeGenLevelDefault,
321 &triple);
322 if (!compiler->tm)
323 return false;
324
325 if (tm_options & AC_TM_CREATE_LOW_OPT) {
326 compiler->low_opt_tm =
327 ac_create_target_machine(family, tm_options,
328 LLVMCodeGenLevelLess, NULL);
329 if (!compiler->low_opt_tm)
330 goto fail;
331 }
332
333 compiler->target_library_info =
334 ac_create_target_library_info(triple);
335 if (!compiler->target_library_info)
336 goto fail;
337
338 compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
339 tm_options & AC_TM_CHECK_IR);
340 if (!compiler->passmgr)
341 goto fail;
342
343 return true;
344 fail:
345 ac_destroy_llvm_compiler(compiler);
346 return false;
347 }
348
349 void
350 ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
351 {
352 if (compiler->passmgr)
353 LLVMDisposePassManager(compiler->passmgr);
354 if (compiler->target_library_info)
355 ac_dispose_target_library_info(compiler->target_library_info);
356 if (compiler->low_opt_tm)
357 LLVMDisposeTargetMachine(compiler->low_opt_tm);
358 if (compiler->tm)
359 LLVMDisposeTargetMachine(compiler->tm);
360 }