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ac/nir: add ac_shader_abi::inputs
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 enum desc_type {
51 DESC_IMAGE,
52 DESC_FMASK,
53 DESC_SAMPLER,
54 DESC_BUFFER,
55 };
56
57 struct nir_to_llvm_context;
58
59 struct ac_nir_context {
60 struct ac_llvm_context ac;
61 struct ac_shader_abi *abi;
62
63 gl_shader_stage stage;
64
65 struct hash_table *defs;
66 struct hash_table *phis;
67 struct hash_table *vars;
68
69 LLVMBasicBlockRef continue_block;
70 LLVMBasicBlockRef break_block;
71
72 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
73
74 int num_locals;
75 LLVMValueRef *locals;
76
77 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
78 };
79
80 struct nir_to_llvm_context {
81 struct ac_llvm_context ac;
82 const struct ac_nir_compiler_options *options;
83 struct ac_shader_variant_info *shader_info;
84 struct ac_shader_abi abi;
85 struct ac_nir_context *nir;
86
87 unsigned max_workgroup_size;
88 LLVMContextRef context;
89 LLVMModuleRef module;
90 LLVMBuilderRef builder;
91 LLVMValueRef main_function;
92
93 struct hash_table *defs;
94 struct hash_table *phis;
95
96 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
97 LLVMValueRef ring_offsets;
98 LLVMValueRef push_constants;
99 LLVMValueRef num_work_groups;
100 LLVMValueRef workgroup_ids;
101 LLVMValueRef local_invocation_ids;
102 LLVMValueRef tg_size;
103
104 LLVMValueRef vertex_buffers;
105 LLVMValueRef rel_auto_id;
106 LLVMValueRef vs_prim_id;
107 LLVMValueRef ls_out_layout;
108 LLVMValueRef es2gs_offset;
109
110 LLVMValueRef tcs_offchip_layout;
111 LLVMValueRef tcs_out_offsets;
112 LLVMValueRef tcs_out_layout;
113 LLVMValueRef tcs_in_layout;
114 LLVMValueRef oc_lds;
115 LLVMValueRef tess_factor_offset;
116 LLVMValueRef tcs_patch_id;
117 LLVMValueRef tcs_rel_ids;
118 LLVMValueRef tes_rel_patch_id;
119 LLVMValueRef tes_patch_id;
120 LLVMValueRef tes_u;
121 LLVMValueRef tes_v;
122
123 LLVMValueRef gsvs_ring_stride;
124 LLVMValueRef gsvs_num_entries;
125 LLVMValueRef gs2vs_offset;
126 LLVMValueRef gs_wave_id;
127 LLVMValueRef gs_vtx_offset[6];
128 LLVMValueRef gs_prim_id, gs_invocation_id;
129
130 LLVMValueRef esgs_ring;
131 LLVMValueRef gsvs_ring;
132 LLVMValueRef hs_ring_tess_offchip;
133 LLVMValueRef hs_ring_tess_factor;
134
135 LLVMValueRef prim_mask;
136 LLVMValueRef sample_pos_offset;
137 LLVMValueRef persp_sample, persp_center, persp_centroid;
138 LLVMValueRef linear_sample, linear_center, linear_centroid;
139 LLVMValueRef front_face;
140 LLVMValueRef ancillary;
141 LLVMValueRef sample_coverage;
142 LLVMValueRef frag_pos[4];
143
144 LLVMTypeRef i1;
145 LLVMTypeRef i8;
146 LLVMTypeRef i16;
147 LLVMTypeRef i32;
148 LLVMTypeRef i64;
149 LLVMTypeRef v2i32;
150 LLVMTypeRef v3i32;
151 LLVMTypeRef v4i32;
152 LLVMTypeRef v8i32;
153 LLVMTypeRef f64;
154 LLVMTypeRef f32;
155 LLVMTypeRef f16;
156 LLVMTypeRef v2f32;
157 LLVMTypeRef v4f32;
158 LLVMTypeRef voidt;
159
160 LLVMValueRef i1true;
161 LLVMValueRef i1false;
162 LLVMValueRef i32zero;
163 LLVMValueRef i32one;
164 LLVMValueRef f32zero;
165 LLVMValueRef f32one;
166 LLVMValueRef v4f32empty;
167
168 unsigned uniform_md_kind;
169 LLVMValueRef empty_md;
170 gl_shader_stage stage;
171
172 LLVMValueRef lds;
173 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
174
175 uint64_t input_mask;
176 uint64_t output_mask;
177 uint8_t num_output_clips;
178 uint8_t num_output_culls;
179
180 bool has_ds_bpermute;
181
182 bool is_gs_copy_shader;
183 LLVMValueRef gs_next_vertex;
184 unsigned gs_max_out_vertices;
185
186 unsigned tes_primitive_mode;
187 uint64_t tess_outputs_written;
188 uint64_t tess_patch_outputs_written;
189 };
190
191 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
192 const nir_deref_var *deref,
193 enum desc_type desc_type);
194 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
195 {
196 return (index * 4) + chan;
197 }
198
199 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
200 {
201 /* handle patch indices separate */
202 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
203 return 0;
204 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
205 return 1;
206 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
207 return 2 + (slot - VARYING_SLOT_PATCH0);
208
209 if (slot == VARYING_SLOT_POS)
210 return 0;
211 if (slot == VARYING_SLOT_PSIZ)
212 return 1;
213 if (slot == VARYING_SLOT_CLIP_DIST0)
214 return 2;
215 /* 3 is reserved for clip dist as well */
216 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
217 return 4 + (slot - VARYING_SLOT_VAR0);
218 unreachable("illegal slot in get unique index\n");
219 }
220
221 static unsigned llvm_get_type_size(LLVMTypeRef type)
222 {
223 LLVMTypeKind kind = LLVMGetTypeKind(type);
224
225 switch (kind) {
226 case LLVMIntegerTypeKind:
227 return LLVMGetIntTypeWidth(type) / 8;
228 case LLVMFloatTypeKind:
229 return 4;
230 case LLVMPointerTypeKind:
231 return 8;
232 case LLVMVectorTypeKind:
233 return LLVMGetVectorSize(type) *
234 llvm_get_type_size(LLVMGetElementType(type));
235 default:
236 assert(0);
237 return 0;
238 }
239 }
240
241 static void set_llvm_calling_convention(LLVMValueRef func,
242 gl_shader_stage stage)
243 {
244 enum radeon_llvm_calling_convention calling_conv;
245
246 switch (stage) {
247 case MESA_SHADER_VERTEX:
248 case MESA_SHADER_TESS_CTRL:
249 case MESA_SHADER_TESS_EVAL:
250 calling_conv = RADEON_LLVM_AMDGPU_VS;
251 break;
252 case MESA_SHADER_GEOMETRY:
253 calling_conv = RADEON_LLVM_AMDGPU_GS;
254 break;
255 case MESA_SHADER_FRAGMENT:
256 calling_conv = RADEON_LLVM_AMDGPU_PS;
257 break;
258 case MESA_SHADER_COMPUTE:
259 calling_conv = RADEON_LLVM_AMDGPU_CS;
260 break;
261 default:
262 unreachable("Unhandle shader type");
263 }
264
265 LLVMSetFunctionCallConv(func, calling_conv);
266 }
267
268 #define MAX_ARGS 23
269 struct arg_info {
270 LLVMTypeRef types[MAX_ARGS];
271 LLVMValueRef *assign[MAX_ARGS];
272 unsigned array_params_mask;
273 uint8_t count;
274 uint8_t user_sgpr_count;
275 uint8_t sgpr_count;
276 uint8_t num_user_sgprs_used;
277 uint8_t num_sgprs_used;
278 uint8_t num_vgprs_used;
279 };
280
281 static inline void
282 add_argument(struct arg_info *info,
283 LLVMTypeRef type, LLVMValueRef *param_ptr)
284 {
285 assert(info->count < MAX_ARGS);
286 info->assign[info->count] = param_ptr;
287 info->types[info->count] = type;
288 info->count++;
289 }
290
291 static inline void
292 add_sgpr_argument(struct arg_info *info,
293 LLVMTypeRef type, LLVMValueRef *param_ptr)
294 {
295 add_argument(info, type, param_ptr);
296 info->num_sgprs_used += llvm_get_type_size(type) / 4;
297 info->sgpr_count++;
298 }
299
300 static inline void
301 add_user_sgpr_argument(struct arg_info *info,
302 LLVMTypeRef type,
303 LLVMValueRef *param_ptr)
304 {
305 add_sgpr_argument(info, type, param_ptr);
306 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
307 info->user_sgpr_count++;
308 }
309
310 static inline void
311 add_vgpr_argument(struct arg_info *info,
312 LLVMTypeRef type,
313 LLVMValueRef *param_ptr)
314 {
315 add_argument(info, type, param_ptr);
316 info->num_vgprs_used += llvm_get_type_size(type) / 4;
317 }
318
319 static inline void
320 add_user_sgpr_array_argument(struct arg_info *info,
321 LLVMTypeRef type,
322 LLVMValueRef *param_ptr)
323 {
324 info->array_params_mask |= (1 << info->count);
325 add_user_sgpr_argument(info, type, param_ptr);
326 }
327
328 static void assign_arguments(LLVMValueRef main_function,
329 struct arg_info *info)
330 {
331 unsigned i;
332 for (i = 0; i < info->count; i++) {
333 if (info->assign[i])
334 *info->assign[i] = LLVMGetParam(main_function, i);
335 }
336 }
337
338 static LLVMValueRef
339 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
340 LLVMBuilderRef builder, LLVMTypeRef *return_types,
341 unsigned num_return_elems,
342 struct arg_info *args,
343 unsigned max_workgroup_size,
344 bool unsafe_math)
345 {
346 LLVMTypeRef main_function_type, ret_type;
347 LLVMBasicBlockRef main_function_body;
348
349 if (num_return_elems)
350 ret_type = LLVMStructTypeInContext(ctx, return_types,
351 num_return_elems, true);
352 else
353 ret_type = LLVMVoidTypeInContext(ctx);
354
355 /* Setup the function */
356 main_function_type =
357 LLVMFunctionType(ret_type, args->types, args->count, 0);
358 LLVMValueRef main_function =
359 LLVMAddFunction(module, "main", main_function_type);
360 main_function_body =
361 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
362 LLVMPositionBuilderAtEnd(builder, main_function_body);
363
364 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
365 for (unsigned i = 0; i < args->sgpr_count; ++i) {
366 if (args->array_params_mask & (1 << i)) {
367 LLVMValueRef P = LLVMGetParam(main_function, i);
368 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
369 ac_add_attr_dereferenceable(P, UINT64_MAX);
370 }
371 else {
372 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
373 }
374 }
375
376 if (max_workgroup_size) {
377 ac_llvm_add_target_dep_function_attr(main_function,
378 "amdgpu-max-work-group-size",
379 max_workgroup_size);
380 }
381 if (unsafe_math) {
382 /* These were copied from some LLVM test. */
383 LLVMAddTargetDependentFunctionAttr(main_function,
384 "less-precise-fpmad",
385 "true");
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "no-infs-fp-math",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "no-nans-fp-math",
391 "true");
392 LLVMAddTargetDependentFunctionAttr(main_function,
393 "unsafe-fp-math",
394 "true");
395 }
396 return main_function;
397 }
398
399 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
400 {
401 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
402 CONST_ADDR_SPACE);
403 }
404
405 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
406 {
407 if (t == ctx->f16 || t == ctx->i16)
408 return ctx->i16;
409 else if (t == ctx->f32 || t == ctx->i32)
410 return ctx->i32;
411 else if (t == ctx->f64 || t == ctx->i64)
412 return ctx->i64;
413 else
414 unreachable("Unhandled integer size");
415 }
416
417 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
418 {
419 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
420 LLVMTypeRef elem_type = LLVMGetElementType(t);
421 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
422 LLVMGetVectorSize(t));
423 }
424 return to_integer_type_scalar(ctx, t);
425 }
426
427 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
428 {
429 LLVMTypeRef type = LLVMTypeOf(v);
430 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
431 }
432
433 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
434 {
435 if (t == ctx->i16 || t == ctx->f16)
436 return ctx->f16;
437 else if (t == ctx->i32 || t == ctx->f32)
438 return ctx->f32;
439 else if (t == ctx->i64 || t == ctx->f64)
440 return ctx->f64;
441 else
442 unreachable("Unhandled float size");
443 }
444
445 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
446 {
447 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
448 LLVMTypeRef elem_type = LLVMGetElementType(t);
449 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
450 LLVMGetVectorSize(t));
451 }
452 return to_float_type_scalar(ctx, t);
453 }
454
455 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
456 {
457 LLVMTypeRef type = LLVMTypeOf(v);
458 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
459 }
460
461 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
462 {
463 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
464 type = LLVMGetElementType(type);
465
466 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
467 return LLVMGetIntTypeWidth(type);
468
469 if (type == ctx->f16)
470 return 16;
471 if (type == ctx->f32)
472 return 32;
473 if (type == ctx->f64)
474 return 64;
475
476 unreachable("Unhandled type kind in get_elem_bits");
477 }
478
479 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
480 LLVMValueRef param, unsigned rshift,
481 unsigned bitwidth)
482 {
483 LLVMValueRef value = param;
484 if (rshift)
485 value = LLVMBuildLShr(ctx->builder, value,
486 LLVMConstInt(ctx->i32, rshift, false), "");
487
488 if (rshift + bitwidth < 32) {
489 unsigned mask = (1 << bitwidth) - 1;
490 value = LLVMBuildAnd(ctx->builder, value,
491 LLVMConstInt(ctx->i32, mask, false), "");
492 }
493 return value;
494 }
495
496 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
497 {
498 switch (ctx->stage) {
499 case MESA_SHADER_TESS_CTRL:
500 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
501 case MESA_SHADER_TESS_EVAL:
502 return ctx->tes_rel_patch_id;
503 break;
504 default:
505 unreachable("Illegal stage");
506 }
507 }
508
509 /* Tessellation shaders pass outputs to the next shader using LDS.
510 *
511 * LS outputs = TCS inputs
512 * TCS outputs = TES inputs
513 *
514 * The LDS layout is:
515 * - TCS inputs for patch 0
516 * - TCS inputs for patch 1
517 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
518 * - ...
519 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
520 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
521 * - TCS outputs for patch 1
522 * - Per-patch TCS outputs for patch 1
523 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
524 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
525 * - ...
526 *
527 * All three shaders VS(LS), TCS, TES share the same LDS space.
528 */
529 static LLVMValueRef
530 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
531 {
532 if (ctx->stage == MESA_SHADER_VERTEX)
533 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
534 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
535 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
536 else {
537 assert(0);
538 return NULL;
539 }
540 }
541
542 static LLVMValueRef
543 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
544 {
545 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
546 }
547
548 static LLVMValueRef
549 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
550 {
551 return LLVMBuildMul(ctx->builder,
552 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
553 LLVMConstInt(ctx->i32, 4, false), "");
554 }
555
556 static LLVMValueRef
557 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
558 {
559 return LLVMBuildMul(ctx->builder,
560 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
561 LLVMConstInt(ctx->i32, 4, false), "");
562 }
563
564 static LLVMValueRef
565 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
566 {
567 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
568 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
569
570 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
571 }
572
573 static LLVMValueRef
574 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
575 {
576 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
577 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
578 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
579
580 return LLVMBuildAdd(ctx->builder, patch0_offset,
581 LLVMBuildMul(ctx->builder, patch_stride,
582 rel_patch_id, ""),
583 "");
584 }
585
586 static LLVMValueRef
587 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
588 {
589 LLVMValueRef patch0_patch_data_offset =
590 get_tcs_out_patch0_patch_data_offset(ctx);
591 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
592 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
593
594 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
595 LLVMBuildMul(ctx->builder, patch_stride,
596 rel_patch_id, ""),
597 "");
598 }
599
600 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
601 {
602 ud_info->sgpr_idx = *sgpr_idx;
603 ud_info->num_sgprs = num_sgprs;
604 ud_info->indirect = false;
605 ud_info->indirect_offset = 0;
606 *sgpr_idx += num_sgprs;
607 }
608
609 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
610 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
611 {
612 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
613 }
614
615
616 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
617 uint32_t indirect_offset)
618 {
619 ud_info->sgpr_idx = sgpr_idx;
620 ud_info->num_sgprs = num_sgprs;
621 ud_info->indirect = true;
622 ud_info->indirect_offset = indirect_offset;
623 }
624
625 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
626 {
627 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
628 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
629 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
630 "tess_lds");
631 }
632
633 struct user_sgpr_info {
634 bool need_ring_offsets;
635 uint8_t sgpr_count;
636 bool indirect_all_descriptor_sets;
637 };
638
639 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
640 struct user_sgpr_info *user_sgpr_info)
641 {
642 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
643
644 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
645 if (ctx->stage == MESA_SHADER_GEOMETRY ||
646 ctx->stage == MESA_SHADER_VERTEX ||
647 ctx->stage == MESA_SHADER_TESS_CTRL ||
648 ctx->stage == MESA_SHADER_TESS_EVAL ||
649 ctx->is_gs_copy_shader)
650 user_sgpr_info->need_ring_offsets = true;
651
652 if (ctx->stage == MESA_SHADER_FRAGMENT &&
653 ctx->shader_info->info.ps.needs_sample_positions)
654 user_sgpr_info->need_ring_offsets = true;
655
656 /* 2 user sgprs will nearly always be allocated for scratch/rings */
657 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
658 user_sgpr_info->sgpr_count += 2;
659 }
660
661 switch (ctx->stage) {
662 case MESA_SHADER_COMPUTE:
663 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
664 break;
665 case MESA_SHADER_FRAGMENT:
666 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
667 break;
668 case MESA_SHADER_VERTEX:
669 if (!ctx->is_gs_copy_shader) {
670 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
671 if (ctx->shader_info->info.vs.needs_draw_id) {
672 user_sgpr_info->sgpr_count += 3;
673 } else {
674 user_sgpr_info->sgpr_count += 2;
675 }
676 }
677 if (ctx->options->key.vs.as_ls)
678 user_sgpr_info->sgpr_count++;
679 break;
680 case MESA_SHADER_TESS_CTRL:
681 user_sgpr_info->sgpr_count += 4;
682 break;
683 case MESA_SHADER_TESS_EVAL:
684 user_sgpr_info->sgpr_count += 1;
685 break;
686 case MESA_SHADER_GEOMETRY:
687 user_sgpr_info->sgpr_count += 2;
688 break;
689 default:
690 break;
691 }
692
693 if (ctx->shader_info->info.needs_push_constants)
694 user_sgpr_info->sgpr_count += 2;
695
696 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
697 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
698 user_sgpr_info->sgpr_count += 2;
699 user_sgpr_info->indirect_all_descriptor_sets = true;
700 } else {
701 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
702 }
703 }
704
705 static void create_function(struct nir_to_llvm_context *ctx)
706 {
707 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
708 uint8_t user_sgpr_idx;
709 struct user_sgpr_info user_sgpr_info;
710 struct arg_info args = {};
711 LLVMValueRef desc_sets;
712
713 allocate_user_sgprs(ctx, &user_sgpr_info);
714 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
715 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
716 }
717
718 /* 1 for each descriptor set */
719 if (!user_sgpr_info.indirect_all_descriptor_sets) {
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
722 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
723 }
724 }
725 } else
726 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
727
728 if (ctx->shader_info->info.needs_push_constants) {
729 /* 1 for push constants and dynamic descriptors */
730 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
731 }
732
733 switch (ctx->stage) {
734 case MESA_SHADER_COMPUTE:
735 if (ctx->shader_info->info.cs.grid_components_used)
736 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
737 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
738 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
739 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
740 break;
741 case MESA_SHADER_VERTEX:
742 if (!ctx->is_gs_copy_shader) {
743 if (ctx->shader_info->info.vs.has_vertex_buffers)
744 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
745 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
746 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
747 if (ctx->shader_info->info.vs.needs_draw_id)
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
749 }
750 if (ctx->options->key.vs.as_es)
751 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
752 else if (ctx->options->key.vs.as_ls)
753 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
754 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
755 if (!ctx->is_gs_copy_shader) {
756 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
757 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
758 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
759 }
760 break;
761 case MESA_SHADER_TESS_CTRL:
762 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
763 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
766 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
767 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
768 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
769 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
770 break;
771 case MESA_SHADER_TESS_EVAL:
772 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
773 if (ctx->options->key.tes.as_es) {
774 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
775 add_sgpr_argument(&args, ctx->i32, NULL); //
776 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
777 } else {
778 add_sgpr_argument(&args, ctx->i32, NULL); //
779 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
780 }
781 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
782 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
783 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
784 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
785 break;
786 case MESA_SHADER_GEOMETRY:
787 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
788 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
789 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
790 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
791 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
792 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
799 break;
800 case MESA_SHADER_FRAGMENT:
801 if (ctx->shader_info->info.ps.needs_sample_positions)
802 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
803 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
804 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
805 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
806 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
807 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
810 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
811 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
812 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
813 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
814 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
816 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
817 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
818 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
819 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
820 break;
821 default:
822 unreachable("Shader stage not implemented");
823 }
824
825 ctx->main_function = create_llvm_function(
826 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
827 ctx->max_workgroup_size,
828 ctx->options->unsafe_math);
829 set_llvm_calling_convention(ctx->main_function, ctx->stage);
830
831
832 ctx->shader_info->num_input_vgprs = 0;
833 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
834 ctx->options->supports_spill ? 2 : 0;
835
836 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
837 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
838
839 if (ctx->stage != MESA_SHADER_FRAGMENT)
840 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
841
842 assign_arguments(ctx->main_function, &args);
843
844 user_sgpr_idx = 0;
845
846 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
847 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
848 if (ctx->options->supports_spill) {
849 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
850 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
851 NULL, 0, AC_FUNC_ATTR_READNONE);
852 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
853 const_array(ctx->v4i32, 16), "");
854 }
855 }
856
857 if (!user_sgpr_info.indirect_all_descriptor_sets) {
858 for (unsigned i = 0; i < num_sets; ++i) {
859 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
860 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
861 } else
862 ctx->descriptor_sets[i] = NULL;
863 }
864 } else {
865 uint32_t desc_sgpr_idx = user_sgpr_idx;
866 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
867
868 for (unsigned i = 0; i < num_sets; ++i) {
869 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
870 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
871 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
872
873 } else
874 ctx->descriptor_sets[i] = NULL;
875 }
876 ctx->shader_info->need_indirect_descriptor_sets = true;
877 }
878
879 if (ctx->shader_info->info.needs_push_constants) {
880 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
881 }
882
883 switch (ctx->stage) {
884 case MESA_SHADER_COMPUTE:
885 if (ctx->shader_info->info.cs.grid_components_used) {
886 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
887 }
888 break;
889 case MESA_SHADER_VERTEX:
890 if (!ctx->is_gs_copy_shader) {
891 if (ctx->shader_info->info.vs.has_vertex_buffers) {
892 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
893 }
894 unsigned vs_num = 2;
895 if (ctx->shader_info->info.vs.needs_draw_id)
896 vs_num++;
897
898 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
899 }
900 if (ctx->options->key.vs.as_ls) {
901 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
902 }
903 if (ctx->options->key.vs.as_ls)
904 declare_tess_lds(ctx);
905 break;
906 case MESA_SHADER_TESS_CTRL:
907 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
908 declare_tess_lds(ctx);
909 break;
910 case MESA_SHADER_TESS_EVAL:
911 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
912 break;
913 case MESA_SHADER_GEOMETRY:
914 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
915 break;
916 case MESA_SHADER_FRAGMENT:
917 if (ctx->shader_info->info.ps.needs_sample_positions) {
918 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
919 }
920 break;
921 default:
922 unreachable("Shader stage not implemented");
923 }
924 }
925
926 static void setup_types(struct nir_to_llvm_context *ctx)
927 {
928 LLVMValueRef args[4];
929
930 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
931 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
932 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
933 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
934 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
935 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
936 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
937 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
938 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
939 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
940 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
941 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
942 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
943 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
944 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
945
946 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
947 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
948 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
949 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
950 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
951 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
952
953 args[0] = ctx->f32zero;
954 args[1] = ctx->f32zero;
955 args[2] = ctx->f32zero;
956 args[3] = ctx->f32one;
957 ctx->v4f32empty = LLVMConstVector(args, 4);
958
959 ctx->uniform_md_kind =
960 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
961 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
962
963 args[0] = LLVMConstReal(ctx->f32, 2.5);
964 }
965
966 static int get_llvm_num_components(LLVMValueRef value)
967 {
968 LLVMTypeRef type = LLVMTypeOf(value);
969 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
970 ? LLVMGetVectorSize(type)
971 : 1;
972 return num_components;
973 }
974
975 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
976 LLVMValueRef value,
977 int index)
978 {
979 int count = get_llvm_num_components(value);
980
981 assert(index < count);
982 if (count == 1)
983 return value;
984
985 return LLVMBuildExtractElement(ctx->builder, value,
986 LLVMConstInt(ctx->i32, index, false), "");
987 }
988
989 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
990 LLVMValueRef value, unsigned count)
991 {
992 unsigned num_components = get_llvm_num_components(value);
993 if (count == num_components)
994 return value;
995
996 LLVMValueRef masks[] = {
997 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
998 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
999
1000 if (count == 1)
1001 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1002 "");
1003
1004 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1005 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1006 }
1007
1008 static void
1009 build_store_values_extended(struct nir_to_llvm_context *ctx,
1010 LLVMValueRef *values,
1011 unsigned value_count,
1012 unsigned value_stride,
1013 LLVMValueRef vec)
1014 {
1015 LLVMBuilderRef builder = ctx->builder;
1016 unsigned i;
1017
1018 if (value_count == 1) {
1019 LLVMBuildStore(builder, vec, values[0]);
1020 return;
1021 }
1022
1023 for (i = 0; i < value_count; i++) {
1024 LLVMValueRef ptr = values[i * value_stride];
1025 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1026 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1027 LLVMBuildStore(builder, value, ptr);
1028 }
1029 }
1030
1031 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1032 const nir_ssa_def *def)
1033 {
1034 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1035 if (def->num_components > 1) {
1036 type = LLVMVectorType(type, def->num_components);
1037 }
1038 return type;
1039 }
1040
1041 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1042 {
1043 assert(src.is_ssa);
1044 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1045 return (LLVMValueRef)entry->data;
1046 }
1047
1048
1049 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1050 const struct nir_block *b)
1051 {
1052 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1053 return (LLVMBasicBlockRef)entry->data;
1054 }
1055
1056 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1057 nir_alu_src src,
1058 unsigned num_components)
1059 {
1060 LLVMValueRef value = get_src(ctx, src.src);
1061 bool need_swizzle = false;
1062
1063 assert(value);
1064 LLVMTypeRef type = LLVMTypeOf(value);
1065 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1066 ? LLVMGetVectorSize(type)
1067 : 1;
1068
1069 for (unsigned i = 0; i < num_components; ++i) {
1070 assert(src.swizzle[i] < src_components);
1071 if (src.swizzle[i] != i)
1072 need_swizzle = true;
1073 }
1074
1075 if (need_swizzle || num_components != src_components) {
1076 LLVMValueRef masks[] = {
1077 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1078 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1079 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1080 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1081
1082 if (src_components > 1 && num_components == 1) {
1083 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1084 masks[0], "");
1085 } else if (src_components == 1 && num_components > 1) {
1086 LLVMValueRef values[] = {value, value, value, value};
1087 value = ac_build_gather_values(&ctx->ac, values, num_components);
1088 } else {
1089 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1090 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1091 swizzle, "");
1092 }
1093 }
1094 assert(!src.negate);
1095 assert(!src.abs);
1096 return value;
1097 }
1098
1099 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1100 LLVMIntPredicate pred, LLVMValueRef src0,
1101 LLVMValueRef src1)
1102 {
1103 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1104 return LLVMBuildSelect(ctx->builder, result,
1105 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1106 LLVMConstInt(ctx->i32, 0, false), "");
1107 }
1108
1109 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1110 LLVMRealPredicate pred, LLVMValueRef src0,
1111 LLVMValueRef src1)
1112 {
1113 LLVMValueRef result;
1114 src0 = to_float(ctx, src0);
1115 src1 = to_float(ctx, src1);
1116 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1117 return LLVMBuildSelect(ctx->builder, result,
1118 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1119 LLVMConstInt(ctx->i32, 0, false), "");
1120 }
1121
1122 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1123 const char *intrin,
1124 LLVMTypeRef result_type,
1125 LLVMValueRef src0)
1126 {
1127 char name[64];
1128 LLVMValueRef params[] = {
1129 to_float(ctx, src0),
1130 };
1131
1132 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1133 get_elem_bits(ctx, result_type));
1134 assert(length < sizeof(name));
1135 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1136 }
1137
1138 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1139 const char *intrin,
1140 LLVMTypeRef result_type,
1141 LLVMValueRef src0, LLVMValueRef src1)
1142 {
1143 char name[64];
1144 LLVMValueRef params[] = {
1145 to_float(ctx, src0),
1146 to_float(ctx, src1),
1147 };
1148
1149 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1150 get_elem_bits(ctx, result_type));
1151 assert(length < sizeof(name));
1152 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1153 }
1154
1155 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1156 const char *intrin,
1157 LLVMTypeRef result_type,
1158 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1159 {
1160 char name[64];
1161 LLVMValueRef params[] = {
1162 to_float(ctx, src0),
1163 to_float(ctx, src1),
1164 to_float(ctx, src2),
1165 };
1166
1167 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1168 get_elem_bits(ctx, result_type));
1169 assert(length < sizeof(name));
1170 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1171 }
1172
1173 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1174 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1175 {
1176 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1177 ctx->i32_0, "");
1178 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1179 }
1180
1181 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1182 LLVMValueRef src0)
1183 {
1184 LLVMValueRef params[2] = {
1185 src0,
1186
1187 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1188 * add special code to check for x=0. The reason is that
1189 * the LLVM behavior for x=0 is different from what we
1190 * need here.
1191 *
1192 * The hardware already implements the correct behavior.
1193 */
1194 LLVMConstInt(ctx->i1, 1, false),
1195 };
1196 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1197 }
1198
1199 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1200 LLVMValueRef src0)
1201 {
1202 return ac_build_imsb(ctx, src0, ctx->i32);
1203 }
1204
1205 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1206 LLVMValueRef src0)
1207 {
1208 return ac_build_umsb(ctx, src0, ctx->i32);
1209 }
1210
1211 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1212 LLVMIntPredicate pred,
1213 LLVMValueRef src0, LLVMValueRef src1)
1214 {
1215 return LLVMBuildSelect(ctx->builder,
1216 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1217 src0,
1218 src1, "");
1219
1220 }
1221 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1222 LLVMValueRef src0)
1223 {
1224 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1225 LLVMBuildNeg(ctx->builder, src0, ""));
1226 }
1227
1228 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1229 LLVMValueRef src0)
1230 {
1231 LLVMValueRef cmp, val;
1232
1233 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1234 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1235 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1236 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1237 return val;
1238 }
1239
1240 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1241 LLVMValueRef src0)
1242 {
1243 LLVMValueRef cmp, val;
1244
1245 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1246 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1247 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1248 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1249 return val;
1250 }
1251
1252 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1253 LLVMValueRef src0)
1254 {
1255 const char *intr = "llvm.floor.f32";
1256 LLVMValueRef fsrc0 = to_float(ctx, src0);
1257 LLVMValueRef params[] = {
1258 fsrc0,
1259 };
1260 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1261 ctx->f32, params, 1,
1262 AC_FUNC_ATTR_READNONE);
1263 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1264 }
1265
1266 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1267 const char *intrin,
1268 LLVMValueRef src0, LLVMValueRef src1)
1269 {
1270 LLVMTypeRef ret_type;
1271 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1272 LLVMValueRef res;
1273 LLVMValueRef params[] = { src0, src1 };
1274 ret_type = LLVMStructTypeInContext(ctx->context, types,
1275 2, true);
1276
1277 res = ac_build_intrinsic(ctx, intrin, ret_type,
1278 params, 2, AC_FUNC_ATTR_READNONE);
1279
1280 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1281 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1282 return res;
1283 }
1284
1285 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1286 LLVMValueRef src0)
1287 {
1288 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1289 }
1290
1291 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1292 LLVMValueRef src0)
1293 {
1294 src0 = to_float(ctx, src0);
1295 return LLVMBuildSExt(ctx->builder,
1296 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1297 ctx->i32, "");
1298 }
1299
1300 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1301 LLVMValueRef src0)
1302 {
1303 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1304 }
1305
1306 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1307 LLVMValueRef src0)
1308 {
1309 return LLVMBuildSExt(ctx->builder,
1310 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1311 ctx->i32, "");
1312 }
1313
1314 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1315 LLVMValueRef src0)
1316 {
1317 LLVMValueRef result;
1318 LLVMValueRef cond;
1319
1320 src0 = to_float(&ctx->ac, src0);
1321 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1322
1323 /* TODO SI/CIK options here */
1324 if (ctx->options->chip_class >= VI) {
1325 LLVMValueRef args[2];
1326 /* Check if the result is a denormal - and flush to 0 if so. */
1327 args[0] = result;
1328 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1329 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1330 }
1331
1332 /* need to convert back up to f32 */
1333 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1334
1335 if (ctx->options->chip_class >= VI)
1336 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1337
1338 return result;
1339 }
1340
1341 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1342 LLVMValueRef src0, LLVMValueRef src1)
1343 {
1344 LLVMValueRef dst64, result;
1345 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1346 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1347
1348 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1349 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1350 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1351 return result;
1352 }
1353
1354 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1355 LLVMValueRef src0, LLVMValueRef src1)
1356 {
1357 LLVMValueRef dst64, result;
1358 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1359 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1360
1361 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1362 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1363 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1364 return result;
1365 }
1366
1367 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1368 bool is_signed,
1369 const LLVMValueRef srcs[3])
1370 {
1371 LLVMValueRef result;
1372 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1373
1374 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1375 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1376 return result;
1377 }
1378
1379 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1380 LLVMValueRef src0, LLVMValueRef src1,
1381 LLVMValueRef src2, LLVMValueRef src3)
1382 {
1383 LLVMValueRef bfi_args[3], result;
1384
1385 bfi_args[0] = LLVMBuildShl(ctx->builder,
1386 LLVMBuildSub(ctx->builder,
1387 LLVMBuildShl(ctx->builder,
1388 ctx->i32_1,
1389 src3, ""),
1390 ctx->i32_1, ""),
1391 src2, "");
1392 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1393 bfi_args[2] = src0;
1394
1395 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1396
1397 /* Calculate:
1398 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1399 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1400 */
1401 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1402 LLVMBuildAnd(ctx->builder, bfi_args[0],
1403 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1404
1405 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1406 return result;
1407 }
1408
1409 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1410 LLVMValueRef src0)
1411 {
1412 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1413 int i;
1414 LLVMValueRef comp[2];
1415
1416 src0 = to_float(ctx, src0);
1417 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1418 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1419 for (i = 0; i < 2; i++) {
1420 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1421 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1422 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1423 }
1424
1425 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1426 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1427
1428 return comp[0];
1429 }
1430
1431 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1432 LLVMValueRef src0)
1433 {
1434 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1435 LLVMValueRef temps[2], result, val;
1436 int i;
1437
1438 for (i = 0; i < 2; i++) {
1439 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1440 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1441 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1442 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1443 }
1444
1445 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1446 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1447 ctx->i32_0, "");
1448 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1449 ctx->i32_1, "");
1450 return result;
1451 }
1452
1453 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1454 nir_op op,
1455 LLVMValueRef src0)
1456 {
1457 unsigned mask;
1458 int idx;
1459 LLVMValueRef result;
1460
1461 if (!ctx->lds && !ctx->has_ds_bpermute)
1462 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1463 LLVMArrayType(ctx->i32, 64),
1464 "ddxy_lds", LOCAL_ADDR_SPACE);
1465
1466 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1467 mask = AC_TID_MASK_LEFT;
1468 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1469 mask = AC_TID_MASK_TOP;
1470 else
1471 mask = AC_TID_MASK_TOP_LEFT;
1472
1473 /* for DDX we want to next X pixel, DDY next Y pixel. */
1474 if (op == nir_op_fddx_fine ||
1475 op == nir_op_fddx_coarse ||
1476 op == nir_op_fddx)
1477 idx = 1;
1478 else
1479 idx = 2;
1480
1481 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1482 mask, idx, ctx->lds,
1483 src0);
1484 return result;
1485 }
1486
1487 /*
1488 * this takes an I,J coordinate pair,
1489 * and works out the X and Y derivatives.
1490 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1491 */
1492 static LLVMValueRef emit_ddxy_interp(
1493 struct nir_to_llvm_context *ctx,
1494 LLVMValueRef interp_ij)
1495 {
1496 LLVMValueRef result[4], a;
1497 unsigned i;
1498
1499 for (i = 0; i < 2; i++) {
1500 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1501 LLVMConstInt(ctx->i32, i, false), "");
1502 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1503 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1504 }
1505 return ac_build_gather_values(&ctx->ac, result, 4);
1506 }
1507
1508 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1509 {
1510 LLVMValueRef src[4], result = NULL;
1511 unsigned num_components = instr->dest.dest.ssa.num_components;
1512 unsigned src_components;
1513 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1514
1515 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1516 switch (instr->op) {
1517 case nir_op_vec2:
1518 case nir_op_vec3:
1519 case nir_op_vec4:
1520 src_components = 1;
1521 break;
1522 case nir_op_pack_half_2x16:
1523 src_components = 2;
1524 break;
1525 case nir_op_unpack_half_2x16:
1526 src_components = 1;
1527 break;
1528 default:
1529 src_components = num_components;
1530 break;
1531 }
1532 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1533 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1534
1535 switch (instr->op) {
1536 case nir_op_fmov:
1537 case nir_op_imov:
1538 result = src[0];
1539 break;
1540 case nir_op_fneg:
1541 src[0] = to_float(&ctx->ac, src[0]);
1542 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1543 break;
1544 case nir_op_ineg:
1545 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1546 break;
1547 case nir_op_inot:
1548 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1549 break;
1550 case nir_op_iadd:
1551 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1552 break;
1553 case nir_op_fadd:
1554 src[0] = to_float(&ctx->ac, src[0]);
1555 src[1] = to_float(&ctx->ac, src[1]);
1556 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1557 break;
1558 case nir_op_fsub:
1559 src[0] = to_float(&ctx->ac, src[0]);
1560 src[1] = to_float(&ctx->ac, src[1]);
1561 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1562 break;
1563 case nir_op_isub:
1564 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1565 break;
1566 case nir_op_imul:
1567 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1568 break;
1569 case nir_op_imod:
1570 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1571 break;
1572 case nir_op_umod:
1573 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_fmod:
1576 src[0] = to_float(&ctx->ac, src[0]);
1577 src[1] = to_float(&ctx->ac, src[1]);
1578 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1579 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1580 to_float_type(&ctx->ac, def_type), result);
1581 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1582 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1583 break;
1584 case nir_op_frem:
1585 src[0] = to_float(&ctx->ac, src[0]);
1586 src[1] = to_float(&ctx->ac, src[1]);
1587 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1588 break;
1589 case nir_op_irem:
1590 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1591 break;
1592 case nir_op_idiv:
1593 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1594 break;
1595 case nir_op_udiv:
1596 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_fmul:
1599 src[0] = to_float(&ctx->ac, src[0]);
1600 src[1] = to_float(&ctx->ac, src[1]);
1601 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1602 break;
1603 case nir_op_fdiv:
1604 src[0] = to_float(&ctx->ac, src[0]);
1605 src[1] = to_float(&ctx->ac, src[1]);
1606 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1607 break;
1608 case nir_op_frcp:
1609 src[0] = to_float(&ctx->ac, src[0]);
1610 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1611 break;
1612 case nir_op_iand:
1613 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1614 break;
1615 case nir_op_ior:
1616 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_ixor:
1619 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_ishl:
1622 result = LLVMBuildShl(ctx->ac.builder, src[0],
1623 LLVMBuildZExt(ctx->ac.builder, src[1],
1624 LLVMTypeOf(src[0]), ""),
1625 "");
1626 break;
1627 case nir_op_ishr:
1628 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1629 LLVMBuildZExt(ctx->ac.builder, src[1],
1630 LLVMTypeOf(src[0]), ""),
1631 "");
1632 break;
1633 case nir_op_ushr:
1634 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1635 LLVMBuildZExt(ctx->ac.builder, src[1],
1636 LLVMTypeOf(src[0]), ""),
1637 "");
1638 break;
1639 case nir_op_ilt:
1640 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1641 break;
1642 case nir_op_ine:
1643 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1644 break;
1645 case nir_op_ieq:
1646 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1647 break;
1648 case nir_op_ige:
1649 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1650 break;
1651 case nir_op_ult:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1653 break;
1654 case nir_op_uge:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1656 break;
1657 case nir_op_feq:
1658 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1659 break;
1660 case nir_op_fne:
1661 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1662 break;
1663 case nir_op_flt:
1664 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1665 break;
1666 case nir_op_fge:
1667 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1668 break;
1669 case nir_op_fabs:
1670 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1671 to_float_type(&ctx->ac, def_type), src[0]);
1672 break;
1673 case nir_op_iabs:
1674 result = emit_iabs(&ctx->ac, src[0]);
1675 break;
1676 case nir_op_imax:
1677 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1678 break;
1679 case nir_op_imin:
1680 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1681 break;
1682 case nir_op_umax:
1683 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1684 break;
1685 case nir_op_umin:
1686 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1687 break;
1688 case nir_op_isign:
1689 result = emit_isign(&ctx->ac, src[0]);
1690 break;
1691 case nir_op_fsign:
1692 src[0] = to_float(&ctx->ac, src[0]);
1693 result = emit_fsign(&ctx->ac, src[0]);
1694 break;
1695 case nir_op_ffloor:
1696 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1697 to_float_type(&ctx->ac, def_type), src[0]);
1698 break;
1699 case nir_op_ftrunc:
1700 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1701 to_float_type(&ctx->ac, def_type), src[0]);
1702 break;
1703 case nir_op_fceil:
1704 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1705 to_float_type(&ctx->ac, def_type), src[0]);
1706 break;
1707 case nir_op_fround_even:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1709 to_float_type(&ctx->ac, def_type),src[0]);
1710 break;
1711 case nir_op_ffract:
1712 result = emit_ffract(&ctx->ac, src[0]);
1713 break;
1714 case nir_op_fsin:
1715 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1716 to_float_type(&ctx->ac, def_type), src[0]);
1717 break;
1718 case nir_op_fcos:
1719 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1720 to_float_type(&ctx->ac, def_type), src[0]);
1721 break;
1722 case nir_op_fsqrt:
1723 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1724 to_float_type(&ctx->ac, def_type), src[0]);
1725 break;
1726 case nir_op_fexp2:
1727 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1728 to_float_type(&ctx->ac, def_type), src[0]);
1729 break;
1730 case nir_op_flog2:
1731 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1732 to_float_type(&ctx->ac, def_type), src[0]);
1733 break;
1734 case nir_op_frsq:
1735 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1736 to_float_type(&ctx->ac, def_type), src[0]);
1737 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1738 break;
1739 case nir_op_fpow:
1740 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1741 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1742 break;
1743 case nir_op_fmax:
1744 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1745 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1746 if (instr->dest.dest.ssa.bit_size == 32)
1747 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1748 to_float_type(&ctx->ac, def_type),
1749 result);
1750 break;
1751 case nir_op_fmin:
1752 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1753 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1754 if (instr->dest.dest.ssa.bit_size == 32)
1755 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1756 to_float_type(&ctx->ac, def_type),
1757 result);
1758 break;
1759 case nir_op_ffma:
1760 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1761 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1762 break;
1763 case nir_op_ibitfield_extract:
1764 result = emit_bitfield_extract(&ctx->ac, true, src);
1765 break;
1766 case nir_op_ubitfield_extract:
1767 result = emit_bitfield_extract(&ctx->ac, false, src);
1768 break;
1769 case nir_op_bitfield_insert:
1770 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1771 break;
1772 case nir_op_bitfield_reverse:
1773 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1774 break;
1775 case nir_op_bit_count:
1776 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1777 break;
1778 case nir_op_vec2:
1779 case nir_op_vec3:
1780 case nir_op_vec4:
1781 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1782 src[i] = to_integer(&ctx->ac, src[i]);
1783 result = ac_build_gather_values(&ctx->ac, src, num_components);
1784 break;
1785 case nir_op_f2i32:
1786 case nir_op_f2i64:
1787 src[0] = to_float(&ctx->ac, src[0]);
1788 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1789 break;
1790 case nir_op_f2u32:
1791 case nir_op_f2u64:
1792 src[0] = to_float(&ctx->ac, src[0]);
1793 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1794 break;
1795 case nir_op_i2f32:
1796 case nir_op_i2f64:
1797 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1798 break;
1799 case nir_op_u2f32:
1800 case nir_op_u2f64:
1801 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1802 break;
1803 case nir_op_f2f64:
1804 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1805 break;
1806 case nir_op_f2f32:
1807 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_u2u32:
1810 case nir_op_u2u64:
1811 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1812 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1813 else
1814 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1815 break;
1816 case nir_op_i2i32:
1817 case nir_op_i2i64:
1818 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1819 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1820 else
1821 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1822 break;
1823 case nir_op_bcsel:
1824 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1825 break;
1826 case nir_op_find_lsb:
1827 result = emit_find_lsb(&ctx->ac, src[0]);
1828 break;
1829 case nir_op_ufind_msb:
1830 result = emit_ufind_msb(&ctx->ac, src[0]);
1831 break;
1832 case nir_op_ifind_msb:
1833 result = emit_ifind_msb(&ctx->ac, src[0]);
1834 break;
1835 case nir_op_uadd_carry:
1836 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1837 break;
1838 case nir_op_usub_borrow:
1839 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1840 break;
1841 case nir_op_b2f:
1842 result = emit_b2f(&ctx->ac, src[0]);
1843 break;
1844 case nir_op_f2b:
1845 result = emit_f2b(&ctx->ac, src[0]);
1846 break;
1847 case nir_op_b2i:
1848 result = emit_b2i(&ctx->ac, src[0]);
1849 break;
1850 case nir_op_i2b:
1851 result = emit_i2b(&ctx->ac, src[0]);
1852 break;
1853 case nir_op_fquantize2f16:
1854 result = emit_f2f16(ctx->nctx, src[0]);
1855 break;
1856 case nir_op_umul_high:
1857 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1858 break;
1859 case nir_op_imul_high:
1860 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1861 break;
1862 case nir_op_pack_half_2x16:
1863 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1864 break;
1865 case nir_op_unpack_half_2x16:
1866 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1867 break;
1868 case nir_op_fddx:
1869 case nir_op_fddy:
1870 case nir_op_fddx_fine:
1871 case nir_op_fddy_fine:
1872 case nir_op_fddx_coarse:
1873 case nir_op_fddy_coarse:
1874 result = emit_ddxy(ctx->nctx, instr->op, src[0]);
1875 break;
1876
1877 case nir_op_unpack_64_2x32_split_x: {
1878 assert(instr->src[0].src.ssa->num_components == 1);
1879 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1880 LLVMVectorType(ctx->ac.i32, 2),
1881 "");
1882 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1883 ctx->ac.i32_0, "");
1884 break;
1885 }
1886
1887 case nir_op_unpack_64_2x32_split_y: {
1888 assert(instr->src[0].src.ssa->num_components == 1);
1889 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1890 LLVMVectorType(ctx->ac.i32, 2),
1891 "");
1892 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1893 ctx->ac.i32_0, "");
1894 break;
1895 }
1896
1897 case nir_op_pack_64_2x32_split: {
1898 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1899 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1900 src[0], ctx->ac.i32_0, "");
1901 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1902 src[1], ctx->ac.i32_1, "");
1903 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1904 break;
1905 }
1906
1907 default:
1908 fprintf(stderr, "Unknown NIR alu instr: ");
1909 nir_print_instr(&instr->instr, stderr);
1910 fprintf(stderr, "\n");
1911 abort();
1912 }
1913
1914 if (result) {
1915 assert(instr->dest.dest.is_ssa);
1916 result = to_integer(&ctx->ac, result);
1917 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1918 result);
1919 }
1920 }
1921
1922 static void visit_load_const(struct ac_nir_context *ctx,
1923 const nir_load_const_instr *instr)
1924 {
1925 LLVMValueRef values[4], value = NULL;
1926 LLVMTypeRef element_type =
1927 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1928
1929 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1930 switch (instr->def.bit_size) {
1931 case 32:
1932 values[i] = LLVMConstInt(element_type,
1933 instr->value.u32[i], false);
1934 break;
1935 case 64:
1936 values[i] = LLVMConstInt(element_type,
1937 instr->value.u64[i], false);
1938 break;
1939 default:
1940 fprintf(stderr,
1941 "unsupported nir load_const bit_size: %d\n",
1942 instr->def.bit_size);
1943 abort();
1944 }
1945 }
1946 if (instr->def.num_components > 1) {
1947 value = LLVMConstVector(values, instr->def.num_components);
1948 } else
1949 value = values[0];
1950
1951 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1952 }
1953
1954 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1955 LLVMTypeRef type)
1956 {
1957 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1958 return LLVMBuildBitCast(ctx->builder, ptr,
1959 LLVMPointerType(type, addr_space), "");
1960 }
1961
1962 static LLVMValueRef
1963 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1964 {
1965 LLVMValueRef size =
1966 LLVMBuildExtractElement(ctx->builder, descriptor,
1967 LLVMConstInt(ctx->i32, 2, false), "");
1968
1969 /* VI only */
1970 if (ctx->options->chip_class >= VI && in_elements) {
1971 /* On VI, the descriptor contains the size in bytes,
1972 * but TXQ must return the size in elements.
1973 * The stride is always non-zero for resources using TXQ.
1974 */
1975 LLVMValueRef stride =
1976 LLVMBuildExtractElement(ctx->builder, descriptor,
1977 LLVMConstInt(ctx->i32, 1, false), "");
1978 stride = LLVMBuildLShr(ctx->builder, stride,
1979 LLVMConstInt(ctx->i32, 16, false), "");
1980 stride = LLVMBuildAnd(ctx->builder, stride,
1981 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1982
1983 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1984 }
1985 return size;
1986 }
1987
1988 /**
1989 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1990 * intrinsic names).
1991 */
1992 static void build_int_type_name(
1993 LLVMTypeRef type,
1994 char *buf, unsigned bufsize)
1995 {
1996 assert(bufsize >= 6);
1997
1998 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1999 snprintf(buf, bufsize, "v%ui32",
2000 LLVMGetVectorSize(type));
2001 else
2002 strcpy(buf, "i32");
2003 }
2004
2005 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
2006 struct ac_image_args *args,
2007 const nir_tex_instr *instr)
2008 {
2009 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2010 LLVMValueRef coord = args->addr;
2011 LLVMValueRef half_texel[2];
2012 LLVMValueRef compare_cube_wa;
2013 LLVMValueRef result;
2014 int c;
2015 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2016
2017 //TODO Rect
2018 {
2019 struct ac_image_args txq_args = { 0 };
2020
2021 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2022 txq_args.opcode = ac_image_get_resinfo;
2023 txq_args.dmask = 0xf;
2024 txq_args.addr = ctx->i32zero;
2025 txq_args.resource = args->resource;
2026 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
2027
2028 for (c = 0; c < 2; c++) {
2029 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2030 LLVMConstInt(ctx->i32, c, false), "");
2031 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2032 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
2033 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2034 LLVMConstReal(ctx->f32, -0.5), "");
2035 }
2036 }
2037
2038 LLVMValueRef orig_coords = args->addr;
2039
2040 for (c = 0; c < 2; c++) {
2041 LLVMValueRef tmp;
2042 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2043 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2044 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2045 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2046 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2047 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2048 }
2049
2050
2051 /*
2052 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2053 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2054 * workaround by sampling using a scaled type and converting.
2055 * This is taken from amdgpu-pro shaders.
2056 */
2057 /* NOTE this produces some ugly code compared to amdgpu-pro,
2058 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2059 * and then reads them back. -pro generates two selects,
2060 * one s_cmp for the descriptor rewriting
2061 * one v_cmp for the coordinate and result changes.
2062 */
2063 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2064 LLVMValueRef tmp, tmp2;
2065
2066 /* workaround 8/8/8/8 uint/sint cube gather bug */
2067 /* first detect it then change to a scaled read and f2i */
2068 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2069 tmp2 = tmp;
2070
2071 /* extract the DATA_FORMAT */
2072 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2073 LLVMConstInt(ctx->i32, 6, false), false);
2074
2075 /* is the DATA_FORMAT == 8_8_8_8 */
2076 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2077
2078 if (stype == GLSL_TYPE_UINT)
2079 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2080 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2081 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2082 else
2083 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2084 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2085 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2086
2087 /* replace the NUM FORMAT in the descriptor */
2088 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2089 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2090
2091 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2092
2093 /* don't modify the coordinates for this case */
2094 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2095 }
2096 args->addr = coord;
2097 result = ac_build_image_opcode(&ctx->ac, args);
2098
2099 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2100 LLVMValueRef tmp, tmp2;
2101
2102 /* if the cube workaround is in place, f2i the result. */
2103 for (c = 0; c < 4; c++) {
2104 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2105 if (stype == GLSL_TYPE_UINT)
2106 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2107 else
2108 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2109 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2110 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2111 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2112 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2113 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2114 }
2115 }
2116 return result;
2117 }
2118
2119 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2120 const nir_tex_instr *instr,
2121 bool lod_is_zero,
2122 struct ac_image_args *args)
2123 {
2124 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2125 return ac_build_buffer_load_format(&ctx->ac,
2126 args->resource,
2127 args->addr,
2128 LLVMConstInt(ctx->i32, 0, false),
2129 true);
2130 }
2131
2132 args->opcode = ac_image_sample;
2133 args->compare = instr->is_shadow;
2134
2135 switch (instr->op) {
2136 case nir_texop_txf:
2137 case nir_texop_txf_ms:
2138 case nir_texop_samples_identical:
2139 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2140 args->compare = false;
2141 args->offset = false;
2142 break;
2143 case nir_texop_txb:
2144 args->bias = true;
2145 break;
2146 case nir_texop_txl:
2147 if (lod_is_zero)
2148 args->level_zero = true;
2149 else
2150 args->lod = true;
2151 break;
2152 case nir_texop_txs:
2153 case nir_texop_query_levels:
2154 args->opcode = ac_image_get_resinfo;
2155 break;
2156 case nir_texop_tex:
2157 if (ctx->stage != MESA_SHADER_FRAGMENT)
2158 args->level_zero = true;
2159 break;
2160 case nir_texop_txd:
2161 args->deriv = true;
2162 break;
2163 case nir_texop_tg4:
2164 args->opcode = ac_image_gather4;
2165 args->level_zero = true;
2166 break;
2167 case nir_texop_lod:
2168 args->opcode = ac_image_get_lod;
2169 args->compare = false;
2170 args->offset = false;
2171 break;
2172 default:
2173 break;
2174 }
2175
2176 if (instr->op == nir_texop_tg4) {
2177 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2178 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2179 return radv_lower_gather4_integer(ctx, args, instr);
2180 }
2181 }
2182 return ac_build_image_opcode(&ctx->ac, args);
2183 }
2184
2185 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2186 nir_intrinsic_instr *instr)
2187 {
2188 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2189 unsigned desc_set = nir_intrinsic_desc_set(instr);
2190 unsigned binding = nir_intrinsic_binding(instr);
2191 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2192 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2193 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2194 unsigned base_offset = layout->binding[binding].offset;
2195 LLVMValueRef offset, stride;
2196
2197 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2198 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2199 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2200 layout->binding[binding].dynamic_offset_offset;
2201 desc_ptr = ctx->push_constants;
2202 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2203 stride = LLVMConstInt(ctx->i32, 16, false);
2204 } else
2205 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2206
2207 offset = LLVMConstInt(ctx->i32, base_offset, false);
2208 index = LLVMBuildMul(ctx->builder, index, stride, "");
2209 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2210
2211 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2212 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2213 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2214
2215 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2216 }
2217
2218 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2219 nir_intrinsic_instr *instr)
2220 {
2221 LLVMValueRef ptr, addr;
2222
2223 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2224 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2225
2226 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2227 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2228
2229 return LLVMBuildLoad(ctx->builder, ptr, "");
2230 }
2231
2232 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2233 const nir_intrinsic_instr *instr)
2234 {
2235 LLVMValueRef desc = get_src(ctx->nir, instr->src[0]);
2236
2237 return get_buffer_size(ctx, desc, false);
2238 }
2239 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2240 nir_intrinsic_instr *instr)
2241 {
2242 const char *store_name;
2243 LLVMValueRef src_data = get_src(ctx->nir, instr->src[0]);
2244 LLVMTypeRef data_type = ctx->f32;
2245 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2246 int components_32bit = elem_size_mult * instr->num_components;
2247 unsigned writemask = nir_intrinsic_write_mask(instr);
2248 LLVMValueRef base_data, base_offset;
2249 LLVMValueRef params[6];
2250
2251 if (ctx->stage == MESA_SHADER_FRAGMENT)
2252 ctx->shader_info->fs.writes_memory = true;
2253
2254 params[1] = get_src(ctx->nir, instr->src[1]);
2255 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2256 params[4] = ctx->i1false; /* glc */
2257 params[5] = ctx->i1false; /* slc */
2258
2259 if (components_32bit > 1)
2260 data_type = LLVMVectorType(ctx->f32, components_32bit);
2261
2262 base_data = to_float(&ctx->ac, src_data);
2263 base_data = trim_vector(ctx, base_data, instr->num_components);
2264 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2265 data_type, "");
2266 base_offset = get_src(ctx->nir, instr->src[2]); /* voffset */
2267 while (writemask) {
2268 int start, count;
2269 LLVMValueRef data;
2270 LLVMValueRef offset;
2271 LLVMValueRef tmp;
2272 u_bit_scan_consecutive_range(&writemask, &start, &count);
2273
2274 /* Due to an LLVM limitation, split 3-element writes
2275 * into a 2-element and a 1-element write. */
2276 if (count == 3) {
2277 writemask |= 1 << (start + 2);
2278 count = 2;
2279 }
2280
2281 start *= elem_size_mult;
2282 count *= elem_size_mult;
2283
2284 if (count > 4) {
2285 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2286 count = 4;
2287 }
2288
2289 if (count == 4) {
2290 store_name = "llvm.amdgcn.buffer.store.v4f32";
2291 data = base_data;
2292 } else if (count == 2) {
2293 tmp = LLVMBuildExtractElement(ctx->builder,
2294 base_data, LLVMConstInt(ctx->i32, start, false), "");
2295 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2296 ctx->i32zero, "");
2297
2298 tmp = LLVMBuildExtractElement(ctx->builder,
2299 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2300 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2301 ctx->i32one, "");
2302 store_name = "llvm.amdgcn.buffer.store.v2f32";
2303
2304 } else {
2305 assert(count == 1);
2306 if (get_llvm_num_components(base_data) > 1)
2307 data = LLVMBuildExtractElement(ctx->builder, base_data,
2308 LLVMConstInt(ctx->i32, start, false), "");
2309 else
2310 data = base_data;
2311 store_name = "llvm.amdgcn.buffer.store.f32";
2312 }
2313
2314 offset = base_offset;
2315 if (start != 0) {
2316 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2317 }
2318 params[0] = data;
2319 params[3] = offset;
2320 ac_build_intrinsic(&ctx->ac, store_name,
2321 ctx->voidt, params, 6, 0);
2322 }
2323 }
2324
2325 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2326 const nir_intrinsic_instr *instr)
2327 {
2328 const char *name;
2329 LLVMValueRef params[6];
2330 int arg_count = 0;
2331 if (ctx->stage == MESA_SHADER_FRAGMENT)
2332 ctx->shader_info->fs.writes_memory = true;
2333
2334 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2335 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx->nir, instr->src[3]), 0);
2336 }
2337 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx->nir, instr->src[2]), 0);
2338 params[arg_count++] = get_src(ctx->nir, instr->src[0]);
2339 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2340 params[arg_count++] = get_src(ctx->nir, instr->src[1]); /* voffset */
2341 params[arg_count++] = ctx->i1false; /* slc */
2342
2343 switch (instr->intrinsic) {
2344 case nir_intrinsic_ssbo_atomic_add:
2345 name = "llvm.amdgcn.buffer.atomic.add";
2346 break;
2347 case nir_intrinsic_ssbo_atomic_imin:
2348 name = "llvm.amdgcn.buffer.atomic.smin";
2349 break;
2350 case nir_intrinsic_ssbo_atomic_umin:
2351 name = "llvm.amdgcn.buffer.atomic.umin";
2352 break;
2353 case nir_intrinsic_ssbo_atomic_imax:
2354 name = "llvm.amdgcn.buffer.atomic.smax";
2355 break;
2356 case nir_intrinsic_ssbo_atomic_umax:
2357 name = "llvm.amdgcn.buffer.atomic.umax";
2358 break;
2359 case nir_intrinsic_ssbo_atomic_and:
2360 name = "llvm.amdgcn.buffer.atomic.and";
2361 break;
2362 case nir_intrinsic_ssbo_atomic_or:
2363 name = "llvm.amdgcn.buffer.atomic.or";
2364 break;
2365 case nir_intrinsic_ssbo_atomic_xor:
2366 name = "llvm.amdgcn.buffer.atomic.xor";
2367 break;
2368 case nir_intrinsic_ssbo_atomic_exchange:
2369 name = "llvm.amdgcn.buffer.atomic.swap";
2370 break;
2371 case nir_intrinsic_ssbo_atomic_comp_swap:
2372 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2373 break;
2374 default:
2375 abort();
2376 }
2377
2378 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2379 }
2380
2381 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2382 const nir_intrinsic_instr *instr)
2383 {
2384 LLVMValueRef results[2];
2385 int load_components;
2386 int num_components = instr->num_components;
2387 if (instr->dest.ssa.bit_size == 64)
2388 num_components *= 2;
2389
2390 for (int i = 0; i < num_components; i += load_components) {
2391 load_components = MIN2(num_components - i, 4);
2392 const char *load_name;
2393 LLVMTypeRef data_type = ctx->f32;
2394 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2395 offset = LLVMBuildAdd(ctx->builder, get_src(ctx->nir, instr->src[1]), offset, "");
2396
2397 if (load_components == 3)
2398 data_type = LLVMVectorType(ctx->f32, 4);
2399 else if (load_components > 1)
2400 data_type = LLVMVectorType(ctx->f32, load_components);
2401
2402 if (load_components >= 3)
2403 load_name = "llvm.amdgcn.buffer.load.v4f32";
2404 else if (load_components == 2)
2405 load_name = "llvm.amdgcn.buffer.load.v2f32";
2406 else if (load_components == 1)
2407 load_name = "llvm.amdgcn.buffer.load.f32";
2408 else
2409 unreachable("unhandled number of components");
2410
2411 LLVMValueRef params[] = {
2412 get_src(ctx->nir, instr->src[0]),
2413 LLVMConstInt(ctx->i32, 0, false),
2414 offset,
2415 ctx->i1false,
2416 ctx->i1false,
2417 };
2418
2419 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2420
2421 }
2422
2423 LLVMValueRef ret = results[0];
2424 if (num_components > 4 || num_components == 3) {
2425 LLVMValueRef masks[] = {
2426 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2427 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2428 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2429 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2430 };
2431
2432 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2433 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2434 results[num_components > 4 ? 1 : 0], swizzle, "");
2435 }
2436
2437 return LLVMBuildBitCast(ctx->builder, ret,
2438 get_def_type(ctx->nir, &instr->dest.ssa), "");
2439 }
2440
2441 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2442 const nir_intrinsic_instr *instr)
2443 {
2444 LLVMValueRef results[8], ret;
2445 LLVMValueRef rsrc = get_src(ctx->nir, instr->src[0]);
2446 LLVMValueRef offset = get_src(ctx->nir, instr->src[1]);
2447 int num_components = instr->num_components;
2448
2449 if (instr->dest.ssa.bit_size == 64)
2450 num_components *= 2;
2451
2452 for (unsigned i = 0; i < num_components; ++i) {
2453 LLVMValueRef params[] = {
2454 rsrc,
2455 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2456 offset, "")
2457 };
2458 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->f32,
2459 params, 2,
2460 AC_FUNC_ATTR_READNONE |
2461 AC_FUNC_ATTR_LEGACY);
2462 }
2463
2464
2465 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2466 return LLVMBuildBitCast(ctx->builder, ret,
2467 get_def_type(ctx->nir, &instr->dest.ssa), "");
2468 }
2469
2470 static void
2471 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2472 bool vs_in, unsigned *vertex_index_out,
2473 LLVMValueRef *vertex_index_ref,
2474 unsigned *const_out, LLVMValueRef *indir_out)
2475 {
2476 unsigned const_offset = 0;
2477 nir_deref *tail = &deref->deref;
2478 LLVMValueRef offset = NULL;
2479
2480 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2481 tail = tail->child;
2482 nir_deref_array *deref_array = nir_deref_as_array(tail);
2483 if (vertex_index_out)
2484 *vertex_index_out = deref_array->base_offset;
2485
2486 if (vertex_index_ref) {
2487 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2488 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2489 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx->nir, deref_array->indirect), "");
2490 }
2491 *vertex_index_ref = vtx;
2492 }
2493 }
2494
2495 if (deref->var->data.compact) {
2496 assert(tail->child->deref_type == nir_deref_type_array);
2497 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2498 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2499 /* We always lower indirect dereferences for "compact" array vars. */
2500 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2501
2502 const_offset = deref_array->base_offset;
2503 goto out;
2504 }
2505
2506 while (tail->child != NULL) {
2507 const struct glsl_type *parent_type = tail->type;
2508 tail = tail->child;
2509
2510 if (tail->deref_type == nir_deref_type_array) {
2511 nir_deref_array *deref_array = nir_deref_as_array(tail);
2512 LLVMValueRef index, stride, local_offset;
2513 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2514
2515 const_offset += size * deref_array->base_offset;
2516 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2517 continue;
2518
2519 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2520 index = get_src(ctx->nir, deref_array->indirect);
2521 stride = LLVMConstInt(ctx->i32, size, 0);
2522 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2523
2524 if (offset)
2525 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2526 else
2527 offset = local_offset;
2528 } else if (tail->deref_type == nir_deref_type_struct) {
2529 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2530
2531 for (unsigned i = 0; i < deref_struct->index; i++) {
2532 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2533 const_offset += glsl_count_attribute_slots(ft, vs_in);
2534 }
2535 } else
2536 unreachable("unsupported deref type");
2537
2538 }
2539 out:
2540 if (const_offset && offset)
2541 offset = LLVMBuildAdd(ctx->builder, offset,
2542 LLVMConstInt(ctx->i32, const_offset, 0),
2543 "");
2544
2545 *const_out = const_offset;
2546 *indir_out = offset;
2547 }
2548
2549 static LLVMValueRef
2550 lds_load(struct nir_to_llvm_context *ctx,
2551 LLVMValueRef dw_addr)
2552 {
2553 LLVMValueRef value;
2554 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2555 return value;
2556 }
2557
2558 static void
2559 lds_store(struct nir_to_llvm_context *ctx,
2560 LLVMValueRef dw_addr, LLVMValueRef value)
2561 {
2562 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2563 ac_build_indexed_store(&ctx->ac, ctx->lds,
2564 dw_addr, value);
2565 }
2566
2567 /* The offchip buffer layout for TCS->TES is
2568 *
2569 * - attribute 0 of patch 0 vertex 0
2570 * - attribute 0 of patch 0 vertex 1
2571 * - attribute 0 of patch 0 vertex 2
2572 * ...
2573 * - attribute 0 of patch 1 vertex 0
2574 * - attribute 0 of patch 1 vertex 1
2575 * ...
2576 * - attribute 1 of patch 0 vertex 0
2577 * - attribute 1 of patch 0 vertex 1
2578 * ...
2579 * - per patch attribute 0 of patch 0
2580 * - per patch attribute 0 of patch 1
2581 * ...
2582 *
2583 * Note that every attribute has 4 components.
2584 */
2585 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2586 LLVMValueRef vertex_index,
2587 LLVMValueRef param_index)
2588 {
2589 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2590 LLVMValueRef param_stride, constant16;
2591 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2592
2593 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2594 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2595 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2596 num_patches, "");
2597
2598 constant16 = LLVMConstInt(ctx->i32, 16, false);
2599 if (vertex_index) {
2600 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2601 vertices_per_patch, "");
2602
2603 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2604 vertex_index, "");
2605
2606 param_stride = total_vertices;
2607 } else {
2608 base_addr = rel_patch_id;
2609 param_stride = num_patches;
2610 }
2611
2612 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2613 LLVMBuildMul(ctx->builder, param_index,
2614 param_stride, ""), "");
2615
2616 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2617
2618 if (!vertex_index) {
2619 LLVMValueRef patch_data_offset =
2620 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2621
2622 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2623 patch_data_offset, "");
2624 }
2625 return base_addr;
2626 }
2627
2628 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2629 unsigned param,
2630 unsigned const_index,
2631 bool is_compact,
2632 LLVMValueRef vertex_index,
2633 LLVMValueRef indir_index)
2634 {
2635 LLVMValueRef param_index;
2636
2637 if (indir_index)
2638 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2639 indir_index, "");
2640 else {
2641 if (const_index && !is_compact)
2642 param += const_index;
2643 param_index = LLVMConstInt(ctx->i32, param, false);
2644 }
2645 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2646 }
2647
2648 static void
2649 mark_tess_output(struct nir_to_llvm_context *ctx,
2650 bool is_patch, uint32_t param)
2651
2652 {
2653 if (is_patch) {
2654 ctx->tess_patch_outputs_written |= (1ull << param);
2655 } else
2656 ctx->tess_outputs_written |= (1ull << param);
2657 }
2658
2659 static LLVMValueRef
2660 get_dw_address(struct nir_to_llvm_context *ctx,
2661 LLVMValueRef dw_addr,
2662 unsigned param,
2663 unsigned const_index,
2664 bool compact_const_index,
2665 LLVMValueRef vertex_index,
2666 LLVMValueRef stride,
2667 LLVMValueRef indir_index)
2668
2669 {
2670
2671 if (vertex_index) {
2672 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2673 LLVMBuildMul(ctx->builder,
2674 vertex_index,
2675 stride, ""), "");
2676 }
2677
2678 if (indir_index)
2679 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2680 LLVMBuildMul(ctx->builder, indir_index,
2681 LLVMConstInt(ctx->i32, 4, false), ""), "");
2682 else if (const_index && !compact_const_index)
2683 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2684 LLVMConstInt(ctx->i32, const_index, false), "");
2685
2686 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2687 LLVMConstInt(ctx->i32, param * 4, false), "");
2688
2689 if (const_index && compact_const_index)
2690 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2691 LLVMConstInt(ctx->i32, const_index, false), "");
2692 return dw_addr;
2693 }
2694
2695 static LLVMValueRef
2696 load_tcs_input(struct nir_to_llvm_context *ctx,
2697 nir_intrinsic_instr *instr)
2698 {
2699 LLVMValueRef dw_addr, stride;
2700 unsigned const_index;
2701 LLVMValueRef vertex_index;
2702 LLVMValueRef indir_index;
2703 unsigned param;
2704 LLVMValueRef value[4], result;
2705 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2706 const bool is_compact = instr->variables[0]->var->data.compact;
2707 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2708 radv_get_deref_offset(ctx, instr->variables[0],
2709 false, NULL, per_vertex ? &vertex_index : NULL,
2710 &const_index, &indir_index);
2711
2712 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2713 dw_addr = get_tcs_in_current_patch_offset(ctx);
2714 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2715 indir_index);
2716
2717 for (unsigned i = 0; i < instr->num_components; i++) {
2718 value[i] = lds_load(ctx, dw_addr);
2719 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2720 ctx->i32one, "");
2721 }
2722 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2723 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2724 return result;
2725 }
2726
2727 static LLVMValueRef
2728 load_tcs_output(struct nir_to_llvm_context *ctx,
2729 nir_intrinsic_instr *instr)
2730 {
2731 LLVMValueRef dw_addr, stride;
2732 LLVMValueRef value[4], result;
2733 LLVMValueRef vertex_index = NULL;
2734 LLVMValueRef indir_index = NULL;
2735 unsigned const_index = 0;
2736 unsigned param;
2737 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2738 const bool is_compact = instr->variables[0]->var->data.compact;
2739 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2740 radv_get_deref_offset(ctx, instr->variables[0],
2741 false, NULL, per_vertex ? &vertex_index : NULL,
2742 &const_index, &indir_index);
2743
2744 if (!instr->variables[0]->var->data.patch) {
2745 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2746 dw_addr = get_tcs_out_current_patch_offset(ctx);
2747 } else {
2748 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2749 }
2750
2751 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2752 indir_index);
2753
2754 for (unsigned i = 0; i < instr->num_components; i++) {
2755 value[i] = lds_load(ctx, dw_addr);
2756 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2757 ctx->i32one, "");
2758 }
2759 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2760 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2761 return result;
2762 }
2763
2764 static void
2765 store_tcs_output(struct nir_to_llvm_context *ctx,
2766 nir_intrinsic_instr *instr,
2767 LLVMValueRef src,
2768 unsigned writemask)
2769 {
2770 LLVMValueRef stride, dw_addr;
2771 LLVMValueRef buf_addr = NULL;
2772 LLVMValueRef vertex_index = NULL;
2773 LLVMValueRef indir_index = NULL;
2774 unsigned const_index = 0;
2775 unsigned param;
2776 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2777 const bool is_compact = instr->variables[0]->var->data.compact;
2778
2779 radv_get_deref_offset(ctx, instr->variables[0],
2780 false, NULL, per_vertex ? &vertex_index : NULL,
2781 &const_index, &indir_index);
2782
2783 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2784 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2785 is_compact && const_index > 3) {
2786 const_index -= 3;
2787 param++;
2788 }
2789
2790 if (!instr->variables[0]->var->data.patch) {
2791 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2792 dw_addr = get_tcs_out_current_patch_offset(ctx);
2793 } else {
2794 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2795 }
2796
2797 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2798
2799 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2800 indir_index);
2801 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2802 vertex_index, indir_index);
2803
2804 unsigned base = is_compact ? const_index : 0;
2805 for (unsigned chan = 0; chan < 8; chan++) {
2806 bool is_tess_factor = false;
2807 if (!(writemask & (1 << chan)))
2808 continue;
2809 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2810
2811 lds_store(ctx, dw_addr, value);
2812
2813 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2814 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2815 is_tess_factor = true;
2816
2817 if (!is_tess_factor && writemask != 0xF)
2818 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2819 buf_addr, ctx->oc_lds,
2820 4 * (base + chan), 1, 0, true, false);
2821
2822 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2823 ctx->i32one, "");
2824 }
2825
2826 if (writemask == 0xF) {
2827 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2828 buf_addr, ctx->oc_lds,
2829 (base * 4), 1, 0, true, false);
2830 }
2831 }
2832
2833 static LLVMValueRef
2834 load_tes_input(struct nir_to_llvm_context *ctx,
2835 const nir_intrinsic_instr *instr)
2836 {
2837 LLVMValueRef buf_addr;
2838 LLVMValueRef result;
2839 LLVMValueRef vertex_index = NULL;
2840 LLVMValueRef indir_index = NULL;
2841 unsigned const_index = 0;
2842 unsigned param;
2843 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2844 const bool is_compact = instr->variables[0]->var->data.compact;
2845
2846 radv_get_deref_offset(ctx, instr->variables[0],
2847 false, NULL, per_vertex ? &vertex_index : NULL,
2848 &const_index, &indir_index);
2849 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2850 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2851 is_compact && const_index > 3) {
2852 const_index -= 3;
2853 param++;
2854 }
2855 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2856 is_compact, vertex_index, indir_index);
2857
2858 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2859 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2860 result = trim_vector(ctx, result, instr->num_components);
2861 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2862 return result;
2863 }
2864
2865 static LLVMValueRef
2866 load_gs_input(struct nir_to_llvm_context *ctx,
2867 nir_intrinsic_instr *instr)
2868 {
2869 LLVMValueRef indir_index, vtx_offset;
2870 unsigned const_index;
2871 LLVMValueRef args[9];
2872 unsigned param, vtx_offset_param;
2873 LLVMValueRef value[4], result;
2874 unsigned vertex_index;
2875 radv_get_deref_offset(ctx, instr->variables[0],
2876 false, &vertex_index, NULL,
2877 &const_index, &indir_index);
2878 vtx_offset_param = vertex_index;
2879 assert(vtx_offset_param < 6);
2880 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2881 LLVMConstInt(ctx->i32, 4, false), "");
2882
2883 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2884 for (unsigned i = 0; i < instr->num_components; i++) {
2885
2886 args[0] = ctx->esgs_ring;
2887 args[1] = vtx_offset;
2888 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2889 args[3] = ctx->i32zero;
2890 args[4] = ctx->i32one; /* OFFEN */
2891 args[5] = ctx->i32zero; /* IDXEN */
2892 args[6] = ctx->i32one; /* GLC */
2893 args[7] = ctx->i32zero; /* SLC */
2894 args[8] = ctx->i32zero; /* TFE */
2895
2896 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2897 ctx->i32, args, 9,
2898 AC_FUNC_ATTR_READONLY |
2899 AC_FUNC_ATTR_LEGACY);
2900 }
2901 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2902
2903 return result;
2904 }
2905
2906 static LLVMValueRef
2907 build_gep_for_deref(struct ac_nir_context *ctx,
2908 nir_deref_var *deref)
2909 {
2910 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2911 assert(entry->data);
2912 LLVMValueRef val = entry->data;
2913 nir_deref *tail = deref->deref.child;
2914 while (tail != NULL) {
2915 LLVMValueRef offset;
2916 switch (tail->deref_type) {
2917 case nir_deref_type_array: {
2918 nir_deref_array *array = nir_deref_as_array(tail);
2919 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2920 if (array->deref_array_type ==
2921 nir_deref_array_type_indirect) {
2922 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2923 get_src(ctx,
2924 array->indirect),
2925 "");
2926 }
2927 break;
2928 }
2929 case nir_deref_type_struct: {
2930 nir_deref_struct *deref_struct =
2931 nir_deref_as_struct(tail);
2932 offset = LLVMConstInt(ctx->ac.i32,
2933 deref_struct->index, 0);
2934 break;
2935 }
2936 default:
2937 unreachable("bad deref type");
2938 }
2939 val = ac_build_gep0(&ctx->ac, val, offset);
2940 tail = tail->child;
2941 }
2942 return val;
2943 }
2944
2945 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2946 nir_intrinsic_instr *instr)
2947 {
2948 LLVMValueRef values[8];
2949 int idx = instr->variables[0]->var->data.driver_location;
2950 int ve = instr->dest.ssa.num_components;
2951 LLVMValueRef indir_index;
2952 LLVMValueRef ret;
2953 unsigned const_index;
2954 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2955 instr->variables[0]->var->data.mode == nir_var_shader_in;
2956 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2957 &const_index, &indir_index);
2958
2959 if (instr->dest.ssa.bit_size == 64)
2960 ve *= 2;
2961
2962 switch (instr->variables[0]->var->data.mode) {
2963 case nir_var_shader_in:
2964 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2965 return load_tcs_input(ctx, instr);
2966 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2967 return load_tes_input(ctx, instr);
2968 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2969 return load_gs_input(ctx, instr);
2970 }
2971 for (unsigned chan = 0; chan < ve; chan++) {
2972 if (indir_index) {
2973 unsigned count = glsl_count_attribute_slots(
2974 instr->variables[0]->var->type,
2975 ctx->stage == MESA_SHADER_VERTEX);
2976 count -= chan / 4;
2977 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2978 &ctx->ac, ctx->inputs + idx + chan, count,
2979 4, false);
2980
2981 values[chan] = LLVMBuildExtractElement(ctx->builder,
2982 tmp_vec,
2983 indir_index, "");
2984 } else
2985 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2986 }
2987 break;
2988 case nir_var_local:
2989 for (unsigned chan = 0; chan < ve; chan++) {
2990 if (indir_index) {
2991 unsigned count = glsl_count_attribute_slots(
2992 instr->variables[0]->var->type, false);
2993 count -= chan / 4;
2994 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2995 &ctx->ac, ctx->nir->locals + idx + chan, count,
2996 4, true);
2997
2998 values[chan] = LLVMBuildExtractElement(ctx->builder,
2999 tmp_vec,
3000 indir_index, "");
3001 } else {
3002 values[chan] = LLVMBuildLoad(ctx->builder, ctx->nir->locals[idx + chan + const_index * 4], "");
3003 }
3004 }
3005 break;
3006 case nir_var_shared: {
3007 LLVMValueRef address = build_gep_for_deref(ctx->nir,
3008 instr->variables[0]);
3009 LLVMValueRef val = LLVMBuildLoad(ctx->builder, address, "");
3010 return LLVMBuildBitCast(ctx->builder, val,
3011 get_def_type(ctx->nir, &instr->dest.ssa),
3012 "");
3013 }
3014 case nir_var_shader_out:
3015 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3016 return load_tcs_output(ctx, instr);
3017 for (unsigned chan = 0; chan < ve; chan++) {
3018 if (indir_index) {
3019 unsigned count = glsl_count_attribute_slots(
3020 instr->variables[0]->var->type, false);
3021 count -= chan / 4;
3022 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3023 &ctx->ac, ctx->nir->outputs + idx + chan, count,
3024 4, true);
3025
3026 values[chan] = LLVMBuildExtractElement(ctx->builder,
3027 tmp_vec,
3028 indir_index, "");
3029 } else {
3030 values[chan] = LLVMBuildLoad(ctx->builder,
3031 ctx->nir->outputs[idx + chan + const_index * 4],
3032 "");
3033 }
3034 }
3035 break;
3036 default:
3037 unreachable("unhandle variable mode");
3038 }
3039 ret = ac_build_gather_values(&ctx->ac, values, ve);
3040 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx->nir, &instr->dest.ssa), "");
3041 }
3042
3043 static void
3044 visit_store_var(struct nir_to_llvm_context *ctx,
3045 nir_intrinsic_instr *instr)
3046 {
3047 LLVMValueRef temp_ptr, value;
3048 int idx = instr->variables[0]->var->data.driver_location;
3049 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx->nir, instr->src[0]));
3050 int writemask = instr->const_index[0];
3051 LLVMValueRef indir_index;
3052 unsigned const_index;
3053 radv_get_deref_offset(ctx, instr->variables[0], false,
3054 NULL, NULL, &const_index, &indir_index);
3055
3056 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3057 int old_writemask = writemask;
3058
3059 src = LLVMBuildBitCast(ctx->builder, src,
3060 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
3061 "");
3062
3063 writemask = 0;
3064 for (unsigned chan = 0; chan < 4; chan++) {
3065 if (old_writemask & (1 << chan))
3066 writemask |= 3u << (2 * chan);
3067 }
3068 }
3069
3070 switch (instr->variables[0]->var->data.mode) {
3071 case nir_var_shader_out:
3072
3073 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3074 store_tcs_output(ctx, instr, src, writemask);
3075 return;
3076 }
3077
3078 for (unsigned chan = 0; chan < 8; chan++) {
3079 int stride = 4;
3080 if (!(writemask & (1 << chan)))
3081 continue;
3082
3083 value = llvm_extract_elem(ctx, src, chan);
3084
3085 if (instr->variables[0]->var->data.compact)
3086 stride = 1;
3087 if (indir_index) {
3088 unsigned count = glsl_count_attribute_slots(
3089 instr->variables[0]->var->type, false);
3090 count -= chan / 4;
3091 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3092 &ctx->ac, ctx->nir->outputs + idx + chan, count,
3093 stride, true);
3094
3095 if (get_llvm_num_components(tmp_vec) > 1) {
3096 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3097 value, indir_index, "");
3098 } else
3099 tmp_vec = value;
3100 build_store_values_extended(ctx, ctx->nir->outputs + idx + chan,
3101 count, stride, tmp_vec);
3102
3103 } else {
3104 temp_ptr = ctx->nir->outputs[idx + chan + const_index * stride];
3105
3106 LLVMBuildStore(ctx->builder, value, temp_ptr);
3107 }
3108 }
3109 break;
3110 case nir_var_local:
3111 for (unsigned chan = 0; chan < 8; chan++) {
3112 if (!(writemask & (1 << chan)))
3113 continue;
3114
3115 value = llvm_extract_elem(ctx, src, chan);
3116 if (indir_index) {
3117 unsigned count = glsl_count_attribute_slots(
3118 instr->variables[0]->var->type, false);
3119 count -= chan / 4;
3120 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3121 &ctx->ac, ctx->nir->locals + idx + chan, count,
3122 4, true);
3123
3124 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3125 value, indir_index, "");
3126 build_store_values_extended(ctx, ctx->nir->locals + idx + chan,
3127 count, 4, tmp_vec);
3128 } else {
3129 temp_ptr = ctx->nir->locals[idx + chan + const_index * 4];
3130
3131 LLVMBuildStore(ctx->builder, value, temp_ptr);
3132 }
3133 }
3134 break;
3135 case nir_var_shared: {
3136 int writemask = instr->const_index[0];
3137 LLVMValueRef address = build_gep_for_deref(ctx->nir,
3138 instr->variables[0]);
3139 LLVMValueRef val = get_src(ctx->nir, instr->src[0]);
3140 unsigned components =
3141 glsl_get_vector_elements(
3142 nir_deref_tail(&instr->variables[0]->deref)->type);
3143 if (writemask == (1 << components) - 1) {
3144 val = LLVMBuildBitCast(
3145 ctx->builder, val,
3146 LLVMGetElementType(LLVMTypeOf(address)), "");
3147 LLVMBuildStore(ctx->builder, val, address);
3148 } else {
3149 for (unsigned chan = 0; chan < 4; chan++) {
3150 if (!(writemask & (1 << chan)))
3151 continue;
3152 LLVMValueRef ptr =
3153 LLVMBuildStructGEP(ctx->builder,
3154 address, chan, "");
3155 LLVMValueRef src = llvm_extract_elem(ctx, val,
3156 chan);
3157 src = LLVMBuildBitCast(
3158 ctx->builder, src,
3159 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3160 LLVMBuildStore(ctx->builder, src, ptr);
3161 }
3162 }
3163 break;
3164 }
3165 default:
3166 break;
3167 }
3168 }
3169
3170 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3171 {
3172 switch (dim) {
3173 case GLSL_SAMPLER_DIM_BUF:
3174 return 1;
3175 case GLSL_SAMPLER_DIM_1D:
3176 return array ? 2 : 1;
3177 case GLSL_SAMPLER_DIM_2D:
3178 return array ? 3 : 2;
3179 case GLSL_SAMPLER_DIM_MS:
3180 return array ? 4 : 3;
3181 case GLSL_SAMPLER_DIM_3D:
3182 case GLSL_SAMPLER_DIM_CUBE:
3183 return 3;
3184 case GLSL_SAMPLER_DIM_RECT:
3185 case GLSL_SAMPLER_DIM_SUBPASS:
3186 return 2;
3187 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3188 return 3;
3189 default:
3190 break;
3191 }
3192 return 0;
3193 }
3194
3195
3196
3197 /* Adjust the sample index according to FMASK.
3198 *
3199 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3200 * which is the identity mapping. Each nibble says which physical sample
3201 * should be fetched to get that sample.
3202 *
3203 * For example, 0x11111100 means there are only 2 samples stored and
3204 * the second sample covers 3/4 of the pixel. When reading samples 0
3205 * and 1, return physical sample 0 (determined by the first two 0s
3206 * in FMASK), otherwise return physical sample 1.
3207 *
3208 * The sample index should be adjusted as follows:
3209 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3210 */
3211 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3212 LLVMValueRef coord_x, LLVMValueRef coord_y,
3213 LLVMValueRef coord_z,
3214 LLVMValueRef sample_index,
3215 LLVMValueRef fmask_desc_ptr)
3216 {
3217 LLVMValueRef fmask_load_address[4];
3218 LLVMValueRef res;
3219
3220 fmask_load_address[0] = coord_x;
3221 fmask_load_address[1] = coord_y;
3222 if (coord_z) {
3223 fmask_load_address[2] = coord_z;
3224 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3225 }
3226
3227 struct ac_image_args args = {0};
3228
3229 args.opcode = ac_image_load;
3230 args.da = coord_z ? true : false;
3231 args.resource = fmask_desc_ptr;
3232 args.dmask = 0xf;
3233 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3234
3235 res = ac_build_image_opcode(&ctx->ac, &args);
3236
3237 res = to_integer(&ctx->ac, res);
3238 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3239 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3240
3241 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3242 res,
3243 ctx->i32zero, "");
3244
3245 LLVMValueRef sample_index4 =
3246 LLVMBuildMul(ctx->builder, sample_index, four, "");
3247 LLVMValueRef shifted_fmask =
3248 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3249 LLVMValueRef final_sample =
3250 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3251
3252 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3253 * resource descriptor is 0 (invalid),
3254 */
3255 LLVMValueRef fmask_desc =
3256 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3257 ctx->v8i32, "");
3258
3259 LLVMValueRef fmask_word1 =
3260 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3261 ctx->i32one, "");
3262
3263 LLVMValueRef word1_is_nonzero =
3264 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3265 fmask_word1, ctx->i32zero, "");
3266
3267 /* Replace the MSAA sample index. */
3268 sample_index =
3269 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3270 final_sample, sample_index, "");
3271 return sample_index;
3272 }
3273
3274 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3275 const nir_intrinsic_instr *instr)
3276 {
3277 const struct glsl_type *type = instr->variables[0]->var->type;
3278 if(instr->variables[0]->deref.child)
3279 type = instr->variables[0]->deref.child->type;
3280
3281 LLVMValueRef src0 = get_src(ctx->nir, instr->src[0]);
3282 LLVMValueRef coords[4];
3283 LLVMValueRef masks[] = {
3284 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3285 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3286 };
3287 LLVMValueRef res;
3288 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx->nir, instr->src[1]), 0);
3289
3290 int count;
3291 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3292 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3293 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3294 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3295 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3296
3297 count = image_type_to_components_count(dim,
3298 glsl_sampler_type_is_array(type));
3299
3300 if (is_ms) {
3301 LLVMValueRef fmask_load_address[3];
3302 int chan;
3303
3304 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3305 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3306 if (glsl_sampler_type_is_array(type))
3307 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3308 else
3309 fmask_load_address[2] = NULL;
3310 if (add_frag_pos) {
3311 for (chan = 0; chan < 2; ++chan)
3312 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3313 }
3314 sample_index = adjust_sample_index_using_fmask(ctx,
3315 fmask_load_address[0],
3316 fmask_load_address[1],
3317 fmask_load_address[2],
3318 sample_index,
3319 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3320 }
3321 if (count == 1) {
3322 if (instr->src[0].ssa->num_components)
3323 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3324 else
3325 res = src0;
3326 } else {
3327 int chan;
3328 if (is_ms)
3329 count--;
3330 for (chan = 0; chan < count; ++chan) {
3331 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3332 }
3333
3334 if (add_frag_pos) {
3335 for (chan = 0; chan < count; ++chan)
3336 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3337 }
3338 if (is_ms) {
3339 coords[count] = sample_index;
3340 count++;
3341 }
3342
3343 if (count == 3) {
3344 coords[3] = LLVMGetUndef(ctx->i32);
3345 count = 4;
3346 }
3347 res = ac_build_gather_values(&ctx->ac, coords, count);
3348 }
3349 return res;
3350 }
3351
3352 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3353 const nir_intrinsic_instr *instr)
3354 {
3355 LLVMValueRef params[7];
3356 LLVMValueRef res;
3357 char intrinsic_name[64];
3358 const nir_variable *var = instr->variables[0]->var;
3359 const struct glsl_type *type = var->type;
3360 if(instr->variables[0]->deref.child)
3361 type = instr->variables[0]->deref.child->type;
3362
3363 type = glsl_without_array(type);
3364 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3365 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3366 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3367 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3368 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3369 params[3] = ctx->i1false; /* glc */
3370 params[4] = ctx->i1false; /* slc */
3371 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3372 params, 5, 0);
3373
3374 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3375 res = to_integer(&ctx->ac, res);
3376 } else {
3377 bool is_da = glsl_sampler_type_is_array(type) ||
3378 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3379 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3380 LLVMValueRef glc = ctx->i1false;
3381 LLVMValueRef slc = ctx->i1false;
3382
3383 params[0] = get_image_coords(ctx, instr);
3384 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3385 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3386 if (HAVE_LLVM <= 0x0309) {
3387 params[3] = ctx->i1false; /* r128 */
3388 params[4] = da;
3389 params[5] = glc;
3390 params[6] = slc;
3391 } else {
3392 LLVMValueRef lwe = ctx->i1false;
3393 params[3] = glc;
3394 params[4] = slc;
3395 params[5] = lwe;
3396 params[6] = da;
3397 }
3398
3399 ac_get_image_intr_name("llvm.amdgcn.image.load",
3400 ctx->v4f32, /* vdata */
3401 LLVMTypeOf(params[0]), /* coords */
3402 LLVMTypeOf(params[1]), /* rsrc */
3403 intrinsic_name, sizeof(intrinsic_name));
3404
3405 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3406 params, 7, AC_FUNC_ATTR_READONLY);
3407 }
3408 return to_integer(&ctx->ac, res);
3409 }
3410
3411 static void visit_image_store(struct nir_to_llvm_context *ctx,
3412 nir_intrinsic_instr *instr)
3413 {
3414 LLVMValueRef params[8];
3415 char intrinsic_name[64];
3416 const nir_variable *var = instr->variables[0]->var;
3417 const struct glsl_type *type = glsl_without_array(var->type);
3418 LLVMValueRef glc = ctx->i1false;
3419 bool force_glc = ctx->options->chip_class == SI;
3420 if (force_glc)
3421 glc = ctx->i1true;
3422 if (ctx->stage == MESA_SHADER_FRAGMENT)
3423 ctx->shader_info->fs.writes_memory = true;
3424
3425 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3426 params[0] = to_float(&ctx->ac, get_src(ctx->nir, instr->src[2])); /* data */
3427 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3428 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3429 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3430 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3431 params[4] = glc; /* glc */
3432 params[5] = ctx->i1false; /* slc */
3433 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3434 params, 6, 0);
3435 } else {
3436 bool is_da = glsl_sampler_type_is_array(type) ||
3437 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3438 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3439 LLVMValueRef slc = ctx->i1false;
3440
3441 params[0] = to_float(&ctx->ac, get_src(ctx->nir, instr->src[2]));
3442 params[1] = get_image_coords(ctx, instr); /* coords */
3443 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3444 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3445 if (HAVE_LLVM <= 0x0309) {
3446 params[4] = ctx->i1false; /* r128 */
3447 params[5] = da;
3448 params[6] = glc;
3449 params[7] = slc;
3450 } else {
3451 LLVMValueRef lwe = ctx->i1false;
3452 params[4] = glc;
3453 params[5] = slc;
3454 params[6] = lwe;
3455 params[7] = da;
3456 }
3457
3458 ac_get_image_intr_name("llvm.amdgcn.image.store",
3459 LLVMTypeOf(params[0]), /* vdata */
3460 LLVMTypeOf(params[1]), /* coords */
3461 LLVMTypeOf(params[2]), /* rsrc */
3462 intrinsic_name, sizeof(intrinsic_name));
3463
3464 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3465 params, 8, 0);
3466 }
3467
3468 }
3469
3470 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3471 const nir_intrinsic_instr *instr)
3472 {
3473 LLVMValueRef params[6];
3474 int param_count = 0;
3475 const nir_variable *var = instr->variables[0]->var;
3476
3477 const char *atomic_name;
3478 char intrinsic_name[41];
3479 const struct glsl_type *type = glsl_without_array(var->type);
3480 MAYBE_UNUSED int length;
3481
3482 if (ctx->stage == MESA_SHADER_FRAGMENT)
3483 ctx->shader_info->fs.writes_memory = true;
3484
3485 switch (instr->intrinsic) {
3486 case nir_intrinsic_image_atomic_add:
3487 atomic_name = "add";
3488 break;
3489 case nir_intrinsic_image_atomic_min:
3490 atomic_name = "smin";
3491 break;
3492 case nir_intrinsic_image_atomic_max:
3493 atomic_name = "smax";
3494 break;
3495 case nir_intrinsic_image_atomic_and:
3496 atomic_name = "and";
3497 break;
3498 case nir_intrinsic_image_atomic_or:
3499 atomic_name = "or";
3500 break;
3501 case nir_intrinsic_image_atomic_xor:
3502 atomic_name = "xor";
3503 break;
3504 case nir_intrinsic_image_atomic_exchange:
3505 atomic_name = "swap";
3506 break;
3507 case nir_intrinsic_image_atomic_comp_swap:
3508 atomic_name = "cmpswap";
3509 break;
3510 default:
3511 abort();
3512 }
3513
3514 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3515 params[param_count++] = get_src(ctx->nir, instr->src[3]);
3516 params[param_count++] = get_src(ctx->nir, instr->src[2]);
3517
3518 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3519 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3520 params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3521 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3522 params[param_count++] = ctx->i32zero; /* voffset */
3523 params[param_count++] = ctx->i1false; /* slc */
3524
3525 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3526 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3527 } else {
3528 char coords_type[8];
3529
3530 bool da = glsl_sampler_type_is_array(type) ||
3531 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3532
3533 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3534 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3535 params[param_count++] = ctx->i1false; /* r128 */
3536 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3537 params[param_count++] = ctx->i1false; /* slc */
3538
3539 build_int_type_name(LLVMTypeOf(coords),
3540 coords_type, sizeof(coords_type));
3541
3542 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3543 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3544 }
3545
3546 assert(length < sizeof(intrinsic_name));
3547 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3548 }
3549
3550 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3551 const nir_intrinsic_instr *instr)
3552 {
3553 LLVMValueRef res;
3554 const nir_variable *var = instr->variables[0]->var;
3555 const struct glsl_type *type = instr->variables[0]->var->type;
3556 bool da = glsl_sampler_type_is_array(var->type) ||
3557 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3558 if(instr->variables[0]->deref.child)
3559 type = instr->variables[0]->deref.child->type;
3560
3561 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3562 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3563
3564 struct ac_image_args args = { 0 };
3565
3566 args.da = da;
3567 args.dmask = 0xf;
3568 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3569 args.opcode = ac_image_get_resinfo;
3570 args.addr = ctx->i32zero;
3571
3572 res = ac_build_image_opcode(&ctx->ac, &args);
3573
3574 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3575 glsl_sampler_type_is_array(type)) {
3576 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3577 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3578 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3579 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3580 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3581 }
3582 return res;
3583 }
3584
3585 #define NOOP_WAITCNT 0xf7f
3586 #define LGKM_CNT 0x07f
3587 #define VM_CNT 0xf70
3588
3589 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3590 unsigned simm16)
3591 {
3592 LLVMValueRef args[1] = {
3593 LLVMConstInt(ctx->i32, simm16, false),
3594 };
3595 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3596 ctx->voidt, args, 1, 0);
3597 }
3598
3599 static void emit_barrier(struct nir_to_llvm_context *ctx)
3600 {
3601 /* SI only (thanks to a hw bug workaround):
3602 * The real barrier instruction isn’t needed, because an entire patch
3603 * always fits into a single wave.
3604 */
3605 if (ctx->options->chip_class == SI &&
3606 ctx->stage == MESA_SHADER_TESS_CTRL) {
3607 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3608 return;
3609 }
3610 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3611 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3612 }
3613
3614 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3615 const nir_intrinsic_instr *instr)
3616 {
3617 LLVMValueRef cond;
3618 ctx->shader_info->fs.can_discard = true;
3619
3620 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3621 get_src(ctx->nir, instr->src[0]),
3622 ctx->i32zero, "");
3623
3624 cond = LLVMBuildSelect(ctx->builder, cond,
3625 LLVMConstReal(ctx->f32, -1.0f),
3626 ctx->f32zero, "");
3627 ac_build_kill(&ctx->ac, cond);
3628 }
3629
3630 static LLVMValueRef
3631 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3632 {
3633 LLVMValueRef result;
3634 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3635 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3636 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3637
3638 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3639 }
3640
3641 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3642 const nir_intrinsic_instr *instr)
3643 {
3644 LLVMValueRef ptr, result;
3645 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3646 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3647
3648 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3649 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3650 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3651 ptr, src, src1,
3652 LLVMAtomicOrderingSequentiallyConsistent,
3653 LLVMAtomicOrderingSequentiallyConsistent,
3654 false);
3655 } else {
3656 LLVMAtomicRMWBinOp op;
3657 switch (instr->intrinsic) {
3658 case nir_intrinsic_var_atomic_add:
3659 op = LLVMAtomicRMWBinOpAdd;
3660 break;
3661 case nir_intrinsic_var_atomic_umin:
3662 op = LLVMAtomicRMWBinOpUMin;
3663 break;
3664 case nir_intrinsic_var_atomic_umax:
3665 op = LLVMAtomicRMWBinOpUMax;
3666 break;
3667 case nir_intrinsic_var_atomic_imin:
3668 op = LLVMAtomicRMWBinOpMin;
3669 break;
3670 case nir_intrinsic_var_atomic_imax:
3671 op = LLVMAtomicRMWBinOpMax;
3672 break;
3673 case nir_intrinsic_var_atomic_and:
3674 op = LLVMAtomicRMWBinOpAnd;
3675 break;
3676 case nir_intrinsic_var_atomic_or:
3677 op = LLVMAtomicRMWBinOpOr;
3678 break;
3679 case nir_intrinsic_var_atomic_xor:
3680 op = LLVMAtomicRMWBinOpXor;
3681 break;
3682 case nir_intrinsic_var_atomic_exchange:
3683 op = LLVMAtomicRMWBinOpXchg;
3684 break;
3685 default:
3686 return NULL;
3687 }
3688
3689 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3690 LLVMAtomicOrderingSequentiallyConsistent,
3691 false);
3692 }
3693 return result;
3694 }
3695
3696 #define INTERP_CENTER 0
3697 #define INTERP_CENTROID 1
3698 #define INTERP_SAMPLE 2
3699
3700 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3701 enum glsl_interp_mode interp, unsigned location)
3702 {
3703 switch (interp) {
3704 case INTERP_MODE_FLAT:
3705 default:
3706 return NULL;
3707 case INTERP_MODE_SMOOTH:
3708 case INTERP_MODE_NONE:
3709 if (location == INTERP_CENTER)
3710 return ctx->persp_center;
3711 else if (location == INTERP_CENTROID)
3712 return ctx->persp_centroid;
3713 else if (location == INTERP_SAMPLE)
3714 return ctx->persp_sample;
3715 break;
3716 case INTERP_MODE_NOPERSPECTIVE:
3717 if (location == INTERP_CENTER)
3718 return ctx->linear_center;
3719 else if (location == INTERP_CENTROID)
3720 return ctx->linear_centroid;
3721 else if (location == INTERP_SAMPLE)
3722 return ctx->linear_sample;
3723 break;
3724 }
3725 return NULL;
3726 }
3727
3728 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3729 LLVMValueRef sample_id)
3730 {
3731 LLVMValueRef result;
3732 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3733
3734 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3735 const_array(ctx->v2f32, 64), "");
3736
3737 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3738 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3739
3740 return result;
3741 }
3742
3743 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3744 {
3745 LLVMValueRef values[2];
3746
3747 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3748 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3749 return ac_build_gather_values(&ctx->ac, values, 2);
3750 }
3751
3752 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3753 const nir_intrinsic_instr *instr)
3754 {
3755 LLVMValueRef result[2];
3756 LLVMValueRef interp_param, attr_number;
3757 unsigned location;
3758 unsigned chan;
3759 LLVMValueRef src_c0, src_c1;
3760 LLVMValueRef src0;
3761 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3762 switch (instr->intrinsic) {
3763 case nir_intrinsic_interp_var_at_centroid:
3764 location = INTERP_CENTROID;
3765 break;
3766 case nir_intrinsic_interp_var_at_sample:
3767 case nir_intrinsic_interp_var_at_offset:
3768 location = INTERP_CENTER;
3769 src0 = get_src(ctx->nir, instr->src[0]);
3770 break;
3771 default:
3772 break;
3773 }
3774
3775 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3776 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3777 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3778 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3779 LLVMValueRef sample_position;
3780 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3781
3782 /* fetch sample ID */
3783 sample_position = load_sample_position(ctx, src0);
3784
3785 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3786 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3787 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3788 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3789 }
3790 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3791 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3792
3793 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3794 LLVMValueRef ij_out[2];
3795 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3796
3797 /*
3798 * take the I then J parameters, and the DDX/Y for it, and
3799 * calculate the IJ inputs for the interpolator.
3800 * temp1 = ddx * offset/sample.x + I;
3801 * interp_param.I = ddy * offset/sample.y + temp1;
3802 * temp1 = ddx * offset/sample.x + J;
3803 * interp_param.J = ddy * offset/sample.y + temp1;
3804 */
3805 for (unsigned i = 0; i < 2; i++) {
3806 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3807 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3808 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3809 ddxy_out, ix_ll, "");
3810 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3811 ddxy_out, iy_ll, "");
3812 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3813 interp_param, ix_ll, "");
3814 LLVMValueRef temp1, temp2;
3815
3816 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3817 ctx->f32, "");
3818
3819 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3820 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3821
3822 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3823 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3824
3825 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3826 temp2, ctx->i32, "");
3827 }
3828 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3829
3830 }
3831
3832 for (chan = 0; chan < 2; chan++) {
3833 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3834
3835 if (interp_param) {
3836 interp_param = LLVMBuildBitCast(ctx->builder,
3837 interp_param, LLVMVectorType(ctx->f32, 2), "");
3838 LLVMValueRef i = LLVMBuildExtractElement(
3839 ctx->builder, interp_param, ctx->i32zero, "");
3840 LLVMValueRef j = LLVMBuildExtractElement(
3841 ctx->builder, interp_param, ctx->i32one, "");
3842
3843 result[chan] = ac_build_fs_interp(&ctx->ac,
3844 llvm_chan, attr_number,
3845 ctx->prim_mask, i, j);
3846 } else {
3847 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3848 LLVMConstInt(ctx->i32, 2, false),
3849 llvm_chan, attr_number,
3850 ctx->prim_mask);
3851 }
3852 }
3853 return ac_build_gather_values(&ctx->ac, result, 2);
3854 }
3855
3856 static void
3857 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3858 const nir_intrinsic_instr *instr)
3859 {
3860 LLVMValueRef gs_next_vertex;
3861 LLVMValueRef can_emit, kill;
3862 int idx;
3863
3864 assert(instr->const_index[0] == 0);
3865 /* Write vertex attribute values to GSVS ring */
3866 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3867 ctx->gs_next_vertex,
3868 "");
3869
3870 /* If this thread has already emitted the declared maximum number of
3871 * vertices, kill it: excessive vertex emissions are not supposed to
3872 * have any effect, and GS threads have no externally observable
3873 * effects other than emitting vertices.
3874 */
3875 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3876 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3877
3878 kill = LLVMBuildSelect(ctx->builder, can_emit,
3879 LLVMConstReal(ctx->f32, 1.0f),
3880 LLVMConstReal(ctx->f32, -1.0f), "");
3881 ac_build_kill(&ctx->ac, kill);
3882
3883 /* loop num outputs */
3884 idx = 0;
3885 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3886 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3887 int length = 4;
3888 int slot = idx;
3889 int slot_inc = 1;
3890
3891 if (!(ctx->output_mask & (1ull << i)))
3892 continue;
3893
3894 if (i == VARYING_SLOT_CLIP_DIST0) {
3895 /* pack clip and cull into a single set of slots */
3896 length = ctx->num_output_clips + ctx->num_output_culls;
3897 if (length > 4)
3898 slot_inc = 2;
3899 }
3900 for (unsigned j = 0; j < length; j++) {
3901 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3902 out_ptr[j], "");
3903 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3904 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3905 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3906
3907 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3908
3909 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3910 out_val, 1,
3911 voffset, ctx->gs2vs_offset, 0,
3912 1, 1, true, true);
3913 }
3914 idx += slot_inc;
3915 }
3916
3917 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3918 ctx->i32one, "");
3919 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3920
3921 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3922 }
3923
3924 static void
3925 visit_end_primitive(struct nir_to_llvm_context *ctx,
3926 const nir_intrinsic_instr *instr)
3927 {
3928 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3929 }
3930
3931 static LLVMValueRef
3932 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3933 const nir_intrinsic_instr *instr)
3934 {
3935 LLVMValueRef coord[4] = {
3936 ctx->tes_u,
3937 ctx->tes_v,
3938 ctx->f32zero,
3939 ctx->f32zero,
3940 };
3941
3942 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3943 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3944 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3945
3946 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3947 return LLVMBuildBitCast(ctx->builder, result,
3948 get_def_type(ctx->nir, &instr->dest.ssa), "");
3949 }
3950
3951 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3952 nir_intrinsic_instr *instr)
3953 {
3954 LLVMValueRef result = NULL;
3955
3956 switch (instr->intrinsic) {
3957 case nir_intrinsic_load_work_group_id: {
3958 result = ctx->workgroup_ids;
3959 break;
3960 }
3961 case nir_intrinsic_load_base_vertex: {
3962 result = ctx->abi.base_vertex;
3963 break;
3964 }
3965 case nir_intrinsic_load_vertex_id_zero_base: {
3966 result = ctx->abi.vertex_id;
3967 break;
3968 }
3969 case nir_intrinsic_load_local_invocation_id: {
3970 result = ctx->local_invocation_ids;
3971 break;
3972 }
3973 case nir_intrinsic_load_base_instance:
3974 result = ctx->abi.start_instance;
3975 break;
3976 case nir_intrinsic_load_draw_id:
3977 result = ctx->abi.draw_id;
3978 break;
3979 case nir_intrinsic_load_invocation_id:
3980 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3981 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3982 else
3983 result = ctx->gs_invocation_id;
3984 break;
3985 case nir_intrinsic_load_primitive_id:
3986 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3987 ctx->shader_info->gs.uses_prim_id = true;
3988 result = ctx->gs_prim_id;
3989 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3990 ctx->shader_info->tcs.uses_prim_id = true;
3991 result = ctx->tcs_patch_id;
3992 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
3993 ctx->shader_info->tcs.uses_prim_id = true;
3994 result = ctx->tes_patch_id;
3995 } else
3996 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3997 break;
3998 case nir_intrinsic_load_sample_id:
3999 ctx->shader_info->fs.force_persample = true;
4000 result = unpack_param(ctx, ctx->ancillary, 8, 4);
4001 break;
4002 case nir_intrinsic_load_sample_pos:
4003 ctx->shader_info->fs.force_persample = true;
4004 result = load_sample_pos(ctx);
4005 break;
4006 case nir_intrinsic_load_sample_mask_in:
4007 result = ctx->sample_coverage;
4008 break;
4009 case nir_intrinsic_load_front_face:
4010 result = ctx->front_face;
4011 break;
4012 case nir_intrinsic_load_instance_id:
4013 result = ctx->abi.instance_id;
4014 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4015 ctx->shader_info->vs.vgpr_comp_cnt);
4016 break;
4017 case nir_intrinsic_load_num_work_groups:
4018 result = ctx->num_work_groups;
4019 break;
4020 case nir_intrinsic_load_local_invocation_index:
4021 result = visit_load_local_invocation_index(ctx);
4022 break;
4023 case nir_intrinsic_load_push_constant:
4024 result = visit_load_push_constant(ctx, instr);
4025 break;
4026 case nir_intrinsic_vulkan_resource_index:
4027 result = visit_vulkan_resource_index(ctx, instr);
4028 break;
4029 case nir_intrinsic_store_ssbo:
4030 visit_store_ssbo(ctx, instr);
4031 break;
4032 case nir_intrinsic_load_ssbo:
4033 result = visit_load_buffer(ctx, instr);
4034 break;
4035 case nir_intrinsic_ssbo_atomic_add:
4036 case nir_intrinsic_ssbo_atomic_imin:
4037 case nir_intrinsic_ssbo_atomic_umin:
4038 case nir_intrinsic_ssbo_atomic_imax:
4039 case nir_intrinsic_ssbo_atomic_umax:
4040 case nir_intrinsic_ssbo_atomic_and:
4041 case nir_intrinsic_ssbo_atomic_or:
4042 case nir_intrinsic_ssbo_atomic_xor:
4043 case nir_intrinsic_ssbo_atomic_exchange:
4044 case nir_intrinsic_ssbo_atomic_comp_swap:
4045 result = visit_atomic_ssbo(ctx, instr);
4046 break;
4047 case nir_intrinsic_load_ubo:
4048 result = visit_load_ubo_buffer(ctx, instr);
4049 break;
4050 case nir_intrinsic_get_buffer_size:
4051 result = visit_get_buffer_size(ctx, instr);
4052 break;
4053 case nir_intrinsic_load_var:
4054 result = visit_load_var(ctx, instr);
4055 break;
4056 case nir_intrinsic_store_var:
4057 visit_store_var(ctx, instr);
4058 break;
4059 case nir_intrinsic_image_load:
4060 result = visit_image_load(ctx, instr);
4061 break;
4062 case nir_intrinsic_image_store:
4063 visit_image_store(ctx, instr);
4064 break;
4065 case nir_intrinsic_image_atomic_add:
4066 case nir_intrinsic_image_atomic_min:
4067 case nir_intrinsic_image_atomic_max:
4068 case nir_intrinsic_image_atomic_and:
4069 case nir_intrinsic_image_atomic_or:
4070 case nir_intrinsic_image_atomic_xor:
4071 case nir_intrinsic_image_atomic_exchange:
4072 case nir_intrinsic_image_atomic_comp_swap:
4073 result = visit_image_atomic(ctx, instr);
4074 break;
4075 case nir_intrinsic_image_size:
4076 result = visit_image_size(ctx, instr);
4077 break;
4078 case nir_intrinsic_discard:
4079 ctx->shader_info->fs.can_discard = true;
4080 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4081 ctx->voidt,
4082 NULL, 0, AC_FUNC_ATTR_LEGACY);
4083 break;
4084 case nir_intrinsic_discard_if:
4085 emit_discard_if(ctx, instr);
4086 break;
4087 case nir_intrinsic_memory_barrier:
4088 emit_waitcnt(ctx, VM_CNT);
4089 break;
4090 case nir_intrinsic_barrier:
4091 emit_barrier(ctx);
4092 break;
4093 case nir_intrinsic_var_atomic_add:
4094 case nir_intrinsic_var_atomic_imin:
4095 case nir_intrinsic_var_atomic_umin:
4096 case nir_intrinsic_var_atomic_imax:
4097 case nir_intrinsic_var_atomic_umax:
4098 case nir_intrinsic_var_atomic_and:
4099 case nir_intrinsic_var_atomic_or:
4100 case nir_intrinsic_var_atomic_xor:
4101 case nir_intrinsic_var_atomic_exchange:
4102 case nir_intrinsic_var_atomic_comp_swap:
4103 result = visit_var_atomic(ctx, instr);
4104 break;
4105 case nir_intrinsic_interp_var_at_centroid:
4106 case nir_intrinsic_interp_var_at_sample:
4107 case nir_intrinsic_interp_var_at_offset:
4108 result = visit_interp(ctx, instr);
4109 break;
4110 case nir_intrinsic_emit_vertex:
4111 visit_emit_vertex(ctx, instr);
4112 break;
4113 case nir_intrinsic_end_primitive:
4114 visit_end_primitive(ctx, instr);
4115 break;
4116 case nir_intrinsic_load_tess_coord:
4117 result = visit_load_tess_coord(ctx, instr);
4118 break;
4119 case nir_intrinsic_load_patch_vertices_in:
4120 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4121 break;
4122 default:
4123 fprintf(stderr, "Unknown intrinsic: ");
4124 nir_print_instr(&instr->instr, stderr);
4125 fprintf(stderr, "\n");
4126 break;
4127 }
4128 if (result) {
4129 _mesa_hash_table_insert(ctx->nir->defs, &instr->dest.ssa, result);
4130 }
4131 }
4132
4133 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4134 const nir_deref_var *deref,
4135 enum desc_type desc_type)
4136 {
4137 unsigned desc_set = deref->var->data.descriptor_set;
4138 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4139 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4140 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4141 unsigned offset = binding->offset;
4142 unsigned stride = binding->size;
4143 unsigned type_size;
4144 LLVMBuilderRef builder = ctx->builder;
4145 LLVMTypeRef type;
4146 LLVMValueRef index = NULL;
4147 unsigned constant_index = 0;
4148
4149 assert(deref->var->data.binding < layout->binding_count);
4150
4151 switch (desc_type) {
4152 case DESC_IMAGE:
4153 type = ctx->v8i32;
4154 type_size = 32;
4155 break;
4156 case DESC_FMASK:
4157 type = ctx->v8i32;
4158 offset += 32;
4159 type_size = 32;
4160 break;
4161 case DESC_SAMPLER:
4162 type = ctx->v4i32;
4163 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4164 offset += 64;
4165
4166 type_size = 16;
4167 break;
4168 case DESC_BUFFER:
4169 type = ctx->v4i32;
4170 type_size = 16;
4171 break;
4172 default:
4173 unreachable("invalid desc_type\n");
4174 }
4175
4176 if (deref->deref.child) {
4177 const nir_deref_array *child =
4178 (const nir_deref_array *)deref->deref.child;
4179
4180 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4181 offset += child->base_offset * stride;
4182 if (child->deref_array_type == nir_deref_array_type_indirect) {
4183 index = get_src(ctx->nir, child->indirect);
4184 }
4185
4186 constant_index = child->base_offset;
4187 }
4188 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4189 (!index || binding->immutable_samplers_equal)) {
4190 if (binding->immutable_samplers_equal)
4191 constant_index = 0;
4192
4193 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4194
4195 LLVMValueRef constants[] = {
4196 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4197 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4198 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4199 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4200 };
4201 return ac_build_gather_values(&ctx->ac, constants, 4);
4202 }
4203
4204 assert(stride % type_size == 0);
4205
4206 if (!index)
4207 index = ctx->i32zero;
4208
4209 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4210
4211 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4212 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4213
4214 return ac_build_indexed_load_const(&ctx->ac, list, index);
4215 }
4216
4217 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4218 struct ac_image_args *args,
4219 const nir_tex_instr *instr,
4220 nir_texop op,
4221 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4222 LLVMValueRef *param, unsigned count,
4223 unsigned dmask)
4224 {
4225 unsigned is_rect = 0;
4226 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4227
4228 if (op == nir_texop_lod)
4229 da = false;
4230 /* Pad to power of two vector */
4231 while (count < util_next_power_of_two(count))
4232 param[count++] = LLVMGetUndef(ctx->i32);
4233
4234 if (count > 1)
4235 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4236 else
4237 args->addr = param[0];
4238
4239 args->resource = res_ptr;
4240 args->sampler = samp_ptr;
4241
4242 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4243 args->addr = param[0];
4244 return;
4245 }
4246
4247 args->dmask = dmask;
4248 args->unorm = is_rect;
4249 args->da = da;
4250 }
4251
4252 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4253 *
4254 * SI-CI:
4255 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4256 * filtering manually. The driver sets img7 to a mask clearing
4257 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4258 * s_and_b32 samp0, samp0, img7
4259 *
4260 * VI:
4261 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4262 */
4263 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4264 LLVMValueRef res, LLVMValueRef samp)
4265 {
4266 LLVMBuilderRef builder = ctx->builder;
4267 LLVMValueRef img7, samp0;
4268
4269 if (ctx->options->chip_class >= VI)
4270 return samp;
4271
4272 img7 = LLVMBuildExtractElement(builder, res,
4273 LLVMConstInt(ctx->i32, 7, 0), "");
4274 samp0 = LLVMBuildExtractElement(builder, samp,
4275 LLVMConstInt(ctx->i32, 0, 0), "");
4276 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4277 return LLVMBuildInsertElement(builder, samp, samp0,
4278 LLVMConstInt(ctx->i32, 0, 0), "");
4279 }
4280
4281 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4282 nir_tex_instr *instr,
4283 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4284 LLVMValueRef *fmask_ptr)
4285 {
4286 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4287 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4288 else
4289 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4290 if (samp_ptr) {
4291 if (instr->sampler)
4292 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4293 else
4294 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4295 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4296 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4297 }
4298 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4299 instr->op == nir_texop_samples_identical))
4300 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4301 }
4302
4303 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4304 LLVMValueRef coord)
4305 {
4306 coord = to_float(&ctx->ac, coord);
4307 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4308 coord = to_integer(&ctx->ac, coord);
4309 return coord;
4310 }
4311
4312 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4313 {
4314 LLVMValueRef result = NULL;
4315 struct ac_image_args args = { 0 };
4316 unsigned dmask = 0xf;
4317 LLVMValueRef address[16];
4318 LLVMValueRef coords[5];
4319 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4320 LLVMValueRef bias = NULL, offsets = NULL;
4321 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4322 LLVMValueRef ddx = NULL, ddy = NULL;
4323 LLVMValueRef derivs[6];
4324 unsigned chan, count = 0;
4325 unsigned const_src = 0, num_deriv_comp = 0;
4326 bool lod_is_zero = false;
4327 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4328
4329 for (unsigned i = 0; i < instr->num_srcs; i++) {
4330 switch (instr->src[i].src_type) {
4331 case nir_tex_src_coord:
4332 coord = get_src(ctx->nir, instr->src[i].src);
4333 break;
4334 case nir_tex_src_projector:
4335 break;
4336 case nir_tex_src_comparator:
4337 comparator = get_src(ctx->nir, instr->src[i].src);
4338 break;
4339 case nir_tex_src_offset:
4340 offsets = get_src(ctx->nir, instr->src[i].src);
4341 const_src = i;
4342 break;
4343 case nir_tex_src_bias:
4344 bias = get_src(ctx->nir, instr->src[i].src);
4345 break;
4346 case nir_tex_src_lod: {
4347 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4348
4349 if (val && val->i32[0] == 0)
4350 lod_is_zero = true;
4351 lod = get_src(ctx->nir, instr->src[i].src);
4352 break;
4353 }
4354 case nir_tex_src_ms_index:
4355 sample_index = get_src(ctx->nir, instr->src[i].src);
4356 break;
4357 case nir_tex_src_ms_mcs:
4358 break;
4359 case nir_tex_src_ddx:
4360 ddx = get_src(ctx->nir, instr->src[i].src);
4361 num_deriv_comp = instr->src[i].src.ssa->num_components;
4362 break;
4363 case nir_tex_src_ddy:
4364 ddy = get_src(ctx->nir, instr->src[i].src);
4365 break;
4366 case nir_tex_src_texture_offset:
4367 case nir_tex_src_sampler_offset:
4368 case nir_tex_src_plane:
4369 default:
4370 break;
4371 }
4372 }
4373
4374 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4375 result = get_buffer_size(ctx, res_ptr, true);
4376 goto write_result;
4377 }
4378
4379 if (instr->op == nir_texop_texture_samples) {
4380 LLVMValueRef res, samples, is_msaa;
4381 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4382 samples = LLVMBuildExtractElement(ctx->builder, res,
4383 LLVMConstInt(ctx->i32, 3, false), "");
4384 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4385 LLVMConstInt(ctx->i32, 28, false), "");
4386 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4387 LLVMConstInt(ctx->i32, 0xe, false), "");
4388 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4389 LLVMConstInt(ctx->i32, 0xe, false), "");
4390
4391 samples = LLVMBuildLShr(ctx->builder, samples,
4392 LLVMConstInt(ctx->i32, 16, false), "");
4393 samples = LLVMBuildAnd(ctx->builder, samples,
4394 LLVMConstInt(ctx->i32, 0xf, false), "");
4395 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4396 samples, "");
4397 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4398 ctx->i32one, "");
4399 result = samples;
4400 goto write_result;
4401 }
4402
4403 if (coord)
4404 for (chan = 0; chan < instr->coord_components; chan++)
4405 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4406
4407 if (offsets && instr->op != nir_texop_txf) {
4408 LLVMValueRef offset[3], pack;
4409 for (chan = 0; chan < 3; ++chan)
4410 offset[chan] = ctx->i32zero;
4411
4412 args.offset = true;
4413 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4414 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4415 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4416 LLVMConstInt(ctx->i32, 0x3f, false), "");
4417 if (chan)
4418 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4419 LLVMConstInt(ctx->i32, chan * 8, false), "");
4420 }
4421 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4422 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4423 address[count++] = pack;
4424
4425 }
4426 /* pack LOD bias value */
4427 if (instr->op == nir_texop_txb && bias) {
4428 address[count++] = bias;
4429 }
4430
4431 /* Pack depth comparison value */
4432 if (instr->is_shadow && comparator) {
4433 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4434 }
4435
4436 /* pack derivatives */
4437 if (ddx || ddy) {
4438 switch (instr->sampler_dim) {
4439 case GLSL_SAMPLER_DIM_3D:
4440 case GLSL_SAMPLER_DIM_CUBE:
4441 num_deriv_comp = 3;
4442 break;
4443 case GLSL_SAMPLER_DIM_2D:
4444 default:
4445 num_deriv_comp = 2;
4446 break;
4447 case GLSL_SAMPLER_DIM_1D:
4448 num_deriv_comp = 1;
4449 break;
4450 }
4451
4452 for (unsigned i = 0; i < num_deriv_comp; i++) {
4453 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddx, i));
4454 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddy, i));
4455 }
4456 }
4457
4458 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4459 if (instr->is_array && instr->op != nir_texop_lod)
4460 coords[3] = apply_round_slice(ctx, coords[3]);
4461 for (chan = 0; chan < instr->coord_components; chan++)
4462 coords[chan] = to_float(&ctx->ac, coords[chan]);
4463 if (instr->coord_components == 3)
4464 coords[3] = LLVMGetUndef(ctx->f32);
4465 ac_prepare_cube_coords(&ctx->ac,
4466 instr->op == nir_texop_txd, instr->is_array,
4467 coords, derivs);
4468 if (num_deriv_comp)
4469 num_deriv_comp--;
4470 }
4471
4472 if (ddx || ddy) {
4473 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4474 address[count++] = derivs[i];
4475 }
4476
4477 /* Pack texture coordinates */
4478 if (coord) {
4479 address[count++] = coords[0];
4480 if (instr->coord_components > 1) {
4481 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4482 coords[1] = apply_round_slice(ctx, coords[1]);
4483 }
4484 address[count++] = coords[1];
4485 }
4486 if (instr->coord_components > 2) {
4487 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4488 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4489 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4490 instr->op != nir_texop_txf) {
4491 coords[2] = apply_round_slice(ctx, coords[2]);
4492 }
4493 address[count++] = coords[2];
4494 }
4495 }
4496
4497 /* Pack LOD */
4498 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4499 instr->op == nir_texop_txf)) {
4500 address[count++] = lod;
4501 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4502 address[count++] = sample_index;
4503 } else if(instr->op == nir_texop_txs) {
4504 count = 0;
4505 if (lod)
4506 address[count++] = lod;
4507 else
4508 address[count++] = ctx->i32zero;
4509 }
4510
4511 for (chan = 0; chan < count; chan++) {
4512 address[chan] = LLVMBuildBitCast(ctx->builder,
4513 address[chan], ctx->i32, "");
4514 }
4515
4516 if (instr->op == nir_texop_samples_identical) {
4517 LLVMValueRef txf_address[4];
4518 struct ac_image_args txf_args = { 0 };
4519 unsigned txf_count = count;
4520 memcpy(txf_address, address, sizeof(txf_address));
4521
4522 if (!instr->is_array)
4523 txf_address[2] = ctx->i32zero;
4524 txf_address[3] = ctx->i32zero;
4525
4526 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4527 fmask_ptr, NULL,
4528 txf_address, txf_count, 0xf);
4529
4530 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4531
4532 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4533 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->i32zero);
4534 goto write_result;
4535 }
4536
4537 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4538 instr->op != nir_texop_txs) {
4539 unsigned sample_chan = instr->is_array ? 3 : 2;
4540 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4541 address[0],
4542 address[1],
4543 instr->is_array ? address[2] : NULL,
4544 address[sample_chan],
4545 fmask_ptr);
4546 }
4547
4548 if (offsets && instr->op == nir_texop_txf) {
4549 nir_const_value *const_offset =
4550 nir_src_as_const_value(instr->src[const_src].src);
4551 int num_offsets = instr->src[const_src].src.ssa->num_components;
4552 assert(const_offset);
4553 num_offsets = MIN2(num_offsets, instr->coord_components);
4554 if (num_offsets > 2)
4555 address[2] = LLVMBuildAdd(ctx->builder,
4556 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4557 if (num_offsets > 1)
4558 address[1] = LLVMBuildAdd(ctx->builder,
4559 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4560 address[0] = LLVMBuildAdd(ctx->builder,
4561 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4562
4563 }
4564
4565 /* TODO TG4 support */
4566 if (instr->op == nir_texop_tg4) {
4567 if (instr->is_shadow)
4568 dmask = 1;
4569 else
4570 dmask = 1 << instr->component;
4571 }
4572 set_tex_fetch_args(ctx, &args, instr, instr->op,
4573 res_ptr, samp_ptr, address, count, dmask);
4574
4575 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4576
4577 if (instr->op == nir_texop_query_levels)
4578 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4579 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4580 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4581 else if (instr->op == nir_texop_txs &&
4582 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4583 instr->is_array) {
4584 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4585 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4586 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4587 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4588 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4589 } else if (instr->dest.ssa.num_components != 4)
4590 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4591
4592 write_result:
4593 if (result) {
4594 assert(instr->dest.is_ssa);
4595 result = to_integer(&ctx->ac, result);
4596 _mesa_hash_table_insert(ctx->nir->defs, &instr->dest.ssa, result);
4597 }
4598 }
4599
4600
4601 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4602 {
4603 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4604 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4605
4606 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4607 _mesa_hash_table_insert(ctx->phis, instr, result);
4608 }
4609
4610 static void visit_post_phi(struct ac_nir_context *ctx,
4611 nir_phi_instr *instr,
4612 LLVMValueRef llvm_phi)
4613 {
4614 nir_foreach_phi_src(src, instr) {
4615 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4616 LLVMValueRef llvm_src = get_src(ctx, src->src);
4617
4618 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4619 }
4620 }
4621
4622 static void phi_post_pass(struct ac_nir_context *ctx)
4623 {
4624 struct hash_entry *entry;
4625 hash_table_foreach(ctx->phis, entry) {
4626 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4627 (LLVMValueRef)entry->data);
4628 }
4629 }
4630
4631
4632 static void visit_ssa_undef(struct ac_nir_context *ctx,
4633 const nir_ssa_undef_instr *instr)
4634 {
4635 unsigned num_components = instr->def.num_components;
4636 LLVMValueRef undef;
4637
4638 if (num_components == 1)
4639 undef = LLVMGetUndef(ctx->ac.i32);
4640 else {
4641 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4642 }
4643 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4644 }
4645
4646 static void visit_jump(struct ac_nir_context *ctx,
4647 const nir_jump_instr *instr)
4648 {
4649 switch (instr->type) {
4650 case nir_jump_break:
4651 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4652 LLVMClearInsertionPosition(ctx->ac.builder);
4653 break;
4654 case nir_jump_continue:
4655 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4656 LLVMClearInsertionPosition(ctx->ac.builder);
4657 break;
4658 default:
4659 fprintf(stderr, "Unknown NIR jump instr: ");
4660 nir_print_instr(&instr->instr, stderr);
4661 fprintf(stderr, "\n");
4662 abort();
4663 }
4664 }
4665
4666 static void visit_cf_list(struct ac_nir_context *ctx,
4667 struct exec_list *list);
4668
4669 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4670 {
4671 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4672 nir_foreach_instr(instr, block)
4673 {
4674 switch (instr->type) {
4675 case nir_instr_type_alu:
4676 visit_alu(ctx, nir_instr_as_alu(instr));
4677 break;
4678 case nir_instr_type_load_const:
4679 visit_load_const(ctx, nir_instr_as_load_const(instr));
4680 break;
4681 case nir_instr_type_intrinsic:
4682 visit_intrinsic(ctx->nctx, nir_instr_as_intrinsic(instr));
4683 break;
4684 case nir_instr_type_tex:
4685 visit_tex(ctx->nctx, nir_instr_as_tex(instr));
4686 break;
4687 case nir_instr_type_phi:
4688 visit_phi(ctx, nir_instr_as_phi(instr));
4689 break;
4690 case nir_instr_type_ssa_undef:
4691 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4692 break;
4693 case nir_instr_type_jump:
4694 visit_jump(ctx, nir_instr_as_jump(instr));
4695 break;
4696 default:
4697 fprintf(stderr, "Unknown NIR instr type: ");
4698 nir_print_instr(instr, stderr);
4699 fprintf(stderr, "\n");
4700 abort();
4701 }
4702 }
4703
4704 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4705 }
4706
4707 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4708 {
4709 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4710
4711 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4712 LLVMBasicBlockRef merge_block =
4713 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4714 LLVMBasicBlockRef if_block =
4715 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4716 LLVMBasicBlockRef else_block = merge_block;
4717 if (!exec_list_is_empty(&if_stmt->else_list))
4718 else_block = LLVMAppendBasicBlockInContext(
4719 ctx->ac.context, fn, "");
4720
4721 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4722 LLVMConstInt(ctx->ac.i32, 0, false), "");
4723 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4724
4725 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4726 visit_cf_list(ctx, &if_stmt->then_list);
4727 if (LLVMGetInsertBlock(ctx->ac.builder))
4728 LLVMBuildBr(ctx->ac.builder, merge_block);
4729
4730 if (!exec_list_is_empty(&if_stmt->else_list)) {
4731 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4732 visit_cf_list(ctx, &if_stmt->else_list);
4733 if (LLVMGetInsertBlock(ctx->ac.builder))
4734 LLVMBuildBr(ctx->ac.builder, merge_block);
4735 }
4736
4737 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4738 }
4739
4740 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4741 {
4742 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4743 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4744 LLVMBasicBlockRef break_parent = ctx->break_block;
4745
4746 ctx->continue_block =
4747 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4748 ctx->break_block =
4749 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4750
4751 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4752 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4753 visit_cf_list(ctx, &loop->body);
4754
4755 if (LLVMGetInsertBlock(ctx->ac.builder))
4756 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4757 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4758
4759 ctx->continue_block = continue_parent;
4760 ctx->break_block = break_parent;
4761 }
4762
4763 static void visit_cf_list(struct ac_nir_context *ctx,
4764 struct exec_list *list)
4765 {
4766 foreach_list_typed(nir_cf_node, node, node, list)
4767 {
4768 switch (node->type) {
4769 case nir_cf_node_block:
4770 visit_block(ctx, nir_cf_node_as_block(node));
4771 break;
4772
4773 case nir_cf_node_if:
4774 visit_if(ctx, nir_cf_node_as_if(node));
4775 break;
4776
4777 case nir_cf_node_loop:
4778 visit_loop(ctx, nir_cf_node_as_loop(node));
4779 break;
4780
4781 default:
4782 assert(0);
4783 }
4784 }
4785 }
4786
4787 static void
4788 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4789 struct nir_variable *variable)
4790 {
4791 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4792 LLVMValueRef t_offset;
4793 LLVMValueRef t_list;
4794 LLVMValueRef input;
4795 LLVMValueRef buffer_index;
4796 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4797 int idx = variable->data.location;
4798 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4799
4800 variable->data.driver_location = idx * 4;
4801
4802 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4803 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4804 ctx->abi.start_instance, "");
4805 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4806 ctx->shader_info->vs.vgpr_comp_cnt);
4807 } else
4808 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4809 ctx->abi.base_vertex, "");
4810
4811 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4812 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4813
4814 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4815
4816 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4817 buffer_index,
4818 LLVMConstInt(ctx->i32, 0, false),
4819 true);
4820
4821 for (unsigned chan = 0; chan < 4; chan++) {
4822 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4823 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4824 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4825 input, llvm_chan, ""));
4826 }
4827 }
4828 }
4829
4830 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4831 unsigned attr,
4832 LLVMValueRef interp_param,
4833 LLVMValueRef prim_mask,
4834 LLVMValueRef result[4])
4835 {
4836 LLVMValueRef attr_number;
4837 unsigned chan;
4838 LLVMValueRef i, j;
4839 bool interp = interp_param != NULL;
4840
4841 attr_number = LLVMConstInt(ctx->i32, attr, false);
4842
4843 /* fs.constant returns the param from the middle vertex, so it's not
4844 * really useful for flat shading. It's meant to be used for custom
4845 * interpolation (but the intrinsic can't fetch from the other two
4846 * vertices).
4847 *
4848 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4849 * to do the right thing. The only reason we use fs.constant is that
4850 * fs.interp cannot be used on integers, because they can be equal
4851 * to NaN.
4852 */
4853 if (interp) {
4854 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4855 LLVMVectorType(ctx->f32, 2), "");
4856
4857 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4858 ctx->i32zero, "");
4859 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4860 ctx->i32one, "");
4861 }
4862
4863 for (chan = 0; chan < 4; chan++) {
4864 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4865
4866 if (interp) {
4867 result[chan] = ac_build_fs_interp(&ctx->ac,
4868 llvm_chan,
4869 attr_number,
4870 prim_mask, i, j);
4871 } else {
4872 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4873 LLVMConstInt(ctx->i32, 2, false),
4874 llvm_chan,
4875 attr_number,
4876 prim_mask);
4877 }
4878 }
4879 }
4880
4881 static void
4882 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4883 struct nir_variable *variable)
4884 {
4885 int idx = variable->data.location;
4886 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4887 LLVMValueRef interp;
4888
4889 variable->data.driver_location = idx * 4;
4890 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4891
4892 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4893 unsigned interp_type;
4894 if (variable->data.sample) {
4895 interp_type = INTERP_SAMPLE;
4896 ctx->shader_info->fs.force_persample = true;
4897 } else if (variable->data.centroid)
4898 interp_type = INTERP_CENTROID;
4899 else
4900 interp_type = INTERP_CENTER;
4901
4902 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4903 } else
4904 interp = NULL;
4905
4906 for (unsigned i = 0; i < attrib_count; ++i)
4907 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4908
4909 }
4910
4911 static void
4912 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4913 struct nir_variable *variable)
4914 {
4915 switch (ctx->stage) {
4916 case MESA_SHADER_VERTEX:
4917 handle_vs_input_decl(ctx, variable);
4918 break;
4919 case MESA_SHADER_FRAGMENT:
4920 handle_fs_input_decl(ctx, variable);
4921 break;
4922 default:
4923 break;
4924 }
4925
4926 }
4927
4928 static void
4929 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4930 struct nir_shader *nir)
4931 {
4932 unsigned index = 0;
4933 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4934 LLVMValueRef interp_param;
4935 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4936
4937 if (!(ctx->input_mask & (1ull << i)))
4938 continue;
4939
4940 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4941 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4942 interp_param = *inputs;
4943 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4944 inputs);
4945
4946 if (!interp_param)
4947 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4948 ++index;
4949 } else if (i == VARYING_SLOT_POS) {
4950 for(int i = 0; i < 3; ++i)
4951 inputs[i] = ctx->frag_pos[i];
4952
4953 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4954 }
4955 }
4956 ctx->shader_info->fs.num_interp = index;
4957 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4958 ctx->shader_info->fs.has_pcoord = true;
4959 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4960 ctx->shader_info->fs.prim_id_input = true;
4961 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4962 ctx->shader_info->fs.layer_input = true;
4963 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4964 }
4965
4966 static LLVMValueRef
4967 ac_build_alloca(struct nir_to_llvm_context *ctx,
4968 LLVMTypeRef type,
4969 const char *name)
4970 {
4971 LLVMBuilderRef builder = ctx->builder;
4972 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4973 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4974 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4975 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4976 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4977 LLVMValueRef res;
4978
4979 if (first_instr) {
4980 LLVMPositionBuilderBefore(first_builder, first_instr);
4981 } else {
4982 LLVMPositionBuilderAtEnd(first_builder, first_block);
4983 }
4984
4985 res = LLVMBuildAlloca(first_builder, type, name);
4986 LLVMBuildStore(builder, LLVMConstNull(type), res);
4987
4988 LLVMDisposeBuilder(first_builder);
4989
4990 return res;
4991 }
4992
4993 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4994 LLVMTypeRef type,
4995 const char *name)
4996 {
4997 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4998 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4999 return ptr;
5000 }
5001
5002 static void
5003 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
5004 struct nir_variable *variable)
5005 {
5006 int idx = variable->data.location + variable->data.index;
5007 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5008 uint64_t mask_attribs;
5009 variable->data.driver_location = idx * 4;
5010
5011 /* tess ctrl has it's own load/store paths for outputs */
5012 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5013 return;
5014
5015 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5016 if (ctx->stage == MESA_SHADER_VERTEX ||
5017 ctx->stage == MESA_SHADER_TESS_EVAL ||
5018 ctx->stage == MESA_SHADER_GEOMETRY) {
5019 if (idx == VARYING_SLOT_CLIP_DIST0) {
5020 int length = ctx->num_output_clips + ctx->num_output_culls;
5021 if (ctx->stage == MESA_SHADER_VERTEX) {
5022 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5023 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5024 }
5025 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5026 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5027 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5028 }
5029
5030 if (length > 4)
5031 attrib_count = 2;
5032 else
5033 attrib_count = 1;
5034 mask_attribs = 1ull << idx;
5035 }
5036 }
5037
5038 for (unsigned i = 0; i < attrib_count; ++i) {
5039 for (unsigned chan = 0; chan < 4; chan++) {
5040 ctx->nir->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
5041 si_build_alloca_undef(ctx, ctx->f32, "");
5042 }
5043 }
5044 ctx->output_mask |= mask_attribs;
5045 }
5046
5047 static LLVMTypeRef
5048 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5049 enum glsl_base_type type)
5050 {
5051 switch (type) {
5052 case GLSL_TYPE_INT:
5053 case GLSL_TYPE_UINT:
5054 case GLSL_TYPE_BOOL:
5055 case GLSL_TYPE_SUBROUTINE:
5056 return ctx->i32;
5057 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5058 return ctx->f32;
5059 case GLSL_TYPE_INT64:
5060 case GLSL_TYPE_UINT64:
5061 return ctx->i64;
5062 case GLSL_TYPE_DOUBLE:
5063 return ctx->f64;
5064 default:
5065 unreachable("unknown GLSL type");
5066 }
5067 }
5068
5069 static LLVMTypeRef
5070 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5071 const struct glsl_type *type)
5072 {
5073 if (glsl_type_is_scalar(type)) {
5074 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5075 }
5076
5077 if (glsl_type_is_vector(type)) {
5078 return LLVMVectorType(
5079 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5080 glsl_get_vector_elements(type));
5081 }
5082
5083 if (glsl_type_is_matrix(type)) {
5084 return LLVMArrayType(
5085 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5086 glsl_get_matrix_columns(type));
5087 }
5088
5089 if (glsl_type_is_array(type)) {
5090 return LLVMArrayType(
5091 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5092 glsl_get_length(type));
5093 }
5094
5095 assert(glsl_type_is_struct(type));
5096
5097 LLVMTypeRef member_types[glsl_get_length(type)];
5098
5099 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5100 member_types[i] =
5101 glsl_to_llvm_type(ctx,
5102 glsl_get_struct_field(type, i));
5103 }
5104
5105 return LLVMStructTypeInContext(ctx->context, member_types,
5106 glsl_get_length(type), false);
5107 }
5108
5109 static void
5110 setup_locals(struct ac_nir_context *ctx,
5111 struct nir_function *func)
5112 {
5113 int i, j;
5114 ctx->num_locals = 0;
5115 nir_foreach_variable(variable, &func->impl->locals) {
5116 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5117 variable->data.driver_location = ctx->num_locals * 4;
5118 ctx->num_locals += attrib_count;
5119 }
5120 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5121 if (!ctx->locals)
5122 return;
5123
5124 for (i = 0; i < ctx->num_locals; i++) {
5125 for (j = 0; j < 4; j++) {
5126 ctx->locals[i * 4 + j] =
5127 si_build_alloca_undef(ctx->nctx, ctx->ac.f32, "temp");
5128 }
5129 }
5130 }
5131
5132 static void
5133 setup_shared(struct ac_nir_context *ctx,
5134 struct nir_shader *nir)
5135 {
5136 nir_foreach_variable(variable, &nir->shared) {
5137 LLVMValueRef shared =
5138 LLVMAddGlobalInAddressSpace(
5139 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5140 variable->name ? variable->name : "",
5141 LOCAL_ADDR_SPACE);
5142 _mesa_hash_table_insert(ctx->vars, variable, shared);
5143 }
5144 }
5145
5146 static LLVMValueRef
5147 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5148 {
5149 v = to_float(ctx, v);
5150 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5151 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5152 }
5153
5154
5155 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5156 LLVMValueRef src0, LLVMValueRef src1)
5157 {
5158 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5159 LLVMValueRef comp[2];
5160
5161 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5162 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5163 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5164 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5165 }
5166
5167 /* Initialize arguments for the shader export intrinsic */
5168 static void
5169 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5170 LLVMValueRef *values,
5171 unsigned target,
5172 struct ac_export_args *args)
5173 {
5174 /* Default is 0xf. Adjusted below depending on the format. */
5175 args->enabled_channels = 0xf;
5176
5177 /* Specify whether the EXEC mask represents the valid mask */
5178 args->valid_mask = 0;
5179
5180 /* Specify whether this is the last export */
5181 args->done = 0;
5182
5183 /* Specify the target we are exporting */
5184 args->target = target;
5185
5186 args->compr = false;
5187 args->out[0] = LLVMGetUndef(ctx->f32);
5188 args->out[1] = LLVMGetUndef(ctx->f32);
5189 args->out[2] = LLVMGetUndef(ctx->f32);
5190 args->out[3] = LLVMGetUndef(ctx->f32);
5191
5192 if (!values)
5193 return;
5194
5195 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5196 LLVMValueRef val[4];
5197 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5198 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5199 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5200
5201 switch(col_format) {
5202 case V_028714_SPI_SHADER_ZERO:
5203 args->enabled_channels = 0; /* writemask */
5204 args->target = V_008DFC_SQ_EXP_NULL;
5205 break;
5206
5207 case V_028714_SPI_SHADER_32_R:
5208 args->enabled_channels = 1;
5209 args->out[0] = values[0];
5210 break;
5211
5212 case V_028714_SPI_SHADER_32_GR:
5213 args->enabled_channels = 0x3;
5214 args->out[0] = values[0];
5215 args->out[1] = values[1];
5216 break;
5217
5218 case V_028714_SPI_SHADER_32_AR:
5219 args->enabled_channels = 0x9;
5220 args->out[0] = values[0];
5221 args->out[3] = values[3];
5222 break;
5223
5224 case V_028714_SPI_SHADER_FP16_ABGR:
5225 args->compr = 1;
5226
5227 for (unsigned chan = 0; chan < 2; chan++) {
5228 LLVMValueRef pack_args[2] = {
5229 values[2 * chan],
5230 values[2 * chan + 1]
5231 };
5232 LLVMValueRef packed;
5233
5234 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5235 args->out[chan] = packed;
5236 }
5237 break;
5238
5239 case V_028714_SPI_SHADER_UNORM16_ABGR:
5240 for (unsigned chan = 0; chan < 4; chan++) {
5241 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5242 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5243 LLVMConstReal(ctx->f32, 65535), "");
5244 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5245 LLVMConstReal(ctx->f32, 0.5), "");
5246 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5247 ctx->i32, "");
5248 }
5249
5250 args->compr = 1;
5251 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5252 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5253 break;
5254
5255 case V_028714_SPI_SHADER_SNORM16_ABGR:
5256 for (unsigned chan = 0; chan < 4; chan++) {
5257 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5258 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5259 LLVMConstReal(ctx->f32, 32767), "");
5260
5261 /* If positive, add 0.5, else add -0.5. */
5262 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5263 LLVMBuildSelect(ctx->builder,
5264 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5265 val[chan], ctx->f32zero, ""),
5266 LLVMConstReal(ctx->f32, 0.5),
5267 LLVMConstReal(ctx->f32, -0.5), ""), "");
5268 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5269 }
5270
5271 args->compr = 1;
5272 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5273 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5274 break;
5275
5276 case V_028714_SPI_SHADER_UINT16_ABGR: {
5277 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5278
5279 for (unsigned chan = 0; chan < 4; chan++) {
5280 val[chan] = to_integer(&ctx->ac, values[chan]);
5281 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5282 }
5283
5284 args->compr = 1;
5285 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5286 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5287 break;
5288 }
5289
5290 case V_028714_SPI_SHADER_SINT16_ABGR: {
5291 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5292 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5293
5294 /* Clamp. */
5295 for (unsigned chan = 0; chan < 4; chan++) {
5296 val[chan] = to_integer(&ctx->ac, values[chan]);
5297 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5298 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5299 }
5300
5301 args->compr = 1;
5302 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5303 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5304 break;
5305 }
5306
5307 default:
5308 case V_028714_SPI_SHADER_32_ABGR:
5309 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5310 break;
5311 }
5312 } else
5313 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5314
5315 for (unsigned i = 0; i < 4; ++i)
5316 args->out[i] = to_float(&ctx->ac, args->out[i]);
5317 }
5318
5319 static void
5320 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5321 bool export_prim_id,
5322 struct ac_vs_output_info *outinfo)
5323 {
5324 uint32_t param_count = 0;
5325 unsigned target;
5326 unsigned pos_idx, num_pos_exports = 0;
5327 struct ac_export_args args, pos_args[4] = {};
5328 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5329 int i;
5330
5331 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5332 sizeof(outinfo->vs_output_param_offset));
5333
5334 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5335 LLVMValueRef slots[8];
5336 unsigned j;
5337
5338 if (outinfo->cull_dist_mask)
5339 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5340
5341 i = VARYING_SLOT_CLIP_DIST0;
5342 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5343 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5344 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5345
5346 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5347 slots[i] = LLVMGetUndef(ctx->f32);
5348
5349 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5350 target = V_008DFC_SQ_EXP_POS + 3;
5351 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5352 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5353 &args, sizeof(args));
5354 }
5355
5356 target = V_008DFC_SQ_EXP_POS + 2;
5357 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5358 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5359 &args, sizeof(args));
5360
5361 }
5362
5363 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5364 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5365 for (unsigned j = 0; j < 4; j++)
5366 pos_values[j] = LLVMBuildLoad(ctx->builder,
5367 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5368 }
5369 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5370
5371 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5372 outinfo->writes_pointsize = true;
5373 psize_value = LLVMBuildLoad(ctx->builder,
5374 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5375 }
5376
5377 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5378 outinfo->writes_layer = true;
5379 layer_value = LLVMBuildLoad(ctx->builder,
5380 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5381 }
5382
5383 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5384 outinfo->writes_viewport_index = true;
5385 viewport_index_value = LLVMBuildLoad(ctx->builder,
5386 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5387 }
5388
5389 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5390 (outinfo->writes_layer == true ? 4 : 0) |
5391 (outinfo->writes_viewport_index == true ? 8 : 0));
5392 if (mask) {
5393 pos_args[1].enabled_channels = mask;
5394 pos_args[1].valid_mask = 0;
5395 pos_args[1].done = 0;
5396 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5397 pos_args[1].compr = 0;
5398 pos_args[1].out[0] = ctx->f32zero; /* X */
5399 pos_args[1].out[1] = ctx->f32zero; /* Y */
5400 pos_args[1].out[2] = ctx->f32zero; /* Z */
5401 pos_args[1].out[3] = ctx->f32zero; /* W */
5402
5403 if (outinfo->writes_pointsize == true)
5404 pos_args[1].out[0] = psize_value;
5405 if (outinfo->writes_layer == true)
5406 pos_args[1].out[2] = layer_value;
5407 if (outinfo->writes_viewport_index == true)
5408 pos_args[1].out[3] = viewport_index_value;
5409 }
5410 for (i = 0; i < 4; i++) {
5411 if (pos_args[i].out[0])
5412 num_pos_exports++;
5413 }
5414
5415 pos_idx = 0;
5416 for (i = 0; i < 4; i++) {
5417 if (!pos_args[i].out[0])
5418 continue;
5419
5420 /* Specify the target we are exporting */
5421 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5422 if (pos_idx == num_pos_exports)
5423 pos_args[i].done = 1;
5424 ac_build_export(&ctx->ac, &pos_args[i]);
5425 }
5426
5427 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5428 LLVMValueRef values[4];
5429 if (!(ctx->output_mask & (1ull << i)))
5430 continue;
5431
5432 for (unsigned j = 0; j < 4; j++)
5433 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5434 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5435
5436 if (i == VARYING_SLOT_LAYER) {
5437 target = V_008DFC_SQ_EXP_PARAM + param_count;
5438 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5439 param_count++;
5440 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5441 target = V_008DFC_SQ_EXP_PARAM + param_count;
5442 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5443 param_count++;
5444 } else if (i >= VARYING_SLOT_VAR0) {
5445 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5446 target = V_008DFC_SQ_EXP_PARAM + param_count;
5447 outinfo->vs_output_param_offset[i] = param_count;
5448 param_count++;
5449 } else
5450 continue;
5451
5452 si_llvm_init_export_args(ctx, values, target, &args);
5453
5454 if (target >= V_008DFC_SQ_EXP_POS &&
5455 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5456 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5457 &args, sizeof(args));
5458 } else {
5459 ac_build_export(&ctx->ac, &args);
5460 }
5461 }
5462
5463 if (export_prim_id) {
5464 LLVMValueRef values[4];
5465 target = V_008DFC_SQ_EXP_PARAM + param_count;
5466 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5467 param_count++;
5468
5469 values[0] = ctx->vs_prim_id;
5470 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5471 ctx->shader_info->vs.vgpr_comp_cnt);
5472 for (unsigned j = 1; j < 4; j++)
5473 values[j] = ctx->f32zero;
5474 si_llvm_init_export_args(ctx, values, target, &args);
5475 ac_build_export(&ctx->ac, &args);
5476 outinfo->export_prim_id = true;
5477 }
5478
5479 outinfo->pos_exports = num_pos_exports;
5480 outinfo->param_exports = param_count;
5481 }
5482
5483 static void
5484 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5485 struct ac_es_output_info *outinfo)
5486 {
5487 int j;
5488 uint64_t max_output_written = 0;
5489 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5490 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5491 int param_index;
5492 int length = 4;
5493
5494 if (!(ctx->output_mask & (1ull << i)))
5495 continue;
5496
5497 if (i == VARYING_SLOT_CLIP_DIST0)
5498 length = ctx->num_output_clips + ctx->num_output_culls;
5499
5500 param_index = shader_io_get_unique_index(i);
5501
5502 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5503
5504 for (j = 0; j < length; j++) {
5505 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5506 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5507
5508 ac_build_buffer_store_dword(&ctx->ac,
5509 ctx->esgs_ring,
5510 out_val, 1,
5511 NULL, ctx->es2gs_offset,
5512 (4 * param_index + j) * 4,
5513 1, 1, true, true);
5514 }
5515 }
5516 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5517 }
5518
5519 static void
5520 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5521 {
5522 LLVMValueRef vertex_id = ctx->rel_auto_id;
5523 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5524 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5525 vertex_dw_stride, "");
5526
5527 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5528 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5529 int length = 4;
5530
5531 if (!(ctx->output_mask & (1ull << i)))
5532 continue;
5533
5534 if (i == VARYING_SLOT_CLIP_DIST0)
5535 length = ctx->num_output_clips + ctx->num_output_culls;
5536 int param = shader_io_get_unique_index(i);
5537 mark_tess_output(ctx, false, param);
5538 if (length > 4)
5539 mark_tess_output(ctx, false, param + 1);
5540 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5541 LLVMConstInt(ctx->i32, param * 4, false),
5542 "");
5543 for (unsigned j = 0; j < length; j++) {
5544 lds_store(ctx, dw_addr,
5545 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5546 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5547 }
5548 }
5549 }
5550
5551 struct ac_build_if_state
5552 {
5553 struct nir_to_llvm_context *ctx;
5554 LLVMValueRef condition;
5555 LLVMBasicBlockRef entry_block;
5556 LLVMBasicBlockRef true_block;
5557 LLVMBasicBlockRef false_block;
5558 LLVMBasicBlockRef merge_block;
5559 };
5560
5561 static LLVMBasicBlockRef
5562 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5563 {
5564 LLVMBasicBlockRef current_block;
5565 LLVMBasicBlockRef next_block;
5566 LLVMBasicBlockRef new_block;
5567
5568 /* get current basic block */
5569 current_block = LLVMGetInsertBlock(ctx->builder);
5570
5571 /* chqeck if there's another block after this one */
5572 next_block = LLVMGetNextBasicBlock(current_block);
5573 if (next_block) {
5574 /* insert the new block before the next block */
5575 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5576 }
5577 else {
5578 /* append new block after current block */
5579 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5580 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5581 }
5582 return new_block;
5583 }
5584
5585 static void
5586 ac_nir_build_if(struct ac_build_if_state *ifthen,
5587 struct nir_to_llvm_context *ctx,
5588 LLVMValueRef condition)
5589 {
5590 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5591
5592 memset(ifthen, 0, sizeof *ifthen);
5593 ifthen->ctx = ctx;
5594 ifthen->condition = condition;
5595 ifthen->entry_block = block;
5596
5597 /* create endif/merge basic block for the phi functions */
5598 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5599
5600 /* create/insert true_block before merge_block */
5601 ifthen->true_block =
5602 LLVMInsertBasicBlockInContext(ctx->context,
5603 ifthen->merge_block,
5604 "if-true-block");
5605
5606 /* successive code goes into the true block */
5607 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5608 }
5609
5610 /**
5611 * End a conditional.
5612 */
5613 static void
5614 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5615 {
5616 LLVMBuilderRef builder = ifthen->ctx->builder;
5617
5618 /* Insert branch to the merge block from current block */
5619 LLVMBuildBr(builder, ifthen->merge_block);
5620
5621 /*
5622 * Now patch in the various branch instructions.
5623 */
5624
5625 /* Insert the conditional branch instruction at the end of entry_block */
5626 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5627 if (ifthen->false_block) {
5628 /* we have an else clause */
5629 LLVMBuildCondBr(builder, ifthen->condition,
5630 ifthen->true_block, ifthen->false_block);
5631 }
5632 else {
5633 /* no else clause */
5634 LLVMBuildCondBr(builder, ifthen->condition,
5635 ifthen->true_block, ifthen->merge_block);
5636 }
5637
5638 /* Resume building code at end of the ifthen->merge_block */
5639 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5640 }
5641
5642 static void
5643 write_tess_factors(struct nir_to_llvm_context *ctx)
5644 {
5645 unsigned stride, outer_comps, inner_comps;
5646 struct ac_build_if_state if_ctx, inner_if_ctx;
5647 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5648 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5649 unsigned tess_inner_index, tess_outer_index;
5650 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5651 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5652 int i;
5653 emit_barrier(ctx);
5654
5655 switch (ctx->options->key.tcs.primitive_mode) {
5656 case GL_ISOLINES:
5657 stride = 2;
5658 outer_comps = 2;
5659 inner_comps = 0;
5660 break;
5661 case GL_TRIANGLES:
5662 stride = 4;
5663 outer_comps = 3;
5664 inner_comps = 1;
5665 break;
5666 case GL_QUADS:
5667 stride = 6;
5668 outer_comps = 4;
5669 inner_comps = 2;
5670 break;
5671 default:
5672 return;
5673 }
5674
5675 ac_nir_build_if(&if_ctx, ctx,
5676 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5677 invocation_id, ctx->i32zero, ""));
5678
5679 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5680 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5681
5682 mark_tess_output(ctx, true, tess_inner_index);
5683 mark_tess_output(ctx, true, tess_outer_index);
5684 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5685 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5686 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5687 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5688 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5689
5690 for (i = 0; i < 4; i++) {
5691 inner[i] = LLVMGetUndef(ctx->i32);
5692 outer[i] = LLVMGetUndef(ctx->i32);
5693 }
5694
5695 // LINES reverseal
5696 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5697 outer[0] = out[1] = lds_load(ctx, lds_outer);
5698 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5699 LLVMConstInt(ctx->i32, 1, false), "");
5700 outer[1] = out[0] = lds_load(ctx, lds_outer);
5701 } else {
5702 for (i = 0; i < outer_comps; i++) {
5703 outer[i] = out[i] =
5704 lds_load(ctx, lds_outer);
5705 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5706 LLVMConstInt(ctx->i32, 1, false), "");
5707 }
5708 for (i = 0; i < inner_comps; i++) {
5709 inner[i] = out[outer_comps+i] =
5710 lds_load(ctx, lds_inner);
5711 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5712 LLVMConstInt(ctx->i32, 1, false), "");
5713 }
5714 }
5715
5716 /* Convert the outputs to vectors for stores. */
5717 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5718 vec1 = NULL;
5719
5720 if (stride > 4)
5721 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5722
5723
5724 buffer = ctx->hs_ring_tess_factor;
5725 tf_base = ctx->tess_factor_offset;
5726 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5727 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5728
5729 ac_nir_build_if(&inner_if_ctx, ctx,
5730 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5731 rel_patch_id, ctx->i32zero, ""));
5732
5733 /* Store the dynamic HS control word. */
5734 ac_build_buffer_store_dword(&ctx->ac, buffer,
5735 LLVMConstInt(ctx->i32, 0x80000000, false),
5736 1, ctx->i32zero, tf_base,
5737 0, 1, 0, true, false);
5738 ac_nir_build_endif(&inner_if_ctx);
5739
5740 /* Store the tessellation factors. */
5741 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5742 MIN2(stride, 4), byteoffset, tf_base,
5743 4, 1, 0, true, false);
5744 if (vec1)
5745 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5746 stride - 4, byteoffset, tf_base,
5747 20, 1, 0, true, false);
5748
5749 //TODO store to offchip for TES to read - only if TES reads them
5750 if (1) {
5751 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5752 LLVMValueRef tf_inner_offset;
5753 unsigned param_outer, param_inner;
5754
5755 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5756 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5757 LLVMConstInt(ctx->i32, param_outer, 0));
5758
5759 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5760 util_next_power_of_two(outer_comps));
5761
5762 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5763 outer_comps, tf_outer_offset,
5764 ctx->oc_lds, 0, 1, 0, true, false);
5765 if (inner_comps) {
5766 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5767 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5768 LLVMConstInt(ctx->i32, param_inner, 0));
5769
5770 inner_vec = inner_comps == 1 ? inner[0] :
5771 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5772 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5773 inner_comps, tf_inner_offset,
5774 ctx->oc_lds, 0, 1, 0, true, false);
5775 }
5776 }
5777 ac_nir_build_endif(&if_ctx);
5778 }
5779
5780 static void
5781 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5782 {
5783 write_tess_factors(ctx);
5784 }
5785
5786 static bool
5787 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5788 LLVMValueRef *color, unsigned param, bool is_last,
5789 struct ac_export_args *args)
5790 {
5791 /* Export */
5792 si_llvm_init_export_args(ctx, color, param,
5793 args);
5794
5795 if (is_last) {
5796 args->valid_mask = 1; /* whether the EXEC mask is valid */
5797 args->done = 1; /* DONE bit */
5798 } else if (!args->enabled_channels)
5799 return false; /* unnecessary NULL export */
5800
5801 return true;
5802 }
5803
5804 static void
5805 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5806 LLVMValueRef depth, LLVMValueRef stencil,
5807 LLVMValueRef samplemask)
5808 {
5809 struct ac_export_args args;
5810
5811 args.enabled_channels = 0;
5812 args.valid_mask = 1;
5813 args.done = 1;
5814 args.target = V_008DFC_SQ_EXP_MRTZ;
5815 args.compr = false;
5816
5817 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5818 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5819 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5820 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5821
5822 if (depth) {
5823 args.out[0] = depth;
5824 args.enabled_channels |= 0x1;
5825 }
5826
5827 if (stencil) {
5828 args.out[1] = stencil;
5829 args.enabled_channels |= 0x2;
5830 }
5831
5832 if (samplemask) {
5833 args.out[2] = samplemask;
5834 args.enabled_channels |= 0x4;
5835 }
5836
5837 /* SI (except OLAND and HAINAN) has a bug that it only looks
5838 * at the X writemask component. */
5839 if (ctx->options->chip_class == SI &&
5840 ctx->options->family != CHIP_OLAND &&
5841 ctx->options->family != CHIP_HAINAN)
5842 args.enabled_channels |= 0x1;
5843
5844 ac_build_export(&ctx->ac, &args);
5845 }
5846
5847 static void
5848 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5849 {
5850 unsigned index = 0;
5851 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5852 struct ac_export_args color_args[8];
5853
5854 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5855 LLVMValueRef values[4];
5856
5857 if (!(ctx->output_mask & (1ull << i)))
5858 continue;
5859
5860 if (i == FRAG_RESULT_DEPTH) {
5861 ctx->shader_info->fs.writes_z = true;
5862 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5863 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5864 } else if (i == FRAG_RESULT_STENCIL) {
5865 ctx->shader_info->fs.writes_stencil = true;
5866 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5867 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5868 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5869 ctx->shader_info->fs.writes_sample_mask = true;
5870 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5871 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5872 } else {
5873 bool last = false;
5874 for (unsigned j = 0; j < 4; j++)
5875 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5876 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5877
5878 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5879 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5880
5881 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5882 if (ret)
5883 index++;
5884 }
5885 }
5886
5887 for (unsigned i = 0; i < index; i++)
5888 ac_build_export(&ctx->ac, &color_args[i]);
5889 if (depth || stencil || samplemask)
5890 si_export_mrt_z(ctx, depth, stencil, samplemask);
5891 else if (!index) {
5892 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5893 ac_build_export(&ctx->ac, &color_args[0]);
5894 }
5895
5896 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5897 }
5898
5899 static void
5900 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5901 {
5902 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5903 }
5904
5905 static void
5906 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5907 {
5908 switch (ctx->stage) {
5909 case MESA_SHADER_VERTEX:
5910 if (ctx->options->key.vs.as_ls)
5911 handle_ls_outputs_post(ctx);
5912 else if (ctx->options->key.vs.as_es)
5913 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5914 else
5915 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5916 &ctx->shader_info->vs.outinfo);
5917 break;
5918 case MESA_SHADER_FRAGMENT:
5919 handle_fs_outputs_post(ctx);
5920 break;
5921 case MESA_SHADER_GEOMETRY:
5922 emit_gs_epilogue(ctx);
5923 break;
5924 case MESA_SHADER_TESS_CTRL:
5925 handle_tcs_outputs_post(ctx);
5926 break;
5927 case MESA_SHADER_TESS_EVAL:
5928 if (ctx->options->key.tes.as_es)
5929 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5930 else
5931 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
5932 &ctx->shader_info->tes.outinfo);
5933 break;
5934 default:
5935 break;
5936 }
5937 }
5938
5939 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5940 {
5941 LLVMPassManagerRef passmgr;
5942 /* Create the pass manager */
5943 passmgr = LLVMCreateFunctionPassManagerForModule(
5944 ctx->module);
5945
5946 /* This pass should eliminate all the load and store instructions */
5947 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5948
5949 /* Add some optimization passes */
5950 LLVMAddScalarReplAggregatesPass(passmgr);
5951 LLVMAddLICMPass(passmgr);
5952 LLVMAddAggressiveDCEPass(passmgr);
5953 LLVMAddCFGSimplificationPass(passmgr);
5954 LLVMAddInstructionCombiningPass(passmgr);
5955
5956 /* Run the pass */
5957 LLVMInitializeFunctionPassManager(passmgr);
5958 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5959 LLVMFinalizeFunctionPassManager(passmgr);
5960
5961 LLVMDisposeBuilder(ctx->builder);
5962 LLVMDisposePassManager(passmgr);
5963 }
5964
5965 static void
5966 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5967 {
5968 struct ac_vs_output_info *outinfo;
5969
5970 switch (ctx->stage) {
5971 case MESA_SHADER_FRAGMENT:
5972 case MESA_SHADER_COMPUTE:
5973 case MESA_SHADER_TESS_CTRL:
5974 case MESA_SHADER_GEOMETRY:
5975 return;
5976 case MESA_SHADER_VERTEX:
5977 if (ctx->options->key.vs.as_ls ||
5978 ctx->options->key.vs.as_es)
5979 return;
5980 outinfo = &ctx->shader_info->vs.outinfo;
5981 break;
5982 case MESA_SHADER_TESS_EVAL:
5983 if (ctx->options->key.vs.as_es)
5984 return;
5985 outinfo = &ctx->shader_info->tes.outinfo;
5986 break;
5987 default:
5988 unreachable("Unhandled shader type");
5989 }
5990
5991 ac_optimize_vs_outputs(&ctx->ac,
5992 ctx->main_function,
5993 outinfo->vs_output_param_offset,
5994 VARYING_SLOT_MAX,
5995 &outinfo->param_exports);
5996 }
5997
5998 static void
5999 ac_setup_rings(struct nir_to_llvm_context *ctx)
6000 {
6001 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6002 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6003 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6004 }
6005
6006 if (ctx->is_gs_copy_shader) {
6007 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6008 }
6009 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6010 LLVMValueRef tmp;
6011 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6012 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6013
6014 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6015
6016 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6017 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6018 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6019 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6020 }
6021
6022 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6023 ctx->stage == MESA_SHADER_TESS_EVAL) {
6024 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6025 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6026 }
6027 }
6028
6029 static unsigned
6030 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6031 const struct nir_shader *nir)
6032 {
6033 switch (nir->stage) {
6034 case MESA_SHADER_TESS_CTRL:
6035 return chip_class >= CIK ? 128 : 64;
6036 case MESA_SHADER_GEOMETRY:
6037 return 64;
6038 case MESA_SHADER_COMPUTE:
6039 break;
6040 default:
6041 return 0;
6042 }
6043
6044 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6045 nir->info.cs.local_size[1] *
6046 nir->info.cs.local_size[2];
6047 return max_workgroup_size;
6048 }
6049
6050 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6051 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6052 {
6053 struct ac_nir_context ctx = {};
6054 struct nir_function *func;
6055
6056 ctx.ac = *ac;
6057 ctx.abi = abi;
6058
6059 ctx.nctx = nctx;
6060 if (nctx)
6061 nctx->nir = &ctx;
6062
6063 ctx.stage = nir->stage;
6064
6065 nir_foreach_variable(variable, &nir->outputs)
6066 handle_shader_output_decl(nctx, variable);
6067
6068 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6069 _mesa_key_pointer_equal);
6070 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6071 _mesa_key_pointer_equal);
6072 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6073 _mesa_key_pointer_equal);
6074
6075 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6076
6077 setup_locals(&ctx, func);
6078
6079 if (nir->stage == MESA_SHADER_COMPUTE)
6080 setup_shared(&ctx, nir);
6081
6082 visit_cf_list(&ctx, &func->impl->body);
6083 phi_post_pass(&ctx);
6084
6085 handle_shader_outputs_post(nctx);
6086
6087 free(ctx.locals);
6088 ralloc_free(ctx.defs);
6089 ralloc_free(ctx.phis);
6090 ralloc_free(ctx.vars);
6091
6092 if (nctx)
6093 nctx->nir = NULL;
6094 }
6095
6096 static
6097 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6098 struct nir_shader *nir,
6099 struct ac_shader_variant_info *shader_info,
6100 const struct ac_nir_compiler_options *options)
6101 {
6102 struct nir_to_llvm_context ctx = {0};
6103 unsigned i;
6104 ctx.options = options;
6105 ctx.shader_info = shader_info;
6106 ctx.context = LLVMContextCreate();
6107 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6108
6109 ac_llvm_context_init(&ctx.ac, ctx.context);
6110 ctx.ac.module = ctx.module;
6111
6112 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6113
6114 memset(shader_info, 0, sizeof(*shader_info));
6115
6116 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6117
6118 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6119
6120 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6121 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6122 LLVMSetDataLayout(ctx.module, data_layout_str);
6123 LLVMDisposeTargetData(data_layout);
6124 LLVMDisposeMessage(data_layout_str);
6125
6126 setup_types(&ctx);
6127
6128 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6129 ctx.ac.builder = ctx.builder;
6130 ctx.stage = nir->stage;
6131 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6132
6133 for (i = 0; i < AC_UD_MAX_SETS; i++)
6134 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6135 for (i = 0; i < AC_UD_MAX_UD; i++)
6136 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6137
6138 create_function(&ctx);
6139
6140 if (nir->stage == MESA_SHADER_GEOMETRY) {
6141 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
6142
6143 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6144 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6145 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6146 }
6147
6148 ac_setup_rings(&ctx);
6149
6150 ctx.num_output_clips = nir->info.clip_distance_array_size;
6151 ctx.num_output_culls = nir->info.cull_distance_array_size;
6152
6153 nir_foreach_variable(variable, &nir->inputs)
6154 handle_shader_input_decl(&ctx, variable);
6155
6156 if (nir->stage == MESA_SHADER_FRAGMENT)
6157 handle_fs_inputs_pre(&ctx, nir);
6158
6159 ctx.abi.inputs = &ctx.inputs[0];
6160
6161 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6162
6163 LLVMBuildRetVoid(ctx.builder);
6164
6165 ac_llvm_finalize_module(&ctx);
6166
6167 ac_nir_eliminate_const_vs_outputs(&ctx);
6168
6169 if (nir->stage == MESA_SHADER_GEOMETRY) {
6170 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6171 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6172 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6173 nir->info.gs.vertices_out;
6174 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6175 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6176 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6177 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6178 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6179 }
6180
6181 return ctx.module;
6182 }
6183
6184 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6185 {
6186 unsigned *retval = (unsigned *)context;
6187 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6188 char *description = LLVMGetDiagInfoDescription(di);
6189
6190 if (severity == LLVMDSError) {
6191 *retval = 1;
6192 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6193 description);
6194 }
6195
6196 LLVMDisposeMessage(description);
6197 }
6198
6199 static unsigned ac_llvm_compile(LLVMModuleRef M,
6200 struct ac_shader_binary *binary,
6201 LLVMTargetMachineRef tm)
6202 {
6203 unsigned retval = 0;
6204 char *err;
6205 LLVMContextRef llvm_ctx;
6206 LLVMMemoryBufferRef out_buffer;
6207 unsigned buffer_size;
6208 const char *buffer_data;
6209 LLVMBool mem_err;
6210
6211 /* Setup Diagnostic Handler*/
6212 llvm_ctx = LLVMGetModuleContext(M);
6213
6214 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6215 &retval);
6216
6217 /* Compile IR*/
6218 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6219 &err, &out_buffer);
6220
6221 /* Process Errors/Warnings */
6222 if (mem_err) {
6223 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6224 free(err);
6225 retval = 1;
6226 goto out;
6227 }
6228
6229 /* Extract Shader Code*/
6230 buffer_size = LLVMGetBufferSize(out_buffer);
6231 buffer_data = LLVMGetBufferStart(out_buffer);
6232
6233 ac_elf_read(buffer_data, buffer_size, binary);
6234
6235 /* Clean up */
6236 LLVMDisposeMemoryBuffer(out_buffer);
6237
6238 out:
6239 return retval;
6240 }
6241
6242 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6243 LLVMModuleRef llvm_module,
6244 struct ac_shader_binary *binary,
6245 struct ac_shader_config *config,
6246 struct ac_shader_variant_info *shader_info,
6247 gl_shader_stage stage,
6248 bool dump_shader, bool supports_spill)
6249 {
6250 if (dump_shader)
6251 ac_dump_module(llvm_module);
6252
6253 memset(binary, 0, sizeof(*binary));
6254 int v = ac_llvm_compile(llvm_module, binary, tm);
6255 if (v) {
6256 fprintf(stderr, "compile failed\n");
6257 }
6258
6259 if (dump_shader)
6260 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6261
6262 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6263
6264 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6265 LLVMDisposeModule(llvm_module);
6266 LLVMContextDispose(ctx);
6267
6268 if (stage == MESA_SHADER_FRAGMENT) {
6269 shader_info->num_input_vgprs = 0;
6270 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6271 shader_info->num_input_vgprs += 2;
6272 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6273 shader_info->num_input_vgprs += 2;
6274 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6275 shader_info->num_input_vgprs += 2;
6276 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6277 shader_info->num_input_vgprs += 3;
6278 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6279 shader_info->num_input_vgprs += 2;
6280 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6281 shader_info->num_input_vgprs += 2;
6282 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6283 shader_info->num_input_vgprs += 2;
6284 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6285 shader_info->num_input_vgprs += 1;
6286 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6287 shader_info->num_input_vgprs += 1;
6288 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6289 shader_info->num_input_vgprs += 1;
6290 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6291 shader_info->num_input_vgprs += 1;
6292 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6293 shader_info->num_input_vgprs += 1;
6294 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6295 shader_info->num_input_vgprs += 1;
6296 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6297 shader_info->num_input_vgprs += 1;
6298 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6299 shader_info->num_input_vgprs += 1;
6300 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6301 shader_info->num_input_vgprs += 1;
6302 }
6303 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6304
6305 /* +3 for scratch wave offset and VCC */
6306 config->num_sgprs = MAX2(config->num_sgprs,
6307 shader_info->num_input_sgprs + 3);
6308 }
6309
6310 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6311 struct ac_shader_binary *binary,
6312 struct ac_shader_config *config,
6313 struct ac_shader_variant_info *shader_info,
6314 struct nir_shader *nir,
6315 const struct ac_nir_compiler_options *options,
6316 bool dump_shader)
6317 {
6318
6319 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6320 options);
6321
6322 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6323 switch (nir->stage) {
6324 case MESA_SHADER_COMPUTE:
6325 for (int i = 0; i < 3; ++i)
6326 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6327 break;
6328 case MESA_SHADER_FRAGMENT:
6329 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6330 break;
6331 case MESA_SHADER_GEOMETRY:
6332 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6333 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6334 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6335 shader_info->gs.invocations = nir->info.gs.invocations;
6336 break;
6337 case MESA_SHADER_TESS_EVAL:
6338 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6339 shader_info->tes.spacing = nir->info.tess.spacing;
6340 shader_info->tes.ccw = nir->info.tess.ccw;
6341 shader_info->tes.point_mode = nir->info.tess.point_mode;
6342 shader_info->tes.as_es = options->key.tes.as_es;
6343 break;
6344 case MESA_SHADER_TESS_CTRL:
6345 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6346 break;
6347 case MESA_SHADER_VERTEX:
6348 shader_info->vs.as_es = options->key.vs.as_es;
6349 shader_info->vs.as_ls = options->key.vs.as_ls;
6350 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6351 if (options->key.vs.as_ls)
6352 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6353 break;
6354 default:
6355 break;
6356 }
6357 }
6358
6359 static void
6360 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6361 {
6362 LLVMValueRef args[9];
6363 args[0] = ctx->gsvs_ring;
6364 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6365 args[3] = ctx->i32zero;
6366 args[4] = ctx->i32one; /* OFFEN */
6367 args[5] = ctx->i32zero; /* IDXEN */
6368 args[6] = ctx->i32one; /* GLC */
6369 args[7] = ctx->i32one; /* SLC */
6370 args[8] = ctx->i32zero; /* TFE */
6371
6372 int idx = 0;
6373
6374 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6375 int length = 4;
6376 int slot = idx;
6377 int slot_inc = 1;
6378 if (!(ctx->output_mask & (1ull << i)))
6379 continue;
6380
6381 if (i == VARYING_SLOT_CLIP_DIST0) {
6382 /* unpack clip and cull from a single set of slots */
6383 length = ctx->num_output_clips + ctx->num_output_culls;
6384 if (length > 4)
6385 slot_inc = 2;
6386 }
6387
6388 for (unsigned j = 0; j < length; j++) {
6389 LLVMValueRef value;
6390 args[2] = LLVMConstInt(ctx->i32,
6391 (slot * 4 + j) *
6392 ctx->gs_max_out_vertices * 16 * 4, false);
6393
6394 value = ac_build_intrinsic(&ctx->ac,
6395 "llvm.SI.buffer.load.dword.i32.i32",
6396 ctx->i32, args, 9,
6397 AC_FUNC_ATTR_READONLY |
6398 AC_FUNC_ATTR_LEGACY);
6399
6400 LLVMBuildStore(ctx->builder,
6401 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6402 }
6403 idx += slot_inc;
6404 }
6405 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6406 }
6407
6408 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6409 struct nir_shader *geom_shader,
6410 struct ac_shader_binary *binary,
6411 struct ac_shader_config *config,
6412 struct ac_shader_variant_info *shader_info,
6413 const struct ac_nir_compiler_options *options,
6414 bool dump_shader)
6415 {
6416 struct nir_to_llvm_context ctx = {0};
6417 ctx.context = LLVMContextCreate();
6418 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6419 ctx.options = options;
6420 ctx.shader_info = shader_info;
6421
6422 ac_llvm_context_init(&ctx.ac, ctx.context);
6423 ctx.ac.module = ctx.module;
6424
6425 ctx.is_gs_copy_shader = true;
6426 LLVMSetTarget(ctx.module, "amdgcn--");
6427 setup_types(&ctx);
6428
6429 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6430 ctx.ac.builder = ctx.builder;
6431 ctx.stage = MESA_SHADER_VERTEX;
6432
6433 create_function(&ctx);
6434
6435 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6436 ac_setup_rings(&ctx);
6437
6438 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6439 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6440
6441 struct ac_nir_context nir_ctx = {};
6442 nir_ctx.ac = ctx.ac;
6443 nir_ctx.abi = &ctx.abi;
6444
6445 nir_ctx.nctx = &ctx;
6446 ctx.nir = &nir_ctx;
6447
6448 nir_foreach_variable(variable, &geom_shader->outputs)
6449 handle_shader_output_decl(&ctx, variable);
6450
6451 ac_gs_copy_shader_emit(&ctx);
6452
6453 ctx.nir = NULL;
6454
6455 LLVMBuildRetVoid(ctx.builder);
6456
6457 ac_llvm_finalize_module(&ctx);
6458
6459 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6460 MESA_SHADER_VERTEX,
6461 dump_shader, options->supports_spill);
6462 }