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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 LLVMTypeRef type = LLVMTypeOf(value);
1211 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1212 ? LLVMGetVectorSize(type)
1213 : 1;
1214
1215 for (unsigned i = 0; i < num_components; ++i) {
1216 assert(src.swizzle[i] < src_components);
1217 if (src.swizzle[i] != i)
1218 need_swizzle = true;
1219 }
1220
1221 if (need_swizzle || num_components != src_components) {
1222 LLVMValueRef masks[] = {
1223 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1224 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1225 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1226 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1227
1228 if (src_components > 1 && num_components == 1) {
1229 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1230 masks[0], "");
1231 } else if (src_components == 1 && num_components > 1) {
1232 LLVMValueRef values[] = {value, value, value, value};
1233 value = ac_build_gather_values(&ctx->ac, values, num_components);
1234 } else {
1235 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1236 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1237 swizzle, "");
1238 }
1239 }
1240 assert(!src.negate);
1241 assert(!src.abs);
1242 return value;
1243 }
1244
1245 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1246 LLVMIntPredicate pred, LLVMValueRef src0,
1247 LLVMValueRef src1)
1248 {
1249 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1256 LLVMRealPredicate pred, LLVMValueRef src0,
1257 LLVMValueRef src1)
1258 {
1259 LLVMValueRef result;
1260 src0 = ac_to_float(ctx, src0);
1261 src1 = ac_to_float(ctx, src1);
1262 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1263 return LLVMBuildSelect(ctx->builder, result,
1264 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1265 ctx->i32_0, "");
1266 }
1267
1268 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMTypeRef result_type,
1271 LLVMValueRef src0)
1272 {
1273 char name[64];
1274 LLVMValueRef params[] = {
1275 ac_to_float(ctx, src0),
1276 };
1277
1278 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1279 ac_get_elem_bits(ctx, result_type));
1280 assert(length < sizeof(name));
1281 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1282 }
1283
1284 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1285 const char *intrin,
1286 LLVMTypeRef result_type,
1287 LLVMValueRef src0, LLVMValueRef src1)
1288 {
1289 char name[64];
1290 LLVMValueRef params[] = {
1291 ac_to_float(ctx, src0),
1292 ac_to_float(ctx, src1),
1293 };
1294
1295 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1296 ac_get_elem_bits(ctx, result_type));
1297 assert(length < sizeof(name));
1298 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1299 }
1300
1301 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1302 const char *intrin,
1303 LLVMTypeRef result_type,
1304 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1305 {
1306 char name[64];
1307 LLVMValueRef params[] = {
1308 ac_to_float(ctx, src0),
1309 ac_to_float(ctx, src1),
1310 ac_to_float(ctx, src2),
1311 };
1312
1313 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1314 ac_get_elem_bits(ctx, result_type));
1315 assert(length < sizeof(name));
1316 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1317 }
1318
1319 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1320 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1321 {
1322 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1323 ctx->i32_0, "");
1324 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1325 ac_to_integer(ctx, src2), "");
1326 }
1327
1328 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1329 LLVMIntPredicate pred,
1330 LLVMValueRef src0, LLVMValueRef src1)
1331 {
1332 return LLVMBuildSelect(ctx->builder,
1333 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1334 src0,
1335 src1, "");
1336
1337 }
1338 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0)
1340 {
1341 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1342 LLVMBuildNeg(ctx->builder, src0, ""));
1343 }
1344
1345 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1346 LLVMValueRef src0,
1347 unsigned bitsize)
1348 {
1349 LLVMValueRef cmp, val, zero, one;
1350 LLVMTypeRef type;
1351
1352 if (bitsize == 32) {
1353 type = ctx->f32;
1354 zero = ctx->f32_0;
1355 one = ctx->f32_1;
1356 } else {
1357 type = ctx->f64;
1358 zero = ctx->f64_0;
1359 one = ctx->f64_1;
1360 }
1361
1362 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1363 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1364 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1365 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1366 return val;
1367 }
1368
1369 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0, unsigned bitsize)
1371 {
1372 LLVMValueRef cmp, val, zero, one;
1373 LLVMTypeRef type;
1374
1375 if (bitsize == 32) {
1376 type = ctx->i32;
1377 zero = ctx->i32_0;
1378 one = ctx->i32_1;
1379 } else {
1380 type = ctx->i64;
1381 zero = ctx->i64_0;
1382 one = ctx->i64_1;
1383 }
1384
1385 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1386 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1387 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1388 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1389 return val;
1390 }
1391
1392 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1393 LLVMValueRef src0, unsigned bitsize)
1394 {
1395 LLVMTypeRef type;
1396 char *intr;
1397
1398 if (bitsize == 32) {
1399 intr = "llvm.floor.f32";
1400 type = ctx->f32;
1401 } else {
1402 intr = "llvm.floor.f64";
1403 type = ctx->f64;
1404 }
1405
1406 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1407 LLVMValueRef params[] = {
1408 fsrc0,
1409 };
1410 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1411 AC_FUNC_ATTR_READNONE);
1412 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1413 }
1414
1415 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1416 const char *intrin,
1417 LLVMValueRef src0, LLVMValueRef src1)
1418 {
1419 LLVMTypeRef ret_type;
1420 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1421 LLVMValueRef res;
1422 LLVMValueRef params[] = { src0, src1 };
1423 ret_type = LLVMStructTypeInContext(ctx->context, types,
1424 2, true);
1425
1426 res = ac_build_intrinsic(ctx, intrin, ret_type,
1427 params, 2, AC_FUNC_ATTR_READNONE);
1428
1429 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1430 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1431 return res;
1432 }
1433
1434 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1438 }
1439
1440 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0)
1442 {
1443 src0 = ac_to_float(ctx, src0);
1444 return LLVMBuildSExt(ctx->builder,
1445 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1446 ctx->i32, "");
1447 }
1448
1449 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0,
1451 unsigned bitsize)
1452 {
1453 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1454
1455 if (bitsize == 32)
1456 return result;
1457
1458 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1459 }
1460
1461 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1462 LLVMValueRef src0)
1463 {
1464 return LLVMBuildSExt(ctx->builder,
1465 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1466 ctx->i32, "");
1467 }
1468
1469 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1470 LLVMValueRef src0)
1471 {
1472 LLVMValueRef result;
1473 LLVMValueRef cond = NULL;
1474
1475 src0 = ac_to_float(ctx, src0);
1476 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1477
1478 if (ctx->chip_class >= VI) {
1479 LLVMValueRef args[2];
1480 /* Check if the result is a denormal - and flush to 0 if so. */
1481 args[0] = result;
1482 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1483 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1484 }
1485
1486 /* need to convert back up to f32 */
1487 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1488
1489 if (ctx->chip_class >= VI)
1490 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1491 else {
1492 /* for SI/CIK */
1493 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1494 * so compare the result and flush to 0 if it's smaller.
1495 */
1496 LLVMValueRef temp, cond2;
1497 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1498 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1499 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1500 temp, "");
1501 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1502 temp, ctx->f32_0, "");
1503 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1504 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1505 }
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1523 LLVMValueRef src0, LLVMValueRef src1)
1524 {
1525 LLVMValueRef dst64, result;
1526 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1527 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1528
1529 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1530 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1531 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1536 bool is_signed,
1537 const LLVMValueRef srcs[3])
1538 {
1539 LLVMValueRef result;
1540 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1541
1542 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1543 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1544 return result;
1545 }
1546
1547 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0, LLVMValueRef src1,
1549 LLVMValueRef src2, LLVMValueRef src3)
1550 {
1551 LLVMValueRef bfi_args[3], result;
1552
1553 bfi_args[0] = LLVMBuildShl(ctx->builder,
1554 LLVMBuildSub(ctx->builder,
1555 LLVMBuildShl(ctx->builder,
1556 ctx->i32_1,
1557 src3, ""),
1558 ctx->i32_1, ""),
1559 src2, "");
1560 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1561 bfi_args[2] = src0;
1562
1563 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1564
1565 /* Calculate:
1566 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1567 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1568 */
1569 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1570 LLVMBuildAnd(ctx->builder, bfi_args[0],
1571 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1572
1573 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1574 return result;
1575 }
1576
1577 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1578 LLVMValueRef src0)
1579 {
1580 LLVMValueRef comp[2];
1581
1582 src0 = ac_to_float(ctx, src0);
1583 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1584 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1585
1586 return ac_build_cvt_pkrtz_f16(ctx, comp);
1587 }
1588
1589 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1590 LLVMValueRef src0)
1591 {
1592 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1593 LLVMValueRef temps[2], result, val;
1594 int i;
1595
1596 for (i = 0; i < 2; i++) {
1597 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1598 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1599 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1600 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1601 }
1602
1603 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1604 ctx->i32_0, "");
1605 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1606 ctx->i32_1, "");
1607 return result;
1608 }
1609
1610 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1611 nir_op op,
1612 LLVMValueRef src0)
1613 {
1614 unsigned mask;
1615 int idx;
1616 LLVMValueRef result;
1617
1618 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1619 mask = AC_TID_MASK_LEFT;
1620 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1621 mask = AC_TID_MASK_TOP;
1622 else
1623 mask = AC_TID_MASK_TOP_LEFT;
1624
1625 /* for DDX we want to next X pixel, DDY next Y pixel. */
1626 if (op == nir_op_fddx_fine ||
1627 op == nir_op_fddx_coarse ||
1628 op == nir_op_fddx)
1629 idx = 1;
1630 else
1631 idx = 2;
1632
1633 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1634 return result;
1635 }
1636
1637 /*
1638 * this takes an I,J coordinate pair,
1639 * and works out the X and Y derivatives.
1640 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1641 */
1642 static LLVMValueRef emit_ddxy_interp(
1643 struct ac_nir_context *ctx,
1644 LLVMValueRef interp_ij)
1645 {
1646 LLVMValueRef result[4], a;
1647 unsigned i;
1648
1649 for (i = 0; i < 2; i++) {
1650 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1651 LLVMConstInt(ctx->ac.i32, i, false), "");
1652 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1653 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1654 }
1655 return ac_build_gather_values(&ctx->ac, result, 4);
1656 }
1657
1658 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1659 {
1660 LLVMValueRef src[4], result = NULL;
1661 unsigned num_components = instr->dest.dest.ssa.num_components;
1662 unsigned src_components;
1663 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1664
1665 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1666 switch (instr->op) {
1667 case nir_op_vec2:
1668 case nir_op_vec3:
1669 case nir_op_vec4:
1670 src_components = 1;
1671 break;
1672 case nir_op_pack_half_2x16:
1673 src_components = 2;
1674 break;
1675 case nir_op_unpack_half_2x16:
1676 src_components = 1;
1677 break;
1678 default:
1679 src_components = num_components;
1680 break;
1681 }
1682 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1683 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1684
1685 switch (instr->op) {
1686 case nir_op_fmov:
1687 case nir_op_imov:
1688 result = src[0];
1689 break;
1690 case nir_op_fneg:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1693 break;
1694 case nir_op_ineg:
1695 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1696 break;
1697 case nir_op_inot:
1698 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1699 break;
1700 case nir_op_iadd:
1701 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_fadd:
1704 src[0] = ac_to_float(&ctx->ac, src[0]);
1705 src[1] = ac_to_float(&ctx->ac, src[1]);
1706 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_fsub:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_isub:
1714 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_imul:
1717 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_imod:
1720 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_umod:
1723 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1724 break;
1725 case nir_op_fmod:
1726 src[0] = ac_to_float(&ctx->ac, src[0]);
1727 src[1] = ac_to_float(&ctx->ac, src[1]);
1728 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1730 ac_to_float_type(&ctx->ac, def_type), result);
1731 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1732 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1733 break;
1734 case nir_op_frem:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 src[1] = ac_to_float(&ctx->ac, src[1]);
1737 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_irem:
1740 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_idiv:
1743 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_udiv:
1746 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_fmul:
1749 src[0] = ac_to_float(&ctx->ac, src[0]);
1750 src[1] = ac_to_float(&ctx->ac, src[1]);
1751 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_frcp:
1754 src[0] = ac_to_float(&ctx->ac, src[0]);
1755 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1756 src[0]);
1757 break;
1758 case nir_op_iand:
1759 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_ior:
1762 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1763 break;
1764 case nir_op_ixor:
1765 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1766 break;
1767 case nir_op_ishl:
1768 result = LLVMBuildShl(ctx->ac.builder, src[0],
1769 LLVMBuildZExt(ctx->ac.builder, src[1],
1770 LLVMTypeOf(src[0]), ""),
1771 "");
1772 break;
1773 case nir_op_ishr:
1774 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1775 LLVMBuildZExt(ctx->ac.builder, src[1],
1776 LLVMTypeOf(src[0]), ""),
1777 "");
1778 break;
1779 case nir_op_ushr:
1780 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1781 LLVMBuildZExt(ctx->ac.builder, src[1],
1782 LLVMTypeOf(src[0]), ""),
1783 "");
1784 break;
1785 case nir_op_ilt:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1787 break;
1788 case nir_op_ine:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1790 break;
1791 case nir_op_ieq:
1792 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1793 break;
1794 case nir_op_ige:
1795 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1796 break;
1797 case nir_op_ult:
1798 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1799 break;
1800 case nir_op_uge:
1801 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1802 break;
1803 case nir_op_feq:
1804 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1805 break;
1806 case nir_op_fne:
1807 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1808 break;
1809 case nir_op_flt:
1810 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1811 break;
1812 case nir_op_fge:
1813 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1814 break;
1815 case nir_op_fabs:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1817 ac_to_float_type(&ctx->ac, def_type), src[0]);
1818 break;
1819 case nir_op_iabs:
1820 result = emit_iabs(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_imax:
1823 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1824 break;
1825 case nir_op_imin:
1826 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1827 break;
1828 case nir_op_umax:
1829 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1830 break;
1831 case nir_op_umin:
1832 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1833 break;
1834 case nir_op_isign:
1835 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1836 break;
1837 case nir_op_fsign:
1838 src[0] = ac_to_float(&ctx->ac, src[0]);
1839 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1840 break;
1841 case nir_op_ffloor:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_ftrunc:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1847 ac_to_float_type(&ctx->ac, def_type), src[0]);
1848 break;
1849 case nir_op_fceil:
1850 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1851 ac_to_float_type(&ctx->ac, def_type), src[0]);
1852 break;
1853 case nir_op_fround_even:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1855 ac_to_float_type(&ctx->ac, def_type),src[0]);
1856 break;
1857 case nir_op_ffract:
1858 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1859 break;
1860 case nir_op_fsin:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fcos:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_fsqrt:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_fexp2:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 break;
1876 case nir_op_flog2:
1877 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1878 ac_to_float_type(&ctx->ac, def_type), src[0]);
1879 break;
1880 case nir_op_frsq:
1881 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1882 ac_to_float_type(&ctx->ac, def_type), src[0]);
1883 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1884 result);
1885 break;
1886 case nir_op_fpow:
1887 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1888 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1889 break;
1890 case nir_op_fmax:
1891 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1892 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1893 if (ctx->ac.chip_class < GFX9 &&
1894 instr->dest.dest.ssa.bit_size == 32) {
1895 /* Only pre-GFX9 chips do not flush denorms. */
1896 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1897 ac_to_float_type(&ctx->ac, def_type),
1898 result);
1899 }
1900 break;
1901 case nir_op_fmin:
1902 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1903 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1904 if (ctx->ac.chip_class < GFX9 &&
1905 instr->dest.dest.ssa.bit_size == 32) {
1906 /* Only pre-GFX9 chips do not flush denorms. */
1907 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1908 ac_to_float_type(&ctx->ac, def_type),
1909 result);
1910 }
1911 break;
1912 case nir_op_ffma:
1913 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1914 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1915 break;
1916 case nir_op_ibitfield_extract:
1917 result = emit_bitfield_extract(&ctx->ac, true, src);
1918 break;
1919 case nir_op_ubitfield_extract:
1920 result = emit_bitfield_extract(&ctx->ac, false, src);
1921 break;
1922 case nir_op_bitfield_insert:
1923 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1924 break;
1925 case nir_op_bitfield_reverse:
1926 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1927 break;
1928 case nir_op_bit_count:
1929 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1930 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1931 else {
1932 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1933 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1934 }
1935 break;
1936 case nir_op_vec2:
1937 case nir_op_vec3:
1938 case nir_op_vec4:
1939 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1940 src[i] = ac_to_integer(&ctx->ac, src[i]);
1941 result = ac_build_gather_values(&ctx->ac, src, num_components);
1942 break;
1943 case nir_op_f2i32:
1944 case nir_op_f2i64:
1945 src[0] = ac_to_float(&ctx->ac, src[0]);
1946 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1947 break;
1948 case nir_op_f2u32:
1949 case nir_op_f2u64:
1950 src[0] = ac_to_float(&ctx->ac, src[0]);
1951 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1952 break;
1953 case nir_op_i2f32:
1954 case nir_op_i2f64:
1955 src[0] = ac_to_integer(&ctx->ac, src[0]);
1956 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2f32:
1959 case nir_op_u2f64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1962 break;
1963 case nir_op_f2f64:
1964 src[0] = ac_to_float(&ctx->ac, src[0]);
1965 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1966 break;
1967 case nir_op_f2f32:
1968 src[0] = ac_to_float(&ctx->ac, src[0]);
1969 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1970 break;
1971 case nir_op_u2u32:
1972 case nir_op_u2u64:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1975 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1976 else
1977 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1978 break;
1979 case nir_op_i2i32:
1980 case nir_op_i2i64:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1983 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1984 else
1985 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1986 break;
1987 case nir_op_bcsel:
1988 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1989 break;
1990 case nir_op_find_lsb:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1993 break;
1994 case nir_op_ufind_msb:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1997 break;
1998 case nir_op_ifind_msb:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2001 break;
2002 case nir_op_uadd_carry:
2003 src[0] = ac_to_integer(&ctx->ac, src[0]);
2004 src[1] = ac_to_integer(&ctx->ac, src[1]);
2005 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2006 break;
2007 case nir_op_usub_borrow:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 src[1] = ac_to_integer(&ctx->ac, src[1]);
2010 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2011 break;
2012 case nir_op_b2f:
2013 result = emit_b2f(&ctx->ac, src[0]);
2014 break;
2015 case nir_op_f2b:
2016 result = emit_f2b(&ctx->ac, src[0]);
2017 break;
2018 case nir_op_b2i:
2019 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2020 break;
2021 case nir_op_i2b:
2022 src[0] = ac_to_integer(&ctx->ac, src[0]);
2023 result = emit_i2b(&ctx->ac, src[0]);
2024 break;
2025 case nir_op_fquantize2f16:
2026 result = emit_f2f16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_umul_high:
2029 src[0] = ac_to_integer(&ctx->ac, src[0]);
2030 src[1] = ac_to_integer(&ctx->ac, src[1]);
2031 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2032 break;
2033 case nir_op_imul_high:
2034 src[0] = ac_to_integer(&ctx->ac, src[0]);
2035 src[1] = ac_to_integer(&ctx->ac, src[1]);
2036 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2037 break;
2038 case nir_op_pack_half_2x16:
2039 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2040 break;
2041 case nir_op_unpack_half_2x16:
2042 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2043 break;
2044 case nir_op_fddx:
2045 case nir_op_fddy:
2046 case nir_op_fddx_fine:
2047 case nir_op_fddy_fine:
2048 case nir_op_fddx_coarse:
2049 case nir_op_fddy_coarse:
2050 result = emit_ddxy(ctx, instr->op, src[0]);
2051 break;
2052
2053 case nir_op_unpack_64_2x32_split_x: {
2054 assert(ac_get_llvm_num_components(src[0]) == 1);
2055 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2056 ctx->ac.v2i32,
2057 "");
2058 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2059 ctx->ac.i32_0, "");
2060 break;
2061 }
2062
2063 case nir_op_unpack_64_2x32_split_y: {
2064 assert(ac_get_llvm_num_components(src[0]) == 1);
2065 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2066 ctx->ac.v2i32,
2067 "");
2068 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2069 ctx->ac.i32_1, "");
2070 break;
2071 }
2072
2073 case nir_op_pack_64_2x32_split: {
2074 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2075 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2076 src[0], ctx->ac.i32_0, "");
2077 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2078 src[1], ctx->ac.i32_1, "");
2079 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2080 break;
2081 }
2082
2083 default:
2084 fprintf(stderr, "Unknown NIR alu instr: ");
2085 nir_print_instr(&instr->instr, stderr);
2086 fprintf(stderr, "\n");
2087 abort();
2088 }
2089
2090 if (result) {
2091 assert(instr->dest.dest.is_ssa);
2092 result = ac_to_integer(&ctx->ac, result);
2093 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2094 result);
2095 }
2096 }
2097
2098 static void visit_load_const(struct ac_nir_context *ctx,
2099 const nir_load_const_instr *instr)
2100 {
2101 LLVMValueRef values[4], value = NULL;
2102 LLVMTypeRef element_type =
2103 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2104
2105 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2106 switch (instr->def.bit_size) {
2107 case 32:
2108 values[i] = LLVMConstInt(element_type,
2109 instr->value.u32[i], false);
2110 break;
2111 case 64:
2112 values[i] = LLVMConstInt(element_type,
2113 instr->value.u64[i], false);
2114 break;
2115 default:
2116 fprintf(stderr,
2117 "unsupported nir load_const bit_size: %d\n",
2118 instr->def.bit_size);
2119 abort();
2120 }
2121 }
2122 if (instr->def.num_components > 1) {
2123 value = LLVMConstVector(values, instr->def.num_components);
2124 } else
2125 value = values[0];
2126
2127 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2128 }
2129
2130 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2131 LLVMTypeRef type)
2132 {
2133 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2134 return LLVMBuildBitCast(ctx->builder, ptr,
2135 LLVMPointerType(type, addr_space), "");
2136 }
2137
2138 static LLVMValueRef
2139 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2140 {
2141 LLVMValueRef size =
2142 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2143 LLVMConstInt(ctx->ac.i32, 2, false), "");
2144
2145 /* VI only */
2146 if (ctx->ac.chip_class == VI && in_elements) {
2147 /* On VI, the descriptor contains the size in bytes,
2148 * but TXQ must return the size in elements.
2149 * The stride is always non-zero for resources using TXQ.
2150 */
2151 LLVMValueRef stride =
2152 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2153 ctx->ac.i32_1, "");
2154 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2155 LLVMConstInt(ctx->ac.i32, 16, false), "");
2156 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2157 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2158
2159 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2160 }
2161 return size;
2162 }
2163
2164 /**
2165 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2166 * intrinsic names).
2167 */
2168 static void build_int_type_name(
2169 LLVMTypeRef type,
2170 char *buf, unsigned bufsize)
2171 {
2172 assert(bufsize >= 6);
2173
2174 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2175 snprintf(buf, bufsize, "v%ui32",
2176 LLVMGetVectorSize(type));
2177 else
2178 strcpy(buf, "i32");
2179 }
2180
2181 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2182 struct ac_image_args *args,
2183 const nir_tex_instr *instr)
2184 {
2185 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2186 LLVMValueRef coord = args->addr;
2187 LLVMValueRef half_texel[2];
2188 LLVMValueRef compare_cube_wa = NULL;
2189 LLVMValueRef result;
2190 int c;
2191 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2192
2193 //TODO Rect
2194 {
2195 struct ac_image_args txq_args = { 0 };
2196
2197 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2198 txq_args.opcode = ac_image_get_resinfo;
2199 txq_args.dmask = 0xf;
2200 txq_args.addr = ctx->i32_0;
2201 txq_args.resource = args->resource;
2202 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2203
2204 for (c = 0; c < 2; c++) {
2205 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2206 LLVMConstInt(ctx->i32, c, false), "");
2207 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2208 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2209 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2210 LLVMConstReal(ctx->f32, -0.5), "");
2211 }
2212 }
2213
2214 LLVMValueRef orig_coords = args->addr;
2215
2216 for (c = 0; c < 2; c++) {
2217 LLVMValueRef tmp;
2218 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2219 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2220 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2221 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2222 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2223 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2224 }
2225
2226
2227 /*
2228 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2229 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2230 * workaround by sampling using a scaled type and converting.
2231 * This is taken from amdgpu-pro shaders.
2232 */
2233 /* NOTE this produces some ugly code compared to amdgpu-pro,
2234 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2235 * and then reads them back. -pro generates two selects,
2236 * one s_cmp for the descriptor rewriting
2237 * one v_cmp for the coordinate and result changes.
2238 */
2239 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2240 LLVMValueRef tmp, tmp2;
2241
2242 /* workaround 8/8/8/8 uint/sint cube gather bug */
2243 /* first detect it then change to a scaled read and f2i */
2244 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2245 tmp2 = tmp;
2246
2247 /* extract the DATA_FORMAT */
2248 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2249 LLVMConstInt(ctx->i32, 6, false), false);
2250
2251 /* is the DATA_FORMAT == 8_8_8_8 */
2252 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2253
2254 if (stype == GLSL_TYPE_UINT)
2255 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2256 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2257 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2258 else
2259 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2260 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2261 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2262
2263 /* replace the NUM FORMAT in the descriptor */
2264 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2265 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2266
2267 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2268
2269 /* don't modify the coordinates for this case */
2270 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2271 }
2272 args->addr = coord;
2273 result = ac_build_image_opcode(ctx, args);
2274
2275 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2276 LLVMValueRef tmp, tmp2;
2277
2278 /* if the cube workaround is in place, f2i the result. */
2279 for (c = 0; c < 4; c++) {
2280 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2281 if (stype == GLSL_TYPE_UINT)
2282 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2283 else
2284 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2285 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2286 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2287 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2288 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2289 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2290 }
2291 }
2292 return result;
2293 }
2294
2295 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2296 const nir_tex_instr *instr,
2297 bool lod_is_zero,
2298 struct ac_image_args *args)
2299 {
2300 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2301 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2302
2303 return ac_build_buffer_load_format(&ctx->ac,
2304 args->resource,
2305 args->addr,
2306 ctx->ac.i32_0,
2307 util_last_bit(mask),
2308 false, true);
2309 }
2310
2311 args->opcode = ac_image_sample;
2312 args->compare = instr->is_shadow;
2313
2314 switch (instr->op) {
2315 case nir_texop_txf:
2316 case nir_texop_txf_ms:
2317 case nir_texop_samples_identical:
2318 args->opcode = lod_is_zero ||
2319 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2320 ac_image_load : ac_image_load_mip;
2321 args->compare = false;
2322 args->offset = false;
2323 break;
2324 case nir_texop_txb:
2325 args->bias = true;
2326 break;
2327 case nir_texop_txl:
2328 if (lod_is_zero)
2329 args->level_zero = true;
2330 else
2331 args->lod = true;
2332 break;
2333 case nir_texop_txs:
2334 case nir_texop_query_levels:
2335 args->opcode = ac_image_get_resinfo;
2336 break;
2337 case nir_texop_tex:
2338 if (ctx->stage != MESA_SHADER_FRAGMENT)
2339 args->level_zero = true;
2340 break;
2341 case nir_texop_txd:
2342 args->deriv = true;
2343 break;
2344 case nir_texop_tg4:
2345 args->opcode = ac_image_gather4;
2346 args->level_zero = true;
2347 break;
2348 case nir_texop_lod:
2349 args->opcode = ac_image_get_lod;
2350 args->compare = false;
2351 args->offset = false;
2352 break;
2353 default:
2354 break;
2355 }
2356
2357 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2358 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2359 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2360 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2361 }
2362 }
2363 return ac_build_image_opcode(&ctx->ac, args);
2364 }
2365
2366 static LLVMValueRef
2367 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2368 unsigned desc_set, unsigned binding)
2369 {
2370 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2371 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2372 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2373 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2374 unsigned base_offset = layout->binding[binding].offset;
2375 LLVMValueRef offset, stride;
2376
2377 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2378 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2379 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2380 layout->binding[binding].dynamic_offset_offset;
2381 desc_ptr = ctx->abi.push_constants;
2382 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2383 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2384 } else
2385 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2386
2387 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2388 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2389 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2390
2391 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2392 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2393 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2394
2395 return desc_ptr;
2396 }
2397
2398 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2399 nir_intrinsic_instr *instr)
2400 {
2401 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2402 LLVMValueRef index = get_src(ctx, instr->src[1]);
2403
2404 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2405 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2406 return result;
2407 }
2408
2409 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2410 nir_intrinsic_instr *instr)
2411 {
2412 LLVMValueRef ptr, addr;
2413
2414 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2415 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2416 get_src(ctx, instr->src[0]), "");
2417
2418 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2419 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2420
2421 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2422 }
2423
2424 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2425 const nir_intrinsic_instr *instr)
2426 {
2427 LLVMValueRef index = get_src(ctx, instr->src[0]);
2428
2429 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2430 }
2431
2432 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2433 {
2434 uint32_t new_mask = 0;
2435 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2436 if (mask & (1u << i))
2437 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2438 return new_mask;
2439 }
2440
2441 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2442 unsigned start, unsigned count)
2443 {
2444 LLVMTypeRef type = LLVMTypeOf(src);
2445
2446 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2447 assert(start == 0);
2448 assert(count == 1);
2449 return src;
2450 }
2451
2452 unsigned src_elements = LLVMGetVectorSize(type);
2453 assert(start < src_elements);
2454 assert(start + count <= src_elements);
2455
2456 if (start == 0 && count == src_elements)
2457 return src;
2458
2459 if (count == 1)
2460 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2461
2462 assert(count <= 8);
2463 LLVMValueRef indices[8];
2464 for (unsigned i = 0; i < count; ++i)
2465 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2466
2467 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2468 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2469 }
2470
2471 static void visit_store_ssbo(struct ac_nir_context *ctx,
2472 nir_intrinsic_instr *instr)
2473 {
2474 const char *store_name;
2475 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2476 LLVMTypeRef data_type = ctx->ac.f32;
2477 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2478 int components_32bit = elem_size_mult * instr->num_components;
2479 unsigned writemask = nir_intrinsic_write_mask(instr);
2480 LLVMValueRef base_data, base_offset;
2481 LLVMValueRef params[6];
2482
2483 params[1] = ctx->abi->load_ssbo(ctx->abi,
2484 get_src(ctx, instr->src[1]), true);
2485 params[2] = ctx->ac.i32_0; /* vindex */
2486 params[4] = ctx->ac.i1false; /* glc */
2487 params[5] = ctx->ac.i1false; /* slc */
2488
2489 if (components_32bit > 1)
2490 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2491
2492 writemask = widen_mask(writemask, elem_size_mult);
2493
2494 base_data = ac_to_float(&ctx->ac, src_data);
2495 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2496 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2497 data_type, "");
2498 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2499 while (writemask) {
2500 int start, count;
2501 LLVMValueRef data;
2502 LLVMValueRef offset;
2503
2504 u_bit_scan_consecutive_range(&writemask, &start, &count);
2505
2506 /* Due to an LLVM limitation, split 3-element writes
2507 * into a 2-element and a 1-element write. */
2508 if (count == 3) {
2509 writemask |= 1 << (start + 2);
2510 count = 2;
2511 }
2512
2513 if (count > 4) {
2514 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2515 count = 4;
2516 }
2517
2518 if (count == 4) {
2519 store_name = "llvm.amdgcn.buffer.store.v4f32";
2520 } else if (count == 2) {
2521 store_name = "llvm.amdgcn.buffer.store.v2f32";
2522
2523 } else {
2524 assert(count == 1);
2525 store_name = "llvm.amdgcn.buffer.store.f32";
2526 }
2527 data = extract_vector_range(&ctx->ac, base_data, start, count);
2528
2529 offset = base_offset;
2530 if (start != 0) {
2531 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2532 }
2533 params[0] = data;
2534 params[3] = offset;
2535 ac_build_intrinsic(&ctx->ac, store_name,
2536 ctx->ac.voidt, params, 6, 0);
2537 }
2538 }
2539
2540 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2541 const nir_intrinsic_instr *instr)
2542 {
2543 const char *name;
2544 LLVMValueRef params[6];
2545 int arg_count = 0;
2546
2547 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2548 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2549 }
2550 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2551 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2552 get_src(ctx, instr->src[0]),
2553 true);
2554 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2555 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2556 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2557
2558 switch (instr->intrinsic) {
2559 case nir_intrinsic_ssbo_atomic_add:
2560 name = "llvm.amdgcn.buffer.atomic.add";
2561 break;
2562 case nir_intrinsic_ssbo_atomic_imin:
2563 name = "llvm.amdgcn.buffer.atomic.smin";
2564 break;
2565 case nir_intrinsic_ssbo_atomic_umin:
2566 name = "llvm.amdgcn.buffer.atomic.umin";
2567 break;
2568 case nir_intrinsic_ssbo_atomic_imax:
2569 name = "llvm.amdgcn.buffer.atomic.smax";
2570 break;
2571 case nir_intrinsic_ssbo_atomic_umax:
2572 name = "llvm.amdgcn.buffer.atomic.umax";
2573 break;
2574 case nir_intrinsic_ssbo_atomic_and:
2575 name = "llvm.amdgcn.buffer.atomic.and";
2576 break;
2577 case nir_intrinsic_ssbo_atomic_or:
2578 name = "llvm.amdgcn.buffer.atomic.or";
2579 break;
2580 case nir_intrinsic_ssbo_atomic_xor:
2581 name = "llvm.amdgcn.buffer.atomic.xor";
2582 break;
2583 case nir_intrinsic_ssbo_atomic_exchange:
2584 name = "llvm.amdgcn.buffer.atomic.swap";
2585 break;
2586 case nir_intrinsic_ssbo_atomic_comp_swap:
2587 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2588 break;
2589 default:
2590 abort();
2591 }
2592
2593 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2594 }
2595
2596 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2597 const nir_intrinsic_instr *instr)
2598 {
2599 LLVMValueRef results[2];
2600 int load_components;
2601 int num_components = instr->num_components;
2602 if (instr->dest.ssa.bit_size == 64)
2603 num_components *= 2;
2604
2605 for (int i = 0; i < num_components; i += load_components) {
2606 load_components = MIN2(num_components - i, 4);
2607 const char *load_name;
2608 LLVMTypeRef data_type = ctx->ac.f32;
2609 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2610 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2611
2612 if (load_components == 3)
2613 data_type = LLVMVectorType(ctx->ac.f32, 4);
2614 else if (load_components > 1)
2615 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2616
2617 if (load_components >= 3)
2618 load_name = "llvm.amdgcn.buffer.load.v4f32";
2619 else if (load_components == 2)
2620 load_name = "llvm.amdgcn.buffer.load.v2f32";
2621 else if (load_components == 1)
2622 load_name = "llvm.amdgcn.buffer.load.f32";
2623 else
2624 unreachable("unhandled number of components");
2625
2626 LLVMValueRef params[] = {
2627 ctx->abi->load_ssbo(ctx->abi,
2628 get_src(ctx, instr->src[0]),
2629 false),
2630 ctx->ac.i32_0,
2631 offset,
2632 ctx->ac.i1false,
2633 ctx->ac.i1false,
2634 };
2635
2636 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2637 }
2638
2639 assume(results[0]);
2640 LLVMValueRef ret = results[0];
2641 if (num_components > 4 || num_components == 3) {
2642 LLVMValueRef masks[] = {
2643 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2644 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2645 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2646 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2647 };
2648
2649 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2650 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2651 results[num_components > 4 ? 1 : 0], swizzle, "");
2652 }
2653
2654 return LLVMBuildBitCast(ctx->ac.builder, ret,
2655 get_def_type(ctx, &instr->dest.ssa), "");
2656 }
2657
2658 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2659 const nir_intrinsic_instr *instr)
2660 {
2661 LLVMValueRef ret;
2662 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2663 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2664 int num_components = instr->num_components;
2665
2666 if (ctx->abi->load_ubo)
2667 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2668
2669 if (instr->dest.ssa.bit_size == 64)
2670 num_components *= 2;
2671
2672 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2673 NULL, 0, false, false, true, true);
2674 ret = trim_vector(&ctx->ac, ret, num_components);
2675 return LLVMBuildBitCast(ctx->ac.builder, ret,
2676 get_def_type(ctx, &instr->dest.ssa), "");
2677 }
2678
2679 static void
2680 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2681 bool vs_in, unsigned *vertex_index_out,
2682 LLVMValueRef *vertex_index_ref,
2683 unsigned *const_out, LLVMValueRef *indir_out)
2684 {
2685 unsigned const_offset = 0;
2686 nir_deref *tail = &deref->deref;
2687 LLVMValueRef offset = NULL;
2688
2689 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2690 tail = tail->child;
2691 nir_deref_array *deref_array = nir_deref_as_array(tail);
2692 if (vertex_index_out)
2693 *vertex_index_out = deref_array->base_offset;
2694
2695 if (vertex_index_ref) {
2696 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2697 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2698 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2699 }
2700 *vertex_index_ref = vtx;
2701 }
2702 }
2703
2704 if (deref->var->data.compact) {
2705 assert(tail->child->deref_type == nir_deref_type_array);
2706 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2707 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2708 /* We always lower indirect dereferences for "compact" array vars. */
2709 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2710
2711 const_offset = deref_array->base_offset;
2712 goto out;
2713 }
2714
2715 while (tail->child != NULL) {
2716 const struct glsl_type *parent_type = tail->type;
2717 tail = tail->child;
2718
2719 if (tail->deref_type == nir_deref_type_array) {
2720 nir_deref_array *deref_array = nir_deref_as_array(tail);
2721 LLVMValueRef index, stride, local_offset;
2722 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2723
2724 const_offset += size * deref_array->base_offset;
2725 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2726 continue;
2727
2728 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2729 index = get_src(ctx, deref_array->indirect);
2730 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2731 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2732
2733 if (offset)
2734 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2735 else
2736 offset = local_offset;
2737 } else if (tail->deref_type == nir_deref_type_struct) {
2738 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2739
2740 for (unsigned i = 0; i < deref_struct->index; i++) {
2741 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2742 const_offset += glsl_count_attribute_slots(ft, vs_in);
2743 }
2744 } else
2745 unreachable("unsupported deref type");
2746
2747 }
2748 out:
2749 if (const_offset && offset)
2750 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2751 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2752 "");
2753
2754 *const_out = const_offset;
2755 *indir_out = offset;
2756 }
2757
2758
2759 /* The offchip buffer layout for TCS->TES is
2760 *
2761 * - attribute 0 of patch 0 vertex 0
2762 * - attribute 0 of patch 0 vertex 1
2763 * - attribute 0 of patch 0 vertex 2
2764 * ...
2765 * - attribute 0 of patch 1 vertex 0
2766 * - attribute 0 of patch 1 vertex 1
2767 * ...
2768 * - attribute 1 of patch 0 vertex 0
2769 * - attribute 1 of patch 0 vertex 1
2770 * ...
2771 * - per patch attribute 0 of patch 0
2772 * - per patch attribute 0 of patch 1
2773 * ...
2774 *
2775 * Note that every attribute has 4 components.
2776 */
2777 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2778 LLVMValueRef vertex_index,
2779 LLVMValueRef param_index)
2780 {
2781 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2782 LLVMValueRef param_stride, constant16;
2783 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2784
2785 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2786 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2787
2788 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2789 if (vertex_index) {
2790 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2791 vertices_per_patch, "");
2792
2793 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2794 vertex_index, "");
2795
2796 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2797 num_patches, "");
2798 } else {
2799 base_addr = rel_patch_id;
2800 param_stride = num_patches;
2801 }
2802
2803 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2804 LLVMBuildMul(ctx->ac.builder, param_index,
2805 param_stride, ""), "");
2806
2807 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2808
2809 if (!vertex_index) {
2810 LLVMValueRef patch_data_offset =
2811 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2812
2813 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2814 patch_data_offset, "");
2815 }
2816 return base_addr;
2817 }
2818
2819 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2820 unsigned param,
2821 unsigned const_index,
2822 bool is_compact,
2823 LLVMValueRef vertex_index,
2824 LLVMValueRef indir_index)
2825 {
2826 LLVMValueRef param_index;
2827
2828 if (indir_index)
2829 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2830 indir_index, "");
2831 else {
2832 if (const_index && !is_compact)
2833 param += const_index;
2834 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2835 }
2836 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2837 }
2838
2839 static void
2840 mark_tess_output(struct radv_shader_context *ctx,
2841 bool is_patch, uint32_t param)
2842
2843 {
2844 if (is_patch) {
2845 ctx->tess_patch_outputs_written |= (1ull << param);
2846 } else
2847 ctx->tess_outputs_written |= (1ull << param);
2848 }
2849
2850 static LLVMValueRef
2851 get_dw_address(struct radv_shader_context *ctx,
2852 LLVMValueRef dw_addr,
2853 unsigned param,
2854 unsigned const_index,
2855 bool compact_const_index,
2856 LLVMValueRef vertex_index,
2857 LLVMValueRef stride,
2858 LLVMValueRef indir_index)
2859
2860 {
2861
2862 if (vertex_index) {
2863 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2864 LLVMBuildMul(ctx->ac.builder,
2865 vertex_index,
2866 stride, ""), "");
2867 }
2868
2869 if (indir_index)
2870 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2871 LLVMBuildMul(ctx->ac.builder, indir_index,
2872 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2873 else if (const_index && !compact_const_index)
2874 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2875 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2876
2877 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2878 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2879
2880 if (const_index && compact_const_index)
2881 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2882 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2883 return dw_addr;
2884 }
2885
2886 static LLVMValueRef
2887 load_tcs_varyings(struct ac_shader_abi *abi,
2888 LLVMTypeRef type,
2889 LLVMValueRef vertex_index,
2890 LLVMValueRef indir_index,
2891 unsigned const_index,
2892 unsigned location,
2893 unsigned driver_location,
2894 unsigned component,
2895 unsigned num_components,
2896 bool is_patch,
2897 bool is_compact,
2898 bool load_input)
2899 {
2900 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2901 LLVMValueRef dw_addr, stride;
2902 LLVMValueRef value[4], result;
2903 unsigned param = shader_io_get_unique_index(location);
2904
2905 if (load_input) {
2906 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2907 dw_addr = get_tcs_in_current_patch_offset(ctx);
2908 } else {
2909 if (!is_patch) {
2910 stride = get_tcs_out_vertex_stride(ctx);
2911 dw_addr = get_tcs_out_current_patch_offset(ctx);
2912 } else {
2913 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2914 stride = NULL;
2915 }
2916 }
2917
2918 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2919 indir_index);
2920
2921 for (unsigned i = 0; i < num_components + component; i++) {
2922 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2923 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2924 ctx->ac.i32_1, "");
2925 }
2926 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2927 return result;
2928 }
2929
2930 static void
2931 store_tcs_output(struct ac_shader_abi *abi,
2932 LLVMValueRef vertex_index,
2933 LLVMValueRef param_index,
2934 unsigned const_index,
2935 unsigned location,
2936 unsigned driver_location,
2937 LLVMValueRef src,
2938 unsigned component,
2939 bool is_patch,
2940 bool is_compact,
2941 unsigned writemask)
2942 {
2943 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2944 LLVMValueRef dw_addr;
2945 LLVMValueRef stride = NULL;
2946 LLVMValueRef buf_addr = NULL;
2947 unsigned param;
2948 bool store_lds = true;
2949
2950 if (is_patch) {
2951 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2952 store_lds = false;
2953 } else {
2954 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2955 store_lds = false;
2956 }
2957
2958 param = shader_io_get_unique_index(location);
2959 if (location == VARYING_SLOT_CLIP_DIST0 &&
2960 is_compact && const_index > 3) {
2961 const_index -= 3;
2962 param++;
2963 }
2964
2965 if (!is_patch) {
2966 stride = get_tcs_out_vertex_stride(ctx);
2967 dw_addr = get_tcs_out_current_patch_offset(ctx);
2968 } else {
2969 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2970 }
2971
2972 mark_tess_output(ctx, is_patch, param);
2973
2974 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2975 param_index);
2976 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2977 vertex_index, param_index);
2978
2979 bool is_tess_factor = false;
2980 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2981 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2982 is_tess_factor = true;
2983
2984 unsigned base = is_compact ? const_index : 0;
2985 for (unsigned chan = 0; chan < 8; chan++) {
2986 if (!(writemask & (1 << chan)))
2987 continue;
2988 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2989
2990 if (store_lds || is_tess_factor) {
2991 LLVMValueRef dw_addr_chan =
2992 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2993 LLVMConstInt(ctx->ac.i32, chan, false), "");
2994 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2995 }
2996
2997 if (!is_tess_factor && writemask != 0xF)
2998 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2999 buf_addr, ctx->oc_lds,
3000 4 * (base + chan), 1, 0, true, false);
3001 }
3002
3003 if (writemask == 0xF) {
3004 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3005 buf_addr, ctx->oc_lds,
3006 (base * 4), 1, 0, true, false);
3007 }
3008 }
3009
3010 static LLVMValueRef
3011 load_tes_input(struct ac_shader_abi *abi,
3012 LLVMTypeRef type,
3013 LLVMValueRef vertex_index,
3014 LLVMValueRef param_index,
3015 unsigned const_index,
3016 unsigned location,
3017 unsigned driver_location,
3018 unsigned component,
3019 unsigned num_components,
3020 bool is_patch,
3021 bool is_compact,
3022 bool load_input)
3023 {
3024 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3025 LLVMValueRef buf_addr;
3026 LLVMValueRef result;
3027 unsigned param = shader_io_get_unique_index(location);
3028
3029 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3030 const_index -= 3;
3031 param++;
3032 }
3033
3034 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3035 is_compact, vertex_index, param_index);
3036
3037 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3038 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3039
3040 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3041 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3042 result = trim_vector(&ctx->ac, result, num_components);
3043 return result;
3044 }
3045
3046 static LLVMValueRef
3047 load_gs_input(struct ac_shader_abi *abi,
3048 unsigned location,
3049 unsigned driver_location,
3050 unsigned component,
3051 unsigned num_components,
3052 unsigned vertex_index,
3053 unsigned const_index,
3054 LLVMTypeRef type)
3055 {
3056 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3057 LLVMValueRef vtx_offset;
3058 unsigned param, vtx_offset_param;
3059 LLVMValueRef value[4], result;
3060
3061 vtx_offset_param = vertex_index;
3062 assert(vtx_offset_param < 6);
3063 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3064 LLVMConstInt(ctx->ac.i32, 4, false), "");
3065
3066 param = shader_io_get_unique_index(location);
3067
3068 for (unsigned i = component; i < num_components + component; i++) {
3069 if (ctx->ac.chip_class >= GFX9) {
3070 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3071 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3072 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3073 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3074 } else {
3075 LLVMValueRef soffset =
3076 LLVMConstInt(ctx->ac.i32,
3077 (param * 4 + i + const_index) * 256,
3078 false);
3079
3080 value[i] = ac_build_buffer_load(&ctx->ac,
3081 ctx->esgs_ring, 1,
3082 ctx->ac.i32_0,
3083 vtx_offset, soffset,
3084 0, 1, 0, true, false);
3085
3086 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3087 type, "");
3088 }
3089 }
3090 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3091 result = ac_to_integer(&ctx->ac, result);
3092 return result;
3093 }
3094
3095 static LLVMValueRef
3096 build_gep_for_deref(struct ac_nir_context *ctx,
3097 nir_deref_var *deref)
3098 {
3099 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3100 assert(entry->data);
3101 LLVMValueRef val = entry->data;
3102 nir_deref *tail = deref->deref.child;
3103 while (tail != NULL) {
3104 LLVMValueRef offset;
3105 switch (tail->deref_type) {
3106 case nir_deref_type_array: {
3107 nir_deref_array *array = nir_deref_as_array(tail);
3108 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3109 if (array->deref_array_type ==
3110 nir_deref_array_type_indirect) {
3111 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3112 get_src(ctx,
3113 array->indirect),
3114 "");
3115 }
3116 break;
3117 }
3118 case nir_deref_type_struct: {
3119 nir_deref_struct *deref_struct =
3120 nir_deref_as_struct(tail);
3121 offset = LLVMConstInt(ctx->ac.i32,
3122 deref_struct->index, 0);
3123 break;
3124 }
3125 default:
3126 unreachable("bad deref type");
3127 }
3128 val = ac_build_gep0(&ctx->ac, val, offset);
3129 tail = tail->child;
3130 }
3131 return val;
3132 }
3133
3134 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3135 nir_intrinsic_instr *instr,
3136 bool load_inputs)
3137 {
3138 LLVMValueRef result;
3139 LLVMValueRef vertex_index = NULL;
3140 LLVMValueRef indir_index = NULL;
3141 unsigned const_index = 0;
3142 unsigned location = instr->variables[0]->var->data.location;
3143 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3144 const bool is_patch = instr->variables[0]->var->data.patch;
3145 const bool is_compact = instr->variables[0]->var->data.compact;
3146
3147 get_deref_offset(ctx, instr->variables[0],
3148 false, NULL, is_patch ? NULL : &vertex_index,
3149 &const_index, &indir_index);
3150
3151 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3152
3153 LLVMTypeRef src_component_type;
3154 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3155 src_component_type = LLVMGetElementType(dest_type);
3156 else
3157 src_component_type = dest_type;
3158
3159 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3160 vertex_index, indir_index,
3161 const_index, location, driver_location,
3162 instr->variables[0]->var->data.location_frac,
3163 instr->num_components,
3164 is_patch, is_compact, load_inputs);
3165 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3166 }
3167
3168 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3169 nir_intrinsic_instr *instr)
3170 {
3171 LLVMValueRef values[8];
3172 int idx = instr->variables[0]->var->data.driver_location;
3173 int ve = instr->dest.ssa.num_components;
3174 unsigned comp = instr->variables[0]->var->data.location_frac;
3175 LLVMValueRef indir_index;
3176 LLVMValueRef ret;
3177 unsigned const_index;
3178 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3179 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3180 instr->variables[0]->var->data.mode == nir_var_shader_in;
3181 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3182 &const_index, &indir_index);
3183
3184 if (instr->dest.ssa.bit_size == 64)
3185 ve *= 2;
3186
3187 switch (instr->variables[0]->var->data.mode) {
3188 case nir_var_shader_in:
3189 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3190 ctx->stage == MESA_SHADER_TESS_EVAL) {
3191 return load_tess_varyings(ctx, instr, true);
3192 }
3193
3194 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3195 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3196 LLVMValueRef indir_index;
3197 unsigned const_index, vertex_index;
3198 get_deref_offset(ctx, instr->variables[0],
3199 false, &vertex_index, NULL,
3200 &const_index, &indir_index);
3201
3202 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3203 instr->variables[0]->var->data.driver_location,
3204 instr->variables[0]->var->data.location_frac, ve,
3205 vertex_index, const_index, type);
3206 }
3207
3208 for (unsigned chan = comp; chan < ve + comp; chan++) {
3209 if (indir_index) {
3210 unsigned count = glsl_count_attribute_slots(
3211 instr->variables[0]->var->type,
3212 ctx->stage == MESA_SHADER_VERTEX);
3213 count -= chan / 4;
3214 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3215 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3216 stride, false, true);
3217
3218 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3219 tmp_vec,
3220 indir_index, "");
3221 } else
3222 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3223 }
3224 break;
3225 case nir_var_local:
3226 for (unsigned chan = 0; chan < ve; chan++) {
3227 if (indir_index) {
3228 unsigned count = glsl_count_attribute_slots(
3229 instr->variables[0]->var->type, false);
3230 count -= chan / 4;
3231 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3232 &ctx->ac, ctx->locals + idx + chan, count,
3233 stride, true, true);
3234
3235 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3236 tmp_vec,
3237 indir_index, "");
3238 } else {
3239 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3240 }
3241 }
3242 break;
3243 case nir_var_shared: {
3244 LLVMValueRef address = build_gep_for_deref(ctx,
3245 instr->variables[0]);
3246 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3247 return LLVMBuildBitCast(ctx->ac.builder, val,
3248 get_def_type(ctx, &instr->dest.ssa),
3249 "");
3250 }
3251 case nir_var_shader_out:
3252 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3253 return load_tess_varyings(ctx, instr, false);
3254 }
3255
3256 for (unsigned chan = comp; chan < ve + comp; chan++) {
3257 if (indir_index) {
3258 unsigned count = glsl_count_attribute_slots(
3259 instr->variables[0]->var->type, false);
3260 count -= chan / 4;
3261 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3262 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3263 stride, true, true);
3264
3265 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3266 tmp_vec,
3267 indir_index, "");
3268 } else {
3269 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3270 ctx->abi->outputs[idx + chan + const_index * stride],
3271 "");
3272 }
3273 }
3274 break;
3275 default:
3276 unreachable("unhandle variable mode");
3277 }
3278 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3279 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3280 }
3281
3282 static void
3283 visit_store_var(struct ac_nir_context *ctx,
3284 nir_intrinsic_instr *instr)
3285 {
3286 LLVMValueRef temp_ptr, value;
3287 int idx = instr->variables[0]->var->data.driver_location;
3288 unsigned comp = instr->variables[0]->var->data.location_frac;
3289 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3290 int writemask = instr->const_index[0] << comp;
3291 LLVMValueRef indir_index;
3292 unsigned const_index;
3293 get_deref_offset(ctx, instr->variables[0], false,
3294 NULL, NULL, &const_index, &indir_index);
3295
3296 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3297
3298 src = LLVMBuildBitCast(ctx->ac.builder, src,
3299 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3300 "");
3301
3302 writemask = widen_mask(writemask, 2);
3303 }
3304
3305 switch (instr->variables[0]->var->data.mode) {
3306 case nir_var_shader_out:
3307
3308 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3309 LLVMValueRef vertex_index = NULL;
3310 LLVMValueRef indir_index = NULL;
3311 unsigned const_index = 0;
3312 const unsigned location = instr->variables[0]->var->data.location;
3313 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3314 const unsigned comp = instr->variables[0]->var->data.location_frac;
3315 const bool is_patch = instr->variables[0]->var->data.patch;
3316 const bool is_compact = instr->variables[0]->var->data.compact;
3317
3318 get_deref_offset(ctx, instr->variables[0],
3319 false, NULL, is_patch ? NULL : &vertex_index,
3320 &const_index, &indir_index);
3321
3322 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3323 const_index, location, driver_location,
3324 src, comp, is_patch, is_compact, writemask);
3325 return;
3326 }
3327
3328 for (unsigned chan = 0; chan < 8; chan++) {
3329 int stride = 4;
3330 if (!(writemask & (1 << chan)))
3331 continue;
3332
3333 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3334
3335 if (instr->variables[0]->var->data.compact)
3336 stride = 1;
3337 if (indir_index) {
3338 unsigned count = glsl_count_attribute_slots(
3339 instr->variables[0]->var->type, false);
3340 count -= chan / 4;
3341 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3342 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3343 stride, true, true);
3344
3345 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3346 value, indir_index, "");
3347 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3348 count, stride, tmp_vec);
3349
3350 } else {
3351 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3352
3353 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3354 }
3355 }
3356 break;
3357 case nir_var_local:
3358 for (unsigned chan = 0; chan < 8; chan++) {
3359 if (!(writemask & (1 << chan)))
3360 continue;
3361
3362 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3363 if (indir_index) {
3364 unsigned count = glsl_count_attribute_slots(
3365 instr->variables[0]->var->type, false);
3366 count -= chan / 4;
3367 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3368 &ctx->ac, ctx->locals + idx + chan, count,
3369 4, true, true);
3370
3371 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3372 value, indir_index, "");
3373 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3374 count, 4, tmp_vec);
3375 } else {
3376 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3377
3378 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3379 }
3380 }
3381 break;
3382 case nir_var_shared: {
3383 int writemask = instr->const_index[0];
3384 LLVMValueRef address = build_gep_for_deref(ctx,
3385 instr->variables[0]);
3386 LLVMValueRef val = get_src(ctx, instr->src[0]);
3387 unsigned components =
3388 glsl_get_vector_elements(
3389 nir_deref_tail(&instr->variables[0]->deref)->type);
3390 if (writemask == (1 << components) - 1) {
3391 val = LLVMBuildBitCast(
3392 ctx->ac.builder, val,
3393 LLVMGetElementType(LLVMTypeOf(address)), "");
3394 LLVMBuildStore(ctx->ac.builder, val, address);
3395 } else {
3396 for (unsigned chan = 0; chan < 4; chan++) {
3397 if (!(writemask & (1 << chan)))
3398 continue;
3399 LLVMValueRef ptr =
3400 LLVMBuildStructGEP(ctx->ac.builder,
3401 address, chan, "");
3402 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3403 chan);
3404 src = LLVMBuildBitCast(
3405 ctx->ac.builder, src,
3406 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3407 LLVMBuildStore(ctx->ac.builder, src, ptr);
3408 }
3409 }
3410 break;
3411 }
3412 default:
3413 break;
3414 }
3415 }
3416
3417 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3418 {
3419 switch (dim) {
3420 case GLSL_SAMPLER_DIM_BUF:
3421 return 1;
3422 case GLSL_SAMPLER_DIM_1D:
3423 return array ? 2 : 1;
3424 case GLSL_SAMPLER_DIM_2D:
3425 return array ? 3 : 2;
3426 case GLSL_SAMPLER_DIM_MS:
3427 return array ? 4 : 3;
3428 case GLSL_SAMPLER_DIM_3D:
3429 case GLSL_SAMPLER_DIM_CUBE:
3430 return 3;
3431 case GLSL_SAMPLER_DIM_RECT:
3432 case GLSL_SAMPLER_DIM_SUBPASS:
3433 return 2;
3434 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3435 return 3;
3436 default:
3437 break;
3438 }
3439 return 0;
3440 }
3441
3442 static bool
3443 glsl_is_array_image(const struct glsl_type *type)
3444 {
3445 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3446
3447 if (glsl_sampler_type_is_array(type))
3448 return true;
3449
3450 return dim == GLSL_SAMPLER_DIM_CUBE ||
3451 dim == GLSL_SAMPLER_DIM_3D ||
3452 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3453 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3454 }
3455
3456
3457 /* Adjust the sample index according to FMASK.
3458 *
3459 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3460 * which is the identity mapping. Each nibble says which physical sample
3461 * should be fetched to get that sample.
3462 *
3463 * For example, 0x11111100 means there are only 2 samples stored and
3464 * the second sample covers 3/4 of the pixel. When reading samples 0
3465 * and 1, return physical sample 0 (determined by the first two 0s
3466 * in FMASK), otherwise return physical sample 1.
3467 *
3468 * The sample index should be adjusted as follows:
3469 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3470 */
3471 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3472 LLVMValueRef coord_x, LLVMValueRef coord_y,
3473 LLVMValueRef coord_z,
3474 LLVMValueRef sample_index,
3475 LLVMValueRef fmask_desc_ptr)
3476 {
3477 LLVMValueRef fmask_load_address[4];
3478 LLVMValueRef res;
3479
3480 fmask_load_address[0] = coord_x;
3481 fmask_load_address[1] = coord_y;
3482 if (coord_z) {
3483 fmask_load_address[2] = coord_z;
3484 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3485 }
3486
3487 struct ac_image_args args = {0};
3488
3489 args.opcode = ac_image_load;
3490 args.da = coord_z ? true : false;
3491 args.resource = fmask_desc_ptr;
3492 args.dmask = 0xf;
3493 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3494
3495 res = ac_build_image_opcode(ctx, &args);
3496
3497 res = ac_to_integer(ctx, res);
3498 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3499 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3500
3501 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3502 res,
3503 ctx->i32_0, "");
3504
3505 LLVMValueRef sample_index4 =
3506 LLVMBuildMul(ctx->builder, sample_index, four, "");
3507 LLVMValueRef shifted_fmask =
3508 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3509 LLVMValueRef final_sample =
3510 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3511
3512 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3513 * resource descriptor is 0 (invalid),
3514 */
3515 LLVMValueRef fmask_desc =
3516 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3517 ctx->v8i32, "");
3518
3519 LLVMValueRef fmask_word1 =
3520 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3521 ctx->i32_1, "");
3522
3523 LLVMValueRef word1_is_nonzero =
3524 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3525 fmask_word1, ctx->i32_0, "");
3526
3527 /* Replace the MSAA sample index. */
3528 sample_index =
3529 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3530 final_sample, sample_index, "");
3531 return sample_index;
3532 }
3533
3534 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3535 const nir_intrinsic_instr *instr)
3536 {
3537 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3538
3539 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3540 LLVMValueRef coords[4];
3541 LLVMValueRef masks[] = {
3542 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3543 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3544 };
3545 LLVMValueRef res;
3546 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3547
3548 int count;
3549 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3550 bool is_array = glsl_sampler_type_is_array(type);
3551 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3552 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3553 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3554 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3555 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3556 count = image_type_to_components_count(dim, is_array);
3557
3558 if (is_ms) {
3559 LLVMValueRef fmask_load_address[3];
3560 int chan;
3561
3562 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3563 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3564 if (is_array)
3565 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3566 else
3567 fmask_load_address[2] = NULL;
3568 if (add_frag_pos) {
3569 for (chan = 0; chan < 2; ++chan)
3570 fmask_load_address[chan] =
3571 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3572 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3573 ctx->ac.i32, ""), "");
3574 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3575 }
3576 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3577 fmask_load_address[0],
3578 fmask_load_address[1],
3579 fmask_load_address[2],
3580 sample_index,
3581 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3582 }
3583 if (count == 1 && !gfx9_1d) {
3584 if (instr->src[0].ssa->num_components)
3585 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3586 else
3587 res = src0;
3588 } else {
3589 int chan;
3590 if (is_ms)
3591 count--;
3592 for (chan = 0; chan < count; ++chan) {
3593 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3594 }
3595 if (add_frag_pos) {
3596 for (chan = 0; chan < 2; ++chan)
3597 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3598 ctx->ac.i32, ""), "");
3599 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3600 count++;
3601 }
3602
3603 if (gfx9_1d) {
3604 if (is_array) {
3605 coords[2] = coords[1];
3606 coords[1] = ctx->ac.i32_0;
3607 } else
3608 coords[1] = ctx->ac.i32_0;
3609 count++;
3610 }
3611
3612 if (is_ms) {
3613 coords[count] = sample_index;
3614 count++;
3615 }
3616
3617 if (count == 3) {
3618 coords[3] = LLVMGetUndef(ctx->ac.i32);
3619 count = 4;
3620 }
3621 res = ac_build_gather_values(&ctx->ac, coords, count);
3622 }
3623 return res;
3624 }
3625
3626 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3627 const nir_intrinsic_instr *instr)
3628 {
3629 LLVMValueRef params[7];
3630 LLVMValueRef res;
3631 char intrinsic_name[64];
3632 const nir_variable *var = instr->variables[0]->var;
3633 const struct glsl_type *type = var->type;
3634
3635 if(instr->variables[0]->deref.child)
3636 type = instr->variables[0]->deref.child->type;
3637
3638 type = glsl_without_array(type);
3639
3640 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3641 if (dim == GLSL_SAMPLER_DIM_BUF) {
3642 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3643 unsigned num_channels = util_last_bit(mask);
3644 LLVMValueRef rsrc, vindex;
3645
3646 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3647 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3648 ctx->ac.i32_0, "");
3649
3650 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3651 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3652 ctx->ac.i32_0, num_channels,
3653 false, false);
3654 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3655
3656 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3657 res = ac_to_integer(&ctx->ac, res);
3658 } else {
3659 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 LLVMValueRef slc = ctx->ac.i1false;
3662
3663 params[0] = get_image_coords(ctx, instr);
3664 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3665 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3666 params[3] = glc;
3667 params[4] = slc;
3668 params[5] = ctx->ac.i1false;
3669 params[6] = da;
3670
3671 ac_get_image_intr_name("llvm.amdgcn.image.load",
3672 ctx->ac.v4f32, /* vdata */
3673 LLVMTypeOf(params[0]), /* coords */
3674 LLVMTypeOf(params[1]), /* rsrc */
3675 intrinsic_name, sizeof(intrinsic_name));
3676
3677 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3678 params, 7, AC_FUNC_ATTR_READONLY);
3679 }
3680 return ac_to_integer(&ctx->ac, res);
3681 }
3682
3683 static void visit_image_store(struct ac_nir_context *ctx,
3684 nir_intrinsic_instr *instr)
3685 {
3686 LLVMValueRef params[8];
3687 char intrinsic_name[64];
3688 const nir_variable *var = instr->variables[0]->var;
3689 const struct glsl_type *type = glsl_without_array(var->type);
3690 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3691 LLVMValueRef glc = ctx->ac.i1false;
3692 bool force_glc = ctx->ac.chip_class == SI;
3693 if (force_glc)
3694 glc = ctx->ac.i1true;
3695
3696 if (dim == GLSL_SAMPLER_DIM_BUF) {
3697 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3698 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3699 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3700 ctx->ac.i32_0, ""); /* vindex */
3701 params[3] = ctx->ac.i32_0; /* voffset */
3702 params[4] = glc; /* glc */
3703 params[5] = ctx->ac.i1false; /* slc */
3704 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3705 params, 6, 0);
3706 } else {
3707 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3708 LLVMValueRef slc = ctx->ac.i1false;
3709
3710 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3711 params[1] = get_image_coords(ctx, instr); /* coords */
3712 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3713 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3714 params[4] = glc;
3715 params[5] = slc;
3716 params[6] = ctx->ac.i1false;
3717 params[7] = da;
3718
3719 ac_get_image_intr_name("llvm.amdgcn.image.store",
3720 LLVMTypeOf(params[0]), /* vdata */
3721 LLVMTypeOf(params[1]), /* coords */
3722 LLVMTypeOf(params[2]), /* rsrc */
3723 intrinsic_name, sizeof(intrinsic_name));
3724
3725 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3726 params, 8, 0);
3727 }
3728
3729 }
3730
3731 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3732 const nir_intrinsic_instr *instr)
3733 {
3734 LLVMValueRef params[7];
3735 int param_count = 0;
3736 const nir_variable *var = instr->variables[0]->var;
3737
3738 const char *atomic_name;
3739 char intrinsic_name[41];
3740 const struct glsl_type *type = glsl_without_array(var->type);
3741 MAYBE_UNUSED int length;
3742
3743 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3744
3745 switch (instr->intrinsic) {
3746 case nir_intrinsic_image_atomic_add:
3747 atomic_name = "add";
3748 break;
3749 case nir_intrinsic_image_atomic_min:
3750 atomic_name = is_unsigned ? "umin" : "smin";
3751 break;
3752 case nir_intrinsic_image_atomic_max:
3753 atomic_name = is_unsigned ? "umax" : "smax";
3754 break;
3755 case nir_intrinsic_image_atomic_and:
3756 atomic_name = "and";
3757 break;
3758 case nir_intrinsic_image_atomic_or:
3759 atomic_name = "or";
3760 break;
3761 case nir_intrinsic_image_atomic_xor:
3762 atomic_name = "xor";
3763 break;
3764 case nir_intrinsic_image_atomic_exchange:
3765 atomic_name = "swap";
3766 break;
3767 case nir_intrinsic_image_atomic_comp_swap:
3768 atomic_name = "cmpswap";
3769 break;
3770 default:
3771 abort();
3772 }
3773
3774 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3775 params[param_count++] = get_src(ctx, instr->src[3]);
3776 params[param_count++] = get_src(ctx, instr->src[2]);
3777
3778 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3779 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3780 NULL, true, true);
3781 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3782 ctx->ac.i32_0, ""); /* vindex */
3783 params[param_count++] = ctx->ac.i32_0; /* voffset */
3784 params[param_count++] = ctx->ac.i1false; /* slc */
3785
3786 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3787 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3788 } else {
3789 char coords_type[8];
3790
3791 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3792 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3793 NULL, true, true);
3794 params[param_count++] = ctx->ac.i1false; /* r128 */
3795 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3796 params[param_count++] = ctx->ac.i1false; /* slc */
3797
3798 build_int_type_name(LLVMTypeOf(coords),
3799 coords_type, sizeof(coords_type));
3800
3801 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3802 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3803 }
3804
3805 assert(length < sizeof(intrinsic_name));
3806 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3807 }
3808
3809 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3810 const nir_intrinsic_instr *instr)
3811 {
3812 const nir_variable *var = instr->variables[0]->var;
3813 const struct glsl_type *type = glsl_without_array(var->type);
3814
3815 struct ac_image_args args = { 0 };
3816 args.da = glsl_is_array_image(type);
3817 args.dmask = 0xf;
3818 args.resource = get_sampler_desc(ctx, instr->variables[0],
3819 AC_DESC_IMAGE, NULL, true, false);
3820 args.opcode = ac_image_get_resinfo;
3821 args.addr = ctx->ac.i32_0;
3822
3823 return ac_build_image_opcode(&ctx->ac, &args);
3824 }
3825
3826 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3827 const nir_intrinsic_instr *instr)
3828 {
3829 LLVMValueRef res;
3830 const nir_variable *var = instr->variables[0]->var;
3831 const struct glsl_type *type = glsl_without_array(var->type);
3832
3833 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3834 return get_buffer_size(ctx,
3835 get_sampler_desc(ctx, instr->variables[0],
3836 AC_DESC_BUFFER, NULL, true, false), true);
3837
3838 struct ac_image_args args = { 0 };
3839
3840 args.da = glsl_is_array_image(type);
3841 args.dmask = 0xf;
3842 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3843 args.opcode = ac_image_get_resinfo;
3844 args.addr = ctx->ac.i32_0;
3845
3846 res = ac_build_image_opcode(&ctx->ac, &args);
3847
3848 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3849
3850 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3851 glsl_sampler_type_is_array(type)) {
3852 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3853 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3854 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3855 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3856 }
3857 if (ctx->ac.chip_class >= GFX9 &&
3858 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3859 glsl_sampler_type_is_array(type)) {
3860 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3861 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3862 ctx->ac.i32_1, "");
3863
3864 }
3865 return res;
3866 }
3867
3868 #define NOOP_WAITCNT 0xf7f
3869 #define LGKM_CNT 0x07f
3870 #define VM_CNT 0xf70
3871
3872 static void emit_membar(struct ac_llvm_context *ac,
3873 const nir_intrinsic_instr *instr)
3874 {
3875 unsigned waitcnt = NOOP_WAITCNT;
3876
3877 switch (instr->intrinsic) {
3878 case nir_intrinsic_memory_barrier:
3879 case nir_intrinsic_group_memory_barrier:
3880 waitcnt &= VM_CNT & LGKM_CNT;
3881 break;
3882 case nir_intrinsic_memory_barrier_atomic_counter:
3883 case nir_intrinsic_memory_barrier_buffer:
3884 case nir_intrinsic_memory_barrier_image:
3885 waitcnt &= VM_CNT;
3886 break;
3887 case nir_intrinsic_memory_barrier_shared:
3888 waitcnt &= LGKM_CNT;
3889 break;
3890 default:
3891 break;
3892 }
3893 if (waitcnt != NOOP_WAITCNT)
3894 ac_build_waitcnt(ac, waitcnt);
3895 }
3896
3897 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3898 {
3899 /* SI only (thanks to a hw bug workaround):
3900 * The real barrier instruction isn’t needed, because an entire patch
3901 * always fits into a single wave.
3902 */
3903 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3904 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3905 return;
3906 }
3907 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3908 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3909 }
3910
3911 static void emit_discard(struct ac_nir_context *ctx,
3912 const nir_intrinsic_instr *instr)
3913 {
3914 LLVMValueRef cond;
3915
3916 if (instr->intrinsic == nir_intrinsic_discard_if) {
3917 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3918 get_src(ctx, instr->src[0]),
3919 ctx->ac.i32_0, "");
3920 } else {
3921 assert(instr->intrinsic == nir_intrinsic_discard);
3922 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3923 }
3924
3925 ac_build_kill_if_false(&ctx->ac, cond);
3926 }
3927
3928 static LLVMValueRef
3929 visit_load_helper_invocation(struct ac_nir_context *ctx)
3930 {
3931 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3932 "llvm.amdgcn.ps.live",
3933 ctx->ac.i1, NULL, 0,
3934 AC_FUNC_ATTR_READNONE);
3935 result = LLVMBuildNot(ctx->ac.builder, result, "");
3936 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3937 }
3938
3939 static LLVMValueRef
3940 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3941 {
3942 LLVMValueRef result;
3943 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3944 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3945 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3946
3947 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3948 }
3949
3950 static LLVMValueRef
3951 visit_load_shared(struct ac_nir_context *ctx,
3952 const nir_intrinsic_instr *instr)
3953 {
3954 LLVMValueRef values[4], derived_ptr, index, ret;
3955
3956 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3957
3958 for (int chan = 0; chan < instr->num_components; chan++) {
3959 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3960 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3961 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3962 }
3963
3964 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3965 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3966 }
3967
3968 static void
3969 visit_store_shared(struct ac_nir_context *ctx,
3970 const nir_intrinsic_instr *instr)
3971 {
3972 LLVMValueRef derived_ptr, data,index;
3973 LLVMBuilderRef builder = ctx->ac.builder;
3974
3975 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3976 LLVMValueRef src = get_src(ctx, instr->src[0]);
3977
3978 int writemask = nir_intrinsic_write_mask(instr);
3979 for (int chan = 0; chan < 4; chan++) {
3980 if (!(writemask & (1 << chan))) {
3981 continue;
3982 }
3983 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3984 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3985 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3986 LLVMBuildStore(builder, data, derived_ptr);
3987 }
3988 }
3989
3990 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3991 const nir_intrinsic_instr *instr,
3992 LLVMValueRef ptr)
3993 {
3994 LLVMValueRef result;
3995 LLVMValueRef src = get_src(ctx, instr->src[0]);
3996
3997 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3998 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3999 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
4000 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
4001 ptr, src, src1,
4002 LLVMAtomicOrderingSequentiallyConsistent,
4003 LLVMAtomicOrderingSequentiallyConsistent,
4004 false);
4005 } else {
4006 LLVMAtomicRMWBinOp op;
4007 switch (instr->intrinsic) {
4008 case nir_intrinsic_var_atomic_add:
4009 case nir_intrinsic_shared_atomic_add:
4010 op = LLVMAtomicRMWBinOpAdd;
4011 break;
4012 case nir_intrinsic_var_atomic_umin:
4013 case nir_intrinsic_shared_atomic_umin:
4014 op = LLVMAtomicRMWBinOpUMin;
4015 break;
4016 case nir_intrinsic_var_atomic_umax:
4017 case nir_intrinsic_shared_atomic_umax:
4018 op = LLVMAtomicRMWBinOpUMax;
4019 break;
4020 case nir_intrinsic_var_atomic_imin:
4021 case nir_intrinsic_shared_atomic_imin:
4022 op = LLVMAtomicRMWBinOpMin;
4023 break;
4024 case nir_intrinsic_var_atomic_imax:
4025 case nir_intrinsic_shared_atomic_imax:
4026 op = LLVMAtomicRMWBinOpMax;
4027 break;
4028 case nir_intrinsic_var_atomic_and:
4029 case nir_intrinsic_shared_atomic_and:
4030 op = LLVMAtomicRMWBinOpAnd;
4031 break;
4032 case nir_intrinsic_var_atomic_or:
4033 case nir_intrinsic_shared_atomic_or:
4034 op = LLVMAtomicRMWBinOpOr;
4035 break;
4036 case nir_intrinsic_var_atomic_xor:
4037 case nir_intrinsic_shared_atomic_xor:
4038 op = LLVMAtomicRMWBinOpXor;
4039 break;
4040 case nir_intrinsic_var_atomic_exchange:
4041 case nir_intrinsic_shared_atomic_exchange:
4042 op = LLVMAtomicRMWBinOpXchg;
4043 break;
4044 default:
4045 return NULL;
4046 }
4047
4048 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4049 LLVMAtomicOrderingSequentiallyConsistent,
4050 false);
4051 }
4052 return result;
4053 }
4054
4055 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4056 enum glsl_interp_mode interp, unsigned location)
4057 {
4058 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4059
4060 switch (interp) {
4061 case INTERP_MODE_FLAT:
4062 default:
4063 return NULL;
4064 case INTERP_MODE_SMOOTH:
4065 case INTERP_MODE_NONE:
4066 if (location == INTERP_CENTER)
4067 return ctx->persp_center;
4068 else if (location == INTERP_CENTROID)
4069 return ctx->persp_centroid;
4070 else if (location == INTERP_SAMPLE)
4071 return ctx->persp_sample;
4072 break;
4073 case INTERP_MODE_NOPERSPECTIVE:
4074 if (location == INTERP_CENTER)
4075 return ctx->linear_center;
4076 else if (location == INTERP_CENTROID)
4077 return ctx->linear_centroid;
4078 else if (location == INTERP_SAMPLE)
4079 return ctx->linear_sample;
4080 break;
4081 }
4082 return NULL;
4083 }
4084
4085 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4086 LLVMValueRef sample_id)
4087 {
4088 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4089
4090 LLVMValueRef result;
4091 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4092
4093 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4094 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4095
4096 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4097 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4098
4099 return result;
4100 }
4101
4102 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4103 {
4104 LLVMValueRef values[2];
4105
4106 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4107 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4108 return ac_build_gather_values(&ctx->ac, values, 2);
4109 }
4110
4111 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4112 {
4113 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4114 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4115 ctx->options->key.fs.log2_num_samples :
4116 ctx->options->key.fs.log2_ps_iter_samples;
4117
4118 /* The bit pattern matches that used by fixed function fragment
4119 * processing. */
4120 static const uint16_t ps_iter_masks[] = {
4121 0xffff, /* not used */
4122 0x5555,
4123 0x1111,
4124 0x0101,
4125 0x0001,
4126 };
4127 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4128
4129 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4130
4131 LLVMValueRef result, sample_id;
4132 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4133 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4134 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4135 return result;
4136 }
4137
4138 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4139 const nir_intrinsic_instr *instr)
4140 {
4141 LLVMValueRef result[4];
4142 LLVMValueRef interp_param, attr_number;
4143 unsigned location;
4144 unsigned chan;
4145 LLVMValueRef src_c0 = NULL;
4146 LLVMValueRef src_c1 = NULL;
4147 LLVMValueRef src0 = NULL;
4148 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4149 switch (instr->intrinsic) {
4150 case nir_intrinsic_interp_var_at_centroid:
4151 location = INTERP_CENTROID;
4152 break;
4153 case nir_intrinsic_interp_var_at_sample:
4154 case nir_intrinsic_interp_var_at_offset:
4155 location = INTERP_CENTER;
4156 src0 = get_src(ctx, instr->src[0]);
4157 break;
4158 default:
4159 break;
4160 }
4161
4162 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4163 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4164 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4165 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4166 LLVMValueRef sample_position;
4167 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4168
4169 /* fetch sample ID */
4170 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4171
4172 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4173 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4174 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4175 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4176 }
4177 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4178 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4179
4180 if (location == INTERP_CENTER) {
4181 LLVMValueRef ij_out[2];
4182 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4183
4184 /*
4185 * take the I then J parameters, and the DDX/Y for it, and
4186 * calculate the IJ inputs for the interpolator.
4187 * temp1 = ddx * offset/sample.x + I;
4188 * interp_param.I = ddy * offset/sample.y + temp1;
4189 * temp1 = ddx * offset/sample.x + J;
4190 * interp_param.J = ddy * offset/sample.y + temp1;
4191 */
4192 for (unsigned i = 0; i < 2; i++) {
4193 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4194 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4195 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4196 ddxy_out, ix_ll, "");
4197 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4198 ddxy_out, iy_ll, "");
4199 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4200 interp_param, ix_ll, "");
4201 LLVMValueRef temp1, temp2;
4202
4203 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4204 ctx->ac.f32, "");
4205
4206 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4207 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4208
4209 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4210 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4211
4212 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4213 temp2, ctx->ac.i32, "");
4214 }
4215 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4216
4217 }
4218
4219 for (chan = 0; chan < 4; chan++) {
4220 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4221
4222 if (interp_param) {
4223 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4224 interp_param, ctx->ac.v2f32, "");
4225 LLVMValueRef i = LLVMBuildExtractElement(
4226 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4227 LLVMValueRef j = LLVMBuildExtractElement(
4228 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4229
4230 result[chan] = ac_build_fs_interp(&ctx->ac,
4231 llvm_chan, attr_number,
4232 ctx->abi->prim_mask, i, j);
4233 } else {
4234 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4235 LLVMConstInt(ctx->ac.i32, 2, false),
4236 llvm_chan, attr_number,
4237 ctx->abi->prim_mask);
4238 }
4239 }
4240 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4241 instr->variables[0]->var->data.location_frac);
4242 }
4243
4244 static void
4245 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4246 {
4247 LLVMValueRef gs_next_vertex;
4248 LLVMValueRef can_emit;
4249 int idx;
4250 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4251
4252 assert(stream == 0);
4253
4254 /* Write vertex attribute values to GSVS ring */
4255 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4256 ctx->gs_next_vertex,
4257 "");
4258
4259 /* If this thread has already emitted the declared maximum number of
4260 * vertices, kill it: excessive vertex emissions are not supposed to
4261 * have any effect, and GS threads have no externally observable
4262 * effects other than emitting vertices.
4263 */
4264 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4265 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4266 ac_build_kill_if_false(&ctx->ac, can_emit);
4267
4268 /* loop num outputs */
4269 idx = 0;
4270 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4271 LLVMValueRef *out_ptr = &addrs[i * 4];
4272 int length = 4;
4273 int slot = idx;
4274 int slot_inc = 1;
4275
4276 if (!(ctx->output_mask & (1ull << i)))
4277 continue;
4278
4279 if (i == VARYING_SLOT_CLIP_DIST0) {
4280 /* pack clip and cull into a single set of slots */
4281 length = ctx->num_output_clips + ctx->num_output_culls;
4282 if (length > 4)
4283 slot_inc = 2;
4284 }
4285 for (unsigned j = 0; j < length; j++) {
4286 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4287 out_ptr[j], "");
4288 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4289 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4290 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4291
4292 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4293
4294 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4295 out_val, 1,
4296 voffset, ctx->gs2vs_offset, 0,
4297 1, 1, true, true);
4298 }
4299 idx += slot_inc;
4300 }
4301
4302 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4303 ctx->ac.i32_1, "");
4304 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4305
4306 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4307 }
4308
4309 static void
4310 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4311 {
4312 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4313 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4314 }
4315
4316 static LLVMValueRef
4317 load_tess_coord(struct ac_shader_abi *abi)
4318 {
4319 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4320
4321 LLVMValueRef coord[4] = {
4322 ctx->tes_u,
4323 ctx->tes_v,
4324 ctx->ac.f32_0,
4325 ctx->ac.f32_0,
4326 };
4327
4328 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4329 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4330 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4331
4332 return ac_build_gather_values(&ctx->ac, coord, 3);
4333 }
4334
4335 static LLVMValueRef
4336 load_patch_vertices_in(struct ac_shader_abi *abi)
4337 {
4338 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4339 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4340 }
4341
4342 static void visit_intrinsic(struct ac_nir_context *ctx,
4343 nir_intrinsic_instr *instr)
4344 {
4345 LLVMValueRef result = NULL;
4346
4347 switch (instr->intrinsic) {
4348 case nir_intrinsic_ballot:
4349 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4350 break;
4351 case nir_intrinsic_read_invocation:
4352 case nir_intrinsic_read_first_invocation: {
4353 LLVMValueRef args[2];
4354
4355 /* Value */
4356 args[0] = get_src(ctx, instr->src[0]);
4357
4358 unsigned num_args;
4359 const char *intr_name;
4360 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4361 num_args = 2;
4362 intr_name = "llvm.amdgcn.readlane";
4363
4364 /* Invocation */
4365 args[1] = get_src(ctx, instr->src[1]);
4366 } else {
4367 num_args = 1;
4368 intr_name = "llvm.amdgcn.readfirstlane";
4369 }
4370
4371 /* We currently have no other way to prevent LLVM from lifting the icmp
4372 * calls to a dominating basic block.
4373 */
4374 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4375
4376 result = ac_build_intrinsic(&ctx->ac, intr_name,
4377 ctx->ac.i32, args, num_args,
4378 AC_FUNC_ATTR_READNONE |
4379 AC_FUNC_ATTR_CONVERGENT);
4380 break;
4381 }
4382 case nir_intrinsic_load_subgroup_invocation:
4383 result = ac_get_thread_id(&ctx->ac);
4384 break;
4385 case nir_intrinsic_load_work_group_id: {
4386 LLVMValueRef values[3];
4387
4388 for (int i = 0; i < 3; i++) {
4389 values[i] = ctx->abi->workgroup_ids[i] ?
4390 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4391 }
4392
4393 result = ac_build_gather_values(&ctx->ac, values, 3);
4394 break;
4395 }
4396 case nir_intrinsic_load_base_vertex: {
4397 result = ctx->abi->base_vertex;
4398 break;
4399 }
4400 case nir_intrinsic_load_local_group_size:
4401 result = ctx->abi->load_local_group_size(ctx->abi);
4402 break;
4403 case nir_intrinsic_load_vertex_id_zero_base: {
4404 result = ctx->abi->vertex_id;
4405 break;
4406 }
4407 case nir_intrinsic_load_local_invocation_id: {
4408 result = ctx->abi->local_invocation_ids;
4409 break;
4410 }
4411 case nir_intrinsic_load_base_instance:
4412 result = ctx->abi->start_instance;
4413 break;
4414 case nir_intrinsic_load_draw_id:
4415 result = ctx->abi->draw_id;
4416 break;
4417 case nir_intrinsic_load_view_index:
4418 result = ctx->abi->view_index;
4419 break;
4420 case nir_intrinsic_load_invocation_id:
4421 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4422 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4423 else
4424 result = ctx->abi->gs_invocation_id;
4425 break;
4426 case nir_intrinsic_load_primitive_id:
4427 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4428 result = ctx->abi->gs_prim_id;
4429 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4430 result = ctx->abi->tcs_patch_id;
4431 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4432 result = ctx->abi->tes_patch_id;
4433 } else
4434 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4435 break;
4436 case nir_intrinsic_load_sample_id:
4437 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4438 break;
4439 case nir_intrinsic_load_sample_pos:
4440 result = load_sample_pos(ctx);
4441 break;
4442 case nir_intrinsic_load_sample_mask_in:
4443 result = ctx->abi->load_sample_mask_in(ctx->abi);
4444 break;
4445 case nir_intrinsic_load_frag_coord: {
4446 LLVMValueRef values[4] = {
4447 ctx->abi->frag_pos[0],
4448 ctx->abi->frag_pos[1],
4449 ctx->abi->frag_pos[2],
4450 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4451 };
4452 result = ac_build_gather_values(&ctx->ac, values, 4);
4453 break;
4454 }
4455 case nir_intrinsic_load_front_face:
4456 result = ctx->abi->front_face;
4457 break;
4458 case nir_intrinsic_load_helper_invocation:
4459 result = visit_load_helper_invocation(ctx);
4460 break;
4461 case nir_intrinsic_load_instance_id:
4462 result = ctx->abi->instance_id;
4463 break;
4464 case nir_intrinsic_load_num_work_groups:
4465 result = ctx->abi->num_work_groups;
4466 break;
4467 case nir_intrinsic_load_local_invocation_index:
4468 result = visit_load_local_invocation_index(ctx);
4469 break;
4470 case nir_intrinsic_load_push_constant:
4471 result = visit_load_push_constant(ctx, instr);
4472 break;
4473 case nir_intrinsic_vulkan_resource_index: {
4474 LLVMValueRef index = get_src(ctx, instr->src[0]);
4475 unsigned desc_set = nir_intrinsic_desc_set(instr);
4476 unsigned binding = nir_intrinsic_binding(instr);
4477
4478 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4479 binding);
4480 break;
4481 }
4482 case nir_intrinsic_vulkan_resource_reindex:
4483 result = visit_vulkan_resource_reindex(ctx, instr);
4484 break;
4485 case nir_intrinsic_store_ssbo:
4486 visit_store_ssbo(ctx, instr);
4487 break;
4488 case nir_intrinsic_load_ssbo:
4489 result = visit_load_buffer(ctx, instr);
4490 break;
4491 case nir_intrinsic_ssbo_atomic_add:
4492 case nir_intrinsic_ssbo_atomic_imin:
4493 case nir_intrinsic_ssbo_atomic_umin:
4494 case nir_intrinsic_ssbo_atomic_imax:
4495 case nir_intrinsic_ssbo_atomic_umax:
4496 case nir_intrinsic_ssbo_atomic_and:
4497 case nir_intrinsic_ssbo_atomic_or:
4498 case nir_intrinsic_ssbo_atomic_xor:
4499 case nir_intrinsic_ssbo_atomic_exchange:
4500 case nir_intrinsic_ssbo_atomic_comp_swap:
4501 result = visit_atomic_ssbo(ctx, instr);
4502 break;
4503 case nir_intrinsic_load_ubo:
4504 result = visit_load_ubo_buffer(ctx, instr);
4505 break;
4506 case nir_intrinsic_get_buffer_size:
4507 result = visit_get_buffer_size(ctx, instr);
4508 break;
4509 case nir_intrinsic_load_var:
4510 result = visit_load_var(ctx, instr);
4511 break;
4512 case nir_intrinsic_store_var:
4513 visit_store_var(ctx, instr);
4514 break;
4515 case nir_intrinsic_load_shared:
4516 result = visit_load_shared(ctx, instr);
4517 break;
4518 case nir_intrinsic_store_shared:
4519 visit_store_shared(ctx, instr);
4520 break;
4521 case nir_intrinsic_image_samples:
4522 result = visit_image_samples(ctx, instr);
4523 break;
4524 case nir_intrinsic_image_load:
4525 result = visit_image_load(ctx, instr);
4526 break;
4527 case nir_intrinsic_image_store:
4528 visit_image_store(ctx, instr);
4529 break;
4530 case nir_intrinsic_image_atomic_add:
4531 case nir_intrinsic_image_atomic_min:
4532 case nir_intrinsic_image_atomic_max:
4533 case nir_intrinsic_image_atomic_and:
4534 case nir_intrinsic_image_atomic_or:
4535 case nir_intrinsic_image_atomic_xor:
4536 case nir_intrinsic_image_atomic_exchange:
4537 case nir_intrinsic_image_atomic_comp_swap:
4538 result = visit_image_atomic(ctx, instr);
4539 break;
4540 case nir_intrinsic_image_size:
4541 result = visit_image_size(ctx, instr);
4542 break;
4543 case nir_intrinsic_shader_clock:
4544 result = ac_build_shader_clock(&ctx->ac);
4545 break;
4546 case nir_intrinsic_discard:
4547 case nir_intrinsic_discard_if:
4548 emit_discard(ctx, instr);
4549 break;
4550 case nir_intrinsic_memory_barrier:
4551 case nir_intrinsic_group_memory_barrier:
4552 case nir_intrinsic_memory_barrier_atomic_counter:
4553 case nir_intrinsic_memory_barrier_buffer:
4554 case nir_intrinsic_memory_barrier_image:
4555 case nir_intrinsic_memory_barrier_shared:
4556 emit_membar(&ctx->ac, instr);
4557 break;
4558 case nir_intrinsic_barrier:
4559 emit_barrier(&ctx->ac, ctx->stage);
4560 break;
4561 case nir_intrinsic_shared_atomic_add:
4562 case nir_intrinsic_shared_atomic_imin:
4563 case nir_intrinsic_shared_atomic_umin:
4564 case nir_intrinsic_shared_atomic_imax:
4565 case nir_intrinsic_shared_atomic_umax:
4566 case nir_intrinsic_shared_atomic_and:
4567 case nir_intrinsic_shared_atomic_or:
4568 case nir_intrinsic_shared_atomic_xor:
4569 case nir_intrinsic_shared_atomic_exchange:
4570 case nir_intrinsic_shared_atomic_comp_swap: {
4571 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4572 result = visit_var_atomic(ctx, instr, ptr);
4573 break;
4574 }
4575 case nir_intrinsic_var_atomic_add:
4576 case nir_intrinsic_var_atomic_imin:
4577 case nir_intrinsic_var_atomic_umin:
4578 case nir_intrinsic_var_atomic_imax:
4579 case nir_intrinsic_var_atomic_umax:
4580 case nir_intrinsic_var_atomic_and:
4581 case nir_intrinsic_var_atomic_or:
4582 case nir_intrinsic_var_atomic_xor:
4583 case nir_intrinsic_var_atomic_exchange:
4584 case nir_intrinsic_var_atomic_comp_swap: {
4585 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4586 result = visit_var_atomic(ctx, instr, ptr);
4587 break;
4588 }
4589 case nir_intrinsic_interp_var_at_centroid:
4590 case nir_intrinsic_interp_var_at_sample:
4591 case nir_intrinsic_interp_var_at_offset:
4592 result = visit_interp(ctx, instr);
4593 break;
4594 case nir_intrinsic_emit_vertex:
4595 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4596 break;
4597 case nir_intrinsic_end_primitive:
4598 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4599 break;
4600 case nir_intrinsic_load_tess_coord:
4601 result = ctx->abi->load_tess_coord(ctx->abi);
4602 break;
4603 case nir_intrinsic_load_tess_level_outer:
4604 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4605 break;
4606 case nir_intrinsic_load_tess_level_inner:
4607 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4608 break;
4609 case nir_intrinsic_load_patch_vertices_in:
4610 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4611 break;
4612 case nir_intrinsic_vote_all: {
4613 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4614 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4615 break;
4616 }
4617 case nir_intrinsic_vote_any: {
4618 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4619 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4620 break;
4621 }
4622 case nir_intrinsic_vote_eq: {
4623 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4624 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4625 break;
4626 }
4627 default:
4628 fprintf(stderr, "Unknown intrinsic: ");
4629 nir_print_instr(&instr->instr, stderr);
4630 fprintf(stderr, "\n");
4631 break;
4632 }
4633 if (result) {
4634 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4635 }
4636 }
4637
4638 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4639 LLVMValueRef buffer_ptr, bool write)
4640 {
4641 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4642 LLVMValueRef result;
4643
4644 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4645
4646 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4647 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4648
4649 return result;
4650 }
4651
4652 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4653 {
4654 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4655 LLVMValueRef result;
4656
4657 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4658
4659 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4660 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4661
4662 return result;
4663 }
4664
4665 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4666 unsigned descriptor_set,
4667 unsigned base_index,
4668 unsigned constant_index,
4669 LLVMValueRef index,
4670 enum ac_descriptor_type desc_type,
4671 bool image, bool write)
4672 {
4673 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4674 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4675 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4676 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4677 unsigned offset = binding->offset;
4678 unsigned stride = binding->size;
4679 unsigned type_size;
4680 LLVMBuilderRef builder = ctx->ac.builder;
4681 LLVMTypeRef type;
4682
4683 assert(base_index < layout->binding_count);
4684
4685 switch (desc_type) {
4686 case AC_DESC_IMAGE:
4687 type = ctx->ac.v8i32;
4688 type_size = 32;
4689 break;
4690 case AC_DESC_FMASK:
4691 type = ctx->ac.v8i32;
4692 offset += 32;
4693 type_size = 32;
4694 break;
4695 case AC_DESC_SAMPLER:
4696 type = ctx->ac.v4i32;
4697 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4698 offset += 64;
4699
4700 type_size = 16;
4701 break;
4702 case AC_DESC_BUFFER:
4703 type = ctx->ac.v4i32;
4704 type_size = 16;
4705 break;
4706 default:
4707 unreachable("invalid desc_type\n");
4708 }
4709
4710 offset += constant_index * stride;
4711
4712 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4713 (!index || binding->immutable_samplers_equal)) {
4714 if (binding->immutable_samplers_equal)
4715 constant_index = 0;
4716
4717 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4718
4719 LLVMValueRef constants[] = {
4720 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4721 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4722 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4723 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4724 };
4725 return ac_build_gather_values(&ctx->ac, constants, 4);
4726 }
4727
4728 assert(stride % type_size == 0);
4729
4730 if (!index)
4731 index = ctx->ac.i32_0;
4732
4733 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4734
4735 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4736 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4737
4738 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4739 }
4740
4741 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4742 const nir_deref_var *deref,
4743 enum ac_descriptor_type desc_type,
4744 const nir_tex_instr *tex_instr,
4745 bool image, bool write)
4746 {
4747 LLVMValueRef index = NULL;
4748 unsigned constant_index = 0;
4749 unsigned descriptor_set;
4750 unsigned base_index;
4751
4752 if (!deref) {
4753 assert(tex_instr && !image);
4754 descriptor_set = 0;
4755 base_index = tex_instr->sampler_index;
4756 } else {
4757 const nir_deref *tail = &deref->deref;
4758 while (tail->child) {
4759 const nir_deref_array *child = nir_deref_as_array(tail->child);
4760 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4761
4762 if (!array_size)
4763 array_size = 1;
4764
4765 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4766
4767 if (child->deref_array_type == nir_deref_array_type_indirect) {
4768 LLVMValueRef indirect = get_src(ctx, child->indirect);
4769
4770 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4771 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4772
4773 if (!index)
4774 index = indirect;
4775 else
4776 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4777 }
4778
4779 constant_index += child->base_offset * array_size;
4780
4781 tail = &child->deref;
4782 }
4783 descriptor_set = deref->var->data.descriptor_set;
4784 base_index = deref->var->data.binding;
4785 }
4786
4787 return ctx->abi->load_sampler_desc(ctx->abi,
4788 descriptor_set,
4789 base_index,
4790 constant_index, index,
4791 desc_type, image, write);
4792 }
4793
4794 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4795 struct ac_image_args *args,
4796 const nir_tex_instr *instr,
4797 nir_texop op,
4798 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4799 LLVMValueRef *param, unsigned count,
4800 unsigned dmask)
4801 {
4802 unsigned is_rect = 0;
4803 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4804
4805 if (op == nir_texop_lod)
4806 da = false;
4807 /* Pad to power of two vector */
4808 while (count < util_next_power_of_two(count))
4809 param[count++] = LLVMGetUndef(ctx->i32);
4810
4811 if (count > 1)
4812 args->addr = ac_build_gather_values(ctx, param, count);
4813 else
4814 args->addr = param[0];
4815
4816 args->resource = res_ptr;
4817 args->sampler = samp_ptr;
4818
4819 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4820 args->addr = param[0];
4821 return;
4822 }
4823
4824 args->dmask = dmask;
4825 args->unorm = is_rect;
4826 args->da = da;
4827 }
4828
4829 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4830 *
4831 * SI-CI:
4832 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4833 * filtering manually. The driver sets img7 to a mask clearing
4834 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4835 * s_and_b32 samp0, samp0, img7
4836 *
4837 * VI:
4838 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4839 */
4840 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4841 LLVMValueRef res, LLVMValueRef samp)
4842 {
4843 LLVMBuilderRef builder = ctx->ac.builder;
4844 LLVMValueRef img7, samp0;
4845
4846 if (ctx->ac.chip_class >= VI)
4847 return samp;
4848
4849 img7 = LLVMBuildExtractElement(builder, res,
4850 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4851 samp0 = LLVMBuildExtractElement(builder, samp,
4852 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4853 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4854 return LLVMBuildInsertElement(builder, samp, samp0,
4855 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4856 }
4857
4858 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4859 nir_tex_instr *instr,
4860 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4861 LLVMValueRef *fmask_ptr)
4862 {
4863 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4864 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4865 else
4866 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4867 if (samp_ptr) {
4868 if (instr->sampler)
4869 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4870 else
4871 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4872 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4873 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4874 }
4875 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4876 instr->op == nir_texop_samples_identical))
4877 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4878 }
4879
4880 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4881 LLVMValueRef coord)
4882 {
4883 coord = ac_to_float(ctx, coord);
4884 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4885 coord = ac_to_integer(ctx, coord);
4886 return coord;
4887 }
4888
4889 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4890 {
4891 LLVMValueRef result = NULL;
4892 struct ac_image_args args = { 0 };
4893 unsigned dmask = 0xf;
4894 LLVMValueRef address[16];
4895 LLVMValueRef coords[5];
4896 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4897 LLVMValueRef bias = NULL, offsets = NULL;
4898 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4899 LLVMValueRef ddx = NULL, ddy = NULL;
4900 LLVMValueRef derivs[6];
4901 unsigned chan, count = 0;
4902 unsigned const_src = 0, num_deriv_comp = 0;
4903 bool lod_is_zero = false;
4904
4905 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4906
4907 for (unsigned i = 0; i < instr->num_srcs; i++) {
4908 switch (instr->src[i].src_type) {
4909 case nir_tex_src_coord:
4910 coord = get_src(ctx, instr->src[i].src);
4911 break;
4912 case nir_tex_src_projector:
4913 break;
4914 case nir_tex_src_comparator:
4915 comparator = get_src(ctx, instr->src[i].src);
4916 break;
4917 case nir_tex_src_offset:
4918 offsets = get_src(ctx, instr->src[i].src);
4919 const_src = i;
4920 break;
4921 case nir_tex_src_bias:
4922 bias = get_src(ctx, instr->src[i].src);
4923 break;
4924 case nir_tex_src_lod: {
4925 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4926
4927 if (val && val->i32[0] == 0)
4928 lod_is_zero = true;
4929 lod = get_src(ctx, instr->src[i].src);
4930 break;
4931 }
4932 case nir_tex_src_ms_index:
4933 sample_index = get_src(ctx, instr->src[i].src);
4934 break;
4935 case nir_tex_src_ms_mcs:
4936 break;
4937 case nir_tex_src_ddx:
4938 ddx = get_src(ctx, instr->src[i].src);
4939 num_deriv_comp = instr->src[i].src.ssa->num_components;
4940 break;
4941 case nir_tex_src_ddy:
4942 ddy = get_src(ctx, instr->src[i].src);
4943 break;
4944 case nir_tex_src_texture_offset:
4945 case nir_tex_src_sampler_offset:
4946 case nir_tex_src_plane:
4947 default:
4948 break;
4949 }
4950 }
4951
4952 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4953 result = get_buffer_size(ctx, res_ptr, true);
4954 goto write_result;
4955 }
4956
4957 if (instr->op == nir_texop_texture_samples) {
4958 LLVMValueRef res, samples, is_msaa;
4959 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4960 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4961 LLVMConstInt(ctx->ac.i32, 3, false), "");
4962 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4963 LLVMConstInt(ctx->ac.i32, 28, false), "");
4964 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4965 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4966 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4967 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4968
4969 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4970 LLVMConstInt(ctx->ac.i32, 16, false), "");
4971 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4972 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4973 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4974 samples, "");
4975 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4976 ctx->ac.i32_1, "");
4977 result = samples;
4978 goto write_result;
4979 }
4980
4981 if (coord)
4982 for (chan = 0; chan < instr->coord_components; chan++)
4983 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4984
4985 if (offsets && instr->op != nir_texop_txf) {
4986 LLVMValueRef offset[3], pack;
4987 for (chan = 0; chan < 3; ++chan)
4988 offset[chan] = ctx->ac.i32_0;
4989
4990 args.offset = true;
4991 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4992 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4993 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4994 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4995 if (chan)
4996 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4997 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4998 }
4999 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
5000 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
5001 address[count++] = pack;
5002
5003 }
5004 /* pack LOD bias value */
5005 if (instr->op == nir_texop_txb && bias) {
5006 address[count++] = bias;
5007 }
5008
5009 /* Pack depth comparison value */
5010 if (instr->is_shadow && comparator) {
5011 LLVMValueRef z = ac_to_float(&ctx->ac,
5012 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5013
5014 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5015 * so the depth comparison value isn't clamped for Z16 and
5016 * Z24 anymore. Do it manually here.
5017 *
5018 * It's unnecessary if the original texture format was
5019 * Z32_FLOAT, but we don't know that here.
5020 */
5021 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5022 z = ac_build_clamp(&ctx->ac, z);
5023
5024 address[count++] = z;
5025 }
5026
5027 /* pack derivatives */
5028 if (ddx || ddy) {
5029 int num_src_deriv_channels, num_dest_deriv_channels;
5030 switch (instr->sampler_dim) {
5031 case GLSL_SAMPLER_DIM_3D:
5032 case GLSL_SAMPLER_DIM_CUBE:
5033 num_deriv_comp = 3;
5034 num_src_deriv_channels = 3;
5035 num_dest_deriv_channels = 3;
5036 break;
5037 case GLSL_SAMPLER_DIM_2D:
5038 default:
5039 num_src_deriv_channels = 2;
5040 num_dest_deriv_channels = 2;
5041 num_deriv_comp = 2;
5042 break;
5043 case GLSL_SAMPLER_DIM_1D:
5044 num_src_deriv_channels = 1;
5045 if (ctx->ac.chip_class >= GFX9) {
5046 num_dest_deriv_channels = 2;
5047 num_deriv_comp = 2;
5048 } else {
5049 num_dest_deriv_channels = 1;
5050 num_deriv_comp = 1;
5051 }
5052 break;
5053 }
5054
5055 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5056 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5057 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5058 }
5059 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5060 derivs[i] = ctx->ac.f32_0;
5061 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5062 }
5063 }
5064
5065 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5066 for (chan = 0; chan < instr->coord_components; chan++)
5067 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5068 if (instr->coord_components == 3)
5069 coords[3] = LLVMGetUndef(ctx->ac.f32);
5070 ac_prepare_cube_coords(&ctx->ac,
5071 instr->op == nir_texop_txd, instr->is_array,
5072 instr->op == nir_texop_lod, coords, derivs);
5073 if (num_deriv_comp)
5074 num_deriv_comp--;
5075 }
5076
5077 if (ddx || ddy) {
5078 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5079 address[count++] = derivs[i];
5080 }
5081
5082 /* Pack texture coordinates */
5083 if (coord) {
5084 address[count++] = coords[0];
5085 if (instr->coord_components > 1) {
5086 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5087 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5088 }
5089 address[count++] = coords[1];
5090 }
5091 if (instr->coord_components > 2) {
5092 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5093 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5094 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5095 instr->op != nir_texop_txf) {
5096 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5097 }
5098 address[count++] = coords[2];
5099 }
5100
5101 if (ctx->ac.chip_class >= GFX9) {
5102 LLVMValueRef filler;
5103 if (instr->op == nir_texop_txf)
5104 filler = ctx->ac.i32_0;
5105 else
5106 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5107
5108 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5109 /* No nir_texop_lod, because it does not take a slice
5110 * even with array textures. */
5111 if (instr->is_array && instr->op != nir_texop_lod ) {
5112 address[count] = address[count - 1];
5113 address[count - 1] = filler;
5114 count++;
5115 } else
5116 address[count++] = filler;
5117 }
5118 }
5119 }
5120
5121 /* Pack LOD */
5122 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5123 instr->op == nir_texop_txf)) {
5124 address[count++] = lod;
5125 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5126 address[count++] = sample_index;
5127 } else if(instr->op == nir_texop_txs) {
5128 count = 0;
5129 if (lod)
5130 address[count++] = lod;
5131 else
5132 address[count++] = ctx->ac.i32_0;
5133 }
5134
5135 for (chan = 0; chan < count; chan++) {
5136 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5137 address[chan], ctx->ac.i32, "");
5138 }
5139
5140 if (instr->op == nir_texop_samples_identical) {
5141 LLVMValueRef txf_address[4];
5142 struct ac_image_args txf_args = { 0 };
5143 unsigned txf_count = count;
5144 memcpy(txf_address, address, sizeof(txf_address));
5145
5146 if (!instr->is_array)
5147 txf_address[2] = ctx->ac.i32_0;
5148 txf_address[3] = ctx->ac.i32_0;
5149
5150 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5151 fmask_ptr, NULL,
5152 txf_address, txf_count, 0xf);
5153
5154 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5155
5156 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5157 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5158 goto write_result;
5159 }
5160
5161 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5162 instr->op != nir_texop_txs) {
5163 unsigned sample_chan = instr->is_array ? 3 : 2;
5164 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5165 address[0],
5166 address[1],
5167 instr->is_array ? address[2] : NULL,
5168 address[sample_chan],
5169 fmask_ptr);
5170 }
5171
5172 if (offsets && instr->op == nir_texop_txf) {
5173 nir_const_value *const_offset =
5174 nir_src_as_const_value(instr->src[const_src].src);
5175 int num_offsets = instr->src[const_src].src.ssa->num_components;
5176 assert(const_offset);
5177 num_offsets = MIN2(num_offsets, instr->coord_components);
5178 if (num_offsets > 2)
5179 address[2] = LLVMBuildAdd(ctx->ac.builder,
5180 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5181 if (num_offsets > 1)
5182 address[1] = LLVMBuildAdd(ctx->ac.builder,
5183 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5184 address[0] = LLVMBuildAdd(ctx->ac.builder,
5185 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5186
5187 }
5188
5189 /* TODO TG4 support */
5190 if (instr->op == nir_texop_tg4) {
5191 if (instr->is_shadow)
5192 dmask = 1;
5193 else
5194 dmask = 1 << instr->component;
5195 }
5196 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5197 res_ptr, samp_ptr, address, count, dmask);
5198
5199 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5200
5201 if (instr->op == nir_texop_query_levels)
5202 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5203 else if (instr->is_shadow && instr->is_new_style_shadow &&
5204 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5205 instr->op != nir_texop_tg4)
5206 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5207 else if (instr->op == nir_texop_txs &&
5208 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5209 instr->is_array) {
5210 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5211 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5212 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5213 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5214 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5215 } else if (ctx->ac.chip_class >= GFX9 &&
5216 instr->op == nir_texop_txs &&
5217 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5218 instr->is_array) {
5219 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5220 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5221 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5222 ctx->ac.i32_1, "");
5223 } else if (instr->dest.ssa.num_components != 4)
5224 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5225
5226 write_result:
5227 if (result) {
5228 assert(instr->dest.is_ssa);
5229 result = ac_to_integer(&ctx->ac, result);
5230 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5231 }
5232 }
5233
5234
5235 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5236 {
5237 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5238 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5239
5240 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5241 _mesa_hash_table_insert(ctx->phis, instr, result);
5242 }
5243
5244 static void visit_post_phi(struct ac_nir_context *ctx,
5245 nir_phi_instr *instr,
5246 LLVMValueRef llvm_phi)
5247 {
5248 nir_foreach_phi_src(src, instr) {
5249 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5250 LLVMValueRef llvm_src = get_src(ctx, src->src);
5251
5252 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5253 }
5254 }
5255
5256 static void phi_post_pass(struct ac_nir_context *ctx)
5257 {
5258 struct hash_entry *entry;
5259 hash_table_foreach(ctx->phis, entry) {
5260 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5261 (LLVMValueRef)entry->data);
5262 }
5263 }
5264
5265
5266 static void visit_ssa_undef(struct ac_nir_context *ctx,
5267 const nir_ssa_undef_instr *instr)
5268 {
5269 unsigned num_components = instr->def.num_components;
5270 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5271 LLVMValueRef undef;
5272
5273 if (num_components == 1)
5274 undef = LLVMGetUndef(type);
5275 else {
5276 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5277 }
5278 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5279 }
5280
5281 static void visit_jump(struct ac_nir_context *ctx,
5282 const nir_jump_instr *instr)
5283 {
5284 switch (instr->type) {
5285 case nir_jump_break:
5286 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5287 LLVMClearInsertionPosition(ctx->ac.builder);
5288 break;
5289 case nir_jump_continue:
5290 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5291 LLVMClearInsertionPosition(ctx->ac.builder);
5292 break;
5293 default:
5294 fprintf(stderr, "Unknown NIR jump instr: ");
5295 nir_print_instr(&instr->instr, stderr);
5296 fprintf(stderr, "\n");
5297 abort();
5298 }
5299 }
5300
5301 static void visit_cf_list(struct ac_nir_context *ctx,
5302 struct exec_list *list);
5303
5304 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5305 {
5306 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5307 nir_foreach_instr(instr, block)
5308 {
5309 switch (instr->type) {
5310 case nir_instr_type_alu:
5311 visit_alu(ctx, nir_instr_as_alu(instr));
5312 break;
5313 case nir_instr_type_load_const:
5314 visit_load_const(ctx, nir_instr_as_load_const(instr));
5315 break;
5316 case nir_instr_type_intrinsic:
5317 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5318 break;
5319 case nir_instr_type_tex:
5320 visit_tex(ctx, nir_instr_as_tex(instr));
5321 break;
5322 case nir_instr_type_phi:
5323 visit_phi(ctx, nir_instr_as_phi(instr));
5324 break;
5325 case nir_instr_type_ssa_undef:
5326 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5327 break;
5328 case nir_instr_type_jump:
5329 visit_jump(ctx, nir_instr_as_jump(instr));
5330 break;
5331 default:
5332 fprintf(stderr, "Unknown NIR instr type: ");
5333 nir_print_instr(instr, stderr);
5334 fprintf(stderr, "\n");
5335 abort();
5336 }
5337 }
5338
5339 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5340 }
5341
5342 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5343 {
5344 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5345
5346 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5347 LLVMBasicBlockRef merge_block =
5348 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5349 LLVMBasicBlockRef if_block =
5350 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5351 LLVMBasicBlockRef else_block = merge_block;
5352 if (!exec_list_is_empty(&if_stmt->else_list))
5353 else_block = LLVMAppendBasicBlockInContext(
5354 ctx->ac.context, fn, "");
5355
5356 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5357 ctx->ac.i32_0, "");
5358 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5359
5360 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5361 visit_cf_list(ctx, &if_stmt->then_list);
5362 if (LLVMGetInsertBlock(ctx->ac.builder))
5363 LLVMBuildBr(ctx->ac.builder, merge_block);
5364
5365 if (!exec_list_is_empty(&if_stmt->else_list)) {
5366 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5367 visit_cf_list(ctx, &if_stmt->else_list);
5368 if (LLVMGetInsertBlock(ctx->ac.builder))
5369 LLVMBuildBr(ctx->ac.builder, merge_block);
5370 }
5371
5372 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5373 }
5374
5375 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5376 {
5377 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5378 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5379 LLVMBasicBlockRef break_parent = ctx->break_block;
5380
5381 ctx->continue_block =
5382 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5383 ctx->break_block =
5384 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5385
5386 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5387 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5388 visit_cf_list(ctx, &loop->body);
5389
5390 if (LLVMGetInsertBlock(ctx->ac.builder))
5391 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5392 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5393
5394 ctx->continue_block = continue_parent;
5395 ctx->break_block = break_parent;
5396 }
5397
5398 static void visit_cf_list(struct ac_nir_context *ctx,
5399 struct exec_list *list)
5400 {
5401 foreach_list_typed(nir_cf_node, node, node, list)
5402 {
5403 switch (node->type) {
5404 case nir_cf_node_block:
5405 visit_block(ctx, nir_cf_node_as_block(node));
5406 break;
5407
5408 case nir_cf_node_if:
5409 visit_if(ctx, nir_cf_node_as_if(node));
5410 break;
5411
5412 case nir_cf_node_loop:
5413 visit_loop(ctx, nir_cf_node_as_loop(node));
5414 break;
5415
5416 default:
5417 assert(0);
5418 }
5419 }
5420 }
5421
5422 static void
5423 handle_vs_input_decl(struct radv_shader_context *ctx,
5424 struct nir_variable *variable)
5425 {
5426 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5427 LLVMValueRef t_offset;
5428 LLVMValueRef t_list;
5429 LLVMValueRef input;
5430 LLVMValueRef buffer_index;
5431 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5432 int idx = variable->data.location;
5433 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5434 uint8_t input_usage_mask =
5435 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5436 unsigned num_channels = util_last_bit(input_usage_mask);
5437
5438 variable->data.driver_location = idx * 4;
5439
5440 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5441 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5442 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5443 ctx->abi.start_instance, "");
5444 if (ctx->options->key.vs.as_ls) {
5445 ctx->shader_info->vs.vgpr_comp_cnt =
5446 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5447 } else {
5448 ctx->shader_info->vs.vgpr_comp_cnt =
5449 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5450 }
5451 } else
5452 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5453 ctx->abi.base_vertex, "");
5454 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5455
5456 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5457
5458 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5459 buffer_index,
5460 ctx->ac.i32_0,
5461 num_channels, false, true);
5462
5463 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5464
5465 for (unsigned chan = 0; chan < 4; chan++) {
5466 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5467 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5468 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5469 input, llvm_chan, ""));
5470 }
5471 }
5472 }
5473
5474 static void interp_fs_input(struct radv_shader_context *ctx,
5475 unsigned attr,
5476 LLVMValueRef interp_param,
5477 LLVMValueRef prim_mask,
5478 LLVMValueRef result[4])
5479 {
5480 LLVMValueRef attr_number;
5481 unsigned chan;
5482 LLVMValueRef i, j;
5483 bool interp = interp_param != NULL;
5484
5485 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5486
5487 /* fs.constant returns the param from the middle vertex, so it's not
5488 * really useful for flat shading. It's meant to be used for custom
5489 * interpolation (but the intrinsic can't fetch from the other two
5490 * vertices).
5491 *
5492 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5493 * to do the right thing. The only reason we use fs.constant is that
5494 * fs.interp cannot be used on integers, because they can be equal
5495 * to NaN.
5496 */
5497 if (interp) {
5498 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5499 ctx->ac.v2f32, "");
5500
5501 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5502 ctx->ac.i32_0, "");
5503 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5504 ctx->ac.i32_1, "");
5505 }
5506
5507 for (chan = 0; chan < 4; chan++) {
5508 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5509
5510 if (interp) {
5511 result[chan] = ac_build_fs_interp(&ctx->ac,
5512 llvm_chan,
5513 attr_number,
5514 prim_mask, i, j);
5515 } else {
5516 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5517 LLVMConstInt(ctx->ac.i32, 2, false),
5518 llvm_chan,
5519 attr_number,
5520 prim_mask);
5521 }
5522 }
5523 }
5524
5525 static void
5526 handle_fs_input_decl(struct radv_shader_context *ctx,
5527 struct nir_variable *variable)
5528 {
5529 int idx = variable->data.location;
5530 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5531 LLVMValueRef interp;
5532
5533 variable->data.driver_location = idx * 4;
5534 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5535
5536 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5537 unsigned interp_type;
5538 if (variable->data.sample)
5539 interp_type = INTERP_SAMPLE;
5540 else if (variable->data.centroid)
5541 interp_type = INTERP_CENTROID;
5542 else
5543 interp_type = INTERP_CENTER;
5544
5545 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5546 } else
5547 interp = NULL;
5548
5549 for (unsigned i = 0; i < attrib_count; ++i)
5550 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5551
5552 }
5553
5554 static void
5555 handle_vs_inputs(struct radv_shader_context *ctx,
5556 struct nir_shader *nir) {
5557 nir_foreach_variable(variable, &nir->inputs)
5558 handle_vs_input_decl(ctx, variable);
5559 }
5560
5561 static void
5562 prepare_interp_optimize(struct radv_shader_context *ctx,
5563 struct nir_shader *nir)
5564 {
5565 if (!ctx->options->key.fs.multisample)
5566 return;
5567
5568 bool uses_center = false;
5569 bool uses_centroid = false;
5570 nir_foreach_variable(variable, &nir->inputs) {
5571 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5572 variable->data.sample)
5573 continue;
5574
5575 if (variable->data.centroid)
5576 uses_centroid = true;
5577 else
5578 uses_center = true;
5579 }
5580
5581 if (uses_center && uses_centroid) {
5582 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5583 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5584 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5585 }
5586 }
5587
5588 static void
5589 handle_fs_inputs(struct radv_shader_context *ctx,
5590 struct nir_shader *nir)
5591 {
5592 prepare_interp_optimize(ctx, nir);
5593
5594 nir_foreach_variable(variable, &nir->inputs)
5595 handle_fs_input_decl(ctx, variable);
5596
5597 unsigned index = 0;
5598
5599 if (ctx->shader_info->info.ps.uses_input_attachments ||
5600 ctx->shader_info->info.needs_multiview_view_index)
5601 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5602
5603 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5604 LLVMValueRef interp_param;
5605 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5606
5607 if (!(ctx->input_mask & (1ull << i)))
5608 continue;
5609
5610 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5611 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5612 interp_param = *inputs;
5613 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5614 inputs);
5615
5616 if (!interp_param)
5617 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5618 ++index;
5619 } else if (i == VARYING_SLOT_POS) {
5620 for(int i = 0; i < 3; ++i)
5621 inputs[i] = ctx->abi.frag_pos[i];
5622
5623 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5624 ctx->abi.frag_pos[3]);
5625 }
5626 }
5627 ctx->shader_info->fs.num_interp = index;
5628 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5629 ctx->shader_info->fs.has_pcoord = true;
5630 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5631 ctx->shader_info->fs.prim_id_input = true;
5632 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5633 ctx->shader_info->fs.layer_input = true;
5634 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5635
5636 if (ctx->shader_info->info.needs_multiview_view_index)
5637 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5638 }
5639
5640 static LLVMValueRef
5641 ac_build_alloca(struct ac_llvm_context *ac,
5642 LLVMTypeRef type,
5643 const char *name)
5644 {
5645 LLVMBuilderRef builder = ac->builder;
5646 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5647 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5648 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5649 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5650 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5651 LLVMValueRef res;
5652
5653 if (first_instr) {
5654 LLVMPositionBuilderBefore(first_builder, first_instr);
5655 } else {
5656 LLVMPositionBuilderAtEnd(first_builder, first_block);
5657 }
5658
5659 res = LLVMBuildAlloca(first_builder, type, name);
5660 LLVMBuildStore(builder, LLVMConstNull(type), res);
5661
5662 LLVMDisposeBuilder(first_builder);
5663
5664 return res;
5665 }
5666
5667 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5668 LLVMTypeRef type,
5669 const char *name)
5670 {
5671 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5672 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5673 return ptr;
5674 }
5675
5676 static void
5677 scan_shader_output_decl(struct radv_shader_context *ctx,
5678 struct nir_variable *variable,
5679 struct nir_shader *shader,
5680 gl_shader_stage stage)
5681 {
5682 int idx = variable->data.location + variable->data.index;
5683 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5684 uint64_t mask_attribs;
5685
5686 variable->data.driver_location = idx * 4;
5687
5688 /* tess ctrl has it's own load/store paths for outputs */
5689 if (stage == MESA_SHADER_TESS_CTRL)
5690 return;
5691
5692 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5693 if (stage == MESA_SHADER_VERTEX ||
5694 stage == MESA_SHADER_TESS_EVAL ||
5695 stage == MESA_SHADER_GEOMETRY) {
5696 if (idx == VARYING_SLOT_CLIP_DIST0) {
5697 int length = shader->info.clip_distance_array_size +
5698 shader->info.cull_distance_array_size;
5699 if (stage == MESA_SHADER_VERTEX) {
5700 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5701 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5702 }
5703 if (stage == MESA_SHADER_TESS_EVAL) {
5704 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5705 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5706 }
5707
5708 if (length > 4)
5709 attrib_count = 2;
5710 else
5711 attrib_count = 1;
5712 mask_attribs = 1ull << idx;
5713 }
5714 }
5715
5716 ctx->output_mask |= mask_attribs;
5717 }
5718
5719 static void
5720 handle_shader_output_decl(struct ac_nir_context *ctx,
5721 struct nir_shader *nir,
5722 struct nir_variable *variable)
5723 {
5724 unsigned output_loc = variable->data.driver_location / 4;
5725 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5726
5727 /* tess ctrl has it's own load/store paths for outputs */
5728 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5729 return;
5730
5731 if (ctx->stage == MESA_SHADER_VERTEX ||
5732 ctx->stage == MESA_SHADER_TESS_EVAL ||
5733 ctx->stage == MESA_SHADER_GEOMETRY) {
5734 int idx = variable->data.location + variable->data.index;
5735 if (idx == VARYING_SLOT_CLIP_DIST0) {
5736 int length = nir->info.clip_distance_array_size +
5737 nir->info.cull_distance_array_size;
5738
5739 if (length > 4)
5740 attrib_count = 2;
5741 else
5742 attrib_count = 1;
5743 }
5744 }
5745
5746 for (unsigned i = 0; i < attrib_count; ++i) {
5747 for (unsigned chan = 0; chan < 4; chan++) {
5748 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5749 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5750 }
5751 }
5752 }
5753
5754 static LLVMTypeRef
5755 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5756 enum glsl_base_type type)
5757 {
5758 switch (type) {
5759 case GLSL_TYPE_INT:
5760 case GLSL_TYPE_UINT:
5761 case GLSL_TYPE_BOOL:
5762 case GLSL_TYPE_SUBROUTINE:
5763 return ac->i32;
5764 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5765 return ac->f32;
5766 case GLSL_TYPE_INT64:
5767 case GLSL_TYPE_UINT64:
5768 return ac->i64;
5769 case GLSL_TYPE_DOUBLE:
5770 return ac->f64;
5771 default:
5772 unreachable("unknown GLSL type");
5773 }
5774 }
5775
5776 static LLVMTypeRef
5777 glsl_to_llvm_type(struct ac_llvm_context *ac,
5778 const struct glsl_type *type)
5779 {
5780 if (glsl_type_is_scalar(type)) {
5781 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5782 }
5783
5784 if (glsl_type_is_vector(type)) {
5785 return LLVMVectorType(
5786 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5787 glsl_get_vector_elements(type));
5788 }
5789
5790 if (glsl_type_is_matrix(type)) {
5791 return LLVMArrayType(
5792 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5793 glsl_get_matrix_columns(type));
5794 }
5795
5796 if (glsl_type_is_array(type)) {
5797 return LLVMArrayType(
5798 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5799 glsl_get_length(type));
5800 }
5801
5802 assert(glsl_type_is_struct(type));
5803
5804 LLVMTypeRef member_types[glsl_get_length(type)];
5805
5806 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5807 member_types[i] =
5808 glsl_to_llvm_type(ac,
5809 glsl_get_struct_field(type, i));
5810 }
5811
5812 return LLVMStructTypeInContext(ac->context, member_types,
5813 glsl_get_length(type), false);
5814 }
5815
5816 static void
5817 setup_locals(struct ac_nir_context *ctx,
5818 struct nir_function *func)
5819 {
5820 int i, j;
5821 ctx->num_locals = 0;
5822 nir_foreach_variable(variable, &func->impl->locals) {
5823 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5824 variable->data.driver_location = ctx->num_locals * 4;
5825 variable->data.location_frac = 0;
5826 ctx->num_locals += attrib_count;
5827 }
5828 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5829 if (!ctx->locals)
5830 return;
5831
5832 for (i = 0; i < ctx->num_locals; i++) {
5833 for (j = 0; j < 4; j++) {
5834 ctx->locals[i * 4 + j] =
5835 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5836 }
5837 }
5838 }
5839
5840 static void
5841 setup_shared(struct ac_nir_context *ctx,
5842 struct nir_shader *nir)
5843 {
5844 nir_foreach_variable(variable, &nir->shared) {
5845 LLVMValueRef shared =
5846 LLVMAddGlobalInAddressSpace(
5847 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5848 variable->name ? variable->name : "",
5849 AC_LOCAL_ADDR_SPACE);
5850 _mesa_hash_table_insert(ctx->vars, variable, shared);
5851 }
5852 }
5853
5854 /* Initialize arguments for the shader export intrinsic */
5855 static void
5856 si_llvm_init_export_args(struct radv_shader_context *ctx,
5857 LLVMValueRef *values,
5858 unsigned target,
5859 struct ac_export_args *args)
5860 {
5861 /* Default is 0xf. Adjusted below depending on the format. */
5862 args->enabled_channels = 0xf;
5863
5864 /* Specify whether the EXEC mask represents the valid mask */
5865 args->valid_mask = 0;
5866
5867 /* Specify whether this is the last export */
5868 args->done = 0;
5869
5870 /* Specify the target we are exporting */
5871 args->target = target;
5872
5873 args->compr = false;
5874 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5875 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5876 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5877 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5878
5879 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5880 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5881 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5882 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5883 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5884 unsigned chan;
5885
5886 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5887 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5888 unsigned bits, bool hi) = NULL;
5889
5890 switch(col_format) {
5891 case V_028714_SPI_SHADER_ZERO:
5892 args->enabled_channels = 0; /* writemask */
5893 args->target = V_008DFC_SQ_EXP_NULL;
5894 break;
5895
5896 case V_028714_SPI_SHADER_32_R:
5897 args->enabled_channels = 1;
5898 args->out[0] = values[0];
5899 break;
5900
5901 case V_028714_SPI_SHADER_32_GR:
5902 args->enabled_channels = 0x3;
5903 args->out[0] = values[0];
5904 args->out[1] = values[1];
5905 break;
5906
5907 case V_028714_SPI_SHADER_32_AR:
5908 args->enabled_channels = 0x9;
5909 args->out[0] = values[0];
5910 args->out[3] = values[3];
5911 break;
5912
5913 case V_028714_SPI_SHADER_FP16_ABGR:
5914 packf = ac_build_cvt_pkrtz_f16;
5915 break;
5916
5917 case V_028714_SPI_SHADER_UNORM16_ABGR:
5918 packf = ac_build_cvt_pknorm_u16;
5919 break;
5920
5921 case V_028714_SPI_SHADER_SNORM16_ABGR:
5922 packf = ac_build_cvt_pknorm_i16;
5923 break;
5924
5925 case V_028714_SPI_SHADER_UINT16_ABGR:
5926 packi = ac_build_cvt_pk_u16;
5927 break;
5928
5929 case V_028714_SPI_SHADER_SINT16_ABGR:
5930 packi = ac_build_cvt_pk_i16;
5931 break;
5932
5933 default:
5934 case V_028714_SPI_SHADER_32_ABGR:
5935 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5936 break;
5937 }
5938
5939 /* Pack f16 or norm_i16/u16. */
5940 if (packf) {
5941 for (chan = 0; chan < 2; chan++) {
5942 LLVMValueRef pack_args[2] = {
5943 values[2 * chan],
5944 values[2 * chan + 1]
5945 };
5946 LLVMValueRef packed;
5947
5948 packed = packf(&ctx->ac, pack_args);
5949 args->out[chan] = ac_to_float(&ctx->ac, packed);
5950 }
5951 args->compr = 1; /* COMPR flag */
5952 }
5953
5954 /* Pack i16/u16. */
5955 if (packi) {
5956 for (chan = 0; chan < 2; chan++) {
5957 LLVMValueRef pack_args[2] = {
5958 ac_to_integer(&ctx->ac, values[2 * chan]),
5959 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5960 };
5961 LLVMValueRef packed;
5962
5963 packed = packi(&ctx->ac, pack_args,
5964 is_int8 ? 8 : is_int10 ? 10 : 16,
5965 chan == 1);
5966 args->out[chan] = ac_to_float(&ctx->ac, packed);
5967 }
5968 args->compr = 1; /* COMPR flag */
5969 }
5970 return;
5971 }
5972
5973 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5974
5975 for (unsigned i = 0; i < 4; ++i)
5976 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5977 }
5978
5979 static void
5980 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5981 LLVMValueRef *values)
5982 {
5983 struct ac_export_args args;
5984
5985 si_llvm_init_export_args(ctx, values,
5986 V_008DFC_SQ_EXP_PARAM + index, &args);
5987 ac_build_export(&ctx->ac, &args);
5988 }
5989
5990 static LLVMValueRef
5991 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5992 {
5993 LLVMValueRef output =
5994 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5995
5996 return LLVMBuildLoad(ctx->ac.builder, output, "");
5997 }
5998
5999 static void
6000 handle_vs_outputs_post(struct radv_shader_context *ctx,
6001 bool export_prim_id,
6002 struct ac_vs_output_info *outinfo)
6003 {
6004 uint32_t param_count = 0;
6005 unsigned target;
6006 unsigned pos_idx, num_pos_exports = 0;
6007 struct ac_export_args args, pos_args[4] = {};
6008 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6009 int i;
6010
6011 if (ctx->options->key.has_multiview_view_index) {
6012 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6013 if(!*tmp_out) {
6014 for(unsigned i = 0; i < 4; ++i)
6015 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6016 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6017 }
6018
6019 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6020 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6021 }
6022
6023 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6024 sizeof(outinfo->vs_output_param_offset));
6025
6026 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6027 LLVMValueRef slots[8];
6028 unsigned j;
6029
6030 if (outinfo->cull_dist_mask)
6031 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6032
6033 i = VARYING_SLOT_CLIP_DIST0;
6034 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6035 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6036
6037 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6038 slots[i] = LLVMGetUndef(ctx->ac.f32);
6039
6040 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6041 target = V_008DFC_SQ_EXP_POS + 3;
6042 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6043 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6044 &args, sizeof(args));
6045 }
6046
6047 target = V_008DFC_SQ_EXP_POS + 2;
6048 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6049 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6050 &args, sizeof(args));
6051
6052 }
6053
6054 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6055 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6056 for (unsigned j = 0; j < 4; j++)
6057 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6058 }
6059 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6060
6061 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6062 outinfo->writes_pointsize = true;
6063 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6064 }
6065
6066 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6067 outinfo->writes_layer = true;
6068 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6069 }
6070
6071 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6072 outinfo->writes_viewport_index = true;
6073 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6074 }
6075
6076 if (outinfo->writes_pointsize ||
6077 outinfo->writes_layer ||
6078 outinfo->writes_viewport_index) {
6079 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6080 (outinfo->writes_layer == true ? 4 : 0));
6081 pos_args[1].valid_mask = 0;
6082 pos_args[1].done = 0;
6083 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6084 pos_args[1].compr = 0;
6085 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6086 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6087 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6088 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6089
6090 if (outinfo->writes_pointsize == true)
6091 pos_args[1].out[0] = psize_value;
6092 if (outinfo->writes_layer == true)
6093 pos_args[1].out[2] = layer_value;
6094 if (outinfo->writes_viewport_index == true) {
6095 if (ctx->options->chip_class >= GFX9) {
6096 /* GFX9 has the layer in out.z[10:0] and the viewport
6097 * index in out.z[19:16].
6098 */
6099 LLVMValueRef v = viewport_index_value;
6100 v = ac_to_integer(&ctx->ac, v);
6101 v = LLVMBuildShl(ctx->ac.builder, v,
6102 LLVMConstInt(ctx->ac.i32, 16, false),
6103 "");
6104 v = LLVMBuildOr(ctx->ac.builder, v,
6105 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6106
6107 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6108 pos_args[1].enabled_channels |= 1 << 2;
6109 } else {
6110 pos_args[1].out[3] = viewport_index_value;
6111 pos_args[1].enabled_channels |= 1 << 3;
6112 }
6113 }
6114 }
6115 for (i = 0; i < 4; i++) {
6116 if (pos_args[i].out[0])
6117 num_pos_exports++;
6118 }
6119
6120 pos_idx = 0;
6121 for (i = 0; i < 4; i++) {
6122 if (!pos_args[i].out[0])
6123 continue;
6124
6125 /* Specify the target we are exporting */
6126 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6127 if (pos_idx == num_pos_exports)
6128 pos_args[i].done = 1;
6129 ac_build_export(&ctx->ac, &pos_args[i]);
6130 }
6131
6132 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6133 LLVMValueRef values[4];
6134 if (!(ctx->output_mask & (1ull << i)))
6135 continue;
6136
6137 if (i != VARYING_SLOT_LAYER &&
6138 i != VARYING_SLOT_PRIMITIVE_ID &&
6139 i < VARYING_SLOT_VAR0)
6140 continue;
6141
6142 for (unsigned j = 0; j < 4; j++)
6143 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6144
6145 radv_export_param(ctx, param_count, values);
6146
6147 outinfo->vs_output_param_offset[i] = param_count++;
6148 }
6149
6150 if (export_prim_id) {
6151 LLVMValueRef values[4];
6152
6153 values[0] = ctx->vs_prim_id;
6154 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6155 ctx->shader_info->vs.vgpr_comp_cnt);
6156 for (unsigned j = 1; j < 4; j++)
6157 values[j] = ctx->ac.f32_0;
6158
6159 radv_export_param(ctx, param_count, values);
6160
6161 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6162 outinfo->export_prim_id = true;
6163 }
6164
6165 outinfo->pos_exports = num_pos_exports;
6166 outinfo->param_exports = param_count;
6167 }
6168
6169 static void
6170 handle_es_outputs_post(struct radv_shader_context *ctx,
6171 struct ac_es_output_info *outinfo)
6172 {
6173 int j;
6174 uint64_t max_output_written = 0;
6175 LLVMValueRef lds_base = NULL;
6176
6177 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6178 int param_index;
6179 int length = 4;
6180
6181 if (!(ctx->output_mask & (1ull << i)))
6182 continue;
6183
6184 if (i == VARYING_SLOT_CLIP_DIST0)
6185 length = ctx->num_output_clips + ctx->num_output_culls;
6186
6187 param_index = shader_io_get_unique_index(i);
6188
6189 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6190 }
6191
6192 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6193
6194 if (ctx->ac.chip_class >= GFX9) {
6195 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6196 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6197 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6198 LLVMConstInt(ctx->ac.i32, 24, false),
6199 LLVMConstInt(ctx->ac.i32, 4, false), false);
6200 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6201 LLVMBuildMul(ctx->ac.builder, wave_idx,
6202 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6203 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6204 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6205 }
6206
6207 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6208 LLVMValueRef dw_addr = NULL;
6209 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6210 int param_index;
6211 int length = 4;
6212
6213 if (!(ctx->output_mask & (1ull << i)))
6214 continue;
6215
6216 if (i == VARYING_SLOT_CLIP_DIST0)
6217 length = ctx->num_output_clips + ctx->num_output_culls;
6218
6219 param_index = shader_io_get_unique_index(i);
6220
6221 if (lds_base) {
6222 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6223 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6224 "");
6225 }
6226 for (j = 0; j < length; j++) {
6227 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6228 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6229
6230 if (ctx->ac.chip_class >= GFX9) {
6231 ac_lds_store(&ctx->ac, dw_addr,
6232 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6233 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6234 } else {
6235 ac_build_buffer_store_dword(&ctx->ac,
6236 ctx->esgs_ring,
6237 out_val, 1,
6238 NULL, ctx->es2gs_offset,
6239 (4 * param_index + j) * 4,
6240 1, 1, true, true);
6241 }
6242 }
6243 }
6244 }
6245
6246 static void
6247 handle_ls_outputs_post(struct radv_shader_context *ctx)
6248 {
6249 LLVMValueRef vertex_id = ctx->rel_auto_id;
6250 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6251 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6252 vertex_dw_stride, "");
6253
6254 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6255 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6256 int length = 4;
6257
6258 if (!(ctx->output_mask & (1ull << i)))
6259 continue;
6260
6261 if (i == VARYING_SLOT_CLIP_DIST0)
6262 length = ctx->num_output_clips + ctx->num_output_culls;
6263 int param = shader_io_get_unique_index(i);
6264 mark_tess_output(ctx, false, param);
6265 if (length > 4)
6266 mark_tess_output(ctx, false, param + 1);
6267 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6268 LLVMConstInt(ctx->ac.i32, param * 4, false),
6269 "");
6270 for (unsigned j = 0; j < length; j++) {
6271 ac_lds_store(&ctx->ac, dw_addr,
6272 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6273 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6274 }
6275 }
6276 }
6277
6278 struct ac_build_if_state
6279 {
6280 struct radv_shader_context *ctx;
6281 LLVMValueRef condition;
6282 LLVMBasicBlockRef entry_block;
6283 LLVMBasicBlockRef true_block;
6284 LLVMBasicBlockRef false_block;
6285 LLVMBasicBlockRef merge_block;
6286 };
6287
6288 static LLVMBasicBlockRef
6289 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6290 {
6291 LLVMBasicBlockRef current_block;
6292 LLVMBasicBlockRef next_block;
6293 LLVMBasicBlockRef new_block;
6294
6295 /* get current basic block */
6296 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6297
6298 /* chqeck if there's another block after this one */
6299 next_block = LLVMGetNextBasicBlock(current_block);
6300 if (next_block) {
6301 /* insert the new block before the next block */
6302 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6303 }
6304 else {
6305 /* append new block after current block */
6306 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6307 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6308 }
6309 return new_block;
6310 }
6311
6312 static void
6313 ac_nir_build_if(struct ac_build_if_state *ifthen,
6314 struct radv_shader_context *ctx,
6315 LLVMValueRef condition)
6316 {
6317 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6318
6319 memset(ifthen, 0, sizeof *ifthen);
6320 ifthen->ctx = ctx;
6321 ifthen->condition = condition;
6322 ifthen->entry_block = block;
6323
6324 /* create endif/merge basic block for the phi functions */
6325 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6326
6327 /* create/insert true_block before merge_block */
6328 ifthen->true_block =
6329 LLVMInsertBasicBlockInContext(ctx->context,
6330 ifthen->merge_block,
6331 "if-true-block");
6332
6333 /* successive code goes into the true block */
6334 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6335 }
6336
6337 /**
6338 * End a conditional.
6339 */
6340 static void
6341 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6342 {
6343 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6344
6345 /* Insert branch to the merge block from current block */
6346 LLVMBuildBr(builder, ifthen->merge_block);
6347
6348 /*
6349 * Now patch in the various branch instructions.
6350 */
6351
6352 /* Insert the conditional branch instruction at the end of entry_block */
6353 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6354 if (ifthen->false_block) {
6355 /* we have an else clause */
6356 LLVMBuildCondBr(builder, ifthen->condition,
6357 ifthen->true_block, ifthen->false_block);
6358 }
6359 else {
6360 /* no else clause */
6361 LLVMBuildCondBr(builder, ifthen->condition,
6362 ifthen->true_block, ifthen->merge_block);
6363 }
6364
6365 /* Resume building code at end of the ifthen->merge_block */
6366 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6367 }
6368
6369 static void
6370 write_tess_factors(struct radv_shader_context *ctx)
6371 {
6372 unsigned stride, outer_comps, inner_comps;
6373 struct ac_build_if_state if_ctx, inner_if_ctx;
6374 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6375 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6376 unsigned tess_inner_index = 0, tess_outer_index;
6377 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6378 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6379 int i;
6380 emit_barrier(&ctx->ac, ctx->stage);
6381
6382 switch (ctx->options->key.tcs.primitive_mode) {
6383 case GL_ISOLINES:
6384 stride = 2;
6385 outer_comps = 2;
6386 inner_comps = 0;
6387 break;
6388 case GL_TRIANGLES:
6389 stride = 4;
6390 outer_comps = 3;
6391 inner_comps = 1;
6392 break;
6393 case GL_QUADS:
6394 stride = 6;
6395 outer_comps = 4;
6396 inner_comps = 2;
6397 break;
6398 default:
6399 return;
6400 }
6401
6402 ac_nir_build_if(&if_ctx, ctx,
6403 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6404 invocation_id, ctx->ac.i32_0, ""));
6405
6406 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6407
6408 if (inner_comps) {
6409 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6410 mark_tess_output(ctx, true, tess_inner_index);
6411 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6412 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6413 }
6414
6415 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6416 mark_tess_output(ctx, true, tess_outer_index);
6417 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6418 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6419
6420 for (i = 0; i < 4; i++) {
6421 inner[i] = LLVMGetUndef(ctx->ac.i32);
6422 outer[i] = LLVMGetUndef(ctx->ac.i32);
6423 }
6424
6425 // LINES reverseal
6426 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6427 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6428 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6429 ctx->ac.i32_1, "");
6430 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6431 } else {
6432 for (i = 0; i < outer_comps; i++) {
6433 outer[i] = out[i] =
6434 ac_lds_load(&ctx->ac, lds_outer);
6435 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6436 ctx->ac.i32_1, "");
6437 }
6438 for (i = 0; i < inner_comps; i++) {
6439 inner[i] = out[outer_comps+i] =
6440 ac_lds_load(&ctx->ac, lds_inner);
6441 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6442 ctx->ac.i32_1, "");
6443 }
6444 }
6445
6446 /* Convert the outputs to vectors for stores. */
6447 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6448 vec1 = NULL;
6449
6450 if (stride > 4)
6451 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6452
6453
6454 buffer = ctx->hs_ring_tess_factor;
6455 tf_base = ctx->tess_factor_offset;
6456 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6457 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6458 unsigned tf_offset = 0;
6459
6460 if (ctx->options->chip_class <= VI) {
6461 ac_nir_build_if(&inner_if_ctx, ctx,
6462 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6463 rel_patch_id, ctx->ac.i32_0, ""));
6464
6465 /* Store the dynamic HS control word. */
6466 ac_build_buffer_store_dword(&ctx->ac, buffer,
6467 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6468 1, ctx->ac.i32_0, tf_base,
6469 0, 1, 0, true, false);
6470 tf_offset += 4;
6471
6472 ac_nir_build_endif(&inner_if_ctx);
6473 }
6474
6475 /* Store the tessellation factors. */
6476 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6477 MIN2(stride, 4), byteoffset, tf_base,
6478 tf_offset, 1, 0, true, false);
6479 if (vec1)
6480 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6481 stride - 4, byteoffset, tf_base,
6482 16 + tf_offset, 1, 0, true, false);
6483
6484 //store to offchip for TES to read - only if TES reads them
6485 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6486 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6487 LLVMValueRef tf_inner_offset;
6488 unsigned param_outer, param_inner;
6489
6490 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6491 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6492 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6493
6494 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6495 util_next_power_of_two(outer_comps));
6496
6497 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6498 outer_comps, tf_outer_offset,
6499 ctx->oc_lds, 0, 1, 0, true, false);
6500 if (inner_comps) {
6501 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6502 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6503 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6504
6505 inner_vec = inner_comps == 1 ? inner[0] :
6506 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6507 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6508 inner_comps, tf_inner_offset,
6509 ctx->oc_lds, 0, 1, 0, true, false);
6510 }
6511 }
6512 ac_nir_build_endif(&if_ctx);
6513 }
6514
6515 static void
6516 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6517 {
6518 write_tess_factors(ctx);
6519 }
6520
6521 static bool
6522 si_export_mrt_color(struct radv_shader_context *ctx,
6523 LLVMValueRef *color, unsigned index, bool is_last,
6524 struct ac_export_args *args)
6525 {
6526 /* Export */
6527 si_llvm_init_export_args(ctx, color,
6528 V_008DFC_SQ_EXP_MRT + index, args);
6529
6530 if (is_last) {
6531 args->valid_mask = 1; /* whether the EXEC mask is valid */
6532 args->done = 1; /* DONE bit */
6533 } else if (!args->enabled_channels)
6534 return false; /* unnecessary NULL export */
6535
6536 return true;
6537 }
6538
6539 static void
6540 radv_export_mrt_z(struct radv_shader_context *ctx,
6541 LLVMValueRef depth, LLVMValueRef stencil,
6542 LLVMValueRef samplemask)
6543 {
6544 struct ac_export_args args;
6545
6546 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6547
6548 ac_build_export(&ctx->ac, &args);
6549 }
6550
6551 static void
6552 handle_fs_outputs_post(struct radv_shader_context *ctx)
6553 {
6554 unsigned index = 0;
6555 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6556 struct ac_export_args color_args[8];
6557
6558 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6559 LLVMValueRef values[4];
6560 bool last = false;
6561
6562 if (!(ctx->output_mask & (1ull << i)))
6563 continue;
6564
6565 if (i < FRAG_RESULT_DATA0)
6566 continue;
6567
6568 for (unsigned j = 0; j < 4; j++)
6569 values[j] = ac_to_float(&ctx->ac,
6570 radv_load_output(ctx, i, j));
6571
6572 if (!ctx->shader_info->info.ps.writes_z &&
6573 !ctx->shader_info->info.ps.writes_stencil &&
6574 !ctx->shader_info->info.ps.writes_sample_mask)
6575 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6576
6577 bool ret = si_export_mrt_color(ctx, values,
6578 i - FRAG_RESULT_DATA0,
6579 last, &color_args[index]);
6580 if (ret)
6581 index++;
6582 }
6583
6584 /* Process depth, stencil, samplemask. */
6585 if (ctx->shader_info->info.ps.writes_z) {
6586 depth = ac_to_float(&ctx->ac,
6587 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6588 }
6589 if (ctx->shader_info->info.ps.writes_stencil) {
6590 stencil = ac_to_float(&ctx->ac,
6591 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6592 }
6593 if (ctx->shader_info->info.ps.writes_sample_mask) {
6594 samplemask = ac_to_float(&ctx->ac,
6595 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6596 }
6597
6598 /* Export PS outputs. */
6599 for (unsigned i = 0; i < index; i++)
6600 ac_build_export(&ctx->ac, &color_args[i]);
6601
6602 if (depth || stencil || samplemask)
6603 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6604 else if (!index)
6605 ac_build_export_null(&ctx->ac);
6606 }
6607
6608 static void
6609 emit_gs_epilogue(struct radv_shader_context *ctx)
6610 {
6611 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6612 }
6613
6614 static void
6615 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6616 LLVMValueRef *addrs)
6617 {
6618 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6619
6620 switch (ctx->stage) {
6621 case MESA_SHADER_VERTEX:
6622 if (ctx->options->key.vs.as_ls)
6623 handle_ls_outputs_post(ctx);
6624 else if (ctx->options->key.vs.as_es)
6625 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6626 else
6627 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6628 &ctx->shader_info->vs.outinfo);
6629 break;
6630 case MESA_SHADER_FRAGMENT:
6631 handle_fs_outputs_post(ctx);
6632 break;
6633 case MESA_SHADER_GEOMETRY:
6634 emit_gs_epilogue(ctx);
6635 break;
6636 case MESA_SHADER_TESS_CTRL:
6637 handle_tcs_outputs_post(ctx);
6638 break;
6639 case MESA_SHADER_TESS_EVAL:
6640 if (ctx->options->key.tes.as_es)
6641 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6642 else
6643 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6644 &ctx->shader_info->tes.outinfo);
6645 break;
6646 default:
6647 break;
6648 }
6649 }
6650
6651 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6652 {
6653 LLVMPassManagerRef passmgr;
6654 /* Create the pass manager */
6655 passmgr = LLVMCreateFunctionPassManagerForModule(
6656 ctx->ac.module);
6657
6658 /* This pass should eliminate all the load and store instructions */
6659 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6660
6661 /* Add some optimization passes */
6662 LLVMAddScalarReplAggregatesPass(passmgr);
6663 LLVMAddLICMPass(passmgr);
6664 LLVMAddAggressiveDCEPass(passmgr);
6665 LLVMAddCFGSimplificationPass(passmgr);
6666 LLVMAddInstructionCombiningPass(passmgr);
6667
6668 /* Run the pass */
6669 LLVMInitializeFunctionPassManager(passmgr);
6670 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6671 LLVMFinalizeFunctionPassManager(passmgr);
6672
6673 LLVMDisposeBuilder(ctx->ac.builder);
6674 LLVMDisposePassManager(passmgr);
6675 }
6676
6677 static void
6678 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6679 {
6680 struct ac_vs_output_info *outinfo;
6681
6682 switch (ctx->stage) {
6683 case MESA_SHADER_FRAGMENT:
6684 case MESA_SHADER_COMPUTE:
6685 case MESA_SHADER_TESS_CTRL:
6686 case MESA_SHADER_GEOMETRY:
6687 return;
6688 case MESA_SHADER_VERTEX:
6689 if (ctx->options->key.vs.as_ls ||
6690 ctx->options->key.vs.as_es)
6691 return;
6692 outinfo = &ctx->shader_info->vs.outinfo;
6693 break;
6694 case MESA_SHADER_TESS_EVAL:
6695 if (ctx->options->key.vs.as_es)
6696 return;
6697 outinfo = &ctx->shader_info->tes.outinfo;
6698 break;
6699 default:
6700 unreachable("Unhandled shader type");
6701 }
6702
6703 ac_optimize_vs_outputs(&ctx->ac,
6704 ctx->main_function,
6705 outinfo->vs_output_param_offset,
6706 VARYING_SLOT_MAX,
6707 &outinfo->param_exports);
6708 }
6709
6710 static void
6711 ac_setup_rings(struct radv_shader_context *ctx)
6712 {
6713 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6714 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6715 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6716 }
6717
6718 if (ctx->is_gs_copy_shader) {
6719 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6720 }
6721 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6722 LLVMValueRef tmp;
6723 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6724 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6725
6726 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6727
6728 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6729 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6730 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6731 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6732 }
6733
6734 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6735 ctx->stage == MESA_SHADER_TESS_EVAL) {
6736 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6737 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6738 }
6739 }
6740
6741 static unsigned
6742 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6743 const struct nir_shader *nir)
6744 {
6745 switch (nir->info.stage) {
6746 case MESA_SHADER_TESS_CTRL:
6747 return chip_class >= CIK ? 128 : 64;
6748 case MESA_SHADER_GEOMETRY:
6749 return chip_class >= GFX9 ? 128 : 64;
6750 case MESA_SHADER_COMPUTE:
6751 break;
6752 default:
6753 return 0;
6754 }
6755
6756 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6757 nir->info.cs.local_size[1] *
6758 nir->info.cs.local_size[2];
6759 return max_workgroup_size;
6760 }
6761
6762 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6763 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6764 {
6765 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6766 LLVMConstInt(ctx->ac.i32, 8, false),
6767 LLVMConstInt(ctx->ac.i32, 8, false), false);
6768 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6769 ctx->ac.i32_0, "");
6770 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6771 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6772 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6773 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6774 }
6775
6776 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6777 {
6778 for(int i = 5; i >= 0; --i) {
6779 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6780 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6781 LLVMConstInt(ctx->ac.i32, 16, false), false);
6782 }
6783
6784 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6785 LLVMConstInt(ctx->ac.i32, 16, false),
6786 LLVMConstInt(ctx->ac.i32, 8, false), false);
6787 }
6788
6789 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6790 struct nir_shader *nir)
6791 {
6792 struct ac_nir_context ctx = {};
6793 struct nir_function *func;
6794
6795 ctx.ac = *ac;
6796 ctx.abi = abi;
6797
6798 ctx.stage = nir->info.stage;
6799
6800 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6801
6802 nir_foreach_variable(variable, &nir->outputs)
6803 handle_shader_output_decl(&ctx, nir, variable);
6804
6805 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6806 _mesa_key_pointer_equal);
6807 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6808 _mesa_key_pointer_equal);
6809 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6810 _mesa_key_pointer_equal);
6811
6812 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6813
6814 setup_locals(&ctx, func);
6815
6816 if (nir->info.stage == MESA_SHADER_COMPUTE)
6817 setup_shared(&ctx, nir);
6818
6819 visit_cf_list(&ctx, &func->impl->body);
6820 phi_post_pass(&ctx);
6821
6822 if (nir->info.stage != MESA_SHADER_COMPUTE)
6823 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6824 ctx.abi->outputs);
6825
6826 free(ctx.locals);
6827 ralloc_free(ctx.defs);
6828 ralloc_free(ctx.phis);
6829 ralloc_free(ctx.vars);
6830 }
6831
6832 static
6833 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6834 struct nir_shader *const *shaders,
6835 int shader_count,
6836 struct ac_shader_variant_info *shader_info,
6837 const struct ac_nir_compiler_options *options)
6838 {
6839 struct radv_shader_context ctx = {0};
6840 unsigned i;
6841 ctx.options = options;
6842 ctx.shader_info = shader_info;
6843 ctx.context = LLVMContextCreate();
6844
6845 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6846 options->family);
6847 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6848 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6849
6850 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6851 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6852 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6853 LLVMDisposeTargetData(data_layout);
6854 LLVMDisposeMessage(data_layout_str);
6855
6856 enum ac_float_mode float_mode =
6857 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6858 AC_FLOAT_MODE_DEFAULT;
6859
6860 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6861
6862 memset(shader_info, 0, sizeof(*shader_info));
6863
6864 for(int i = 0; i < shader_count; ++i)
6865 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6866
6867 for (i = 0; i < AC_UD_MAX_SETS; i++)
6868 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6869 for (i = 0; i < AC_UD_MAX_UD; i++)
6870 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6871
6872 ctx.max_workgroup_size = 0;
6873 for (int i = 0; i < shader_count; ++i) {
6874 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6875 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6876 shaders[i]));
6877 }
6878
6879 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6880 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6881
6882 ctx.abi.inputs = &ctx.inputs[0];
6883 ctx.abi.emit_outputs = handle_shader_outputs_post;
6884 ctx.abi.emit_vertex = visit_emit_vertex;
6885 ctx.abi.load_ubo = radv_load_ubo;
6886 ctx.abi.load_ssbo = radv_load_ssbo;
6887 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6888 ctx.abi.load_resource = radv_load_resource;
6889 ctx.abi.clamp_shadow_reference = false;
6890
6891 if (shader_count >= 2)
6892 ac_init_exec_full_mask(&ctx.ac);
6893
6894 if (ctx.ac.chip_class == GFX9 &&
6895 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6896 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6897
6898 for(int i = 0; i < shader_count; ++i) {
6899 ctx.stage = shaders[i]->info.stage;
6900 ctx.output_mask = 0;
6901 ctx.tess_outputs_written = 0;
6902 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6903 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6904
6905 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6906 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6907 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6908 ctx.abi.load_inputs = load_gs_input;
6909 ctx.abi.emit_primitive = visit_end_primitive;
6910 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6911 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6912 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6913 ctx.abi.load_tess_varyings = load_tcs_varyings;
6914 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6915 ctx.abi.store_tcs_outputs = store_tcs_output;
6916 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6917 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6918 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6919 ctx.abi.load_tess_varyings = load_tes_input;
6920 ctx.abi.load_tess_coord = load_tess_coord;
6921 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6922 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6923 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6924 if (shader_info->info.vs.needs_instance_id) {
6925 if (ctx.options->key.vs.as_ls) {
6926 ctx.shader_info->vs.vgpr_comp_cnt =
6927 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6928 } else {
6929 ctx.shader_info->vs.vgpr_comp_cnt =
6930 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6931 }
6932 }
6933 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6934 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6935 ctx.abi.lookup_interp_param = lookup_interp_param;
6936 ctx.abi.load_sample_position = load_sample_position;
6937 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6938 }
6939
6940 if (i)
6941 emit_barrier(&ctx.ac, ctx.stage);
6942
6943 ac_setup_rings(&ctx);
6944
6945 LLVMBasicBlockRef merge_block;
6946 if (shader_count >= 2) {
6947 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6948 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6949 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6950
6951 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6952 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6953 LLVMConstInt(ctx.ac.i32, 8, false), false);
6954 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6955 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6956 thread_id, count, "");
6957 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6958
6959 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6960 }
6961
6962 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6963 handle_fs_inputs(&ctx, shaders[i]);
6964 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6965 handle_vs_inputs(&ctx, shaders[i]);
6966 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6967 prepare_gs_input_vgprs(&ctx);
6968
6969 nir_foreach_variable(variable, &shaders[i]->outputs)
6970 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6971
6972 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6973
6974 if (shader_count >= 2) {
6975 LLVMBuildBr(ctx.ac.builder, merge_block);
6976 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6977 }
6978
6979 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6980 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6981 shaders[i]->info.cull_distance_array_size > 4;
6982 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6983 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6984 shaders[i]->info.gs.vertices_out;
6985 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6986 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6987 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6988 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6989 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6990 }
6991 }
6992
6993 LLVMBuildRetVoid(ctx.ac.builder);
6994
6995 if (options->dump_preoptir)
6996 ac_dump_module(ctx.ac.module);
6997
6998 ac_llvm_finalize_module(&ctx);
6999
7000 if (shader_count == 1)
7001 ac_nir_eliminate_const_vs_outputs(&ctx);
7002
7003 return ctx.ac.module;
7004 }
7005
7006 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7007 {
7008 unsigned *retval = (unsigned *)context;
7009 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7010 char *description = LLVMGetDiagInfoDescription(di);
7011
7012 if (severity == LLVMDSError) {
7013 *retval = 1;
7014 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7015 description);
7016 }
7017
7018 LLVMDisposeMessage(description);
7019 }
7020
7021 static unsigned ac_llvm_compile(LLVMModuleRef M,
7022 struct ac_shader_binary *binary,
7023 LLVMTargetMachineRef tm)
7024 {
7025 unsigned retval = 0;
7026 char *err;
7027 LLVMContextRef llvm_ctx;
7028 LLVMMemoryBufferRef out_buffer;
7029 unsigned buffer_size;
7030 const char *buffer_data;
7031 LLVMBool mem_err;
7032
7033 /* Setup Diagnostic Handler*/
7034 llvm_ctx = LLVMGetModuleContext(M);
7035
7036 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7037 &retval);
7038
7039 /* Compile IR*/
7040 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7041 &err, &out_buffer);
7042
7043 /* Process Errors/Warnings */
7044 if (mem_err) {
7045 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7046 free(err);
7047 retval = 1;
7048 goto out;
7049 }
7050
7051 /* Extract Shader Code*/
7052 buffer_size = LLVMGetBufferSize(out_buffer);
7053 buffer_data = LLVMGetBufferStart(out_buffer);
7054
7055 ac_elf_read(buffer_data, buffer_size, binary);
7056
7057 /* Clean up */
7058 LLVMDisposeMemoryBuffer(out_buffer);
7059
7060 out:
7061 return retval;
7062 }
7063
7064 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7065 LLVMModuleRef llvm_module,
7066 struct ac_shader_binary *binary,
7067 struct ac_shader_config *config,
7068 struct ac_shader_variant_info *shader_info,
7069 gl_shader_stage stage,
7070 bool dump_shader, bool supports_spill)
7071 {
7072 if (dump_shader)
7073 ac_dump_module(llvm_module);
7074
7075 memset(binary, 0, sizeof(*binary));
7076 int v = ac_llvm_compile(llvm_module, binary, tm);
7077 if (v) {
7078 fprintf(stderr, "compile failed\n");
7079 }
7080
7081 if (dump_shader)
7082 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7083
7084 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7085
7086 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7087 LLVMDisposeModule(llvm_module);
7088 LLVMContextDispose(ctx);
7089
7090 if (stage == MESA_SHADER_FRAGMENT) {
7091 shader_info->num_input_vgprs = 0;
7092 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7093 shader_info->num_input_vgprs += 2;
7094 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7095 shader_info->num_input_vgprs += 2;
7096 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7097 shader_info->num_input_vgprs += 2;
7098 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7099 shader_info->num_input_vgprs += 3;
7100 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7101 shader_info->num_input_vgprs += 2;
7102 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7103 shader_info->num_input_vgprs += 2;
7104 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7105 shader_info->num_input_vgprs += 2;
7106 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7107 shader_info->num_input_vgprs += 1;
7108 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7109 shader_info->num_input_vgprs += 1;
7110 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7111 shader_info->num_input_vgprs += 1;
7112 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7113 shader_info->num_input_vgprs += 1;
7114 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7115 shader_info->num_input_vgprs += 1;
7116 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7117 shader_info->num_input_vgprs += 1;
7118 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7119 shader_info->num_input_vgprs += 1;
7120 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7121 shader_info->num_input_vgprs += 1;
7122 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7123 shader_info->num_input_vgprs += 1;
7124 }
7125 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7126
7127 /* +3 for scratch wave offset and VCC */
7128 config->num_sgprs = MAX2(config->num_sgprs,
7129 shader_info->num_input_sgprs + 3);
7130
7131 /* Enable 64-bit and 16-bit denormals, because there is no performance
7132 * cost.
7133 *
7134 * If denormals are enabled, all floating-point output modifiers are
7135 * ignored.
7136 *
7137 * Don't enable denormals for 32-bit floats, because:
7138 * - Floating-point output modifiers would be ignored by the hw.
7139 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7140 * have to stop using those.
7141 * - SI & CI would be very slow.
7142 */
7143 config->float_mode |= V_00B028_FP_64_DENORMS;
7144 }
7145
7146 static void
7147 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7148 {
7149 switch (nir->info.stage) {
7150 case MESA_SHADER_COMPUTE:
7151 for (int i = 0; i < 3; ++i)
7152 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7153 break;
7154 case MESA_SHADER_FRAGMENT:
7155 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7156 break;
7157 case MESA_SHADER_GEOMETRY:
7158 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7159 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7160 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7161 shader_info->gs.invocations = nir->info.gs.invocations;
7162 break;
7163 case MESA_SHADER_TESS_EVAL:
7164 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7165 shader_info->tes.spacing = nir->info.tess.spacing;
7166 shader_info->tes.ccw = nir->info.tess.ccw;
7167 shader_info->tes.point_mode = nir->info.tess.point_mode;
7168 shader_info->tes.as_es = options->key.tes.as_es;
7169 break;
7170 case MESA_SHADER_TESS_CTRL:
7171 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7172 break;
7173 case MESA_SHADER_VERTEX:
7174 shader_info->vs.as_es = options->key.vs.as_es;
7175 shader_info->vs.as_ls = options->key.vs.as_ls;
7176 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7177 if (options->key.vs.as_ls)
7178 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7179 break;
7180 default:
7181 break;
7182 }
7183 }
7184
7185 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7186 struct ac_shader_binary *binary,
7187 struct ac_shader_config *config,
7188 struct ac_shader_variant_info *shader_info,
7189 struct nir_shader *const *nir,
7190 int nir_count,
7191 const struct ac_nir_compiler_options *options,
7192 bool dump_shader)
7193 {
7194
7195 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7196 options);
7197
7198 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7199 for (int i = 0; i < nir_count; ++i)
7200 ac_fill_shader_info(shader_info, nir[i], options);
7201
7202 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7203 if (options->chip_class == GFX9) {
7204 if (nir_count == 2 &&
7205 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7206 shader_info->gs.es_type = nir[0]->info.stage;
7207 }
7208 }
7209 }
7210
7211 static void
7212 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7213 {
7214 LLVMValueRef vtx_offset =
7215 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7216 LLVMConstInt(ctx->ac.i32, 4, false), "");
7217 int idx = 0;
7218
7219 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7220 int length = 4;
7221 int slot = idx;
7222 int slot_inc = 1;
7223 if (!(ctx->output_mask & (1ull << i)))
7224 continue;
7225
7226 if (i == VARYING_SLOT_CLIP_DIST0) {
7227 /* unpack clip and cull from a single set of slots */
7228 length = ctx->num_output_clips + ctx->num_output_culls;
7229 if (length > 4)
7230 slot_inc = 2;
7231 }
7232
7233 for (unsigned j = 0; j < length; j++) {
7234 LLVMValueRef value, soffset;
7235
7236 soffset = LLVMConstInt(ctx->ac.i32,
7237 (slot * 4 + j) *
7238 ctx->gs_max_out_vertices * 16 * 4, false);
7239
7240 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7241 1, ctx->ac.i32_0,
7242 vtx_offset, soffset,
7243 0, 1, 1, true, false);
7244
7245 LLVMBuildStore(ctx->ac.builder,
7246 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7247 }
7248 idx += slot_inc;
7249 }
7250 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7251 }
7252
7253 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7254 struct nir_shader *geom_shader,
7255 struct ac_shader_binary *binary,
7256 struct ac_shader_config *config,
7257 struct ac_shader_variant_info *shader_info,
7258 const struct ac_nir_compiler_options *options,
7259 bool dump_shader)
7260 {
7261 struct radv_shader_context ctx = {0};
7262 ctx.context = LLVMContextCreate();
7263 ctx.options = options;
7264 ctx.shader_info = shader_info;
7265
7266 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7267 options->family);
7268 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7269
7270 ctx.is_gs_copy_shader = true;
7271 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7272
7273 enum ac_float_mode float_mode =
7274 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7275 AC_FLOAT_MODE_DEFAULT;
7276
7277 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7278 ctx.stage = MESA_SHADER_VERTEX;
7279
7280 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7281
7282 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7283 ac_setup_rings(&ctx);
7284
7285 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7286 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7287
7288 struct ac_nir_context nir_ctx = {};
7289 nir_ctx.ac = ctx.ac;
7290 nir_ctx.abi = &ctx.abi;
7291
7292 nir_foreach_variable(variable, &geom_shader->outputs) {
7293 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7294 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7295 }
7296
7297 ac_gs_copy_shader_emit(&ctx);
7298
7299 LLVMBuildRetVoid(ctx.ac.builder);
7300
7301 ac_llvm_finalize_module(&ctx);
7302
7303 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7304 MESA_SHADER_VERTEX,
7305 dump_shader, options->supports_spill);
7306 }