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38f47b34e10003219c41064fe9bb901902009837
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef tess_factor_offset;
112 LLVMValueRef tcs_patch_id;
113 LLVMValueRef tcs_rel_ids;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_patch_id;
116 LLVMValueRef tes_u;
117 LLVMValueRef tes_v;
118
119 LLVMValueRef gsvs_ring_stride;
120 LLVMValueRef gsvs_num_entries;
121 LLVMValueRef gs2vs_offset;
122 LLVMValueRef gs_wave_id;
123 LLVMValueRef gs_vtx_offset[6];
124 LLVMValueRef gs_prim_id, gs_invocation_id;
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 LLVMTypeRef i1;
137 LLVMTypeRef i8;
138 LLVMTypeRef i16;
139 LLVMTypeRef i32;
140 LLVMTypeRef i64;
141 LLVMTypeRef v2i32;
142 LLVMTypeRef v3i32;
143 LLVMTypeRef v4i32;
144 LLVMTypeRef v8i32;
145 LLVMTypeRef f64;
146 LLVMTypeRef f32;
147 LLVMTypeRef f16;
148 LLVMTypeRef v2f32;
149 LLVMTypeRef v4f32;
150 LLVMTypeRef voidt;
151
152 LLVMValueRef i1true;
153 LLVMValueRef i1false;
154 LLVMValueRef i32zero;
155 LLVMValueRef i32one;
156 LLVMValueRef f32zero;
157 LLVMValueRef f32one;
158 LLVMValueRef v4f32empty;
159
160 unsigned uniform_md_kind;
161 LLVMValueRef empty_md;
162 gl_shader_stage stage;
163
164 LLVMValueRef lds;
165 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
166
167 uint64_t input_mask;
168 uint64_t output_mask;
169 uint8_t num_output_clips;
170 uint8_t num_output_culls;
171
172 bool is_gs_copy_shader;
173 LLVMValueRef gs_next_vertex;
174 unsigned gs_max_out_vertices;
175
176 unsigned tes_primitive_mode;
177 uint64_t tess_outputs_written;
178 uint64_t tess_patch_outputs_written;
179 };
180
181 static inline struct nir_to_llvm_context *
182 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
183 {
184 struct nir_to_llvm_context *ctx = NULL;
185 return container_of(abi, ctx, abi);
186 }
187
188 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
189 const nir_deref_var *deref,
190 enum ac_descriptor_type desc_type,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t user_sgpr_count;
256 uint8_t sgpr_count;
257 uint8_t num_user_sgprs_used;
258 uint8_t num_sgprs_used;
259 uint8_t num_vgprs_used;
260 };
261
262 static inline void
263 add_argument(struct arg_info *info,
264 LLVMTypeRef type, LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267 info->assign[info->count] = param_ptr;
268 info->types[info->count] = type;
269 info->count++;
270 }
271
272 static inline void
273 add_sgpr_argument(struct arg_info *info,
274 LLVMTypeRef type, LLVMValueRef *param_ptr)
275 {
276 add_argument(info, type, param_ptr);
277 info->num_sgprs_used += ac_get_type_size(type) / 4;
278 info->sgpr_count++;
279 }
280
281 static inline void
282 add_user_sgpr_argument(struct arg_info *info,
283 LLVMTypeRef type,
284 LLVMValueRef *param_ptr)
285 {
286 add_sgpr_argument(info, type, param_ptr);
287 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
288 info->user_sgpr_count++;
289 }
290
291 static inline void
292 add_vgpr_argument(struct arg_info *info,
293 LLVMTypeRef type,
294 LLVMValueRef *param_ptr)
295 {
296 add_argument(info, type, param_ptr);
297 info->num_vgprs_used += ac_get_type_size(type) / 4;
298 }
299
300 static inline void
301 add_user_sgpr_array_argument(struct arg_info *info,
302 LLVMTypeRef type,
303 LLVMValueRef *param_ptr)
304 {
305 info->array_params_mask |= (1 << info->count);
306 add_user_sgpr_argument(info, type, param_ptr);
307 }
308
309 static void assign_arguments(LLVMValueRef main_function,
310 struct arg_info *info)
311 {
312 unsigned i;
313 for (i = 0; i < info->count; i++) {
314 if (info->assign[i])
315 *info->assign[i] = LLVMGetParam(main_function, i);
316 }
317 }
318
319 static LLVMValueRef
320 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
321 LLVMBuilderRef builder, LLVMTypeRef *return_types,
322 unsigned num_return_elems,
323 struct arg_info *args,
324 unsigned max_workgroup_size,
325 bool unsafe_math)
326 {
327 LLVMTypeRef main_function_type, ret_type;
328 LLVMBasicBlockRef main_function_body;
329
330 if (num_return_elems)
331 ret_type = LLVMStructTypeInContext(ctx, return_types,
332 num_return_elems, true);
333 else
334 ret_type = LLVMVoidTypeInContext(ctx);
335
336 /* Setup the function */
337 main_function_type =
338 LLVMFunctionType(ret_type, args->types, args->count, 0);
339 LLVMValueRef main_function =
340 LLVMAddFunction(module, "main", main_function_type);
341 main_function_body =
342 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
343 LLVMPositionBuilderAtEnd(builder, main_function_body);
344
345 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
346 for (unsigned i = 0; i < args->sgpr_count; ++i) {
347 if (args->array_params_mask & (1 << i)) {
348 LLVMValueRef P = LLVMGetParam(main_function, i);
349 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
350 ac_add_attr_dereferenceable(P, UINT64_MAX);
351 }
352 else {
353 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
354 }
355 }
356
357 if (max_workgroup_size) {
358 ac_llvm_add_target_dep_function_attr(main_function,
359 "amdgpu-max-work-group-size",
360 max_workgroup_size);
361 }
362 if (unsafe_math) {
363 /* These were copied from some LLVM test. */
364 LLVMAddTargetDependentFunctionAttr(main_function,
365 "less-precise-fpmad",
366 "true");
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "no-infs-fp-math",
369 "true");
370 LLVMAddTargetDependentFunctionAttr(main_function,
371 "no-nans-fp-math",
372 "true");
373 LLVMAddTargetDependentFunctionAttr(main_function,
374 "unsafe-fp-math",
375 "true");
376 }
377 return main_function;
378 }
379
380 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
381 {
382 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
383 CONST_ADDR_SPACE);
384 }
385
386 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
387 {
388 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
389 type = LLVMGetElementType(type);
390
391 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
392 return LLVMGetIntTypeWidth(type);
393
394 if (type == ctx->f16)
395 return 16;
396 if (type == ctx->f32)
397 return 32;
398 if (type == ctx->f64)
399 return 64;
400
401 unreachable("Unhandled type kind in get_elem_bits");
402 }
403
404 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
405 LLVMValueRef param, unsigned rshift,
406 unsigned bitwidth)
407 {
408 LLVMValueRef value = param;
409 if (rshift)
410 value = LLVMBuildLShr(ctx->builder, value,
411 LLVMConstInt(ctx->i32, rshift, false), "");
412
413 if (rshift + bitwidth < 32) {
414 unsigned mask = (1 << bitwidth) - 1;
415 value = LLVMBuildAnd(ctx->builder, value,
416 LLVMConstInt(ctx->i32, mask, false), "");
417 }
418 return value;
419 }
420
421 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
422 {
423 switch (ctx->stage) {
424 case MESA_SHADER_TESS_CTRL:
425 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
426 case MESA_SHADER_TESS_EVAL:
427 return ctx->tes_rel_patch_id;
428 break;
429 default:
430 unreachable("Illegal stage");
431 }
432 }
433
434 /* Tessellation shaders pass outputs to the next shader using LDS.
435 *
436 * LS outputs = TCS inputs
437 * TCS outputs = TES inputs
438 *
439 * The LDS layout is:
440 * - TCS inputs for patch 0
441 * - TCS inputs for patch 1
442 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
443 * - ...
444 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
445 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
446 * - TCS outputs for patch 1
447 * - Per-patch TCS outputs for patch 1
448 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
449 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
450 * - ...
451 *
452 * All three shaders VS(LS), TCS, TES share the same LDS space.
453 */
454 static LLVMValueRef
455 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
456 {
457 if (ctx->stage == MESA_SHADER_VERTEX)
458 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
459 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
460 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
461 else {
462 assert(0);
463 return NULL;
464 }
465 }
466
467 static LLVMValueRef
468 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
469 {
470 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
471 }
472
473 static LLVMValueRef
474 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
475 {
476 return LLVMBuildMul(ctx->builder,
477 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
478 LLVMConstInt(ctx->i32, 4, false), "");
479 }
480
481 static LLVMValueRef
482 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
483 {
484 return LLVMBuildMul(ctx->builder,
485 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
486 LLVMConstInt(ctx->i32, 4, false), "");
487 }
488
489 static LLVMValueRef
490 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
491 {
492 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
493 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
494
495 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
496 }
497
498 static LLVMValueRef
499 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
500 {
501 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
502 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
503 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
504
505 return LLVMBuildAdd(ctx->builder, patch0_offset,
506 LLVMBuildMul(ctx->builder, patch_stride,
507 rel_patch_id, ""),
508 "");
509 }
510
511 static LLVMValueRef
512 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
513 {
514 LLVMValueRef patch0_patch_data_offset =
515 get_tcs_out_patch0_patch_data_offset(ctx);
516 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
517 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
518
519 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
520 LLVMBuildMul(ctx->builder, patch_stride,
521 rel_patch_id, ""),
522 "");
523 }
524
525 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
526 {
527 ud_info->sgpr_idx = *sgpr_idx;
528 ud_info->num_sgprs = num_sgprs;
529 ud_info->indirect = false;
530 ud_info->indirect_offset = 0;
531 *sgpr_idx += num_sgprs;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549
550 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
551 {
552 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
553 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
554 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
555 "tess_lds");
556 }
557
558 struct user_sgpr_info {
559 bool need_ring_offsets;
560 uint8_t sgpr_count;
561 bool indirect_all_descriptor_sets;
562 };
563
564 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
565 struct user_sgpr_info *user_sgpr_info)
566 {
567 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
568
569 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
570 if (ctx->stage == MESA_SHADER_GEOMETRY ||
571 ctx->stage == MESA_SHADER_VERTEX ||
572 ctx->stage == MESA_SHADER_TESS_CTRL ||
573 ctx->stage == MESA_SHADER_TESS_EVAL ||
574 ctx->is_gs_copy_shader)
575 user_sgpr_info->need_ring_offsets = true;
576
577 if (ctx->stage == MESA_SHADER_FRAGMENT &&
578 ctx->shader_info->info.ps.needs_sample_positions)
579 user_sgpr_info->need_ring_offsets = true;
580
581 /* 2 user sgprs will nearly always be allocated for scratch/rings */
582 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
583 user_sgpr_info->sgpr_count += 2;
584 }
585
586 switch (ctx->stage) {
587 case MESA_SHADER_COMPUTE:
588 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
589 break;
590 case MESA_SHADER_FRAGMENT:
591 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
592 break;
593 case MESA_SHADER_VERTEX:
594 if (!ctx->is_gs_copy_shader) {
595 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
596 if (ctx->shader_info->info.vs.needs_draw_id) {
597 user_sgpr_info->sgpr_count += 3;
598 } else {
599 user_sgpr_info->sgpr_count += 2;
600 }
601 }
602 if (ctx->options->key.vs.as_ls)
603 user_sgpr_info->sgpr_count++;
604 break;
605 case MESA_SHADER_TESS_CTRL:
606 user_sgpr_info->sgpr_count += 4;
607 break;
608 case MESA_SHADER_TESS_EVAL:
609 user_sgpr_info->sgpr_count += 1;
610 break;
611 case MESA_SHADER_GEOMETRY:
612 user_sgpr_info->sgpr_count += 2;
613 break;
614 default:
615 break;
616 }
617
618 if (ctx->shader_info->info.needs_push_constants)
619 user_sgpr_info->sgpr_count += 2;
620
621 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
622 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
623 user_sgpr_info->sgpr_count += 2;
624 user_sgpr_info->indirect_all_descriptor_sets = true;
625 } else {
626 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
627 }
628 }
629
630 static void create_function(struct nir_to_llvm_context *ctx)
631 {
632 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
633 uint8_t user_sgpr_idx;
634 struct user_sgpr_info user_sgpr_info;
635 struct arg_info args = {};
636 LLVMValueRef desc_sets;
637
638 allocate_user_sgprs(ctx, &user_sgpr_info);
639 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
640 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
641 }
642
643 /* 1 for each descriptor set */
644 if (!user_sgpr_info.indirect_all_descriptor_sets) {
645 for (unsigned i = 0; i < num_sets; ++i) {
646 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
647 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
648 }
649 }
650 } else
651 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
652
653 if (ctx->shader_info->info.needs_push_constants) {
654 /* 1 for push constants and dynamic descriptors */
655 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
656 }
657
658 switch (ctx->stage) {
659 case MESA_SHADER_COMPUTE:
660 if (ctx->shader_info->info.cs.grid_components_used)
661 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
662 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
663 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
664 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
665 break;
666 case MESA_SHADER_VERTEX:
667 if (!ctx->is_gs_copy_shader) {
668 if (ctx->shader_info->info.vs.has_vertex_buffers)
669 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
670 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
671 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
672 if (ctx->shader_info->info.vs.needs_draw_id)
673 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
674 }
675 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
676 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
677 if (ctx->options->key.vs.as_es)
678 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
679 else if (ctx->options->key.vs.as_ls)
680 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
681 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
682 if (!ctx->is_gs_copy_shader) {
683 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
684 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
685 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
686 }
687 break;
688 case MESA_SHADER_TESS_CTRL:
689 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
690 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
691 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
692 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
693 if (ctx->shader_info->info.needs_multiview_view_index)
694 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
695 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
696 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
697 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
698 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
699 break;
700 case MESA_SHADER_TESS_EVAL:
701 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
702 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
703 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
704 if (ctx->options->key.tes.as_es) {
705 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
706 add_sgpr_argument(&args, ctx->i32, NULL); //
707 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
708 } else {
709 add_sgpr_argument(&args, ctx->i32, NULL); //
710 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
711 }
712 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
713 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
714 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
715 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
716 break;
717 case MESA_SHADER_GEOMETRY:
718 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
719 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
720 if (ctx->shader_info->info.needs_multiview_view_index)
721 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
722 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
723 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
724 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
725 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
726 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
727 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
728 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
729 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
730 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
731 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
732 break;
733 case MESA_SHADER_FRAGMENT:
734 if (ctx->shader_info->info.ps.needs_sample_positions)
735 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
736 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
737 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
738 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
739 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
740 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
741 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
742 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
743 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
744 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
745 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
746 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
747 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
748 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
749 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
750 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
751 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
752 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
753 break;
754 default:
755 unreachable("Shader stage not implemented");
756 }
757
758 ctx->main_function = create_llvm_function(
759 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
760 ctx->max_workgroup_size,
761 ctx->options->unsafe_math);
762 set_llvm_calling_convention(ctx->main_function, ctx->stage);
763
764
765 ctx->shader_info->num_input_vgprs = 0;
766 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
767 ctx->options->supports_spill ? 2 : 0;
768
769 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
770 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
771
772 if (ctx->stage != MESA_SHADER_FRAGMENT)
773 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
774
775 assign_arguments(ctx->main_function, &args);
776
777 user_sgpr_idx = 0;
778
779 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
780 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
781 if (ctx->options->supports_spill) {
782 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
783 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
784 NULL, 0, AC_FUNC_ATTR_READNONE);
785 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
786 const_array(ctx->v4i32, 16), "");
787 }
788 }
789
790 if (!user_sgpr_info.indirect_all_descriptor_sets) {
791 for (unsigned i = 0; i < num_sets; ++i) {
792 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
793 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
794 } else
795 ctx->descriptor_sets[i] = NULL;
796 }
797 } else {
798 uint32_t desc_sgpr_idx = user_sgpr_idx;
799 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
800
801 for (unsigned i = 0; i < num_sets; ++i) {
802 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
803 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
804 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
805
806 } else
807 ctx->descriptor_sets[i] = NULL;
808 }
809 ctx->shader_info->need_indirect_descriptor_sets = true;
810 }
811
812 if (ctx->shader_info->info.needs_push_constants) {
813 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
814 }
815
816 switch (ctx->stage) {
817 case MESA_SHADER_COMPUTE:
818 if (ctx->shader_info->info.cs.grid_components_used) {
819 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
820 }
821 break;
822 case MESA_SHADER_VERTEX:
823 if (!ctx->is_gs_copy_shader) {
824 if (ctx->shader_info->info.vs.has_vertex_buffers) {
825 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
826 }
827 unsigned vs_num = 2;
828 if (ctx->shader_info->info.vs.needs_draw_id)
829 vs_num++;
830
831 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
832 }
833 if (ctx->view_index)
834 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
835 if (ctx->options->key.vs.as_ls) {
836 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
837 }
838 if (ctx->options->key.vs.as_ls)
839 declare_tess_lds(ctx);
840 break;
841 case MESA_SHADER_TESS_CTRL:
842 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
843 if (ctx->view_index)
844 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
845 declare_tess_lds(ctx);
846 break;
847 case MESA_SHADER_TESS_EVAL:
848 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
849 if (ctx->view_index)
850 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
851 break;
852 case MESA_SHADER_GEOMETRY:
853 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
854 if (ctx->view_index)
855 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
856 break;
857 case MESA_SHADER_FRAGMENT:
858 if (ctx->shader_info->info.ps.needs_sample_positions) {
859 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
860 }
861 break;
862 default:
863 unreachable("Shader stage not implemented");
864 }
865 }
866
867 static void setup_types(struct nir_to_llvm_context *ctx)
868 {
869 LLVMValueRef args[4];
870
871 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
872 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
873 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
874 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
875 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
876 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
877 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
878 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
879 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
880 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
881 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
882 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
883 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
884 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
885 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
886
887 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
888 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
889 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
890 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
891 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
892 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
893
894 args[0] = ctx->f32zero;
895 args[1] = ctx->f32zero;
896 args[2] = ctx->f32zero;
897 args[3] = ctx->f32one;
898 ctx->v4f32empty = LLVMConstVector(args, 4);
899
900 ctx->uniform_md_kind =
901 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
902 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
903
904 args[0] = LLVMConstReal(ctx->f32, 2.5);
905 }
906
907 static int get_llvm_num_components(LLVMValueRef value)
908 {
909 LLVMTypeRef type = LLVMTypeOf(value);
910 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
911 ? LLVMGetVectorSize(type)
912 : 1;
913 return num_components;
914 }
915
916 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
917 LLVMValueRef value,
918 int index)
919 {
920 int count = get_llvm_num_components(value);
921
922 assert(index < count);
923 if (count == 1)
924 return value;
925
926 return LLVMBuildExtractElement(ac->builder, value,
927 LLVMConstInt(ac->i32, index, false), "");
928 }
929
930 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
931 LLVMValueRef value, unsigned count)
932 {
933 unsigned num_components = get_llvm_num_components(value);
934 if (count == num_components)
935 return value;
936
937 LLVMValueRef masks[] = {
938 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
939 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
940
941 if (count == 1)
942 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
943 "");
944
945 LLVMValueRef swizzle = LLVMConstVector(masks, count);
946 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
947 }
948
949 static void
950 build_store_values_extended(struct ac_llvm_context *ac,
951 LLVMValueRef *values,
952 unsigned value_count,
953 unsigned value_stride,
954 LLVMValueRef vec)
955 {
956 LLVMBuilderRef builder = ac->builder;
957 unsigned i;
958
959 for (i = 0; i < value_count; i++) {
960 LLVMValueRef ptr = values[i * value_stride];
961 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
962 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
963 LLVMBuildStore(builder, value, ptr);
964 }
965 }
966
967 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
968 const nir_ssa_def *def)
969 {
970 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
971 if (def->num_components > 1) {
972 type = LLVMVectorType(type, def->num_components);
973 }
974 return type;
975 }
976
977 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
978 {
979 assert(src.is_ssa);
980 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
981 return (LLVMValueRef)entry->data;
982 }
983
984
985 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
986 const struct nir_block *b)
987 {
988 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
989 return (LLVMBasicBlockRef)entry->data;
990 }
991
992 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
993 nir_alu_src src,
994 unsigned num_components)
995 {
996 LLVMValueRef value = get_src(ctx, src.src);
997 bool need_swizzle = false;
998
999 assert(value);
1000 LLVMTypeRef type = LLVMTypeOf(value);
1001 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1002 ? LLVMGetVectorSize(type)
1003 : 1;
1004
1005 for (unsigned i = 0; i < num_components; ++i) {
1006 assert(src.swizzle[i] < src_components);
1007 if (src.swizzle[i] != i)
1008 need_swizzle = true;
1009 }
1010
1011 if (need_swizzle || num_components != src_components) {
1012 LLVMValueRef masks[] = {
1013 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1014 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1015 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1016 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1017
1018 if (src_components > 1 && num_components == 1) {
1019 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1020 masks[0], "");
1021 } else if (src_components == 1 && num_components > 1) {
1022 LLVMValueRef values[] = {value, value, value, value};
1023 value = ac_build_gather_values(&ctx->ac, values, num_components);
1024 } else {
1025 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1026 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1027 swizzle, "");
1028 }
1029 }
1030 assert(!src.negate);
1031 assert(!src.abs);
1032 return value;
1033 }
1034
1035 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1036 LLVMIntPredicate pred, LLVMValueRef src0,
1037 LLVMValueRef src1)
1038 {
1039 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1040 return LLVMBuildSelect(ctx->builder, result,
1041 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1042 LLVMConstInt(ctx->i32, 0, false), "");
1043 }
1044
1045 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1046 LLVMRealPredicate pred, LLVMValueRef src0,
1047 LLVMValueRef src1)
1048 {
1049 LLVMValueRef result;
1050 src0 = ac_to_float(ctx, src0);
1051 src1 = ac_to_float(ctx, src1);
1052 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1053 return LLVMBuildSelect(ctx->builder, result,
1054 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1055 LLVMConstInt(ctx->i32, 0, false), "");
1056 }
1057
1058 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1059 const char *intrin,
1060 LLVMTypeRef result_type,
1061 LLVMValueRef src0)
1062 {
1063 char name[64];
1064 LLVMValueRef params[] = {
1065 ac_to_float(ctx, src0),
1066 };
1067
1068 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1069 get_elem_bits(ctx, result_type));
1070 assert(length < sizeof(name));
1071 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1072 }
1073
1074 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1075 const char *intrin,
1076 LLVMTypeRef result_type,
1077 LLVMValueRef src0, LLVMValueRef src1)
1078 {
1079 char name[64];
1080 LLVMValueRef params[] = {
1081 ac_to_float(ctx, src0),
1082 ac_to_float(ctx, src1),
1083 };
1084
1085 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1086 get_elem_bits(ctx, result_type));
1087 assert(length < sizeof(name));
1088 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1089 }
1090
1091 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1092 const char *intrin,
1093 LLVMTypeRef result_type,
1094 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1095 {
1096 char name[64];
1097 LLVMValueRef params[] = {
1098 ac_to_float(ctx, src0),
1099 ac_to_float(ctx, src1),
1100 ac_to_float(ctx, src2),
1101 };
1102
1103 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1104 get_elem_bits(ctx, result_type));
1105 assert(length < sizeof(name));
1106 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1107 }
1108
1109 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1110 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1111 {
1112 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1113 ctx->i32_0, "");
1114 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1115 }
1116
1117 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1118 LLVMValueRef src0)
1119 {
1120 LLVMValueRef params[2] = {
1121 src0,
1122
1123 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1124 * add special code to check for x=0. The reason is that
1125 * the LLVM behavior for x=0 is different from what we
1126 * need here.
1127 *
1128 * The hardware already implements the correct behavior.
1129 */
1130 LLVMConstInt(ctx->i1, 1, false),
1131 };
1132
1133 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1134 params, 2,
1135 AC_FUNC_ATTR_READNONE);
1136
1137 /* TODO: We need an intrinsic to skip this conditional. */
1138 /* Check for zero: */
1139 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1140 LLVMIntEQ, src0,
1141 ctx->i32_0, ""),
1142 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1143 }
1144
1145 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1146 LLVMValueRef src0)
1147 {
1148 return ac_build_imsb(ctx, src0, ctx->i32);
1149 }
1150
1151 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1152 LLVMValueRef src0)
1153 {
1154 return ac_build_umsb(ctx, src0, ctx->i32);
1155 }
1156
1157 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1158 LLVMIntPredicate pred,
1159 LLVMValueRef src0, LLVMValueRef src1)
1160 {
1161 return LLVMBuildSelect(ctx->builder,
1162 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1163 src0,
1164 src1, "");
1165
1166 }
1167 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1168 LLVMValueRef src0)
1169 {
1170 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1171 LLVMBuildNeg(ctx->builder, src0, ""));
1172 }
1173
1174 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1175 LLVMValueRef src0)
1176 {
1177 LLVMValueRef cmp, val;
1178
1179 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1180 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1181 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1182 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1183 return val;
1184 }
1185
1186 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1187 LLVMValueRef src0)
1188 {
1189 LLVMValueRef cmp, val;
1190
1191 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1192 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1193 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1194 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1195 return val;
1196 }
1197
1198 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1199 LLVMValueRef src0)
1200 {
1201 const char *intr = "llvm.floor.f32";
1202 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1203 LLVMValueRef params[] = {
1204 fsrc0,
1205 };
1206 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1207 ctx->f32, params, 1,
1208 AC_FUNC_ATTR_READNONE);
1209 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1210 }
1211
1212 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1213 const char *intrin,
1214 LLVMValueRef src0, LLVMValueRef src1)
1215 {
1216 LLVMTypeRef ret_type;
1217 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1218 LLVMValueRef res;
1219 LLVMValueRef params[] = { src0, src1 };
1220 ret_type = LLVMStructTypeInContext(ctx->context, types,
1221 2, true);
1222
1223 res = ac_build_intrinsic(ctx, intrin, ret_type,
1224 params, 2, AC_FUNC_ATTR_READNONE);
1225
1226 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1227 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1228 return res;
1229 }
1230
1231 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1235 }
1236
1237 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1238 LLVMValueRef src0)
1239 {
1240 src0 = ac_to_float(ctx, src0);
1241 return LLVMBuildSExt(ctx->builder,
1242 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1243 ctx->i32, "");
1244 }
1245
1246 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1247 LLVMValueRef src0)
1248 {
1249 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1250 }
1251
1252 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1253 LLVMValueRef src0)
1254 {
1255 return LLVMBuildSExt(ctx->builder,
1256 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1257 ctx->i32, "");
1258 }
1259
1260 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1261 LLVMValueRef src0)
1262 {
1263 LLVMValueRef result;
1264 LLVMValueRef cond = NULL;
1265
1266 src0 = ac_to_float(&ctx->ac, src0);
1267 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1268
1269 if (ctx->options->chip_class >= VI) {
1270 LLVMValueRef args[2];
1271 /* Check if the result is a denormal - and flush to 0 if so. */
1272 args[0] = result;
1273 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1274 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1275 }
1276
1277 /* need to convert back up to f32 */
1278 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1279
1280 if (ctx->options->chip_class >= VI)
1281 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1282 else {
1283 /* for SI/CIK */
1284 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1285 * so compare the result and flush to 0 if it's smaller.
1286 */
1287 LLVMValueRef temp, cond2;
1288 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1289 ctx->f32, result);
1290 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1291 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1292 temp, "");
1293 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1294 temp, ctx->f32zero, "");
1295 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1296 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1297 }
1298 return result;
1299 }
1300
1301 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1302 LLVMValueRef src0, LLVMValueRef src1)
1303 {
1304 LLVMValueRef dst64, result;
1305 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1306 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1307
1308 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1309 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1310 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1311 return result;
1312 }
1313
1314 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1315 LLVMValueRef src0, LLVMValueRef src1)
1316 {
1317 LLVMValueRef dst64, result;
1318 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1319 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1320
1321 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1322 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1323 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1324 return result;
1325 }
1326
1327 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1328 bool is_signed,
1329 const LLVMValueRef srcs[3])
1330 {
1331 LLVMValueRef result;
1332 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1333
1334 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1335 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1336 return result;
1337 }
1338
1339 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1340 LLVMValueRef src0, LLVMValueRef src1,
1341 LLVMValueRef src2, LLVMValueRef src3)
1342 {
1343 LLVMValueRef bfi_args[3], result;
1344
1345 bfi_args[0] = LLVMBuildShl(ctx->builder,
1346 LLVMBuildSub(ctx->builder,
1347 LLVMBuildShl(ctx->builder,
1348 ctx->i32_1,
1349 src3, ""),
1350 ctx->i32_1, ""),
1351 src2, "");
1352 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1353 bfi_args[2] = src0;
1354
1355 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1356
1357 /* Calculate:
1358 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1359 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1360 */
1361 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1362 LLVMBuildAnd(ctx->builder, bfi_args[0],
1363 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1364
1365 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1366 return result;
1367 }
1368
1369 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0)
1371 {
1372 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1373 int i;
1374 LLVMValueRef comp[2];
1375
1376 src0 = ac_to_float(ctx, src0);
1377 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1378 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1379 for (i = 0; i < 2; i++) {
1380 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1381 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1382 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1383 }
1384
1385 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1386 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1387
1388 return comp[0];
1389 }
1390
1391 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1392 LLVMValueRef src0)
1393 {
1394 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1395 LLVMValueRef temps[2], result, val;
1396 int i;
1397
1398 for (i = 0; i < 2; i++) {
1399 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1400 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1401 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1402 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1403 }
1404
1405 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1406 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1407 ctx->i32_0, "");
1408 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1409 ctx->i32_1, "");
1410 return result;
1411 }
1412
1413 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1414 nir_op op,
1415 LLVMValueRef src0)
1416 {
1417 unsigned mask;
1418 int idx;
1419 LLVMValueRef result;
1420
1421 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1422 mask = AC_TID_MASK_LEFT;
1423 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1424 mask = AC_TID_MASK_TOP;
1425 else
1426 mask = AC_TID_MASK_TOP_LEFT;
1427
1428 /* for DDX we want to next X pixel, DDY next Y pixel. */
1429 if (op == nir_op_fddx_fine ||
1430 op == nir_op_fddx_coarse ||
1431 op == nir_op_fddx)
1432 idx = 1;
1433 else
1434 idx = 2;
1435
1436 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1437 return result;
1438 }
1439
1440 /*
1441 * this takes an I,J coordinate pair,
1442 * and works out the X and Y derivatives.
1443 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1444 */
1445 static LLVMValueRef emit_ddxy_interp(
1446 struct ac_nir_context *ctx,
1447 LLVMValueRef interp_ij)
1448 {
1449 LLVMValueRef result[4], a;
1450 unsigned i;
1451
1452 for (i = 0; i < 2; i++) {
1453 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1454 LLVMConstInt(ctx->ac.i32, i, false), "");
1455 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1456 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1457 }
1458 return ac_build_gather_values(&ctx->ac, result, 4);
1459 }
1460
1461 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1462 {
1463 LLVMValueRef src[4], result = NULL;
1464 unsigned num_components = instr->dest.dest.ssa.num_components;
1465 unsigned src_components;
1466 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1467
1468 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1469 switch (instr->op) {
1470 case nir_op_vec2:
1471 case nir_op_vec3:
1472 case nir_op_vec4:
1473 src_components = 1;
1474 break;
1475 case nir_op_pack_half_2x16:
1476 src_components = 2;
1477 break;
1478 case nir_op_unpack_half_2x16:
1479 src_components = 1;
1480 break;
1481 default:
1482 src_components = num_components;
1483 break;
1484 }
1485 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1486 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1487
1488 switch (instr->op) {
1489 case nir_op_fmov:
1490 case nir_op_imov:
1491 result = src[0];
1492 break;
1493 case nir_op_fneg:
1494 src[0] = ac_to_float(&ctx->ac, src[0]);
1495 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1496 break;
1497 case nir_op_ineg:
1498 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1499 break;
1500 case nir_op_inot:
1501 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1502 break;
1503 case nir_op_iadd:
1504 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1505 break;
1506 case nir_op_fadd:
1507 src[0] = ac_to_float(&ctx->ac, src[0]);
1508 src[1] = ac_to_float(&ctx->ac, src[1]);
1509 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1510 break;
1511 case nir_op_fsub:
1512 src[0] = ac_to_float(&ctx->ac, src[0]);
1513 src[1] = ac_to_float(&ctx->ac, src[1]);
1514 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1515 break;
1516 case nir_op_isub:
1517 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1518 break;
1519 case nir_op_imul:
1520 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1521 break;
1522 case nir_op_imod:
1523 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1524 break;
1525 case nir_op_umod:
1526 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1527 break;
1528 case nir_op_fmod:
1529 src[0] = ac_to_float(&ctx->ac, src[0]);
1530 src[1] = ac_to_float(&ctx->ac, src[1]);
1531 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1532 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1533 ac_to_float_type(&ctx->ac, def_type), result);
1534 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1535 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1536 break;
1537 case nir_op_frem:
1538 src[0] = ac_to_float(&ctx->ac, src[0]);
1539 src[1] = ac_to_float(&ctx->ac, src[1]);
1540 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1541 break;
1542 case nir_op_irem:
1543 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1544 break;
1545 case nir_op_idiv:
1546 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1547 break;
1548 case nir_op_udiv:
1549 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1550 break;
1551 case nir_op_fmul:
1552 src[0] = ac_to_float(&ctx->ac, src[0]);
1553 src[1] = ac_to_float(&ctx->ac, src[1]);
1554 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fdiv:
1557 src[0] = ac_to_float(&ctx->ac, src[0]);
1558 src[1] = ac_to_float(&ctx->ac, src[1]);
1559 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1560 break;
1561 case nir_op_frcp:
1562 src[0] = ac_to_float(&ctx->ac, src[0]);
1563 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1564 break;
1565 case nir_op_iand:
1566 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1567 break;
1568 case nir_op_ior:
1569 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_ixor:
1572 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_ishl:
1575 result = LLVMBuildShl(ctx->ac.builder, src[0],
1576 LLVMBuildZExt(ctx->ac.builder, src[1],
1577 LLVMTypeOf(src[0]), ""),
1578 "");
1579 break;
1580 case nir_op_ishr:
1581 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1582 LLVMBuildZExt(ctx->ac.builder, src[1],
1583 LLVMTypeOf(src[0]), ""),
1584 "");
1585 break;
1586 case nir_op_ushr:
1587 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1588 LLVMBuildZExt(ctx->ac.builder, src[1],
1589 LLVMTypeOf(src[0]), ""),
1590 "");
1591 break;
1592 case nir_op_ilt:
1593 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1594 break;
1595 case nir_op_ine:
1596 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1597 break;
1598 case nir_op_ieq:
1599 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1600 break;
1601 case nir_op_ige:
1602 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1603 break;
1604 case nir_op_ult:
1605 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1606 break;
1607 case nir_op_uge:
1608 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1609 break;
1610 case nir_op_feq:
1611 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1612 break;
1613 case nir_op_fne:
1614 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1615 break;
1616 case nir_op_flt:
1617 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1618 break;
1619 case nir_op_fge:
1620 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1621 break;
1622 case nir_op_fabs:
1623 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1624 ac_to_float_type(&ctx->ac, def_type), src[0]);
1625 break;
1626 case nir_op_iabs:
1627 result = emit_iabs(&ctx->ac, src[0]);
1628 break;
1629 case nir_op_imax:
1630 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1631 break;
1632 case nir_op_imin:
1633 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1634 break;
1635 case nir_op_umax:
1636 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1637 break;
1638 case nir_op_umin:
1639 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1640 break;
1641 case nir_op_isign:
1642 result = emit_isign(&ctx->ac, src[0]);
1643 break;
1644 case nir_op_fsign:
1645 src[0] = ac_to_float(&ctx->ac, src[0]);
1646 result = emit_fsign(&ctx->ac, src[0]);
1647 break;
1648 case nir_op_ffloor:
1649 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1650 ac_to_float_type(&ctx->ac, def_type), src[0]);
1651 break;
1652 case nir_op_ftrunc:
1653 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1654 ac_to_float_type(&ctx->ac, def_type), src[0]);
1655 break;
1656 case nir_op_fceil:
1657 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1658 ac_to_float_type(&ctx->ac, def_type), src[0]);
1659 break;
1660 case nir_op_fround_even:
1661 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1662 ac_to_float_type(&ctx->ac, def_type),src[0]);
1663 break;
1664 case nir_op_ffract:
1665 result = emit_ffract(&ctx->ac, src[0]);
1666 break;
1667 case nir_op_fsin:
1668 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1669 ac_to_float_type(&ctx->ac, def_type), src[0]);
1670 break;
1671 case nir_op_fcos:
1672 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1673 ac_to_float_type(&ctx->ac, def_type), src[0]);
1674 break;
1675 case nir_op_fsqrt:
1676 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1677 ac_to_float_type(&ctx->ac, def_type), src[0]);
1678 break;
1679 case nir_op_fexp2:
1680 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1681 ac_to_float_type(&ctx->ac, def_type), src[0]);
1682 break;
1683 case nir_op_flog2:
1684 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1685 ac_to_float_type(&ctx->ac, def_type), src[0]);
1686 break;
1687 case nir_op_frsq:
1688 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1689 ac_to_float_type(&ctx->ac, def_type), src[0]);
1690 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1691 break;
1692 case nir_op_fpow:
1693 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1694 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1695 break;
1696 case nir_op_fmax:
1697 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1698 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1699 if (instr->dest.dest.ssa.bit_size == 32)
1700 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1701 ac_to_float_type(&ctx->ac, def_type),
1702 result);
1703 break;
1704 case nir_op_fmin:
1705 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1706 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1707 if (instr->dest.dest.ssa.bit_size == 32)
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1709 ac_to_float_type(&ctx->ac, def_type),
1710 result);
1711 break;
1712 case nir_op_ffma:
1713 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1714 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1715 break;
1716 case nir_op_ibitfield_extract:
1717 result = emit_bitfield_extract(&ctx->ac, true, src);
1718 break;
1719 case nir_op_ubitfield_extract:
1720 result = emit_bitfield_extract(&ctx->ac, false, src);
1721 break;
1722 case nir_op_bitfield_insert:
1723 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1724 break;
1725 case nir_op_bitfield_reverse:
1726 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1727 break;
1728 case nir_op_bit_count:
1729 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1730 break;
1731 case nir_op_vec2:
1732 case nir_op_vec3:
1733 case nir_op_vec4:
1734 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1735 src[i] = ac_to_integer(&ctx->ac, src[i]);
1736 result = ac_build_gather_values(&ctx->ac, src, num_components);
1737 break;
1738 case nir_op_f2i32:
1739 case nir_op_f2i64:
1740 src[0] = ac_to_float(&ctx->ac, src[0]);
1741 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1742 break;
1743 case nir_op_f2u32:
1744 case nir_op_f2u64:
1745 src[0] = ac_to_float(&ctx->ac, src[0]);
1746 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1747 break;
1748 case nir_op_i2f32:
1749 case nir_op_i2f64:
1750 src[0] = ac_to_integer(&ctx->ac, src[0]);
1751 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1752 break;
1753 case nir_op_u2f32:
1754 case nir_op_u2f64:
1755 src[0] = ac_to_integer(&ctx->ac, src[0]);
1756 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1757 break;
1758 case nir_op_f2f64:
1759 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1760 break;
1761 case nir_op_f2f32:
1762 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1763 break;
1764 case nir_op_u2u32:
1765 case nir_op_u2u64:
1766 src[0] = ac_to_integer(&ctx->ac, src[0]);
1767 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1768 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1769 else
1770 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1771 break;
1772 case nir_op_i2i32:
1773 case nir_op_i2i64:
1774 src[0] = ac_to_integer(&ctx->ac, src[0]);
1775 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1776 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1777 else
1778 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1779 break;
1780 case nir_op_bcsel:
1781 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1782 break;
1783 case nir_op_find_lsb:
1784 src[0] = ac_to_integer(&ctx->ac, src[0]);
1785 result = emit_find_lsb(&ctx->ac, src[0]);
1786 break;
1787 case nir_op_ufind_msb:
1788 src[0] = ac_to_integer(&ctx->ac, src[0]);
1789 result = emit_ufind_msb(&ctx->ac, src[0]);
1790 break;
1791 case nir_op_ifind_msb:
1792 src[0] = ac_to_integer(&ctx->ac, src[0]);
1793 result = emit_ifind_msb(&ctx->ac, src[0]);
1794 break;
1795 case nir_op_uadd_carry:
1796 src[0] = ac_to_integer(&ctx->ac, src[0]);
1797 src[1] = ac_to_integer(&ctx->ac, src[1]);
1798 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1799 break;
1800 case nir_op_usub_borrow:
1801 src[0] = ac_to_integer(&ctx->ac, src[0]);
1802 src[1] = ac_to_integer(&ctx->ac, src[1]);
1803 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1804 break;
1805 case nir_op_b2f:
1806 result = emit_b2f(&ctx->ac, src[0]);
1807 break;
1808 case nir_op_f2b:
1809 result = emit_f2b(&ctx->ac, src[0]);
1810 break;
1811 case nir_op_b2i:
1812 result = emit_b2i(&ctx->ac, src[0]);
1813 break;
1814 case nir_op_i2b:
1815 src[0] = ac_to_integer(&ctx->ac, src[0]);
1816 result = emit_i2b(&ctx->ac, src[0]);
1817 break;
1818 case nir_op_fquantize2f16:
1819 result = emit_f2f16(ctx->nctx, src[0]);
1820 break;
1821 case nir_op_umul_high:
1822 src[0] = ac_to_integer(&ctx->ac, src[0]);
1823 src[1] = ac_to_integer(&ctx->ac, src[1]);
1824 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1825 break;
1826 case nir_op_imul_high:
1827 src[0] = ac_to_integer(&ctx->ac, src[0]);
1828 src[1] = ac_to_integer(&ctx->ac, src[1]);
1829 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1830 break;
1831 case nir_op_pack_half_2x16:
1832 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1833 break;
1834 case nir_op_unpack_half_2x16:
1835 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1836 break;
1837 case nir_op_fddx:
1838 case nir_op_fddy:
1839 case nir_op_fddx_fine:
1840 case nir_op_fddy_fine:
1841 case nir_op_fddx_coarse:
1842 case nir_op_fddy_coarse:
1843 result = emit_ddxy(ctx, instr->op, src[0]);
1844 break;
1845
1846 case nir_op_unpack_64_2x32_split_x: {
1847 assert(instr->src[0].src.ssa->num_components == 1);
1848 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1849 LLVMVectorType(ctx->ac.i32, 2),
1850 "");
1851 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1852 ctx->ac.i32_0, "");
1853 break;
1854 }
1855
1856 case nir_op_unpack_64_2x32_split_y: {
1857 assert(instr->src[0].src.ssa->num_components == 1);
1858 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1859 LLVMVectorType(ctx->ac.i32, 2),
1860 "");
1861 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1862 ctx->ac.i32_1, "");
1863 break;
1864 }
1865
1866 case nir_op_pack_64_2x32_split: {
1867 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1868 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1869 src[0], ctx->ac.i32_0, "");
1870 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1871 src[1], ctx->ac.i32_1, "");
1872 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1873 break;
1874 }
1875
1876 default:
1877 fprintf(stderr, "Unknown NIR alu instr: ");
1878 nir_print_instr(&instr->instr, stderr);
1879 fprintf(stderr, "\n");
1880 abort();
1881 }
1882
1883 if (result) {
1884 assert(instr->dest.dest.is_ssa);
1885 result = ac_to_integer(&ctx->ac, result);
1886 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1887 result);
1888 }
1889 }
1890
1891 static void visit_load_const(struct ac_nir_context *ctx,
1892 const nir_load_const_instr *instr)
1893 {
1894 LLVMValueRef values[4], value = NULL;
1895 LLVMTypeRef element_type =
1896 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1897
1898 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1899 switch (instr->def.bit_size) {
1900 case 32:
1901 values[i] = LLVMConstInt(element_type,
1902 instr->value.u32[i], false);
1903 break;
1904 case 64:
1905 values[i] = LLVMConstInt(element_type,
1906 instr->value.u64[i], false);
1907 break;
1908 default:
1909 fprintf(stderr,
1910 "unsupported nir load_const bit_size: %d\n",
1911 instr->def.bit_size);
1912 abort();
1913 }
1914 }
1915 if (instr->def.num_components > 1) {
1916 value = LLVMConstVector(values, instr->def.num_components);
1917 } else
1918 value = values[0];
1919
1920 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1921 }
1922
1923 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1924 LLVMTypeRef type)
1925 {
1926 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1927 return LLVMBuildBitCast(ctx->builder, ptr,
1928 LLVMPointerType(type, addr_space), "");
1929 }
1930
1931 static LLVMValueRef
1932 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1933 {
1934 LLVMValueRef size =
1935 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1936 LLVMConstInt(ctx->ac.i32, 2, false), "");
1937
1938 /* VI only */
1939 if (ctx->ac.chip_class == VI && in_elements) {
1940 /* On VI, the descriptor contains the size in bytes,
1941 * but TXQ must return the size in elements.
1942 * The stride is always non-zero for resources using TXQ.
1943 */
1944 LLVMValueRef stride =
1945 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1946 LLVMConstInt(ctx->ac.i32, 1, false), "");
1947 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1948 LLVMConstInt(ctx->ac.i32, 16, false), "");
1949 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1950 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1951
1952 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1953 }
1954 return size;
1955 }
1956
1957 /**
1958 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1959 * intrinsic names).
1960 */
1961 static void build_int_type_name(
1962 LLVMTypeRef type,
1963 char *buf, unsigned bufsize)
1964 {
1965 assert(bufsize >= 6);
1966
1967 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1968 snprintf(buf, bufsize, "v%ui32",
1969 LLVMGetVectorSize(type));
1970 else
1971 strcpy(buf, "i32");
1972 }
1973
1974 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
1975 struct ac_image_args *args,
1976 const nir_tex_instr *instr)
1977 {
1978 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1979 LLVMValueRef coord = args->addr;
1980 LLVMValueRef half_texel[2];
1981 LLVMValueRef compare_cube_wa = NULL;
1982 LLVMValueRef result;
1983 int c;
1984 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1985
1986 //TODO Rect
1987 {
1988 struct ac_image_args txq_args = { 0 };
1989
1990 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1991 txq_args.opcode = ac_image_get_resinfo;
1992 txq_args.dmask = 0xf;
1993 txq_args.addr = ctx->i32_0;
1994 txq_args.resource = args->resource;
1995 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
1996
1997 for (c = 0; c < 2; c++) {
1998 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1999 LLVMConstInt(ctx->i32, c, false), "");
2000 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2001 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2002 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2003 LLVMConstReal(ctx->f32, -0.5), "");
2004 }
2005 }
2006
2007 LLVMValueRef orig_coords = args->addr;
2008
2009 for (c = 0; c < 2; c++) {
2010 LLVMValueRef tmp;
2011 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2012 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2013 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2014 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2015 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2016 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2017 }
2018
2019
2020 /*
2021 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2022 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2023 * workaround by sampling using a scaled type and converting.
2024 * This is taken from amdgpu-pro shaders.
2025 */
2026 /* NOTE this produces some ugly code compared to amdgpu-pro,
2027 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2028 * and then reads them back. -pro generates two selects,
2029 * one s_cmp for the descriptor rewriting
2030 * one v_cmp for the coordinate and result changes.
2031 */
2032 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2033 LLVMValueRef tmp, tmp2;
2034
2035 /* workaround 8/8/8/8 uint/sint cube gather bug */
2036 /* first detect it then change to a scaled read and f2i */
2037 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2038 tmp2 = tmp;
2039
2040 /* extract the DATA_FORMAT */
2041 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2042 LLVMConstInt(ctx->i32, 6, false), false);
2043
2044 /* is the DATA_FORMAT == 8_8_8_8 */
2045 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2046
2047 if (stype == GLSL_TYPE_UINT)
2048 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2049 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2050 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2051 else
2052 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2053 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2054 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2055
2056 /* replace the NUM FORMAT in the descriptor */
2057 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2058 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2059
2060 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2061
2062 /* don't modify the coordinates for this case */
2063 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2064 }
2065 args->addr = coord;
2066 result = ac_build_image_opcode(ctx, args);
2067
2068 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2069 LLVMValueRef tmp, tmp2;
2070
2071 /* if the cube workaround is in place, f2i the result. */
2072 for (c = 0; c < 4; c++) {
2073 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2074 if (stype == GLSL_TYPE_UINT)
2075 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2076 else
2077 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2078 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2079 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2080 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2081 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2082 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2083 }
2084 }
2085 return result;
2086 }
2087
2088 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2089 const nir_tex_instr *instr,
2090 bool lod_is_zero,
2091 struct ac_image_args *args)
2092 {
2093 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2094 return ac_build_buffer_load_format(&ctx->ac,
2095 args->resource,
2096 args->addr,
2097 LLVMConstInt(ctx->ac.i32, 0, false),
2098 true);
2099 }
2100
2101 args->opcode = ac_image_sample;
2102 args->compare = instr->is_shadow;
2103
2104 switch (instr->op) {
2105 case nir_texop_txf:
2106 case nir_texop_txf_ms:
2107 case nir_texop_samples_identical:
2108 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2109 args->compare = false;
2110 args->offset = false;
2111 break;
2112 case nir_texop_txb:
2113 args->bias = true;
2114 break;
2115 case nir_texop_txl:
2116 if (lod_is_zero)
2117 args->level_zero = true;
2118 else
2119 args->lod = true;
2120 break;
2121 case nir_texop_txs:
2122 case nir_texop_query_levels:
2123 args->opcode = ac_image_get_resinfo;
2124 break;
2125 case nir_texop_tex:
2126 if (ctx->stage != MESA_SHADER_FRAGMENT)
2127 args->level_zero = true;
2128 break;
2129 case nir_texop_txd:
2130 args->deriv = true;
2131 break;
2132 case nir_texop_tg4:
2133 args->opcode = ac_image_gather4;
2134 args->level_zero = true;
2135 break;
2136 case nir_texop_lod:
2137 args->opcode = ac_image_get_lod;
2138 args->compare = false;
2139 args->offset = false;
2140 break;
2141 default:
2142 break;
2143 }
2144
2145 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2146 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2147 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2148 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2149 }
2150 }
2151 return ac_build_image_opcode(&ctx->ac, args);
2152 }
2153
2154 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2155 nir_intrinsic_instr *instr)
2156 {
2157 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2158 unsigned desc_set = nir_intrinsic_desc_set(instr);
2159 unsigned binding = nir_intrinsic_binding(instr);
2160 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2161 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2162 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2163 unsigned base_offset = layout->binding[binding].offset;
2164 LLVMValueRef offset, stride;
2165
2166 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2167 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2168 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2169 layout->binding[binding].dynamic_offset_offset;
2170 desc_ptr = ctx->push_constants;
2171 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2172 stride = LLVMConstInt(ctx->i32, 16, false);
2173 } else
2174 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2175
2176 offset = LLVMConstInt(ctx->i32, base_offset, false);
2177 index = LLVMBuildMul(ctx->builder, index, stride, "");
2178 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2179
2180 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2181 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2182 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2183
2184 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2185 }
2186
2187 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2188 nir_intrinsic_instr *instr)
2189 {
2190 LLVMValueRef ptr, addr;
2191
2192 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2193 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2194
2195 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2196 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2197
2198 return LLVMBuildLoad(ctx->builder, ptr, "");
2199 }
2200
2201 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2202 const nir_intrinsic_instr *instr)
2203 {
2204 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2205
2206 return get_buffer_size(ctx, desc, false);
2207 }
2208 static void visit_store_ssbo(struct ac_nir_context *ctx,
2209 nir_intrinsic_instr *instr)
2210 {
2211 const char *store_name;
2212 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2213 LLVMTypeRef data_type = ctx->ac.f32;
2214 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2215 int components_32bit = elem_size_mult * instr->num_components;
2216 unsigned writemask = nir_intrinsic_write_mask(instr);
2217 LLVMValueRef base_data, base_offset;
2218 LLVMValueRef params[6];
2219 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2220
2221 params[1] = ctx->abi->load_ssbo(ctx->abi,
2222 get_src(ctx, instr->src[1]), true);
2223 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2224 params[4] = i1false; /* glc */
2225 params[5] = i1false; /* slc */
2226
2227 if (components_32bit > 1)
2228 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2229
2230 base_data = ac_to_float(&ctx->ac, src_data);
2231 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2232 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2233 data_type, "");
2234 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2235 while (writemask) {
2236 int start, count;
2237 LLVMValueRef data;
2238 LLVMValueRef offset;
2239 LLVMValueRef tmp;
2240 u_bit_scan_consecutive_range(&writemask, &start, &count);
2241
2242 /* Due to an LLVM limitation, split 3-element writes
2243 * into a 2-element and a 1-element write. */
2244 if (count == 3) {
2245 writemask |= 1 << (start + 2);
2246 count = 2;
2247 }
2248
2249 start *= elem_size_mult;
2250 count *= elem_size_mult;
2251
2252 if (count > 4) {
2253 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2254 count = 4;
2255 }
2256
2257 if (count == 4) {
2258 store_name = "llvm.amdgcn.buffer.store.v4f32";
2259 data = base_data;
2260 } else if (count == 2) {
2261 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2262
2263 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2264 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2265 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2266 ctx->ac.i32_0, "");
2267
2268 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2269 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2270 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2271 ctx->ac.i32_1, "");
2272 store_name = "llvm.amdgcn.buffer.store.v2f32";
2273
2274 } else {
2275 assert(count == 1);
2276 if (get_llvm_num_components(base_data) > 1)
2277 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2278 LLVMConstInt(ctx->ac.i32, start, false), "");
2279 else
2280 data = base_data;
2281 store_name = "llvm.amdgcn.buffer.store.f32";
2282 }
2283
2284 offset = base_offset;
2285 if (start != 0) {
2286 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2287 }
2288 params[0] = data;
2289 params[3] = offset;
2290 ac_build_intrinsic(&ctx->ac, store_name,
2291 ctx->ac.voidt, params, 6, 0);
2292 }
2293 }
2294
2295 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2296 const nir_intrinsic_instr *instr)
2297 {
2298 const char *name;
2299 LLVMValueRef params[6];
2300 int arg_count = 0;
2301
2302 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2303 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2304 }
2305 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2306 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2307 get_src(ctx, instr->src[0]),
2308 true);
2309 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2310 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2311 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2312
2313 switch (instr->intrinsic) {
2314 case nir_intrinsic_ssbo_atomic_add:
2315 name = "llvm.amdgcn.buffer.atomic.add";
2316 break;
2317 case nir_intrinsic_ssbo_atomic_imin:
2318 name = "llvm.amdgcn.buffer.atomic.smin";
2319 break;
2320 case nir_intrinsic_ssbo_atomic_umin:
2321 name = "llvm.amdgcn.buffer.atomic.umin";
2322 break;
2323 case nir_intrinsic_ssbo_atomic_imax:
2324 name = "llvm.amdgcn.buffer.atomic.smax";
2325 break;
2326 case nir_intrinsic_ssbo_atomic_umax:
2327 name = "llvm.amdgcn.buffer.atomic.umax";
2328 break;
2329 case nir_intrinsic_ssbo_atomic_and:
2330 name = "llvm.amdgcn.buffer.atomic.and";
2331 break;
2332 case nir_intrinsic_ssbo_atomic_or:
2333 name = "llvm.amdgcn.buffer.atomic.or";
2334 break;
2335 case nir_intrinsic_ssbo_atomic_xor:
2336 name = "llvm.amdgcn.buffer.atomic.xor";
2337 break;
2338 case nir_intrinsic_ssbo_atomic_exchange:
2339 name = "llvm.amdgcn.buffer.atomic.swap";
2340 break;
2341 case nir_intrinsic_ssbo_atomic_comp_swap:
2342 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2343 break;
2344 default:
2345 abort();
2346 }
2347
2348 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2349 }
2350
2351 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2352 const nir_intrinsic_instr *instr)
2353 {
2354 LLVMValueRef results[2];
2355 int load_components;
2356 int num_components = instr->num_components;
2357 if (instr->dest.ssa.bit_size == 64)
2358 num_components *= 2;
2359
2360 for (int i = 0; i < num_components; i += load_components) {
2361 load_components = MIN2(num_components - i, 4);
2362 const char *load_name;
2363 LLVMTypeRef data_type = ctx->ac.f32;
2364 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2365 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2366
2367 if (load_components == 3)
2368 data_type = LLVMVectorType(ctx->ac.f32, 4);
2369 else if (load_components > 1)
2370 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2371
2372 if (load_components >= 3)
2373 load_name = "llvm.amdgcn.buffer.load.v4f32";
2374 else if (load_components == 2)
2375 load_name = "llvm.amdgcn.buffer.load.v2f32";
2376 else if (load_components == 1)
2377 load_name = "llvm.amdgcn.buffer.load.f32";
2378 else
2379 unreachable("unhandled number of components");
2380
2381 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2382 LLVMValueRef params[] = {
2383 ctx->abi->load_ssbo(ctx->abi,
2384 get_src(ctx, instr->src[0]),
2385 false),
2386 LLVMConstInt(ctx->ac.i32, 0, false),
2387 offset,
2388 i1false,
2389 i1false,
2390 };
2391
2392 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2393
2394 }
2395
2396 LLVMValueRef ret = results[0];
2397 if (num_components > 4 || num_components == 3) {
2398 LLVMValueRef masks[] = {
2399 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2400 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2401 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2402 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2403 };
2404
2405 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2406 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2407 results[num_components > 4 ? 1 : 0], swizzle, "");
2408 }
2409
2410 return LLVMBuildBitCast(ctx->ac.builder, ret,
2411 get_def_type(ctx, &instr->dest.ssa), "");
2412 }
2413
2414 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2415 const nir_intrinsic_instr *instr)
2416 {
2417 LLVMValueRef results[8], ret;
2418 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2419 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2420 int num_components = instr->num_components;
2421
2422 if (ctx->abi->load_ubo)
2423 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2424
2425 if (instr->dest.ssa.bit_size == 64)
2426 num_components *= 2;
2427
2428 for (unsigned i = 0; i < num_components; ++i) {
2429 LLVMValueRef params[] = {
2430 rsrc,
2431 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2432 offset, "")
2433 };
2434 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2435 params, 2,
2436 AC_FUNC_ATTR_READNONE |
2437 AC_FUNC_ATTR_LEGACY);
2438 }
2439
2440
2441 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2442 return LLVMBuildBitCast(ctx->ac.builder, ret,
2443 get_def_type(ctx, &instr->dest.ssa), "");
2444 }
2445
2446 static void
2447 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2448 bool vs_in, unsigned *vertex_index_out,
2449 LLVMValueRef *vertex_index_ref,
2450 unsigned *const_out, LLVMValueRef *indir_out)
2451 {
2452 unsigned const_offset = 0;
2453 nir_deref *tail = &deref->deref;
2454 LLVMValueRef offset = NULL;
2455
2456 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2457 tail = tail->child;
2458 nir_deref_array *deref_array = nir_deref_as_array(tail);
2459 if (vertex_index_out)
2460 *vertex_index_out = deref_array->base_offset;
2461
2462 if (vertex_index_ref) {
2463 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2464 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2465 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2466 }
2467 *vertex_index_ref = vtx;
2468 }
2469 }
2470
2471 if (deref->var->data.compact) {
2472 assert(tail->child->deref_type == nir_deref_type_array);
2473 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2474 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2475 /* We always lower indirect dereferences for "compact" array vars. */
2476 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2477
2478 const_offset = deref_array->base_offset;
2479 goto out;
2480 }
2481
2482 while (tail->child != NULL) {
2483 const struct glsl_type *parent_type = tail->type;
2484 tail = tail->child;
2485
2486 if (tail->deref_type == nir_deref_type_array) {
2487 nir_deref_array *deref_array = nir_deref_as_array(tail);
2488 LLVMValueRef index, stride, local_offset;
2489 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2490
2491 const_offset += size * deref_array->base_offset;
2492 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2493 continue;
2494
2495 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2496 index = get_src(ctx, deref_array->indirect);
2497 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2498 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2499
2500 if (offset)
2501 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2502 else
2503 offset = local_offset;
2504 } else if (tail->deref_type == nir_deref_type_struct) {
2505 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2506
2507 for (unsigned i = 0; i < deref_struct->index; i++) {
2508 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2509 const_offset += glsl_count_attribute_slots(ft, vs_in);
2510 }
2511 } else
2512 unreachable("unsupported deref type");
2513
2514 }
2515 out:
2516 if (const_offset && offset)
2517 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2518 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2519 "");
2520
2521 *const_out = const_offset;
2522 *indir_out = offset;
2523 }
2524
2525 static LLVMValueRef
2526 lds_load(struct nir_to_llvm_context *ctx,
2527 LLVMValueRef dw_addr)
2528 {
2529 LLVMValueRef value;
2530 value = ac_build_load(&ctx->ac, ctx->lds, dw_addr);
2531 return value;
2532 }
2533
2534 static void
2535 lds_store(struct nir_to_llvm_context *ctx,
2536 LLVMValueRef dw_addr, LLVMValueRef value)
2537 {
2538 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2539 ac_build_indexed_store(&ctx->ac, ctx->lds,
2540 dw_addr, value);
2541 }
2542
2543 /* The offchip buffer layout for TCS->TES is
2544 *
2545 * - attribute 0 of patch 0 vertex 0
2546 * - attribute 0 of patch 0 vertex 1
2547 * - attribute 0 of patch 0 vertex 2
2548 * ...
2549 * - attribute 0 of patch 1 vertex 0
2550 * - attribute 0 of patch 1 vertex 1
2551 * ...
2552 * - attribute 1 of patch 0 vertex 0
2553 * - attribute 1 of patch 0 vertex 1
2554 * ...
2555 * - per patch attribute 0 of patch 0
2556 * - per patch attribute 0 of patch 1
2557 * ...
2558 *
2559 * Note that every attribute has 4 components.
2560 */
2561 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2562 LLVMValueRef vertex_index,
2563 LLVMValueRef param_index)
2564 {
2565 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2566 LLVMValueRef param_stride, constant16;
2567 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2568
2569 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2570 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2571 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2572 num_patches, "");
2573
2574 constant16 = LLVMConstInt(ctx->i32, 16, false);
2575 if (vertex_index) {
2576 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2577 vertices_per_patch, "");
2578
2579 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2580 vertex_index, "");
2581
2582 param_stride = total_vertices;
2583 } else {
2584 base_addr = rel_patch_id;
2585 param_stride = num_patches;
2586 }
2587
2588 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2589 LLVMBuildMul(ctx->builder, param_index,
2590 param_stride, ""), "");
2591
2592 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2593
2594 if (!vertex_index) {
2595 LLVMValueRef patch_data_offset =
2596 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2597
2598 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2599 patch_data_offset, "");
2600 }
2601 return base_addr;
2602 }
2603
2604 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2605 unsigned param,
2606 unsigned const_index,
2607 bool is_compact,
2608 LLVMValueRef vertex_index,
2609 LLVMValueRef indir_index)
2610 {
2611 LLVMValueRef param_index;
2612
2613 if (indir_index)
2614 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2615 indir_index, "");
2616 else {
2617 if (const_index && !is_compact)
2618 param += const_index;
2619 param_index = LLVMConstInt(ctx->i32, param, false);
2620 }
2621 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2622 }
2623
2624 static void
2625 mark_tess_output(struct nir_to_llvm_context *ctx,
2626 bool is_patch, uint32_t param)
2627
2628 {
2629 if (is_patch) {
2630 ctx->tess_patch_outputs_written |= (1ull << param);
2631 } else
2632 ctx->tess_outputs_written |= (1ull << param);
2633 }
2634
2635 static LLVMValueRef
2636 get_dw_address(struct nir_to_llvm_context *ctx,
2637 LLVMValueRef dw_addr,
2638 unsigned param,
2639 unsigned const_index,
2640 bool compact_const_index,
2641 LLVMValueRef vertex_index,
2642 LLVMValueRef stride,
2643 LLVMValueRef indir_index)
2644
2645 {
2646
2647 if (vertex_index) {
2648 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2649 LLVMBuildMul(ctx->builder,
2650 vertex_index,
2651 stride, ""), "");
2652 }
2653
2654 if (indir_index)
2655 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2656 LLVMBuildMul(ctx->builder, indir_index,
2657 LLVMConstInt(ctx->i32, 4, false), ""), "");
2658 else if (const_index && !compact_const_index)
2659 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2660 LLVMConstInt(ctx->i32, const_index, false), "");
2661
2662 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2663 LLVMConstInt(ctx->i32, param * 4, false), "");
2664
2665 if (const_index && compact_const_index)
2666 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2667 LLVMConstInt(ctx->i32, const_index, false), "");
2668 return dw_addr;
2669 }
2670
2671 static LLVMValueRef
2672 load_tcs_input(struct nir_to_llvm_context *ctx,
2673 nir_intrinsic_instr *instr)
2674 {
2675 LLVMValueRef dw_addr, stride;
2676 unsigned const_index;
2677 LLVMValueRef vertex_index;
2678 LLVMValueRef indir_index;
2679 unsigned param;
2680 LLVMValueRef value[4], result;
2681 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2682 const bool is_compact = instr->variables[0]->var->data.compact;
2683 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2684 get_deref_offset(ctx->nir, instr->variables[0],
2685 false, NULL, per_vertex ? &vertex_index : NULL,
2686 &const_index, &indir_index);
2687
2688 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2689 dw_addr = get_tcs_in_current_patch_offset(ctx);
2690 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2691 indir_index);
2692
2693 for (unsigned i = 0; i < instr->num_components; i++) {
2694 value[i] = lds_load(ctx, dw_addr);
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 ctx->i32one, "");
2697 }
2698 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2699 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2700 return result;
2701 }
2702
2703 static LLVMValueRef
2704 load_tcs_output(struct nir_to_llvm_context *ctx,
2705 nir_intrinsic_instr *instr)
2706 {
2707 LLVMValueRef dw_addr;
2708 LLVMValueRef stride = NULL;
2709 LLVMValueRef value[4], result;
2710 LLVMValueRef vertex_index = NULL;
2711 LLVMValueRef indir_index = NULL;
2712 unsigned const_index = 0;
2713 unsigned param;
2714 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2715 const bool is_compact = instr->variables[0]->var->data.compact;
2716 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2717 get_deref_offset(ctx->nir, instr->variables[0],
2718 false, NULL, per_vertex ? &vertex_index : NULL,
2719 &const_index, &indir_index);
2720
2721 if (!instr->variables[0]->var->data.patch) {
2722 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2723 dw_addr = get_tcs_out_current_patch_offset(ctx);
2724 } else {
2725 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2726 }
2727
2728 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2729 indir_index);
2730
2731 for (unsigned i = 0; i < instr->num_components; i++) {
2732 value[i] = lds_load(ctx, dw_addr);
2733 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2734 ctx->i32one, "");
2735 }
2736 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2737 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2738 return result;
2739 }
2740
2741 static void
2742 store_tcs_output(struct nir_to_llvm_context *ctx,
2743 nir_intrinsic_instr *instr,
2744 LLVMValueRef src,
2745 unsigned writemask)
2746 {
2747 LLVMValueRef dw_addr;
2748 LLVMValueRef stride = NULL;
2749 LLVMValueRef buf_addr = NULL;
2750 LLVMValueRef vertex_index = NULL;
2751 LLVMValueRef indir_index = NULL;
2752 unsigned const_index = 0;
2753 unsigned param;
2754 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2755 const bool is_compact = instr->variables[0]->var->data.compact;
2756
2757 get_deref_offset(ctx->nir, instr->variables[0],
2758 false, NULL, per_vertex ? &vertex_index : NULL,
2759 &const_index, &indir_index);
2760
2761 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2762 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2763 is_compact && const_index > 3) {
2764 const_index -= 3;
2765 param++;
2766 }
2767
2768 if (!instr->variables[0]->var->data.patch) {
2769 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2770 dw_addr = get_tcs_out_current_patch_offset(ctx);
2771 } else {
2772 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2773 }
2774
2775 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2776
2777 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2778 indir_index);
2779 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2780 vertex_index, indir_index);
2781
2782 unsigned base = is_compact ? const_index : 0;
2783 for (unsigned chan = 0; chan < 8; chan++) {
2784 bool is_tess_factor = false;
2785 if (!(writemask & (1 << chan)))
2786 continue;
2787 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2788
2789 lds_store(ctx, dw_addr, value);
2790
2791 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2792 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2793 is_tess_factor = true;
2794
2795 if (!is_tess_factor && writemask != 0xF)
2796 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2797 buf_addr, ctx->oc_lds,
2798 4 * (base + chan), 1, 0, true, false);
2799
2800 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2801 ctx->i32one, "");
2802 }
2803
2804 if (writemask == 0xF) {
2805 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2806 buf_addr, ctx->oc_lds,
2807 (base * 4), 1, 0, true, false);
2808 }
2809 }
2810
2811 static LLVMValueRef
2812 load_tes_input(struct nir_to_llvm_context *ctx,
2813 const nir_intrinsic_instr *instr)
2814 {
2815 LLVMValueRef buf_addr;
2816 LLVMValueRef result;
2817 LLVMValueRef vertex_index = NULL;
2818 LLVMValueRef indir_index = NULL;
2819 unsigned const_index = 0;
2820 unsigned param;
2821 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2822 const bool is_compact = instr->variables[0]->var->data.compact;
2823
2824 get_deref_offset(ctx->nir, instr->variables[0],
2825 false, NULL, per_vertex ? &vertex_index : NULL,
2826 &const_index, &indir_index);
2827 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2828 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2829 is_compact && const_index > 3) {
2830 const_index -= 3;
2831 param++;
2832 }
2833 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2834 is_compact, vertex_index, indir_index);
2835
2836 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2837 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2838 result = trim_vector(&ctx->ac, result, instr->num_components);
2839 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2840 return result;
2841 }
2842
2843 static LLVMValueRef
2844 load_gs_input(struct nir_to_llvm_context *ctx,
2845 nir_intrinsic_instr *instr)
2846 {
2847 LLVMValueRef indir_index, vtx_offset;
2848 unsigned const_index;
2849 LLVMValueRef args[9];
2850 unsigned param, vtx_offset_param;
2851 LLVMValueRef value[4], result;
2852 unsigned vertex_index;
2853 get_deref_offset(ctx->nir, instr->variables[0],
2854 false, &vertex_index, NULL,
2855 &const_index, &indir_index);
2856 vtx_offset_param = vertex_index;
2857 assert(vtx_offset_param < 6);
2858 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2859 LLVMConstInt(ctx->i32, 4, false), "");
2860
2861 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2862 for (unsigned i = 0; i < instr->num_components; i++) {
2863
2864 args[0] = ctx->esgs_ring;
2865 args[1] = vtx_offset;
2866 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2867 args[3] = ctx->i32zero;
2868 args[4] = ctx->i32one; /* OFFEN */
2869 args[5] = ctx->i32zero; /* IDXEN */
2870 args[6] = ctx->i32one; /* GLC */
2871 args[7] = ctx->i32zero; /* SLC */
2872 args[8] = ctx->i32zero; /* TFE */
2873
2874 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2875 ctx->i32, args, 9,
2876 AC_FUNC_ATTR_READONLY |
2877 AC_FUNC_ATTR_LEGACY);
2878 }
2879 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2880
2881 return result;
2882 }
2883
2884 static LLVMValueRef
2885 build_gep_for_deref(struct ac_nir_context *ctx,
2886 nir_deref_var *deref)
2887 {
2888 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2889 assert(entry->data);
2890 LLVMValueRef val = entry->data;
2891 nir_deref *tail = deref->deref.child;
2892 while (tail != NULL) {
2893 LLVMValueRef offset;
2894 switch (tail->deref_type) {
2895 case nir_deref_type_array: {
2896 nir_deref_array *array = nir_deref_as_array(tail);
2897 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2898 if (array->deref_array_type ==
2899 nir_deref_array_type_indirect) {
2900 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2901 get_src(ctx,
2902 array->indirect),
2903 "");
2904 }
2905 break;
2906 }
2907 case nir_deref_type_struct: {
2908 nir_deref_struct *deref_struct =
2909 nir_deref_as_struct(tail);
2910 offset = LLVMConstInt(ctx->ac.i32,
2911 deref_struct->index, 0);
2912 break;
2913 }
2914 default:
2915 unreachable("bad deref type");
2916 }
2917 val = ac_build_gep0(&ctx->ac, val, offset);
2918 tail = tail->child;
2919 }
2920 return val;
2921 }
2922
2923 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2924 nir_intrinsic_instr *instr)
2925 {
2926 LLVMValueRef values[8];
2927 int idx = instr->variables[0]->var->data.driver_location;
2928 int ve = instr->dest.ssa.num_components;
2929 LLVMValueRef indir_index;
2930 LLVMValueRef ret;
2931 unsigned const_index;
2932 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2933 instr->variables[0]->var->data.mode == nir_var_shader_in;
2934 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2935 &const_index, &indir_index);
2936
2937 if (instr->dest.ssa.bit_size == 64)
2938 ve *= 2;
2939
2940 switch (instr->variables[0]->var->data.mode) {
2941 case nir_var_shader_in:
2942 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2943 return load_tcs_input(ctx->nctx, instr);
2944 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2945 return load_tes_input(ctx->nctx, instr);
2946 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2947 return load_gs_input(ctx->nctx, instr);
2948 }
2949 for (unsigned chan = 0; chan < ve; chan++) {
2950 if (indir_index) {
2951 unsigned count = glsl_count_attribute_slots(
2952 instr->variables[0]->var->type,
2953 ctx->stage == MESA_SHADER_VERTEX);
2954 count -= chan / 4;
2955 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2956 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2957 4, false, true);
2958
2959 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2960 tmp_vec,
2961 indir_index, "");
2962 } else
2963 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2964 }
2965 break;
2966 case nir_var_local:
2967 for (unsigned chan = 0; chan < ve; chan++) {
2968 if (indir_index) {
2969 unsigned count = glsl_count_attribute_slots(
2970 instr->variables[0]->var->type, false);
2971 count -= chan / 4;
2972 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2973 &ctx->ac, ctx->locals + idx + chan, count,
2974 4, true, true);
2975
2976 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2977 tmp_vec,
2978 indir_index, "");
2979 } else {
2980 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
2981 }
2982 }
2983 break;
2984 case nir_var_shared: {
2985 LLVMValueRef address = build_gep_for_deref(ctx,
2986 instr->variables[0]);
2987 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
2988 return LLVMBuildBitCast(ctx->ac.builder, val,
2989 get_def_type(ctx, &instr->dest.ssa),
2990 "");
2991 }
2992 case nir_var_shader_out:
2993 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2994 return load_tcs_output(ctx->nctx, instr);
2995 for (unsigned chan = 0; chan < ve; chan++) {
2996 if (indir_index) {
2997 unsigned count = glsl_count_attribute_slots(
2998 instr->variables[0]->var->type, false);
2999 count -= chan / 4;
3000 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3001 &ctx->ac, ctx->outputs + idx + chan, count,
3002 4, true, true);
3003
3004 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3005 tmp_vec,
3006 indir_index, "");
3007 } else {
3008 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3009 ctx->outputs[idx + chan + const_index * 4],
3010 "");
3011 }
3012 }
3013 break;
3014 default:
3015 unreachable("unhandle variable mode");
3016 }
3017 ret = ac_build_gather_values(&ctx->ac, values, ve);
3018 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3019 }
3020
3021 static void
3022 visit_store_var(struct ac_nir_context *ctx,
3023 nir_intrinsic_instr *instr)
3024 {
3025 LLVMValueRef temp_ptr, value;
3026 int idx = instr->variables[0]->var->data.driver_location;
3027 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3028 int writemask = instr->const_index[0];
3029 LLVMValueRef indir_index;
3030 unsigned const_index;
3031 get_deref_offset(ctx, instr->variables[0], false,
3032 NULL, NULL, &const_index, &indir_index);
3033
3034 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3035 int old_writemask = writemask;
3036
3037 src = LLVMBuildBitCast(ctx->ac.builder, src,
3038 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3039 "");
3040
3041 writemask = 0;
3042 for (unsigned chan = 0; chan < 4; chan++) {
3043 if (old_writemask & (1 << chan))
3044 writemask |= 3u << (2 * chan);
3045 }
3046 }
3047
3048 switch (instr->variables[0]->var->data.mode) {
3049 case nir_var_shader_out:
3050
3051 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3052 store_tcs_output(ctx->nctx, instr, src, writemask);
3053 return;
3054 }
3055
3056 for (unsigned chan = 0; chan < 8; chan++) {
3057 int stride = 4;
3058 if (!(writemask & (1 << chan)))
3059 continue;
3060
3061 value = llvm_extract_elem(&ctx->ac, src, chan);
3062
3063 if (instr->variables[0]->var->data.compact)
3064 stride = 1;
3065 if (indir_index) {
3066 unsigned count = glsl_count_attribute_slots(
3067 instr->variables[0]->var->type, false);
3068 count -= chan / 4;
3069 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3070 &ctx->ac, ctx->outputs + idx + chan, count,
3071 stride, true, true);
3072
3073 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3074 value, indir_index, "");
3075 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3076 count, stride, tmp_vec);
3077
3078 } else {
3079 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3080
3081 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3082 }
3083 }
3084 break;
3085 case nir_var_local:
3086 for (unsigned chan = 0; chan < 8; chan++) {
3087 if (!(writemask & (1 << chan)))
3088 continue;
3089
3090 value = llvm_extract_elem(&ctx->ac, src, chan);
3091 if (indir_index) {
3092 unsigned count = glsl_count_attribute_slots(
3093 instr->variables[0]->var->type, false);
3094 count -= chan / 4;
3095 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3096 &ctx->ac, ctx->locals + idx + chan, count,
3097 4, true, true);
3098
3099 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3100 value, indir_index, "");
3101 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3102 count, 4, tmp_vec);
3103 } else {
3104 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3105
3106 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3107 }
3108 }
3109 break;
3110 case nir_var_shared: {
3111 int writemask = instr->const_index[0];
3112 LLVMValueRef address = build_gep_for_deref(ctx,
3113 instr->variables[0]);
3114 LLVMValueRef val = get_src(ctx, instr->src[0]);
3115 unsigned components =
3116 glsl_get_vector_elements(
3117 nir_deref_tail(&instr->variables[0]->deref)->type);
3118 if (writemask == (1 << components) - 1) {
3119 val = LLVMBuildBitCast(
3120 ctx->ac.builder, val,
3121 LLVMGetElementType(LLVMTypeOf(address)), "");
3122 LLVMBuildStore(ctx->ac.builder, val, address);
3123 } else {
3124 for (unsigned chan = 0; chan < 4; chan++) {
3125 if (!(writemask & (1 << chan)))
3126 continue;
3127 LLVMValueRef ptr =
3128 LLVMBuildStructGEP(ctx->ac.builder,
3129 address, chan, "");
3130 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3131 chan);
3132 src = LLVMBuildBitCast(
3133 ctx->ac.builder, src,
3134 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3135 LLVMBuildStore(ctx->ac.builder, src, ptr);
3136 }
3137 }
3138 break;
3139 }
3140 default:
3141 break;
3142 }
3143 }
3144
3145 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3146 {
3147 switch (dim) {
3148 case GLSL_SAMPLER_DIM_BUF:
3149 return 1;
3150 case GLSL_SAMPLER_DIM_1D:
3151 return array ? 2 : 1;
3152 case GLSL_SAMPLER_DIM_2D:
3153 return array ? 3 : 2;
3154 case GLSL_SAMPLER_DIM_MS:
3155 return array ? 4 : 3;
3156 case GLSL_SAMPLER_DIM_3D:
3157 case GLSL_SAMPLER_DIM_CUBE:
3158 return 3;
3159 case GLSL_SAMPLER_DIM_RECT:
3160 case GLSL_SAMPLER_DIM_SUBPASS:
3161 return 2;
3162 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3163 return 3;
3164 default:
3165 break;
3166 }
3167 return 0;
3168 }
3169
3170
3171
3172 /* Adjust the sample index according to FMASK.
3173 *
3174 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3175 * which is the identity mapping. Each nibble says which physical sample
3176 * should be fetched to get that sample.
3177 *
3178 * For example, 0x11111100 means there are only 2 samples stored and
3179 * the second sample covers 3/4 of the pixel. When reading samples 0
3180 * and 1, return physical sample 0 (determined by the first two 0s
3181 * in FMASK), otherwise return physical sample 1.
3182 *
3183 * The sample index should be adjusted as follows:
3184 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3185 */
3186 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3187 LLVMValueRef coord_x, LLVMValueRef coord_y,
3188 LLVMValueRef coord_z,
3189 LLVMValueRef sample_index,
3190 LLVMValueRef fmask_desc_ptr)
3191 {
3192 LLVMValueRef fmask_load_address[4];
3193 LLVMValueRef res;
3194
3195 fmask_load_address[0] = coord_x;
3196 fmask_load_address[1] = coord_y;
3197 if (coord_z) {
3198 fmask_load_address[2] = coord_z;
3199 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3200 }
3201
3202 struct ac_image_args args = {0};
3203
3204 args.opcode = ac_image_load;
3205 args.da = coord_z ? true : false;
3206 args.resource = fmask_desc_ptr;
3207 args.dmask = 0xf;
3208 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3209
3210 res = ac_build_image_opcode(ctx, &args);
3211
3212 res = ac_to_integer(ctx, res);
3213 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3214 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3215
3216 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3217 res,
3218 ctx->i32_0, "");
3219
3220 LLVMValueRef sample_index4 =
3221 LLVMBuildMul(ctx->builder, sample_index, four, "");
3222 LLVMValueRef shifted_fmask =
3223 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3224 LLVMValueRef final_sample =
3225 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3226
3227 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3228 * resource descriptor is 0 (invalid),
3229 */
3230 LLVMValueRef fmask_desc =
3231 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3232 ctx->v8i32, "");
3233
3234 LLVMValueRef fmask_word1 =
3235 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3236 ctx->i32_1, "");
3237
3238 LLVMValueRef word1_is_nonzero =
3239 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3240 fmask_word1, ctx->i32_0, "");
3241
3242 /* Replace the MSAA sample index. */
3243 sample_index =
3244 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3245 final_sample, sample_index, "");
3246 return sample_index;
3247 }
3248
3249 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3250 const nir_intrinsic_instr *instr)
3251 {
3252 const struct glsl_type *type = instr->variables[0]->var->type;
3253 if(instr->variables[0]->deref.child)
3254 type = instr->variables[0]->deref.child->type;
3255
3256 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3257 LLVMValueRef coords[4];
3258 LLVMValueRef masks[] = {
3259 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3260 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3261 };
3262 LLVMValueRef res;
3263 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3264
3265 int count;
3266 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3267 bool is_array = glsl_sampler_type_is_array(type);
3268 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3269 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3270 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3271 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3272 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3273 count = image_type_to_components_count(dim, is_array);
3274
3275 if (is_ms) {
3276 LLVMValueRef fmask_load_address[3];
3277 int chan;
3278
3279 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3280 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3281 if (is_array)
3282 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3283 else
3284 fmask_load_address[2] = NULL;
3285 if (add_frag_pos) {
3286 for (chan = 0; chan < 2; ++chan)
3287 fmask_load_address[chan] =
3288 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3289 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3290 ctx->ac.i32, ""), "");
3291 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3292 }
3293 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3294 fmask_load_address[0],
3295 fmask_load_address[1],
3296 fmask_load_address[2],
3297 sample_index,
3298 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3299 }
3300 if (count == 1 && !gfx9_1d) {
3301 if (instr->src[0].ssa->num_components)
3302 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3303 else
3304 res = src0;
3305 } else {
3306 int chan;
3307 if (is_ms)
3308 count--;
3309 for (chan = 0; chan < count; ++chan) {
3310 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3311 }
3312 if (add_frag_pos) {
3313 for (chan = 0; chan < 2; ++chan)
3314 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3315 ctx->ac.i32, ""), "");
3316 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3317 count++;
3318 }
3319
3320 if (gfx9_1d) {
3321 if (is_array) {
3322 coords[2] = coords[1];
3323 coords[1] = ctx->ac.i32_0;
3324 } else
3325 coords[1] = ctx->ac.i32_0;
3326 count++;
3327 }
3328
3329 if (is_ms) {
3330 coords[count] = sample_index;
3331 count++;
3332 }
3333
3334 if (count == 3) {
3335 coords[3] = LLVMGetUndef(ctx->ac.i32);
3336 count = 4;
3337 }
3338 res = ac_build_gather_values(&ctx->ac, coords, count);
3339 }
3340 return res;
3341 }
3342
3343 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3344 const nir_intrinsic_instr *instr)
3345 {
3346 LLVMValueRef params[7];
3347 LLVMValueRef res;
3348 char intrinsic_name[64];
3349 const nir_variable *var = instr->variables[0]->var;
3350 const struct glsl_type *type = var->type;
3351 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3352 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3353
3354 if(instr->variables[0]->deref.child)
3355 type = instr->variables[0]->deref.child->type;
3356
3357 type = glsl_without_array(type);
3358 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3359 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3360 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3361 ctx->ac.i32_0, ""); /* vindex */
3362 params[2] = ctx->ac.i32_0; /* voffset */
3363 params[3] = i1false; /* glc */
3364 params[4] = i1false; /* slc */
3365 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3366 params, 5, 0);
3367
3368 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3369 res = ac_to_integer(&ctx->ac, res);
3370 } else {
3371 bool is_da = glsl_sampler_type_is_array(type) ||
3372 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3373 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3374 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3375 LLVMValueRef da = is_da ? i1true : i1false;
3376 LLVMValueRef glc = i1false;
3377 LLVMValueRef slc = i1false;
3378
3379 params[0] = get_image_coords(ctx, instr);
3380 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3381 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3382 if (HAVE_LLVM <= 0x0309) {
3383 params[3] = i1false; /* r128 */
3384 params[4] = da;
3385 params[5] = glc;
3386 params[6] = slc;
3387 } else {
3388 LLVMValueRef lwe = i1false;
3389 params[3] = glc;
3390 params[4] = slc;
3391 params[5] = lwe;
3392 params[6] = da;
3393 }
3394
3395 ac_get_image_intr_name("llvm.amdgcn.image.load",
3396 ctx->ac.v4f32, /* vdata */
3397 LLVMTypeOf(params[0]), /* coords */
3398 LLVMTypeOf(params[1]), /* rsrc */
3399 intrinsic_name, sizeof(intrinsic_name));
3400
3401 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3402 params, 7, AC_FUNC_ATTR_READONLY);
3403 }
3404 return ac_to_integer(&ctx->ac, res);
3405 }
3406
3407 static void visit_image_store(struct ac_nir_context *ctx,
3408 nir_intrinsic_instr *instr)
3409 {
3410 LLVMValueRef params[8];
3411 char intrinsic_name[64];
3412 const nir_variable *var = instr->variables[0]->var;
3413 const struct glsl_type *type = glsl_without_array(var->type);
3414 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3415 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3416 LLVMValueRef glc = i1false;
3417 bool force_glc = ctx->ac.chip_class == SI;
3418 if (force_glc)
3419 glc = i1true;
3420
3421 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3422 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3423 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3424 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3425 ctx->ac.i32_0, ""); /* vindex */
3426 params[3] = ctx->ac.i32_0; /* voffset */
3427 params[4] = glc; /* glc */
3428 params[5] = i1false; /* slc */
3429 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3430 params, 6, 0);
3431 } else {
3432 bool is_da = glsl_sampler_type_is_array(type) ||
3433 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3434 LLVMValueRef da = is_da ? i1true : i1false;
3435 LLVMValueRef slc = i1false;
3436
3437 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3438 params[1] = get_image_coords(ctx, instr); /* coords */
3439 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3440 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3441 if (HAVE_LLVM <= 0x0309) {
3442 params[4] = i1false; /* r128 */
3443 params[5] = da;
3444 params[6] = glc;
3445 params[7] = slc;
3446 } else {
3447 LLVMValueRef lwe = i1false;
3448 params[4] = glc;
3449 params[5] = slc;
3450 params[6] = lwe;
3451 params[7] = da;
3452 }
3453
3454 ac_get_image_intr_name("llvm.amdgcn.image.store",
3455 LLVMTypeOf(params[0]), /* vdata */
3456 LLVMTypeOf(params[1]), /* coords */
3457 LLVMTypeOf(params[2]), /* rsrc */
3458 intrinsic_name, sizeof(intrinsic_name));
3459
3460 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3461 params, 8, 0);
3462 }
3463
3464 }
3465
3466 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3467 const nir_intrinsic_instr *instr)
3468 {
3469 LLVMValueRef params[7];
3470 int param_count = 0;
3471 const nir_variable *var = instr->variables[0]->var;
3472
3473 const char *atomic_name;
3474 char intrinsic_name[41];
3475 const struct glsl_type *type = glsl_without_array(var->type);
3476 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3477 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3478 MAYBE_UNUSED int length;
3479
3480 switch (instr->intrinsic) {
3481 case nir_intrinsic_image_atomic_add:
3482 atomic_name = "add";
3483 break;
3484 case nir_intrinsic_image_atomic_min:
3485 atomic_name = "smin";
3486 break;
3487 case nir_intrinsic_image_atomic_max:
3488 atomic_name = "smax";
3489 break;
3490 case nir_intrinsic_image_atomic_and:
3491 atomic_name = "and";
3492 break;
3493 case nir_intrinsic_image_atomic_or:
3494 atomic_name = "or";
3495 break;
3496 case nir_intrinsic_image_atomic_xor:
3497 atomic_name = "xor";
3498 break;
3499 case nir_intrinsic_image_atomic_exchange:
3500 atomic_name = "swap";
3501 break;
3502 case nir_intrinsic_image_atomic_comp_swap:
3503 atomic_name = "cmpswap";
3504 break;
3505 default:
3506 abort();
3507 }
3508
3509 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3510 params[param_count++] = get_src(ctx, instr->src[3]);
3511 params[param_count++] = get_src(ctx, instr->src[2]);
3512
3513 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3514 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3515 true, true);
3516 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3517 ctx->ac.i32_0, ""); /* vindex */
3518 params[param_count++] = ctx->ac.i32_0; /* voffset */
3519 params[param_count++] = i1false; /* slc */
3520
3521 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3522 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3523 } else {
3524 char coords_type[8];
3525
3526 bool da = glsl_sampler_type_is_array(type) ||
3527 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3528
3529 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3530 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3531 true, true);
3532 params[param_count++] = i1false; /* r128 */
3533 params[param_count++] = da ? i1true : i1false; /* da */
3534 params[param_count++] = i1false; /* slc */
3535
3536 build_int_type_name(LLVMTypeOf(coords),
3537 coords_type, sizeof(coords_type));
3538
3539 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3540 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3541 }
3542
3543 assert(length < sizeof(intrinsic_name));
3544 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3545 }
3546
3547 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3548 const nir_intrinsic_instr *instr)
3549 {
3550 LLVMValueRef res;
3551 const nir_variable *var = instr->variables[0]->var;
3552 const struct glsl_type *type = instr->variables[0]->var->type;
3553 bool da = glsl_sampler_type_is_array(var->type) ||
3554 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3555 if(instr->variables[0]->deref.child)
3556 type = instr->variables[0]->deref.child->type;
3557
3558 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3559 return get_buffer_size(ctx,
3560 get_sampler_desc(ctx, instr->variables[0],
3561 AC_DESC_BUFFER, true, false), true);
3562
3563 struct ac_image_args args = { 0 };
3564
3565 args.da = da;
3566 args.dmask = 0xf;
3567 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3568 args.opcode = ac_image_get_resinfo;
3569 args.addr = ctx->ac.i32_0;
3570
3571 res = ac_build_image_opcode(&ctx->ac, &args);
3572
3573 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3574
3575 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3576 glsl_sampler_type_is_array(type)) {
3577 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3578 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3579 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3580 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3581 }
3582 if (ctx->ac.chip_class >= GFX9 &&
3583 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3584 glsl_sampler_type_is_array(type)) {
3585 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3586 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3587 ctx->ac.i32_1, "");
3588
3589 }
3590 return res;
3591 }
3592
3593 #define NOOP_WAITCNT 0xf7f
3594 #define LGKM_CNT 0x07f
3595 #define VM_CNT 0xf70
3596
3597 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3598 unsigned simm16)
3599 {
3600 LLVMValueRef args[1] = {
3601 LLVMConstInt(ctx->i32, simm16, false),
3602 };
3603 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3604 ctx->voidt, args, 1, 0);
3605 }
3606
3607 static void emit_barrier(struct nir_to_llvm_context *ctx)
3608 {
3609 /* SI only (thanks to a hw bug workaround):
3610 * The real barrier instruction isn’t needed, because an entire patch
3611 * always fits into a single wave.
3612 */
3613 if (ctx->options->chip_class == SI &&
3614 ctx->stage == MESA_SHADER_TESS_CTRL) {
3615 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3616 return;
3617 }
3618 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3619 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3620 }
3621
3622 static void emit_discard_if(struct ac_nir_context *ctx,
3623 const nir_intrinsic_instr *instr)
3624 {
3625 LLVMValueRef cond;
3626
3627 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3628 get_src(ctx, instr->src[0]),
3629 ctx->ac.i32_0, "");
3630
3631 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3632 LLVMConstReal(ctx->ac.f32, -1.0f),
3633 ctx->ac.f32_0, "");
3634 ac_build_kill(&ctx->ac, cond);
3635 }
3636
3637 static LLVMValueRef
3638 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3639 {
3640 LLVMValueRef result;
3641 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3642 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3643 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3644
3645 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3646 }
3647
3648 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3649 const nir_intrinsic_instr *instr)
3650 {
3651 LLVMValueRef ptr, result;
3652 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3653 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3654
3655 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3656 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3657 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3658 ptr, src, src1,
3659 LLVMAtomicOrderingSequentiallyConsistent,
3660 LLVMAtomicOrderingSequentiallyConsistent,
3661 false);
3662 } else {
3663 LLVMAtomicRMWBinOp op;
3664 switch (instr->intrinsic) {
3665 case nir_intrinsic_var_atomic_add:
3666 op = LLVMAtomicRMWBinOpAdd;
3667 break;
3668 case nir_intrinsic_var_atomic_umin:
3669 op = LLVMAtomicRMWBinOpUMin;
3670 break;
3671 case nir_intrinsic_var_atomic_umax:
3672 op = LLVMAtomicRMWBinOpUMax;
3673 break;
3674 case nir_intrinsic_var_atomic_imin:
3675 op = LLVMAtomicRMWBinOpMin;
3676 break;
3677 case nir_intrinsic_var_atomic_imax:
3678 op = LLVMAtomicRMWBinOpMax;
3679 break;
3680 case nir_intrinsic_var_atomic_and:
3681 op = LLVMAtomicRMWBinOpAnd;
3682 break;
3683 case nir_intrinsic_var_atomic_or:
3684 op = LLVMAtomicRMWBinOpOr;
3685 break;
3686 case nir_intrinsic_var_atomic_xor:
3687 op = LLVMAtomicRMWBinOpXor;
3688 break;
3689 case nir_intrinsic_var_atomic_exchange:
3690 op = LLVMAtomicRMWBinOpXchg;
3691 break;
3692 default:
3693 return NULL;
3694 }
3695
3696 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3697 LLVMAtomicOrderingSequentiallyConsistent,
3698 false);
3699 }
3700 return result;
3701 }
3702
3703 #define INTERP_CENTER 0
3704 #define INTERP_CENTROID 1
3705 #define INTERP_SAMPLE 2
3706
3707 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3708 enum glsl_interp_mode interp, unsigned location)
3709 {
3710 switch (interp) {
3711 case INTERP_MODE_FLAT:
3712 default:
3713 return NULL;
3714 case INTERP_MODE_SMOOTH:
3715 case INTERP_MODE_NONE:
3716 if (location == INTERP_CENTER)
3717 return ctx->persp_center;
3718 else if (location == INTERP_CENTROID)
3719 return ctx->persp_centroid;
3720 else if (location == INTERP_SAMPLE)
3721 return ctx->persp_sample;
3722 break;
3723 case INTERP_MODE_NOPERSPECTIVE:
3724 if (location == INTERP_CENTER)
3725 return ctx->linear_center;
3726 else if (location == INTERP_CENTROID)
3727 return ctx->linear_centroid;
3728 else if (location == INTERP_SAMPLE)
3729 return ctx->linear_sample;
3730 break;
3731 }
3732 return NULL;
3733 }
3734
3735 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3736 LLVMValueRef sample_id)
3737 {
3738 LLVMValueRef result;
3739 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3740
3741 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3742 const_array(ctx->v2f32, 64), "");
3743
3744 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3745 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3746
3747 return result;
3748 }
3749
3750 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3751 {
3752 LLVMValueRef values[2];
3753
3754 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3755 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3756 return ac_build_gather_values(&ctx->ac, values, 2);
3757 }
3758
3759 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3760 const nir_intrinsic_instr *instr)
3761 {
3762 LLVMValueRef result[2];
3763 LLVMValueRef interp_param, attr_number;
3764 unsigned location;
3765 unsigned chan;
3766 LLVMValueRef src_c0 = NULL;
3767 LLVMValueRef src_c1 = NULL;
3768 LLVMValueRef src0 = NULL;
3769 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3770 switch (instr->intrinsic) {
3771 case nir_intrinsic_interp_var_at_centroid:
3772 location = INTERP_CENTROID;
3773 break;
3774 case nir_intrinsic_interp_var_at_sample:
3775 case nir_intrinsic_interp_var_at_offset:
3776 location = INTERP_CENTER;
3777 src0 = get_src(ctx->nir, instr->src[0]);
3778 break;
3779 default:
3780 break;
3781 }
3782
3783 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3784 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3785 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3786 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3787 LLVMValueRef sample_position;
3788 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3789
3790 /* fetch sample ID */
3791 sample_position = load_sample_position(ctx, src0);
3792
3793 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3794 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3795 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3796 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3797 }
3798 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3799 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3800
3801 if (location == INTERP_CENTER) {
3802 LLVMValueRef ij_out[2];
3803 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3804
3805 /*
3806 * take the I then J parameters, and the DDX/Y for it, and
3807 * calculate the IJ inputs for the interpolator.
3808 * temp1 = ddx * offset/sample.x + I;
3809 * interp_param.I = ddy * offset/sample.y + temp1;
3810 * temp1 = ddx * offset/sample.x + J;
3811 * interp_param.J = ddy * offset/sample.y + temp1;
3812 */
3813 for (unsigned i = 0; i < 2; i++) {
3814 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3815 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3816 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3817 ddxy_out, ix_ll, "");
3818 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3819 ddxy_out, iy_ll, "");
3820 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3821 interp_param, ix_ll, "");
3822 LLVMValueRef temp1, temp2;
3823
3824 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3825 ctx->f32, "");
3826
3827 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3828 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3829
3830 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3831 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3832
3833 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3834 temp2, ctx->i32, "");
3835 }
3836 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3837
3838 }
3839
3840 for (chan = 0; chan < 2; chan++) {
3841 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3842
3843 if (interp_param) {
3844 interp_param = LLVMBuildBitCast(ctx->builder,
3845 interp_param, LLVMVectorType(ctx->f32, 2), "");
3846 LLVMValueRef i = LLVMBuildExtractElement(
3847 ctx->builder, interp_param, ctx->i32zero, "");
3848 LLVMValueRef j = LLVMBuildExtractElement(
3849 ctx->builder, interp_param, ctx->i32one, "");
3850
3851 result[chan] = ac_build_fs_interp(&ctx->ac,
3852 llvm_chan, attr_number,
3853 ctx->prim_mask, i, j);
3854 } else {
3855 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3856 LLVMConstInt(ctx->i32, 2, false),
3857 llvm_chan, attr_number,
3858 ctx->prim_mask);
3859 }
3860 }
3861 return ac_build_gather_values(&ctx->ac, result, 2);
3862 }
3863
3864 static void
3865 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3866 const nir_intrinsic_instr *instr)
3867 {
3868 LLVMValueRef gs_next_vertex;
3869 LLVMValueRef can_emit, kill;
3870 int idx;
3871
3872 assert(instr->const_index[0] == 0);
3873 /* Write vertex attribute values to GSVS ring */
3874 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3875 ctx->gs_next_vertex,
3876 "");
3877
3878 /* If this thread has already emitted the declared maximum number of
3879 * vertices, kill it: excessive vertex emissions are not supposed to
3880 * have any effect, and GS threads have no externally observable
3881 * effects other than emitting vertices.
3882 */
3883 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3884 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3885
3886 kill = LLVMBuildSelect(ctx->builder, can_emit,
3887 LLVMConstReal(ctx->f32, 1.0f),
3888 LLVMConstReal(ctx->f32, -1.0f), "");
3889 ac_build_kill(&ctx->ac, kill);
3890
3891 /* loop num outputs */
3892 idx = 0;
3893 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3894 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3895 int length = 4;
3896 int slot = idx;
3897 int slot_inc = 1;
3898
3899 if (!(ctx->output_mask & (1ull << i)))
3900 continue;
3901
3902 if (i == VARYING_SLOT_CLIP_DIST0) {
3903 /* pack clip and cull into a single set of slots */
3904 length = ctx->num_output_clips + ctx->num_output_culls;
3905 if (length > 4)
3906 slot_inc = 2;
3907 }
3908 for (unsigned j = 0; j < length; j++) {
3909 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3910 out_ptr[j], "");
3911 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3912 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3913 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3914
3915 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3916
3917 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3918 out_val, 1,
3919 voffset, ctx->gs2vs_offset, 0,
3920 1, 1, true, true);
3921 }
3922 idx += slot_inc;
3923 }
3924
3925 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3926 ctx->i32one, "");
3927 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3928
3929 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3930 }
3931
3932 static void
3933 visit_end_primitive(struct nir_to_llvm_context *ctx,
3934 const nir_intrinsic_instr *instr)
3935 {
3936 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3937 }
3938
3939 static LLVMValueRef
3940 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3941 const nir_intrinsic_instr *instr)
3942 {
3943 LLVMValueRef coord[4] = {
3944 ctx->tes_u,
3945 ctx->tes_v,
3946 ctx->f32zero,
3947 ctx->f32zero,
3948 };
3949
3950 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3951 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3952 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3953
3954 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3955 return LLVMBuildBitCast(ctx->builder, result,
3956 get_def_type(ctx->nir, &instr->dest.ssa), "");
3957 }
3958
3959 static void visit_intrinsic(struct ac_nir_context *ctx,
3960 nir_intrinsic_instr *instr)
3961 {
3962 LLVMValueRef result = NULL;
3963
3964 switch (instr->intrinsic) {
3965 case nir_intrinsic_load_work_group_id: {
3966 result = ctx->nctx->workgroup_ids;
3967 break;
3968 }
3969 case nir_intrinsic_load_base_vertex: {
3970 result = ctx->abi->base_vertex;
3971 break;
3972 }
3973 case nir_intrinsic_load_vertex_id_zero_base: {
3974 result = ctx->abi->vertex_id;
3975 break;
3976 }
3977 case nir_intrinsic_load_local_invocation_id: {
3978 result = ctx->nctx->local_invocation_ids;
3979 break;
3980 }
3981 case nir_intrinsic_load_base_instance:
3982 result = ctx->abi->start_instance;
3983 break;
3984 case nir_intrinsic_load_draw_id:
3985 result = ctx->abi->draw_id;
3986 break;
3987 case nir_intrinsic_load_view_index:
3988 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
3989 break;
3990 case nir_intrinsic_load_invocation_id:
3991 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3992 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
3993 else
3994 result = ctx->nctx->gs_invocation_id;
3995 break;
3996 case nir_intrinsic_load_primitive_id:
3997 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3998 ctx->nctx->shader_info->gs.uses_prim_id = true;
3999 result = ctx->nctx->gs_prim_id;
4000 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4001 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4002 result = ctx->nctx->tcs_patch_id;
4003 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4004 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4005 result = ctx->nctx->tes_patch_id;
4006 } else
4007 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4008 break;
4009 case nir_intrinsic_load_sample_id:
4010 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4011 break;
4012 case nir_intrinsic_load_sample_pos:
4013 result = load_sample_pos(ctx);
4014 break;
4015 case nir_intrinsic_load_sample_mask_in:
4016 result = ctx->abi->sample_coverage;
4017 break;
4018 case nir_intrinsic_load_frag_coord: {
4019 LLVMValueRef values[4] = {
4020 ctx->abi->frag_pos[0],
4021 ctx->abi->frag_pos[1],
4022 ctx->abi->frag_pos[2],
4023 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4024 };
4025 result = ac_build_gather_values(&ctx->ac, values, 4);
4026 break;
4027 }
4028 case nir_intrinsic_load_front_face:
4029 result = ctx->abi->front_face;
4030 break;
4031 case nir_intrinsic_load_instance_id:
4032 result = ctx->abi->instance_id;
4033 break;
4034 case nir_intrinsic_load_num_work_groups:
4035 result = ctx->nctx->num_work_groups;
4036 break;
4037 case nir_intrinsic_load_local_invocation_index:
4038 result = visit_load_local_invocation_index(ctx->nctx);
4039 break;
4040 case nir_intrinsic_load_push_constant:
4041 result = visit_load_push_constant(ctx->nctx, instr);
4042 break;
4043 case nir_intrinsic_vulkan_resource_index:
4044 result = visit_vulkan_resource_index(ctx->nctx, instr);
4045 break;
4046 case nir_intrinsic_store_ssbo:
4047 visit_store_ssbo(ctx, instr);
4048 break;
4049 case nir_intrinsic_load_ssbo:
4050 result = visit_load_buffer(ctx, instr);
4051 break;
4052 case nir_intrinsic_ssbo_atomic_add:
4053 case nir_intrinsic_ssbo_atomic_imin:
4054 case nir_intrinsic_ssbo_atomic_umin:
4055 case nir_intrinsic_ssbo_atomic_imax:
4056 case nir_intrinsic_ssbo_atomic_umax:
4057 case nir_intrinsic_ssbo_atomic_and:
4058 case nir_intrinsic_ssbo_atomic_or:
4059 case nir_intrinsic_ssbo_atomic_xor:
4060 case nir_intrinsic_ssbo_atomic_exchange:
4061 case nir_intrinsic_ssbo_atomic_comp_swap:
4062 result = visit_atomic_ssbo(ctx, instr);
4063 break;
4064 case nir_intrinsic_load_ubo:
4065 result = visit_load_ubo_buffer(ctx, instr);
4066 break;
4067 case nir_intrinsic_get_buffer_size:
4068 result = visit_get_buffer_size(ctx, instr);
4069 break;
4070 case nir_intrinsic_load_var:
4071 result = visit_load_var(ctx, instr);
4072 break;
4073 case nir_intrinsic_store_var:
4074 visit_store_var(ctx, instr);
4075 break;
4076 case nir_intrinsic_image_load:
4077 result = visit_image_load(ctx, instr);
4078 break;
4079 case nir_intrinsic_image_store:
4080 visit_image_store(ctx, instr);
4081 break;
4082 case nir_intrinsic_image_atomic_add:
4083 case nir_intrinsic_image_atomic_min:
4084 case nir_intrinsic_image_atomic_max:
4085 case nir_intrinsic_image_atomic_and:
4086 case nir_intrinsic_image_atomic_or:
4087 case nir_intrinsic_image_atomic_xor:
4088 case nir_intrinsic_image_atomic_exchange:
4089 case nir_intrinsic_image_atomic_comp_swap:
4090 result = visit_image_atomic(ctx, instr);
4091 break;
4092 case nir_intrinsic_image_size:
4093 result = visit_image_size(ctx, instr);
4094 break;
4095 case nir_intrinsic_discard:
4096 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4097 LLVMVoidTypeInContext(ctx->ac.context),
4098 NULL, 0, AC_FUNC_ATTR_LEGACY);
4099 break;
4100 case nir_intrinsic_discard_if:
4101 emit_discard_if(ctx, instr);
4102 break;
4103 case nir_intrinsic_memory_barrier:
4104 emit_waitcnt(ctx->nctx, VM_CNT);
4105 break;
4106 case nir_intrinsic_barrier:
4107 emit_barrier(ctx->nctx);
4108 break;
4109 case nir_intrinsic_var_atomic_add:
4110 case nir_intrinsic_var_atomic_imin:
4111 case nir_intrinsic_var_atomic_umin:
4112 case nir_intrinsic_var_atomic_imax:
4113 case nir_intrinsic_var_atomic_umax:
4114 case nir_intrinsic_var_atomic_and:
4115 case nir_intrinsic_var_atomic_or:
4116 case nir_intrinsic_var_atomic_xor:
4117 case nir_intrinsic_var_atomic_exchange:
4118 case nir_intrinsic_var_atomic_comp_swap:
4119 result = visit_var_atomic(ctx->nctx, instr);
4120 break;
4121 case nir_intrinsic_interp_var_at_centroid:
4122 case nir_intrinsic_interp_var_at_sample:
4123 case nir_intrinsic_interp_var_at_offset:
4124 result = visit_interp(ctx->nctx, instr);
4125 break;
4126 case nir_intrinsic_emit_vertex:
4127 visit_emit_vertex(ctx->nctx, instr);
4128 break;
4129 case nir_intrinsic_end_primitive:
4130 visit_end_primitive(ctx->nctx, instr);
4131 break;
4132 case nir_intrinsic_load_tess_coord:
4133 result = visit_load_tess_coord(ctx->nctx, instr);
4134 break;
4135 case nir_intrinsic_load_patch_vertices_in:
4136 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4137 break;
4138 default:
4139 fprintf(stderr, "Unknown intrinsic: ");
4140 nir_print_instr(&instr->instr, stderr);
4141 fprintf(stderr, "\n");
4142 break;
4143 }
4144 if (result) {
4145 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4146 }
4147 }
4148
4149 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4150 LLVMValueRef buffer, bool write)
4151 {
4152 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4153
4154 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4155 ctx->shader_info->fs.writes_memory = true;
4156
4157 return buffer;
4158 }
4159
4160 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4161 unsigned descriptor_set,
4162 unsigned base_index,
4163 unsigned constant_index,
4164 LLVMValueRef index,
4165 enum ac_descriptor_type desc_type,
4166 bool image, bool write)
4167 {
4168 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4169 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4170 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4171 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4172 unsigned offset = binding->offset;
4173 unsigned stride = binding->size;
4174 unsigned type_size;
4175 LLVMBuilderRef builder = ctx->builder;
4176 LLVMTypeRef type;
4177
4178 assert(base_index < layout->binding_count);
4179
4180 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4181 ctx->shader_info->fs.writes_memory = true;
4182
4183 switch (desc_type) {
4184 case AC_DESC_IMAGE:
4185 type = ctx->v8i32;
4186 type_size = 32;
4187 break;
4188 case AC_DESC_FMASK:
4189 type = ctx->v8i32;
4190 offset += 32;
4191 type_size = 32;
4192 break;
4193 case AC_DESC_SAMPLER:
4194 type = ctx->v4i32;
4195 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4196 offset += 64;
4197
4198 type_size = 16;
4199 break;
4200 case AC_DESC_BUFFER:
4201 type = ctx->v4i32;
4202 type_size = 16;
4203 break;
4204 default:
4205 unreachable("invalid desc_type\n");
4206 }
4207
4208 offset += constant_index * stride;
4209
4210 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4211 (!index || binding->immutable_samplers_equal)) {
4212 if (binding->immutable_samplers_equal)
4213 constant_index = 0;
4214
4215 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4216
4217 LLVMValueRef constants[] = {
4218 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4219 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4220 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4221 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4222 };
4223 return ac_build_gather_values(&ctx->ac, constants, 4);
4224 }
4225
4226 assert(stride % type_size == 0);
4227
4228 if (!index)
4229 index = ctx->i32zero;
4230
4231 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4232
4233 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4234 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4235
4236 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4237 }
4238
4239 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4240 const nir_deref_var *deref,
4241 enum ac_descriptor_type desc_type,
4242 bool image, bool write)
4243 {
4244 LLVMValueRef index = NULL;
4245 unsigned constant_index = 0;
4246 const nir_deref *tail = &deref->deref;
4247
4248 while (tail->child) {
4249 const nir_deref_array *child = nir_deref_as_array(tail->child);
4250 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4251
4252 if (!array_size)
4253 array_size = 1;
4254
4255 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4256
4257 if (child->deref_array_type == nir_deref_array_type_indirect) {
4258 LLVMValueRef indirect = get_src(ctx, child->indirect);
4259
4260 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4261 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4262
4263 if (!index)
4264 index = indirect;
4265 else
4266 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4267 }
4268
4269 constant_index += child->base_offset * array_size;
4270
4271 tail = &child->deref;
4272 }
4273
4274 return ctx->abi->load_sampler_desc(ctx->abi,
4275 deref->var->data.descriptor_set,
4276 deref->var->data.binding,
4277 constant_index, index,
4278 desc_type, image, write);
4279 }
4280
4281 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4282 struct ac_image_args *args,
4283 const nir_tex_instr *instr,
4284 nir_texop op,
4285 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4286 LLVMValueRef *param, unsigned count,
4287 unsigned dmask)
4288 {
4289 unsigned is_rect = 0;
4290 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4291
4292 if (op == nir_texop_lod)
4293 da = false;
4294 /* Pad to power of two vector */
4295 while (count < util_next_power_of_two(count))
4296 param[count++] = LLVMGetUndef(ctx->i32);
4297
4298 if (count > 1)
4299 args->addr = ac_build_gather_values(ctx, param, count);
4300 else
4301 args->addr = param[0];
4302
4303 args->resource = res_ptr;
4304 args->sampler = samp_ptr;
4305
4306 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4307 args->addr = param[0];
4308 return;
4309 }
4310
4311 args->dmask = dmask;
4312 args->unorm = is_rect;
4313 args->da = da;
4314 }
4315
4316 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4317 *
4318 * SI-CI:
4319 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4320 * filtering manually. The driver sets img7 to a mask clearing
4321 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4322 * s_and_b32 samp0, samp0, img7
4323 *
4324 * VI:
4325 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4326 */
4327 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4328 LLVMValueRef res, LLVMValueRef samp)
4329 {
4330 LLVMBuilderRef builder = ctx->ac.builder;
4331 LLVMValueRef img7, samp0;
4332
4333 if (ctx->ac.chip_class >= VI)
4334 return samp;
4335
4336 img7 = LLVMBuildExtractElement(builder, res,
4337 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4338 samp0 = LLVMBuildExtractElement(builder, samp,
4339 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4340 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4341 return LLVMBuildInsertElement(builder, samp, samp0,
4342 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4343 }
4344
4345 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4346 nir_tex_instr *instr,
4347 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4348 LLVMValueRef *fmask_ptr)
4349 {
4350 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4351 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4352 else
4353 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4354 if (samp_ptr) {
4355 if (instr->sampler)
4356 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4357 else
4358 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4359 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4360 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4361 }
4362 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4363 instr->op == nir_texop_samples_identical))
4364 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4365 }
4366
4367 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4368 LLVMValueRef coord)
4369 {
4370 coord = ac_to_float(ctx, coord);
4371 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4372 coord = ac_to_integer(ctx, coord);
4373 return coord;
4374 }
4375
4376 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4377 {
4378 LLVMValueRef result = NULL;
4379 struct ac_image_args args = { 0 };
4380 unsigned dmask = 0xf;
4381 LLVMValueRef address[16];
4382 LLVMValueRef coords[5];
4383 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4384 LLVMValueRef bias = NULL, offsets = NULL;
4385 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4386 LLVMValueRef ddx = NULL, ddy = NULL;
4387 LLVMValueRef derivs[6];
4388 unsigned chan, count = 0;
4389 unsigned const_src = 0, num_deriv_comp = 0;
4390 bool lod_is_zero = false;
4391
4392 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4393
4394 for (unsigned i = 0; i < instr->num_srcs; i++) {
4395 switch (instr->src[i].src_type) {
4396 case nir_tex_src_coord:
4397 coord = get_src(ctx, instr->src[i].src);
4398 break;
4399 case nir_tex_src_projector:
4400 break;
4401 case nir_tex_src_comparator:
4402 comparator = get_src(ctx, instr->src[i].src);
4403 break;
4404 case nir_tex_src_offset:
4405 offsets = get_src(ctx, instr->src[i].src);
4406 const_src = i;
4407 break;
4408 case nir_tex_src_bias:
4409 bias = get_src(ctx, instr->src[i].src);
4410 break;
4411 case nir_tex_src_lod: {
4412 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4413
4414 if (val && val->i32[0] == 0)
4415 lod_is_zero = true;
4416 lod = get_src(ctx, instr->src[i].src);
4417 break;
4418 }
4419 case nir_tex_src_ms_index:
4420 sample_index = get_src(ctx, instr->src[i].src);
4421 break;
4422 case nir_tex_src_ms_mcs:
4423 break;
4424 case nir_tex_src_ddx:
4425 ddx = get_src(ctx, instr->src[i].src);
4426 num_deriv_comp = instr->src[i].src.ssa->num_components;
4427 break;
4428 case nir_tex_src_ddy:
4429 ddy = get_src(ctx, instr->src[i].src);
4430 break;
4431 case nir_tex_src_texture_offset:
4432 case nir_tex_src_sampler_offset:
4433 case nir_tex_src_plane:
4434 default:
4435 break;
4436 }
4437 }
4438
4439 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4440 result = get_buffer_size(ctx, res_ptr, true);
4441 goto write_result;
4442 }
4443
4444 if (instr->op == nir_texop_texture_samples) {
4445 LLVMValueRef res, samples, is_msaa;
4446 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4447 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4448 LLVMConstInt(ctx->ac.i32, 3, false), "");
4449 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4450 LLVMConstInt(ctx->ac.i32, 28, false), "");
4451 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4452 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4453 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4454 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4455
4456 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4457 LLVMConstInt(ctx->ac.i32, 16, false), "");
4458 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4459 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4460 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4461 samples, "");
4462 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4463 ctx->ac.i32_1, "");
4464 result = samples;
4465 goto write_result;
4466 }
4467
4468 if (coord)
4469 for (chan = 0; chan < instr->coord_components; chan++)
4470 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4471
4472 if (offsets && instr->op != nir_texop_txf) {
4473 LLVMValueRef offset[3], pack;
4474 for (chan = 0; chan < 3; ++chan)
4475 offset[chan] = ctx->ac.i32_0;
4476
4477 args.offset = true;
4478 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4479 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4480 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4481 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4482 if (chan)
4483 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4484 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4485 }
4486 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4487 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4488 address[count++] = pack;
4489
4490 }
4491 /* pack LOD bias value */
4492 if (instr->op == nir_texop_txb && bias) {
4493 address[count++] = bias;
4494 }
4495
4496 /* Pack depth comparison value */
4497 if (instr->is_shadow && comparator) {
4498 LLVMValueRef z = ac_to_float(&ctx->ac,
4499 llvm_extract_elem(&ctx->ac, comparator, 0));
4500
4501 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4502 * so the depth comparison value isn't clamped for Z16 and
4503 * Z24 anymore. Do it manually here.
4504 *
4505 * It's unnecessary if the original texture format was
4506 * Z32_FLOAT, but we don't know that here.
4507 */
4508 if (ctx->ac.chip_class == VI)
4509 z = ac_build_clamp(&ctx->ac, z);
4510
4511 address[count++] = z;
4512 }
4513
4514 /* pack derivatives */
4515 if (ddx || ddy) {
4516 int num_src_deriv_channels, num_dest_deriv_channels;
4517 switch (instr->sampler_dim) {
4518 case GLSL_SAMPLER_DIM_3D:
4519 case GLSL_SAMPLER_DIM_CUBE:
4520 num_deriv_comp = 3;
4521 num_src_deriv_channels = 3;
4522 num_dest_deriv_channels = 3;
4523 break;
4524 case GLSL_SAMPLER_DIM_2D:
4525 default:
4526 num_src_deriv_channels = 2;
4527 num_dest_deriv_channels = 2;
4528 num_deriv_comp = 2;
4529 break;
4530 case GLSL_SAMPLER_DIM_1D:
4531 num_src_deriv_channels = 1;
4532 if (ctx->ac.chip_class >= GFX9) {
4533 num_dest_deriv_channels = 2;
4534 num_deriv_comp = 2;
4535 } else {
4536 num_dest_deriv_channels = 1;
4537 num_deriv_comp = 1;
4538 }
4539 break;
4540 }
4541
4542 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4543 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4544 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4545 }
4546 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4547 derivs[i] = ctx->ac.f32_0;
4548 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4549 }
4550 }
4551
4552 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4553 for (chan = 0; chan < instr->coord_components; chan++)
4554 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4555 if (instr->coord_components == 3)
4556 coords[3] = LLVMGetUndef(ctx->ac.f32);
4557 ac_prepare_cube_coords(&ctx->ac,
4558 instr->op == nir_texop_txd, instr->is_array,
4559 instr->op == nir_texop_lod, coords, derivs);
4560 if (num_deriv_comp)
4561 num_deriv_comp--;
4562 }
4563
4564 if (ddx || ddy) {
4565 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4566 address[count++] = derivs[i];
4567 }
4568
4569 /* Pack texture coordinates */
4570 if (coord) {
4571 address[count++] = coords[0];
4572 if (instr->coord_components > 1) {
4573 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4574 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4575 }
4576 address[count++] = coords[1];
4577 }
4578 if (instr->coord_components > 2) {
4579 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4580 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4581 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4582 instr->op != nir_texop_txf) {
4583 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4584 }
4585 address[count++] = coords[2];
4586 }
4587
4588 if (ctx->ac.chip_class >= GFX9) {
4589 LLVMValueRef filler;
4590 if (instr->op == nir_texop_txf)
4591 filler = ctx->ac.i32_0;
4592 else
4593 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4594
4595 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4596 if (instr->is_array) {
4597 address[count] = address[count - 1];
4598 address[count - 1] = filler;
4599 count++;
4600 } else
4601 address[count++] = filler;
4602 }
4603 }
4604 }
4605
4606 /* Pack LOD */
4607 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4608 instr->op == nir_texop_txf)) {
4609 address[count++] = lod;
4610 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4611 address[count++] = sample_index;
4612 } else if(instr->op == nir_texop_txs) {
4613 count = 0;
4614 if (lod)
4615 address[count++] = lod;
4616 else
4617 address[count++] = ctx->ac.i32_0;
4618 }
4619
4620 for (chan = 0; chan < count; chan++) {
4621 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4622 address[chan], ctx->ac.i32, "");
4623 }
4624
4625 if (instr->op == nir_texop_samples_identical) {
4626 LLVMValueRef txf_address[4];
4627 struct ac_image_args txf_args = { 0 };
4628 unsigned txf_count = count;
4629 memcpy(txf_address, address, sizeof(txf_address));
4630
4631 if (!instr->is_array)
4632 txf_address[2] = ctx->ac.i32_0;
4633 txf_address[3] = ctx->ac.i32_0;
4634
4635 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4636 fmask_ptr, NULL,
4637 txf_address, txf_count, 0xf);
4638
4639 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4640
4641 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4642 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4643 goto write_result;
4644 }
4645
4646 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4647 instr->op != nir_texop_txs) {
4648 unsigned sample_chan = instr->is_array ? 3 : 2;
4649 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4650 address[0],
4651 address[1],
4652 instr->is_array ? address[2] : NULL,
4653 address[sample_chan],
4654 fmask_ptr);
4655 }
4656
4657 if (offsets && instr->op == nir_texop_txf) {
4658 nir_const_value *const_offset =
4659 nir_src_as_const_value(instr->src[const_src].src);
4660 int num_offsets = instr->src[const_src].src.ssa->num_components;
4661 assert(const_offset);
4662 num_offsets = MIN2(num_offsets, instr->coord_components);
4663 if (num_offsets > 2)
4664 address[2] = LLVMBuildAdd(ctx->ac.builder,
4665 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4666 if (num_offsets > 1)
4667 address[1] = LLVMBuildAdd(ctx->ac.builder,
4668 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4669 address[0] = LLVMBuildAdd(ctx->ac.builder,
4670 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4671
4672 }
4673
4674 /* TODO TG4 support */
4675 if (instr->op == nir_texop_tg4) {
4676 if (instr->is_shadow)
4677 dmask = 1;
4678 else
4679 dmask = 1 << instr->component;
4680 }
4681 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4682 res_ptr, samp_ptr, address, count, dmask);
4683
4684 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4685
4686 if (instr->op == nir_texop_query_levels)
4687 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4688 else if (instr->is_shadow && instr->is_new_style_shadow &&
4689 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4690 instr->op != nir_texop_tg4)
4691 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4692 else if (instr->op == nir_texop_txs &&
4693 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4694 instr->is_array) {
4695 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4696 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4697 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4698 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4699 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4700 } else if (ctx->ac.chip_class >= GFX9 &&
4701 instr->op == nir_texop_txs &&
4702 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4703 instr->is_array) {
4704 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4705 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4706 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4707 ctx->ac.i32_1, "");
4708 } else if (instr->dest.ssa.num_components != 4)
4709 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4710
4711 write_result:
4712 if (result) {
4713 assert(instr->dest.is_ssa);
4714 result = ac_to_integer(&ctx->ac, result);
4715 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4716 }
4717 }
4718
4719
4720 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4721 {
4722 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4723 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4724
4725 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4726 _mesa_hash_table_insert(ctx->phis, instr, result);
4727 }
4728
4729 static void visit_post_phi(struct ac_nir_context *ctx,
4730 nir_phi_instr *instr,
4731 LLVMValueRef llvm_phi)
4732 {
4733 nir_foreach_phi_src(src, instr) {
4734 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4735 LLVMValueRef llvm_src = get_src(ctx, src->src);
4736
4737 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4738 }
4739 }
4740
4741 static void phi_post_pass(struct ac_nir_context *ctx)
4742 {
4743 struct hash_entry *entry;
4744 hash_table_foreach(ctx->phis, entry) {
4745 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4746 (LLVMValueRef)entry->data);
4747 }
4748 }
4749
4750
4751 static void visit_ssa_undef(struct ac_nir_context *ctx,
4752 const nir_ssa_undef_instr *instr)
4753 {
4754 unsigned num_components = instr->def.num_components;
4755 LLVMValueRef undef;
4756
4757 if (num_components == 1)
4758 undef = LLVMGetUndef(ctx->ac.i32);
4759 else {
4760 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4761 }
4762 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4763 }
4764
4765 static void visit_jump(struct ac_nir_context *ctx,
4766 const nir_jump_instr *instr)
4767 {
4768 switch (instr->type) {
4769 case nir_jump_break:
4770 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4771 LLVMClearInsertionPosition(ctx->ac.builder);
4772 break;
4773 case nir_jump_continue:
4774 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4775 LLVMClearInsertionPosition(ctx->ac.builder);
4776 break;
4777 default:
4778 fprintf(stderr, "Unknown NIR jump instr: ");
4779 nir_print_instr(&instr->instr, stderr);
4780 fprintf(stderr, "\n");
4781 abort();
4782 }
4783 }
4784
4785 static void visit_cf_list(struct ac_nir_context *ctx,
4786 struct exec_list *list);
4787
4788 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4789 {
4790 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4791 nir_foreach_instr(instr, block)
4792 {
4793 switch (instr->type) {
4794 case nir_instr_type_alu:
4795 visit_alu(ctx, nir_instr_as_alu(instr));
4796 break;
4797 case nir_instr_type_load_const:
4798 visit_load_const(ctx, nir_instr_as_load_const(instr));
4799 break;
4800 case nir_instr_type_intrinsic:
4801 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4802 break;
4803 case nir_instr_type_tex:
4804 visit_tex(ctx, nir_instr_as_tex(instr));
4805 break;
4806 case nir_instr_type_phi:
4807 visit_phi(ctx, nir_instr_as_phi(instr));
4808 break;
4809 case nir_instr_type_ssa_undef:
4810 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4811 break;
4812 case nir_instr_type_jump:
4813 visit_jump(ctx, nir_instr_as_jump(instr));
4814 break;
4815 default:
4816 fprintf(stderr, "Unknown NIR instr type: ");
4817 nir_print_instr(instr, stderr);
4818 fprintf(stderr, "\n");
4819 abort();
4820 }
4821 }
4822
4823 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4824 }
4825
4826 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4827 {
4828 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4829
4830 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4831 LLVMBasicBlockRef merge_block =
4832 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4833 LLVMBasicBlockRef if_block =
4834 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4835 LLVMBasicBlockRef else_block = merge_block;
4836 if (!exec_list_is_empty(&if_stmt->else_list))
4837 else_block = LLVMAppendBasicBlockInContext(
4838 ctx->ac.context, fn, "");
4839
4840 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4841 LLVMConstInt(ctx->ac.i32, 0, false), "");
4842 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4843
4844 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4845 visit_cf_list(ctx, &if_stmt->then_list);
4846 if (LLVMGetInsertBlock(ctx->ac.builder))
4847 LLVMBuildBr(ctx->ac.builder, merge_block);
4848
4849 if (!exec_list_is_empty(&if_stmt->else_list)) {
4850 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4851 visit_cf_list(ctx, &if_stmt->else_list);
4852 if (LLVMGetInsertBlock(ctx->ac.builder))
4853 LLVMBuildBr(ctx->ac.builder, merge_block);
4854 }
4855
4856 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4857 }
4858
4859 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4860 {
4861 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4862 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4863 LLVMBasicBlockRef break_parent = ctx->break_block;
4864
4865 ctx->continue_block =
4866 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4867 ctx->break_block =
4868 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4869
4870 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4871 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4872 visit_cf_list(ctx, &loop->body);
4873
4874 if (LLVMGetInsertBlock(ctx->ac.builder))
4875 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4876 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4877
4878 ctx->continue_block = continue_parent;
4879 ctx->break_block = break_parent;
4880 }
4881
4882 static void visit_cf_list(struct ac_nir_context *ctx,
4883 struct exec_list *list)
4884 {
4885 foreach_list_typed(nir_cf_node, node, node, list)
4886 {
4887 switch (node->type) {
4888 case nir_cf_node_block:
4889 visit_block(ctx, nir_cf_node_as_block(node));
4890 break;
4891
4892 case nir_cf_node_if:
4893 visit_if(ctx, nir_cf_node_as_if(node));
4894 break;
4895
4896 case nir_cf_node_loop:
4897 visit_loop(ctx, nir_cf_node_as_loop(node));
4898 break;
4899
4900 default:
4901 assert(0);
4902 }
4903 }
4904 }
4905
4906 static void
4907 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4908 struct nir_variable *variable)
4909 {
4910 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4911 LLVMValueRef t_offset;
4912 LLVMValueRef t_list;
4913 LLVMValueRef input;
4914 LLVMValueRef buffer_index;
4915 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4916 int idx = variable->data.location;
4917 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4918
4919 variable->data.driver_location = idx * 4;
4920
4921 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4922 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4923 ctx->abi.start_instance, "");
4924 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4925 ctx->shader_info->vs.vgpr_comp_cnt);
4926 } else
4927 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4928 ctx->abi.base_vertex, "");
4929
4930 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4931 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4932
4933 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
4934
4935 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4936 buffer_index,
4937 LLVMConstInt(ctx->i32, 0, false),
4938 true);
4939
4940 for (unsigned chan = 0; chan < 4; chan++) {
4941 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4942 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4943 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4944 input, llvm_chan, ""));
4945 }
4946 }
4947 }
4948
4949 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4950 unsigned attr,
4951 LLVMValueRef interp_param,
4952 LLVMValueRef prim_mask,
4953 LLVMValueRef result[4])
4954 {
4955 LLVMValueRef attr_number;
4956 unsigned chan;
4957 LLVMValueRef i, j;
4958 bool interp = interp_param != NULL;
4959
4960 attr_number = LLVMConstInt(ctx->i32, attr, false);
4961
4962 /* fs.constant returns the param from the middle vertex, so it's not
4963 * really useful for flat shading. It's meant to be used for custom
4964 * interpolation (but the intrinsic can't fetch from the other two
4965 * vertices).
4966 *
4967 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4968 * to do the right thing. The only reason we use fs.constant is that
4969 * fs.interp cannot be used on integers, because they can be equal
4970 * to NaN.
4971 */
4972 if (interp) {
4973 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4974 LLVMVectorType(ctx->f32, 2), "");
4975
4976 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4977 ctx->i32zero, "");
4978 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4979 ctx->i32one, "");
4980 }
4981
4982 for (chan = 0; chan < 4; chan++) {
4983 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4984
4985 if (interp) {
4986 result[chan] = ac_build_fs_interp(&ctx->ac,
4987 llvm_chan,
4988 attr_number,
4989 prim_mask, i, j);
4990 } else {
4991 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4992 LLVMConstInt(ctx->i32, 2, false),
4993 llvm_chan,
4994 attr_number,
4995 prim_mask);
4996 }
4997 }
4998 }
4999
5000 static void
5001 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5002 struct nir_variable *variable)
5003 {
5004 int idx = variable->data.location;
5005 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5006 LLVMValueRef interp;
5007
5008 variable->data.driver_location = idx * 4;
5009 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5010
5011 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5012 unsigned interp_type;
5013 if (variable->data.sample) {
5014 interp_type = INTERP_SAMPLE;
5015 ctx->shader_info->info.ps.force_persample = true;
5016 } else if (variable->data.centroid)
5017 interp_type = INTERP_CENTROID;
5018 else
5019 interp_type = INTERP_CENTER;
5020
5021 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5022 } else
5023 interp = NULL;
5024
5025 for (unsigned i = 0; i < attrib_count; ++i)
5026 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5027
5028 }
5029
5030 static void
5031 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5032 struct nir_shader *nir) {
5033 nir_foreach_variable(variable, &nir->inputs)
5034 handle_vs_input_decl(ctx, variable);
5035 }
5036
5037 static void
5038 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5039 struct nir_shader *nir)
5040 {
5041 if (!ctx->options->key.fs.multisample)
5042 return;
5043
5044 bool uses_center = false;
5045 bool uses_centroid = false;
5046 nir_foreach_variable(variable, &nir->inputs) {
5047 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5048 variable->data.sample)
5049 continue;
5050
5051 if (variable->data.centroid)
5052 uses_centroid = true;
5053 else
5054 uses_center = true;
5055 }
5056
5057 if (uses_center && uses_centroid) {
5058 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5059 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5060 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5061 }
5062 }
5063
5064 static void
5065 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5066 struct nir_shader *nir)
5067 {
5068 prepare_interp_optimize(ctx, nir);
5069
5070 nir_foreach_variable(variable, &nir->inputs)
5071 handle_fs_input_decl(ctx, variable);
5072
5073 unsigned index = 0;
5074
5075 if (ctx->shader_info->info.ps.uses_input_attachments ||
5076 ctx->shader_info->info.needs_multiview_view_index)
5077 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5078
5079 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5080 LLVMValueRef interp_param;
5081 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5082
5083 if (!(ctx->input_mask & (1ull << i)))
5084 continue;
5085
5086 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5087 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5088 interp_param = *inputs;
5089 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5090 inputs);
5091
5092 if (!interp_param)
5093 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5094 ++index;
5095 } else if (i == VARYING_SLOT_POS) {
5096 for(int i = 0; i < 3; ++i)
5097 inputs[i] = ctx->abi.frag_pos[i];
5098
5099 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5100 ctx->abi.frag_pos[3]);
5101 }
5102 }
5103 ctx->shader_info->fs.num_interp = index;
5104 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5105 ctx->shader_info->fs.has_pcoord = true;
5106 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5107 ctx->shader_info->fs.prim_id_input = true;
5108 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5109 ctx->shader_info->fs.layer_input = true;
5110 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5111
5112 if (ctx->shader_info->info.needs_multiview_view_index)
5113 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5114 }
5115
5116 static LLVMValueRef
5117 ac_build_alloca(struct ac_llvm_context *ac,
5118 LLVMTypeRef type,
5119 const char *name)
5120 {
5121 LLVMBuilderRef builder = ac->builder;
5122 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5123 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5124 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5125 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5126 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5127 LLVMValueRef res;
5128
5129 if (first_instr) {
5130 LLVMPositionBuilderBefore(first_builder, first_instr);
5131 } else {
5132 LLVMPositionBuilderAtEnd(first_builder, first_block);
5133 }
5134
5135 res = LLVMBuildAlloca(first_builder, type, name);
5136 LLVMBuildStore(builder, LLVMConstNull(type), res);
5137
5138 LLVMDisposeBuilder(first_builder);
5139
5140 return res;
5141 }
5142
5143 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5144 LLVMTypeRef type,
5145 const char *name)
5146 {
5147 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5148 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5149 return ptr;
5150 }
5151
5152 static void
5153 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5154 struct nir_variable *variable)
5155 {
5156 int idx = variable->data.location + variable->data.index;
5157 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5158 uint64_t mask_attribs;
5159
5160 variable->data.driver_location = idx * 4;
5161
5162 /* tess ctrl has it's own load/store paths for outputs */
5163 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5164 return;
5165
5166 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5167 if (ctx->stage == MESA_SHADER_VERTEX ||
5168 ctx->stage == MESA_SHADER_TESS_EVAL ||
5169 ctx->stage == MESA_SHADER_GEOMETRY) {
5170 if (idx == VARYING_SLOT_CLIP_DIST0) {
5171 int length = ctx->num_output_clips + ctx->num_output_culls;
5172 if (ctx->stage == MESA_SHADER_VERTEX) {
5173 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5174 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5175 }
5176 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5177 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5178 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5179 }
5180
5181 if (length > 4)
5182 attrib_count = 2;
5183 else
5184 attrib_count = 1;
5185 mask_attribs = 1ull << idx;
5186 }
5187 }
5188
5189 ctx->output_mask |= mask_attribs;
5190 }
5191
5192 static void
5193 handle_shader_output_decl(struct ac_nir_context *ctx,
5194 struct nir_shader *nir,
5195 struct nir_variable *variable)
5196 {
5197 unsigned output_loc = variable->data.driver_location / 4;
5198 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5199
5200 /* tess ctrl has it's own load/store paths for outputs */
5201 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5202 return;
5203
5204 if (ctx->stage == MESA_SHADER_VERTEX ||
5205 ctx->stage == MESA_SHADER_TESS_EVAL ||
5206 ctx->stage == MESA_SHADER_GEOMETRY) {
5207 int idx = variable->data.location + variable->data.index;
5208 if (idx == VARYING_SLOT_CLIP_DIST0) {
5209 int length = nir->info.clip_distance_array_size +
5210 nir->info.cull_distance_array_size;
5211
5212 if (length > 4)
5213 attrib_count = 2;
5214 else
5215 attrib_count = 1;
5216 }
5217 }
5218
5219 for (unsigned i = 0; i < attrib_count; ++i) {
5220 for (unsigned chan = 0; chan < 4; chan++) {
5221 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5222 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5223 }
5224 }
5225 }
5226
5227 static LLVMTypeRef
5228 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5229 enum glsl_base_type type)
5230 {
5231 switch (type) {
5232 case GLSL_TYPE_INT:
5233 case GLSL_TYPE_UINT:
5234 case GLSL_TYPE_BOOL:
5235 case GLSL_TYPE_SUBROUTINE:
5236 return ctx->i32;
5237 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5238 return ctx->f32;
5239 case GLSL_TYPE_INT64:
5240 case GLSL_TYPE_UINT64:
5241 return ctx->i64;
5242 case GLSL_TYPE_DOUBLE:
5243 return ctx->f64;
5244 default:
5245 unreachable("unknown GLSL type");
5246 }
5247 }
5248
5249 static LLVMTypeRef
5250 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5251 const struct glsl_type *type)
5252 {
5253 if (glsl_type_is_scalar(type)) {
5254 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5255 }
5256
5257 if (glsl_type_is_vector(type)) {
5258 return LLVMVectorType(
5259 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5260 glsl_get_vector_elements(type));
5261 }
5262
5263 if (glsl_type_is_matrix(type)) {
5264 return LLVMArrayType(
5265 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5266 glsl_get_matrix_columns(type));
5267 }
5268
5269 if (glsl_type_is_array(type)) {
5270 return LLVMArrayType(
5271 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5272 glsl_get_length(type));
5273 }
5274
5275 assert(glsl_type_is_struct(type));
5276
5277 LLVMTypeRef member_types[glsl_get_length(type)];
5278
5279 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5280 member_types[i] =
5281 glsl_to_llvm_type(ctx,
5282 glsl_get_struct_field(type, i));
5283 }
5284
5285 return LLVMStructTypeInContext(ctx->context, member_types,
5286 glsl_get_length(type), false);
5287 }
5288
5289 static void
5290 setup_locals(struct ac_nir_context *ctx,
5291 struct nir_function *func)
5292 {
5293 int i, j;
5294 ctx->num_locals = 0;
5295 nir_foreach_variable(variable, &func->impl->locals) {
5296 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5297 variable->data.driver_location = ctx->num_locals * 4;
5298 ctx->num_locals += attrib_count;
5299 }
5300 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5301 if (!ctx->locals)
5302 return;
5303
5304 for (i = 0; i < ctx->num_locals; i++) {
5305 for (j = 0; j < 4; j++) {
5306 ctx->locals[i * 4 + j] =
5307 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5308 }
5309 }
5310 }
5311
5312 static void
5313 setup_shared(struct ac_nir_context *ctx,
5314 struct nir_shader *nir)
5315 {
5316 nir_foreach_variable(variable, &nir->shared) {
5317 LLVMValueRef shared =
5318 LLVMAddGlobalInAddressSpace(
5319 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5320 variable->name ? variable->name : "",
5321 LOCAL_ADDR_SPACE);
5322 _mesa_hash_table_insert(ctx->vars, variable, shared);
5323 }
5324 }
5325
5326 static LLVMValueRef
5327 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5328 {
5329 v = ac_to_float(ctx, v);
5330 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5331 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5332 }
5333
5334
5335 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5336 LLVMValueRef src0, LLVMValueRef src1)
5337 {
5338 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5339 LLVMValueRef comp[2];
5340
5341 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5342 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5343 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5344 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5345 }
5346
5347 /* Initialize arguments for the shader export intrinsic */
5348 static void
5349 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5350 LLVMValueRef *values,
5351 unsigned target,
5352 struct ac_export_args *args)
5353 {
5354 /* Default is 0xf. Adjusted below depending on the format. */
5355 args->enabled_channels = 0xf;
5356
5357 /* Specify whether the EXEC mask represents the valid mask */
5358 args->valid_mask = 0;
5359
5360 /* Specify whether this is the last export */
5361 args->done = 0;
5362
5363 /* Specify the target we are exporting */
5364 args->target = target;
5365
5366 args->compr = false;
5367 args->out[0] = LLVMGetUndef(ctx->f32);
5368 args->out[1] = LLVMGetUndef(ctx->f32);
5369 args->out[2] = LLVMGetUndef(ctx->f32);
5370 args->out[3] = LLVMGetUndef(ctx->f32);
5371
5372 if (!values)
5373 return;
5374
5375 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5376 LLVMValueRef val[4];
5377 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5378 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5379 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5380 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5381
5382 switch(col_format) {
5383 case V_028714_SPI_SHADER_ZERO:
5384 args->enabled_channels = 0; /* writemask */
5385 args->target = V_008DFC_SQ_EXP_NULL;
5386 break;
5387
5388 case V_028714_SPI_SHADER_32_R:
5389 args->enabled_channels = 1;
5390 args->out[0] = values[0];
5391 break;
5392
5393 case V_028714_SPI_SHADER_32_GR:
5394 args->enabled_channels = 0x3;
5395 args->out[0] = values[0];
5396 args->out[1] = values[1];
5397 break;
5398
5399 case V_028714_SPI_SHADER_32_AR:
5400 args->enabled_channels = 0x9;
5401 args->out[0] = values[0];
5402 args->out[3] = values[3];
5403 break;
5404
5405 case V_028714_SPI_SHADER_FP16_ABGR:
5406 args->compr = 1;
5407
5408 for (unsigned chan = 0; chan < 2; chan++) {
5409 LLVMValueRef pack_args[2] = {
5410 values[2 * chan],
5411 values[2 * chan + 1]
5412 };
5413 LLVMValueRef packed;
5414
5415 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5416 args->out[chan] = packed;
5417 }
5418 break;
5419
5420 case V_028714_SPI_SHADER_UNORM16_ABGR:
5421 for (unsigned chan = 0; chan < 4; chan++) {
5422 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5423 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5424 LLVMConstReal(ctx->f32, 65535), "");
5425 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5426 LLVMConstReal(ctx->f32, 0.5), "");
5427 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5428 ctx->i32, "");
5429 }
5430
5431 args->compr = 1;
5432 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5433 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5434 break;
5435
5436 case V_028714_SPI_SHADER_SNORM16_ABGR:
5437 for (unsigned chan = 0; chan < 4; chan++) {
5438 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5439 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5440 LLVMConstReal(ctx->f32, 32767), "");
5441
5442 /* If positive, add 0.5, else add -0.5. */
5443 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5444 LLVMBuildSelect(ctx->builder,
5445 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5446 val[chan], ctx->f32zero, ""),
5447 LLVMConstReal(ctx->f32, 0.5),
5448 LLVMConstReal(ctx->f32, -0.5), ""), "");
5449 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5450 }
5451
5452 args->compr = 1;
5453 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5454 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5455 break;
5456
5457 case V_028714_SPI_SHADER_UINT16_ABGR: {
5458 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5459 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5460 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5461
5462 for (unsigned chan = 0; chan < 4; chan++) {
5463 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5464 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5465 }
5466
5467 args->compr = 1;
5468 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5469 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5470 break;
5471 }
5472
5473 case V_028714_SPI_SHADER_SINT16_ABGR: {
5474 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5475 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5476 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5477 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5478 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5479 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5480
5481 /* Clamp. */
5482 for (unsigned chan = 0; chan < 4; chan++) {
5483 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5484 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5485 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5486 }
5487
5488 args->compr = 1;
5489 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5490 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5491 break;
5492 }
5493
5494 default:
5495 case V_028714_SPI_SHADER_32_ABGR:
5496 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5497 break;
5498 }
5499 } else
5500 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5501
5502 for (unsigned i = 0; i < 4; ++i)
5503 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5504 }
5505
5506 static void
5507 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5508 bool export_prim_id,
5509 struct ac_vs_output_info *outinfo)
5510 {
5511 uint32_t param_count = 0;
5512 unsigned target;
5513 unsigned pos_idx, num_pos_exports = 0;
5514 struct ac_export_args args, pos_args[4] = {};
5515 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5516 int i;
5517
5518 if (ctx->options->key.has_multiview_view_index) {
5519 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5520 if(!*tmp_out) {
5521 for(unsigned i = 0; i < 4; ++i)
5522 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5523 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5524 }
5525
5526 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5527 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5528 }
5529
5530 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5531 sizeof(outinfo->vs_output_param_offset));
5532
5533 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5534 LLVMValueRef slots[8];
5535 unsigned j;
5536
5537 if (outinfo->cull_dist_mask)
5538 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5539
5540 i = VARYING_SLOT_CLIP_DIST0;
5541 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5542 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5543 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5544
5545 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5546 slots[i] = LLVMGetUndef(ctx->f32);
5547
5548 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5549 target = V_008DFC_SQ_EXP_POS + 3;
5550 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5551 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5552 &args, sizeof(args));
5553 }
5554
5555 target = V_008DFC_SQ_EXP_POS + 2;
5556 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5557 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5558 &args, sizeof(args));
5559
5560 }
5561
5562 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5563 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5564 for (unsigned j = 0; j < 4; j++)
5565 pos_values[j] = LLVMBuildLoad(ctx->builder,
5566 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5567 }
5568 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5569
5570 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5571 outinfo->writes_pointsize = true;
5572 psize_value = LLVMBuildLoad(ctx->builder,
5573 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5574 }
5575
5576 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5577 outinfo->writes_layer = true;
5578 layer_value = LLVMBuildLoad(ctx->builder,
5579 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5580 }
5581
5582 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5583 outinfo->writes_viewport_index = true;
5584 viewport_index_value = LLVMBuildLoad(ctx->builder,
5585 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5586 }
5587
5588 if (outinfo->writes_pointsize ||
5589 outinfo->writes_layer ||
5590 outinfo->writes_viewport_index) {
5591 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5592 (outinfo->writes_layer == true ? 4 : 0));
5593 pos_args[1].valid_mask = 0;
5594 pos_args[1].done = 0;
5595 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5596 pos_args[1].compr = 0;
5597 pos_args[1].out[0] = ctx->f32zero; /* X */
5598 pos_args[1].out[1] = ctx->f32zero; /* Y */
5599 pos_args[1].out[2] = ctx->f32zero; /* Z */
5600 pos_args[1].out[3] = ctx->f32zero; /* W */
5601
5602 if (outinfo->writes_pointsize == true)
5603 pos_args[1].out[0] = psize_value;
5604 if (outinfo->writes_layer == true)
5605 pos_args[1].out[2] = layer_value;
5606 if (outinfo->writes_viewport_index == true) {
5607 if (ctx->options->chip_class >= GFX9) {
5608 /* GFX9 has the layer in out.z[10:0] and the viewport
5609 * index in out.z[19:16].
5610 */
5611 LLVMValueRef v = viewport_index_value;
5612 v = ac_to_integer(&ctx->ac, v);
5613 v = LLVMBuildShl(ctx->builder, v,
5614 LLVMConstInt(ctx->i32, 16, false),
5615 "");
5616 v = LLVMBuildOr(ctx->builder, v,
5617 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5618
5619 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5620 pos_args[1].enabled_channels |= 1 << 2;
5621 } else {
5622 pos_args[1].out[3] = viewport_index_value;
5623 pos_args[1].enabled_channels |= 1 << 3;
5624 }
5625 }
5626 }
5627 for (i = 0; i < 4; i++) {
5628 if (pos_args[i].out[0])
5629 num_pos_exports++;
5630 }
5631
5632 pos_idx = 0;
5633 for (i = 0; i < 4; i++) {
5634 if (!pos_args[i].out[0])
5635 continue;
5636
5637 /* Specify the target we are exporting */
5638 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5639 if (pos_idx == num_pos_exports)
5640 pos_args[i].done = 1;
5641 ac_build_export(&ctx->ac, &pos_args[i]);
5642 }
5643
5644 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5645 LLVMValueRef values[4];
5646 if (!(ctx->output_mask & (1ull << i)))
5647 continue;
5648
5649 for (unsigned j = 0; j < 4; j++)
5650 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5651 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5652
5653 if (i == VARYING_SLOT_LAYER) {
5654 target = V_008DFC_SQ_EXP_PARAM + param_count;
5655 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5656 param_count++;
5657 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5658 target = V_008DFC_SQ_EXP_PARAM + param_count;
5659 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5660 param_count++;
5661 } else if (i >= VARYING_SLOT_VAR0) {
5662 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5663 target = V_008DFC_SQ_EXP_PARAM + param_count;
5664 outinfo->vs_output_param_offset[i] = param_count;
5665 param_count++;
5666 } else
5667 continue;
5668
5669 si_llvm_init_export_args(ctx, values, target, &args);
5670
5671 if (target >= V_008DFC_SQ_EXP_POS &&
5672 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5673 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5674 &args, sizeof(args));
5675 } else {
5676 ac_build_export(&ctx->ac, &args);
5677 }
5678 }
5679
5680 if (export_prim_id) {
5681 LLVMValueRef values[4];
5682 target = V_008DFC_SQ_EXP_PARAM + param_count;
5683 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5684 param_count++;
5685
5686 values[0] = ctx->vs_prim_id;
5687 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5688 ctx->shader_info->vs.vgpr_comp_cnt);
5689 for (unsigned j = 1; j < 4; j++)
5690 values[j] = ctx->f32zero;
5691 si_llvm_init_export_args(ctx, values, target, &args);
5692 ac_build_export(&ctx->ac, &args);
5693 outinfo->export_prim_id = true;
5694 }
5695
5696 outinfo->pos_exports = num_pos_exports;
5697 outinfo->param_exports = param_count;
5698 }
5699
5700 static void
5701 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5702 struct ac_es_output_info *outinfo)
5703 {
5704 int j;
5705 uint64_t max_output_written = 0;
5706 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5707 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5708 int param_index;
5709 int length = 4;
5710
5711 if (!(ctx->output_mask & (1ull << i)))
5712 continue;
5713
5714 if (i == VARYING_SLOT_CLIP_DIST0)
5715 length = ctx->num_output_clips + ctx->num_output_culls;
5716
5717 param_index = shader_io_get_unique_index(i);
5718
5719 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5720
5721 for (j = 0; j < length; j++) {
5722 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5723 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5724
5725 ac_build_buffer_store_dword(&ctx->ac,
5726 ctx->esgs_ring,
5727 out_val, 1,
5728 NULL, ctx->es2gs_offset,
5729 (4 * param_index + j) * 4,
5730 1, 1, true, true);
5731 }
5732 }
5733 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5734 }
5735
5736 static void
5737 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5738 {
5739 LLVMValueRef vertex_id = ctx->rel_auto_id;
5740 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5741 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5742 vertex_dw_stride, "");
5743
5744 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5745 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5746 int length = 4;
5747
5748 if (!(ctx->output_mask & (1ull << i)))
5749 continue;
5750
5751 if (i == VARYING_SLOT_CLIP_DIST0)
5752 length = ctx->num_output_clips + ctx->num_output_culls;
5753 int param = shader_io_get_unique_index(i);
5754 mark_tess_output(ctx, false, param);
5755 if (length > 4)
5756 mark_tess_output(ctx, false, param + 1);
5757 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5758 LLVMConstInt(ctx->i32, param * 4, false),
5759 "");
5760 for (unsigned j = 0; j < length; j++) {
5761 lds_store(ctx, dw_addr,
5762 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5763 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5764 }
5765 }
5766 }
5767
5768 struct ac_build_if_state
5769 {
5770 struct nir_to_llvm_context *ctx;
5771 LLVMValueRef condition;
5772 LLVMBasicBlockRef entry_block;
5773 LLVMBasicBlockRef true_block;
5774 LLVMBasicBlockRef false_block;
5775 LLVMBasicBlockRef merge_block;
5776 };
5777
5778 static LLVMBasicBlockRef
5779 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5780 {
5781 LLVMBasicBlockRef current_block;
5782 LLVMBasicBlockRef next_block;
5783 LLVMBasicBlockRef new_block;
5784
5785 /* get current basic block */
5786 current_block = LLVMGetInsertBlock(ctx->builder);
5787
5788 /* chqeck if there's another block after this one */
5789 next_block = LLVMGetNextBasicBlock(current_block);
5790 if (next_block) {
5791 /* insert the new block before the next block */
5792 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5793 }
5794 else {
5795 /* append new block after current block */
5796 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5797 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5798 }
5799 return new_block;
5800 }
5801
5802 static void
5803 ac_nir_build_if(struct ac_build_if_state *ifthen,
5804 struct nir_to_llvm_context *ctx,
5805 LLVMValueRef condition)
5806 {
5807 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5808
5809 memset(ifthen, 0, sizeof *ifthen);
5810 ifthen->ctx = ctx;
5811 ifthen->condition = condition;
5812 ifthen->entry_block = block;
5813
5814 /* create endif/merge basic block for the phi functions */
5815 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5816
5817 /* create/insert true_block before merge_block */
5818 ifthen->true_block =
5819 LLVMInsertBasicBlockInContext(ctx->context,
5820 ifthen->merge_block,
5821 "if-true-block");
5822
5823 /* successive code goes into the true block */
5824 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5825 }
5826
5827 /**
5828 * End a conditional.
5829 */
5830 static void
5831 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5832 {
5833 LLVMBuilderRef builder = ifthen->ctx->builder;
5834
5835 /* Insert branch to the merge block from current block */
5836 LLVMBuildBr(builder, ifthen->merge_block);
5837
5838 /*
5839 * Now patch in the various branch instructions.
5840 */
5841
5842 /* Insert the conditional branch instruction at the end of entry_block */
5843 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5844 if (ifthen->false_block) {
5845 /* we have an else clause */
5846 LLVMBuildCondBr(builder, ifthen->condition,
5847 ifthen->true_block, ifthen->false_block);
5848 }
5849 else {
5850 /* no else clause */
5851 LLVMBuildCondBr(builder, ifthen->condition,
5852 ifthen->true_block, ifthen->merge_block);
5853 }
5854
5855 /* Resume building code at end of the ifthen->merge_block */
5856 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5857 }
5858
5859 static void
5860 write_tess_factors(struct nir_to_llvm_context *ctx)
5861 {
5862 unsigned stride, outer_comps, inner_comps;
5863 struct ac_build_if_state if_ctx, inner_if_ctx;
5864 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5865 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5866 unsigned tess_inner_index, tess_outer_index;
5867 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5868 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5869 int i;
5870 emit_barrier(ctx);
5871
5872 switch (ctx->options->key.tcs.primitive_mode) {
5873 case GL_ISOLINES:
5874 stride = 2;
5875 outer_comps = 2;
5876 inner_comps = 0;
5877 break;
5878 case GL_TRIANGLES:
5879 stride = 4;
5880 outer_comps = 3;
5881 inner_comps = 1;
5882 break;
5883 case GL_QUADS:
5884 stride = 6;
5885 outer_comps = 4;
5886 inner_comps = 2;
5887 break;
5888 default:
5889 return;
5890 }
5891
5892 ac_nir_build_if(&if_ctx, ctx,
5893 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5894 invocation_id, ctx->i32zero, ""));
5895
5896 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5897 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5898
5899 mark_tess_output(ctx, true, tess_inner_index);
5900 mark_tess_output(ctx, true, tess_outer_index);
5901 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5902 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5903 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5904 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5905 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5906
5907 for (i = 0; i < 4; i++) {
5908 inner[i] = LLVMGetUndef(ctx->i32);
5909 outer[i] = LLVMGetUndef(ctx->i32);
5910 }
5911
5912 // LINES reverseal
5913 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5914 outer[0] = out[1] = lds_load(ctx, lds_outer);
5915 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5916 LLVMConstInt(ctx->i32, 1, false), "");
5917 outer[1] = out[0] = lds_load(ctx, lds_outer);
5918 } else {
5919 for (i = 0; i < outer_comps; i++) {
5920 outer[i] = out[i] =
5921 lds_load(ctx, lds_outer);
5922 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5923 LLVMConstInt(ctx->i32, 1, false), "");
5924 }
5925 for (i = 0; i < inner_comps; i++) {
5926 inner[i] = out[outer_comps+i] =
5927 lds_load(ctx, lds_inner);
5928 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5929 LLVMConstInt(ctx->i32, 1, false), "");
5930 }
5931 }
5932
5933 /* Convert the outputs to vectors for stores. */
5934 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5935 vec1 = NULL;
5936
5937 if (stride > 4)
5938 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5939
5940
5941 buffer = ctx->hs_ring_tess_factor;
5942 tf_base = ctx->tess_factor_offset;
5943 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5944 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5945
5946 ac_nir_build_if(&inner_if_ctx, ctx,
5947 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5948 rel_patch_id, ctx->i32zero, ""));
5949
5950 /* Store the dynamic HS control word. */
5951 ac_build_buffer_store_dword(&ctx->ac, buffer,
5952 LLVMConstInt(ctx->i32, 0x80000000, false),
5953 1, ctx->i32zero, tf_base,
5954 0, 1, 0, true, false);
5955 ac_nir_build_endif(&inner_if_ctx);
5956
5957 /* Store the tessellation factors. */
5958 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5959 MIN2(stride, 4), byteoffset, tf_base,
5960 4, 1, 0, true, false);
5961 if (vec1)
5962 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5963 stride - 4, byteoffset, tf_base,
5964 20, 1, 0, true, false);
5965
5966 //TODO store to offchip for TES to read - only if TES reads them
5967 if (1) {
5968 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5969 LLVMValueRef tf_inner_offset;
5970 unsigned param_outer, param_inner;
5971
5972 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5973 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5974 LLVMConstInt(ctx->i32, param_outer, 0));
5975
5976 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5977 util_next_power_of_two(outer_comps));
5978
5979 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5980 outer_comps, tf_outer_offset,
5981 ctx->oc_lds, 0, 1, 0, true, false);
5982 if (inner_comps) {
5983 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5984 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5985 LLVMConstInt(ctx->i32, param_inner, 0));
5986
5987 inner_vec = inner_comps == 1 ? inner[0] :
5988 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5989 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5990 inner_comps, tf_inner_offset,
5991 ctx->oc_lds, 0, 1, 0, true, false);
5992 }
5993 }
5994 ac_nir_build_endif(&if_ctx);
5995 }
5996
5997 static void
5998 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5999 {
6000 write_tess_factors(ctx);
6001 }
6002
6003 static bool
6004 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6005 LLVMValueRef *color, unsigned param, bool is_last,
6006 struct ac_export_args *args)
6007 {
6008 /* Export */
6009 si_llvm_init_export_args(ctx, color, param,
6010 args);
6011
6012 if (is_last) {
6013 args->valid_mask = 1; /* whether the EXEC mask is valid */
6014 args->done = 1; /* DONE bit */
6015 } else if (!args->enabled_channels)
6016 return false; /* unnecessary NULL export */
6017
6018 return true;
6019 }
6020
6021 static void
6022 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6023 LLVMValueRef depth, LLVMValueRef stencil,
6024 LLVMValueRef samplemask)
6025 {
6026 struct ac_export_args args;
6027
6028 args.enabled_channels = 0;
6029 args.valid_mask = 1;
6030 args.done = 1;
6031 args.target = V_008DFC_SQ_EXP_MRTZ;
6032 args.compr = false;
6033
6034 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6035 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6036 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6037 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6038
6039 if (depth) {
6040 args.out[0] = depth;
6041 args.enabled_channels |= 0x1;
6042 }
6043
6044 if (stencil) {
6045 args.out[1] = stencil;
6046 args.enabled_channels |= 0x2;
6047 }
6048
6049 if (samplemask) {
6050 args.out[2] = samplemask;
6051 args.enabled_channels |= 0x4;
6052 }
6053
6054 /* SI (except OLAND and HAINAN) has a bug that it only looks
6055 * at the X writemask component. */
6056 if (ctx->options->chip_class == SI &&
6057 ctx->options->family != CHIP_OLAND &&
6058 ctx->options->family != CHIP_HAINAN)
6059 args.enabled_channels |= 0x1;
6060
6061 ac_build_export(&ctx->ac, &args);
6062 }
6063
6064 static void
6065 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6066 {
6067 unsigned index = 0;
6068 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6069 struct ac_export_args color_args[8];
6070
6071 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6072 LLVMValueRef values[4];
6073
6074 if (!(ctx->output_mask & (1ull << i)))
6075 continue;
6076
6077 if (i == FRAG_RESULT_DEPTH) {
6078 ctx->shader_info->fs.writes_z = true;
6079 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6080 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6081 } else if (i == FRAG_RESULT_STENCIL) {
6082 ctx->shader_info->fs.writes_stencil = true;
6083 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6084 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6085 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6086 ctx->shader_info->fs.writes_sample_mask = true;
6087 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6088 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6089 } else {
6090 bool last = false;
6091 for (unsigned j = 0; j < 4; j++)
6092 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6093 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6094
6095 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6096 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6097
6098 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6099 if (ret)
6100 index++;
6101 }
6102 }
6103
6104 for (unsigned i = 0; i < index; i++)
6105 ac_build_export(&ctx->ac, &color_args[i]);
6106 if (depth || stencil || samplemask)
6107 si_export_mrt_z(ctx, depth, stencil, samplemask);
6108 else if (!index) {
6109 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6110 ac_build_export(&ctx->ac, &color_args[0]);
6111 }
6112
6113 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6114 }
6115
6116 static void
6117 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6118 {
6119 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6120 }
6121
6122 static void
6123 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6124 LLVMValueRef *addrs)
6125 {
6126 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6127
6128 switch (ctx->stage) {
6129 case MESA_SHADER_VERTEX:
6130 if (ctx->options->key.vs.as_ls)
6131 handle_ls_outputs_post(ctx);
6132 else if (ctx->options->key.vs.as_es)
6133 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6134 else
6135 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6136 &ctx->shader_info->vs.outinfo);
6137 break;
6138 case MESA_SHADER_FRAGMENT:
6139 handle_fs_outputs_post(ctx);
6140 break;
6141 case MESA_SHADER_GEOMETRY:
6142 emit_gs_epilogue(ctx);
6143 break;
6144 case MESA_SHADER_TESS_CTRL:
6145 handle_tcs_outputs_post(ctx);
6146 break;
6147 case MESA_SHADER_TESS_EVAL:
6148 if (ctx->options->key.tes.as_es)
6149 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6150 else
6151 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6152 &ctx->shader_info->tes.outinfo);
6153 break;
6154 default:
6155 break;
6156 }
6157 }
6158
6159 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6160 {
6161 LLVMPassManagerRef passmgr;
6162 /* Create the pass manager */
6163 passmgr = LLVMCreateFunctionPassManagerForModule(
6164 ctx->module);
6165
6166 /* This pass should eliminate all the load and store instructions */
6167 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6168
6169 /* Add some optimization passes */
6170 LLVMAddScalarReplAggregatesPass(passmgr);
6171 LLVMAddLICMPass(passmgr);
6172 LLVMAddAggressiveDCEPass(passmgr);
6173 LLVMAddCFGSimplificationPass(passmgr);
6174 LLVMAddInstructionCombiningPass(passmgr);
6175
6176 /* Run the pass */
6177 LLVMInitializeFunctionPassManager(passmgr);
6178 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6179 LLVMFinalizeFunctionPassManager(passmgr);
6180
6181 LLVMDisposeBuilder(ctx->builder);
6182 LLVMDisposePassManager(passmgr);
6183 }
6184
6185 static void
6186 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6187 {
6188 struct ac_vs_output_info *outinfo;
6189
6190 switch (ctx->stage) {
6191 case MESA_SHADER_FRAGMENT:
6192 case MESA_SHADER_COMPUTE:
6193 case MESA_SHADER_TESS_CTRL:
6194 case MESA_SHADER_GEOMETRY:
6195 return;
6196 case MESA_SHADER_VERTEX:
6197 if (ctx->options->key.vs.as_ls ||
6198 ctx->options->key.vs.as_es)
6199 return;
6200 outinfo = &ctx->shader_info->vs.outinfo;
6201 break;
6202 case MESA_SHADER_TESS_EVAL:
6203 if (ctx->options->key.vs.as_es)
6204 return;
6205 outinfo = &ctx->shader_info->tes.outinfo;
6206 break;
6207 default:
6208 unreachable("Unhandled shader type");
6209 }
6210
6211 ac_optimize_vs_outputs(&ctx->ac,
6212 ctx->main_function,
6213 outinfo->vs_output_param_offset,
6214 VARYING_SLOT_MAX,
6215 &outinfo->param_exports);
6216 }
6217
6218 static void
6219 ac_setup_rings(struct nir_to_llvm_context *ctx)
6220 {
6221 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6222 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6223 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6224 }
6225
6226 if (ctx->is_gs_copy_shader) {
6227 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6228 }
6229 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6230 LLVMValueRef tmp;
6231 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6232 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6233
6234 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6235
6236 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6237 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6238 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6239 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6240 }
6241
6242 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6243 ctx->stage == MESA_SHADER_TESS_EVAL) {
6244 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6245 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6246 }
6247 }
6248
6249 static unsigned
6250 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6251 const struct nir_shader *nir)
6252 {
6253 switch (nir->stage) {
6254 case MESA_SHADER_TESS_CTRL:
6255 return chip_class >= CIK ? 128 : 64;
6256 case MESA_SHADER_GEOMETRY:
6257 return 64;
6258 case MESA_SHADER_COMPUTE:
6259 break;
6260 default:
6261 return 0;
6262 }
6263
6264 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6265 nir->info.cs.local_size[1] *
6266 nir->info.cs.local_size[2];
6267 return max_workgroup_size;
6268 }
6269
6270 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6271 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6272 {
6273 struct ac_nir_context ctx = {};
6274 struct nir_function *func;
6275
6276 ctx.ac = *ac;
6277 ctx.abi = abi;
6278
6279 ctx.nctx = nctx;
6280 if (nctx)
6281 nctx->nir = &ctx;
6282
6283 ctx.stage = nir->stage;
6284
6285 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6286
6287 nir_foreach_variable(variable, &nir->outputs)
6288 handle_shader_output_decl(&ctx, nir, variable);
6289
6290 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6291 _mesa_key_pointer_equal);
6292 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6293 _mesa_key_pointer_equal);
6294 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6295 _mesa_key_pointer_equal);
6296
6297 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6298
6299 setup_locals(&ctx, func);
6300
6301 if (nir->stage == MESA_SHADER_COMPUTE)
6302 setup_shared(&ctx, nir);
6303
6304 visit_cf_list(&ctx, &func->impl->body);
6305 phi_post_pass(&ctx);
6306
6307 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6308 ctx.outputs);
6309
6310 free(ctx.locals);
6311 ralloc_free(ctx.defs);
6312 ralloc_free(ctx.phis);
6313 ralloc_free(ctx.vars);
6314
6315 if (nctx)
6316 nctx->nir = NULL;
6317 }
6318
6319 static
6320 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6321 struct nir_shader *nir,
6322 struct ac_shader_variant_info *shader_info,
6323 const struct ac_nir_compiler_options *options)
6324 {
6325 struct nir_to_llvm_context ctx = {0};
6326 unsigned i;
6327 ctx.options = options;
6328 ctx.shader_info = shader_info;
6329 ctx.context = LLVMContextCreate();
6330 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6331
6332 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6333 ctx.ac.module = ctx.module;
6334
6335 memset(shader_info, 0, sizeof(*shader_info));
6336
6337 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6338
6339 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6340
6341 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6342 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6343 LLVMSetDataLayout(ctx.module, data_layout_str);
6344 LLVMDisposeTargetData(data_layout);
6345 LLVMDisposeMessage(data_layout_str);
6346
6347 setup_types(&ctx);
6348
6349 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6350 ctx.ac.builder = ctx.builder;
6351 ctx.stage = nir->stage;
6352 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6353
6354 for (i = 0; i < AC_UD_MAX_SETS; i++)
6355 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6356 for (i = 0; i < AC_UD_MAX_UD; i++)
6357 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6358
6359 create_function(&ctx);
6360
6361 if (nir->stage == MESA_SHADER_GEOMETRY) {
6362 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6363
6364 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6365 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6366 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6367 } else if (nir->stage == MESA_SHADER_VERTEX) {
6368 if (shader_info->info.vs.needs_instance_id) {
6369 ctx.shader_info->vs.vgpr_comp_cnt =
6370 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6371 }
6372 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6373 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6374 }
6375
6376 ac_setup_rings(&ctx);
6377
6378 ctx.num_output_clips = nir->info.clip_distance_array_size;
6379 ctx.num_output_culls = nir->info.cull_distance_array_size;
6380
6381 if (nir->stage == MESA_SHADER_FRAGMENT)
6382 handle_fs_inputs(&ctx, nir);
6383 else if(nir->stage == MESA_SHADER_VERTEX)
6384 handle_vs_inputs(&ctx, nir);
6385
6386 ctx.abi.inputs = &ctx.inputs[0];
6387 ctx.abi.emit_outputs = handle_shader_outputs_post;
6388 ctx.abi.load_ssbo = radv_load_ssbo;
6389 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6390
6391 nir_foreach_variable(variable, &nir->outputs)
6392 scan_shader_output_decl(&ctx, variable);
6393
6394 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6395
6396 LLVMBuildRetVoid(ctx.builder);
6397
6398 ac_llvm_finalize_module(&ctx);
6399
6400 ac_nir_eliminate_const_vs_outputs(&ctx);
6401
6402 if (nir->stage == MESA_SHADER_GEOMETRY) {
6403 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6404 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6405 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6406 nir->info.gs.vertices_out;
6407 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6408 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6409 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6410 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6411 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6412 }
6413
6414 return ctx.module;
6415 }
6416
6417 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6418 {
6419 unsigned *retval = (unsigned *)context;
6420 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6421 char *description = LLVMGetDiagInfoDescription(di);
6422
6423 if (severity == LLVMDSError) {
6424 *retval = 1;
6425 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6426 description);
6427 }
6428
6429 LLVMDisposeMessage(description);
6430 }
6431
6432 static unsigned ac_llvm_compile(LLVMModuleRef M,
6433 struct ac_shader_binary *binary,
6434 LLVMTargetMachineRef tm)
6435 {
6436 unsigned retval = 0;
6437 char *err;
6438 LLVMContextRef llvm_ctx;
6439 LLVMMemoryBufferRef out_buffer;
6440 unsigned buffer_size;
6441 const char *buffer_data;
6442 LLVMBool mem_err;
6443
6444 /* Setup Diagnostic Handler*/
6445 llvm_ctx = LLVMGetModuleContext(M);
6446
6447 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6448 &retval);
6449
6450 /* Compile IR*/
6451 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6452 &err, &out_buffer);
6453
6454 /* Process Errors/Warnings */
6455 if (mem_err) {
6456 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6457 free(err);
6458 retval = 1;
6459 goto out;
6460 }
6461
6462 /* Extract Shader Code*/
6463 buffer_size = LLVMGetBufferSize(out_buffer);
6464 buffer_data = LLVMGetBufferStart(out_buffer);
6465
6466 ac_elf_read(buffer_data, buffer_size, binary);
6467
6468 /* Clean up */
6469 LLVMDisposeMemoryBuffer(out_buffer);
6470
6471 out:
6472 return retval;
6473 }
6474
6475 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6476 LLVMModuleRef llvm_module,
6477 struct ac_shader_binary *binary,
6478 struct ac_shader_config *config,
6479 struct ac_shader_variant_info *shader_info,
6480 gl_shader_stage stage,
6481 bool dump_shader, bool supports_spill)
6482 {
6483 if (dump_shader)
6484 ac_dump_module(llvm_module);
6485
6486 memset(binary, 0, sizeof(*binary));
6487 int v = ac_llvm_compile(llvm_module, binary, tm);
6488 if (v) {
6489 fprintf(stderr, "compile failed\n");
6490 }
6491
6492 if (dump_shader)
6493 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6494
6495 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6496
6497 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6498 LLVMDisposeModule(llvm_module);
6499 LLVMContextDispose(ctx);
6500
6501 if (stage == MESA_SHADER_FRAGMENT) {
6502 shader_info->num_input_vgprs = 0;
6503 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6504 shader_info->num_input_vgprs += 2;
6505 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6506 shader_info->num_input_vgprs += 2;
6507 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6508 shader_info->num_input_vgprs += 2;
6509 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6510 shader_info->num_input_vgprs += 3;
6511 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6512 shader_info->num_input_vgprs += 2;
6513 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6514 shader_info->num_input_vgprs += 2;
6515 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6516 shader_info->num_input_vgprs += 2;
6517 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6518 shader_info->num_input_vgprs += 1;
6519 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6520 shader_info->num_input_vgprs += 1;
6521 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6522 shader_info->num_input_vgprs += 1;
6523 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6524 shader_info->num_input_vgprs += 1;
6525 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6526 shader_info->num_input_vgprs += 1;
6527 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6528 shader_info->num_input_vgprs += 1;
6529 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6530 shader_info->num_input_vgprs += 1;
6531 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6532 shader_info->num_input_vgprs += 1;
6533 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6534 shader_info->num_input_vgprs += 1;
6535 }
6536 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6537
6538 /* +3 for scratch wave offset and VCC */
6539 config->num_sgprs = MAX2(config->num_sgprs,
6540 shader_info->num_input_sgprs + 3);
6541 }
6542
6543 static void
6544 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6545 {
6546 switch (nir->stage) {
6547 case MESA_SHADER_COMPUTE:
6548 for (int i = 0; i < 3; ++i)
6549 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6550 break;
6551 case MESA_SHADER_FRAGMENT:
6552 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6553 break;
6554 case MESA_SHADER_GEOMETRY:
6555 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6556 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6557 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6558 shader_info->gs.invocations = nir->info.gs.invocations;
6559 break;
6560 case MESA_SHADER_TESS_EVAL:
6561 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6562 shader_info->tes.spacing = nir->info.tess.spacing;
6563 shader_info->tes.ccw = nir->info.tess.ccw;
6564 shader_info->tes.point_mode = nir->info.tess.point_mode;
6565 shader_info->tes.as_es = options->key.tes.as_es;
6566 break;
6567 case MESA_SHADER_TESS_CTRL:
6568 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6569 break;
6570 case MESA_SHADER_VERTEX:
6571 shader_info->vs.as_es = options->key.vs.as_es;
6572 shader_info->vs.as_ls = options->key.vs.as_ls;
6573 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6574 if (options->key.vs.as_ls)
6575 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6576 break;
6577 default:
6578 break;
6579 }
6580 }
6581
6582 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6583 struct ac_shader_binary *binary,
6584 struct ac_shader_config *config,
6585 struct ac_shader_variant_info *shader_info,
6586 struct nir_shader *const *nir,
6587 int nir_count,
6588 const struct ac_nir_compiler_options *options,
6589 bool dump_shader)
6590 {
6591
6592 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir[0], shader_info,
6593 options);
6594
6595 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->stage, dump_shader, options->supports_spill);
6596 for (int i = 0; i < nir_count; ++i)
6597 ac_fill_shader_info(shader_info, nir[i], options);
6598 }
6599
6600 static void
6601 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6602 {
6603 LLVMValueRef args[9];
6604 args[0] = ctx->gsvs_ring;
6605 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6606 args[3] = ctx->i32zero;
6607 args[4] = ctx->i32one; /* OFFEN */
6608 args[5] = ctx->i32zero; /* IDXEN */
6609 args[6] = ctx->i32one; /* GLC */
6610 args[7] = ctx->i32one; /* SLC */
6611 args[8] = ctx->i32zero; /* TFE */
6612
6613 int idx = 0;
6614
6615 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6616 int length = 4;
6617 int slot = idx;
6618 int slot_inc = 1;
6619 if (!(ctx->output_mask & (1ull << i)))
6620 continue;
6621
6622 if (i == VARYING_SLOT_CLIP_DIST0) {
6623 /* unpack clip and cull from a single set of slots */
6624 length = ctx->num_output_clips + ctx->num_output_culls;
6625 if (length > 4)
6626 slot_inc = 2;
6627 }
6628
6629 for (unsigned j = 0; j < length; j++) {
6630 LLVMValueRef value;
6631 args[2] = LLVMConstInt(ctx->i32,
6632 (slot * 4 + j) *
6633 ctx->gs_max_out_vertices * 16 * 4, false);
6634
6635 value = ac_build_intrinsic(&ctx->ac,
6636 "llvm.SI.buffer.load.dword.i32.i32",
6637 ctx->i32, args, 9,
6638 AC_FUNC_ATTR_READONLY |
6639 AC_FUNC_ATTR_LEGACY);
6640
6641 LLVMBuildStore(ctx->builder,
6642 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6643 }
6644 idx += slot_inc;
6645 }
6646 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6647 }
6648
6649 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6650 struct nir_shader *geom_shader,
6651 struct ac_shader_binary *binary,
6652 struct ac_shader_config *config,
6653 struct ac_shader_variant_info *shader_info,
6654 const struct ac_nir_compiler_options *options,
6655 bool dump_shader)
6656 {
6657 struct nir_to_llvm_context ctx = {0};
6658 ctx.context = LLVMContextCreate();
6659 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6660 ctx.options = options;
6661 ctx.shader_info = shader_info;
6662
6663 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6664 ctx.ac.module = ctx.module;
6665
6666 ctx.is_gs_copy_shader = true;
6667 LLVMSetTarget(ctx.module, "amdgcn--");
6668 setup_types(&ctx);
6669
6670 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6671 ctx.ac.builder = ctx.builder;
6672 ctx.stage = MESA_SHADER_VERTEX;
6673
6674 create_function(&ctx);
6675
6676 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6677 ac_setup_rings(&ctx);
6678
6679 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6680 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6681
6682 struct ac_nir_context nir_ctx = {};
6683 nir_ctx.ac = ctx.ac;
6684 nir_ctx.abi = &ctx.abi;
6685
6686 nir_ctx.nctx = &ctx;
6687 ctx.nir = &nir_ctx;
6688
6689 nir_foreach_variable(variable, &geom_shader->outputs) {
6690 scan_shader_output_decl(&ctx, variable);
6691 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6692 }
6693
6694 ac_gs_copy_shader_emit(&ctx);
6695
6696 ctx.nir = NULL;
6697
6698 LLVMBuildRetVoid(ctx.builder);
6699
6700 ac_llvm_finalize_module(&ctx);
6701
6702 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6703 MESA_SHADER_VERTEX,
6704 dump_shader, options->supports_spill);
6705 }