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ac: add emit_vertex to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
163 const nir_deref_var *deref,
164 enum ac_descriptor_type desc_type,
165 const nir_tex_instr *instr,
166 bool image, bool write);
167
168 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
169 {
170 return (index * 4) + chan;
171 }
172
173 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
174 {
175 /* handle patch indices separate */
176 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
177 return 0;
178 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
179 return 1;
180 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
181 return 2 + (slot - VARYING_SLOT_PATCH0);
182
183 if (slot == VARYING_SLOT_POS)
184 return 0;
185 if (slot == VARYING_SLOT_PSIZ)
186 return 1;
187 if (slot == VARYING_SLOT_CLIP_DIST0)
188 return 2;
189 /* 3 is reserved for clip dist as well */
190 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
191 return 4 + (slot - VARYING_SLOT_VAR0);
192 unreachable("illegal slot in get unique index\n");
193 }
194
195 static void set_llvm_calling_convention(LLVMValueRef func,
196 gl_shader_stage stage)
197 {
198 enum radeon_llvm_calling_convention calling_conv;
199
200 switch (stage) {
201 case MESA_SHADER_VERTEX:
202 case MESA_SHADER_TESS_EVAL:
203 calling_conv = RADEON_LLVM_AMDGPU_VS;
204 break;
205 case MESA_SHADER_GEOMETRY:
206 calling_conv = RADEON_LLVM_AMDGPU_GS;
207 break;
208 case MESA_SHADER_TESS_CTRL:
209 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
210 break;
211 case MESA_SHADER_FRAGMENT:
212 calling_conv = RADEON_LLVM_AMDGPU_PS;
213 break;
214 case MESA_SHADER_COMPUTE:
215 calling_conv = RADEON_LLVM_AMDGPU_CS;
216 break;
217 default:
218 unreachable("Unhandle shader type");
219 }
220
221 LLVMSetFunctionCallConv(func, calling_conv);
222 }
223
224 #define MAX_ARGS 23
225 struct arg_info {
226 LLVMTypeRef types[MAX_ARGS];
227 LLVMValueRef *assign[MAX_ARGS];
228 unsigned array_params_mask;
229 uint8_t count;
230 uint8_t user_sgpr_count;
231 uint8_t sgpr_count;
232 uint8_t num_user_sgprs_used;
233 uint8_t num_sgprs_used;
234 uint8_t num_vgprs_used;
235 };
236
237 static inline void
238 add_argument(struct arg_info *info,
239 LLVMTypeRef type, LLVMValueRef *param_ptr)
240 {
241 assert(info->count < MAX_ARGS);
242 info->assign[info->count] = param_ptr;
243 info->types[info->count] = type;
244 info->count++;
245 }
246
247 static inline void
248 add_sgpr_argument(struct arg_info *info,
249 LLVMTypeRef type, LLVMValueRef *param_ptr)
250 {
251 add_argument(info, type, param_ptr);
252 info->num_sgprs_used += ac_get_type_size(type) / 4;
253 info->sgpr_count++;
254 }
255
256 static inline void
257 add_user_sgpr_argument(struct arg_info *info,
258 LLVMTypeRef type,
259 LLVMValueRef *param_ptr)
260 {
261 add_sgpr_argument(info, type, param_ptr);
262 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
263 info->user_sgpr_count++;
264 }
265
266 static inline void
267 add_vgpr_argument(struct arg_info *info,
268 LLVMTypeRef type,
269 LLVMValueRef *param_ptr)
270 {
271 add_argument(info, type, param_ptr);
272 info->num_vgprs_used += ac_get_type_size(type) / 4;
273 }
274
275 static inline void
276 add_user_sgpr_array_argument(struct arg_info *info,
277 LLVMTypeRef type,
278 LLVMValueRef *param_ptr)
279 {
280 info->array_params_mask |= (1 << info->count);
281 add_user_sgpr_argument(info, type, param_ptr);
282 }
283
284 static void assign_arguments(LLVMValueRef main_function,
285 struct arg_info *info)
286 {
287 unsigned i;
288 for (i = 0; i < info->count; i++) {
289 if (info->assign[i])
290 *info->assign[i] = LLVMGetParam(main_function, i);
291 }
292 }
293
294 static LLVMValueRef
295 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
296 LLVMBuilderRef builder, LLVMTypeRef *return_types,
297 unsigned num_return_elems,
298 struct arg_info *args,
299 unsigned max_workgroup_size,
300 bool unsafe_math)
301 {
302 LLVMTypeRef main_function_type, ret_type;
303 LLVMBasicBlockRef main_function_body;
304
305 if (num_return_elems)
306 ret_type = LLVMStructTypeInContext(ctx, return_types,
307 num_return_elems, true);
308 else
309 ret_type = LLVMVoidTypeInContext(ctx);
310
311 /* Setup the function */
312 main_function_type =
313 LLVMFunctionType(ret_type, args->types, args->count, 0);
314 LLVMValueRef main_function =
315 LLVMAddFunction(module, "main", main_function_type);
316 main_function_body =
317 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
318 LLVMPositionBuilderAtEnd(builder, main_function_body);
319
320 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
321 for (unsigned i = 0; i < args->sgpr_count; ++i) {
322 if (args->array_params_mask & (1 << i)) {
323 LLVMValueRef P = LLVMGetParam(main_function, i);
324 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
325 ac_add_attr_dereferenceable(P, UINT64_MAX);
326 }
327 else {
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
329 }
330 }
331
332 if (max_workgroup_size) {
333 ac_llvm_add_target_dep_function_attr(main_function,
334 "amdgpu-max-work-group-size",
335 max_workgroup_size);
336 }
337 if (unsafe_math) {
338 /* These were copied from some LLVM test. */
339 LLVMAddTargetDependentFunctionAttr(main_function,
340 "less-precise-fpmad",
341 "true");
342 LLVMAddTargetDependentFunctionAttr(main_function,
343 "no-infs-fp-math",
344 "true");
345 LLVMAddTargetDependentFunctionAttr(main_function,
346 "no-nans-fp-math",
347 "true");
348 LLVMAddTargetDependentFunctionAttr(main_function,
349 "unsafe-fp-math",
350 "true");
351 }
352 return main_function;
353 }
354
355 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
356 {
357 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
358 CONST_ADDR_SPACE);
359 }
360
361 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
362 {
363 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
364 type = LLVMGetElementType(type);
365
366 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
367 return LLVMGetIntTypeWidth(type);
368
369 if (type == ctx->f16)
370 return 16;
371 if (type == ctx->f32)
372 return 32;
373 if (type == ctx->f64)
374 return 64;
375
376 unreachable("Unhandled type kind in get_elem_bits");
377 }
378
379 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
380 LLVMValueRef param, unsigned rshift,
381 unsigned bitwidth)
382 {
383 LLVMValueRef value = param;
384 if (rshift)
385 value = LLVMBuildLShr(ctx->builder, value,
386 LLVMConstInt(ctx->i32, rshift, false), "");
387
388 if (rshift + bitwidth < 32) {
389 unsigned mask = (1 << bitwidth) - 1;
390 value = LLVMBuildAnd(ctx->builder, value,
391 LLVMConstInt(ctx->i32, mask, false), "");
392 }
393 return value;
394 }
395
396 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
397 {
398 switch (ctx->stage) {
399 case MESA_SHADER_TESS_CTRL:
400 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
401 case MESA_SHADER_TESS_EVAL:
402 return ctx->tes_rel_patch_id;
403 break;
404 default:
405 unreachable("Illegal stage");
406 }
407 }
408
409 /* Tessellation shaders pass outputs to the next shader using LDS.
410 *
411 * LS outputs = TCS inputs
412 * TCS outputs = TES inputs
413 *
414 * The LDS layout is:
415 * - TCS inputs for patch 0
416 * - TCS inputs for patch 1
417 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
418 * - ...
419 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
420 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
421 * - TCS outputs for patch 1
422 * - Per-patch TCS outputs for patch 1
423 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
424 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
425 * - ...
426 *
427 * All three shaders VS(LS), TCS, TES share the same LDS space.
428 */
429 static LLVMValueRef
430 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
431 {
432 if (ctx->stage == MESA_SHADER_VERTEX)
433 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
434 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
435 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
436 else {
437 assert(0);
438 return NULL;
439 }
440 }
441
442 static LLVMValueRef
443 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
444 {
445 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
446 }
447
448 static LLVMValueRef
449 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
450 {
451 return LLVMBuildMul(ctx->builder,
452 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
453 LLVMConstInt(ctx->ac.i32, 4, false), "");
454 }
455
456 static LLVMValueRef
457 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
458 {
459 return LLVMBuildMul(ctx->builder,
460 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
461 LLVMConstInt(ctx->ac.i32, 4, false), "");
462 }
463
464 static LLVMValueRef
465 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
466 {
467 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
468 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
469
470 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
471 }
472
473 static LLVMValueRef
474 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
475 {
476 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
477 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
478 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
479
480 return LLVMBuildAdd(ctx->builder, patch0_offset,
481 LLVMBuildMul(ctx->builder, patch_stride,
482 rel_patch_id, ""),
483 "");
484 }
485
486 static LLVMValueRef
487 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
488 {
489 LLVMValueRef patch0_patch_data_offset =
490 get_tcs_out_patch0_patch_data_offset(ctx);
491 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
492 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
493
494 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
495 LLVMBuildMul(ctx->builder, patch_stride,
496 rel_patch_id, ""),
497 "");
498 }
499
500 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
501 {
502 ud_info->sgpr_idx = *sgpr_idx;
503 ud_info->num_sgprs = num_sgprs;
504 ud_info->indirect = false;
505 ud_info->indirect_offset = 0;
506 *sgpr_idx += num_sgprs;
507 }
508
509 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
510 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
511 {
512 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
513 }
514
515
516 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
517 uint32_t indirect_offset)
518 {
519 ud_info->sgpr_idx = sgpr_idx;
520 ud_info->num_sgprs = num_sgprs;
521 ud_info->indirect = true;
522 ud_info->indirect_offset = indirect_offset;
523 }
524
525 struct user_sgpr_info {
526 bool need_ring_offsets;
527 uint8_t sgpr_count;
528 bool indirect_all_descriptor_sets;
529 };
530
531 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
532 struct user_sgpr_info *user_sgpr_info)
533 {
534 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
535
536 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
537 if (ctx->stage == MESA_SHADER_GEOMETRY ||
538 ctx->stage == MESA_SHADER_VERTEX ||
539 ctx->stage == MESA_SHADER_TESS_CTRL ||
540 ctx->stage == MESA_SHADER_TESS_EVAL ||
541 ctx->is_gs_copy_shader)
542 user_sgpr_info->need_ring_offsets = true;
543
544 if (ctx->stage == MESA_SHADER_FRAGMENT &&
545 ctx->shader_info->info.ps.needs_sample_positions)
546 user_sgpr_info->need_ring_offsets = true;
547
548 /* 2 user sgprs will nearly always be allocated for scratch/rings */
549 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
550 user_sgpr_info->sgpr_count += 2;
551 }
552
553 switch (ctx->stage) {
554 case MESA_SHADER_COMPUTE:
555 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
556 break;
557 case MESA_SHADER_FRAGMENT:
558 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
559 break;
560 case MESA_SHADER_VERTEX:
561 if (!ctx->is_gs_copy_shader) {
562 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
563 if (ctx->shader_info->info.vs.needs_draw_id) {
564 user_sgpr_info->sgpr_count += 3;
565 } else {
566 user_sgpr_info->sgpr_count += 2;
567 }
568 }
569 if (ctx->options->key.vs.as_ls)
570 user_sgpr_info->sgpr_count++;
571 break;
572 case MESA_SHADER_TESS_CTRL:
573 user_sgpr_info->sgpr_count += 4;
574 break;
575 case MESA_SHADER_TESS_EVAL:
576 user_sgpr_info->sgpr_count += 1;
577 break;
578 case MESA_SHADER_GEOMETRY:
579 user_sgpr_info->sgpr_count += 2;
580 break;
581 default:
582 break;
583 }
584
585 if (ctx->shader_info->info.needs_push_constants)
586 user_sgpr_info->sgpr_count += 2;
587
588 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
589 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
590 user_sgpr_info->sgpr_count += 2;
591 user_sgpr_info->indirect_all_descriptor_sets = true;
592 } else {
593 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
594 }
595 }
596
597 static void
598 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
599 gl_shader_stage stage,
600 bool has_previous_stage,
601 gl_shader_stage previous_stage,
602 const struct user_sgpr_info *user_sgpr_info,
603 struct arg_info *args,
604 LLVMValueRef *desc_sets)
605 {
606 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
607 unsigned stage_mask = 1 << stage;
608 if (has_previous_stage)
609 stage_mask |= 1 << previous_stage;
610
611 /* 1 for each descriptor set */
612 if (!user_sgpr_info->indirect_all_descriptor_sets) {
613 for (unsigned i = 0; i < num_sets; ++i) {
614 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
615 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
616 }
617 }
618 } else
619 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
620
621 if (ctx->shader_info->info.needs_push_constants) {
622 /* 1 for push constants and dynamic descriptors */
623 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
624 }
625 }
626
627 static void
628 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
629 gl_shader_stage stage,
630 bool has_previous_stage,
631 gl_shader_stage previous_stage,
632 const struct user_sgpr_info *user_sgpr_info,
633 LLVMValueRef desc_sets,
634 uint8_t *user_sgpr_idx)
635 {
636 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
637 unsigned stage_mask = 1 << stage;
638 if (has_previous_stage)
639 stage_mask |= 1 << previous_stage;
640
641 if (!user_sgpr_info->indirect_all_descriptor_sets) {
642 for (unsigned i = 0; i < num_sets; ++i) {
643 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
644 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
645 } else
646 ctx->descriptor_sets[i] = NULL;
647 }
648 } else {
649 uint32_t desc_sgpr_idx = *user_sgpr_idx;
650 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
651
652 for (unsigned i = 0; i < num_sets; ++i) {
653 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
654 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
655 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
656
657 } else
658 ctx->descriptor_sets[i] = NULL;
659 }
660 ctx->shader_info->need_indirect_descriptor_sets = true;
661 }
662
663 if (ctx->shader_info->info.needs_push_constants) {
664 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
665 }
666 }
667
668 static void
669 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
670 gl_shader_stage stage,
671 bool has_previous_stage,
672 gl_shader_stage previous_stage,
673 struct arg_info *args)
674 {
675 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
676 if (ctx->shader_info->info.vs.has_vertex_buffers)
677 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
678 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
679 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
680 if (ctx->shader_info->info.vs.needs_draw_id)
681 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
682 }
683 }
684
685 static void
686 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
687 gl_shader_stage stage,
688 bool has_previous_stage,
689 gl_shader_stage previous_stage,
690 uint8_t *user_sgpr_idx)
691 {
692 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
693 if (ctx->shader_info->info.vs.has_vertex_buffers) {
694 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
695 }
696 unsigned vs_num = 2;
697 if (ctx->shader_info->info.vs.needs_draw_id)
698 vs_num++;
699
700 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
701 }
702 }
703
704
705 static void create_function(struct nir_to_llvm_context *ctx,
706 gl_shader_stage stage,
707 bool has_previous_stage,
708 gl_shader_stage previous_stage)
709 {
710 uint8_t user_sgpr_idx;
711 struct user_sgpr_info user_sgpr_info;
712 struct arg_info args = {};
713 LLVMValueRef desc_sets;
714
715 allocate_user_sgprs(ctx, &user_sgpr_info);
716
717 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
718 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
719 }
720
721 switch (stage) {
722 case MESA_SHADER_COMPUTE:
723 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
724 if (ctx->shader_info->info.cs.grid_components_used)
725 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
726 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
727 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
728 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
729 break;
730 case MESA_SHADER_VERTEX:
731 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
732 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
733 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
734 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
735 if (ctx->options->key.vs.as_es)
736 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
737 else if (ctx->options->key.vs.as_ls)
738 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
739 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
740 if (!ctx->is_gs_copy_shader) {
741 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
742 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
743 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
744 }
745 break;
746 case MESA_SHADER_TESS_CTRL:
747 if (has_previous_stage) {
748 // First 6 system regs
749 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
750 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
751 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
752
753 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
754 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
755 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
756
757 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
758 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
759 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
760
761 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
762 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
763 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
764 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
765 if (ctx->shader_info->info.needs_multiview_view_index)
766 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
767
768 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
769 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
770 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
771 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
772 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
773 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
774 } else {
775 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
776 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
777 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
778 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
779 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
780 if (ctx->shader_info->info.needs_multiview_view_index)
781 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
782 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
783 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
784 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
785 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
786 }
787 break;
788 case MESA_SHADER_TESS_EVAL:
789 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
791 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
792 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
793 if (ctx->options->key.tes.as_es) {
794 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
795 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
796 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
797 } else {
798 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
799 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
800 }
801 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
802 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
803 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
804 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
805 break;
806 case MESA_SHADER_GEOMETRY:
807 if (has_previous_stage) {
808 // First 6 system regs
809 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
810 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
811 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
812
813 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
814 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
815 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
816
817 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
818 if (previous_stage == MESA_SHADER_TESS_EVAL)
819 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
820 else
821 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
822 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
823 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
824 if (ctx->shader_info->info.needs_multiview_view_index)
825 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
826
827 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
828 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
829 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_prim_id); // prim id
830 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_invocation_id);
831 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
832
833 if (previous_stage == MESA_SHADER_VERTEX) {
834 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
835 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
836 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
837 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
838 } else {
839 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
840 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
841 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
842 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
843 }
844 } else {
845 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
846 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
847 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
848 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
849 if (ctx->shader_info->info.needs_multiview_view_index)
850 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
851 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
852 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
853 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
854 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_prim_id); // prim id
856 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
857 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
860 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_invocation_id);
861 }
862 break;
863 case MESA_SHADER_FRAGMENT:
864 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
865 if (ctx->shader_info->info.ps.needs_sample_positions)
866 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
867 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
868 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
869 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
870 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
871 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
872 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
873 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
874 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
875 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
876 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
877 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
878 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
879 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
880 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
881 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
883 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
884 break;
885 default:
886 unreachable("Shader stage not implemented");
887 }
888
889 ctx->main_function = create_llvm_function(
890 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
891 ctx->max_workgroup_size,
892 ctx->options->unsafe_math);
893 set_llvm_calling_convention(ctx->main_function, stage);
894
895
896 ctx->shader_info->num_input_vgprs = 0;
897 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
898
899 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
900
901 if (ctx->stage != MESA_SHADER_FRAGMENT)
902 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
903
904 assign_arguments(ctx->main_function, &args);
905
906 user_sgpr_idx = 0;
907
908 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
909 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
910 if (ctx->options->supports_spill) {
911 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
912 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
913 NULL, 0, AC_FUNC_ATTR_READNONE);
914 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
915 const_array(ctx->ac.v4i32, 16), "");
916 }
917 }
918
919 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
920 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
921 if (has_previous_stage)
922 user_sgpr_idx = 0;
923
924 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
925
926 switch (stage) {
927 case MESA_SHADER_COMPUTE:
928 if (ctx->shader_info->info.cs.grid_components_used) {
929 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
930 }
931 break;
932 case MESA_SHADER_VERTEX:
933 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
934 if (ctx->view_index)
935 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
936 if (ctx->options->key.vs.as_ls) {
937 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
938 }
939 if (ctx->options->key.vs.as_ls)
940 ac_declare_lds_as_pointer(&ctx->ac);
941 break;
942 case MESA_SHADER_TESS_CTRL:
943 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
944 if (has_previous_stage)
945 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
946 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
947 if (ctx->view_index)
948 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
949 ac_declare_lds_as_pointer(&ctx->ac);
950 break;
951 case MESA_SHADER_TESS_EVAL:
952 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
953 if (ctx->view_index)
954 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
955 break;
956 case MESA_SHADER_GEOMETRY:
957 if (has_previous_stage) {
958 if (previous_stage == MESA_SHADER_VERTEX)
959 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
960 else
961 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
962 }
963 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
964 if (ctx->view_index)
965 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
966 if (has_previous_stage)
967 ac_declare_lds_as_pointer(&ctx->ac);
968 break;
969 case MESA_SHADER_FRAGMENT:
970 if (ctx->shader_info->info.ps.needs_sample_positions) {
971 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
972 }
973 break;
974 default:
975 unreachable("Shader stage not implemented");
976 }
977
978 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
979 }
980
981 static int get_llvm_num_components(LLVMValueRef value)
982 {
983 LLVMTypeRef type = LLVMTypeOf(value);
984 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
985 ? LLVMGetVectorSize(type)
986 : 1;
987 return num_components;
988 }
989
990 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
991 LLVMValueRef value,
992 int index)
993 {
994 int count = get_llvm_num_components(value);
995
996 if (count == 1)
997 return value;
998
999 return LLVMBuildExtractElement(ac->builder, value,
1000 LLVMConstInt(ac->i32, index, false), "");
1001 }
1002
1003 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1004 LLVMValueRef value, unsigned count)
1005 {
1006 unsigned num_components = get_llvm_num_components(value);
1007 if (count == num_components)
1008 return value;
1009
1010 LLVMValueRef masks[] = {
1011 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1012 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1013
1014 if (count == 1)
1015 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1016 "");
1017
1018 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1019 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1020 }
1021
1022 static void
1023 build_store_values_extended(struct ac_llvm_context *ac,
1024 LLVMValueRef *values,
1025 unsigned value_count,
1026 unsigned value_stride,
1027 LLVMValueRef vec)
1028 {
1029 LLVMBuilderRef builder = ac->builder;
1030 unsigned i;
1031
1032 for (i = 0; i < value_count; i++) {
1033 LLVMValueRef ptr = values[i * value_stride];
1034 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1035 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1036 LLVMBuildStore(builder, value, ptr);
1037 }
1038 }
1039
1040 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1041 const nir_ssa_def *def)
1042 {
1043 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1044 if (def->num_components > 1) {
1045 type = LLVMVectorType(type, def->num_components);
1046 }
1047 return type;
1048 }
1049
1050 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1051 {
1052 assert(src.is_ssa);
1053 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1054 return (LLVMValueRef)entry->data;
1055 }
1056
1057
1058 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1059 const struct nir_block *b)
1060 {
1061 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1062 return (LLVMBasicBlockRef)entry->data;
1063 }
1064
1065 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1066 nir_alu_src src,
1067 unsigned num_components)
1068 {
1069 LLVMValueRef value = get_src(ctx, src.src);
1070 bool need_swizzle = false;
1071
1072 assert(value);
1073 LLVMTypeRef type = LLVMTypeOf(value);
1074 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1075 ? LLVMGetVectorSize(type)
1076 : 1;
1077
1078 for (unsigned i = 0; i < num_components; ++i) {
1079 assert(src.swizzle[i] < src_components);
1080 if (src.swizzle[i] != i)
1081 need_swizzle = true;
1082 }
1083
1084 if (need_swizzle || num_components != src_components) {
1085 LLVMValueRef masks[] = {
1086 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1087 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1088 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1089 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1090
1091 if (src_components > 1 && num_components == 1) {
1092 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1093 masks[0], "");
1094 } else if (src_components == 1 && num_components > 1) {
1095 LLVMValueRef values[] = {value, value, value, value};
1096 value = ac_build_gather_values(&ctx->ac, values, num_components);
1097 } else {
1098 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1099 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1100 swizzle, "");
1101 }
1102 }
1103 assert(!src.negate);
1104 assert(!src.abs);
1105 return value;
1106 }
1107
1108 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1109 LLVMIntPredicate pred, LLVMValueRef src0,
1110 LLVMValueRef src1)
1111 {
1112 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1113 return LLVMBuildSelect(ctx->builder, result,
1114 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1115 LLVMConstInt(ctx->i32, 0, false), "");
1116 }
1117
1118 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1119 LLVMRealPredicate pred, LLVMValueRef src0,
1120 LLVMValueRef src1)
1121 {
1122 LLVMValueRef result;
1123 src0 = ac_to_float(ctx, src0);
1124 src1 = ac_to_float(ctx, src1);
1125 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1126 return LLVMBuildSelect(ctx->builder, result,
1127 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1128 LLVMConstInt(ctx->i32, 0, false), "");
1129 }
1130
1131 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1132 const char *intrin,
1133 LLVMTypeRef result_type,
1134 LLVMValueRef src0)
1135 {
1136 char name[64];
1137 LLVMValueRef params[] = {
1138 ac_to_float(ctx, src0),
1139 };
1140
1141 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1142 get_elem_bits(ctx, result_type));
1143 assert(length < sizeof(name));
1144 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1145 }
1146
1147 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1148 const char *intrin,
1149 LLVMTypeRef result_type,
1150 LLVMValueRef src0, LLVMValueRef src1)
1151 {
1152 char name[64];
1153 LLVMValueRef params[] = {
1154 ac_to_float(ctx, src0),
1155 ac_to_float(ctx, src1),
1156 };
1157
1158 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1159 get_elem_bits(ctx, result_type));
1160 assert(length < sizeof(name));
1161 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1162 }
1163
1164 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1165 const char *intrin,
1166 LLVMTypeRef result_type,
1167 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1168 {
1169 char name[64];
1170 LLVMValueRef params[] = {
1171 ac_to_float(ctx, src0),
1172 ac_to_float(ctx, src1),
1173 ac_to_float(ctx, src2),
1174 };
1175
1176 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1177 get_elem_bits(ctx, result_type));
1178 assert(length < sizeof(name));
1179 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1180 }
1181
1182 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1183 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1184 {
1185 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1186 ctx->i32_0, "");
1187 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1188 }
1189
1190 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1191 LLVMIntPredicate pred,
1192 LLVMValueRef src0, LLVMValueRef src1)
1193 {
1194 return LLVMBuildSelect(ctx->builder,
1195 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1196 src0,
1197 src1, "");
1198
1199 }
1200 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1201 LLVMValueRef src0)
1202 {
1203 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1204 LLVMBuildNeg(ctx->builder, src0, ""));
1205 }
1206
1207 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 LLVMValueRef cmp, val;
1211
1212 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1213 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1214 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1215 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1216 return val;
1217 }
1218
1219 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1220 LLVMValueRef src0)
1221 {
1222 LLVMValueRef cmp, val;
1223
1224 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1225 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1226 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1227 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1228 return val;
1229 }
1230
1231 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 const char *intr = "llvm.floor.f32";
1235 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1236 LLVMValueRef params[] = {
1237 fsrc0,
1238 };
1239 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1240 ctx->f32, params, 1,
1241 AC_FUNC_ATTR_READNONE);
1242 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1243 }
1244
1245 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1246 const char *intrin,
1247 LLVMValueRef src0, LLVMValueRef src1)
1248 {
1249 LLVMTypeRef ret_type;
1250 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1251 LLVMValueRef res;
1252 LLVMValueRef params[] = { src0, src1 };
1253 ret_type = LLVMStructTypeInContext(ctx->context, types,
1254 2, true);
1255
1256 res = ac_build_intrinsic(ctx, intrin, ret_type,
1257 params, 2, AC_FUNC_ATTR_READNONE);
1258
1259 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1260 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1261 return res;
1262 }
1263
1264 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1265 LLVMValueRef src0)
1266 {
1267 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1268 }
1269
1270 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1271 LLVMValueRef src0)
1272 {
1273 src0 = ac_to_float(ctx, src0);
1274 return LLVMBuildSExt(ctx->builder,
1275 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1276 ctx->i32, "");
1277 }
1278
1279 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1280 LLVMValueRef src0)
1281 {
1282 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1283 }
1284
1285 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1286 LLVMValueRef src0)
1287 {
1288 return LLVMBuildSExt(ctx->builder,
1289 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1290 ctx->i32, "");
1291 }
1292
1293 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 LLVMValueRef result;
1297 LLVMValueRef cond = NULL;
1298
1299 src0 = ac_to_float(&ctx->ac, src0);
1300 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1301
1302 if (ctx->options->chip_class >= VI) {
1303 LLVMValueRef args[2];
1304 /* Check if the result is a denormal - and flush to 0 if so. */
1305 args[0] = result;
1306 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1307 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1308 }
1309
1310 /* need to convert back up to f32 */
1311 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1312
1313 if (ctx->options->chip_class >= VI)
1314 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1315 else {
1316 /* for SI/CIK */
1317 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1318 * so compare the result and flush to 0 if it's smaller.
1319 */
1320 LLVMValueRef temp, cond2;
1321 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1322 ctx->ac.f32, result);
1323 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1324 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1325 temp, "");
1326 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1327 temp, ctx->ac.f32_0, "");
1328 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1329 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1330 }
1331 return result;
1332 }
1333
1334 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1335 LLVMValueRef src0, LLVMValueRef src1)
1336 {
1337 LLVMValueRef dst64, result;
1338 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1339 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1340
1341 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1342 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1343 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1344 return result;
1345 }
1346
1347 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1348 LLVMValueRef src0, LLVMValueRef src1)
1349 {
1350 LLVMValueRef dst64, result;
1351 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1352 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1353
1354 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1355 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1356 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1357 return result;
1358 }
1359
1360 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1361 bool is_signed,
1362 const LLVMValueRef srcs[3])
1363 {
1364 LLVMValueRef result;
1365 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1366
1367 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1368 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1369 return result;
1370 }
1371
1372 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1373 LLVMValueRef src0, LLVMValueRef src1,
1374 LLVMValueRef src2, LLVMValueRef src3)
1375 {
1376 LLVMValueRef bfi_args[3], result;
1377
1378 bfi_args[0] = LLVMBuildShl(ctx->builder,
1379 LLVMBuildSub(ctx->builder,
1380 LLVMBuildShl(ctx->builder,
1381 ctx->i32_1,
1382 src3, ""),
1383 ctx->i32_1, ""),
1384 src2, "");
1385 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1386 bfi_args[2] = src0;
1387
1388 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1389
1390 /* Calculate:
1391 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1392 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1393 */
1394 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1395 LLVMBuildAnd(ctx->builder, bfi_args[0],
1396 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1397
1398 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1399 return result;
1400 }
1401
1402 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1403 LLVMValueRef src0)
1404 {
1405 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1406 int i;
1407 LLVMValueRef comp[2];
1408
1409 src0 = ac_to_float(ctx, src0);
1410 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1411 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1412 for (i = 0; i < 2; i++) {
1413 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1414 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1415 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1416 }
1417
1418 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1419 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1420
1421 return comp[0];
1422 }
1423
1424 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1425 LLVMValueRef src0)
1426 {
1427 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1428 LLVMValueRef temps[2], result, val;
1429 int i;
1430
1431 for (i = 0; i < 2; i++) {
1432 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1433 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1434 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1435 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1436 }
1437
1438 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1439 ctx->i32_0, "");
1440 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1441 ctx->i32_1, "");
1442 return result;
1443 }
1444
1445 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1446 nir_op op,
1447 LLVMValueRef src0)
1448 {
1449 unsigned mask;
1450 int idx;
1451 LLVMValueRef result;
1452
1453 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1454 mask = AC_TID_MASK_LEFT;
1455 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1456 mask = AC_TID_MASK_TOP;
1457 else
1458 mask = AC_TID_MASK_TOP_LEFT;
1459
1460 /* for DDX we want to next X pixel, DDY next Y pixel. */
1461 if (op == nir_op_fddx_fine ||
1462 op == nir_op_fddx_coarse ||
1463 op == nir_op_fddx)
1464 idx = 1;
1465 else
1466 idx = 2;
1467
1468 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1469 return result;
1470 }
1471
1472 /*
1473 * this takes an I,J coordinate pair,
1474 * and works out the X and Y derivatives.
1475 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1476 */
1477 static LLVMValueRef emit_ddxy_interp(
1478 struct ac_nir_context *ctx,
1479 LLVMValueRef interp_ij)
1480 {
1481 LLVMValueRef result[4], a;
1482 unsigned i;
1483
1484 for (i = 0; i < 2; i++) {
1485 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1486 LLVMConstInt(ctx->ac.i32, i, false), "");
1487 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1488 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1489 }
1490 return ac_build_gather_values(&ctx->ac, result, 4);
1491 }
1492
1493 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1494 {
1495 LLVMValueRef src[4], result = NULL;
1496 unsigned num_components = instr->dest.dest.ssa.num_components;
1497 unsigned src_components;
1498 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1499
1500 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1501 switch (instr->op) {
1502 case nir_op_vec2:
1503 case nir_op_vec3:
1504 case nir_op_vec4:
1505 src_components = 1;
1506 break;
1507 case nir_op_pack_half_2x16:
1508 src_components = 2;
1509 break;
1510 case nir_op_unpack_half_2x16:
1511 src_components = 1;
1512 break;
1513 default:
1514 src_components = num_components;
1515 break;
1516 }
1517 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1518 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1519
1520 switch (instr->op) {
1521 case nir_op_fmov:
1522 case nir_op_imov:
1523 result = src[0];
1524 break;
1525 case nir_op_fneg:
1526 src[0] = ac_to_float(&ctx->ac, src[0]);
1527 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1528 break;
1529 case nir_op_ineg:
1530 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1531 break;
1532 case nir_op_inot:
1533 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1534 break;
1535 case nir_op_iadd:
1536 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1537 break;
1538 case nir_op_fadd:
1539 src[0] = ac_to_float(&ctx->ac, src[0]);
1540 src[1] = ac_to_float(&ctx->ac, src[1]);
1541 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1542 break;
1543 case nir_op_fsub:
1544 src[0] = ac_to_float(&ctx->ac, src[0]);
1545 src[1] = ac_to_float(&ctx->ac, src[1]);
1546 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1547 break;
1548 case nir_op_isub:
1549 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1550 break;
1551 case nir_op_imul:
1552 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1553 break;
1554 case nir_op_imod:
1555 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1556 break;
1557 case nir_op_umod:
1558 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1559 break;
1560 case nir_op_fmod:
1561 src[0] = ac_to_float(&ctx->ac, src[0]);
1562 src[1] = ac_to_float(&ctx->ac, src[1]);
1563 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1564 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1565 ac_to_float_type(&ctx->ac, def_type), result);
1566 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1567 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1568 break;
1569 case nir_op_frem:
1570 src[0] = ac_to_float(&ctx->ac, src[0]);
1571 src[1] = ac_to_float(&ctx->ac, src[1]);
1572 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_irem:
1575 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1576 break;
1577 case nir_op_idiv:
1578 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1579 break;
1580 case nir_op_udiv:
1581 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1582 break;
1583 case nir_op_fmul:
1584 src[0] = ac_to_float(&ctx->ac, src[0]);
1585 src[1] = ac_to_float(&ctx->ac, src[1]);
1586 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1587 break;
1588 case nir_op_fdiv:
1589 src[0] = ac_to_float(&ctx->ac, src[0]);
1590 src[1] = ac_to_float(&ctx->ac, src[1]);
1591 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1592 break;
1593 case nir_op_frcp:
1594 src[0] = ac_to_float(&ctx->ac, src[0]);
1595 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1596 break;
1597 case nir_op_iand:
1598 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1599 break;
1600 case nir_op_ior:
1601 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1602 break;
1603 case nir_op_ixor:
1604 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_ishl:
1607 result = LLVMBuildShl(ctx->ac.builder, src[0],
1608 LLVMBuildZExt(ctx->ac.builder, src[1],
1609 LLVMTypeOf(src[0]), ""),
1610 "");
1611 break;
1612 case nir_op_ishr:
1613 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1614 LLVMBuildZExt(ctx->ac.builder, src[1],
1615 LLVMTypeOf(src[0]), ""),
1616 "");
1617 break;
1618 case nir_op_ushr:
1619 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1620 LLVMBuildZExt(ctx->ac.builder, src[1],
1621 LLVMTypeOf(src[0]), ""),
1622 "");
1623 break;
1624 case nir_op_ilt:
1625 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1626 break;
1627 case nir_op_ine:
1628 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1629 break;
1630 case nir_op_ieq:
1631 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1632 break;
1633 case nir_op_ige:
1634 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1635 break;
1636 case nir_op_ult:
1637 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1638 break;
1639 case nir_op_uge:
1640 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1641 break;
1642 case nir_op_feq:
1643 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1644 break;
1645 case nir_op_fne:
1646 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1647 break;
1648 case nir_op_flt:
1649 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1650 break;
1651 case nir_op_fge:
1652 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1653 break;
1654 case nir_op_fabs:
1655 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1656 ac_to_float_type(&ctx->ac, def_type), src[0]);
1657 break;
1658 case nir_op_iabs:
1659 result = emit_iabs(&ctx->ac, src[0]);
1660 break;
1661 case nir_op_imax:
1662 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1663 break;
1664 case nir_op_imin:
1665 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1666 break;
1667 case nir_op_umax:
1668 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1669 break;
1670 case nir_op_umin:
1671 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1672 break;
1673 case nir_op_isign:
1674 result = emit_isign(&ctx->ac, src[0]);
1675 break;
1676 case nir_op_fsign:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 result = emit_fsign(&ctx->ac, src[0]);
1679 break;
1680 case nir_op_ffloor:
1681 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1682 ac_to_float_type(&ctx->ac, def_type), src[0]);
1683 break;
1684 case nir_op_ftrunc:
1685 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1686 ac_to_float_type(&ctx->ac, def_type), src[0]);
1687 break;
1688 case nir_op_fceil:
1689 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1690 ac_to_float_type(&ctx->ac, def_type), src[0]);
1691 break;
1692 case nir_op_fround_even:
1693 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1694 ac_to_float_type(&ctx->ac, def_type),src[0]);
1695 break;
1696 case nir_op_ffract:
1697 result = emit_ffract(&ctx->ac, src[0]);
1698 break;
1699 case nir_op_fsin:
1700 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1701 ac_to_float_type(&ctx->ac, def_type), src[0]);
1702 break;
1703 case nir_op_fcos:
1704 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1705 ac_to_float_type(&ctx->ac, def_type), src[0]);
1706 break;
1707 case nir_op_fsqrt:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1709 ac_to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_fexp2:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1713 ac_to_float_type(&ctx->ac, def_type), src[0]);
1714 break;
1715 case nir_op_flog2:
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1717 ac_to_float_type(&ctx->ac, def_type), src[0]);
1718 break;
1719 case nir_op_frsq:
1720 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1721 ac_to_float_type(&ctx->ac, def_type), src[0]);
1722 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1723 break;
1724 case nir_op_fpow:
1725 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1726 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1727 break;
1728 case nir_op_fmax:
1729 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1730 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1731 if (instr->dest.dest.ssa.bit_size == 32)
1732 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1733 ac_to_float_type(&ctx->ac, def_type),
1734 result);
1735 break;
1736 case nir_op_fmin:
1737 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1738 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1739 if (instr->dest.dest.ssa.bit_size == 32)
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1741 ac_to_float_type(&ctx->ac, def_type),
1742 result);
1743 break;
1744 case nir_op_ffma:
1745 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1746 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1747 break;
1748 case nir_op_ibitfield_extract:
1749 result = emit_bitfield_extract(&ctx->ac, true, src);
1750 break;
1751 case nir_op_ubitfield_extract:
1752 result = emit_bitfield_extract(&ctx->ac, false, src);
1753 break;
1754 case nir_op_bitfield_insert:
1755 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1756 break;
1757 case nir_op_bitfield_reverse:
1758 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1759 break;
1760 case nir_op_bit_count:
1761 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1762 break;
1763 case nir_op_vec2:
1764 case nir_op_vec3:
1765 case nir_op_vec4:
1766 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1767 src[i] = ac_to_integer(&ctx->ac, src[i]);
1768 result = ac_build_gather_values(&ctx->ac, src, num_components);
1769 break;
1770 case nir_op_f2i32:
1771 case nir_op_f2i64:
1772 src[0] = ac_to_float(&ctx->ac, src[0]);
1773 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1774 break;
1775 case nir_op_f2u32:
1776 case nir_op_f2u64:
1777 src[0] = ac_to_float(&ctx->ac, src[0]);
1778 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1779 break;
1780 case nir_op_i2f32:
1781 case nir_op_i2f64:
1782 src[0] = ac_to_integer(&ctx->ac, src[0]);
1783 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1784 break;
1785 case nir_op_u2f32:
1786 case nir_op_u2f64:
1787 src[0] = ac_to_integer(&ctx->ac, src[0]);
1788 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1789 break;
1790 case nir_op_f2f64:
1791 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1792 break;
1793 case nir_op_f2f32:
1794 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1795 break;
1796 case nir_op_u2u32:
1797 case nir_op_u2u64:
1798 src[0] = ac_to_integer(&ctx->ac, src[0]);
1799 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1800 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1801 else
1802 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1803 break;
1804 case nir_op_i2i32:
1805 case nir_op_i2i64:
1806 src[0] = ac_to_integer(&ctx->ac, src[0]);
1807 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1808 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1809 else
1810 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1811 break;
1812 case nir_op_bcsel:
1813 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1814 break;
1815 case nir_op_find_lsb:
1816 src[0] = ac_to_integer(&ctx->ac, src[0]);
1817 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1818 break;
1819 case nir_op_ufind_msb:
1820 src[0] = ac_to_integer(&ctx->ac, src[0]);
1821 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1822 break;
1823 case nir_op_ifind_msb:
1824 src[0] = ac_to_integer(&ctx->ac, src[0]);
1825 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1826 break;
1827 case nir_op_uadd_carry:
1828 src[0] = ac_to_integer(&ctx->ac, src[0]);
1829 src[1] = ac_to_integer(&ctx->ac, src[1]);
1830 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1831 break;
1832 case nir_op_usub_borrow:
1833 src[0] = ac_to_integer(&ctx->ac, src[0]);
1834 src[1] = ac_to_integer(&ctx->ac, src[1]);
1835 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1836 break;
1837 case nir_op_b2f:
1838 result = emit_b2f(&ctx->ac, src[0]);
1839 break;
1840 case nir_op_f2b:
1841 result = emit_f2b(&ctx->ac, src[0]);
1842 break;
1843 case nir_op_b2i:
1844 result = emit_b2i(&ctx->ac, src[0]);
1845 break;
1846 case nir_op_i2b:
1847 src[0] = ac_to_integer(&ctx->ac, src[0]);
1848 result = emit_i2b(&ctx->ac, src[0]);
1849 break;
1850 case nir_op_fquantize2f16:
1851 result = emit_f2f16(ctx->nctx, src[0]);
1852 break;
1853 case nir_op_umul_high:
1854 src[0] = ac_to_integer(&ctx->ac, src[0]);
1855 src[1] = ac_to_integer(&ctx->ac, src[1]);
1856 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1857 break;
1858 case nir_op_imul_high:
1859 src[0] = ac_to_integer(&ctx->ac, src[0]);
1860 src[1] = ac_to_integer(&ctx->ac, src[1]);
1861 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1862 break;
1863 case nir_op_pack_half_2x16:
1864 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1865 break;
1866 case nir_op_unpack_half_2x16:
1867 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1868 break;
1869 case nir_op_fddx:
1870 case nir_op_fddy:
1871 case nir_op_fddx_fine:
1872 case nir_op_fddy_fine:
1873 case nir_op_fddx_coarse:
1874 case nir_op_fddy_coarse:
1875 result = emit_ddxy(ctx, instr->op, src[0]);
1876 break;
1877
1878 case nir_op_unpack_64_2x32_split_x: {
1879 assert(instr->src[0].src.ssa->num_components == 1);
1880 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1881 ctx->ac.v2i32,
1882 "");
1883 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1884 ctx->ac.i32_0, "");
1885 break;
1886 }
1887
1888 case nir_op_unpack_64_2x32_split_y: {
1889 assert(instr->src[0].src.ssa->num_components == 1);
1890 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1891 ctx->ac.v2i32,
1892 "");
1893 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1894 ctx->ac.i32_1, "");
1895 break;
1896 }
1897
1898 case nir_op_pack_64_2x32_split: {
1899 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1900 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1901 src[0], ctx->ac.i32_0, "");
1902 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1903 src[1], ctx->ac.i32_1, "");
1904 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1905 break;
1906 }
1907
1908 default:
1909 fprintf(stderr, "Unknown NIR alu instr: ");
1910 nir_print_instr(&instr->instr, stderr);
1911 fprintf(stderr, "\n");
1912 abort();
1913 }
1914
1915 if (result) {
1916 assert(instr->dest.dest.is_ssa);
1917 result = ac_to_integer(&ctx->ac, result);
1918 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1919 result);
1920 }
1921 }
1922
1923 static void visit_load_const(struct ac_nir_context *ctx,
1924 const nir_load_const_instr *instr)
1925 {
1926 LLVMValueRef values[4], value = NULL;
1927 LLVMTypeRef element_type =
1928 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1929
1930 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1931 switch (instr->def.bit_size) {
1932 case 32:
1933 values[i] = LLVMConstInt(element_type,
1934 instr->value.u32[i], false);
1935 break;
1936 case 64:
1937 values[i] = LLVMConstInt(element_type,
1938 instr->value.u64[i], false);
1939 break;
1940 default:
1941 fprintf(stderr,
1942 "unsupported nir load_const bit_size: %d\n",
1943 instr->def.bit_size);
1944 abort();
1945 }
1946 }
1947 if (instr->def.num_components > 1) {
1948 value = LLVMConstVector(values, instr->def.num_components);
1949 } else
1950 value = values[0];
1951
1952 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1953 }
1954
1955 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1956 LLVMTypeRef type)
1957 {
1958 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1959 return LLVMBuildBitCast(ctx->builder, ptr,
1960 LLVMPointerType(type, addr_space), "");
1961 }
1962
1963 static LLVMValueRef
1964 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1965 {
1966 LLVMValueRef size =
1967 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1968 LLVMConstInt(ctx->ac.i32, 2, false), "");
1969
1970 /* VI only */
1971 if (ctx->ac.chip_class == VI && in_elements) {
1972 /* On VI, the descriptor contains the size in bytes,
1973 * but TXQ must return the size in elements.
1974 * The stride is always non-zero for resources using TXQ.
1975 */
1976 LLVMValueRef stride =
1977 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1978 LLVMConstInt(ctx->ac.i32, 1, false), "");
1979 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1980 LLVMConstInt(ctx->ac.i32, 16, false), "");
1981 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1982 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1983
1984 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1985 }
1986 return size;
1987 }
1988
1989 /**
1990 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1991 * intrinsic names).
1992 */
1993 static void build_int_type_name(
1994 LLVMTypeRef type,
1995 char *buf, unsigned bufsize)
1996 {
1997 assert(bufsize >= 6);
1998
1999 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2000 snprintf(buf, bufsize, "v%ui32",
2001 LLVMGetVectorSize(type));
2002 else
2003 strcpy(buf, "i32");
2004 }
2005
2006 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2007 struct ac_image_args *args,
2008 const nir_tex_instr *instr)
2009 {
2010 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2011 LLVMValueRef coord = args->addr;
2012 LLVMValueRef half_texel[2];
2013 LLVMValueRef compare_cube_wa = NULL;
2014 LLVMValueRef result;
2015 int c;
2016 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2017
2018 //TODO Rect
2019 {
2020 struct ac_image_args txq_args = { 0 };
2021
2022 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2023 txq_args.opcode = ac_image_get_resinfo;
2024 txq_args.dmask = 0xf;
2025 txq_args.addr = ctx->i32_0;
2026 txq_args.resource = args->resource;
2027 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2028
2029 for (c = 0; c < 2; c++) {
2030 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2031 LLVMConstInt(ctx->i32, c, false), "");
2032 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2033 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2034 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2035 LLVMConstReal(ctx->f32, -0.5), "");
2036 }
2037 }
2038
2039 LLVMValueRef orig_coords = args->addr;
2040
2041 for (c = 0; c < 2; c++) {
2042 LLVMValueRef tmp;
2043 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2044 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2045 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2046 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2047 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2048 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2049 }
2050
2051
2052 /*
2053 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2054 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2055 * workaround by sampling using a scaled type and converting.
2056 * This is taken from amdgpu-pro shaders.
2057 */
2058 /* NOTE this produces some ugly code compared to amdgpu-pro,
2059 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2060 * and then reads them back. -pro generates two selects,
2061 * one s_cmp for the descriptor rewriting
2062 * one v_cmp for the coordinate and result changes.
2063 */
2064 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2065 LLVMValueRef tmp, tmp2;
2066
2067 /* workaround 8/8/8/8 uint/sint cube gather bug */
2068 /* first detect it then change to a scaled read and f2i */
2069 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2070 tmp2 = tmp;
2071
2072 /* extract the DATA_FORMAT */
2073 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2074 LLVMConstInt(ctx->i32, 6, false), false);
2075
2076 /* is the DATA_FORMAT == 8_8_8_8 */
2077 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2078
2079 if (stype == GLSL_TYPE_UINT)
2080 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2081 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2082 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2083 else
2084 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2085 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2086 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2087
2088 /* replace the NUM FORMAT in the descriptor */
2089 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2090 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2091
2092 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2093
2094 /* don't modify the coordinates for this case */
2095 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2096 }
2097 args->addr = coord;
2098 result = ac_build_image_opcode(ctx, args);
2099
2100 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2101 LLVMValueRef tmp, tmp2;
2102
2103 /* if the cube workaround is in place, f2i the result. */
2104 for (c = 0; c < 4; c++) {
2105 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2106 if (stype == GLSL_TYPE_UINT)
2107 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2108 else
2109 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2110 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2111 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2112 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2113 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2114 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2115 }
2116 }
2117 return result;
2118 }
2119
2120 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2121 const nir_tex_instr *instr,
2122 bool lod_is_zero,
2123 struct ac_image_args *args)
2124 {
2125 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2126 return ac_build_buffer_load_format(&ctx->ac,
2127 args->resource,
2128 args->addr,
2129 LLVMConstInt(ctx->ac.i32, 0, false),
2130 true);
2131 }
2132
2133 args->opcode = ac_image_sample;
2134 args->compare = instr->is_shadow;
2135
2136 switch (instr->op) {
2137 case nir_texop_txf:
2138 case nir_texop_txf_ms:
2139 case nir_texop_samples_identical:
2140 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2141 args->compare = false;
2142 args->offset = false;
2143 break;
2144 case nir_texop_txb:
2145 args->bias = true;
2146 break;
2147 case nir_texop_txl:
2148 if (lod_is_zero)
2149 args->level_zero = true;
2150 else
2151 args->lod = true;
2152 break;
2153 case nir_texop_txs:
2154 case nir_texop_query_levels:
2155 args->opcode = ac_image_get_resinfo;
2156 break;
2157 case nir_texop_tex:
2158 if (ctx->stage != MESA_SHADER_FRAGMENT)
2159 args->level_zero = true;
2160 break;
2161 case nir_texop_txd:
2162 args->deriv = true;
2163 break;
2164 case nir_texop_tg4:
2165 args->opcode = ac_image_gather4;
2166 args->level_zero = true;
2167 break;
2168 case nir_texop_lod:
2169 args->opcode = ac_image_get_lod;
2170 args->compare = false;
2171 args->offset = false;
2172 break;
2173 default:
2174 break;
2175 }
2176
2177 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2178 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2179 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2180 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2181 }
2182 }
2183 return ac_build_image_opcode(&ctx->ac, args);
2184 }
2185
2186 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2187 nir_intrinsic_instr *instr)
2188 {
2189 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2190 unsigned desc_set = nir_intrinsic_desc_set(instr);
2191 unsigned binding = nir_intrinsic_binding(instr);
2192 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2193 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2194 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2195 unsigned base_offset = layout->binding[binding].offset;
2196 LLVMValueRef offset, stride;
2197
2198 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2199 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2200 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2201 layout->binding[binding].dynamic_offset_offset;
2202 desc_ptr = ctx->push_constants;
2203 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2204 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2205 } else
2206 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2207
2208 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2209 index = LLVMBuildMul(ctx->builder, index, stride, "");
2210 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2211
2212 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2213 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2214 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2215
2216 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2217 }
2218
2219 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2220 nir_intrinsic_instr *instr)
2221 {
2222 LLVMValueRef ptr, addr;
2223
2224 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2225 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2226
2227 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2228 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2229
2230 return LLVMBuildLoad(ctx->builder, ptr, "");
2231 }
2232
2233 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2234 const nir_intrinsic_instr *instr)
2235 {
2236 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2237
2238 return get_buffer_size(ctx, desc, false);
2239 }
2240 static void visit_store_ssbo(struct ac_nir_context *ctx,
2241 nir_intrinsic_instr *instr)
2242 {
2243 const char *store_name;
2244 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2245 LLVMTypeRef data_type = ctx->ac.f32;
2246 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2247 int components_32bit = elem_size_mult * instr->num_components;
2248 unsigned writemask = nir_intrinsic_write_mask(instr);
2249 LLVMValueRef base_data, base_offset;
2250 LLVMValueRef params[6];
2251
2252 params[1] = ctx->abi->load_ssbo(ctx->abi,
2253 get_src(ctx, instr->src[1]), true);
2254 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2255 params[4] = ctx->ac.i1false; /* glc */
2256 params[5] = ctx->ac.i1false; /* slc */
2257
2258 if (components_32bit > 1)
2259 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2260
2261 base_data = ac_to_float(&ctx->ac, src_data);
2262 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2263 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2264 data_type, "");
2265 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2266 while (writemask) {
2267 int start, count;
2268 LLVMValueRef data;
2269 LLVMValueRef offset;
2270 LLVMValueRef tmp;
2271 u_bit_scan_consecutive_range(&writemask, &start, &count);
2272
2273 /* Due to an LLVM limitation, split 3-element writes
2274 * into a 2-element and a 1-element write. */
2275 if (count == 3) {
2276 writemask |= 1 << (start + 2);
2277 count = 2;
2278 }
2279
2280 start *= elem_size_mult;
2281 count *= elem_size_mult;
2282
2283 if (count > 4) {
2284 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2285 count = 4;
2286 }
2287
2288 if (count == 4) {
2289 store_name = "llvm.amdgcn.buffer.store.v4f32";
2290 data = base_data;
2291 } else if (count == 2) {
2292 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2293 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2294 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2295 ctx->ac.i32_0, "");
2296
2297 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2298 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2299 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2300 ctx->ac.i32_1, "");
2301 store_name = "llvm.amdgcn.buffer.store.v2f32";
2302
2303 } else {
2304 assert(count == 1);
2305 if (get_llvm_num_components(base_data) > 1)
2306 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2307 LLVMConstInt(ctx->ac.i32, start, false), "");
2308 else
2309 data = base_data;
2310 store_name = "llvm.amdgcn.buffer.store.f32";
2311 }
2312
2313 offset = base_offset;
2314 if (start != 0) {
2315 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2316 }
2317 params[0] = data;
2318 params[3] = offset;
2319 ac_build_intrinsic(&ctx->ac, store_name,
2320 ctx->ac.voidt, params, 6, 0);
2321 }
2322 }
2323
2324 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2325 const nir_intrinsic_instr *instr)
2326 {
2327 const char *name;
2328 LLVMValueRef params[6];
2329 int arg_count = 0;
2330
2331 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2332 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2333 }
2334 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2335 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2336 get_src(ctx, instr->src[0]),
2337 true);
2338 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2339 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2340 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2341
2342 switch (instr->intrinsic) {
2343 case nir_intrinsic_ssbo_atomic_add:
2344 name = "llvm.amdgcn.buffer.atomic.add";
2345 break;
2346 case nir_intrinsic_ssbo_atomic_imin:
2347 name = "llvm.amdgcn.buffer.atomic.smin";
2348 break;
2349 case nir_intrinsic_ssbo_atomic_umin:
2350 name = "llvm.amdgcn.buffer.atomic.umin";
2351 break;
2352 case nir_intrinsic_ssbo_atomic_imax:
2353 name = "llvm.amdgcn.buffer.atomic.smax";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_umax:
2356 name = "llvm.amdgcn.buffer.atomic.umax";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_and:
2359 name = "llvm.amdgcn.buffer.atomic.and";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_or:
2362 name = "llvm.amdgcn.buffer.atomic.or";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_xor:
2365 name = "llvm.amdgcn.buffer.atomic.xor";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_exchange:
2368 name = "llvm.amdgcn.buffer.atomic.swap";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_comp_swap:
2371 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2372 break;
2373 default:
2374 abort();
2375 }
2376
2377 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2378 }
2379
2380 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2381 const nir_intrinsic_instr *instr)
2382 {
2383 LLVMValueRef results[2];
2384 int load_components;
2385 int num_components = instr->num_components;
2386 if (instr->dest.ssa.bit_size == 64)
2387 num_components *= 2;
2388
2389 for (int i = 0; i < num_components; i += load_components) {
2390 load_components = MIN2(num_components - i, 4);
2391 const char *load_name;
2392 LLVMTypeRef data_type = ctx->ac.f32;
2393 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2394 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2395
2396 if (load_components == 3)
2397 data_type = LLVMVectorType(ctx->ac.f32, 4);
2398 else if (load_components > 1)
2399 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2400
2401 if (load_components >= 3)
2402 load_name = "llvm.amdgcn.buffer.load.v4f32";
2403 else if (load_components == 2)
2404 load_name = "llvm.amdgcn.buffer.load.v2f32";
2405 else if (load_components == 1)
2406 load_name = "llvm.amdgcn.buffer.load.f32";
2407 else
2408 unreachable("unhandled number of components");
2409
2410 LLVMValueRef params[] = {
2411 ctx->abi->load_ssbo(ctx->abi,
2412 get_src(ctx, instr->src[0]),
2413 false),
2414 LLVMConstInt(ctx->ac.i32, 0, false),
2415 offset,
2416 ctx->ac.i1false,
2417 ctx->ac.i1false,
2418 };
2419
2420 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2421
2422 }
2423
2424 assume(results[0]);
2425 LLVMValueRef ret = results[0];
2426 if (num_components > 4 || num_components == 3) {
2427 LLVMValueRef masks[] = {
2428 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2429 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2430 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2431 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2432 };
2433
2434 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2435 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2436 results[num_components > 4 ? 1 : 0], swizzle, "");
2437 }
2438
2439 return LLVMBuildBitCast(ctx->ac.builder, ret,
2440 get_def_type(ctx, &instr->dest.ssa), "");
2441 }
2442
2443 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2444 const nir_intrinsic_instr *instr)
2445 {
2446 LLVMValueRef results[8], ret;
2447 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2448 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2449 int num_components = instr->num_components;
2450
2451 if (ctx->abi->load_ubo)
2452 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2453
2454 if (instr->dest.ssa.bit_size == 64)
2455 num_components *= 2;
2456
2457 for (unsigned i = 0; i < num_components; ++i) {
2458 LLVMValueRef params[] = {
2459 rsrc,
2460 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2461 offset, "")
2462 };
2463 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2464 params, 2,
2465 AC_FUNC_ATTR_READNONE |
2466 AC_FUNC_ATTR_LEGACY);
2467 }
2468
2469
2470 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2471 return LLVMBuildBitCast(ctx->ac.builder, ret,
2472 get_def_type(ctx, &instr->dest.ssa), "");
2473 }
2474
2475 static void
2476 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2477 bool vs_in, unsigned *vertex_index_out,
2478 LLVMValueRef *vertex_index_ref,
2479 unsigned *const_out, LLVMValueRef *indir_out)
2480 {
2481 unsigned const_offset = 0;
2482 nir_deref *tail = &deref->deref;
2483 LLVMValueRef offset = NULL;
2484
2485 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2486 tail = tail->child;
2487 nir_deref_array *deref_array = nir_deref_as_array(tail);
2488 if (vertex_index_out)
2489 *vertex_index_out = deref_array->base_offset;
2490
2491 if (vertex_index_ref) {
2492 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2493 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2494 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2495 }
2496 *vertex_index_ref = vtx;
2497 }
2498 }
2499
2500 if (deref->var->data.compact) {
2501 assert(tail->child->deref_type == nir_deref_type_array);
2502 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2503 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2504 /* We always lower indirect dereferences for "compact" array vars. */
2505 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2506
2507 const_offset = deref_array->base_offset;
2508 goto out;
2509 }
2510
2511 while (tail->child != NULL) {
2512 const struct glsl_type *parent_type = tail->type;
2513 tail = tail->child;
2514
2515 if (tail->deref_type == nir_deref_type_array) {
2516 nir_deref_array *deref_array = nir_deref_as_array(tail);
2517 LLVMValueRef index, stride, local_offset;
2518 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2519
2520 const_offset += size * deref_array->base_offset;
2521 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2522 continue;
2523
2524 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2525 index = get_src(ctx, deref_array->indirect);
2526 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2527 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2528
2529 if (offset)
2530 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2531 else
2532 offset = local_offset;
2533 } else if (tail->deref_type == nir_deref_type_struct) {
2534 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2535
2536 for (unsigned i = 0; i < deref_struct->index; i++) {
2537 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2538 const_offset += glsl_count_attribute_slots(ft, vs_in);
2539 }
2540 } else
2541 unreachable("unsupported deref type");
2542
2543 }
2544 out:
2545 if (const_offset && offset)
2546 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2547 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2548 "");
2549
2550 *const_out = const_offset;
2551 *indir_out = offset;
2552 }
2553
2554
2555 /* The offchip buffer layout for TCS->TES is
2556 *
2557 * - attribute 0 of patch 0 vertex 0
2558 * - attribute 0 of patch 0 vertex 1
2559 * - attribute 0 of patch 0 vertex 2
2560 * ...
2561 * - attribute 0 of patch 1 vertex 0
2562 * - attribute 0 of patch 1 vertex 1
2563 * ...
2564 * - attribute 1 of patch 0 vertex 0
2565 * - attribute 1 of patch 0 vertex 1
2566 * ...
2567 * - per patch attribute 0 of patch 0
2568 * - per patch attribute 0 of patch 1
2569 * ...
2570 *
2571 * Note that every attribute has 4 components.
2572 */
2573 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2574 LLVMValueRef vertex_index,
2575 LLVMValueRef param_index)
2576 {
2577 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2578 LLVMValueRef param_stride, constant16;
2579 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2580
2581 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2582 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2583 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2584 num_patches, "");
2585
2586 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2587 if (vertex_index) {
2588 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2589 vertices_per_patch, "");
2590
2591 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2592 vertex_index, "");
2593
2594 param_stride = total_vertices;
2595 } else {
2596 base_addr = rel_patch_id;
2597 param_stride = num_patches;
2598 }
2599
2600 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2601 LLVMBuildMul(ctx->builder, param_index,
2602 param_stride, ""), "");
2603
2604 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2605
2606 if (!vertex_index) {
2607 LLVMValueRef patch_data_offset =
2608 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2609
2610 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2611 patch_data_offset, "");
2612 }
2613 return base_addr;
2614 }
2615
2616 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2617 unsigned param,
2618 unsigned const_index,
2619 bool is_compact,
2620 LLVMValueRef vertex_index,
2621 LLVMValueRef indir_index)
2622 {
2623 LLVMValueRef param_index;
2624
2625 if (indir_index)
2626 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2627 indir_index, "");
2628 else {
2629 if (const_index && !is_compact)
2630 param += const_index;
2631 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2632 }
2633 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2634 }
2635
2636 static void
2637 mark_tess_output(struct nir_to_llvm_context *ctx,
2638 bool is_patch, uint32_t param)
2639
2640 {
2641 if (is_patch) {
2642 ctx->tess_patch_outputs_written |= (1ull << param);
2643 } else
2644 ctx->tess_outputs_written |= (1ull << param);
2645 }
2646
2647 static LLVMValueRef
2648 get_dw_address(struct nir_to_llvm_context *ctx,
2649 LLVMValueRef dw_addr,
2650 unsigned param,
2651 unsigned const_index,
2652 bool compact_const_index,
2653 LLVMValueRef vertex_index,
2654 LLVMValueRef stride,
2655 LLVMValueRef indir_index)
2656
2657 {
2658
2659 if (vertex_index) {
2660 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2661 LLVMBuildMul(ctx->builder,
2662 vertex_index,
2663 stride, ""), "");
2664 }
2665
2666 if (indir_index)
2667 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2668 LLVMBuildMul(ctx->builder, indir_index,
2669 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2670 else if (const_index && !compact_const_index)
2671 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2672 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2673
2674 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2675 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2676
2677 if (const_index && compact_const_index)
2678 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2679 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2680 return dw_addr;
2681 }
2682
2683 static LLVMValueRef
2684 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2685 unsigned value_count, unsigned component)
2686 {
2687 LLVMValueRef vec = NULL;
2688
2689 if (value_count == 1) {
2690 return values[component];
2691 } else if (!value_count)
2692 unreachable("value_count is 0");
2693
2694 for (unsigned i = component; i < value_count + component; i++) {
2695 LLVMValueRef value = values[i];
2696
2697 if (!i)
2698 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2699 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2700 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2701 }
2702 return vec;
2703 }
2704
2705 static LLVMValueRef
2706 load_tcs_input(struct nir_to_llvm_context *ctx,
2707 nir_intrinsic_instr *instr)
2708 {
2709 LLVMValueRef dw_addr, stride;
2710 unsigned const_index;
2711 LLVMValueRef vertex_index;
2712 LLVMValueRef indir_index;
2713 unsigned param;
2714 LLVMValueRef value[4], result;
2715 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2716 const bool is_compact = instr->variables[0]->var->data.compact;
2717 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2718 get_deref_offset(ctx->nir, instr->variables[0],
2719 false, NULL, per_vertex ? &vertex_index : NULL,
2720 &const_index, &indir_index);
2721
2722 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2723 dw_addr = get_tcs_in_current_patch_offset(ctx);
2724 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2725 indir_index);
2726
2727 unsigned comp = instr->variables[0]->var->data.location_frac;
2728 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2729 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2730 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2731 ctx->ac.i32_1, "");
2732 }
2733 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2734 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2735 return result;
2736 }
2737
2738 static LLVMValueRef
2739 load_tcs_output(struct nir_to_llvm_context *ctx,
2740 nir_intrinsic_instr *instr)
2741 {
2742 LLVMValueRef dw_addr;
2743 LLVMValueRef stride = NULL;
2744 LLVMValueRef value[4], result;
2745 LLVMValueRef vertex_index = NULL;
2746 LLVMValueRef indir_index = NULL;
2747 unsigned const_index = 0;
2748 unsigned param;
2749 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2750 const bool is_compact = instr->variables[0]->var->data.compact;
2751 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2752 get_deref_offset(ctx->nir, instr->variables[0],
2753 false, NULL, per_vertex ? &vertex_index : NULL,
2754 &const_index, &indir_index);
2755
2756 if (!instr->variables[0]->var->data.patch) {
2757 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2758 dw_addr = get_tcs_out_current_patch_offset(ctx);
2759 } else {
2760 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2761 }
2762
2763 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2764 indir_index);
2765
2766 unsigned comp = instr->variables[0]->var->data.location_frac;
2767 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2768 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2769 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2770 ctx->ac.i32_1, "");
2771 }
2772 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2773 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2774 return result;
2775 }
2776
2777 static void
2778 store_tcs_output(struct nir_to_llvm_context *ctx,
2779 nir_intrinsic_instr *instr,
2780 LLVMValueRef src,
2781 unsigned writemask)
2782 {
2783 LLVMValueRef dw_addr;
2784 LLVMValueRef stride = NULL;
2785 LLVMValueRef buf_addr = NULL;
2786 LLVMValueRef vertex_index = NULL;
2787 LLVMValueRef indir_index = NULL;
2788 unsigned const_index = 0;
2789 unsigned param;
2790 const unsigned comp = instr->variables[0]->var->data.location_frac;
2791 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2792 const bool is_compact = instr->variables[0]->var->data.compact;
2793
2794 get_deref_offset(ctx->nir, instr->variables[0],
2795 false, NULL, per_vertex ? &vertex_index : NULL,
2796 &const_index, &indir_index);
2797
2798 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2799 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2800 is_compact && const_index > 3) {
2801 const_index -= 3;
2802 param++;
2803 }
2804
2805 if (!instr->variables[0]->var->data.patch) {
2806 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2807 dw_addr = get_tcs_out_current_patch_offset(ctx);
2808 } else {
2809 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2810 }
2811
2812 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2813
2814 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2815 indir_index);
2816 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2817 vertex_index, indir_index);
2818
2819 bool is_tess_factor = false;
2820 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2821 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2822 is_tess_factor = true;
2823
2824 unsigned base = is_compact ? const_index : 0;
2825 for (unsigned chan = 0; chan < 8; chan++) {
2826 if (!(writemask & (1 << chan)))
2827 continue;
2828 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2829
2830 ac_lds_store(&ctx->ac, dw_addr, value);
2831
2832 if (!is_tess_factor && writemask != 0xF)
2833 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2834 buf_addr, ctx->oc_lds,
2835 4 * (base + chan), 1, 0, true, false);
2836
2837 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2838 ctx->ac.i32_1, "");
2839 }
2840
2841 if (writemask == 0xF) {
2842 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2843 buf_addr, ctx->oc_lds,
2844 (base * 4), 1, 0, true, false);
2845 }
2846 }
2847
2848 static LLVMValueRef
2849 load_tes_input(struct nir_to_llvm_context *ctx,
2850 const nir_intrinsic_instr *instr)
2851 {
2852 LLVMValueRef buf_addr;
2853 LLVMValueRef result;
2854 LLVMValueRef vertex_index = NULL;
2855 LLVMValueRef indir_index = NULL;
2856 unsigned const_index = 0;
2857 unsigned param;
2858 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2859 const bool is_compact = instr->variables[0]->var->data.compact;
2860
2861 get_deref_offset(ctx->nir, instr->variables[0],
2862 false, NULL, per_vertex ? &vertex_index : NULL,
2863 &const_index, &indir_index);
2864 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2865 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2866 is_compact && const_index > 3) {
2867 const_index -= 3;
2868 param++;
2869 }
2870
2871 unsigned comp = instr->variables[0]->var->data.location_frac;
2872 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2873 is_compact, vertex_index, indir_index);
2874
2875 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2876 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2877
2878 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2879 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2880 result = trim_vector(&ctx->ac, result, instr->num_components);
2881 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2882 return result;
2883 }
2884
2885 static LLVMValueRef
2886 load_gs_input(struct nir_to_llvm_context *ctx,
2887 nir_intrinsic_instr *instr)
2888 {
2889 LLVMValueRef indir_index, vtx_offset;
2890 unsigned const_index;
2891 LLVMValueRef args[9];
2892 unsigned param, vtx_offset_param;
2893 LLVMValueRef value[4], result;
2894 unsigned vertex_index;
2895 get_deref_offset(ctx->nir, instr->variables[0],
2896 false, &vertex_index, NULL,
2897 &const_index, &indir_index);
2898 vtx_offset_param = vertex_index;
2899 assert(vtx_offset_param < 6);
2900 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2901 LLVMConstInt(ctx->ac.i32, 4, false), "");
2902
2903 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2904
2905 unsigned comp = instr->variables[0]->var->data.location_frac;
2906 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2907 if (ctx->ac.chip_class >= GFX9) {
2908 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2909 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2910 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2911 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2912 } else {
2913 args[0] = ctx->esgs_ring;
2914 args[1] = vtx_offset;
2915 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2916 args[3] = ctx->ac.i32_0;
2917 args[4] = ctx->ac.i32_1; /* OFFEN */
2918 args[5] = ctx->ac.i32_0; /* IDXEN */
2919 args[6] = ctx->ac.i32_1; /* GLC */
2920 args[7] = ctx->ac.i32_0; /* SLC */
2921 args[8] = ctx->ac.i32_0; /* TFE */
2922
2923 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2924 ctx->ac.i32, args, 9,
2925 AC_FUNC_ATTR_READONLY |
2926 AC_FUNC_ATTR_LEGACY);
2927 }
2928 }
2929 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2930
2931 return result;
2932 }
2933
2934 static LLVMValueRef
2935 build_gep_for_deref(struct ac_nir_context *ctx,
2936 nir_deref_var *deref)
2937 {
2938 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2939 assert(entry->data);
2940 LLVMValueRef val = entry->data;
2941 nir_deref *tail = deref->deref.child;
2942 while (tail != NULL) {
2943 LLVMValueRef offset;
2944 switch (tail->deref_type) {
2945 case nir_deref_type_array: {
2946 nir_deref_array *array = nir_deref_as_array(tail);
2947 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2948 if (array->deref_array_type ==
2949 nir_deref_array_type_indirect) {
2950 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2951 get_src(ctx,
2952 array->indirect),
2953 "");
2954 }
2955 break;
2956 }
2957 case nir_deref_type_struct: {
2958 nir_deref_struct *deref_struct =
2959 nir_deref_as_struct(tail);
2960 offset = LLVMConstInt(ctx->ac.i32,
2961 deref_struct->index, 0);
2962 break;
2963 }
2964 default:
2965 unreachable("bad deref type");
2966 }
2967 val = ac_build_gep0(&ctx->ac, val, offset);
2968 tail = tail->child;
2969 }
2970 return val;
2971 }
2972
2973 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2974 nir_intrinsic_instr *instr)
2975 {
2976 LLVMValueRef values[8];
2977 int idx = instr->variables[0]->var->data.driver_location;
2978 int ve = instr->dest.ssa.num_components;
2979 unsigned comp = instr->variables[0]->var->data.location_frac;
2980 LLVMValueRef indir_index;
2981 LLVMValueRef ret;
2982 unsigned const_index;
2983 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2984 instr->variables[0]->var->data.mode == nir_var_shader_in;
2985 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2986 &const_index, &indir_index);
2987
2988 if (instr->dest.ssa.bit_size == 64)
2989 ve *= 2;
2990
2991 switch (instr->variables[0]->var->data.mode) {
2992 case nir_var_shader_in:
2993 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2994 return load_tcs_input(ctx->nctx, instr);
2995 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2996 return load_tes_input(ctx->nctx, instr);
2997 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2998 return load_gs_input(ctx->nctx, instr);
2999 }
3000
3001 for (unsigned chan = comp; chan < ve + comp; chan++) {
3002 if (indir_index) {
3003 unsigned count = glsl_count_attribute_slots(
3004 instr->variables[0]->var->type,
3005 ctx->stage == MESA_SHADER_VERTEX);
3006 count -= chan / 4;
3007 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3008 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3009 4, false, true);
3010
3011 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3012 tmp_vec,
3013 indir_index, "");
3014 } else
3015 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3016 }
3017 break;
3018 case nir_var_local:
3019 for (unsigned chan = 0; chan < ve; chan++) {
3020 if (indir_index) {
3021 unsigned count = glsl_count_attribute_slots(
3022 instr->variables[0]->var->type, false);
3023 count -= chan / 4;
3024 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3025 &ctx->ac, ctx->locals + idx + chan, count,
3026 4, true, true);
3027
3028 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3029 tmp_vec,
3030 indir_index, "");
3031 } else {
3032 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3033 }
3034 }
3035 break;
3036 case nir_var_shared: {
3037 LLVMValueRef address = build_gep_for_deref(ctx,
3038 instr->variables[0]);
3039 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3040 return LLVMBuildBitCast(ctx->ac.builder, val,
3041 get_def_type(ctx, &instr->dest.ssa),
3042 "");
3043 }
3044 case nir_var_shader_out:
3045 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3046 return load_tcs_output(ctx->nctx, instr);
3047
3048 for (unsigned chan = comp; chan < ve + comp; chan++) {
3049 if (indir_index) {
3050 unsigned count = glsl_count_attribute_slots(
3051 instr->variables[0]->var->type, false);
3052 count -= chan / 4;
3053 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3054 &ctx->ac, ctx->outputs + idx + chan, count,
3055 4, true, true);
3056
3057 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3058 tmp_vec,
3059 indir_index, "");
3060 } else {
3061 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3062 ctx->outputs[idx + chan + const_index * 4],
3063 "");
3064 }
3065 }
3066 break;
3067 default:
3068 unreachable("unhandle variable mode");
3069 }
3070 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3071 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3072 }
3073
3074 static void
3075 visit_store_var(struct ac_nir_context *ctx,
3076 nir_intrinsic_instr *instr)
3077 {
3078 LLVMValueRef temp_ptr, value;
3079 int idx = instr->variables[0]->var->data.driver_location;
3080 unsigned comp = instr->variables[0]->var->data.location_frac;
3081 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3082 int writemask = instr->const_index[0] << comp;
3083 LLVMValueRef indir_index;
3084 unsigned const_index;
3085 get_deref_offset(ctx, instr->variables[0], false,
3086 NULL, NULL, &const_index, &indir_index);
3087
3088 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3089 int old_writemask = writemask;
3090
3091 src = LLVMBuildBitCast(ctx->ac.builder, src,
3092 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3093 "");
3094
3095 writemask = 0;
3096 for (unsigned chan = 0; chan < 4; chan++) {
3097 if (old_writemask & (1 << chan))
3098 writemask |= 3u << (2 * chan);
3099 }
3100 }
3101
3102 switch (instr->variables[0]->var->data.mode) {
3103 case nir_var_shader_out:
3104
3105 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3106 store_tcs_output(ctx->nctx, instr, src, writemask);
3107 return;
3108 }
3109
3110 for (unsigned chan = 0; chan < 8; chan++) {
3111 int stride = 4;
3112 if (!(writemask & (1 << chan)))
3113 continue;
3114
3115 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3116
3117 if (instr->variables[0]->var->data.compact)
3118 stride = 1;
3119 if (indir_index) {
3120 unsigned count = glsl_count_attribute_slots(
3121 instr->variables[0]->var->type, false);
3122 count -= chan / 4;
3123 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3124 &ctx->ac, ctx->outputs + idx + chan, count,
3125 stride, true, true);
3126
3127 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3128 value, indir_index, "");
3129 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3130 count, stride, tmp_vec);
3131
3132 } else {
3133 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3134
3135 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3136 }
3137 }
3138 break;
3139 case nir_var_local:
3140 for (unsigned chan = 0; chan < 8; chan++) {
3141 if (!(writemask & (1 << chan)))
3142 continue;
3143
3144 value = llvm_extract_elem(&ctx->ac, src, chan);
3145 if (indir_index) {
3146 unsigned count = glsl_count_attribute_slots(
3147 instr->variables[0]->var->type, false);
3148 count -= chan / 4;
3149 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3150 &ctx->ac, ctx->locals + idx + chan, count,
3151 4, true, true);
3152
3153 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3154 value, indir_index, "");
3155 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3156 count, 4, tmp_vec);
3157 } else {
3158 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3159
3160 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3161 }
3162 }
3163 break;
3164 case nir_var_shared: {
3165 int writemask = instr->const_index[0];
3166 LLVMValueRef address = build_gep_for_deref(ctx,
3167 instr->variables[0]);
3168 LLVMValueRef val = get_src(ctx, instr->src[0]);
3169 unsigned components =
3170 glsl_get_vector_elements(
3171 nir_deref_tail(&instr->variables[0]->deref)->type);
3172 if (writemask == (1 << components) - 1) {
3173 val = LLVMBuildBitCast(
3174 ctx->ac.builder, val,
3175 LLVMGetElementType(LLVMTypeOf(address)), "");
3176 LLVMBuildStore(ctx->ac.builder, val, address);
3177 } else {
3178 for (unsigned chan = 0; chan < 4; chan++) {
3179 if (!(writemask & (1 << chan)))
3180 continue;
3181 LLVMValueRef ptr =
3182 LLVMBuildStructGEP(ctx->ac.builder,
3183 address, chan, "");
3184 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3185 chan);
3186 src = LLVMBuildBitCast(
3187 ctx->ac.builder, src,
3188 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3189 LLVMBuildStore(ctx->ac.builder, src, ptr);
3190 }
3191 }
3192 break;
3193 }
3194 default:
3195 break;
3196 }
3197 }
3198
3199 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3200 {
3201 switch (dim) {
3202 case GLSL_SAMPLER_DIM_BUF:
3203 return 1;
3204 case GLSL_SAMPLER_DIM_1D:
3205 return array ? 2 : 1;
3206 case GLSL_SAMPLER_DIM_2D:
3207 return array ? 3 : 2;
3208 case GLSL_SAMPLER_DIM_MS:
3209 return array ? 4 : 3;
3210 case GLSL_SAMPLER_DIM_3D:
3211 case GLSL_SAMPLER_DIM_CUBE:
3212 return 3;
3213 case GLSL_SAMPLER_DIM_RECT:
3214 case GLSL_SAMPLER_DIM_SUBPASS:
3215 return 2;
3216 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3217 return 3;
3218 default:
3219 break;
3220 }
3221 return 0;
3222 }
3223
3224
3225
3226 /* Adjust the sample index according to FMASK.
3227 *
3228 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3229 * which is the identity mapping. Each nibble says which physical sample
3230 * should be fetched to get that sample.
3231 *
3232 * For example, 0x11111100 means there are only 2 samples stored and
3233 * the second sample covers 3/4 of the pixel. When reading samples 0
3234 * and 1, return physical sample 0 (determined by the first two 0s
3235 * in FMASK), otherwise return physical sample 1.
3236 *
3237 * The sample index should be adjusted as follows:
3238 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3239 */
3240 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3241 LLVMValueRef coord_x, LLVMValueRef coord_y,
3242 LLVMValueRef coord_z,
3243 LLVMValueRef sample_index,
3244 LLVMValueRef fmask_desc_ptr)
3245 {
3246 LLVMValueRef fmask_load_address[4];
3247 LLVMValueRef res;
3248
3249 fmask_load_address[0] = coord_x;
3250 fmask_load_address[1] = coord_y;
3251 if (coord_z) {
3252 fmask_load_address[2] = coord_z;
3253 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3254 }
3255
3256 struct ac_image_args args = {0};
3257
3258 args.opcode = ac_image_load;
3259 args.da = coord_z ? true : false;
3260 args.resource = fmask_desc_ptr;
3261 args.dmask = 0xf;
3262 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3263
3264 res = ac_build_image_opcode(ctx, &args);
3265
3266 res = ac_to_integer(ctx, res);
3267 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3268 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3269
3270 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3271 res,
3272 ctx->i32_0, "");
3273
3274 LLVMValueRef sample_index4 =
3275 LLVMBuildMul(ctx->builder, sample_index, four, "");
3276 LLVMValueRef shifted_fmask =
3277 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3278 LLVMValueRef final_sample =
3279 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3280
3281 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3282 * resource descriptor is 0 (invalid),
3283 */
3284 LLVMValueRef fmask_desc =
3285 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3286 ctx->v8i32, "");
3287
3288 LLVMValueRef fmask_word1 =
3289 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3290 ctx->i32_1, "");
3291
3292 LLVMValueRef word1_is_nonzero =
3293 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3294 fmask_word1, ctx->i32_0, "");
3295
3296 /* Replace the MSAA sample index. */
3297 sample_index =
3298 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3299 final_sample, sample_index, "");
3300 return sample_index;
3301 }
3302
3303 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3304 const nir_intrinsic_instr *instr)
3305 {
3306 const struct glsl_type *type = instr->variables[0]->var->type;
3307 if(instr->variables[0]->deref.child)
3308 type = instr->variables[0]->deref.child->type;
3309
3310 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3311 LLVMValueRef coords[4];
3312 LLVMValueRef masks[] = {
3313 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3314 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3315 };
3316 LLVMValueRef res;
3317 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3318
3319 int count;
3320 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3321 bool is_array = glsl_sampler_type_is_array(type);
3322 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3323 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3324 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3325 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3326 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3327 count = image_type_to_components_count(dim, is_array);
3328
3329 if (is_ms) {
3330 LLVMValueRef fmask_load_address[3];
3331 int chan;
3332
3333 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3334 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3335 if (is_array)
3336 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3337 else
3338 fmask_load_address[2] = NULL;
3339 if (add_frag_pos) {
3340 for (chan = 0; chan < 2; ++chan)
3341 fmask_load_address[chan] =
3342 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3343 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3344 ctx->ac.i32, ""), "");
3345 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3346 }
3347 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3348 fmask_load_address[0],
3349 fmask_load_address[1],
3350 fmask_load_address[2],
3351 sample_index,
3352 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3353 }
3354 if (count == 1 && !gfx9_1d) {
3355 if (instr->src[0].ssa->num_components)
3356 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3357 else
3358 res = src0;
3359 } else {
3360 int chan;
3361 if (is_ms)
3362 count--;
3363 for (chan = 0; chan < count; ++chan) {
3364 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3365 }
3366 if (add_frag_pos) {
3367 for (chan = 0; chan < 2; ++chan)
3368 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3369 ctx->ac.i32, ""), "");
3370 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3371 count++;
3372 }
3373
3374 if (gfx9_1d) {
3375 if (is_array) {
3376 coords[2] = coords[1];
3377 coords[1] = ctx->ac.i32_0;
3378 } else
3379 coords[1] = ctx->ac.i32_0;
3380 count++;
3381 }
3382
3383 if (is_ms) {
3384 coords[count] = sample_index;
3385 count++;
3386 }
3387
3388 if (count == 3) {
3389 coords[3] = LLVMGetUndef(ctx->ac.i32);
3390 count = 4;
3391 }
3392 res = ac_build_gather_values(&ctx->ac, coords, count);
3393 }
3394 return res;
3395 }
3396
3397 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3398 const nir_intrinsic_instr *instr)
3399 {
3400 LLVMValueRef params[7];
3401 LLVMValueRef res;
3402 char intrinsic_name[64];
3403 const nir_variable *var = instr->variables[0]->var;
3404 const struct glsl_type *type = var->type;
3405
3406 if(instr->variables[0]->deref.child)
3407 type = instr->variables[0]->deref.child->type;
3408
3409 type = glsl_without_array(type);
3410 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3411 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3412 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3413 ctx->ac.i32_0, ""); /* vindex */
3414 params[2] = ctx->ac.i32_0; /* voffset */
3415 params[3] = ctx->ac.i1false; /* glc */
3416 params[4] = ctx->ac.i1false; /* slc */
3417 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3418 params, 5, 0);
3419
3420 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3421 res = ac_to_integer(&ctx->ac, res);
3422 } else {
3423 bool is_da = glsl_sampler_type_is_array(type) ||
3424 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3425 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3426 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3427 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3428 LLVMValueRef glc = ctx->ac.i1false;
3429 LLVMValueRef slc = ctx->ac.i1false;
3430
3431 params[0] = get_image_coords(ctx, instr);
3432 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3433 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3434 if (HAVE_LLVM <= 0x0309) {
3435 params[3] = ctx->ac.i1false; /* r128 */
3436 params[4] = da;
3437 params[5] = glc;
3438 params[6] = slc;
3439 } else {
3440 LLVMValueRef lwe = ctx->ac.i1false;
3441 params[3] = glc;
3442 params[4] = slc;
3443 params[5] = lwe;
3444 params[6] = da;
3445 }
3446
3447 ac_get_image_intr_name("llvm.amdgcn.image.load",
3448 ctx->ac.v4f32, /* vdata */
3449 LLVMTypeOf(params[0]), /* coords */
3450 LLVMTypeOf(params[1]), /* rsrc */
3451 intrinsic_name, sizeof(intrinsic_name));
3452
3453 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3454 params, 7, AC_FUNC_ATTR_READONLY);
3455 }
3456 return ac_to_integer(&ctx->ac, res);
3457 }
3458
3459 static void visit_image_store(struct ac_nir_context *ctx,
3460 nir_intrinsic_instr *instr)
3461 {
3462 LLVMValueRef params[8];
3463 char intrinsic_name[64];
3464 const nir_variable *var = instr->variables[0]->var;
3465 const struct glsl_type *type = glsl_without_array(var->type);
3466 LLVMValueRef glc = ctx->ac.i1false;
3467 bool force_glc = ctx->ac.chip_class == SI;
3468 if (force_glc)
3469 glc = ctx->ac.i1true;
3470
3471 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3472 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3473 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3474 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3475 ctx->ac.i32_0, ""); /* vindex */
3476 params[3] = ctx->ac.i32_0; /* voffset */
3477 params[4] = glc; /* glc */
3478 params[5] = ctx->ac.i1false; /* slc */
3479 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3480 params, 6, 0);
3481 } else {
3482 bool is_da = glsl_sampler_type_is_array(type) ||
3483 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3484 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3485 LLVMValueRef slc = ctx->ac.i1false;
3486
3487 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3488 params[1] = get_image_coords(ctx, instr); /* coords */
3489 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3490 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3491 if (HAVE_LLVM <= 0x0309) {
3492 params[4] = ctx->ac.i1false; /* r128 */
3493 params[5] = da;
3494 params[6] = glc;
3495 params[7] = slc;
3496 } else {
3497 LLVMValueRef lwe = ctx->ac.i1false;
3498 params[4] = glc;
3499 params[5] = slc;
3500 params[6] = lwe;
3501 params[7] = da;
3502 }
3503
3504 ac_get_image_intr_name("llvm.amdgcn.image.store",
3505 LLVMTypeOf(params[0]), /* vdata */
3506 LLVMTypeOf(params[1]), /* coords */
3507 LLVMTypeOf(params[2]), /* rsrc */
3508 intrinsic_name, sizeof(intrinsic_name));
3509
3510 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3511 params, 8, 0);
3512 }
3513
3514 }
3515
3516 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3517 const nir_intrinsic_instr *instr)
3518 {
3519 LLVMValueRef params[7];
3520 int param_count = 0;
3521 const nir_variable *var = instr->variables[0]->var;
3522
3523 const char *atomic_name;
3524 char intrinsic_name[41];
3525 const struct glsl_type *type = glsl_without_array(var->type);
3526 MAYBE_UNUSED int length;
3527
3528 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3529
3530 switch (instr->intrinsic) {
3531 case nir_intrinsic_image_atomic_add:
3532 atomic_name = "add";
3533 break;
3534 case nir_intrinsic_image_atomic_min:
3535 atomic_name = is_unsigned ? "umin" : "smin";
3536 break;
3537 case nir_intrinsic_image_atomic_max:
3538 atomic_name = is_unsigned ? "umax" : "smax";
3539 break;
3540 case nir_intrinsic_image_atomic_and:
3541 atomic_name = "and";
3542 break;
3543 case nir_intrinsic_image_atomic_or:
3544 atomic_name = "or";
3545 break;
3546 case nir_intrinsic_image_atomic_xor:
3547 atomic_name = "xor";
3548 break;
3549 case nir_intrinsic_image_atomic_exchange:
3550 atomic_name = "swap";
3551 break;
3552 case nir_intrinsic_image_atomic_comp_swap:
3553 atomic_name = "cmpswap";
3554 break;
3555 default:
3556 abort();
3557 }
3558
3559 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3560 params[param_count++] = get_src(ctx, instr->src[3]);
3561 params[param_count++] = get_src(ctx, instr->src[2]);
3562
3563 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3564 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3565 NULL, true, true);
3566 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3567 ctx->ac.i32_0, ""); /* vindex */
3568 params[param_count++] = ctx->ac.i32_0; /* voffset */
3569 params[param_count++] = ctx->ac.i1false; /* slc */
3570
3571 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3572 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3573 } else {
3574 char coords_type[8];
3575
3576 bool da = glsl_sampler_type_is_array(type) ||
3577 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3578
3579 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3580 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3581 NULL, true, true);
3582 params[param_count++] = ctx->ac.i1false; /* r128 */
3583 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3584 params[param_count++] = ctx->ac.i1false; /* slc */
3585
3586 build_int_type_name(LLVMTypeOf(coords),
3587 coords_type, sizeof(coords_type));
3588
3589 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3590 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3591 }
3592
3593 assert(length < sizeof(intrinsic_name));
3594 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3595 }
3596
3597 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3598 const nir_intrinsic_instr *instr)
3599 {
3600 LLVMValueRef res;
3601 const nir_variable *var = instr->variables[0]->var;
3602 const struct glsl_type *type = instr->variables[0]->var->type;
3603 bool da = glsl_sampler_type_is_array(var->type) ||
3604 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3605 if(instr->variables[0]->deref.child)
3606 type = instr->variables[0]->deref.child->type;
3607
3608 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3609 return get_buffer_size(ctx,
3610 get_sampler_desc(ctx, instr->variables[0],
3611 AC_DESC_BUFFER, NULL, true, false), true);
3612
3613 struct ac_image_args args = { 0 };
3614
3615 args.da = da;
3616 args.dmask = 0xf;
3617 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3618 args.opcode = ac_image_get_resinfo;
3619 args.addr = ctx->ac.i32_0;
3620
3621 res = ac_build_image_opcode(&ctx->ac, &args);
3622
3623 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3624
3625 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3626 glsl_sampler_type_is_array(type)) {
3627 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3628 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3629 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3630 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3631 }
3632 if (ctx->ac.chip_class >= GFX9 &&
3633 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3634 glsl_sampler_type_is_array(type)) {
3635 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3636 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3637 ctx->ac.i32_1, "");
3638
3639 }
3640 return res;
3641 }
3642
3643 #define NOOP_WAITCNT 0xf7f
3644 #define LGKM_CNT 0x07f
3645 #define VM_CNT 0xf70
3646
3647 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3648 unsigned simm16)
3649 {
3650 LLVMValueRef args[1] = {
3651 LLVMConstInt(ctx->ac.i32, simm16, false),
3652 };
3653 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3654 ctx->ac.voidt, args, 1, 0);
3655 }
3656
3657 static void emit_membar(struct nir_to_llvm_context *ctx,
3658 const nir_intrinsic_instr *instr)
3659 {
3660 unsigned waitcnt = NOOP_WAITCNT;
3661
3662 switch (instr->intrinsic) {
3663 case nir_intrinsic_memory_barrier:
3664 case nir_intrinsic_group_memory_barrier:
3665 waitcnt &= VM_CNT & LGKM_CNT;
3666 break;
3667 case nir_intrinsic_memory_barrier_atomic_counter:
3668 case nir_intrinsic_memory_barrier_buffer:
3669 case nir_intrinsic_memory_barrier_image:
3670 waitcnt &= VM_CNT;
3671 break;
3672 case nir_intrinsic_memory_barrier_shared:
3673 waitcnt &= LGKM_CNT;
3674 break;
3675 default:
3676 break;
3677 }
3678 if (waitcnt != NOOP_WAITCNT)
3679 emit_waitcnt(ctx, waitcnt);
3680 }
3681
3682 static void emit_barrier(struct nir_to_llvm_context *ctx)
3683 {
3684 /* SI only (thanks to a hw bug workaround):
3685 * The real barrier instruction isn’t needed, because an entire patch
3686 * always fits into a single wave.
3687 */
3688 if (ctx->options->chip_class == SI &&
3689 ctx->stage == MESA_SHADER_TESS_CTRL) {
3690 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3691 return;
3692 }
3693 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3694 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3695 }
3696
3697 static void emit_discard_if(struct ac_nir_context *ctx,
3698 const nir_intrinsic_instr *instr)
3699 {
3700 LLVMValueRef cond;
3701
3702 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3703 get_src(ctx, instr->src[0]),
3704 ctx->ac.i32_0, "");
3705 ac_build_kill_if_false(&ctx->ac, cond);
3706 }
3707
3708 static LLVMValueRef
3709 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3710 {
3711 LLVMValueRef result;
3712 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3713 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3714 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3715
3716 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3717 }
3718
3719 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3720 const nir_intrinsic_instr *instr)
3721 {
3722 LLVMValueRef ptr, result;
3723 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3724 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3725
3726 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3727 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3728 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3729 ptr, src, src1,
3730 LLVMAtomicOrderingSequentiallyConsistent,
3731 LLVMAtomicOrderingSequentiallyConsistent,
3732 false);
3733 } else {
3734 LLVMAtomicRMWBinOp op;
3735 switch (instr->intrinsic) {
3736 case nir_intrinsic_var_atomic_add:
3737 op = LLVMAtomicRMWBinOpAdd;
3738 break;
3739 case nir_intrinsic_var_atomic_umin:
3740 op = LLVMAtomicRMWBinOpUMin;
3741 break;
3742 case nir_intrinsic_var_atomic_umax:
3743 op = LLVMAtomicRMWBinOpUMax;
3744 break;
3745 case nir_intrinsic_var_atomic_imin:
3746 op = LLVMAtomicRMWBinOpMin;
3747 break;
3748 case nir_intrinsic_var_atomic_imax:
3749 op = LLVMAtomicRMWBinOpMax;
3750 break;
3751 case nir_intrinsic_var_atomic_and:
3752 op = LLVMAtomicRMWBinOpAnd;
3753 break;
3754 case nir_intrinsic_var_atomic_or:
3755 op = LLVMAtomicRMWBinOpOr;
3756 break;
3757 case nir_intrinsic_var_atomic_xor:
3758 op = LLVMAtomicRMWBinOpXor;
3759 break;
3760 case nir_intrinsic_var_atomic_exchange:
3761 op = LLVMAtomicRMWBinOpXchg;
3762 break;
3763 default:
3764 return NULL;
3765 }
3766
3767 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3768 LLVMAtomicOrderingSequentiallyConsistent,
3769 false);
3770 }
3771 return result;
3772 }
3773
3774 #define INTERP_CENTER 0
3775 #define INTERP_CENTROID 1
3776 #define INTERP_SAMPLE 2
3777
3778 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3779 enum glsl_interp_mode interp, unsigned location)
3780 {
3781 switch (interp) {
3782 case INTERP_MODE_FLAT:
3783 default:
3784 return NULL;
3785 case INTERP_MODE_SMOOTH:
3786 case INTERP_MODE_NONE:
3787 if (location == INTERP_CENTER)
3788 return ctx->persp_center;
3789 else if (location == INTERP_CENTROID)
3790 return ctx->persp_centroid;
3791 else if (location == INTERP_SAMPLE)
3792 return ctx->persp_sample;
3793 break;
3794 case INTERP_MODE_NOPERSPECTIVE:
3795 if (location == INTERP_CENTER)
3796 return ctx->linear_center;
3797 else if (location == INTERP_CENTROID)
3798 return ctx->linear_centroid;
3799 else if (location == INTERP_SAMPLE)
3800 return ctx->linear_sample;
3801 break;
3802 }
3803 return NULL;
3804 }
3805
3806 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3807 LLVMValueRef sample_id)
3808 {
3809 LLVMValueRef result;
3810 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3811
3812 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3813 const_array(ctx->ac.v2f32, 64), "");
3814
3815 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3816 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3817
3818 return result;
3819 }
3820
3821 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3822 {
3823 LLVMValueRef values[2];
3824
3825 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3826 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3827 return ac_build_gather_values(&ctx->ac, values, 2);
3828 }
3829
3830 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3831 const nir_intrinsic_instr *instr)
3832 {
3833 LLVMValueRef result[4];
3834 LLVMValueRef interp_param, attr_number;
3835 unsigned location;
3836 unsigned chan;
3837 LLVMValueRef src_c0 = NULL;
3838 LLVMValueRef src_c1 = NULL;
3839 LLVMValueRef src0 = NULL;
3840 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3841 switch (instr->intrinsic) {
3842 case nir_intrinsic_interp_var_at_centroid:
3843 location = INTERP_CENTROID;
3844 break;
3845 case nir_intrinsic_interp_var_at_sample:
3846 case nir_intrinsic_interp_var_at_offset:
3847 location = INTERP_CENTER;
3848 src0 = get_src(ctx->nir, instr->src[0]);
3849 break;
3850 default:
3851 break;
3852 }
3853
3854 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3855 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3856 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3857 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3858 LLVMValueRef sample_position;
3859 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3860
3861 /* fetch sample ID */
3862 sample_position = load_sample_position(ctx, src0);
3863
3864 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3865 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3866 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3867 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3868 }
3869 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3870 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3871
3872 if (location == INTERP_CENTER) {
3873 LLVMValueRef ij_out[2];
3874 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3875
3876 /*
3877 * take the I then J parameters, and the DDX/Y for it, and
3878 * calculate the IJ inputs for the interpolator.
3879 * temp1 = ddx * offset/sample.x + I;
3880 * interp_param.I = ddy * offset/sample.y + temp1;
3881 * temp1 = ddx * offset/sample.x + J;
3882 * interp_param.J = ddy * offset/sample.y + temp1;
3883 */
3884 for (unsigned i = 0; i < 2; i++) {
3885 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3886 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3887 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3888 ddxy_out, ix_ll, "");
3889 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3890 ddxy_out, iy_ll, "");
3891 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3892 interp_param, ix_ll, "");
3893 LLVMValueRef temp1, temp2;
3894
3895 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3896 ctx->ac.f32, "");
3897
3898 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3899 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3900
3901 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3902 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3903
3904 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3905 temp2, ctx->ac.i32, "");
3906 }
3907 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3908
3909 }
3910
3911 for (chan = 0; chan < 4; chan++) {
3912 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3913
3914 if (interp_param) {
3915 interp_param = LLVMBuildBitCast(ctx->builder,
3916 interp_param, ctx->ac.v2f32, "");
3917 LLVMValueRef i = LLVMBuildExtractElement(
3918 ctx->builder, interp_param, ctx->ac.i32_0, "");
3919 LLVMValueRef j = LLVMBuildExtractElement(
3920 ctx->builder, interp_param, ctx->ac.i32_1, "");
3921
3922 result[chan] = ac_build_fs_interp(&ctx->ac,
3923 llvm_chan, attr_number,
3924 ctx->prim_mask, i, j);
3925 } else {
3926 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3927 LLVMConstInt(ctx->ac.i32, 2, false),
3928 llvm_chan, attr_number,
3929 ctx->prim_mask);
3930 }
3931 }
3932 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
3933 instr->variables[0]->var->data.location_frac);
3934 }
3935
3936 static void
3937 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3938 {
3939 LLVMValueRef gs_next_vertex;
3940 LLVMValueRef can_emit;
3941 int idx;
3942 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3943
3944 /* Write vertex attribute values to GSVS ring */
3945 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3946 ctx->gs_next_vertex,
3947 "");
3948
3949 /* If this thread has already emitted the declared maximum number of
3950 * vertices, kill it: excessive vertex emissions are not supposed to
3951 * have any effect, and GS threads have no externally observable
3952 * effects other than emitting vertices.
3953 */
3954 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3955 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3956 ac_build_kill_if_false(&ctx->ac, can_emit);
3957
3958 /* loop num outputs */
3959 idx = 0;
3960 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3961 LLVMValueRef *out_ptr = &addrs[i * 4];
3962 int length = 4;
3963 int slot = idx;
3964 int slot_inc = 1;
3965
3966 if (!(ctx->output_mask & (1ull << i)))
3967 continue;
3968
3969 if (i == VARYING_SLOT_CLIP_DIST0) {
3970 /* pack clip and cull into a single set of slots */
3971 length = ctx->num_output_clips + ctx->num_output_culls;
3972 if (length > 4)
3973 slot_inc = 2;
3974 }
3975 for (unsigned j = 0; j < length; j++) {
3976 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3977 out_ptr[j], "");
3978 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3979 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3980 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
3981
3982 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
3983
3984 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3985 out_val, 1,
3986 voffset, ctx->gs2vs_offset, 0,
3987 1, 1, true, true);
3988 }
3989 idx += slot_inc;
3990 }
3991
3992 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3993 ctx->ac.i32_1, "");
3994 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3995
3996 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3997 }
3998
3999 static void
4000 visit_end_primitive(struct nir_to_llvm_context *ctx,
4001 const nir_intrinsic_instr *instr)
4002 {
4003 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4004 }
4005
4006 static LLVMValueRef
4007 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4008 const nir_intrinsic_instr *instr)
4009 {
4010 LLVMValueRef coord[4] = {
4011 ctx->tes_u,
4012 ctx->tes_v,
4013 ctx->ac.f32_0,
4014 ctx->ac.f32_0,
4015 };
4016
4017 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4018 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4019 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4020
4021 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4022 return LLVMBuildBitCast(ctx->builder, result,
4023 get_def_type(ctx->nir, &instr->dest.ssa), "");
4024 }
4025
4026 static void visit_intrinsic(struct ac_nir_context *ctx,
4027 nir_intrinsic_instr *instr)
4028 {
4029 LLVMValueRef result = NULL;
4030
4031 switch (instr->intrinsic) {
4032 case nir_intrinsic_load_work_group_id: {
4033 result = ctx->nctx->workgroup_ids;
4034 break;
4035 }
4036 case nir_intrinsic_load_base_vertex: {
4037 result = ctx->abi->base_vertex;
4038 break;
4039 }
4040 case nir_intrinsic_load_vertex_id_zero_base: {
4041 result = ctx->abi->vertex_id;
4042 break;
4043 }
4044 case nir_intrinsic_load_local_invocation_id: {
4045 result = ctx->nctx->local_invocation_ids;
4046 break;
4047 }
4048 case nir_intrinsic_load_base_instance:
4049 result = ctx->abi->start_instance;
4050 break;
4051 case nir_intrinsic_load_draw_id:
4052 result = ctx->abi->draw_id;
4053 break;
4054 case nir_intrinsic_load_view_index:
4055 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4056 break;
4057 case nir_intrinsic_load_invocation_id:
4058 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4059 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4060 else
4061 result = ctx->nctx->gs_invocation_id;
4062 break;
4063 case nir_intrinsic_load_primitive_id:
4064 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4065 ctx->nctx->shader_info->gs.uses_prim_id = true;
4066 result = ctx->nctx->gs_prim_id;
4067 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4068 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4069 result = ctx->nctx->tcs_patch_id;
4070 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4071 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4072 result = ctx->nctx->tes_patch_id;
4073 } else
4074 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4075 break;
4076 case nir_intrinsic_load_sample_id:
4077 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4078 break;
4079 case nir_intrinsic_load_sample_pos:
4080 result = load_sample_pos(ctx);
4081 break;
4082 case nir_intrinsic_load_sample_mask_in:
4083 result = ctx->abi->sample_coverage;
4084 break;
4085 case nir_intrinsic_load_frag_coord: {
4086 LLVMValueRef values[4] = {
4087 ctx->abi->frag_pos[0],
4088 ctx->abi->frag_pos[1],
4089 ctx->abi->frag_pos[2],
4090 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4091 };
4092 result = ac_build_gather_values(&ctx->ac, values, 4);
4093 break;
4094 }
4095 case nir_intrinsic_load_front_face:
4096 result = ctx->abi->front_face;
4097 break;
4098 case nir_intrinsic_load_instance_id:
4099 result = ctx->abi->instance_id;
4100 break;
4101 case nir_intrinsic_load_num_work_groups:
4102 result = ctx->nctx->num_work_groups;
4103 break;
4104 case nir_intrinsic_load_local_invocation_index:
4105 result = visit_load_local_invocation_index(ctx->nctx);
4106 break;
4107 case nir_intrinsic_load_push_constant:
4108 result = visit_load_push_constant(ctx->nctx, instr);
4109 break;
4110 case nir_intrinsic_vulkan_resource_index:
4111 result = visit_vulkan_resource_index(ctx->nctx, instr);
4112 break;
4113 case nir_intrinsic_store_ssbo:
4114 visit_store_ssbo(ctx, instr);
4115 break;
4116 case nir_intrinsic_load_ssbo:
4117 result = visit_load_buffer(ctx, instr);
4118 break;
4119 case nir_intrinsic_ssbo_atomic_add:
4120 case nir_intrinsic_ssbo_atomic_imin:
4121 case nir_intrinsic_ssbo_atomic_umin:
4122 case nir_intrinsic_ssbo_atomic_imax:
4123 case nir_intrinsic_ssbo_atomic_umax:
4124 case nir_intrinsic_ssbo_atomic_and:
4125 case nir_intrinsic_ssbo_atomic_or:
4126 case nir_intrinsic_ssbo_atomic_xor:
4127 case nir_intrinsic_ssbo_atomic_exchange:
4128 case nir_intrinsic_ssbo_atomic_comp_swap:
4129 result = visit_atomic_ssbo(ctx, instr);
4130 break;
4131 case nir_intrinsic_load_ubo:
4132 result = visit_load_ubo_buffer(ctx, instr);
4133 break;
4134 case nir_intrinsic_get_buffer_size:
4135 result = visit_get_buffer_size(ctx, instr);
4136 break;
4137 case nir_intrinsic_load_var:
4138 result = visit_load_var(ctx, instr);
4139 break;
4140 case nir_intrinsic_store_var:
4141 visit_store_var(ctx, instr);
4142 break;
4143 case nir_intrinsic_image_load:
4144 result = visit_image_load(ctx, instr);
4145 break;
4146 case nir_intrinsic_image_store:
4147 visit_image_store(ctx, instr);
4148 break;
4149 case nir_intrinsic_image_atomic_add:
4150 case nir_intrinsic_image_atomic_min:
4151 case nir_intrinsic_image_atomic_max:
4152 case nir_intrinsic_image_atomic_and:
4153 case nir_intrinsic_image_atomic_or:
4154 case nir_intrinsic_image_atomic_xor:
4155 case nir_intrinsic_image_atomic_exchange:
4156 case nir_intrinsic_image_atomic_comp_swap:
4157 result = visit_image_atomic(ctx, instr);
4158 break;
4159 case nir_intrinsic_image_size:
4160 result = visit_image_size(ctx, instr);
4161 break;
4162 case nir_intrinsic_discard:
4163 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4164 LLVMVoidTypeInContext(ctx->ac.context),
4165 NULL, 0, AC_FUNC_ATTR_LEGACY);
4166 break;
4167 case nir_intrinsic_discard_if:
4168 emit_discard_if(ctx, instr);
4169 break;
4170 case nir_intrinsic_memory_barrier:
4171 case nir_intrinsic_group_memory_barrier:
4172 case nir_intrinsic_memory_barrier_atomic_counter:
4173 case nir_intrinsic_memory_barrier_buffer:
4174 case nir_intrinsic_memory_barrier_image:
4175 case nir_intrinsic_memory_barrier_shared:
4176 emit_membar(ctx->nctx, instr);
4177 break;
4178 case nir_intrinsic_barrier:
4179 emit_barrier(ctx->nctx);
4180 break;
4181 case nir_intrinsic_var_atomic_add:
4182 case nir_intrinsic_var_atomic_imin:
4183 case nir_intrinsic_var_atomic_umin:
4184 case nir_intrinsic_var_atomic_imax:
4185 case nir_intrinsic_var_atomic_umax:
4186 case nir_intrinsic_var_atomic_and:
4187 case nir_intrinsic_var_atomic_or:
4188 case nir_intrinsic_var_atomic_xor:
4189 case nir_intrinsic_var_atomic_exchange:
4190 case nir_intrinsic_var_atomic_comp_swap:
4191 result = visit_var_atomic(ctx->nctx, instr);
4192 break;
4193 case nir_intrinsic_interp_var_at_centroid:
4194 case nir_intrinsic_interp_var_at_sample:
4195 case nir_intrinsic_interp_var_at_offset:
4196 result = visit_interp(ctx->nctx, instr);
4197 break;
4198 case nir_intrinsic_emit_vertex:
4199 assert(instr->const_index[0] == 0);
4200 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4201 break;
4202 case nir_intrinsic_end_primitive:
4203 visit_end_primitive(ctx->nctx, instr);
4204 break;
4205 case nir_intrinsic_load_tess_coord:
4206 result = visit_load_tess_coord(ctx->nctx, instr);
4207 break;
4208 case nir_intrinsic_load_patch_vertices_in:
4209 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4210 break;
4211 default:
4212 fprintf(stderr, "Unknown intrinsic: ");
4213 nir_print_instr(&instr->instr, stderr);
4214 fprintf(stderr, "\n");
4215 break;
4216 }
4217 if (result) {
4218 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4219 }
4220 }
4221
4222 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4223 LLVMValueRef buffer, bool write)
4224 {
4225 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4226
4227 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4228 ctx->shader_info->fs.writes_memory = true;
4229
4230 return buffer;
4231 }
4232
4233 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4234 unsigned descriptor_set,
4235 unsigned base_index,
4236 unsigned constant_index,
4237 LLVMValueRef index,
4238 enum ac_descriptor_type desc_type,
4239 bool image, bool write)
4240 {
4241 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4242 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4243 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4244 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4245 unsigned offset = binding->offset;
4246 unsigned stride = binding->size;
4247 unsigned type_size;
4248 LLVMBuilderRef builder = ctx->builder;
4249 LLVMTypeRef type;
4250
4251 assert(base_index < layout->binding_count);
4252
4253 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4254 ctx->shader_info->fs.writes_memory = true;
4255
4256 switch (desc_type) {
4257 case AC_DESC_IMAGE:
4258 type = ctx->ac.v8i32;
4259 type_size = 32;
4260 break;
4261 case AC_DESC_FMASK:
4262 type = ctx->ac.v8i32;
4263 offset += 32;
4264 type_size = 32;
4265 break;
4266 case AC_DESC_SAMPLER:
4267 type = ctx->ac.v4i32;
4268 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4269 offset += 64;
4270
4271 type_size = 16;
4272 break;
4273 case AC_DESC_BUFFER:
4274 type = ctx->ac.v4i32;
4275 type_size = 16;
4276 break;
4277 default:
4278 unreachable("invalid desc_type\n");
4279 }
4280
4281 offset += constant_index * stride;
4282
4283 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4284 (!index || binding->immutable_samplers_equal)) {
4285 if (binding->immutable_samplers_equal)
4286 constant_index = 0;
4287
4288 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4289
4290 LLVMValueRef constants[] = {
4291 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4292 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4293 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4294 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4295 };
4296 return ac_build_gather_values(&ctx->ac, constants, 4);
4297 }
4298
4299 assert(stride % type_size == 0);
4300
4301 if (!index)
4302 index = ctx->ac.i32_0;
4303
4304 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4305
4306 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4307 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4308
4309 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4310 }
4311
4312 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4313 const nir_deref_var *deref,
4314 enum ac_descriptor_type desc_type,
4315 const nir_tex_instr *tex_instr,
4316 bool image, bool write)
4317 {
4318 LLVMValueRef index = NULL;
4319 unsigned constant_index = 0;
4320 unsigned descriptor_set;
4321 unsigned base_index;
4322
4323 if (!deref) {
4324 assert(tex_instr && !image);
4325 descriptor_set = 0;
4326 base_index = tex_instr->sampler_index;
4327 } else {
4328 const nir_deref *tail = &deref->deref;
4329 while (tail->child) {
4330 const nir_deref_array *child = nir_deref_as_array(tail->child);
4331 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4332
4333 if (!array_size)
4334 array_size = 1;
4335
4336 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4337
4338 if (child->deref_array_type == nir_deref_array_type_indirect) {
4339 LLVMValueRef indirect = get_src(ctx, child->indirect);
4340
4341 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4342 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4343
4344 if (!index)
4345 index = indirect;
4346 else
4347 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4348 }
4349
4350 constant_index += child->base_offset * array_size;
4351
4352 tail = &child->deref;
4353 }
4354 descriptor_set = deref->var->data.descriptor_set;
4355 base_index = deref->var->data.binding;
4356 }
4357
4358 return ctx->abi->load_sampler_desc(ctx->abi,
4359 descriptor_set,
4360 base_index,
4361 constant_index, index,
4362 desc_type, image, write);
4363 }
4364
4365 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4366 struct ac_image_args *args,
4367 const nir_tex_instr *instr,
4368 nir_texop op,
4369 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4370 LLVMValueRef *param, unsigned count,
4371 unsigned dmask)
4372 {
4373 unsigned is_rect = 0;
4374 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4375
4376 if (op == nir_texop_lod)
4377 da = false;
4378 /* Pad to power of two vector */
4379 while (count < util_next_power_of_two(count))
4380 param[count++] = LLVMGetUndef(ctx->i32);
4381
4382 if (count > 1)
4383 args->addr = ac_build_gather_values(ctx, param, count);
4384 else
4385 args->addr = param[0];
4386
4387 args->resource = res_ptr;
4388 args->sampler = samp_ptr;
4389
4390 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4391 args->addr = param[0];
4392 return;
4393 }
4394
4395 args->dmask = dmask;
4396 args->unorm = is_rect;
4397 args->da = da;
4398 }
4399
4400 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4401 *
4402 * SI-CI:
4403 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4404 * filtering manually. The driver sets img7 to a mask clearing
4405 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4406 * s_and_b32 samp0, samp0, img7
4407 *
4408 * VI:
4409 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4410 */
4411 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4412 LLVMValueRef res, LLVMValueRef samp)
4413 {
4414 LLVMBuilderRef builder = ctx->ac.builder;
4415 LLVMValueRef img7, samp0;
4416
4417 if (ctx->ac.chip_class >= VI)
4418 return samp;
4419
4420 img7 = LLVMBuildExtractElement(builder, res,
4421 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4422 samp0 = LLVMBuildExtractElement(builder, samp,
4423 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4424 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4425 return LLVMBuildInsertElement(builder, samp, samp0,
4426 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4427 }
4428
4429 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4430 nir_tex_instr *instr,
4431 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4432 LLVMValueRef *fmask_ptr)
4433 {
4434 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4435 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4436 else
4437 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4438 if (samp_ptr) {
4439 if (instr->sampler)
4440 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4441 else
4442 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4443 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4444 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4445 }
4446 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4447 instr->op == nir_texop_samples_identical))
4448 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4449 }
4450
4451 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4452 LLVMValueRef coord)
4453 {
4454 coord = ac_to_float(ctx, coord);
4455 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4456 coord = ac_to_integer(ctx, coord);
4457 return coord;
4458 }
4459
4460 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4461 {
4462 LLVMValueRef result = NULL;
4463 struct ac_image_args args = { 0 };
4464 unsigned dmask = 0xf;
4465 LLVMValueRef address[16];
4466 LLVMValueRef coords[5];
4467 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4468 LLVMValueRef bias = NULL, offsets = NULL;
4469 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4470 LLVMValueRef ddx = NULL, ddy = NULL;
4471 LLVMValueRef derivs[6];
4472 unsigned chan, count = 0;
4473 unsigned const_src = 0, num_deriv_comp = 0;
4474 bool lod_is_zero = false;
4475
4476 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4477
4478 for (unsigned i = 0; i < instr->num_srcs; i++) {
4479 switch (instr->src[i].src_type) {
4480 case nir_tex_src_coord:
4481 coord = get_src(ctx, instr->src[i].src);
4482 break;
4483 case nir_tex_src_projector:
4484 break;
4485 case nir_tex_src_comparator:
4486 comparator = get_src(ctx, instr->src[i].src);
4487 break;
4488 case nir_tex_src_offset:
4489 offsets = get_src(ctx, instr->src[i].src);
4490 const_src = i;
4491 break;
4492 case nir_tex_src_bias:
4493 bias = get_src(ctx, instr->src[i].src);
4494 break;
4495 case nir_tex_src_lod: {
4496 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4497
4498 if (val && val->i32[0] == 0)
4499 lod_is_zero = true;
4500 lod = get_src(ctx, instr->src[i].src);
4501 break;
4502 }
4503 case nir_tex_src_ms_index:
4504 sample_index = get_src(ctx, instr->src[i].src);
4505 break;
4506 case nir_tex_src_ms_mcs:
4507 break;
4508 case nir_tex_src_ddx:
4509 ddx = get_src(ctx, instr->src[i].src);
4510 num_deriv_comp = instr->src[i].src.ssa->num_components;
4511 break;
4512 case nir_tex_src_ddy:
4513 ddy = get_src(ctx, instr->src[i].src);
4514 break;
4515 case nir_tex_src_texture_offset:
4516 case nir_tex_src_sampler_offset:
4517 case nir_tex_src_plane:
4518 default:
4519 break;
4520 }
4521 }
4522
4523 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4524 result = get_buffer_size(ctx, res_ptr, true);
4525 goto write_result;
4526 }
4527
4528 if (instr->op == nir_texop_texture_samples) {
4529 LLVMValueRef res, samples, is_msaa;
4530 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4531 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4532 LLVMConstInt(ctx->ac.i32, 3, false), "");
4533 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4534 LLVMConstInt(ctx->ac.i32, 28, false), "");
4535 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4536 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4537 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4538 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4539
4540 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4541 LLVMConstInt(ctx->ac.i32, 16, false), "");
4542 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4543 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4544 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4545 samples, "");
4546 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4547 ctx->ac.i32_1, "");
4548 result = samples;
4549 goto write_result;
4550 }
4551
4552 if (coord)
4553 for (chan = 0; chan < instr->coord_components; chan++)
4554 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4555
4556 if (offsets && instr->op != nir_texop_txf) {
4557 LLVMValueRef offset[3], pack;
4558 for (chan = 0; chan < 3; ++chan)
4559 offset[chan] = ctx->ac.i32_0;
4560
4561 args.offset = true;
4562 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4563 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4564 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4565 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4566 if (chan)
4567 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4568 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4569 }
4570 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4571 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4572 address[count++] = pack;
4573
4574 }
4575 /* pack LOD bias value */
4576 if (instr->op == nir_texop_txb && bias) {
4577 address[count++] = bias;
4578 }
4579
4580 /* Pack depth comparison value */
4581 if (instr->is_shadow && comparator) {
4582 LLVMValueRef z = ac_to_float(&ctx->ac,
4583 llvm_extract_elem(&ctx->ac, comparator, 0));
4584
4585 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4586 * so the depth comparison value isn't clamped for Z16 and
4587 * Z24 anymore. Do it manually here.
4588 *
4589 * It's unnecessary if the original texture format was
4590 * Z32_FLOAT, but we don't know that here.
4591 */
4592 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4593 z = ac_build_clamp(&ctx->ac, z);
4594
4595 address[count++] = z;
4596 }
4597
4598 /* pack derivatives */
4599 if (ddx || ddy) {
4600 int num_src_deriv_channels, num_dest_deriv_channels;
4601 switch (instr->sampler_dim) {
4602 case GLSL_SAMPLER_DIM_3D:
4603 case GLSL_SAMPLER_DIM_CUBE:
4604 num_deriv_comp = 3;
4605 num_src_deriv_channels = 3;
4606 num_dest_deriv_channels = 3;
4607 break;
4608 case GLSL_SAMPLER_DIM_2D:
4609 default:
4610 num_src_deriv_channels = 2;
4611 num_dest_deriv_channels = 2;
4612 num_deriv_comp = 2;
4613 break;
4614 case GLSL_SAMPLER_DIM_1D:
4615 num_src_deriv_channels = 1;
4616 if (ctx->ac.chip_class >= GFX9) {
4617 num_dest_deriv_channels = 2;
4618 num_deriv_comp = 2;
4619 } else {
4620 num_dest_deriv_channels = 1;
4621 num_deriv_comp = 1;
4622 }
4623 break;
4624 }
4625
4626 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4627 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4628 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4629 }
4630 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4631 derivs[i] = ctx->ac.f32_0;
4632 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4633 }
4634 }
4635
4636 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4637 for (chan = 0; chan < instr->coord_components; chan++)
4638 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4639 if (instr->coord_components == 3)
4640 coords[3] = LLVMGetUndef(ctx->ac.f32);
4641 ac_prepare_cube_coords(&ctx->ac,
4642 instr->op == nir_texop_txd, instr->is_array,
4643 instr->op == nir_texop_lod, coords, derivs);
4644 if (num_deriv_comp)
4645 num_deriv_comp--;
4646 }
4647
4648 if (ddx || ddy) {
4649 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4650 address[count++] = derivs[i];
4651 }
4652
4653 /* Pack texture coordinates */
4654 if (coord) {
4655 address[count++] = coords[0];
4656 if (instr->coord_components > 1) {
4657 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4658 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4659 }
4660 address[count++] = coords[1];
4661 }
4662 if (instr->coord_components > 2) {
4663 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4664 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4665 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4666 instr->op != nir_texop_txf) {
4667 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4668 }
4669 address[count++] = coords[2];
4670 }
4671
4672 if (ctx->ac.chip_class >= GFX9) {
4673 LLVMValueRef filler;
4674 if (instr->op == nir_texop_txf)
4675 filler = ctx->ac.i32_0;
4676 else
4677 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4678
4679 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4680 /* No nir_texop_lod, because it does not take a slice
4681 * even with array textures. */
4682 if (instr->is_array && instr->op != nir_texop_lod ) {
4683 address[count] = address[count - 1];
4684 address[count - 1] = filler;
4685 count++;
4686 } else
4687 address[count++] = filler;
4688 }
4689 }
4690 }
4691
4692 /* Pack LOD */
4693 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4694 instr->op == nir_texop_txf)) {
4695 address[count++] = lod;
4696 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4697 address[count++] = sample_index;
4698 } else if(instr->op == nir_texop_txs) {
4699 count = 0;
4700 if (lod)
4701 address[count++] = lod;
4702 else
4703 address[count++] = ctx->ac.i32_0;
4704 }
4705
4706 for (chan = 0; chan < count; chan++) {
4707 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4708 address[chan], ctx->ac.i32, "");
4709 }
4710
4711 if (instr->op == nir_texop_samples_identical) {
4712 LLVMValueRef txf_address[4];
4713 struct ac_image_args txf_args = { 0 };
4714 unsigned txf_count = count;
4715 memcpy(txf_address, address, sizeof(txf_address));
4716
4717 if (!instr->is_array)
4718 txf_address[2] = ctx->ac.i32_0;
4719 txf_address[3] = ctx->ac.i32_0;
4720
4721 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4722 fmask_ptr, NULL,
4723 txf_address, txf_count, 0xf);
4724
4725 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4726
4727 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4728 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4729 goto write_result;
4730 }
4731
4732 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4733 instr->op != nir_texop_txs) {
4734 unsigned sample_chan = instr->is_array ? 3 : 2;
4735 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4736 address[0],
4737 address[1],
4738 instr->is_array ? address[2] : NULL,
4739 address[sample_chan],
4740 fmask_ptr);
4741 }
4742
4743 if (offsets && instr->op == nir_texop_txf) {
4744 nir_const_value *const_offset =
4745 nir_src_as_const_value(instr->src[const_src].src);
4746 int num_offsets = instr->src[const_src].src.ssa->num_components;
4747 assert(const_offset);
4748 num_offsets = MIN2(num_offsets, instr->coord_components);
4749 if (num_offsets > 2)
4750 address[2] = LLVMBuildAdd(ctx->ac.builder,
4751 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4752 if (num_offsets > 1)
4753 address[1] = LLVMBuildAdd(ctx->ac.builder,
4754 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4755 address[0] = LLVMBuildAdd(ctx->ac.builder,
4756 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4757
4758 }
4759
4760 /* TODO TG4 support */
4761 if (instr->op == nir_texop_tg4) {
4762 if (instr->is_shadow)
4763 dmask = 1;
4764 else
4765 dmask = 1 << instr->component;
4766 }
4767 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4768 res_ptr, samp_ptr, address, count, dmask);
4769
4770 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4771
4772 if (instr->op == nir_texop_query_levels)
4773 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4774 else if (instr->is_shadow && instr->is_new_style_shadow &&
4775 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4776 instr->op != nir_texop_tg4)
4777 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4778 else if (instr->op == nir_texop_txs &&
4779 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4780 instr->is_array) {
4781 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4782 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4783 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4784 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4785 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4786 } else if (ctx->ac.chip_class >= GFX9 &&
4787 instr->op == nir_texop_txs &&
4788 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4789 instr->is_array) {
4790 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4791 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4792 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4793 ctx->ac.i32_1, "");
4794 } else if (instr->dest.ssa.num_components != 4)
4795 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4796
4797 write_result:
4798 if (result) {
4799 assert(instr->dest.is_ssa);
4800 result = ac_to_integer(&ctx->ac, result);
4801 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4802 }
4803 }
4804
4805
4806 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4807 {
4808 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4809 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4810
4811 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4812 _mesa_hash_table_insert(ctx->phis, instr, result);
4813 }
4814
4815 static void visit_post_phi(struct ac_nir_context *ctx,
4816 nir_phi_instr *instr,
4817 LLVMValueRef llvm_phi)
4818 {
4819 nir_foreach_phi_src(src, instr) {
4820 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4821 LLVMValueRef llvm_src = get_src(ctx, src->src);
4822
4823 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4824 }
4825 }
4826
4827 static void phi_post_pass(struct ac_nir_context *ctx)
4828 {
4829 struct hash_entry *entry;
4830 hash_table_foreach(ctx->phis, entry) {
4831 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4832 (LLVMValueRef)entry->data);
4833 }
4834 }
4835
4836
4837 static void visit_ssa_undef(struct ac_nir_context *ctx,
4838 const nir_ssa_undef_instr *instr)
4839 {
4840 unsigned num_components = instr->def.num_components;
4841 LLVMValueRef undef;
4842
4843 if (num_components == 1)
4844 undef = LLVMGetUndef(ctx->ac.i32);
4845 else {
4846 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4847 }
4848 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4849 }
4850
4851 static void visit_jump(struct ac_nir_context *ctx,
4852 const nir_jump_instr *instr)
4853 {
4854 switch (instr->type) {
4855 case nir_jump_break:
4856 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4857 LLVMClearInsertionPosition(ctx->ac.builder);
4858 break;
4859 case nir_jump_continue:
4860 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4861 LLVMClearInsertionPosition(ctx->ac.builder);
4862 break;
4863 default:
4864 fprintf(stderr, "Unknown NIR jump instr: ");
4865 nir_print_instr(&instr->instr, stderr);
4866 fprintf(stderr, "\n");
4867 abort();
4868 }
4869 }
4870
4871 static void visit_cf_list(struct ac_nir_context *ctx,
4872 struct exec_list *list);
4873
4874 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4875 {
4876 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4877 nir_foreach_instr(instr, block)
4878 {
4879 switch (instr->type) {
4880 case nir_instr_type_alu:
4881 visit_alu(ctx, nir_instr_as_alu(instr));
4882 break;
4883 case nir_instr_type_load_const:
4884 visit_load_const(ctx, nir_instr_as_load_const(instr));
4885 break;
4886 case nir_instr_type_intrinsic:
4887 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4888 break;
4889 case nir_instr_type_tex:
4890 visit_tex(ctx, nir_instr_as_tex(instr));
4891 break;
4892 case nir_instr_type_phi:
4893 visit_phi(ctx, nir_instr_as_phi(instr));
4894 break;
4895 case nir_instr_type_ssa_undef:
4896 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4897 break;
4898 case nir_instr_type_jump:
4899 visit_jump(ctx, nir_instr_as_jump(instr));
4900 break;
4901 default:
4902 fprintf(stderr, "Unknown NIR instr type: ");
4903 nir_print_instr(instr, stderr);
4904 fprintf(stderr, "\n");
4905 abort();
4906 }
4907 }
4908
4909 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4910 }
4911
4912 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4913 {
4914 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4915
4916 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4917 LLVMBasicBlockRef merge_block =
4918 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4919 LLVMBasicBlockRef if_block =
4920 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4921 LLVMBasicBlockRef else_block = merge_block;
4922 if (!exec_list_is_empty(&if_stmt->else_list))
4923 else_block = LLVMAppendBasicBlockInContext(
4924 ctx->ac.context, fn, "");
4925
4926 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4927 LLVMConstInt(ctx->ac.i32, 0, false), "");
4928 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4929
4930 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4931 visit_cf_list(ctx, &if_stmt->then_list);
4932 if (LLVMGetInsertBlock(ctx->ac.builder))
4933 LLVMBuildBr(ctx->ac.builder, merge_block);
4934
4935 if (!exec_list_is_empty(&if_stmt->else_list)) {
4936 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4937 visit_cf_list(ctx, &if_stmt->else_list);
4938 if (LLVMGetInsertBlock(ctx->ac.builder))
4939 LLVMBuildBr(ctx->ac.builder, merge_block);
4940 }
4941
4942 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4943 }
4944
4945 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4946 {
4947 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4948 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4949 LLVMBasicBlockRef break_parent = ctx->break_block;
4950
4951 ctx->continue_block =
4952 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4953 ctx->break_block =
4954 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4955
4956 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4957 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4958 visit_cf_list(ctx, &loop->body);
4959
4960 if (LLVMGetInsertBlock(ctx->ac.builder))
4961 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4962 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4963
4964 ctx->continue_block = continue_parent;
4965 ctx->break_block = break_parent;
4966 }
4967
4968 static void visit_cf_list(struct ac_nir_context *ctx,
4969 struct exec_list *list)
4970 {
4971 foreach_list_typed(nir_cf_node, node, node, list)
4972 {
4973 switch (node->type) {
4974 case nir_cf_node_block:
4975 visit_block(ctx, nir_cf_node_as_block(node));
4976 break;
4977
4978 case nir_cf_node_if:
4979 visit_if(ctx, nir_cf_node_as_if(node));
4980 break;
4981
4982 case nir_cf_node_loop:
4983 visit_loop(ctx, nir_cf_node_as_loop(node));
4984 break;
4985
4986 default:
4987 assert(0);
4988 }
4989 }
4990 }
4991
4992 static void
4993 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4994 struct nir_variable *variable)
4995 {
4996 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4997 LLVMValueRef t_offset;
4998 LLVMValueRef t_list;
4999 LLVMValueRef input;
5000 LLVMValueRef buffer_index;
5001 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5002 int idx = variable->data.location;
5003 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5004
5005 variable->data.driver_location = idx * 4;
5006
5007 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5008 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5009 ctx->abi.start_instance, "");
5010 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5011 ctx->shader_info->vs.vgpr_comp_cnt);
5012 } else
5013 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5014 ctx->abi.base_vertex, "");
5015
5016 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5017 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5018
5019 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5020
5021 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5022 buffer_index,
5023 LLVMConstInt(ctx->ac.i32, 0, false),
5024 true);
5025
5026 for (unsigned chan = 0; chan < 4; chan++) {
5027 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5028 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5029 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5030 input, llvm_chan, ""));
5031 }
5032 }
5033 }
5034
5035 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5036 unsigned attr,
5037 LLVMValueRef interp_param,
5038 LLVMValueRef prim_mask,
5039 LLVMValueRef result[4])
5040 {
5041 LLVMValueRef attr_number;
5042 unsigned chan;
5043 LLVMValueRef i, j;
5044 bool interp = interp_param != NULL;
5045
5046 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5047
5048 /* fs.constant returns the param from the middle vertex, so it's not
5049 * really useful for flat shading. It's meant to be used for custom
5050 * interpolation (but the intrinsic can't fetch from the other two
5051 * vertices).
5052 *
5053 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5054 * to do the right thing. The only reason we use fs.constant is that
5055 * fs.interp cannot be used on integers, because they can be equal
5056 * to NaN.
5057 */
5058 if (interp) {
5059 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5060 ctx->ac.v2f32, "");
5061
5062 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5063 ctx->ac.i32_0, "");
5064 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5065 ctx->ac.i32_1, "");
5066 }
5067
5068 for (chan = 0; chan < 4; chan++) {
5069 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5070
5071 if (interp) {
5072 result[chan] = ac_build_fs_interp(&ctx->ac,
5073 llvm_chan,
5074 attr_number,
5075 prim_mask, i, j);
5076 } else {
5077 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5078 LLVMConstInt(ctx->ac.i32, 2, false),
5079 llvm_chan,
5080 attr_number,
5081 prim_mask);
5082 }
5083 }
5084 }
5085
5086 static void
5087 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5088 struct nir_variable *variable)
5089 {
5090 int idx = variable->data.location;
5091 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5092 LLVMValueRef interp;
5093
5094 variable->data.driver_location = idx * 4;
5095 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5096
5097 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5098 unsigned interp_type;
5099 if (variable->data.sample) {
5100 interp_type = INTERP_SAMPLE;
5101 ctx->shader_info->info.ps.force_persample = true;
5102 } else if (variable->data.centroid)
5103 interp_type = INTERP_CENTROID;
5104 else
5105 interp_type = INTERP_CENTER;
5106
5107 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5108 } else
5109 interp = NULL;
5110
5111 for (unsigned i = 0; i < attrib_count; ++i)
5112 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5113
5114 }
5115
5116 static void
5117 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5118 struct nir_shader *nir) {
5119 nir_foreach_variable(variable, &nir->inputs)
5120 handle_vs_input_decl(ctx, variable);
5121 }
5122
5123 static void
5124 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5125 struct nir_shader *nir)
5126 {
5127 if (!ctx->options->key.fs.multisample)
5128 return;
5129
5130 bool uses_center = false;
5131 bool uses_centroid = false;
5132 nir_foreach_variable(variable, &nir->inputs) {
5133 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5134 variable->data.sample)
5135 continue;
5136
5137 if (variable->data.centroid)
5138 uses_centroid = true;
5139 else
5140 uses_center = true;
5141 }
5142
5143 if (uses_center && uses_centroid) {
5144 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5145 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5146 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5147 }
5148 }
5149
5150 static void
5151 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5152 struct nir_shader *nir)
5153 {
5154 prepare_interp_optimize(ctx, nir);
5155
5156 nir_foreach_variable(variable, &nir->inputs)
5157 handle_fs_input_decl(ctx, variable);
5158
5159 unsigned index = 0;
5160
5161 if (ctx->shader_info->info.ps.uses_input_attachments ||
5162 ctx->shader_info->info.needs_multiview_view_index)
5163 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5164
5165 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5166 LLVMValueRef interp_param;
5167 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5168
5169 if (!(ctx->input_mask & (1ull << i)))
5170 continue;
5171
5172 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5173 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5174 interp_param = *inputs;
5175 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5176 inputs);
5177
5178 if (!interp_param)
5179 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5180 ++index;
5181 } else if (i == VARYING_SLOT_POS) {
5182 for(int i = 0; i < 3; ++i)
5183 inputs[i] = ctx->abi.frag_pos[i];
5184
5185 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5186 ctx->abi.frag_pos[3]);
5187 }
5188 }
5189 ctx->shader_info->fs.num_interp = index;
5190 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5191 ctx->shader_info->fs.has_pcoord = true;
5192 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5193 ctx->shader_info->fs.prim_id_input = true;
5194 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5195 ctx->shader_info->fs.layer_input = true;
5196 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5197
5198 if (ctx->shader_info->info.needs_multiview_view_index)
5199 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5200 }
5201
5202 static LLVMValueRef
5203 ac_build_alloca(struct ac_llvm_context *ac,
5204 LLVMTypeRef type,
5205 const char *name)
5206 {
5207 LLVMBuilderRef builder = ac->builder;
5208 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5209 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5210 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5211 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5212 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5213 LLVMValueRef res;
5214
5215 if (first_instr) {
5216 LLVMPositionBuilderBefore(first_builder, first_instr);
5217 } else {
5218 LLVMPositionBuilderAtEnd(first_builder, first_block);
5219 }
5220
5221 res = LLVMBuildAlloca(first_builder, type, name);
5222 LLVMBuildStore(builder, LLVMConstNull(type), res);
5223
5224 LLVMDisposeBuilder(first_builder);
5225
5226 return res;
5227 }
5228
5229 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5230 LLVMTypeRef type,
5231 const char *name)
5232 {
5233 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5234 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5235 return ptr;
5236 }
5237
5238 static void
5239 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5240 struct nir_variable *variable,
5241 struct nir_shader *shader,
5242 gl_shader_stage stage)
5243 {
5244 int idx = variable->data.location + variable->data.index;
5245 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5246 uint64_t mask_attribs;
5247
5248 variable->data.driver_location = idx * 4;
5249
5250 /* tess ctrl has it's own load/store paths for outputs */
5251 if (stage == MESA_SHADER_TESS_CTRL)
5252 return;
5253
5254 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5255 if (stage == MESA_SHADER_VERTEX ||
5256 stage == MESA_SHADER_TESS_EVAL ||
5257 stage == MESA_SHADER_GEOMETRY) {
5258 if (idx == VARYING_SLOT_CLIP_DIST0) {
5259 int length = shader->info.clip_distance_array_size +
5260 shader->info.cull_distance_array_size;
5261 if (stage == MESA_SHADER_VERTEX) {
5262 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5263 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5264 }
5265 if (stage == MESA_SHADER_TESS_EVAL) {
5266 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5267 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5268 }
5269
5270 if (length > 4)
5271 attrib_count = 2;
5272 else
5273 attrib_count = 1;
5274 mask_attribs = 1ull << idx;
5275 }
5276 }
5277
5278 ctx->output_mask |= mask_attribs;
5279 }
5280
5281 static void
5282 handle_shader_output_decl(struct ac_nir_context *ctx,
5283 struct nir_shader *nir,
5284 struct nir_variable *variable)
5285 {
5286 unsigned output_loc = variable->data.driver_location / 4;
5287 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5288
5289 /* tess ctrl has it's own load/store paths for outputs */
5290 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5291 return;
5292
5293 if (ctx->stage == MESA_SHADER_VERTEX ||
5294 ctx->stage == MESA_SHADER_TESS_EVAL ||
5295 ctx->stage == MESA_SHADER_GEOMETRY) {
5296 int idx = variable->data.location + variable->data.index;
5297 if (idx == VARYING_SLOT_CLIP_DIST0) {
5298 int length = nir->info.clip_distance_array_size +
5299 nir->info.cull_distance_array_size;
5300
5301 if (length > 4)
5302 attrib_count = 2;
5303 else
5304 attrib_count = 1;
5305 }
5306 }
5307
5308 for (unsigned i = 0; i < attrib_count; ++i) {
5309 for (unsigned chan = 0; chan < 4; chan++) {
5310 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5311 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5312 }
5313 }
5314 }
5315
5316 static LLVMTypeRef
5317 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5318 enum glsl_base_type type)
5319 {
5320 switch (type) {
5321 case GLSL_TYPE_INT:
5322 case GLSL_TYPE_UINT:
5323 case GLSL_TYPE_BOOL:
5324 case GLSL_TYPE_SUBROUTINE:
5325 return ctx->ac.i32;
5326 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5327 return ctx->ac.f32;
5328 case GLSL_TYPE_INT64:
5329 case GLSL_TYPE_UINT64:
5330 return ctx->ac.i64;
5331 case GLSL_TYPE_DOUBLE:
5332 return ctx->ac.f64;
5333 default:
5334 unreachable("unknown GLSL type");
5335 }
5336 }
5337
5338 static LLVMTypeRef
5339 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5340 const struct glsl_type *type)
5341 {
5342 if (glsl_type_is_scalar(type)) {
5343 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5344 }
5345
5346 if (glsl_type_is_vector(type)) {
5347 return LLVMVectorType(
5348 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5349 glsl_get_vector_elements(type));
5350 }
5351
5352 if (glsl_type_is_matrix(type)) {
5353 return LLVMArrayType(
5354 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5355 glsl_get_matrix_columns(type));
5356 }
5357
5358 if (glsl_type_is_array(type)) {
5359 return LLVMArrayType(
5360 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5361 glsl_get_length(type));
5362 }
5363
5364 assert(glsl_type_is_struct(type));
5365
5366 LLVMTypeRef member_types[glsl_get_length(type)];
5367
5368 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5369 member_types[i] =
5370 glsl_to_llvm_type(ctx,
5371 glsl_get_struct_field(type, i));
5372 }
5373
5374 return LLVMStructTypeInContext(ctx->context, member_types,
5375 glsl_get_length(type), false);
5376 }
5377
5378 static void
5379 setup_locals(struct ac_nir_context *ctx,
5380 struct nir_function *func)
5381 {
5382 int i, j;
5383 ctx->num_locals = 0;
5384 nir_foreach_variable(variable, &func->impl->locals) {
5385 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5386 variable->data.driver_location = ctx->num_locals * 4;
5387 ctx->num_locals += attrib_count;
5388 }
5389 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5390 if (!ctx->locals)
5391 return;
5392
5393 for (i = 0; i < ctx->num_locals; i++) {
5394 for (j = 0; j < 4; j++) {
5395 ctx->locals[i * 4 + j] =
5396 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5397 }
5398 }
5399 }
5400
5401 static void
5402 setup_shared(struct ac_nir_context *ctx,
5403 struct nir_shader *nir)
5404 {
5405 nir_foreach_variable(variable, &nir->shared) {
5406 LLVMValueRef shared =
5407 LLVMAddGlobalInAddressSpace(
5408 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5409 variable->name ? variable->name : "",
5410 LOCAL_ADDR_SPACE);
5411 _mesa_hash_table_insert(ctx->vars, variable, shared);
5412 }
5413 }
5414
5415 static LLVMValueRef
5416 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5417 {
5418 v = ac_to_float(ctx, v);
5419 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5420 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5421 }
5422
5423
5424 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5425 LLVMValueRef src0, LLVMValueRef src1)
5426 {
5427 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5428 LLVMValueRef comp[2];
5429
5430 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5431 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5432 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5433 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5434 }
5435
5436 /* Initialize arguments for the shader export intrinsic */
5437 static void
5438 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5439 LLVMValueRef *values,
5440 unsigned target,
5441 struct ac_export_args *args)
5442 {
5443 /* Default is 0xf. Adjusted below depending on the format. */
5444 args->enabled_channels = 0xf;
5445
5446 /* Specify whether the EXEC mask represents the valid mask */
5447 args->valid_mask = 0;
5448
5449 /* Specify whether this is the last export */
5450 args->done = 0;
5451
5452 /* Specify the target we are exporting */
5453 args->target = target;
5454
5455 args->compr = false;
5456 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5457 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5458 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5459 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5460
5461 if (!values)
5462 return;
5463
5464 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5465 LLVMValueRef val[4];
5466 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5467 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5468 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5469 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5470
5471 switch(col_format) {
5472 case V_028714_SPI_SHADER_ZERO:
5473 args->enabled_channels = 0; /* writemask */
5474 args->target = V_008DFC_SQ_EXP_NULL;
5475 break;
5476
5477 case V_028714_SPI_SHADER_32_R:
5478 args->enabled_channels = 1;
5479 args->out[0] = values[0];
5480 break;
5481
5482 case V_028714_SPI_SHADER_32_GR:
5483 args->enabled_channels = 0x3;
5484 args->out[0] = values[0];
5485 args->out[1] = values[1];
5486 break;
5487
5488 case V_028714_SPI_SHADER_32_AR:
5489 args->enabled_channels = 0x9;
5490 args->out[0] = values[0];
5491 args->out[3] = values[3];
5492 break;
5493
5494 case V_028714_SPI_SHADER_FP16_ABGR:
5495 args->compr = 1;
5496
5497 for (unsigned chan = 0; chan < 2; chan++) {
5498 LLVMValueRef pack_args[2] = {
5499 values[2 * chan],
5500 values[2 * chan + 1]
5501 };
5502 LLVMValueRef packed;
5503
5504 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5505 args->out[chan] = packed;
5506 }
5507 break;
5508
5509 case V_028714_SPI_SHADER_UNORM16_ABGR:
5510 for (unsigned chan = 0; chan < 4; chan++) {
5511 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5512 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5513 LLVMConstReal(ctx->ac.f32, 65535), "");
5514 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5515 LLVMConstReal(ctx->ac.f32, 0.5), "");
5516 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5517 ctx->ac.i32, "");
5518 }
5519
5520 args->compr = 1;
5521 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5522 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5523 break;
5524
5525 case V_028714_SPI_SHADER_SNORM16_ABGR:
5526 for (unsigned chan = 0; chan < 4; chan++) {
5527 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5528 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5529 LLVMConstReal(ctx->ac.f32, 32767), "");
5530
5531 /* If positive, add 0.5, else add -0.5. */
5532 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5533 LLVMBuildSelect(ctx->builder,
5534 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5535 val[chan], ctx->ac.f32_0, ""),
5536 LLVMConstReal(ctx->ac.f32, 0.5),
5537 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5538 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5539 }
5540
5541 args->compr = 1;
5542 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5543 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5544 break;
5545
5546 case V_028714_SPI_SHADER_UINT16_ABGR: {
5547 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5548 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5549 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5550
5551 for (unsigned chan = 0; chan < 4; chan++) {
5552 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5553 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5554 }
5555
5556 args->compr = 1;
5557 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5558 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5559 break;
5560 }
5561
5562 case V_028714_SPI_SHADER_SINT16_ABGR: {
5563 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5564 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5565 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5566 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5567 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5568 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5569
5570 /* Clamp. */
5571 for (unsigned chan = 0; chan < 4; chan++) {
5572 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5573 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5574 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5575 }
5576
5577 args->compr = 1;
5578 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5579 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5580 break;
5581 }
5582
5583 default:
5584 case V_028714_SPI_SHADER_32_ABGR:
5585 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5586 break;
5587 }
5588 } else
5589 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5590
5591 for (unsigned i = 0; i < 4; ++i)
5592 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5593 }
5594
5595 static void
5596 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5597 bool export_prim_id,
5598 struct ac_vs_output_info *outinfo)
5599 {
5600 uint32_t param_count = 0;
5601 unsigned target;
5602 unsigned pos_idx, num_pos_exports = 0;
5603 struct ac_export_args args, pos_args[4] = {};
5604 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5605 int i;
5606
5607 if (ctx->options->key.has_multiview_view_index) {
5608 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5609 if(!*tmp_out) {
5610 for(unsigned i = 0; i < 4; ++i)
5611 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5612 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5613 }
5614
5615 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5616 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5617 }
5618
5619 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5620 sizeof(outinfo->vs_output_param_offset));
5621
5622 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5623 LLVMValueRef slots[8];
5624 unsigned j;
5625
5626 if (outinfo->cull_dist_mask)
5627 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5628
5629 i = VARYING_SLOT_CLIP_DIST0;
5630 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5631 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5632 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5633
5634 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5635 slots[i] = LLVMGetUndef(ctx->ac.f32);
5636
5637 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5638 target = V_008DFC_SQ_EXP_POS + 3;
5639 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5640 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5641 &args, sizeof(args));
5642 }
5643
5644 target = V_008DFC_SQ_EXP_POS + 2;
5645 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5646 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5647 &args, sizeof(args));
5648
5649 }
5650
5651 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5652 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5653 for (unsigned j = 0; j < 4; j++)
5654 pos_values[j] = LLVMBuildLoad(ctx->builder,
5655 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5656 }
5657 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5658
5659 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5660 outinfo->writes_pointsize = true;
5661 psize_value = LLVMBuildLoad(ctx->builder,
5662 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5663 }
5664
5665 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5666 outinfo->writes_layer = true;
5667 layer_value = LLVMBuildLoad(ctx->builder,
5668 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5669 }
5670
5671 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5672 outinfo->writes_viewport_index = true;
5673 viewport_index_value = LLVMBuildLoad(ctx->builder,
5674 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5675 }
5676
5677 if (outinfo->writes_pointsize ||
5678 outinfo->writes_layer ||
5679 outinfo->writes_viewport_index) {
5680 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5681 (outinfo->writes_layer == true ? 4 : 0));
5682 pos_args[1].valid_mask = 0;
5683 pos_args[1].done = 0;
5684 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5685 pos_args[1].compr = 0;
5686 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5687 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5688 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5689 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5690
5691 if (outinfo->writes_pointsize == true)
5692 pos_args[1].out[0] = psize_value;
5693 if (outinfo->writes_layer == true)
5694 pos_args[1].out[2] = layer_value;
5695 if (outinfo->writes_viewport_index == true) {
5696 if (ctx->options->chip_class >= GFX9) {
5697 /* GFX9 has the layer in out.z[10:0] and the viewport
5698 * index in out.z[19:16].
5699 */
5700 LLVMValueRef v = viewport_index_value;
5701 v = ac_to_integer(&ctx->ac, v);
5702 v = LLVMBuildShl(ctx->builder, v,
5703 LLVMConstInt(ctx->ac.i32, 16, false),
5704 "");
5705 v = LLVMBuildOr(ctx->builder, v,
5706 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5707
5708 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5709 pos_args[1].enabled_channels |= 1 << 2;
5710 } else {
5711 pos_args[1].out[3] = viewport_index_value;
5712 pos_args[1].enabled_channels |= 1 << 3;
5713 }
5714 }
5715 }
5716 for (i = 0; i < 4; i++) {
5717 if (pos_args[i].out[0])
5718 num_pos_exports++;
5719 }
5720
5721 pos_idx = 0;
5722 for (i = 0; i < 4; i++) {
5723 if (!pos_args[i].out[0])
5724 continue;
5725
5726 /* Specify the target we are exporting */
5727 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5728 if (pos_idx == num_pos_exports)
5729 pos_args[i].done = 1;
5730 ac_build_export(&ctx->ac, &pos_args[i]);
5731 }
5732
5733 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5734 LLVMValueRef values[4];
5735 if (!(ctx->output_mask & (1ull << i)))
5736 continue;
5737
5738 for (unsigned j = 0; j < 4; j++)
5739 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5740 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5741
5742 if (i == VARYING_SLOT_LAYER) {
5743 target = V_008DFC_SQ_EXP_PARAM + param_count;
5744 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5745 param_count++;
5746 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5747 target = V_008DFC_SQ_EXP_PARAM + param_count;
5748 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5749 param_count++;
5750 } else if (i >= VARYING_SLOT_VAR0) {
5751 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5752 target = V_008DFC_SQ_EXP_PARAM + param_count;
5753 outinfo->vs_output_param_offset[i] = param_count;
5754 param_count++;
5755 } else
5756 continue;
5757
5758 si_llvm_init_export_args(ctx, values, target, &args);
5759
5760 if (target >= V_008DFC_SQ_EXP_POS &&
5761 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5762 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5763 &args, sizeof(args));
5764 } else {
5765 ac_build_export(&ctx->ac, &args);
5766 }
5767 }
5768
5769 if (export_prim_id) {
5770 LLVMValueRef values[4];
5771 target = V_008DFC_SQ_EXP_PARAM + param_count;
5772 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5773 param_count++;
5774
5775 values[0] = ctx->vs_prim_id;
5776 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5777 ctx->shader_info->vs.vgpr_comp_cnt);
5778 for (unsigned j = 1; j < 4; j++)
5779 values[j] = ctx->ac.f32_0;
5780 si_llvm_init_export_args(ctx, values, target, &args);
5781 ac_build_export(&ctx->ac, &args);
5782 outinfo->export_prim_id = true;
5783 }
5784
5785 outinfo->pos_exports = num_pos_exports;
5786 outinfo->param_exports = param_count;
5787 }
5788
5789 static void
5790 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5791 struct ac_es_output_info *outinfo)
5792 {
5793 int j;
5794 uint64_t max_output_written = 0;
5795 LLVMValueRef lds_base = NULL;
5796
5797 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5798 int param_index;
5799 int length = 4;
5800
5801 if (!(ctx->output_mask & (1ull << i)))
5802 continue;
5803
5804 if (i == VARYING_SLOT_CLIP_DIST0)
5805 length = ctx->num_output_clips + ctx->num_output_culls;
5806
5807 param_index = shader_io_get_unique_index(i);
5808
5809 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5810 }
5811
5812 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5813
5814 if (ctx->ac.chip_class >= GFX9) {
5815 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5816 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5817 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5818 LLVMConstInt(ctx->ac.i32, 24, false),
5819 LLVMConstInt(ctx->ac.i32, 4, false), false);
5820 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5821 LLVMBuildMul(ctx->ac.builder, wave_idx,
5822 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5823 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5824 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5825 }
5826
5827 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5828 LLVMValueRef dw_addr;
5829 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5830 int param_index;
5831 int length = 4;
5832
5833 if (!(ctx->output_mask & (1ull << i)))
5834 continue;
5835
5836 if (i == VARYING_SLOT_CLIP_DIST0)
5837 length = ctx->num_output_clips + ctx->num_output_culls;
5838
5839 param_index = shader_io_get_unique_index(i);
5840
5841 if (lds_base) {
5842 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5843 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5844 "");
5845 }
5846 for (j = 0; j < length; j++) {
5847 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5848 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5849
5850 if (ctx->ac.chip_class >= GFX9) {
5851 ac_lds_store(&ctx->ac, dw_addr,
5852 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5853 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5854 } else {
5855 ac_build_buffer_store_dword(&ctx->ac,
5856 ctx->esgs_ring,
5857 out_val, 1,
5858 NULL, ctx->es2gs_offset,
5859 (4 * param_index + j) * 4,
5860 1, 1, true, true);
5861 }
5862 }
5863 }
5864 }
5865
5866 static void
5867 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5868 {
5869 LLVMValueRef vertex_id = ctx->rel_auto_id;
5870 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5871 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5872 vertex_dw_stride, "");
5873
5874 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5875 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5876 int length = 4;
5877
5878 if (!(ctx->output_mask & (1ull << i)))
5879 continue;
5880
5881 if (i == VARYING_SLOT_CLIP_DIST0)
5882 length = ctx->num_output_clips + ctx->num_output_culls;
5883 int param = shader_io_get_unique_index(i);
5884 mark_tess_output(ctx, false, param);
5885 if (length > 4)
5886 mark_tess_output(ctx, false, param + 1);
5887 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5888 LLVMConstInt(ctx->ac.i32, param * 4, false),
5889 "");
5890 for (unsigned j = 0; j < length; j++) {
5891 ac_lds_store(&ctx->ac, dw_addr,
5892 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5893 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5894 }
5895 }
5896 }
5897
5898 struct ac_build_if_state
5899 {
5900 struct nir_to_llvm_context *ctx;
5901 LLVMValueRef condition;
5902 LLVMBasicBlockRef entry_block;
5903 LLVMBasicBlockRef true_block;
5904 LLVMBasicBlockRef false_block;
5905 LLVMBasicBlockRef merge_block;
5906 };
5907
5908 static LLVMBasicBlockRef
5909 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5910 {
5911 LLVMBasicBlockRef current_block;
5912 LLVMBasicBlockRef next_block;
5913 LLVMBasicBlockRef new_block;
5914
5915 /* get current basic block */
5916 current_block = LLVMGetInsertBlock(ctx->builder);
5917
5918 /* chqeck if there's another block after this one */
5919 next_block = LLVMGetNextBasicBlock(current_block);
5920 if (next_block) {
5921 /* insert the new block before the next block */
5922 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5923 }
5924 else {
5925 /* append new block after current block */
5926 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5927 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5928 }
5929 return new_block;
5930 }
5931
5932 static void
5933 ac_nir_build_if(struct ac_build_if_state *ifthen,
5934 struct nir_to_llvm_context *ctx,
5935 LLVMValueRef condition)
5936 {
5937 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5938
5939 memset(ifthen, 0, sizeof *ifthen);
5940 ifthen->ctx = ctx;
5941 ifthen->condition = condition;
5942 ifthen->entry_block = block;
5943
5944 /* create endif/merge basic block for the phi functions */
5945 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5946
5947 /* create/insert true_block before merge_block */
5948 ifthen->true_block =
5949 LLVMInsertBasicBlockInContext(ctx->context,
5950 ifthen->merge_block,
5951 "if-true-block");
5952
5953 /* successive code goes into the true block */
5954 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5955 }
5956
5957 /**
5958 * End a conditional.
5959 */
5960 static void
5961 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5962 {
5963 LLVMBuilderRef builder = ifthen->ctx->builder;
5964
5965 /* Insert branch to the merge block from current block */
5966 LLVMBuildBr(builder, ifthen->merge_block);
5967
5968 /*
5969 * Now patch in the various branch instructions.
5970 */
5971
5972 /* Insert the conditional branch instruction at the end of entry_block */
5973 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5974 if (ifthen->false_block) {
5975 /* we have an else clause */
5976 LLVMBuildCondBr(builder, ifthen->condition,
5977 ifthen->true_block, ifthen->false_block);
5978 }
5979 else {
5980 /* no else clause */
5981 LLVMBuildCondBr(builder, ifthen->condition,
5982 ifthen->true_block, ifthen->merge_block);
5983 }
5984
5985 /* Resume building code at end of the ifthen->merge_block */
5986 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5987 }
5988
5989 static void
5990 write_tess_factors(struct nir_to_llvm_context *ctx)
5991 {
5992 unsigned stride, outer_comps, inner_comps;
5993 struct ac_build_if_state if_ctx, inner_if_ctx;
5994 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5995 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5996 unsigned tess_inner_index, tess_outer_index;
5997 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5998 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5999 int i;
6000 emit_barrier(ctx);
6001
6002 switch (ctx->options->key.tcs.primitive_mode) {
6003 case GL_ISOLINES:
6004 stride = 2;
6005 outer_comps = 2;
6006 inner_comps = 0;
6007 break;
6008 case GL_TRIANGLES:
6009 stride = 4;
6010 outer_comps = 3;
6011 inner_comps = 1;
6012 break;
6013 case GL_QUADS:
6014 stride = 6;
6015 outer_comps = 4;
6016 inner_comps = 2;
6017 break;
6018 default:
6019 return;
6020 }
6021
6022 ac_nir_build_if(&if_ctx, ctx,
6023 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6024 invocation_id, ctx->ac.i32_0, ""));
6025
6026 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6027 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6028
6029 mark_tess_output(ctx, true, tess_inner_index);
6030 mark_tess_output(ctx, true, tess_outer_index);
6031 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6032 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6033 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6034 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6035 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6036
6037 for (i = 0; i < 4; i++) {
6038 inner[i] = LLVMGetUndef(ctx->ac.i32);
6039 outer[i] = LLVMGetUndef(ctx->ac.i32);
6040 }
6041
6042 // LINES reverseal
6043 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6044 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6045 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6046 LLVMConstInt(ctx->ac.i32, 1, false), "");
6047 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6048 } else {
6049 for (i = 0; i < outer_comps; i++) {
6050 outer[i] = out[i] =
6051 ac_lds_load(&ctx->ac, lds_outer);
6052 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6053 LLVMConstInt(ctx->ac.i32, 1, false), "");
6054 }
6055 for (i = 0; i < inner_comps; i++) {
6056 inner[i] = out[outer_comps+i] =
6057 ac_lds_load(&ctx->ac, lds_inner);
6058 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6059 LLVMConstInt(ctx->ac.i32, 1, false), "");
6060 }
6061 }
6062
6063 /* Convert the outputs to vectors for stores. */
6064 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6065 vec1 = NULL;
6066
6067 if (stride > 4)
6068 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6069
6070
6071 buffer = ctx->hs_ring_tess_factor;
6072 tf_base = ctx->tess_factor_offset;
6073 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6074 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6075 unsigned tf_offset = 0;
6076
6077 if (ctx->options->chip_class <= VI) {
6078 ac_nir_build_if(&inner_if_ctx, ctx,
6079 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6080 rel_patch_id, ctx->ac.i32_0, ""));
6081
6082 /* Store the dynamic HS control word. */
6083 ac_build_buffer_store_dword(&ctx->ac, buffer,
6084 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6085 1, ctx->ac.i32_0, tf_base,
6086 0, 1, 0, true, false);
6087 tf_offset += 4;
6088
6089 ac_nir_build_endif(&inner_if_ctx);
6090 }
6091
6092 /* Store the tessellation factors. */
6093 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6094 MIN2(stride, 4), byteoffset, tf_base,
6095 tf_offset, 1, 0, true, false);
6096 if (vec1)
6097 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6098 stride - 4, byteoffset, tf_base,
6099 16 + tf_offset, 1, 0, true, false);
6100
6101 //store to offchip for TES to read - only if TES reads them
6102 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6103 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6104 LLVMValueRef tf_inner_offset;
6105 unsigned param_outer, param_inner;
6106
6107 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6108 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6109 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6110
6111 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6112 util_next_power_of_two(outer_comps));
6113
6114 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6115 outer_comps, tf_outer_offset,
6116 ctx->oc_lds, 0, 1, 0, true, false);
6117 if (inner_comps) {
6118 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6119 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6120 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6121
6122 inner_vec = inner_comps == 1 ? inner[0] :
6123 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6124 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6125 inner_comps, tf_inner_offset,
6126 ctx->oc_lds, 0, 1, 0, true, false);
6127 }
6128 }
6129 ac_nir_build_endif(&if_ctx);
6130 }
6131
6132 static void
6133 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6134 {
6135 write_tess_factors(ctx);
6136 }
6137
6138 static bool
6139 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6140 LLVMValueRef *color, unsigned param, bool is_last,
6141 struct ac_export_args *args)
6142 {
6143 /* Export */
6144 si_llvm_init_export_args(ctx, color, param,
6145 args);
6146
6147 if (is_last) {
6148 args->valid_mask = 1; /* whether the EXEC mask is valid */
6149 args->done = 1; /* DONE bit */
6150 } else if (!args->enabled_channels)
6151 return false; /* unnecessary NULL export */
6152
6153 return true;
6154 }
6155
6156 static void
6157 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6158 LLVMValueRef depth, LLVMValueRef stencil,
6159 LLVMValueRef samplemask)
6160 {
6161 struct ac_export_args args;
6162
6163 args.enabled_channels = 0;
6164 args.valid_mask = 1;
6165 args.done = 1;
6166 args.target = V_008DFC_SQ_EXP_MRTZ;
6167 args.compr = false;
6168
6169 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6170 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6171 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6172 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6173
6174 if (depth) {
6175 args.out[0] = depth;
6176 args.enabled_channels |= 0x1;
6177 }
6178
6179 if (stencil) {
6180 args.out[1] = stencil;
6181 args.enabled_channels |= 0x2;
6182 }
6183
6184 if (samplemask) {
6185 args.out[2] = samplemask;
6186 args.enabled_channels |= 0x4;
6187 }
6188
6189 /* SI (except OLAND and HAINAN) has a bug that it only looks
6190 * at the X writemask component. */
6191 if (ctx->options->chip_class == SI &&
6192 ctx->options->family != CHIP_OLAND &&
6193 ctx->options->family != CHIP_HAINAN)
6194 args.enabled_channels |= 0x1;
6195
6196 ac_build_export(&ctx->ac, &args);
6197 }
6198
6199 static void
6200 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6201 {
6202 unsigned index = 0;
6203 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6204 struct ac_export_args color_args[8];
6205
6206 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6207 LLVMValueRef values[4];
6208
6209 if (!(ctx->output_mask & (1ull << i)))
6210 continue;
6211
6212 if (i == FRAG_RESULT_DEPTH) {
6213 ctx->shader_info->fs.writes_z = true;
6214 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6215 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6216 } else if (i == FRAG_RESULT_STENCIL) {
6217 ctx->shader_info->fs.writes_stencil = true;
6218 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6219 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6220 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6221 ctx->shader_info->fs.writes_sample_mask = true;
6222 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6223 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6224 } else {
6225 bool last = false;
6226 for (unsigned j = 0; j < 4; j++)
6227 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6228 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6229
6230 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6231 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6232
6233 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6234 if (ret)
6235 index++;
6236 }
6237 }
6238
6239 for (unsigned i = 0; i < index; i++)
6240 ac_build_export(&ctx->ac, &color_args[i]);
6241 if (depth || stencil || samplemask)
6242 si_export_mrt_z(ctx, depth, stencil, samplemask);
6243 else if (!index) {
6244 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6245 ac_build_export(&ctx->ac, &color_args[0]);
6246 }
6247
6248 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6249 }
6250
6251 static void
6252 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6253 {
6254 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6255 }
6256
6257 static void
6258 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6259 LLVMValueRef *addrs)
6260 {
6261 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6262
6263 switch (ctx->stage) {
6264 case MESA_SHADER_VERTEX:
6265 if (ctx->options->key.vs.as_ls)
6266 handle_ls_outputs_post(ctx);
6267 else if (ctx->options->key.vs.as_es)
6268 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6269 else
6270 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6271 &ctx->shader_info->vs.outinfo);
6272 break;
6273 case MESA_SHADER_FRAGMENT:
6274 handle_fs_outputs_post(ctx);
6275 break;
6276 case MESA_SHADER_GEOMETRY:
6277 emit_gs_epilogue(ctx);
6278 break;
6279 case MESA_SHADER_TESS_CTRL:
6280 handle_tcs_outputs_post(ctx);
6281 break;
6282 case MESA_SHADER_TESS_EVAL:
6283 if (ctx->options->key.tes.as_es)
6284 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6285 else
6286 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6287 &ctx->shader_info->tes.outinfo);
6288 break;
6289 default:
6290 break;
6291 }
6292 }
6293
6294 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6295 {
6296 LLVMPassManagerRef passmgr;
6297 /* Create the pass manager */
6298 passmgr = LLVMCreateFunctionPassManagerForModule(
6299 ctx->module);
6300
6301 /* This pass should eliminate all the load and store instructions */
6302 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6303
6304 /* Add some optimization passes */
6305 LLVMAddScalarReplAggregatesPass(passmgr);
6306 LLVMAddLICMPass(passmgr);
6307 LLVMAddAggressiveDCEPass(passmgr);
6308 LLVMAddCFGSimplificationPass(passmgr);
6309 LLVMAddInstructionCombiningPass(passmgr);
6310
6311 /* Run the pass */
6312 LLVMInitializeFunctionPassManager(passmgr);
6313 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6314 LLVMFinalizeFunctionPassManager(passmgr);
6315
6316 LLVMDisposeBuilder(ctx->builder);
6317 LLVMDisposePassManager(passmgr);
6318 }
6319
6320 static void
6321 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6322 {
6323 struct ac_vs_output_info *outinfo;
6324
6325 switch (ctx->stage) {
6326 case MESA_SHADER_FRAGMENT:
6327 case MESA_SHADER_COMPUTE:
6328 case MESA_SHADER_TESS_CTRL:
6329 case MESA_SHADER_GEOMETRY:
6330 return;
6331 case MESA_SHADER_VERTEX:
6332 if (ctx->options->key.vs.as_ls ||
6333 ctx->options->key.vs.as_es)
6334 return;
6335 outinfo = &ctx->shader_info->vs.outinfo;
6336 break;
6337 case MESA_SHADER_TESS_EVAL:
6338 if (ctx->options->key.vs.as_es)
6339 return;
6340 outinfo = &ctx->shader_info->tes.outinfo;
6341 break;
6342 default:
6343 unreachable("Unhandled shader type");
6344 }
6345
6346 ac_optimize_vs_outputs(&ctx->ac,
6347 ctx->main_function,
6348 outinfo->vs_output_param_offset,
6349 VARYING_SLOT_MAX,
6350 &outinfo->param_exports);
6351 }
6352
6353 static void
6354 ac_setup_rings(struct nir_to_llvm_context *ctx)
6355 {
6356 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6357 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6358 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6359 }
6360
6361 if (ctx->is_gs_copy_shader) {
6362 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6363 }
6364 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6365 LLVMValueRef tmp;
6366 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6367 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6368
6369 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6370
6371 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6372 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6373 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6374 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6375 }
6376
6377 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6378 ctx->stage == MESA_SHADER_TESS_EVAL) {
6379 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6380 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6381 }
6382 }
6383
6384 static unsigned
6385 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6386 const struct nir_shader *nir)
6387 {
6388 switch (nir->info.stage) {
6389 case MESA_SHADER_TESS_CTRL:
6390 return chip_class >= CIK ? 128 : 64;
6391 case MESA_SHADER_GEOMETRY:
6392 return chip_class >= GFX9 ? 128 : 64;
6393 case MESA_SHADER_COMPUTE:
6394 break;
6395 default:
6396 return 0;
6397 }
6398
6399 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6400 nir->info.cs.local_size[1] *
6401 nir->info.cs.local_size[2];
6402 return max_workgroup_size;
6403 }
6404
6405 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6406 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6407 {
6408 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6409 LLVMConstInt(ctx->ac.i32, 8, false),
6410 LLVMConstInt(ctx->ac.i32, 8, false), false);
6411 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6412 LLVMConstInt(ctx->ac.i32, 0, false), "");
6413 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6414 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6415 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6416 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6417 }
6418
6419 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6420 {
6421 for(int i = 5; i >= 0; --i) {
6422 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6423 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6424 LLVMConstInt(ctx->ac.i32, 16, false), false);
6425 }
6426
6427 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6428 LLVMConstInt(ctx->ac.i32, 16, false),
6429 LLVMConstInt(ctx->ac.i32, 8, false), false);
6430 }
6431
6432 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6433 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6434 {
6435 struct ac_nir_context ctx = {};
6436 struct nir_function *func;
6437
6438 ctx.ac = *ac;
6439 ctx.abi = abi;
6440
6441 ctx.nctx = nctx;
6442 if (nctx)
6443 nctx->nir = &ctx;
6444
6445 ctx.stage = nir->info.stage;
6446
6447 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6448
6449 nir_foreach_variable(variable, &nir->outputs)
6450 handle_shader_output_decl(&ctx, nir, variable);
6451
6452 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6453 _mesa_key_pointer_equal);
6454 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6455 _mesa_key_pointer_equal);
6456 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6457 _mesa_key_pointer_equal);
6458
6459 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6460
6461 setup_locals(&ctx, func);
6462
6463 if (nir->info.stage == MESA_SHADER_COMPUTE)
6464 setup_shared(&ctx, nir);
6465
6466 visit_cf_list(&ctx, &func->impl->body);
6467 phi_post_pass(&ctx);
6468
6469 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6470 ctx.outputs);
6471
6472 free(ctx.locals);
6473 ralloc_free(ctx.defs);
6474 ralloc_free(ctx.phis);
6475 ralloc_free(ctx.vars);
6476
6477 if (nctx)
6478 nctx->nir = NULL;
6479 }
6480
6481 static
6482 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6483 struct nir_shader *const *shaders,
6484 int shader_count,
6485 struct ac_shader_variant_info *shader_info,
6486 const struct ac_nir_compiler_options *options)
6487 {
6488 struct nir_to_llvm_context ctx = {0};
6489 unsigned i;
6490 ctx.options = options;
6491 ctx.shader_info = shader_info;
6492 ctx.context = LLVMContextCreate();
6493 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6494
6495 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6496 ctx.ac.module = ctx.module;
6497 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6498
6499 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6500 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6501 LLVMSetDataLayout(ctx.module, data_layout_str);
6502 LLVMDisposeTargetData(data_layout);
6503 LLVMDisposeMessage(data_layout_str);
6504
6505 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6506 ctx.ac.builder = ctx.builder;
6507
6508 memset(shader_info, 0, sizeof(*shader_info));
6509
6510 for(int i = 0; i < shader_count; ++i)
6511 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6512
6513 for (i = 0; i < AC_UD_MAX_SETS; i++)
6514 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6515 for (i = 0; i < AC_UD_MAX_UD; i++)
6516 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6517
6518 ctx.max_workgroup_size = 0;
6519 for (int i = 0; i < shader_count; ++i) {
6520 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6521 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6522 shaders[i]));
6523 }
6524
6525 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6526 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6527
6528 ctx.abi.inputs = &ctx.inputs[0];
6529 ctx.abi.emit_outputs = handle_shader_outputs_post;
6530 ctx.abi.emit_vertex = visit_emit_vertex;
6531 ctx.abi.load_ssbo = radv_load_ssbo;
6532 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6533 ctx.abi.clamp_shadow_reference = false;
6534
6535 if (shader_count >= 2)
6536 ac_init_exec_full_mask(&ctx.ac);
6537
6538 if (ctx.ac.chip_class == GFX9 &&
6539 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6540 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6541
6542 for(int i = 0; i < shader_count; ++i) {
6543 ctx.stage = shaders[i]->info.stage;
6544 ctx.output_mask = 0;
6545 ctx.tess_outputs_written = 0;
6546 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6547 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6548
6549 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6550 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6551
6552 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6553 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6554 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6555 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6556 if (shader_info->info.vs.needs_instance_id) {
6557 ctx.shader_info->vs.vgpr_comp_cnt =
6558 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6559 }
6560 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6561 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6562 }
6563
6564 if (i)
6565 emit_barrier(&ctx);
6566
6567 ac_setup_rings(&ctx);
6568
6569 LLVMBasicBlockRef merge_block;
6570 if (shader_count >= 2) {
6571 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6572 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6573 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6574
6575 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6576 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6577 LLVMConstInt(ctx.ac.i32, 8, false), false);
6578 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6579 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6580 thread_id, count, "");
6581 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6582
6583 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6584 }
6585
6586 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6587 handle_fs_inputs(&ctx, shaders[i]);
6588 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6589 handle_vs_inputs(&ctx, shaders[i]);
6590 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6591 prepare_gs_input_vgprs(&ctx);
6592
6593 nir_foreach_variable(variable, &shaders[i]->outputs)
6594 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6595
6596 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6597
6598 if (shader_count >= 2) {
6599 LLVMBuildBr(ctx.ac.builder, merge_block);
6600 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6601 }
6602
6603 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6604 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6605 shaders[i]->info.cull_distance_array_size > 4;
6606 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6607 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6608 shaders[i]->info.gs.vertices_out;
6609 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6610 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6611 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6612 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6613 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6614 }
6615 }
6616
6617 LLVMBuildRetVoid(ctx.builder);
6618
6619 ac_llvm_finalize_module(&ctx);
6620
6621 if (shader_count == 1)
6622 ac_nir_eliminate_const_vs_outputs(&ctx);
6623
6624 return ctx.module;
6625 }
6626
6627 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6628 {
6629 unsigned *retval = (unsigned *)context;
6630 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6631 char *description = LLVMGetDiagInfoDescription(di);
6632
6633 if (severity == LLVMDSError) {
6634 *retval = 1;
6635 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6636 description);
6637 }
6638
6639 LLVMDisposeMessage(description);
6640 }
6641
6642 static unsigned ac_llvm_compile(LLVMModuleRef M,
6643 struct ac_shader_binary *binary,
6644 LLVMTargetMachineRef tm)
6645 {
6646 unsigned retval = 0;
6647 char *err;
6648 LLVMContextRef llvm_ctx;
6649 LLVMMemoryBufferRef out_buffer;
6650 unsigned buffer_size;
6651 const char *buffer_data;
6652 LLVMBool mem_err;
6653
6654 /* Setup Diagnostic Handler*/
6655 llvm_ctx = LLVMGetModuleContext(M);
6656
6657 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6658 &retval);
6659
6660 /* Compile IR*/
6661 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6662 &err, &out_buffer);
6663
6664 /* Process Errors/Warnings */
6665 if (mem_err) {
6666 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6667 free(err);
6668 retval = 1;
6669 goto out;
6670 }
6671
6672 /* Extract Shader Code*/
6673 buffer_size = LLVMGetBufferSize(out_buffer);
6674 buffer_data = LLVMGetBufferStart(out_buffer);
6675
6676 ac_elf_read(buffer_data, buffer_size, binary);
6677
6678 /* Clean up */
6679 LLVMDisposeMemoryBuffer(out_buffer);
6680
6681 out:
6682 return retval;
6683 }
6684
6685 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6686 LLVMModuleRef llvm_module,
6687 struct ac_shader_binary *binary,
6688 struct ac_shader_config *config,
6689 struct ac_shader_variant_info *shader_info,
6690 gl_shader_stage stage,
6691 bool dump_shader, bool supports_spill)
6692 {
6693 if (dump_shader)
6694 ac_dump_module(llvm_module);
6695
6696 memset(binary, 0, sizeof(*binary));
6697 int v = ac_llvm_compile(llvm_module, binary, tm);
6698 if (v) {
6699 fprintf(stderr, "compile failed\n");
6700 }
6701
6702 if (dump_shader)
6703 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6704
6705 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6706
6707 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6708 LLVMDisposeModule(llvm_module);
6709 LLVMContextDispose(ctx);
6710
6711 if (stage == MESA_SHADER_FRAGMENT) {
6712 shader_info->num_input_vgprs = 0;
6713 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6714 shader_info->num_input_vgprs += 2;
6715 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6716 shader_info->num_input_vgprs += 2;
6717 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6718 shader_info->num_input_vgprs += 2;
6719 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6720 shader_info->num_input_vgprs += 3;
6721 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6722 shader_info->num_input_vgprs += 2;
6723 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6724 shader_info->num_input_vgprs += 2;
6725 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6726 shader_info->num_input_vgprs += 2;
6727 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6728 shader_info->num_input_vgprs += 1;
6729 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6730 shader_info->num_input_vgprs += 1;
6731 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6732 shader_info->num_input_vgprs += 1;
6733 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6734 shader_info->num_input_vgprs += 1;
6735 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6736 shader_info->num_input_vgprs += 1;
6737 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6738 shader_info->num_input_vgprs += 1;
6739 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6740 shader_info->num_input_vgprs += 1;
6741 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6742 shader_info->num_input_vgprs += 1;
6743 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6744 shader_info->num_input_vgprs += 1;
6745 }
6746 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6747
6748 /* +3 for scratch wave offset and VCC */
6749 config->num_sgprs = MAX2(config->num_sgprs,
6750 shader_info->num_input_sgprs + 3);
6751 }
6752
6753 static void
6754 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6755 {
6756 switch (nir->info.stage) {
6757 case MESA_SHADER_COMPUTE:
6758 for (int i = 0; i < 3; ++i)
6759 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6760 break;
6761 case MESA_SHADER_FRAGMENT:
6762 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6763 break;
6764 case MESA_SHADER_GEOMETRY:
6765 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6766 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6767 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6768 shader_info->gs.invocations = nir->info.gs.invocations;
6769 break;
6770 case MESA_SHADER_TESS_EVAL:
6771 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6772 shader_info->tes.spacing = nir->info.tess.spacing;
6773 shader_info->tes.ccw = nir->info.tess.ccw;
6774 shader_info->tes.point_mode = nir->info.tess.point_mode;
6775 shader_info->tes.as_es = options->key.tes.as_es;
6776 break;
6777 case MESA_SHADER_TESS_CTRL:
6778 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6779 break;
6780 case MESA_SHADER_VERTEX:
6781 shader_info->vs.as_es = options->key.vs.as_es;
6782 shader_info->vs.as_ls = options->key.vs.as_ls;
6783 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6784 if (options->key.vs.as_ls)
6785 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6786 break;
6787 default:
6788 break;
6789 }
6790 }
6791
6792 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6793 struct ac_shader_binary *binary,
6794 struct ac_shader_config *config,
6795 struct ac_shader_variant_info *shader_info,
6796 struct nir_shader *const *nir,
6797 int nir_count,
6798 const struct ac_nir_compiler_options *options,
6799 bool dump_shader)
6800 {
6801
6802 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6803 options);
6804
6805 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6806 for (int i = 0; i < nir_count; ++i)
6807 ac_fill_shader_info(shader_info, nir[i], options);
6808 }
6809
6810 static void
6811 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6812 {
6813 LLVMValueRef args[9];
6814 args[0] = ctx->gsvs_ring;
6815 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6816 args[3] = ctx->ac.i32_0;
6817 args[4] = ctx->ac.i32_1; /* OFFEN */
6818 args[5] = ctx->ac.i32_0; /* IDXEN */
6819 args[6] = ctx->ac.i32_1; /* GLC */
6820 args[7] = ctx->ac.i32_1; /* SLC */
6821 args[8] = ctx->ac.i32_0; /* TFE */
6822
6823 int idx = 0;
6824
6825 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6826 int length = 4;
6827 int slot = idx;
6828 int slot_inc = 1;
6829 if (!(ctx->output_mask & (1ull << i)))
6830 continue;
6831
6832 if (i == VARYING_SLOT_CLIP_DIST0) {
6833 /* unpack clip and cull from a single set of slots */
6834 length = ctx->num_output_clips + ctx->num_output_culls;
6835 if (length > 4)
6836 slot_inc = 2;
6837 }
6838
6839 for (unsigned j = 0; j < length; j++) {
6840 LLVMValueRef value;
6841 args[2] = LLVMConstInt(ctx->ac.i32,
6842 (slot * 4 + j) *
6843 ctx->gs_max_out_vertices * 16 * 4, false);
6844
6845 value = ac_build_intrinsic(&ctx->ac,
6846 "llvm.SI.buffer.load.dword.i32.i32",
6847 ctx->ac.i32, args, 9,
6848 AC_FUNC_ATTR_READONLY |
6849 AC_FUNC_ATTR_LEGACY);
6850
6851 LLVMBuildStore(ctx->builder,
6852 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6853 }
6854 idx += slot_inc;
6855 }
6856 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6857 }
6858
6859 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6860 struct nir_shader *geom_shader,
6861 struct ac_shader_binary *binary,
6862 struct ac_shader_config *config,
6863 struct ac_shader_variant_info *shader_info,
6864 const struct ac_nir_compiler_options *options,
6865 bool dump_shader)
6866 {
6867 struct nir_to_llvm_context ctx = {0};
6868 ctx.context = LLVMContextCreate();
6869 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6870 ctx.options = options;
6871 ctx.shader_info = shader_info;
6872
6873 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6874 ctx.ac.module = ctx.module;
6875
6876 ctx.is_gs_copy_shader = true;
6877 LLVMSetTarget(ctx.module, "amdgcn--");
6878
6879 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6880 ctx.ac.builder = ctx.builder;
6881 ctx.stage = MESA_SHADER_VERTEX;
6882
6883 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6884
6885 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6886 ac_setup_rings(&ctx);
6887
6888 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6889 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6890
6891 struct ac_nir_context nir_ctx = {};
6892 nir_ctx.ac = ctx.ac;
6893 nir_ctx.abi = &ctx.abi;
6894
6895 nir_ctx.nctx = &ctx;
6896 ctx.nir = &nir_ctx;
6897
6898 nir_foreach_variable(variable, &geom_shader->outputs) {
6899 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6900 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6901 }
6902
6903 ac_gs_copy_shader_emit(&ctx);
6904
6905 ctx.nir = NULL;
6906
6907 LLVMBuildRetVoid(ctx.builder);
6908
6909 ac_llvm_finalize_module(&ctx);
6910
6911 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6912 MESA_SHADER_VERTEX,
6913 dump_shader, options->supports_spill);
6914 }