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ac: add load_tes_inputs() to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
547 struct user_sgpr_info *user_sgpr_info)
548 {
549 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
550
551 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
552 if (ctx->stage == MESA_SHADER_GEOMETRY ||
553 ctx->stage == MESA_SHADER_VERTEX ||
554 ctx->stage == MESA_SHADER_TESS_CTRL ||
555 ctx->stage == MESA_SHADER_TESS_EVAL ||
556 ctx->is_gs_copy_shader)
557 user_sgpr_info->need_ring_offsets = true;
558
559 if (ctx->stage == MESA_SHADER_FRAGMENT &&
560 ctx->shader_info->info.ps.needs_sample_positions)
561 user_sgpr_info->need_ring_offsets = true;
562
563 /* 2 user sgprs will nearly always be allocated for scratch/rings */
564 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
565 user_sgpr_info->sgpr_count += 2;
566 }
567
568 switch (ctx->stage) {
569 case MESA_SHADER_COMPUTE:
570 if (ctx->shader_info->info.cs.uses_grid_size)
571 user_sgpr_info->sgpr_count += 3;
572 break;
573 case MESA_SHADER_FRAGMENT:
574 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
575 break;
576 case MESA_SHADER_VERTEX:
577 if (!ctx->is_gs_copy_shader) {
578 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
579 if (ctx->shader_info->info.vs.needs_draw_id) {
580 user_sgpr_info->sgpr_count += 3;
581 } else {
582 user_sgpr_info->sgpr_count += 2;
583 }
584 }
585 if (ctx->options->key.vs.as_ls)
586 user_sgpr_info->sgpr_count++;
587 break;
588 case MESA_SHADER_TESS_CTRL:
589 user_sgpr_info->sgpr_count += 4;
590 break;
591 case MESA_SHADER_TESS_EVAL:
592 user_sgpr_info->sgpr_count += 1;
593 break;
594 case MESA_SHADER_GEOMETRY:
595 user_sgpr_info->sgpr_count += 2;
596 break;
597 default:
598 break;
599 }
600
601 if (ctx->shader_info->info.needs_push_constants)
602 user_sgpr_info->sgpr_count += 2;
603
604 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
605 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
606 user_sgpr_info->sgpr_count += 2;
607 user_sgpr_info->indirect_all_descriptor_sets = true;
608 } else {
609 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
610 }
611 }
612
613 static void
614 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
615 gl_shader_stage stage,
616 bool has_previous_stage,
617 gl_shader_stage previous_stage,
618 const struct user_sgpr_info *user_sgpr_info,
619 struct arg_info *args,
620 LLVMValueRef *desc_sets)
621 {
622 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
623 unsigned num_sets = ctx->options->layout ?
624 ctx->options->layout->num_sets : 0;
625 unsigned stage_mask = 1 << stage;
626
627 if (has_previous_stage)
628 stage_mask |= 1 << previous_stage;
629
630 /* 1 for each descriptor set */
631 if (!user_sgpr_info->indirect_all_descriptor_sets) {
632 for (unsigned i = 0; i < num_sets; ++i) {
633 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
634 add_array_arg(args, type,
635 &ctx->descriptor_sets[i]);
636 }
637 }
638 } else {
639 add_array_arg(args, const_array(type, 32), desc_sets);
640 }
641
642 if (ctx->shader_info->info.needs_push_constants) {
643 /* 1 for push constants and dynamic descriptors */
644 add_array_arg(args, type, &ctx->push_constants);
645 }
646 }
647
648 static void
649 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
650 gl_shader_stage stage,
651 bool has_previous_stage,
652 gl_shader_stage previous_stage,
653 struct arg_info *args)
654 {
655 if (!ctx->is_gs_copy_shader &&
656 (stage == MESA_SHADER_VERTEX ||
657 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
658 if (ctx->shader_info->info.vs.has_vertex_buffers) {
659 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
660 &ctx->vertex_buffers);
661 }
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
664 if (ctx->shader_info->info.vs.needs_draw_id) {
665 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
666 }
667 }
668 }
669
670 static void
671 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
672 {
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
674 if (!ctx->is_gs_copy_shader) {
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
678 }
679 }
680
681 static void
682 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
683 {
684 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
685 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
686 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
687 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
688 }
689
690 static void
691 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
692 bool has_previous_stage, gl_shader_stage previous_stage,
693 const struct user_sgpr_info *user_sgpr_info,
694 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
695 {
696 unsigned num_sets = ctx->options->layout ?
697 ctx->options->layout->num_sets : 0;
698 unsigned stage_mask = 1 << stage;
699
700 if (has_previous_stage)
701 stage_mask |= 1 << previous_stage;
702
703 if (!user_sgpr_info->indirect_all_descriptor_sets) {
704 for (unsigned i = 0; i < num_sets; ++i) {
705 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
706 set_loc_desc(ctx, i, user_sgpr_idx, 0);
707 } else
708 ctx->descriptor_sets[i] = NULL;
709 }
710 } else {
711 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
712 user_sgpr_idx, 2);
713
714 for (unsigned i = 0; i < num_sets; ++i) {
715 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
716 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
717 ctx->descriptor_sets[i] =
718 ac_build_load_to_sgpr(&ctx->ac,
719 desc_sets,
720 LLVMConstInt(ctx->ac.i32, i, false));
721
722 } else
723 ctx->descriptor_sets[i] = NULL;
724 }
725 ctx->shader_info->need_indirect_descriptor_sets = true;
726 }
727
728 if (ctx->shader_info->info.needs_push_constants) {
729 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
730 }
731 }
732
733 static void
734 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
735 gl_shader_stage stage, bool has_previous_stage,
736 gl_shader_stage previous_stage,
737 uint8_t *user_sgpr_idx)
738 {
739 if (!ctx->is_gs_copy_shader &&
740 (stage == MESA_SHADER_VERTEX ||
741 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
742 if (ctx->shader_info->info.vs.has_vertex_buffers) {
743 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
744 user_sgpr_idx, 2);
745 }
746
747 unsigned vs_num = 2;
748 if (ctx->shader_info->info.vs.needs_draw_id)
749 vs_num++;
750
751 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
752 user_sgpr_idx, vs_num);
753 }
754 }
755
756 static void create_function(struct nir_to_llvm_context *ctx,
757 gl_shader_stage stage,
758 bool has_previous_stage,
759 gl_shader_stage previous_stage)
760 {
761 uint8_t user_sgpr_idx;
762 struct user_sgpr_info user_sgpr_info;
763 struct arg_info args = {};
764 LLVMValueRef desc_sets;
765
766 allocate_user_sgprs(ctx, &user_sgpr_info);
767
768 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
769 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
770 &ctx->ring_offsets);
771 }
772
773 switch (stage) {
774 case MESA_SHADER_COMPUTE:
775 declare_global_input_sgprs(ctx, stage, has_previous_stage,
776 previous_stage, &user_sgpr_info,
777 &args, &desc_sets);
778
779 if (ctx->shader_info->info.cs.uses_grid_size) {
780 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
781 &ctx->num_work_groups);
782 }
783
784 for (int i = 0; i < 3; i++) {
785 ctx->workgroup_ids[i] = NULL;
786 if (ctx->shader_info->info.cs.uses_block_id[i]) {
787 add_arg(&args, ARG_SGPR, ctx->ac.i32,
788 &ctx->workgroup_ids[i]);
789 }
790 }
791
792 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
793 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
794 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
795 &ctx->local_invocation_ids);
796 break;
797 case MESA_SHADER_VERTEX:
798 declare_global_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &user_sgpr_info,
800 &args, &desc_sets);
801 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
802 previous_stage, &args);
803
804 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
806 if (ctx->options->key.vs.as_es)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->es2gs_offset);
809 else if (ctx->options->key.vs.as_ls)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->ls_out_layout);
812
813 declare_vs_input_vgprs(ctx, &args);
814 break;
815 case MESA_SHADER_TESS_CTRL:
816 if (has_previous_stage) {
817 // First 6 system regs
818 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->merged_wave_info);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->tess_factor_offset);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
825 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
826 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
827
828 declare_global_input_sgprs(ctx, stage,
829 has_previous_stage,
830 previous_stage,
831 &user_sgpr_info, &args,
832 &desc_sets);
833 declare_vs_specific_input_sgprs(ctx, stage,
834 has_previous_stage,
835 previous_stage, &args);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->ls_out_layout);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_offchip_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_out_offsets);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_in_layout);
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->view_index);
851
852 add_arg(&args, ARG_VGPR, ctx->ac.i32,
853 &ctx->tcs_patch_id);
854 add_arg(&args, ARG_VGPR, ctx->ac.i32,
855 &ctx->tcs_rel_ids);
856
857 declare_vs_input_vgprs(ctx, &args);
858 } else {
859 declare_global_input_sgprs(ctx, stage,
860 has_previous_stage,
861 previous_stage,
862 &user_sgpr_info, &args,
863 &desc_sets);
864
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_offchip_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_out_offsets);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_in_layout);
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->view_index);
876
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tess_factor_offset);
880 add_arg(&args, ARG_VGPR, ctx->ac.i32,
881 &ctx->tcs_patch_id);
882 add_arg(&args, ARG_VGPR, ctx->ac.i32,
883 &ctx->tcs_rel_ids);
884 }
885 break;
886 case MESA_SHADER_TESS_EVAL:
887 declare_global_input_sgprs(ctx, stage, has_previous_stage,
888 previous_stage, &user_sgpr_info,
889 &args, &desc_sets);
890
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
892 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
894
895 if (ctx->options->key.tes.as_es) {
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->es2gs_offset);
900 } else {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 }
904 declare_tes_input_vgprs(ctx, &args);
905 break;
906 case MESA_SHADER_GEOMETRY:
907 if (has_previous_stage) {
908 // First 6 system regs
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->gs2vs_offset);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->merged_wave_info);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
914
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918
919 declare_global_input_sgprs(ctx, stage,
920 has_previous_stage,
921 previous_stage,
922 &user_sgpr_info, &args,
923 &desc_sets);
924
925 if (previous_stage == MESA_SHADER_TESS_EVAL) {
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->tcs_offchip_layout);
928 } else {
929 declare_vs_specific_input_sgprs(ctx, stage,
930 has_previous_stage,
931 previous_stage,
932 &args);
933 }
934
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_ring_stride);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->gsvs_num_entries);
939 if (ctx->shader_info->info.needs_multiview_view_index)
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->view_index);
942
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[0]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[2]);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_prim_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->abi.gs_invocation_id);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[4]);
953
954 if (previous_stage == MESA_SHADER_VERTEX) {
955 declare_vs_input_vgprs(ctx, &args);
956 } else {
957 declare_tes_input_vgprs(ctx, &args);
958 }
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_ring_stride);
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->gsvs_num_entries);
970 if (ctx->shader_info->info.needs_multiview_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->view_index);
973
974 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
975 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[0]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[1]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_prim_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[2]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[3]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[5]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->abi.gs_invocation_id);
992 }
993 break;
994 case MESA_SHADER_FRAGMENT:
995 declare_global_input_sgprs(ctx, stage, has_previous_stage,
996 previous_stage, &user_sgpr_info,
997 &args, &desc_sets);
998
999 if (ctx->shader_info->info.ps.needs_sample_positions)
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1001 &ctx->sample_pos_offset);
1002
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1020 break;
1021 default:
1022 unreachable("Shader stage not implemented");
1023 }
1024
1025 ctx->main_function = create_llvm_function(
1026 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1027 ctx->max_workgroup_size,
1028 ctx->options->unsafe_math);
1029 set_llvm_calling_convention(ctx->main_function, stage);
1030
1031
1032 ctx->shader_info->num_input_vgprs = 0;
1033 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1034
1035 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1036
1037 if (ctx->stage != MESA_SHADER_FRAGMENT)
1038 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1039
1040 assign_arguments(ctx->main_function, &args);
1041
1042 user_sgpr_idx = 0;
1043
1044 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1045 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1046 &user_sgpr_idx, 2);
1047 if (ctx->options->supports_spill) {
1048 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1049 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1050 NULL, 0, AC_FUNC_ATTR_READNONE);
1051 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1052 const_array(ctx->ac.v4i32, 16), "");
1053 }
1054 }
1055
1056 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1057 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1058 if (has_previous_stage)
1059 user_sgpr_idx = 0;
1060
1061 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1062 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1063
1064 switch (stage) {
1065 case MESA_SHADER_COMPUTE:
1066 if (ctx->shader_info->info.cs.uses_grid_size) {
1067 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1068 &user_sgpr_idx, 3);
1069 }
1070 break;
1071 case MESA_SHADER_VERTEX:
1072 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1073 previous_stage, &user_sgpr_idx);
1074 if (ctx->view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 if (ctx->options->key.vs.as_ls) {
1077 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1078 &user_sgpr_idx, 1);
1079 }
1080 if (ctx->options->key.vs.as_ls)
1081 ac_declare_lds_as_pointer(&ctx->ac);
1082 break;
1083 case MESA_SHADER_TESS_CTRL:
1084 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1085 previous_stage, &user_sgpr_idx);
1086 if (has_previous_stage)
1087 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1088 &user_sgpr_idx, 1);
1089 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1090 if (ctx->view_index)
1091 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1092 ac_declare_lds_as_pointer(&ctx->ac);
1093 break;
1094 case MESA_SHADER_TESS_EVAL:
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 break;
1099 case MESA_SHADER_GEOMETRY:
1100 if (has_previous_stage) {
1101 if (previous_stage == MESA_SHADER_VERTEX)
1102 set_vs_specific_input_locs(ctx, stage,
1103 has_previous_stage,
1104 previous_stage,
1105 &user_sgpr_idx);
1106 else
1107 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1108 &user_sgpr_idx, 1);
1109 }
1110 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1111 &user_sgpr_idx, 2);
1112 if (ctx->view_index)
1113 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1114 if (has_previous_stage)
1115 ac_declare_lds_as_pointer(&ctx->ac);
1116 break;
1117 case MESA_SHADER_FRAGMENT:
1118 if (ctx->shader_info->info.ps.needs_sample_positions) {
1119 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1120 &user_sgpr_idx, 1);
1121 }
1122 break;
1123 default:
1124 unreachable("Shader stage not implemented");
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static int get_llvm_num_components(LLVMValueRef value)
1131 {
1132 LLVMTypeRef type = LLVMTypeOf(value);
1133 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1134 ? LLVMGetVectorSize(type)
1135 : 1;
1136 return num_components;
1137 }
1138
1139 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1140 LLVMValueRef value,
1141 int index)
1142 {
1143 int count = get_llvm_num_components(value);
1144
1145 if (count == 1)
1146 return value;
1147
1148 return LLVMBuildExtractElement(ac->builder, value,
1149 LLVMConstInt(ac->i32, index, false), "");
1150 }
1151
1152 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1153 LLVMValueRef value, unsigned count)
1154 {
1155 unsigned num_components = get_llvm_num_components(value);
1156 if (count == num_components)
1157 return value;
1158
1159 LLVMValueRef masks[] = {
1160 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1161 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1162
1163 if (count == 1)
1164 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1165 "");
1166
1167 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1168 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1169 }
1170
1171 static void
1172 build_store_values_extended(struct ac_llvm_context *ac,
1173 LLVMValueRef *values,
1174 unsigned value_count,
1175 unsigned value_stride,
1176 LLVMValueRef vec)
1177 {
1178 LLVMBuilderRef builder = ac->builder;
1179 unsigned i;
1180
1181 for (i = 0; i < value_count; i++) {
1182 LLVMValueRef ptr = values[i * value_stride];
1183 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1184 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1185 LLVMBuildStore(builder, value, ptr);
1186 }
1187 }
1188
1189 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1190 const nir_ssa_def *def)
1191 {
1192 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1193 if (def->num_components > 1) {
1194 type = LLVMVectorType(type, def->num_components);
1195 }
1196 return type;
1197 }
1198
1199 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1200 {
1201 assert(src.is_ssa);
1202 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1203 return (LLVMValueRef)entry->data;
1204 }
1205
1206
1207 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1208 const struct nir_block *b)
1209 {
1210 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1211 return (LLVMBasicBlockRef)entry->data;
1212 }
1213
1214 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1215 nir_alu_src src,
1216 unsigned num_components)
1217 {
1218 LLVMValueRef value = get_src(ctx, src.src);
1219 bool need_swizzle = false;
1220
1221 assert(value);
1222 LLVMTypeRef type = LLVMTypeOf(value);
1223 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1224 ? LLVMGetVectorSize(type)
1225 : 1;
1226
1227 for (unsigned i = 0; i < num_components; ++i) {
1228 assert(src.swizzle[i] < src_components);
1229 if (src.swizzle[i] != i)
1230 need_swizzle = true;
1231 }
1232
1233 if (need_swizzle || num_components != src_components) {
1234 LLVMValueRef masks[] = {
1235 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1236 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1237 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1238 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1239
1240 if (src_components > 1 && num_components == 1) {
1241 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1242 masks[0], "");
1243 } else if (src_components == 1 && num_components > 1) {
1244 LLVMValueRef values[] = {value, value, value, value};
1245 value = ac_build_gather_values(&ctx->ac, values, num_components);
1246 } else {
1247 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1248 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1249 swizzle, "");
1250 }
1251 }
1252 assert(!src.negate);
1253 assert(!src.abs);
1254 return value;
1255 }
1256
1257 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1258 LLVMIntPredicate pred, LLVMValueRef src0,
1259 LLVMValueRef src1)
1260 {
1261 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1262 return LLVMBuildSelect(ctx->builder, result,
1263 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1264 ctx->i32_0, "");
1265 }
1266
1267 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1268 LLVMRealPredicate pred, LLVMValueRef src0,
1269 LLVMValueRef src1)
1270 {
1271 LLVMValueRef result;
1272 src0 = ac_to_float(ctx, src0);
1273 src1 = ac_to_float(ctx, src1);
1274 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1275 return LLVMBuildSelect(ctx->builder, result,
1276 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1277 ctx->i32_0, "");
1278 }
1279
1280 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 };
1289
1290 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1291 get_elem_bits(ctx, result_type));
1292 assert(length < sizeof(name));
1293 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1294 }
1295
1296 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1297 const char *intrin,
1298 LLVMTypeRef result_type,
1299 LLVMValueRef src0, LLVMValueRef src1)
1300 {
1301 char name[64];
1302 LLVMValueRef params[] = {
1303 ac_to_float(ctx, src0),
1304 ac_to_float(ctx, src1),
1305 };
1306
1307 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1308 get_elem_bits(ctx, result_type));
1309 assert(length < sizeof(name));
1310 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1311 }
1312
1313 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1314 const char *intrin,
1315 LLVMTypeRef result_type,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 char name[64];
1319 LLVMValueRef params[] = {
1320 ac_to_float(ctx, src0),
1321 ac_to_float(ctx, src1),
1322 ac_to_float(ctx, src2),
1323 };
1324
1325 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1326 get_elem_bits(ctx, result_type));
1327 assert(length < sizeof(name));
1328 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1329 }
1330
1331 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1333 {
1334 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1335 ctx->i32_0, "");
1336 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1337 }
1338
1339 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1340 LLVMIntPredicate pred,
1341 LLVMValueRef src0, LLVMValueRef src1)
1342 {
1343 return LLVMBuildSelect(ctx->builder,
1344 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1345 src0,
1346 src1, "");
1347
1348 }
1349 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1350 LLVMValueRef src0)
1351 {
1352 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1353 LLVMBuildNeg(ctx->builder, src0, ""));
1354 }
1355
1356 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0)
1358 {
1359 LLVMValueRef cmp, val;
1360
1361 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1362 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1363 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1364 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1365 return val;
1366 }
1367
1368 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1369 LLVMValueRef src0)
1370 {
1371 LLVMValueRef cmp, val;
1372
1373 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1374 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1375 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1376 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1377 return val;
1378 }
1379
1380 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1381 LLVMValueRef src0)
1382 {
1383 const char *intr = "llvm.floor.f32";
1384 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1385 LLVMValueRef params[] = {
1386 fsrc0,
1387 };
1388 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1389 ctx->f32, params, 1,
1390 AC_FUNC_ATTR_READNONE);
1391 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1392 }
1393
1394 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1395 const char *intrin,
1396 LLVMValueRef src0, LLVMValueRef src1)
1397 {
1398 LLVMTypeRef ret_type;
1399 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1400 LLVMValueRef res;
1401 LLVMValueRef params[] = { src0, src1 };
1402 ret_type = LLVMStructTypeInContext(ctx->context, types,
1403 2, true);
1404
1405 res = ac_build_intrinsic(ctx, intrin, ret_type,
1406 params, 2, AC_FUNC_ATTR_READNONE);
1407
1408 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1409 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1410 return res;
1411 }
1412
1413 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1414 LLVMValueRef src0)
1415 {
1416 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1417 }
1418
1419 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 src0 = ac_to_float(ctx, src0);
1423 return LLVMBuildSExt(ctx->builder,
1424 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1425 ctx->i32, "");
1426 }
1427
1428 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1429 LLVMValueRef src0)
1430 {
1431 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1432 }
1433
1434 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildSExt(ctx->builder,
1438 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1439 ctx->i32, "");
1440 }
1441
1442 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1443 LLVMValueRef src0)
1444 {
1445 LLVMValueRef result;
1446 LLVMValueRef cond = NULL;
1447
1448 src0 = ac_to_float(&ctx->ac, src0);
1449 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1450
1451 if (ctx->options->chip_class >= VI) {
1452 LLVMValueRef args[2];
1453 /* Check if the result is a denormal - and flush to 0 if so. */
1454 args[0] = result;
1455 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1456 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1457 }
1458
1459 /* need to convert back up to f32 */
1460 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1461
1462 if (ctx->options->chip_class >= VI)
1463 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1464 else {
1465 /* for SI/CIK */
1466 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1467 * so compare the result and flush to 0 if it's smaller.
1468 */
1469 LLVMValueRef temp, cond2;
1470 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1471 ctx->ac.f32, result);
1472 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1473 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1474 temp, "");
1475 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1476 temp, ctx->ac.f32_0, "");
1477 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1478 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1479 }
1480 return result;
1481 }
1482
1483 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1484 LLVMValueRef src0, LLVMValueRef src1)
1485 {
1486 LLVMValueRef dst64, result;
1487 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1488 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1489
1490 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1491 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1492 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1510 bool is_signed,
1511 const LLVMValueRef srcs[3])
1512 {
1513 LLVMValueRef result;
1514 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1515
1516 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1517 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1522 LLVMValueRef src0, LLVMValueRef src1,
1523 LLVMValueRef src2, LLVMValueRef src3)
1524 {
1525 LLVMValueRef bfi_args[3], result;
1526
1527 bfi_args[0] = LLVMBuildShl(ctx->builder,
1528 LLVMBuildSub(ctx->builder,
1529 LLVMBuildShl(ctx->builder,
1530 ctx->i32_1,
1531 src3, ""),
1532 ctx->i32_1, ""),
1533 src2, "");
1534 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1535 bfi_args[2] = src0;
1536
1537 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1538
1539 /* Calculate:
1540 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1541 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1542 */
1543 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1544 LLVMBuildAnd(ctx->builder, bfi_args[0],
1545 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1546
1547 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1548 return result;
1549 }
1550
1551 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1552 LLVMValueRef src0)
1553 {
1554 LLVMValueRef comp[2];
1555
1556 src0 = ac_to_float(ctx, src0);
1557 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1558 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1559
1560 return ac_build_cvt_pkrtz_f16(ctx, comp);
1561 }
1562
1563 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0)
1565 {
1566 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1567 LLVMValueRef temps[2], result, val;
1568 int i;
1569
1570 for (i = 0; i < 2; i++) {
1571 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1572 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1573 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1574 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1575 }
1576
1577 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1578 ctx->i32_0, "");
1579 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1580 ctx->i32_1, "");
1581 return result;
1582 }
1583
1584 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1585 nir_op op,
1586 LLVMValueRef src0)
1587 {
1588 unsigned mask;
1589 int idx;
1590 LLVMValueRef result;
1591
1592 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1593 mask = AC_TID_MASK_LEFT;
1594 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1595 mask = AC_TID_MASK_TOP;
1596 else
1597 mask = AC_TID_MASK_TOP_LEFT;
1598
1599 /* for DDX we want to next X pixel, DDY next Y pixel. */
1600 if (op == nir_op_fddx_fine ||
1601 op == nir_op_fddx_coarse ||
1602 op == nir_op_fddx)
1603 idx = 1;
1604 else
1605 idx = 2;
1606
1607 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1608 return result;
1609 }
1610
1611 /*
1612 * this takes an I,J coordinate pair,
1613 * and works out the X and Y derivatives.
1614 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1615 */
1616 static LLVMValueRef emit_ddxy_interp(
1617 struct ac_nir_context *ctx,
1618 LLVMValueRef interp_ij)
1619 {
1620 LLVMValueRef result[4], a;
1621 unsigned i;
1622
1623 for (i = 0; i < 2; i++) {
1624 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1625 LLVMConstInt(ctx->ac.i32, i, false), "");
1626 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1627 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1628 }
1629 return ac_build_gather_values(&ctx->ac, result, 4);
1630 }
1631
1632 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1633 {
1634 LLVMValueRef src[4], result = NULL;
1635 unsigned num_components = instr->dest.dest.ssa.num_components;
1636 unsigned src_components;
1637 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1638
1639 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1640 switch (instr->op) {
1641 case nir_op_vec2:
1642 case nir_op_vec3:
1643 case nir_op_vec4:
1644 src_components = 1;
1645 break;
1646 case nir_op_pack_half_2x16:
1647 src_components = 2;
1648 break;
1649 case nir_op_unpack_half_2x16:
1650 src_components = 1;
1651 break;
1652 default:
1653 src_components = num_components;
1654 break;
1655 }
1656 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1657 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1658
1659 switch (instr->op) {
1660 case nir_op_fmov:
1661 case nir_op_imov:
1662 result = src[0];
1663 break;
1664 case nir_op_fneg:
1665 src[0] = ac_to_float(&ctx->ac, src[0]);
1666 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1667 break;
1668 case nir_op_ineg:
1669 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1670 break;
1671 case nir_op_inot:
1672 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1673 break;
1674 case nir_op_iadd:
1675 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_fadd:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 src[1] = ac_to_float(&ctx->ac, src[1]);
1680 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1681 break;
1682 case nir_op_fsub:
1683 src[0] = ac_to_float(&ctx->ac, src[0]);
1684 src[1] = ac_to_float(&ctx->ac, src[1]);
1685 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_isub:
1688 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_imul:
1691 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_imod:
1694 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_umod:
1697 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fmod:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1704 ac_to_float_type(&ctx->ac, def_type), result);
1705 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1706 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1707 break;
1708 case nir_op_frem:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_irem:
1714 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_idiv:
1717 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_udiv:
1720 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_fmul:
1723 src[0] = ac_to_float(&ctx->ac, src[0]);
1724 src[1] = ac_to_float(&ctx->ac, src[1]);
1725 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_fdiv:
1728 src[0] = ac_to_float(&ctx->ac, src[0]);
1729 src[1] = ac_to_float(&ctx->ac, src[1]);
1730 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1731 break;
1732 case nir_op_frcp:
1733 src[0] = ac_to_float(&ctx->ac, src[0]);
1734 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1735 break;
1736 case nir_op_iand:
1737 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_ior:
1740 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_ixor:
1743 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_ishl:
1746 result = LLVMBuildShl(ctx->ac.builder, src[0],
1747 LLVMBuildZExt(ctx->ac.builder, src[1],
1748 LLVMTypeOf(src[0]), ""),
1749 "");
1750 break;
1751 case nir_op_ishr:
1752 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1753 LLVMBuildZExt(ctx->ac.builder, src[1],
1754 LLVMTypeOf(src[0]), ""),
1755 "");
1756 break;
1757 case nir_op_ushr:
1758 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1759 LLVMBuildZExt(ctx->ac.builder, src[1],
1760 LLVMTypeOf(src[0]), ""),
1761 "");
1762 break;
1763 case nir_op_ilt:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1765 break;
1766 case nir_op_ine:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1768 break;
1769 case nir_op_ieq:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1771 break;
1772 case nir_op_ige:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1774 break;
1775 case nir_op_ult:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1777 break;
1778 case nir_op_uge:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1780 break;
1781 case nir_op_feq:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1783 break;
1784 case nir_op_fne:
1785 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1786 break;
1787 case nir_op_flt:
1788 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1789 break;
1790 case nir_op_fge:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1792 break;
1793 case nir_op_fabs:
1794 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1795 ac_to_float_type(&ctx->ac, def_type), src[0]);
1796 break;
1797 case nir_op_iabs:
1798 result = emit_iabs(&ctx->ac, src[0]);
1799 break;
1800 case nir_op_imax:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1802 break;
1803 case nir_op_imin:
1804 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1805 break;
1806 case nir_op_umax:
1807 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1808 break;
1809 case nir_op_umin:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1811 break;
1812 case nir_op_isign:
1813 result = emit_isign(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fsign:
1816 src[0] = ac_to_float(&ctx->ac, src[0]);
1817 result = emit_fsign(&ctx->ac, src[0]);
1818 break;
1819 case nir_op_ffloor:
1820 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1821 ac_to_float_type(&ctx->ac, def_type), src[0]);
1822 break;
1823 case nir_op_ftrunc:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fceil:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_fround_even:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1833 ac_to_float_type(&ctx->ac, def_type),src[0]);
1834 break;
1835 case nir_op_ffract:
1836 result = emit_ffract(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_fsin:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_fcos:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 break;
1846 case nir_op_fsqrt:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1848 ac_to_float_type(&ctx->ac, def_type), src[0]);
1849 break;
1850 case nir_op_fexp2:
1851 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1852 ac_to_float_type(&ctx->ac, def_type), src[0]);
1853 break;
1854 case nir_op_flog2:
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1856 ac_to_float_type(&ctx->ac, def_type), src[0]);
1857 break;
1858 case nir_op_frsq:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1862 break;
1863 case nir_op_fpow:
1864 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1865 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1866 break;
1867 case nir_op_fmax:
1868 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1869 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1870 if (instr->dest.dest.ssa.bit_size == 32)
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1872 ac_to_float_type(&ctx->ac, def_type),
1873 result);
1874 break;
1875 case nir_op_fmin:
1876 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1877 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1878 if (instr->dest.dest.ssa.bit_size == 32)
1879 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1880 ac_to_float_type(&ctx->ac, def_type),
1881 result);
1882 break;
1883 case nir_op_ffma:
1884 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1885 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1886 break;
1887 case nir_op_ibitfield_extract:
1888 result = emit_bitfield_extract(&ctx->ac, true, src);
1889 break;
1890 case nir_op_ubitfield_extract:
1891 result = emit_bitfield_extract(&ctx->ac, false, src);
1892 break;
1893 case nir_op_bitfield_insert:
1894 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1895 break;
1896 case nir_op_bitfield_reverse:
1897 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1898 break;
1899 case nir_op_bit_count:
1900 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1901 break;
1902 case nir_op_vec2:
1903 case nir_op_vec3:
1904 case nir_op_vec4:
1905 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1906 src[i] = ac_to_integer(&ctx->ac, src[i]);
1907 result = ac_build_gather_values(&ctx->ac, src, num_components);
1908 break;
1909 case nir_op_f2i32:
1910 case nir_op_f2i64:
1911 src[0] = ac_to_float(&ctx->ac, src[0]);
1912 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1913 break;
1914 case nir_op_f2u32:
1915 case nir_op_f2u64:
1916 src[0] = ac_to_float(&ctx->ac, src[0]);
1917 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2f32:
1920 case nir_op_i2f64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1923 break;
1924 case nir_op_u2f32:
1925 case nir_op_u2f64:
1926 src[0] = ac_to_integer(&ctx->ac, src[0]);
1927 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1928 break;
1929 case nir_op_f2f64:
1930 src[0] = ac_to_float(&ctx->ac, src[0]);
1931 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1932 break;
1933 case nir_op_f2f32:
1934 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1935 break;
1936 case nir_op_u2u32:
1937 case nir_op_u2u64:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1940 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1941 else
1942 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1943 break;
1944 case nir_op_i2i32:
1945 case nir_op_i2i64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1948 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1949 else
1950 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1951 break;
1952 case nir_op_bcsel:
1953 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1954 break;
1955 case nir_op_find_lsb:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1958 break;
1959 case nir_op_ufind_msb:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1962 break;
1963 case nir_op_ifind_msb:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1966 break;
1967 case nir_op_uadd_carry:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 src[1] = ac_to_integer(&ctx->ac, src[1]);
1970 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1971 break;
1972 case nir_op_usub_borrow:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 src[1] = ac_to_integer(&ctx->ac, src[1]);
1975 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1976 break;
1977 case nir_op_b2f:
1978 result = emit_b2f(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_f2b:
1981 result = emit_f2b(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_b2i:
1984 result = emit_b2i(&ctx->ac, src[0]);
1985 break;
1986 case nir_op_i2b:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = emit_i2b(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_fquantize2f16:
1991 result = emit_f2f16(ctx->nctx, src[0]);
1992 break;
1993 case nir_op_umul_high:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1997 break;
1998 case nir_op_imul_high:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 src[1] = ac_to_integer(&ctx->ac, src[1]);
2001 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2002 break;
2003 case nir_op_pack_half_2x16:
2004 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_unpack_half_2x16:
2007 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2008 break;
2009 case nir_op_fddx:
2010 case nir_op_fddy:
2011 case nir_op_fddx_fine:
2012 case nir_op_fddy_fine:
2013 case nir_op_fddx_coarse:
2014 case nir_op_fddy_coarse:
2015 result = emit_ddxy(ctx, instr->op, src[0]);
2016 break;
2017
2018 case nir_op_unpack_64_2x32_split_x: {
2019 assert(instr->src[0].src.ssa->num_components == 1);
2020 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2021 ctx->ac.v2i32,
2022 "");
2023 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2024 ctx->ac.i32_0, "");
2025 break;
2026 }
2027
2028 case nir_op_unpack_64_2x32_split_y: {
2029 assert(instr->src[0].src.ssa->num_components == 1);
2030 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2031 ctx->ac.v2i32,
2032 "");
2033 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2034 ctx->ac.i32_1, "");
2035 break;
2036 }
2037
2038 case nir_op_pack_64_2x32_split: {
2039 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2040 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2041 src[0], ctx->ac.i32_0, "");
2042 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2043 src[1], ctx->ac.i32_1, "");
2044 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2045 break;
2046 }
2047
2048 default:
2049 fprintf(stderr, "Unknown NIR alu instr: ");
2050 nir_print_instr(&instr->instr, stderr);
2051 fprintf(stderr, "\n");
2052 abort();
2053 }
2054
2055 if (result) {
2056 assert(instr->dest.dest.is_ssa);
2057 result = ac_to_integer(&ctx->ac, result);
2058 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2059 result);
2060 }
2061 }
2062
2063 static void visit_load_const(struct ac_nir_context *ctx,
2064 const nir_load_const_instr *instr)
2065 {
2066 LLVMValueRef values[4], value = NULL;
2067 LLVMTypeRef element_type =
2068 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2069
2070 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2071 switch (instr->def.bit_size) {
2072 case 32:
2073 values[i] = LLVMConstInt(element_type,
2074 instr->value.u32[i], false);
2075 break;
2076 case 64:
2077 values[i] = LLVMConstInt(element_type,
2078 instr->value.u64[i], false);
2079 break;
2080 default:
2081 fprintf(stderr,
2082 "unsupported nir load_const bit_size: %d\n",
2083 instr->def.bit_size);
2084 abort();
2085 }
2086 }
2087 if (instr->def.num_components > 1) {
2088 value = LLVMConstVector(values, instr->def.num_components);
2089 } else
2090 value = values[0];
2091
2092 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2093 }
2094
2095 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2096 LLVMTypeRef type)
2097 {
2098 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2099 return LLVMBuildBitCast(ctx->builder, ptr,
2100 LLVMPointerType(type, addr_space), "");
2101 }
2102
2103 static LLVMValueRef
2104 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2105 {
2106 LLVMValueRef size =
2107 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2108 LLVMConstInt(ctx->ac.i32, 2, false), "");
2109
2110 /* VI only */
2111 if (ctx->ac.chip_class == VI && in_elements) {
2112 /* On VI, the descriptor contains the size in bytes,
2113 * but TXQ must return the size in elements.
2114 * The stride is always non-zero for resources using TXQ.
2115 */
2116 LLVMValueRef stride =
2117 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2118 ctx->ac.i32_1, "");
2119 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2120 LLVMConstInt(ctx->ac.i32, 16, false), "");
2121 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2122 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2123
2124 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2125 }
2126 return size;
2127 }
2128
2129 /**
2130 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2131 * intrinsic names).
2132 */
2133 static void build_int_type_name(
2134 LLVMTypeRef type,
2135 char *buf, unsigned bufsize)
2136 {
2137 assert(bufsize >= 6);
2138
2139 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2140 snprintf(buf, bufsize, "v%ui32",
2141 LLVMGetVectorSize(type));
2142 else
2143 strcpy(buf, "i32");
2144 }
2145
2146 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2147 struct ac_image_args *args,
2148 const nir_tex_instr *instr)
2149 {
2150 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2151 LLVMValueRef coord = args->addr;
2152 LLVMValueRef half_texel[2];
2153 LLVMValueRef compare_cube_wa = NULL;
2154 LLVMValueRef result;
2155 int c;
2156 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2157
2158 //TODO Rect
2159 {
2160 struct ac_image_args txq_args = { 0 };
2161
2162 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2163 txq_args.opcode = ac_image_get_resinfo;
2164 txq_args.dmask = 0xf;
2165 txq_args.addr = ctx->i32_0;
2166 txq_args.resource = args->resource;
2167 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2168
2169 for (c = 0; c < 2; c++) {
2170 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2171 LLVMConstInt(ctx->i32, c, false), "");
2172 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2173 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2174 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2175 LLVMConstReal(ctx->f32, -0.5), "");
2176 }
2177 }
2178
2179 LLVMValueRef orig_coords = args->addr;
2180
2181 for (c = 0; c < 2; c++) {
2182 LLVMValueRef tmp;
2183 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2184 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2185 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2186 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2187 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2188 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2189 }
2190
2191
2192 /*
2193 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2194 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2195 * workaround by sampling using a scaled type and converting.
2196 * This is taken from amdgpu-pro shaders.
2197 */
2198 /* NOTE this produces some ugly code compared to amdgpu-pro,
2199 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2200 * and then reads them back. -pro generates two selects,
2201 * one s_cmp for the descriptor rewriting
2202 * one v_cmp for the coordinate and result changes.
2203 */
2204 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2205 LLVMValueRef tmp, tmp2;
2206
2207 /* workaround 8/8/8/8 uint/sint cube gather bug */
2208 /* first detect it then change to a scaled read and f2i */
2209 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2210 tmp2 = tmp;
2211
2212 /* extract the DATA_FORMAT */
2213 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2214 LLVMConstInt(ctx->i32, 6, false), false);
2215
2216 /* is the DATA_FORMAT == 8_8_8_8 */
2217 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2218
2219 if (stype == GLSL_TYPE_UINT)
2220 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2221 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2222 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2223 else
2224 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2225 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2226 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2227
2228 /* replace the NUM FORMAT in the descriptor */
2229 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2230 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2231
2232 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2233
2234 /* don't modify the coordinates for this case */
2235 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2236 }
2237 args->addr = coord;
2238 result = ac_build_image_opcode(ctx, args);
2239
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2241 LLVMValueRef tmp, tmp2;
2242
2243 /* if the cube workaround is in place, f2i the result. */
2244 for (c = 0; c < 4; c++) {
2245 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2246 if (stype == GLSL_TYPE_UINT)
2247 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2248 else
2249 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2250 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2251 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2252 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2253 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2254 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2255 }
2256 }
2257 return result;
2258 }
2259
2260 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2261 const nir_tex_instr *instr,
2262 bool lod_is_zero,
2263 struct ac_image_args *args)
2264 {
2265 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2266 return ac_build_buffer_load_format(&ctx->ac,
2267 args->resource,
2268 args->addr,
2269 ctx->ac.i32_0,
2270 true);
2271 }
2272
2273 args->opcode = ac_image_sample;
2274 args->compare = instr->is_shadow;
2275
2276 switch (instr->op) {
2277 case nir_texop_txf:
2278 case nir_texop_txf_ms:
2279 case nir_texop_samples_identical:
2280 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2281 args->compare = false;
2282 args->offset = false;
2283 break;
2284 case nir_texop_txb:
2285 args->bias = true;
2286 break;
2287 case nir_texop_txl:
2288 if (lod_is_zero)
2289 args->level_zero = true;
2290 else
2291 args->lod = true;
2292 break;
2293 case nir_texop_txs:
2294 case nir_texop_query_levels:
2295 args->opcode = ac_image_get_resinfo;
2296 break;
2297 case nir_texop_tex:
2298 if (ctx->stage != MESA_SHADER_FRAGMENT)
2299 args->level_zero = true;
2300 break;
2301 case nir_texop_txd:
2302 args->deriv = true;
2303 break;
2304 case nir_texop_tg4:
2305 args->opcode = ac_image_gather4;
2306 args->level_zero = true;
2307 break;
2308 case nir_texop_lod:
2309 args->opcode = ac_image_get_lod;
2310 args->compare = false;
2311 args->offset = false;
2312 break;
2313 default:
2314 break;
2315 }
2316
2317 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2318 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2319 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2320 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2321 }
2322 }
2323 return ac_build_image_opcode(&ctx->ac, args);
2324 }
2325
2326 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2327 nir_intrinsic_instr *instr)
2328 {
2329 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2330 unsigned desc_set = nir_intrinsic_desc_set(instr);
2331 unsigned binding = nir_intrinsic_binding(instr);
2332 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2333 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2334 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2335 unsigned base_offset = layout->binding[binding].offset;
2336 LLVMValueRef offset, stride;
2337
2338 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2339 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2340 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2341 layout->binding[binding].dynamic_offset_offset;
2342 desc_ptr = ctx->push_constants;
2343 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2344 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2345 } else
2346 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2347
2348 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2349 index = LLVMBuildMul(ctx->builder, index, stride, "");
2350 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2351
2352 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2353 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2354 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2355
2356 return desc_ptr;
2357 }
2358
2359 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2360 nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2363 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2364
2365 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2366 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2367 return result;
2368 }
2369
2370 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2371 nir_intrinsic_instr *instr)
2372 {
2373 LLVMValueRef ptr, addr;
2374
2375 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2376 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2377
2378 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2379 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2380
2381 return LLVMBuildLoad(ctx->builder, ptr, "");
2382 }
2383
2384 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2388
2389 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2390 }
2391 static void visit_store_ssbo(struct ac_nir_context *ctx,
2392 nir_intrinsic_instr *instr)
2393 {
2394 const char *store_name;
2395 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2396 LLVMTypeRef data_type = ctx->ac.f32;
2397 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2398 int components_32bit = elem_size_mult * instr->num_components;
2399 unsigned writemask = nir_intrinsic_write_mask(instr);
2400 LLVMValueRef base_data, base_offset;
2401 LLVMValueRef params[6];
2402
2403 params[1] = ctx->abi->load_ssbo(ctx->abi,
2404 get_src(ctx, instr->src[1]), true);
2405 params[2] = ctx->ac.i32_0; /* vindex */
2406 params[4] = ctx->ac.i1false; /* glc */
2407 params[5] = ctx->ac.i1false; /* slc */
2408
2409 if (components_32bit > 1)
2410 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2411
2412 base_data = ac_to_float(&ctx->ac, src_data);
2413 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2414 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2415 data_type, "");
2416 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2417 while (writemask) {
2418 int start, count;
2419 LLVMValueRef data;
2420 LLVMValueRef offset;
2421 LLVMValueRef tmp;
2422 u_bit_scan_consecutive_range(&writemask, &start, &count);
2423
2424 /* Due to an LLVM limitation, split 3-element writes
2425 * into a 2-element and a 1-element write. */
2426 if (count == 3) {
2427 writemask |= 1 << (start + 2);
2428 count = 2;
2429 }
2430
2431 start *= elem_size_mult;
2432 count *= elem_size_mult;
2433
2434 if (count > 4) {
2435 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2436 count = 4;
2437 }
2438
2439 if (count == 4) {
2440 store_name = "llvm.amdgcn.buffer.store.v4f32";
2441 data = base_data;
2442 } else if (count == 2) {
2443 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2444 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2445 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2446 ctx->ac.i32_0, "");
2447
2448 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2449 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2450 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2451 ctx->ac.i32_1, "");
2452 store_name = "llvm.amdgcn.buffer.store.v2f32";
2453
2454 } else {
2455 assert(count == 1);
2456 if (get_llvm_num_components(base_data) > 1)
2457 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2458 LLVMConstInt(ctx->ac.i32, start, false), "");
2459 else
2460 data = base_data;
2461 store_name = "llvm.amdgcn.buffer.store.f32";
2462 }
2463
2464 offset = base_offset;
2465 if (start != 0) {
2466 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2467 }
2468 params[0] = data;
2469 params[3] = offset;
2470 ac_build_intrinsic(&ctx->ac, store_name,
2471 ctx->ac.voidt, params, 6, 0);
2472 }
2473 }
2474
2475 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 const char *name;
2479 LLVMValueRef params[6];
2480 int arg_count = 0;
2481
2482 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2483 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2484 }
2485 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2486 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2487 get_src(ctx, instr->src[0]),
2488 true);
2489 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2490 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2491 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2492
2493 switch (instr->intrinsic) {
2494 case nir_intrinsic_ssbo_atomic_add:
2495 name = "llvm.amdgcn.buffer.atomic.add";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_imin:
2498 name = "llvm.amdgcn.buffer.atomic.smin";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_umin:
2501 name = "llvm.amdgcn.buffer.atomic.umin";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_imax:
2504 name = "llvm.amdgcn.buffer.atomic.smax";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_umax:
2507 name = "llvm.amdgcn.buffer.atomic.umax";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_and:
2510 name = "llvm.amdgcn.buffer.atomic.and";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_or:
2513 name = "llvm.amdgcn.buffer.atomic.or";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_xor:
2516 name = "llvm.amdgcn.buffer.atomic.xor";
2517 break;
2518 case nir_intrinsic_ssbo_atomic_exchange:
2519 name = "llvm.amdgcn.buffer.atomic.swap";
2520 break;
2521 case nir_intrinsic_ssbo_atomic_comp_swap:
2522 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2523 break;
2524 default:
2525 abort();
2526 }
2527
2528 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2529 }
2530
2531 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2532 const nir_intrinsic_instr *instr)
2533 {
2534 LLVMValueRef results[2];
2535 int load_components;
2536 int num_components = instr->num_components;
2537 if (instr->dest.ssa.bit_size == 64)
2538 num_components *= 2;
2539
2540 for (int i = 0; i < num_components; i += load_components) {
2541 load_components = MIN2(num_components - i, 4);
2542 const char *load_name;
2543 LLVMTypeRef data_type = ctx->ac.f32;
2544 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2545 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2546
2547 if (load_components == 3)
2548 data_type = LLVMVectorType(ctx->ac.f32, 4);
2549 else if (load_components > 1)
2550 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2551
2552 if (load_components >= 3)
2553 load_name = "llvm.amdgcn.buffer.load.v4f32";
2554 else if (load_components == 2)
2555 load_name = "llvm.amdgcn.buffer.load.v2f32";
2556 else if (load_components == 1)
2557 load_name = "llvm.amdgcn.buffer.load.f32";
2558 else
2559 unreachable("unhandled number of components");
2560
2561 LLVMValueRef params[] = {
2562 ctx->abi->load_ssbo(ctx->abi,
2563 get_src(ctx, instr->src[0]),
2564 false),
2565 ctx->ac.i32_0,
2566 offset,
2567 ctx->ac.i1false,
2568 ctx->ac.i1false,
2569 };
2570
2571 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2572
2573 }
2574
2575 assume(results[0]);
2576 LLVMValueRef ret = results[0];
2577 if (num_components > 4 || num_components == 3) {
2578 LLVMValueRef masks[] = {
2579 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2580 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2581 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2582 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2583 };
2584
2585 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2586 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2587 results[num_components > 4 ? 1 : 0], swizzle, "");
2588 }
2589
2590 return LLVMBuildBitCast(ctx->ac.builder, ret,
2591 get_def_type(ctx, &instr->dest.ssa), "");
2592 }
2593
2594 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2595 const nir_intrinsic_instr *instr)
2596 {
2597 LLVMValueRef results[8], ret;
2598 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2599 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2600 int num_components = instr->num_components;
2601
2602 if (ctx->abi->load_ubo)
2603 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2604
2605 if (instr->dest.ssa.bit_size == 64)
2606 num_components *= 2;
2607
2608 for (unsigned i = 0; i < num_components; ++i) {
2609 LLVMValueRef params[] = {
2610 rsrc,
2611 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2612 offset, "")
2613 };
2614 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2615 params, 2,
2616 AC_FUNC_ATTR_READNONE |
2617 AC_FUNC_ATTR_LEGACY);
2618 }
2619
2620
2621 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2622 return LLVMBuildBitCast(ctx->ac.builder, ret,
2623 get_def_type(ctx, &instr->dest.ssa), "");
2624 }
2625
2626 static void
2627 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2628 bool vs_in, unsigned *vertex_index_out,
2629 LLVMValueRef *vertex_index_ref,
2630 unsigned *const_out, LLVMValueRef *indir_out)
2631 {
2632 unsigned const_offset = 0;
2633 nir_deref *tail = &deref->deref;
2634 LLVMValueRef offset = NULL;
2635
2636 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2637 tail = tail->child;
2638 nir_deref_array *deref_array = nir_deref_as_array(tail);
2639 if (vertex_index_out)
2640 *vertex_index_out = deref_array->base_offset;
2641
2642 if (vertex_index_ref) {
2643 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2644 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2645 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2646 }
2647 *vertex_index_ref = vtx;
2648 }
2649 }
2650
2651 if (deref->var->data.compact) {
2652 assert(tail->child->deref_type == nir_deref_type_array);
2653 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2654 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2655 /* We always lower indirect dereferences for "compact" array vars. */
2656 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2657
2658 const_offset = deref_array->base_offset;
2659 goto out;
2660 }
2661
2662 while (tail->child != NULL) {
2663 const struct glsl_type *parent_type = tail->type;
2664 tail = tail->child;
2665
2666 if (tail->deref_type == nir_deref_type_array) {
2667 nir_deref_array *deref_array = nir_deref_as_array(tail);
2668 LLVMValueRef index, stride, local_offset;
2669 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2670
2671 const_offset += size * deref_array->base_offset;
2672 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2673 continue;
2674
2675 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2676 index = get_src(ctx, deref_array->indirect);
2677 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2678 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2679
2680 if (offset)
2681 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2682 else
2683 offset = local_offset;
2684 } else if (tail->deref_type == nir_deref_type_struct) {
2685 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2686
2687 for (unsigned i = 0; i < deref_struct->index; i++) {
2688 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2689 const_offset += glsl_count_attribute_slots(ft, vs_in);
2690 }
2691 } else
2692 unreachable("unsupported deref type");
2693
2694 }
2695 out:
2696 if (const_offset && offset)
2697 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2698 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2699 "");
2700
2701 *const_out = const_offset;
2702 *indir_out = offset;
2703 }
2704
2705
2706 /* The offchip buffer layout for TCS->TES is
2707 *
2708 * - attribute 0 of patch 0 vertex 0
2709 * - attribute 0 of patch 0 vertex 1
2710 * - attribute 0 of patch 0 vertex 2
2711 * ...
2712 * - attribute 0 of patch 1 vertex 0
2713 * - attribute 0 of patch 1 vertex 1
2714 * ...
2715 * - attribute 1 of patch 0 vertex 0
2716 * - attribute 1 of patch 0 vertex 1
2717 * ...
2718 * - per patch attribute 0 of patch 0
2719 * - per patch attribute 0 of patch 1
2720 * ...
2721 *
2722 * Note that every attribute has 4 components.
2723 */
2724 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2725 LLVMValueRef vertex_index,
2726 LLVMValueRef param_index)
2727 {
2728 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2729 LLVMValueRef param_stride, constant16;
2730 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2731
2732 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2733 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2734 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2735 num_patches, "");
2736
2737 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2738 if (vertex_index) {
2739 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2740 vertices_per_patch, "");
2741
2742 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2743 vertex_index, "");
2744
2745 param_stride = total_vertices;
2746 } else {
2747 base_addr = rel_patch_id;
2748 param_stride = num_patches;
2749 }
2750
2751 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2752 LLVMBuildMul(ctx->builder, param_index,
2753 param_stride, ""), "");
2754
2755 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2756
2757 if (!vertex_index) {
2758 LLVMValueRef patch_data_offset =
2759 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2760
2761 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2762 patch_data_offset, "");
2763 }
2764 return base_addr;
2765 }
2766
2767 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2768 unsigned param,
2769 unsigned const_index,
2770 bool is_compact,
2771 LLVMValueRef vertex_index,
2772 LLVMValueRef indir_index)
2773 {
2774 LLVMValueRef param_index;
2775
2776 if (indir_index)
2777 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2778 indir_index, "");
2779 else {
2780 if (const_index && !is_compact)
2781 param += const_index;
2782 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2783 }
2784 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2785 }
2786
2787 static void
2788 mark_tess_output(struct nir_to_llvm_context *ctx,
2789 bool is_patch, uint32_t param)
2790
2791 {
2792 if (is_patch) {
2793 ctx->tess_patch_outputs_written |= (1ull << param);
2794 } else
2795 ctx->tess_outputs_written |= (1ull << param);
2796 }
2797
2798 static LLVMValueRef
2799 get_dw_address(struct nir_to_llvm_context *ctx,
2800 LLVMValueRef dw_addr,
2801 unsigned param,
2802 unsigned const_index,
2803 bool compact_const_index,
2804 LLVMValueRef vertex_index,
2805 LLVMValueRef stride,
2806 LLVMValueRef indir_index)
2807
2808 {
2809
2810 if (vertex_index) {
2811 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2812 LLVMBuildMul(ctx->builder,
2813 vertex_index,
2814 stride, ""), "");
2815 }
2816
2817 if (indir_index)
2818 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2819 LLVMBuildMul(ctx->builder, indir_index,
2820 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2821 else if (const_index && !compact_const_index)
2822 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2823 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2824
2825 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2826 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2827
2828 if (const_index && compact_const_index)
2829 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2830 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2831 return dw_addr;
2832 }
2833
2834 static LLVMValueRef
2835 load_tcs_input(struct nir_to_llvm_context *ctx,
2836 nir_intrinsic_instr *instr)
2837 {
2838 LLVMValueRef dw_addr, stride;
2839 unsigned const_index;
2840 LLVMValueRef vertex_index;
2841 LLVMValueRef indir_index;
2842 unsigned param;
2843 LLVMValueRef value[4], result;
2844 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2845 const bool is_compact = instr->variables[0]->var->data.compact;
2846 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2847 get_deref_offset(ctx->nir, instr->variables[0],
2848 false, NULL, per_vertex ? &vertex_index : NULL,
2849 &const_index, &indir_index);
2850
2851 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2852 dw_addr = get_tcs_in_current_patch_offset(ctx);
2853 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2854 indir_index);
2855
2856 unsigned comp = instr->variables[0]->var->data.location_frac;
2857 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2858 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2859 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2860 ctx->ac.i32_1, "");
2861 }
2862 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2863 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2864 return result;
2865 }
2866
2867 static LLVMValueRef
2868 load_tcs_output(struct nir_to_llvm_context *ctx,
2869 nir_intrinsic_instr *instr)
2870 {
2871 LLVMValueRef dw_addr;
2872 LLVMValueRef stride = NULL;
2873 LLVMValueRef value[4], result;
2874 LLVMValueRef vertex_index = NULL;
2875 LLVMValueRef indir_index = NULL;
2876 unsigned const_index = 0;
2877 unsigned param;
2878 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2879 const bool is_compact = instr->variables[0]->var->data.compact;
2880 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2881 get_deref_offset(ctx->nir, instr->variables[0],
2882 false, NULL, per_vertex ? &vertex_index : NULL,
2883 &const_index, &indir_index);
2884
2885 if (!instr->variables[0]->var->data.patch) {
2886 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2887 dw_addr = get_tcs_out_current_patch_offset(ctx);
2888 } else {
2889 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2890 }
2891
2892 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2893 indir_index);
2894
2895 unsigned comp = instr->variables[0]->var->data.location_frac;
2896 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2897 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2898 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2899 ctx->ac.i32_1, "");
2900 }
2901 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2902 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2903 return result;
2904 }
2905
2906 static void
2907 store_tcs_output(struct nir_to_llvm_context *ctx,
2908 nir_intrinsic_instr *instr,
2909 LLVMValueRef src,
2910 unsigned writemask)
2911 {
2912 LLVMValueRef dw_addr;
2913 LLVMValueRef stride = NULL;
2914 LLVMValueRef buf_addr = NULL;
2915 LLVMValueRef vertex_index = NULL;
2916 LLVMValueRef indir_index = NULL;
2917 unsigned const_index = 0;
2918 unsigned param;
2919 const unsigned comp = instr->variables[0]->var->data.location_frac;
2920 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2921 const bool is_compact = instr->variables[0]->var->data.compact;
2922 bool store_lds = true;
2923
2924 if (instr->variables[0]->var->data.patch) {
2925 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2926 store_lds = false;
2927 } else {
2928 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2929 store_lds = false;
2930 }
2931 get_deref_offset(ctx->nir, instr->variables[0],
2932 false, NULL, per_vertex ? &vertex_index : NULL,
2933 &const_index, &indir_index);
2934
2935 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2936 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2937 is_compact && const_index > 3) {
2938 const_index -= 3;
2939 param++;
2940 }
2941
2942 if (!instr->variables[0]->var->data.patch) {
2943 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2944 dw_addr = get_tcs_out_current_patch_offset(ctx);
2945 } else {
2946 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2947 }
2948
2949 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2950
2951 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2952 indir_index);
2953 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2954 vertex_index, indir_index);
2955
2956 bool is_tess_factor = false;
2957 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2958 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2959 is_tess_factor = true;
2960
2961 unsigned base = is_compact ? const_index : 0;
2962 for (unsigned chan = 0; chan < 8; chan++) {
2963 if (!(writemask & (1 << chan)))
2964 continue;
2965 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2966
2967 if (store_lds || is_tess_factor)
2968 ac_lds_store(&ctx->ac, dw_addr, value);
2969
2970 if (!is_tess_factor && writemask != 0xF)
2971 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2972 buf_addr, ctx->oc_lds,
2973 4 * (base + chan), 1, 0, true, false);
2974
2975 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2976 ctx->ac.i32_1, "");
2977 }
2978
2979 if (writemask == 0xF) {
2980 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2981 buf_addr, ctx->oc_lds,
2982 (base * 4), 1, 0, true, false);
2983 }
2984 }
2985
2986 static LLVMValueRef
2987 load_tes_input(struct ac_shader_abi *abi,
2988 LLVMValueRef vertex_index,
2989 LLVMValueRef param_index,
2990 unsigned const_index,
2991 unsigned location,
2992 unsigned driver_location,
2993 unsigned component,
2994 unsigned num_components,
2995 bool is_patch,
2996 bool is_compact)
2997 {
2998 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2999 LLVMValueRef buf_addr;
3000 LLVMValueRef result;
3001 unsigned param = shader_io_get_unique_index(location);
3002
3003 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3004 const_index -= 3;
3005 param++;
3006 }
3007
3008 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3009 is_compact, vertex_index, param_index);
3010
3011 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3012 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3013
3014 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3015 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3016 result = trim_vector(&ctx->ac, result, num_components);
3017 return result;
3018 }
3019
3020 static LLVMValueRef
3021 load_gs_input(struct ac_shader_abi *abi,
3022 unsigned location,
3023 unsigned driver_location,
3024 unsigned component,
3025 unsigned num_components,
3026 unsigned vertex_index,
3027 unsigned const_index,
3028 LLVMTypeRef type)
3029 {
3030 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3031 LLVMValueRef vtx_offset;
3032 LLVMValueRef args[9];
3033 unsigned param, vtx_offset_param;
3034 LLVMValueRef value[4], result;
3035
3036 vtx_offset_param = vertex_index;
3037 assert(vtx_offset_param < 6);
3038 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3039 LLVMConstInt(ctx->ac.i32, 4, false), "");
3040
3041 param = shader_io_get_unique_index(location);
3042
3043 for (unsigned i = component; i < num_components + component; i++) {
3044 if (ctx->ac.chip_class >= GFX9) {
3045 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3046 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3047 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3048 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3049 } else {
3050 args[0] = ctx->esgs_ring;
3051 args[1] = vtx_offset;
3052 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3053 args[3] = ctx->ac.i32_0;
3054 args[4] = ctx->ac.i32_1; /* OFFEN */
3055 args[5] = ctx->ac.i32_0; /* IDXEN */
3056 args[6] = ctx->ac.i32_1; /* GLC */
3057 args[7] = ctx->ac.i32_0; /* SLC */
3058 args[8] = ctx->ac.i32_0; /* TFE */
3059
3060 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3061 ctx->ac.i32, args, 9,
3062 AC_FUNC_ATTR_READONLY |
3063 AC_FUNC_ATTR_LEGACY);
3064 }
3065 }
3066 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3067
3068 return result;
3069 }
3070
3071 static LLVMValueRef
3072 build_gep_for_deref(struct ac_nir_context *ctx,
3073 nir_deref_var *deref)
3074 {
3075 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3076 assert(entry->data);
3077 LLVMValueRef val = entry->data;
3078 nir_deref *tail = deref->deref.child;
3079 while (tail != NULL) {
3080 LLVMValueRef offset;
3081 switch (tail->deref_type) {
3082 case nir_deref_type_array: {
3083 nir_deref_array *array = nir_deref_as_array(tail);
3084 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3085 if (array->deref_array_type ==
3086 nir_deref_array_type_indirect) {
3087 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3088 get_src(ctx,
3089 array->indirect),
3090 "");
3091 }
3092 break;
3093 }
3094 case nir_deref_type_struct: {
3095 nir_deref_struct *deref_struct =
3096 nir_deref_as_struct(tail);
3097 offset = LLVMConstInt(ctx->ac.i32,
3098 deref_struct->index, 0);
3099 break;
3100 }
3101 default:
3102 unreachable("bad deref type");
3103 }
3104 val = ac_build_gep0(&ctx->ac, val, offset);
3105 tail = tail->child;
3106 }
3107 return val;
3108 }
3109
3110 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3111 nir_intrinsic_instr *instr)
3112 {
3113 LLVMValueRef values[8];
3114 int idx = instr->variables[0]->var->data.driver_location;
3115 int ve = instr->dest.ssa.num_components;
3116 unsigned comp = instr->variables[0]->var->data.location_frac;
3117 LLVMValueRef indir_index;
3118 LLVMValueRef ret;
3119 unsigned const_index;
3120 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3121 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3122 instr->variables[0]->var->data.mode == nir_var_shader_in;
3123 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3124 &const_index, &indir_index);
3125
3126 if (instr->dest.ssa.bit_size == 64)
3127 ve *= 2;
3128
3129 switch (instr->variables[0]->var->data.mode) {
3130 case nir_var_shader_in:
3131 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3132 return load_tcs_input(ctx->nctx, instr);
3133 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
3134 LLVMValueRef result;
3135 LLVMValueRef vertex_index = NULL;
3136 LLVMValueRef indir_index = NULL;
3137 unsigned const_index = 0;
3138 unsigned location = instr->variables[0]->var->data.location;
3139 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3140 const bool is_patch = instr->variables[0]->var->data.patch;
3141 const bool is_compact = instr->variables[0]->var->data.compact;
3142
3143 get_deref_offset(ctx, instr->variables[0],
3144 false, NULL, is_patch ? NULL : &vertex_index,
3145 &const_index, &indir_index);
3146
3147 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3148 const_index, location, driver_location,
3149 instr->variables[0]->var->data.location_frac,
3150 instr->num_components,
3151 is_patch, is_compact);
3152 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3153 }
3154
3155 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3156 LLVMValueRef indir_index;
3157 unsigned const_index, vertex_index;
3158 get_deref_offset(ctx, instr->variables[0],
3159 false, &vertex_index, NULL,
3160 &const_index, &indir_index);
3161 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3162 instr->variables[0]->var->data.driver_location,
3163 instr->variables[0]->var->data.location_frac, ve,
3164 vertex_index, const_index,
3165 nir2llvmtype(ctx, instr->variables[0]->var->type));
3166 }
3167
3168 for (unsigned chan = comp; chan < ve + comp; chan++) {
3169 if (indir_index) {
3170 unsigned count = glsl_count_attribute_slots(
3171 instr->variables[0]->var->type,
3172 ctx->stage == MESA_SHADER_VERTEX);
3173 count -= chan / 4;
3174 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3175 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3176 stride, false, true);
3177
3178 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3179 tmp_vec,
3180 indir_index, "");
3181 } else
3182 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3183 }
3184 break;
3185 case nir_var_local:
3186 for (unsigned chan = 0; chan < ve; chan++) {
3187 if (indir_index) {
3188 unsigned count = glsl_count_attribute_slots(
3189 instr->variables[0]->var->type, false);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->locals + idx + chan, count,
3193 stride, true, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else {
3199 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3200 }
3201 }
3202 break;
3203 case nir_var_shared: {
3204 LLVMValueRef address = build_gep_for_deref(ctx,
3205 instr->variables[0]);
3206 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3207 return LLVMBuildBitCast(ctx->ac.builder, val,
3208 get_def_type(ctx, &instr->dest.ssa),
3209 "");
3210 }
3211 case nir_var_shader_out:
3212 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3213 return load_tcs_output(ctx->nctx, instr);
3214
3215 for (unsigned chan = comp; chan < ve + comp; chan++) {
3216 if (indir_index) {
3217 unsigned count = glsl_count_attribute_slots(
3218 instr->variables[0]->var->type, false);
3219 count -= chan / 4;
3220 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3221 &ctx->ac, ctx->outputs + idx + chan, count,
3222 stride, true, true);
3223
3224 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3225 tmp_vec,
3226 indir_index, "");
3227 } else {
3228 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3229 ctx->outputs[idx + chan + const_index * stride],
3230 "");
3231 }
3232 }
3233 break;
3234 default:
3235 unreachable("unhandle variable mode");
3236 }
3237 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3238 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3239 }
3240
3241 static void
3242 visit_store_var(struct ac_nir_context *ctx,
3243 nir_intrinsic_instr *instr)
3244 {
3245 LLVMValueRef temp_ptr, value;
3246 int idx = instr->variables[0]->var->data.driver_location;
3247 unsigned comp = instr->variables[0]->var->data.location_frac;
3248 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3249 int writemask = instr->const_index[0] << comp;
3250 LLVMValueRef indir_index;
3251 unsigned const_index;
3252 get_deref_offset(ctx, instr->variables[0], false,
3253 NULL, NULL, &const_index, &indir_index);
3254
3255 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3256 int old_writemask = writemask;
3257
3258 src = LLVMBuildBitCast(ctx->ac.builder, src,
3259 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3260 "");
3261
3262 writemask = 0;
3263 for (unsigned chan = 0; chan < 4; chan++) {
3264 if (old_writemask & (1 << chan))
3265 writemask |= 3u << (2 * chan);
3266 }
3267 }
3268
3269 switch (instr->variables[0]->var->data.mode) {
3270 case nir_var_shader_out:
3271
3272 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3273 store_tcs_output(ctx->nctx, instr, src, writemask);
3274 return;
3275 }
3276
3277 for (unsigned chan = 0; chan < 8; chan++) {
3278 int stride = 4;
3279 if (!(writemask & (1 << chan)))
3280 continue;
3281
3282 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3283
3284 if (instr->variables[0]->var->data.compact)
3285 stride = 1;
3286 if (indir_index) {
3287 unsigned count = glsl_count_attribute_slots(
3288 instr->variables[0]->var->type, false);
3289 count -= chan / 4;
3290 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3291 &ctx->ac, ctx->outputs + idx + chan, count,
3292 stride, true, true);
3293
3294 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3295 value, indir_index, "");
3296 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3297 count, stride, tmp_vec);
3298
3299 } else {
3300 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3301
3302 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3303 }
3304 }
3305 break;
3306 case nir_var_local:
3307 for (unsigned chan = 0; chan < 8; chan++) {
3308 if (!(writemask & (1 << chan)))
3309 continue;
3310
3311 value = llvm_extract_elem(&ctx->ac, src, chan);
3312 if (indir_index) {
3313 unsigned count = glsl_count_attribute_slots(
3314 instr->variables[0]->var->type, false);
3315 count -= chan / 4;
3316 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3317 &ctx->ac, ctx->locals + idx + chan, count,
3318 4, true, true);
3319
3320 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3321 value, indir_index, "");
3322 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3323 count, 4, tmp_vec);
3324 } else {
3325 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3326
3327 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3328 }
3329 }
3330 break;
3331 case nir_var_shared: {
3332 int writemask = instr->const_index[0];
3333 LLVMValueRef address = build_gep_for_deref(ctx,
3334 instr->variables[0]);
3335 LLVMValueRef val = get_src(ctx, instr->src[0]);
3336 unsigned components =
3337 glsl_get_vector_elements(
3338 nir_deref_tail(&instr->variables[0]->deref)->type);
3339 if (writemask == (1 << components) - 1) {
3340 val = LLVMBuildBitCast(
3341 ctx->ac.builder, val,
3342 LLVMGetElementType(LLVMTypeOf(address)), "");
3343 LLVMBuildStore(ctx->ac.builder, val, address);
3344 } else {
3345 for (unsigned chan = 0; chan < 4; chan++) {
3346 if (!(writemask & (1 << chan)))
3347 continue;
3348 LLVMValueRef ptr =
3349 LLVMBuildStructGEP(ctx->ac.builder,
3350 address, chan, "");
3351 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3352 chan);
3353 src = LLVMBuildBitCast(
3354 ctx->ac.builder, src,
3355 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3356 LLVMBuildStore(ctx->ac.builder, src, ptr);
3357 }
3358 }
3359 break;
3360 }
3361 default:
3362 break;
3363 }
3364 }
3365
3366 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3367 {
3368 switch (dim) {
3369 case GLSL_SAMPLER_DIM_BUF:
3370 return 1;
3371 case GLSL_SAMPLER_DIM_1D:
3372 return array ? 2 : 1;
3373 case GLSL_SAMPLER_DIM_2D:
3374 return array ? 3 : 2;
3375 case GLSL_SAMPLER_DIM_MS:
3376 return array ? 4 : 3;
3377 case GLSL_SAMPLER_DIM_3D:
3378 case GLSL_SAMPLER_DIM_CUBE:
3379 return 3;
3380 case GLSL_SAMPLER_DIM_RECT:
3381 case GLSL_SAMPLER_DIM_SUBPASS:
3382 return 2;
3383 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3384 return 3;
3385 default:
3386 break;
3387 }
3388 return 0;
3389 }
3390
3391
3392
3393 /* Adjust the sample index according to FMASK.
3394 *
3395 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3396 * which is the identity mapping. Each nibble says which physical sample
3397 * should be fetched to get that sample.
3398 *
3399 * For example, 0x11111100 means there are only 2 samples stored and
3400 * the second sample covers 3/4 of the pixel. When reading samples 0
3401 * and 1, return physical sample 0 (determined by the first two 0s
3402 * in FMASK), otherwise return physical sample 1.
3403 *
3404 * The sample index should be adjusted as follows:
3405 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3406 */
3407 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3408 LLVMValueRef coord_x, LLVMValueRef coord_y,
3409 LLVMValueRef coord_z,
3410 LLVMValueRef sample_index,
3411 LLVMValueRef fmask_desc_ptr)
3412 {
3413 LLVMValueRef fmask_load_address[4];
3414 LLVMValueRef res;
3415
3416 fmask_load_address[0] = coord_x;
3417 fmask_load_address[1] = coord_y;
3418 if (coord_z) {
3419 fmask_load_address[2] = coord_z;
3420 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3421 }
3422
3423 struct ac_image_args args = {0};
3424
3425 args.opcode = ac_image_load;
3426 args.da = coord_z ? true : false;
3427 args.resource = fmask_desc_ptr;
3428 args.dmask = 0xf;
3429 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3430
3431 res = ac_build_image_opcode(ctx, &args);
3432
3433 res = ac_to_integer(ctx, res);
3434 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3435 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3436
3437 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3438 res,
3439 ctx->i32_0, "");
3440
3441 LLVMValueRef sample_index4 =
3442 LLVMBuildMul(ctx->builder, sample_index, four, "");
3443 LLVMValueRef shifted_fmask =
3444 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3445 LLVMValueRef final_sample =
3446 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3447
3448 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3449 * resource descriptor is 0 (invalid),
3450 */
3451 LLVMValueRef fmask_desc =
3452 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3453 ctx->v8i32, "");
3454
3455 LLVMValueRef fmask_word1 =
3456 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3457 ctx->i32_1, "");
3458
3459 LLVMValueRef word1_is_nonzero =
3460 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3461 fmask_word1, ctx->i32_0, "");
3462
3463 /* Replace the MSAA sample index. */
3464 sample_index =
3465 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3466 final_sample, sample_index, "");
3467 return sample_index;
3468 }
3469
3470 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3471 const nir_intrinsic_instr *instr)
3472 {
3473 const struct glsl_type *type = instr->variables[0]->var->type;
3474 if(instr->variables[0]->deref.child)
3475 type = instr->variables[0]->deref.child->type;
3476
3477 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3478 LLVMValueRef coords[4];
3479 LLVMValueRef masks[] = {
3480 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3481 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3482 };
3483 LLVMValueRef res;
3484 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3485
3486 int count;
3487 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3488 bool is_array = glsl_sampler_type_is_array(type);
3489 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3490 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3491 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3492 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3493 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3494 count = image_type_to_components_count(dim, is_array);
3495
3496 if (is_ms) {
3497 LLVMValueRef fmask_load_address[3];
3498 int chan;
3499
3500 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3501 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3502 if (is_array)
3503 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3504 else
3505 fmask_load_address[2] = NULL;
3506 if (add_frag_pos) {
3507 for (chan = 0; chan < 2; ++chan)
3508 fmask_load_address[chan] =
3509 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3510 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3511 ctx->ac.i32, ""), "");
3512 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3513 }
3514 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3515 fmask_load_address[0],
3516 fmask_load_address[1],
3517 fmask_load_address[2],
3518 sample_index,
3519 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3520 }
3521 if (count == 1 && !gfx9_1d) {
3522 if (instr->src[0].ssa->num_components)
3523 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3524 else
3525 res = src0;
3526 } else {
3527 int chan;
3528 if (is_ms)
3529 count--;
3530 for (chan = 0; chan < count; ++chan) {
3531 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3532 }
3533 if (add_frag_pos) {
3534 for (chan = 0; chan < 2; ++chan)
3535 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3536 ctx->ac.i32, ""), "");
3537 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3538 count++;
3539 }
3540
3541 if (gfx9_1d) {
3542 if (is_array) {
3543 coords[2] = coords[1];
3544 coords[1] = ctx->ac.i32_0;
3545 } else
3546 coords[1] = ctx->ac.i32_0;
3547 count++;
3548 }
3549
3550 if (is_ms) {
3551 coords[count] = sample_index;
3552 count++;
3553 }
3554
3555 if (count == 3) {
3556 coords[3] = LLVMGetUndef(ctx->ac.i32);
3557 count = 4;
3558 }
3559 res = ac_build_gather_values(&ctx->ac, coords, count);
3560 }
3561 return res;
3562 }
3563
3564 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3565 const nir_intrinsic_instr *instr)
3566 {
3567 LLVMValueRef params[7];
3568 LLVMValueRef res;
3569 char intrinsic_name[64];
3570 const nir_variable *var = instr->variables[0]->var;
3571 const struct glsl_type *type = var->type;
3572
3573 if(instr->variables[0]->deref.child)
3574 type = instr->variables[0]->deref.child->type;
3575
3576 type = glsl_without_array(type);
3577 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3578 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3579 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3580 ctx->ac.i32_0, ""); /* vindex */
3581 params[2] = ctx->ac.i32_0; /* voffset */
3582 params[3] = ctx->ac.i1false; /* glc */
3583 params[4] = ctx->ac.i1false; /* slc */
3584 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3585 params, 5, 0);
3586
3587 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3588 res = ac_to_integer(&ctx->ac, res);
3589 } else {
3590 bool is_da = glsl_sampler_type_is_array(type) ||
3591 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3592 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3593 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3594 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3595 LLVMValueRef glc = ctx->ac.i1false;
3596 LLVMValueRef slc = ctx->ac.i1false;
3597
3598 params[0] = get_image_coords(ctx, instr);
3599 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3600 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3601 if (HAVE_LLVM <= 0x0309) {
3602 params[3] = ctx->ac.i1false; /* r128 */
3603 params[4] = da;
3604 params[5] = glc;
3605 params[6] = slc;
3606 } else {
3607 LLVMValueRef lwe = ctx->ac.i1false;
3608 params[3] = glc;
3609 params[4] = slc;
3610 params[5] = lwe;
3611 params[6] = da;
3612 }
3613
3614 ac_get_image_intr_name("llvm.amdgcn.image.load",
3615 ctx->ac.v4f32, /* vdata */
3616 LLVMTypeOf(params[0]), /* coords */
3617 LLVMTypeOf(params[1]), /* rsrc */
3618 intrinsic_name, sizeof(intrinsic_name));
3619
3620 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3621 params, 7, AC_FUNC_ATTR_READONLY);
3622 }
3623 return ac_to_integer(&ctx->ac, res);
3624 }
3625
3626 static void visit_image_store(struct ac_nir_context *ctx,
3627 nir_intrinsic_instr *instr)
3628 {
3629 LLVMValueRef params[8];
3630 char intrinsic_name[64];
3631 const nir_variable *var = instr->variables[0]->var;
3632 const struct glsl_type *type = glsl_without_array(var->type);
3633 LLVMValueRef glc = ctx->ac.i1false;
3634 bool force_glc = ctx->ac.chip_class == SI;
3635 if (force_glc)
3636 glc = ctx->ac.i1true;
3637
3638 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3639 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3640 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3641 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3642 ctx->ac.i32_0, ""); /* vindex */
3643 params[3] = ctx->ac.i32_0; /* voffset */
3644 params[4] = glc; /* glc */
3645 params[5] = ctx->ac.i1false; /* slc */
3646 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3647 params, 6, 0);
3648 } else {
3649 bool is_da = glsl_sampler_type_is_array(type) ||
3650 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3651 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3652 LLVMValueRef slc = ctx->ac.i1false;
3653
3654 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3655 params[1] = get_image_coords(ctx, instr); /* coords */
3656 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3657 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3658 if (HAVE_LLVM <= 0x0309) {
3659 params[4] = ctx->ac.i1false; /* r128 */
3660 params[5] = da;
3661 params[6] = glc;
3662 params[7] = slc;
3663 } else {
3664 LLVMValueRef lwe = ctx->ac.i1false;
3665 params[4] = glc;
3666 params[5] = slc;
3667 params[6] = lwe;
3668 params[7] = da;
3669 }
3670
3671 ac_get_image_intr_name("llvm.amdgcn.image.store",
3672 LLVMTypeOf(params[0]), /* vdata */
3673 LLVMTypeOf(params[1]), /* coords */
3674 LLVMTypeOf(params[2]), /* rsrc */
3675 intrinsic_name, sizeof(intrinsic_name));
3676
3677 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3678 params, 8, 0);
3679 }
3680
3681 }
3682
3683 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3684 const nir_intrinsic_instr *instr)
3685 {
3686 LLVMValueRef params[7];
3687 int param_count = 0;
3688 const nir_variable *var = instr->variables[0]->var;
3689
3690 const char *atomic_name;
3691 char intrinsic_name[41];
3692 const struct glsl_type *type = glsl_without_array(var->type);
3693 MAYBE_UNUSED int length;
3694
3695 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3696
3697 switch (instr->intrinsic) {
3698 case nir_intrinsic_image_atomic_add:
3699 atomic_name = "add";
3700 break;
3701 case nir_intrinsic_image_atomic_min:
3702 atomic_name = is_unsigned ? "umin" : "smin";
3703 break;
3704 case nir_intrinsic_image_atomic_max:
3705 atomic_name = is_unsigned ? "umax" : "smax";
3706 break;
3707 case nir_intrinsic_image_atomic_and:
3708 atomic_name = "and";
3709 break;
3710 case nir_intrinsic_image_atomic_or:
3711 atomic_name = "or";
3712 break;
3713 case nir_intrinsic_image_atomic_xor:
3714 atomic_name = "xor";
3715 break;
3716 case nir_intrinsic_image_atomic_exchange:
3717 atomic_name = "swap";
3718 break;
3719 case nir_intrinsic_image_atomic_comp_swap:
3720 atomic_name = "cmpswap";
3721 break;
3722 default:
3723 abort();
3724 }
3725
3726 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3727 params[param_count++] = get_src(ctx, instr->src[3]);
3728 params[param_count++] = get_src(ctx, instr->src[2]);
3729
3730 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3731 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3732 NULL, true, true);
3733 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3734 ctx->ac.i32_0, ""); /* vindex */
3735 params[param_count++] = ctx->ac.i32_0; /* voffset */
3736 params[param_count++] = ctx->ac.i1false; /* slc */
3737
3738 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3739 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3740 } else {
3741 char coords_type[8];
3742
3743 bool da = glsl_sampler_type_is_array(type) ||
3744 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3745
3746 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3747 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3748 NULL, true, true);
3749 params[param_count++] = ctx->ac.i1false; /* r128 */
3750 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3751 params[param_count++] = ctx->ac.i1false; /* slc */
3752
3753 build_int_type_name(LLVMTypeOf(coords),
3754 coords_type, sizeof(coords_type));
3755
3756 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3757 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3758 }
3759
3760 assert(length < sizeof(intrinsic_name));
3761 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3762 }
3763
3764 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3765 const nir_intrinsic_instr *instr)
3766 {
3767 LLVMValueRef res;
3768 const nir_variable *var = instr->variables[0]->var;
3769 const struct glsl_type *type = instr->variables[0]->var->type;
3770 bool da = glsl_sampler_type_is_array(var->type) ||
3771 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3772 if(instr->variables[0]->deref.child)
3773 type = instr->variables[0]->deref.child->type;
3774
3775 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3776 return get_buffer_size(ctx,
3777 get_sampler_desc(ctx, instr->variables[0],
3778 AC_DESC_BUFFER, NULL, true, false), true);
3779
3780 struct ac_image_args args = { 0 };
3781
3782 args.da = da;
3783 args.dmask = 0xf;
3784 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3785 args.opcode = ac_image_get_resinfo;
3786 args.addr = ctx->ac.i32_0;
3787
3788 res = ac_build_image_opcode(&ctx->ac, &args);
3789
3790 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3791
3792 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3793 glsl_sampler_type_is_array(type)) {
3794 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3795 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3796 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3797 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3798 }
3799 if (ctx->ac.chip_class >= GFX9 &&
3800 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3801 glsl_sampler_type_is_array(type)) {
3802 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3803 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3804 ctx->ac.i32_1, "");
3805
3806 }
3807 return res;
3808 }
3809
3810 #define NOOP_WAITCNT 0xf7f
3811 #define LGKM_CNT 0x07f
3812 #define VM_CNT 0xf70
3813
3814 static void emit_membar(struct nir_to_llvm_context *ctx,
3815 const nir_intrinsic_instr *instr)
3816 {
3817 unsigned waitcnt = NOOP_WAITCNT;
3818
3819 switch (instr->intrinsic) {
3820 case nir_intrinsic_memory_barrier:
3821 case nir_intrinsic_group_memory_barrier:
3822 waitcnt &= VM_CNT & LGKM_CNT;
3823 break;
3824 case nir_intrinsic_memory_barrier_atomic_counter:
3825 case nir_intrinsic_memory_barrier_buffer:
3826 case nir_intrinsic_memory_barrier_image:
3827 waitcnt &= VM_CNT;
3828 break;
3829 case nir_intrinsic_memory_barrier_shared:
3830 waitcnt &= LGKM_CNT;
3831 break;
3832 default:
3833 break;
3834 }
3835 if (waitcnt != NOOP_WAITCNT)
3836 ac_build_waitcnt(&ctx->ac, waitcnt);
3837 }
3838
3839 static void emit_barrier(struct nir_to_llvm_context *ctx)
3840 {
3841 /* SI only (thanks to a hw bug workaround):
3842 * The real barrier instruction isn’t needed, because an entire patch
3843 * always fits into a single wave.
3844 */
3845 if (ctx->options->chip_class == SI &&
3846 ctx->stage == MESA_SHADER_TESS_CTRL) {
3847 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3848 return;
3849 }
3850 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3851 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3852 }
3853
3854 static void emit_discard_if(struct ac_nir_context *ctx,
3855 const nir_intrinsic_instr *instr)
3856 {
3857 LLVMValueRef cond;
3858
3859 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3860 get_src(ctx, instr->src[0]),
3861 ctx->ac.i32_0, "");
3862 ac_build_kill_if_false(&ctx->ac, cond);
3863 }
3864
3865 static LLVMValueRef
3866 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3867 {
3868 LLVMValueRef result;
3869 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3870 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3871 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3872
3873 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3874 }
3875
3876 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3877 const nir_intrinsic_instr *instr)
3878 {
3879 LLVMValueRef ptr, result;
3880 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3881 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3882
3883 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3884 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3885 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3886 ptr, src, src1,
3887 LLVMAtomicOrderingSequentiallyConsistent,
3888 LLVMAtomicOrderingSequentiallyConsistent,
3889 false);
3890 } else {
3891 LLVMAtomicRMWBinOp op;
3892 switch (instr->intrinsic) {
3893 case nir_intrinsic_var_atomic_add:
3894 op = LLVMAtomicRMWBinOpAdd;
3895 break;
3896 case nir_intrinsic_var_atomic_umin:
3897 op = LLVMAtomicRMWBinOpUMin;
3898 break;
3899 case nir_intrinsic_var_atomic_umax:
3900 op = LLVMAtomicRMWBinOpUMax;
3901 break;
3902 case nir_intrinsic_var_atomic_imin:
3903 op = LLVMAtomicRMWBinOpMin;
3904 break;
3905 case nir_intrinsic_var_atomic_imax:
3906 op = LLVMAtomicRMWBinOpMax;
3907 break;
3908 case nir_intrinsic_var_atomic_and:
3909 op = LLVMAtomicRMWBinOpAnd;
3910 break;
3911 case nir_intrinsic_var_atomic_or:
3912 op = LLVMAtomicRMWBinOpOr;
3913 break;
3914 case nir_intrinsic_var_atomic_xor:
3915 op = LLVMAtomicRMWBinOpXor;
3916 break;
3917 case nir_intrinsic_var_atomic_exchange:
3918 op = LLVMAtomicRMWBinOpXchg;
3919 break;
3920 default:
3921 return NULL;
3922 }
3923
3924 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3925 LLVMAtomicOrderingSequentiallyConsistent,
3926 false);
3927 }
3928 return result;
3929 }
3930
3931 #define INTERP_CENTER 0
3932 #define INTERP_CENTROID 1
3933 #define INTERP_SAMPLE 2
3934
3935 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3936 enum glsl_interp_mode interp, unsigned location)
3937 {
3938 switch (interp) {
3939 case INTERP_MODE_FLAT:
3940 default:
3941 return NULL;
3942 case INTERP_MODE_SMOOTH:
3943 case INTERP_MODE_NONE:
3944 if (location == INTERP_CENTER)
3945 return ctx->persp_center;
3946 else if (location == INTERP_CENTROID)
3947 return ctx->persp_centroid;
3948 else if (location == INTERP_SAMPLE)
3949 return ctx->persp_sample;
3950 break;
3951 case INTERP_MODE_NOPERSPECTIVE:
3952 if (location == INTERP_CENTER)
3953 return ctx->linear_center;
3954 else if (location == INTERP_CENTROID)
3955 return ctx->linear_centroid;
3956 else if (location == INTERP_SAMPLE)
3957 return ctx->linear_sample;
3958 break;
3959 }
3960 return NULL;
3961 }
3962
3963 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3964 LLVMValueRef sample_id)
3965 {
3966 LLVMValueRef result;
3967 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3968
3969 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3970 const_array(ctx->ac.v2f32, 64), "");
3971
3972 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3973 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3974
3975 return result;
3976 }
3977
3978 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3979 {
3980 LLVMValueRef values[2];
3981
3982 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3983 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3984 return ac_build_gather_values(&ctx->ac, values, 2);
3985 }
3986
3987 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3988 const nir_intrinsic_instr *instr)
3989 {
3990 LLVMValueRef result[4];
3991 LLVMValueRef interp_param, attr_number;
3992 unsigned location;
3993 unsigned chan;
3994 LLVMValueRef src_c0 = NULL;
3995 LLVMValueRef src_c1 = NULL;
3996 LLVMValueRef src0 = NULL;
3997 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3998 switch (instr->intrinsic) {
3999 case nir_intrinsic_interp_var_at_centroid:
4000 location = INTERP_CENTROID;
4001 break;
4002 case nir_intrinsic_interp_var_at_sample:
4003 case nir_intrinsic_interp_var_at_offset:
4004 location = INTERP_CENTER;
4005 src0 = get_src(ctx->nir, instr->src[0]);
4006 break;
4007 default:
4008 break;
4009 }
4010
4011 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4012 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4013 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4014 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4015 LLVMValueRef sample_position;
4016 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4017
4018 /* fetch sample ID */
4019 sample_position = load_sample_position(ctx, src0);
4020
4021 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4022 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4023 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4024 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4025 }
4026 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4027 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4028
4029 if (location == INTERP_CENTER) {
4030 LLVMValueRef ij_out[2];
4031 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4032
4033 /*
4034 * take the I then J parameters, and the DDX/Y for it, and
4035 * calculate the IJ inputs for the interpolator.
4036 * temp1 = ddx * offset/sample.x + I;
4037 * interp_param.I = ddy * offset/sample.y + temp1;
4038 * temp1 = ddx * offset/sample.x + J;
4039 * interp_param.J = ddy * offset/sample.y + temp1;
4040 */
4041 for (unsigned i = 0; i < 2; i++) {
4042 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4043 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4044 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4045 ddxy_out, ix_ll, "");
4046 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4047 ddxy_out, iy_ll, "");
4048 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4049 interp_param, ix_ll, "");
4050 LLVMValueRef temp1, temp2;
4051
4052 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4053 ctx->ac.f32, "");
4054
4055 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4056 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4057
4058 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4059 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4060
4061 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4062 temp2, ctx->ac.i32, "");
4063 }
4064 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4065
4066 }
4067
4068 for (chan = 0; chan < 4; chan++) {
4069 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4070
4071 if (interp_param) {
4072 interp_param = LLVMBuildBitCast(ctx->builder,
4073 interp_param, ctx->ac.v2f32, "");
4074 LLVMValueRef i = LLVMBuildExtractElement(
4075 ctx->builder, interp_param, ctx->ac.i32_0, "");
4076 LLVMValueRef j = LLVMBuildExtractElement(
4077 ctx->builder, interp_param, ctx->ac.i32_1, "");
4078
4079 result[chan] = ac_build_fs_interp(&ctx->ac,
4080 llvm_chan, attr_number,
4081 ctx->prim_mask, i, j);
4082 } else {
4083 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4084 LLVMConstInt(ctx->ac.i32, 2, false),
4085 llvm_chan, attr_number,
4086 ctx->prim_mask);
4087 }
4088 }
4089 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4090 instr->variables[0]->var->data.location_frac);
4091 }
4092
4093 static void
4094 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4095 {
4096 LLVMValueRef gs_next_vertex;
4097 LLVMValueRef can_emit;
4098 int idx;
4099 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4100
4101 /* Write vertex attribute values to GSVS ring */
4102 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4103 ctx->gs_next_vertex,
4104 "");
4105
4106 /* If this thread has already emitted the declared maximum number of
4107 * vertices, kill it: excessive vertex emissions are not supposed to
4108 * have any effect, and GS threads have no externally observable
4109 * effects other than emitting vertices.
4110 */
4111 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4112 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4113 ac_build_kill_if_false(&ctx->ac, can_emit);
4114
4115 /* loop num outputs */
4116 idx = 0;
4117 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4118 LLVMValueRef *out_ptr = &addrs[i * 4];
4119 int length = 4;
4120 int slot = idx;
4121 int slot_inc = 1;
4122
4123 if (!(ctx->output_mask & (1ull << i)))
4124 continue;
4125
4126 if (i == VARYING_SLOT_CLIP_DIST0) {
4127 /* pack clip and cull into a single set of slots */
4128 length = ctx->num_output_clips + ctx->num_output_culls;
4129 if (length > 4)
4130 slot_inc = 2;
4131 }
4132 for (unsigned j = 0; j < length; j++) {
4133 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4134 out_ptr[j], "");
4135 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4136 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4137 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4138
4139 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4140
4141 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4142 out_val, 1,
4143 voffset, ctx->gs2vs_offset, 0,
4144 1, 1, true, true);
4145 }
4146 idx += slot_inc;
4147 }
4148
4149 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4150 ctx->ac.i32_1, "");
4151 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4152
4153 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4154 }
4155
4156 static void
4157 visit_end_primitive(struct nir_to_llvm_context *ctx,
4158 const nir_intrinsic_instr *instr)
4159 {
4160 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4161 }
4162
4163 static LLVMValueRef
4164 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4165 const nir_intrinsic_instr *instr)
4166 {
4167 LLVMValueRef coord[4] = {
4168 ctx->tes_u,
4169 ctx->tes_v,
4170 ctx->ac.f32_0,
4171 ctx->ac.f32_0,
4172 };
4173
4174 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4175 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4176 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4177
4178 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4179 return LLVMBuildBitCast(ctx->builder, result,
4180 get_def_type(ctx->nir, &instr->dest.ssa), "");
4181 }
4182
4183 static void visit_intrinsic(struct ac_nir_context *ctx,
4184 nir_intrinsic_instr *instr)
4185 {
4186 LLVMValueRef result = NULL;
4187
4188 switch (instr->intrinsic) {
4189 case nir_intrinsic_load_work_group_id: {
4190 LLVMValueRef values[3];
4191
4192 for (int i = 0; i < 3; i++) {
4193 values[i] = ctx->nctx->workgroup_ids[i] ?
4194 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4195 }
4196
4197 result = ac_build_gather_values(&ctx->ac, values, 3);
4198 break;
4199 }
4200 case nir_intrinsic_load_base_vertex: {
4201 result = ctx->abi->base_vertex;
4202 break;
4203 }
4204 case nir_intrinsic_load_vertex_id_zero_base: {
4205 result = ctx->abi->vertex_id;
4206 break;
4207 }
4208 case nir_intrinsic_load_local_invocation_id: {
4209 result = ctx->nctx->local_invocation_ids;
4210 break;
4211 }
4212 case nir_intrinsic_load_base_instance:
4213 result = ctx->abi->start_instance;
4214 break;
4215 case nir_intrinsic_load_draw_id:
4216 result = ctx->abi->draw_id;
4217 break;
4218 case nir_intrinsic_load_view_index:
4219 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4220 break;
4221 case nir_intrinsic_load_invocation_id:
4222 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4223 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4224 else
4225 result = ctx->abi->gs_invocation_id;
4226 break;
4227 case nir_intrinsic_load_primitive_id:
4228 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4229 result = ctx->abi->gs_prim_id;
4230 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4231 result = ctx->nctx->tcs_patch_id;
4232 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4233 result = ctx->nctx->tes_patch_id;
4234 } else
4235 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4236 break;
4237 case nir_intrinsic_load_sample_id:
4238 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4239 break;
4240 case nir_intrinsic_load_sample_pos:
4241 result = load_sample_pos(ctx);
4242 break;
4243 case nir_intrinsic_load_sample_mask_in:
4244 result = ctx->abi->sample_coverage;
4245 break;
4246 case nir_intrinsic_load_frag_coord: {
4247 LLVMValueRef values[4] = {
4248 ctx->abi->frag_pos[0],
4249 ctx->abi->frag_pos[1],
4250 ctx->abi->frag_pos[2],
4251 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4252 };
4253 result = ac_build_gather_values(&ctx->ac, values, 4);
4254 break;
4255 }
4256 case nir_intrinsic_load_front_face:
4257 result = ctx->abi->front_face;
4258 break;
4259 case nir_intrinsic_load_instance_id:
4260 result = ctx->abi->instance_id;
4261 break;
4262 case nir_intrinsic_load_num_work_groups:
4263 result = ctx->nctx->num_work_groups;
4264 break;
4265 case nir_intrinsic_load_local_invocation_index:
4266 result = visit_load_local_invocation_index(ctx->nctx);
4267 break;
4268 case nir_intrinsic_load_push_constant:
4269 result = visit_load_push_constant(ctx->nctx, instr);
4270 break;
4271 case nir_intrinsic_vulkan_resource_index:
4272 result = visit_vulkan_resource_index(ctx->nctx, instr);
4273 break;
4274 case nir_intrinsic_vulkan_resource_reindex:
4275 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4276 break;
4277 case nir_intrinsic_store_ssbo:
4278 visit_store_ssbo(ctx, instr);
4279 break;
4280 case nir_intrinsic_load_ssbo:
4281 result = visit_load_buffer(ctx, instr);
4282 break;
4283 case nir_intrinsic_ssbo_atomic_add:
4284 case nir_intrinsic_ssbo_atomic_imin:
4285 case nir_intrinsic_ssbo_atomic_umin:
4286 case nir_intrinsic_ssbo_atomic_imax:
4287 case nir_intrinsic_ssbo_atomic_umax:
4288 case nir_intrinsic_ssbo_atomic_and:
4289 case nir_intrinsic_ssbo_atomic_or:
4290 case nir_intrinsic_ssbo_atomic_xor:
4291 case nir_intrinsic_ssbo_atomic_exchange:
4292 case nir_intrinsic_ssbo_atomic_comp_swap:
4293 result = visit_atomic_ssbo(ctx, instr);
4294 break;
4295 case nir_intrinsic_load_ubo:
4296 result = visit_load_ubo_buffer(ctx, instr);
4297 break;
4298 case nir_intrinsic_get_buffer_size:
4299 result = visit_get_buffer_size(ctx, instr);
4300 break;
4301 case nir_intrinsic_load_var:
4302 result = visit_load_var(ctx, instr);
4303 break;
4304 case nir_intrinsic_store_var:
4305 visit_store_var(ctx, instr);
4306 break;
4307 case nir_intrinsic_image_load:
4308 result = visit_image_load(ctx, instr);
4309 break;
4310 case nir_intrinsic_image_store:
4311 visit_image_store(ctx, instr);
4312 break;
4313 case nir_intrinsic_image_atomic_add:
4314 case nir_intrinsic_image_atomic_min:
4315 case nir_intrinsic_image_atomic_max:
4316 case nir_intrinsic_image_atomic_and:
4317 case nir_intrinsic_image_atomic_or:
4318 case nir_intrinsic_image_atomic_xor:
4319 case nir_intrinsic_image_atomic_exchange:
4320 case nir_intrinsic_image_atomic_comp_swap:
4321 result = visit_image_atomic(ctx, instr);
4322 break;
4323 case nir_intrinsic_image_size:
4324 result = visit_image_size(ctx, instr);
4325 break;
4326 case nir_intrinsic_discard:
4327 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4328 LLVMVoidTypeInContext(ctx->ac.context),
4329 NULL, 0, AC_FUNC_ATTR_LEGACY);
4330 break;
4331 case nir_intrinsic_discard_if:
4332 emit_discard_if(ctx, instr);
4333 break;
4334 case nir_intrinsic_memory_barrier:
4335 case nir_intrinsic_group_memory_barrier:
4336 case nir_intrinsic_memory_barrier_atomic_counter:
4337 case nir_intrinsic_memory_barrier_buffer:
4338 case nir_intrinsic_memory_barrier_image:
4339 case nir_intrinsic_memory_barrier_shared:
4340 emit_membar(ctx->nctx, instr);
4341 break;
4342 case nir_intrinsic_barrier:
4343 emit_barrier(ctx->nctx);
4344 break;
4345 case nir_intrinsic_var_atomic_add:
4346 case nir_intrinsic_var_atomic_imin:
4347 case nir_intrinsic_var_atomic_umin:
4348 case nir_intrinsic_var_atomic_imax:
4349 case nir_intrinsic_var_atomic_umax:
4350 case nir_intrinsic_var_atomic_and:
4351 case nir_intrinsic_var_atomic_or:
4352 case nir_intrinsic_var_atomic_xor:
4353 case nir_intrinsic_var_atomic_exchange:
4354 case nir_intrinsic_var_atomic_comp_swap:
4355 result = visit_var_atomic(ctx->nctx, instr);
4356 break;
4357 case nir_intrinsic_interp_var_at_centroid:
4358 case nir_intrinsic_interp_var_at_sample:
4359 case nir_intrinsic_interp_var_at_offset:
4360 result = visit_interp(ctx->nctx, instr);
4361 break;
4362 case nir_intrinsic_emit_vertex:
4363 assert(instr->const_index[0] == 0);
4364 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4365 break;
4366 case nir_intrinsic_end_primitive:
4367 visit_end_primitive(ctx->nctx, instr);
4368 break;
4369 case nir_intrinsic_load_tess_coord:
4370 result = visit_load_tess_coord(ctx->nctx, instr);
4371 break;
4372 case nir_intrinsic_load_patch_vertices_in:
4373 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4374 break;
4375 default:
4376 fprintf(stderr, "Unknown intrinsic: ");
4377 nir_print_instr(&instr->instr, stderr);
4378 fprintf(stderr, "\n");
4379 break;
4380 }
4381 if (result) {
4382 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4383 }
4384 }
4385
4386 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4387 LLVMValueRef buffer_ptr, bool write)
4388 {
4389 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4390
4391 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4392 ctx->shader_info->fs.writes_memory = true;
4393
4394 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4395 }
4396
4397 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4398 {
4399 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4400
4401 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4402 }
4403
4404 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4405 unsigned descriptor_set,
4406 unsigned base_index,
4407 unsigned constant_index,
4408 LLVMValueRef index,
4409 enum ac_descriptor_type desc_type,
4410 bool image, bool write)
4411 {
4412 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4413 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4414 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4415 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4416 unsigned offset = binding->offset;
4417 unsigned stride = binding->size;
4418 unsigned type_size;
4419 LLVMBuilderRef builder = ctx->builder;
4420 LLVMTypeRef type;
4421
4422 assert(base_index < layout->binding_count);
4423
4424 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4425 ctx->shader_info->fs.writes_memory = true;
4426
4427 switch (desc_type) {
4428 case AC_DESC_IMAGE:
4429 type = ctx->ac.v8i32;
4430 type_size = 32;
4431 break;
4432 case AC_DESC_FMASK:
4433 type = ctx->ac.v8i32;
4434 offset += 32;
4435 type_size = 32;
4436 break;
4437 case AC_DESC_SAMPLER:
4438 type = ctx->ac.v4i32;
4439 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4440 offset += 64;
4441
4442 type_size = 16;
4443 break;
4444 case AC_DESC_BUFFER:
4445 type = ctx->ac.v4i32;
4446 type_size = 16;
4447 break;
4448 default:
4449 unreachable("invalid desc_type\n");
4450 }
4451
4452 offset += constant_index * stride;
4453
4454 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4455 (!index || binding->immutable_samplers_equal)) {
4456 if (binding->immutable_samplers_equal)
4457 constant_index = 0;
4458
4459 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4460
4461 LLVMValueRef constants[] = {
4462 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4463 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4464 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4465 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4466 };
4467 return ac_build_gather_values(&ctx->ac, constants, 4);
4468 }
4469
4470 assert(stride % type_size == 0);
4471
4472 if (!index)
4473 index = ctx->ac.i32_0;
4474
4475 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4476
4477 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4478 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4479
4480 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4481 }
4482
4483 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4484 const nir_deref_var *deref,
4485 enum ac_descriptor_type desc_type,
4486 const nir_tex_instr *tex_instr,
4487 bool image, bool write)
4488 {
4489 LLVMValueRef index = NULL;
4490 unsigned constant_index = 0;
4491 unsigned descriptor_set;
4492 unsigned base_index;
4493
4494 if (!deref) {
4495 assert(tex_instr && !image);
4496 descriptor_set = 0;
4497 base_index = tex_instr->sampler_index;
4498 } else {
4499 const nir_deref *tail = &deref->deref;
4500 while (tail->child) {
4501 const nir_deref_array *child = nir_deref_as_array(tail->child);
4502 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4503
4504 if (!array_size)
4505 array_size = 1;
4506
4507 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4508
4509 if (child->deref_array_type == nir_deref_array_type_indirect) {
4510 LLVMValueRef indirect = get_src(ctx, child->indirect);
4511
4512 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4513 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4514
4515 if (!index)
4516 index = indirect;
4517 else
4518 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4519 }
4520
4521 constant_index += child->base_offset * array_size;
4522
4523 tail = &child->deref;
4524 }
4525 descriptor_set = deref->var->data.descriptor_set;
4526 base_index = deref->var->data.binding;
4527 }
4528
4529 return ctx->abi->load_sampler_desc(ctx->abi,
4530 descriptor_set,
4531 base_index,
4532 constant_index, index,
4533 desc_type, image, write);
4534 }
4535
4536 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4537 struct ac_image_args *args,
4538 const nir_tex_instr *instr,
4539 nir_texop op,
4540 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4541 LLVMValueRef *param, unsigned count,
4542 unsigned dmask)
4543 {
4544 unsigned is_rect = 0;
4545 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4546
4547 if (op == nir_texop_lod)
4548 da = false;
4549 /* Pad to power of two vector */
4550 while (count < util_next_power_of_two(count))
4551 param[count++] = LLVMGetUndef(ctx->i32);
4552
4553 if (count > 1)
4554 args->addr = ac_build_gather_values(ctx, param, count);
4555 else
4556 args->addr = param[0];
4557
4558 args->resource = res_ptr;
4559 args->sampler = samp_ptr;
4560
4561 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4562 args->addr = param[0];
4563 return;
4564 }
4565
4566 args->dmask = dmask;
4567 args->unorm = is_rect;
4568 args->da = da;
4569 }
4570
4571 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4572 *
4573 * SI-CI:
4574 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4575 * filtering manually. The driver sets img7 to a mask clearing
4576 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4577 * s_and_b32 samp0, samp0, img7
4578 *
4579 * VI:
4580 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4581 */
4582 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4583 LLVMValueRef res, LLVMValueRef samp)
4584 {
4585 LLVMBuilderRef builder = ctx->ac.builder;
4586 LLVMValueRef img7, samp0;
4587
4588 if (ctx->ac.chip_class >= VI)
4589 return samp;
4590
4591 img7 = LLVMBuildExtractElement(builder, res,
4592 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4593 samp0 = LLVMBuildExtractElement(builder, samp,
4594 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4595 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4596 return LLVMBuildInsertElement(builder, samp, samp0,
4597 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4598 }
4599
4600 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4601 nir_tex_instr *instr,
4602 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4603 LLVMValueRef *fmask_ptr)
4604 {
4605 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4606 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4607 else
4608 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4609 if (samp_ptr) {
4610 if (instr->sampler)
4611 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4612 else
4613 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4614 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4615 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4616 }
4617 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4618 instr->op == nir_texop_samples_identical))
4619 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4620 }
4621
4622 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4623 LLVMValueRef coord)
4624 {
4625 coord = ac_to_float(ctx, coord);
4626 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4627 coord = ac_to_integer(ctx, coord);
4628 return coord;
4629 }
4630
4631 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4632 {
4633 LLVMValueRef result = NULL;
4634 struct ac_image_args args = { 0 };
4635 unsigned dmask = 0xf;
4636 LLVMValueRef address[16];
4637 LLVMValueRef coords[5];
4638 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4639 LLVMValueRef bias = NULL, offsets = NULL;
4640 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4641 LLVMValueRef ddx = NULL, ddy = NULL;
4642 LLVMValueRef derivs[6];
4643 unsigned chan, count = 0;
4644 unsigned const_src = 0, num_deriv_comp = 0;
4645 bool lod_is_zero = false;
4646
4647 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4648
4649 for (unsigned i = 0; i < instr->num_srcs; i++) {
4650 switch (instr->src[i].src_type) {
4651 case nir_tex_src_coord:
4652 coord = get_src(ctx, instr->src[i].src);
4653 break;
4654 case nir_tex_src_projector:
4655 break;
4656 case nir_tex_src_comparator:
4657 comparator = get_src(ctx, instr->src[i].src);
4658 break;
4659 case nir_tex_src_offset:
4660 offsets = get_src(ctx, instr->src[i].src);
4661 const_src = i;
4662 break;
4663 case nir_tex_src_bias:
4664 bias = get_src(ctx, instr->src[i].src);
4665 break;
4666 case nir_tex_src_lod: {
4667 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4668
4669 if (val && val->i32[0] == 0)
4670 lod_is_zero = true;
4671 lod = get_src(ctx, instr->src[i].src);
4672 break;
4673 }
4674 case nir_tex_src_ms_index:
4675 sample_index = get_src(ctx, instr->src[i].src);
4676 break;
4677 case nir_tex_src_ms_mcs:
4678 break;
4679 case nir_tex_src_ddx:
4680 ddx = get_src(ctx, instr->src[i].src);
4681 num_deriv_comp = instr->src[i].src.ssa->num_components;
4682 break;
4683 case nir_tex_src_ddy:
4684 ddy = get_src(ctx, instr->src[i].src);
4685 break;
4686 case nir_tex_src_texture_offset:
4687 case nir_tex_src_sampler_offset:
4688 case nir_tex_src_plane:
4689 default:
4690 break;
4691 }
4692 }
4693
4694 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4695 result = get_buffer_size(ctx, res_ptr, true);
4696 goto write_result;
4697 }
4698
4699 if (instr->op == nir_texop_texture_samples) {
4700 LLVMValueRef res, samples, is_msaa;
4701 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4702 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4703 LLVMConstInt(ctx->ac.i32, 3, false), "");
4704 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4705 LLVMConstInt(ctx->ac.i32, 28, false), "");
4706 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4707 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4708 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4709 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4710
4711 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4712 LLVMConstInt(ctx->ac.i32, 16, false), "");
4713 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4714 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4715 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4716 samples, "");
4717 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4718 ctx->ac.i32_1, "");
4719 result = samples;
4720 goto write_result;
4721 }
4722
4723 if (coord)
4724 for (chan = 0; chan < instr->coord_components; chan++)
4725 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4726
4727 if (offsets && instr->op != nir_texop_txf) {
4728 LLVMValueRef offset[3], pack;
4729 for (chan = 0; chan < 3; ++chan)
4730 offset[chan] = ctx->ac.i32_0;
4731
4732 args.offset = true;
4733 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4734 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4735 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4736 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4737 if (chan)
4738 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4739 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4740 }
4741 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4742 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4743 address[count++] = pack;
4744
4745 }
4746 /* pack LOD bias value */
4747 if (instr->op == nir_texop_txb && bias) {
4748 address[count++] = bias;
4749 }
4750
4751 /* Pack depth comparison value */
4752 if (instr->is_shadow && comparator) {
4753 LLVMValueRef z = ac_to_float(&ctx->ac,
4754 llvm_extract_elem(&ctx->ac, comparator, 0));
4755
4756 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4757 * so the depth comparison value isn't clamped for Z16 and
4758 * Z24 anymore. Do it manually here.
4759 *
4760 * It's unnecessary if the original texture format was
4761 * Z32_FLOAT, but we don't know that here.
4762 */
4763 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4764 z = ac_build_clamp(&ctx->ac, z);
4765
4766 address[count++] = z;
4767 }
4768
4769 /* pack derivatives */
4770 if (ddx || ddy) {
4771 int num_src_deriv_channels, num_dest_deriv_channels;
4772 switch (instr->sampler_dim) {
4773 case GLSL_SAMPLER_DIM_3D:
4774 case GLSL_SAMPLER_DIM_CUBE:
4775 num_deriv_comp = 3;
4776 num_src_deriv_channels = 3;
4777 num_dest_deriv_channels = 3;
4778 break;
4779 case GLSL_SAMPLER_DIM_2D:
4780 default:
4781 num_src_deriv_channels = 2;
4782 num_dest_deriv_channels = 2;
4783 num_deriv_comp = 2;
4784 break;
4785 case GLSL_SAMPLER_DIM_1D:
4786 num_src_deriv_channels = 1;
4787 if (ctx->ac.chip_class >= GFX9) {
4788 num_dest_deriv_channels = 2;
4789 num_deriv_comp = 2;
4790 } else {
4791 num_dest_deriv_channels = 1;
4792 num_deriv_comp = 1;
4793 }
4794 break;
4795 }
4796
4797 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4798 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4799 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4800 }
4801 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4802 derivs[i] = ctx->ac.f32_0;
4803 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4804 }
4805 }
4806
4807 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4808 for (chan = 0; chan < instr->coord_components; chan++)
4809 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4810 if (instr->coord_components == 3)
4811 coords[3] = LLVMGetUndef(ctx->ac.f32);
4812 ac_prepare_cube_coords(&ctx->ac,
4813 instr->op == nir_texop_txd, instr->is_array,
4814 instr->op == nir_texop_lod, coords, derivs);
4815 if (num_deriv_comp)
4816 num_deriv_comp--;
4817 }
4818
4819 if (ddx || ddy) {
4820 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4821 address[count++] = derivs[i];
4822 }
4823
4824 /* Pack texture coordinates */
4825 if (coord) {
4826 address[count++] = coords[0];
4827 if (instr->coord_components > 1) {
4828 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4829 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4830 }
4831 address[count++] = coords[1];
4832 }
4833 if (instr->coord_components > 2) {
4834 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4835 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4836 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4837 instr->op != nir_texop_txf) {
4838 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4839 }
4840 address[count++] = coords[2];
4841 }
4842
4843 if (ctx->ac.chip_class >= GFX9) {
4844 LLVMValueRef filler;
4845 if (instr->op == nir_texop_txf)
4846 filler = ctx->ac.i32_0;
4847 else
4848 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4849
4850 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4851 /* No nir_texop_lod, because it does not take a slice
4852 * even with array textures. */
4853 if (instr->is_array && instr->op != nir_texop_lod ) {
4854 address[count] = address[count - 1];
4855 address[count - 1] = filler;
4856 count++;
4857 } else
4858 address[count++] = filler;
4859 }
4860 }
4861 }
4862
4863 /* Pack LOD */
4864 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4865 instr->op == nir_texop_txf)) {
4866 address[count++] = lod;
4867 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4868 address[count++] = sample_index;
4869 } else if(instr->op == nir_texop_txs) {
4870 count = 0;
4871 if (lod)
4872 address[count++] = lod;
4873 else
4874 address[count++] = ctx->ac.i32_0;
4875 }
4876
4877 for (chan = 0; chan < count; chan++) {
4878 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4879 address[chan], ctx->ac.i32, "");
4880 }
4881
4882 if (instr->op == nir_texop_samples_identical) {
4883 LLVMValueRef txf_address[4];
4884 struct ac_image_args txf_args = { 0 };
4885 unsigned txf_count = count;
4886 memcpy(txf_address, address, sizeof(txf_address));
4887
4888 if (!instr->is_array)
4889 txf_address[2] = ctx->ac.i32_0;
4890 txf_address[3] = ctx->ac.i32_0;
4891
4892 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4893 fmask_ptr, NULL,
4894 txf_address, txf_count, 0xf);
4895
4896 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4897
4898 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4899 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4900 goto write_result;
4901 }
4902
4903 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4904 instr->op != nir_texop_txs) {
4905 unsigned sample_chan = instr->is_array ? 3 : 2;
4906 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4907 address[0],
4908 address[1],
4909 instr->is_array ? address[2] : NULL,
4910 address[sample_chan],
4911 fmask_ptr);
4912 }
4913
4914 if (offsets && instr->op == nir_texop_txf) {
4915 nir_const_value *const_offset =
4916 nir_src_as_const_value(instr->src[const_src].src);
4917 int num_offsets = instr->src[const_src].src.ssa->num_components;
4918 assert(const_offset);
4919 num_offsets = MIN2(num_offsets, instr->coord_components);
4920 if (num_offsets > 2)
4921 address[2] = LLVMBuildAdd(ctx->ac.builder,
4922 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4923 if (num_offsets > 1)
4924 address[1] = LLVMBuildAdd(ctx->ac.builder,
4925 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4926 address[0] = LLVMBuildAdd(ctx->ac.builder,
4927 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4928
4929 }
4930
4931 /* TODO TG4 support */
4932 if (instr->op == nir_texop_tg4) {
4933 if (instr->is_shadow)
4934 dmask = 1;
4935 else
4936 dmask = 1 << instr->component;
4937 }
4938 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4939 res_ptr, samp_ptr, address, count, dmask);
4940
4941 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4942
4943 if (instr->op == nir_texop_query_levels)
4944 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4945 else if (instr->is_shadow && instr->is_new_style_shadow &&
4946 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4947 instr->op != nir_texop_tg4)
4948 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4949 else if (instr->op == nir_texop_txs &&
4950 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4951 instr->is_array) {
4952 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4953 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4954 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4955 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4956 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4957 } else if (ctx->ac.chip_class >= GFX9 &&
4958 instr->op == nir_texop_txs &&
4959 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4960 instr->is_array) {
4961 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4962 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4963 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4964 ctx->ac.i32_1, "");
4965 } else if (instr->dest.ssa.num_components != 4)
4966 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4967
4968 write_result:
4969 if (result) {
4970 assert(instr->dest.is_ssa);
4971 result = ac_to_integer(&ctx->ac, result);
4972 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4973 }
4974 }
4975
4976
4977 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4978 {
4979 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4980 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4981
4982 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4983 _mesa_hash_table_insert(ctx->phis, instr, result);
4984 }
4985
4986 static void visit_post_phi(struct ac_nir_context *ctx,
4987 nir_phi_instr *instr,
4988 LLVMValueRef llvm_phi)
4989 {
4990 nir_foreach_phi_src(src, instr) {
4991 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4992 LLVMValueRef llvm_src = get_src(ctx, src->src);
4993
4994 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4995 }
4996 }
4997
4998 static void phi_post_pass(struct ac_nir_context *ctx)
4999 {
5000 struct hash_entry *entry;
5001 hash_table_foreach(ctx->phis, entry) {
5002 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5003 (LLVMValueRef)entry->data);
5004 }
5005 }
5006
5007
5008 static void visit_ssa_undef(struct ac_nir_context *ctx,
5009 const nir_ssa_undef_instr *instr)
5010 {
5011 unsigned num_components = instr->def.num_components;
5012 LLVMValueRef undef;
5013
5014 if (num_components == 1)
5015 undef = LLVMGetUndef(ctx->ac.i32);
5016 else {
5017 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5018 }
5019 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5020 }
5021
5022 static void visit_jump(struct ac_nir_context *ctx,
5023 const nir_jump_instr *instr)
5024 {
5025 switch (instr->type) {
5026 case nir_jump_break:
5027 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5028 LLVMClearInsertionPosition(ctx->ac.builder);
5029 break;
5030 case nir_jump_continue:
5031 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5032 LLVMClearInsertionPosition(ctx->ac.builder);
5033 break;
5034 default:
5035 fprintf(stderr, "Unknown NIR jump instr: ");
5036 nir_print_instr(&instr->instr, stderr);
5037 fprintf(stderr, "\n");
5038 abort();
5039 }
5040 }
5041
5042 static void visit_cf_list(struct ac_nir_context *ctx,
5043 struct exec_list *list);
5044
5045 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5046 {
5047 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5048 nir_foreach_instr(instr, block)
5049 {
5050 switch (instr->type) {
5051 case nir_instr_type_alu:
5052 visit_alu(ctx, nir_instr_as_alu(instr));
5053 break;
5054 case nir_instr_type_load_const:
5055 visit_load_const(ctx, nir_instr_as_load_const(instr));
5056 break;
5057 case nir_instr_type_intrinsic:
5058 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5059 break;
5060 case nir_instr_type_tex:
5061 visit_tex(ctx, nir_instr_as_tex(instr));
5062 break;
5063 case nir_instr_type_phi:
5064 visit_phi(ctx, nir_instr_as_phi(instr));
5065 break;
5066 case nir_instr_type_ssa_undef:
5067 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5068 break;
5069 case nir_instr_type_jump:
5070 visit_jump(ctx, nir_instr_as_jump(instr));
5071 break;
5072 default:
5073 fprintf(stderr, "Unknown NIR instr type: ");
5074 nir_print_instr(instr, stderr);
5075 fprintf(stderr, "\n");
5076 abort();
5077 }
5078 }
5079
5080 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5081 }
5082
5083 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5084 {
5085 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5086
5087 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5088 LLVMBasicBlockRef merge_block =
5089 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5090 LLVMBasicBlockRef if_block =
5091 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5092 LLVMBasicBlockRef else_block = merge_block;
5093 if (!exec_list_is_empty(&if_stmt->else_list))
5094 else_block = LLVMAppendBasicBlockInContext(
5095 ctx->ac.context, fn, "");
5096
5097 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5098 ctx->ac.i32_0, "");
5099 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5100
5101 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5102 visit_cf_list(ctx, &if_stmt->then_list);
5103 if (LLVMGetInsertBlock(ctx->ac.builder))
5104 LLVMBuildBr(ctx->ac.builder, merge_block);
5105
5106 if (!exec_list_is_empty(&if_stmt->else_list)) {
5107 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5108 visit_cf_list(ctx, &if_stmt->else_list);
5109 if (LLVMGetInsertBlock(ctx->ac.builder))
5110 LLVMBuildBr(ctx->ac.builder, merge_block);
5111 }
5112
5113 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5114 }
5115
5116 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5117 {
5118 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5119 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5120 LLVMBasicBlockRef break_parent = ctx->break_block;
5121
5122 ctx->continue_block =
5123 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5124 ctx->break_block =
5125 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5126
5127 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5128 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5129 visit_cf_list(ctx, &loop->body);
5130
5131 if (LLVMGetInsertBlock(ctx->ac.builder))
5132 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5133 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5134
5135 ctx->continue_block = continue_parent;
5136 ctx->break_block = break_parent;
5137 }
5138
5139 static void visit_cf_list(struct ac_nir_context *ctx,
5140 struct exec_list *list)
5141 {
5142 foreach_list_typed(nir_cf_node, node, node, list)
5143 {
5144 switch (node->type) {
5145 case nir_cf_node_block:
5146 visit_block(ctx, nir_cf_node_as_block(node));
5147 break;
5148
5149 case nir_cf_node_if:
5150 visit_if(ctx, nir_cf_node_as_if(node));
5151 break;
5152
5153 case nir_cf_node_loop:
5154 visit_loop(ctx, nir_cf_node_as_loop(node));
5155 break;
5156
5157 default:
5158 assert(0);
5159 }
5160 }
5161 }
5162
5163 static void
5164 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5165 struct nir_variable *variable)
5166 {
5167 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5168 LLVMValueRef t_offset;
5169 LLVMValueRef t_list;
5170 LLVMValueRef input;
5171 LLVMValueRef buffer_index;
5172 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5173 int idx = variable->data.location;
5174 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5175
5176 variable->data.driver_location = idx * 4;
5177
5178 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5179 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5180 ctx->abi.start_instance, "");
5181 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5182 ctx->shader_info->vs.vgpr_comp_cnt);
5183 } else
5184 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5185 ctx->abi.base_vertex, "");
5186
5187 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5188 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5189
5190 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5191
5192 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5193 buffer_index,
5194 ctx->ac.i32_0,
5195 true);
5196
5197 for (unsigned chan = 0; chan < 4; chan++) {
5198 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5199 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5200 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5201 input, llvm_chan, ""));
5202 }
5203 }
5204 }
5205
5206 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5207 unsigned attr,
5208 LLVMValueRef interp_param,
5209 LLVMValueRef prim_mask,
5210 LLVMValueRef result[4])
5211 {
5212 LLVMValueRef attr_number;
5213 unsigned chan;
5214 LLVMValueRef i, j;
5215 bool interp = interp_param != NULL;
5216
5217 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5218
5219 /* fs.constant returns the param from the middle vertex, so it's not
5220 * really useful for flat shading. It's meant to be used for custom
5221 * interpolation (but the intrinsic can't fetch from the other two
5222 * vertices).
5223 *
5224 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5225 * to do the right thing. The only reason we use fs.constant is that
5226 * fs.interp cannot be used on integers, because they can be equal
5227 * to NaN.
5228 */
5229 if (interp) {
5230 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5231 ctx->ac.v2f32, "");
5232
5233 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5234 ctx->ac.i32_0, "");
5235 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5236 ctx->ac.i32_1, "");
5237 }
5238
5239 for (chan = 0; chan < 4; chan++) {
5240 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5241
5242 if (interp) {
5243 result[chan] = ac_build_fs_interp(&ctx->ac,
5244 llvm_chan,
5245 attr_number,
5246 prim_mask, i, j);
5247 } else {
5248 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5249 LLVMConstInt(ctx->ac.i32, 2, false),
5250 llvm_chan,
5251 attr_number,
5252 prim_mask);
5253 }
5254 }
5255 }
5256
5257 static void
5258 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5259 struct nir_variable *variable)
5260 {
5261 int idx = variable->data.location;
5262 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5263 LLVMValueRef interp;
5264
5265 variable->data.driver_location = idx * 4;
5266 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5267
5268 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5269 unsigned interp_type;
5270 if (variable->data.sample) {
5271 interp_type = INTERP_SAMPLE;
5272 ctx->shader_info->info.ps.force_persample = true;
5273 } else if (variable->data.centroid)
5274 interp_type = INTERP_CENTROID;
5275 else
5276 interp_type = INTERP_CENTER;
5277
5278 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5279 } else
5280 interp = NULL;
5281
5282 for (unsigned i = 0; i < attrib_count; ++i)
5283 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5284
5285 }
5286
5287 static void
5288 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5289 struct nir_shader *nir) {
5290 nir_foreach_variable(variable, &nir->inputs)
5291 handle_vs_input_decl(ctx, variable);
5292 }
5293
5294 static void
5295 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5296 struct nir_shader *nir)
5297 {
5298 if (!ctx->options->key.fs.multisample)
5299 return;
5300
5301 bool uses_center = false;
5302 bool uses_centroid = false;
5303 nir_foreach_variable(variable, &nir->inputs) {
5304 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5305 variable->data.sample)
5306 continue;
5307
5308 if (variable->data.centroid)
5309 uses_centroid = true;
5310 else
5311 uses_center = true;
5312 }
5313
5314 if (uses_center && uses_centroid) {
5315 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5316 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5317 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5318 }
5319 }
5320
5321 static void
5322 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5323 struct nir_shader *nir)
5324 {
5325 prepare_interp_optimize(ctx, nir);
5326
5327 nir_foreach_variable(variable, &nir->inputs)
5328 handle_fs_input_decl(ctx, variable);
5329
5330 unsigned index = 0;
5331
5332 if (ctx->shader_info->info.ps.uses_input_attachments ||
5333 ctx->shader_info->info.needs_multiview_view_index)
5334 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5335
5336 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5337 LLVMValueRef interp_param;
5338 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5339
5340 if (!(ctx->input_mask & (1ull << i)))
5341 continue;
5342
5343 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5344 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5345 interp_param = *inputs;
5346 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5347 inputs);
5348
5349 if (!interp_param)
5350 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5351 ++index;
5352 } else if (i == VARYING_SLOT_POS) {
5353 for(int i = 0; i < 3; ++i)
5354 inputs[i] = ctx->abi.frag_pos[i];
5355
5356 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5357 ctx->abi.frag_pos[3]);
5358 }
5359 }
5360 ctx->shader_info->fs.num_interp = index;
5361 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5362 ctx->shader_info->fs.has_pcoord = true;
5363 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5364 ctx->shader_info->fs.prim_id_input = true;
5365 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5366 ctx->shader_info->fs.layer_input = true;
5367 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5368
5369 if (ctx->shader_info->info.needs_multiview_view_index)
5370 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5371 }
5372
5373 static LLVMValueRef
5374 ac_build_alloca(struct ac_llvm_context *ac,
5375 LLVMTypeRef type,
5376 const char *name)
5377 {
5378 LLVMBuilderRef builder = ac->builder;
5379 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5380 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5381 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5382 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5383 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5384 LLVMValueRef res;
5385
5386 if (first_instr) {
5387 LLVMPositionBuilderBefore(first_builder, first_instr);
5388 } else {
5389 LLVMPositionBuilderAtEnd(first_builder, first_block);
5390 }
5391
5392 res = LLVMBuildAlloca(first_builder, type, name);
5393 LLVMBuildStore(builder, LLVMConstNull(type), res);
5394
5395 LLVMDisposeBuilder(first_builder);
5396
5397 return res;
5398 }
5399
5400 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5401 LLVMTypeRef type,
5402 const char *name)
5403 {
5404 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5405 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5406 return ptr;
5407 }
5408
5409 static void
5410 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5411 struct nir_variable *variable,
5412 struct nir_shader *shader,
5413 gl_shader_stage stage)
5414 {
5415 int idx = variable->data.location + variable->data.index;
5416 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5417 uint64_t mask_attribs;
5418
5419 variable->data.driver_location = idx * 4;
5420
5421 /* tess ctrl has it's own load/store paths for outputs */
5422 if (stage == MESA_SHADER_TESS_CTRL)
5423 return;
5424
5425 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5426 if (stage == MESA_SHADER_VERTEX ||
5427 stage == MESA_SHADER_TESS_EVAL ||
5428 stage == MESA_SHADER_GEOMETRY) {
5429 if (idx == VARYING_SLOT_CLIP_DIST0) {
5430 int length = shader->info.clip_distance_array_size +
5431 shader->info.cull_distance_array_size;
5432 if (stage == MESA_SHADER_VERTEX) {
5433 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5434 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5435 }
5436 if (stage == MESA_SHADER_TESS_EVAL) {
5437 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5438 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5439 }
5440
5441 if (length > 4)
5442 attrib_count = 2;
5443 else
5444 attrib_count = 1;
5445 mask_attribs = 1ull << idx;
5446 }
5447 }
5448
5449 ctx->output_mask |= mask_attribs;
5450 }
5451
5452 static void
5453 handle_shader_output_decl(struct ac_nir_context *ctx,
5454 struct nir_shader *nir,
5455 struct nir_variable *variable)
5456 {
5457 unsigned output_loc = variable->data.driver_location / 4;
5458 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5459
5460 /* tess ctrl has it's own load/store paths for outputs */
5461 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5462 return;
5463
5464 if (ctx->stage == MESA_SHADER_VERTEX ||
5465 ctx->stage == MESA_SHADER_TESS_EVAL ||
5466 ctx->stage == MESA_SHADER_GEOMETRY) {
5467 int idx = variable->data.location + variable->data.index;
5468 if (idx == VARYING_SLOT_CLIP_DIST0) {
5469 int length = nir->info.clip_distance_array_size +
5470 nir->info.cull_distance_array_size;
5471
5472 if (length > 4)
5473 attrib_count = 2;
5474 else
5475 attrib_count = 1;
5476 }
5477 }
5478
5479 for (unsigned i = 0; i < attrib_count; ++i) {
5480 for (unsigned chan = 0; chan < 4; chan++) {
5481 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5482 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5483 }
5484 }
5485 }
5486
5487 static LLVMTypeRef
5488 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5489 enum glsl_base_type type)
5490 {
5491 switch (type) {
5492 case GLSL_TYPE_INT:
5493 case GLSL_TYPE_UINT:
5494 case GLSL_TYPE_BOOL:
5495 case GLSL_TYPE_SUBROUTINE:
5496 return ctx->ac.i32;
5497 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5498 return ctx->ac.f32;
5499 case GLSL_TYPE_INT64:
5500 case GLSL_TYPE_UINT64:
5501 return ctx->ac.i64;
5502 case GLSL_TYPE_DOUBLE:
5503 return ctx->ac.f64;
5504 default:
5505 unreachable("unknown GLSL type");
5506 }
5507 }
5508
5509 static LLVMTypeRef
5510 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5511 const struct glsl_type *type)
5512 {
5513 if (glsl_type_is_scalar(type)) {
5514 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5515 }
5516
5517 if (glsl_type_is_vector(type)) {
5518 return LLVMVectorType(
5519 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5520 glsl_get_vector_elements(type));
5521 }
5522
5523 if (glsl_type_is_matrix(type)) {
5524 return LLVMArrayType(
5525 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5526 glsl_get_matrix_columns(type));
5527 }
5528
5529 if (glsl_type_is_array(type)) {
5530 return LLVMArrayType(
5531 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5532 glsl_get_length(type));
5533 }
5534
5535 assert(glsl_type_is_struct(type));
5536
5537 LLVMTypeRef member_types[glsl_get_length(type)];
5538
5539 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5540 member_types[i] =
5541 glsl_to_llvm_type(ctx,
5542 glsl_get_struct_field(type, i));
5543 }
5544
5545 return LLVMStructTypeInContext(ctx->context, member_types,
5546 glsl_get_length(type), false);
5547 }
5548
5549 static void
5550 setup_locals(struct ac_nir_context *ctx,
5551 struct nir_function *func)
5552 {
5553 int i, j;
5554 ctx->num_locals = 0;
5555 nir_foreach_variable(variable, &func->impl->locals) {
5556 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5557 variable->data.driver_location = ctx->num_locals * 4;
5558 ctx->num_locals += attrib_count;
5559 }
5560 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5561 if (!ctx->locals)
5562 return;
5563
5564 for (i = 0; i < ctx->num_locals; i++) {
5565 for (j = 0; j < 4; j++) {
5566 ctx->locals[i * 4 + j] =
5567 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5568 }
5569 }
5570 }
5571
5572 static void
5573 setup_shared(struct ac_nir_context *ctx,
5574 struct nir_shader *nir)
5575 {
5576 nir_foreach_variable(variable, &nir->shared) {
5577 LLVMValueRef shared =
5578 LLVMAddGlobalInAddressSpace(
5579 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5580 variable->name ? variable->name : "",
5581 LOCAL_ADDR_SPACE);
5582 _mesa_hash_table_insert(ctx->vars, variable, shared);
5583 }
5584 }
5585
5586 static LLVMValueRef
5587 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5588 {
5589 v = ac_to_float(ctx, v);
5590 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5591 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5592 }
5593
5594
5595 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5596 LLVMValueRef src0, LLVMValueRef src1)
5597 {
5598 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5599 LLVMValueRef comp[2];
5600
5601 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5602 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5603 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5604 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5605 }
5606
5607 /* Initialize arguments for the shader export intrinsic */
5608 static void
5609 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5610 LLVMValueRef *values,
5611 unsigned target,
5612 struct ac_export_args *args)
5613 {
5614 /* Default is 0xf. Adjusted below depending on the format. */
5615 args->enabled_channels = 0xf;
5616
5617 /* Specify whether the EXEC mask represents the valid mask */
5618 args->valid_mask = 0;
5619
5620 /* Specify whether this is the last export */
5621 args->done = 0;
5622
5623 /* Specify the target we are exporting */
5624 args->target = target;
5625
5626 args->compr = false;
5627 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5628 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5629 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5630 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5631
5632 if (!values)
5633 return;
5634
5635 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5636 LLVMValueRef val[4];
5637 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5638 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5639 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5640 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5641
5642 switch(col_format) {
5643 case V_028714_SPI_SHADER_ZERO:
5644 args->enabled_channels = 0; /* writemask */
5645 args->target = V_008DFC_SQ_EXP_NULL;
5646 break;
5647
5648 case V_028714_SPI_SHADER_32_R:
5649 args->enabled_channels = 1;
5650 args->out[0] = values[0];
5651 break;
5652
5653 case V_028714_SPI_SHADER_32_GR:
5654 args->enabled_channels = 0x3;
5655 args->out[0] = values[0];
5656 args->out[1] = values[1];
5657 break;
5658
5659 case V_028714_SPI_SHADER_32_AR:
5660 args->enabled_channels = 0x9;
5661 args->out[0] = values[0];
5662 args->out[3] = values[3];
5663 break;
5664
5665 case V_028714_SPI_SHADER_FP16_ABGR:
5666 args->compr = 1;
5667
5668 for (unsigned chan = 0; chan < 2; chan++) {
5669 LLVMValueRef pack_args[2] = {
5670 values[2 * chan],
5671 values[2 * chan + 1]
5672 };
5673 LLVMValueRef packed;
5674
5675 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5676 args->out[chan] = packed;
5677 }
5678 break;
5679
5680 case V_028714_SPI_SHADER_UNORM16_ABGR:
5681 for (unsigned chan = 0; chan < 4; chan++) {
5682 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5683 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5684 LLVMConstReal(ctx->ac.f32, 65535), "");
5685 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5686 LLVMConstReal(ctx->ac.f32, 0.5), "");
5687 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5688 ctx->ac.i32, "");
5689 }
5690
5691 args->compr = 1;
5692 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5693 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5694 break;
5695
5696 case V_028714_SPI_SHADER_SNORM16_ABGR:
5697 for (unsigned chan = 0; chan < 4; chan++) {
5698 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5699 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5700 LLVMConstReal(ctx->ac.f32, 32767), "");
5701
5702 /* If positive, add 0.5, else add -0.5. */
5703 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5704 LLVMBuildSelect(ctx->builder,
5705 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5706 val[chan], ctx->ac.f32_0, ""),
5707 LLVMConstReal(ctx->ac.f32, 0.5),
5708 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5709 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5710 }
5711
5712 args->compr = 1;
5713 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5714 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5715 break;
5716
5717 case V_028714_SPI_SHADER_UINT16_ABGR: {
5718 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5719 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5720 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5721
5722 for (unsigned chan = 0; chan < 4; chan++) {
5723 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5724 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5725 }
5726
5727 args->compr = 1;
5728 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5729 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5730 break;
5731 }
5732
5733 case V_028714_SPI_SHADER_SINT16_ABGR: {
5734 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5735 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5736 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5737 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5738 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5739 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5740
5741 /* Clamp. */
5742 for (unsigned chan = 0; chan < 4; chan++) {
5743 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5744 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5745 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5746 }
5747
5748 args->compr = 1;
5749 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5750 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5751 break;
5752 }
5753
5754 default:
5755 case V_028714_SPI_SHADER_32_ABGR:
5756 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5757 break;
5758 }
5759 } else
5760 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5761
5762 for (unsigned i = 0; i < 4; ++i)
5763 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5764 }
5765
5766 static void
5767 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5768 bool export_prim_id,
5769 struct ac_vs_output_info *outinfo)
5770 {
5771 uint32_t param_count = 0;
5772 unsigned target;
5773 unsigned pos_idx, num_pos_exports = 0;
5774 struct ac_export_args args, pos_args[4] = {};
5775 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5776 int i;
5777
5778 if (ctx->options->key.has_multiview_view_index) {
5779 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5780 if(!*tmp_out) {
5781 for(unsigned i = 0; i < 4; ++i)
5782 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5783 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5784 }
5785
5786 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5787 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5788 }
5789
5790 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5791 sizeof(outinfo->vs_output_param_offset));
5792
5793 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5794 LLVMValueRef slots[8];
5795 unsigned j;
5796
5797 if (outinfo->cull_dist_mask)
5798 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5799
5800 i = VARYING_SLOT_CLIP_DIST0;
5801 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5802 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5803 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5804
5805 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5806 slots[i] = LLVMGetUndef(ctx->ac.f32);
5807
5808 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5809 target = V_008DFC_SQ_EXP_POS + 3;
5810 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5811 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5812 &args, sizeof(args));
5813 }
5814
5815 target = V_008DFC_SQ_EXP_POS + 2;
5816 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5817 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5818 &args, sizeof(args));
5819
5820 }
5821
5822 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5823 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5824 for (unsigned j = 0; j < 4; j++)
5825 pos_values[j] = LLVMBuildLoad(ctx->builder,
5826 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5827 }
5828 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5829
5830 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5831 outinfo->writes_pointsize = true;
5832 psize_value = LLVMBuildLoad(ctx->builder,
5833 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5834 }
5835
5836 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5837 outinfo->writes_layer = true;
5838 layer_value = LLVMBuildLoad(ctx->builder,
5839 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5840 }
5841
5842 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5843 outinfo->writes_viewport_index = true;
5844 viewport_index_value = LLVMBuildLoad(ctx->builder,
5845 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5846 }
5847
5848 if (outinfo->writes_pointsize ||
5849 outinfo->writes_layer ||
5850 outinfo->writes_viewport_index) {
5851 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5852 (outinfo->writes_layer == true ? 4 : 0));
5853 pos_args[1].valid_mask = 0;
5854 pos_args[1].done = 0;
5855 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5856 pos_args[1].compr = 0;
5857 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5858 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5859 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5860 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5861
5862 if (outinfo->writes_pointsize == true)
5863 pos_args[1].out[0] = psize_value;
5864 if (outinfo->writes_layer == true)
5865 pos_args[1].out[2] = layer_value;
5866 if (outinfo->writes_viewport_index == true) {
5867 if (ctx->options->chip_class >= GFX9) {
5868 /* GFX9 has the layer in out.z[10:0] and the viewport
5869 * index in out.z[19:16].
5870 */
5871 LLVMValueRef v = viewport_index_value;
5872 v = ac_to_integer(&ctx->ac, v);
5873 v = LLVMBuildShl(ctx->builder, v,
5874 LLVMConstInt(ctx->ac.i32, 16, false),
5875 "");
5876 v = LLVMBuildOr(ctx->builder, v,
5877 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5878
5879 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5880 pos_args[1].enabled_channels |= 1 << 2;
5881 } else {
5882 pos_args[1].out[3] = viewport_index_value;
5883 pos_args[1].enabled_channels |= 1 << 3;
5884 }
5885 }
5886 }
5887 for (i = 0; i < 4; i++) {
5888 if (pos_args[i].out[0])
5889 num_pos_exports++;
5890 }
5891
5892 pos_idx = 0;
5893 for (i = 0; i < 4; i++) {
5894 if (!pos_args[i].out[0])
5895 continue;
5896
5897 /* Specify the target we are exporting */
5898 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5899 if (pos_idx == num_pos_exports)
5900 pos_args[i].done = 1;
5901 ac_build_export(&ctx->ac, &pos_args[i]);
5902 }
5903
5904 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5905 LLVMValueRef values[4];
5906 if (!(ctx->output_mask & (1ull << i)))
5907 continue;
5908
5909 for (unsigned j = 0; j < 4; j++)
5910 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5911 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5912
5913 if (i == VARYING_SLOT_LAYER) {
5914 target = V_008DFC_SQ_EXP_PARAM + param_count;
5915 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5916 param_count++;
5917 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5918 target = V_008DFC_SQ_EXP_PARAM + param_count;
5919 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5920 param_count++;
5921 } else if (i >= VARYING_SLOT_VAR0) {
5922 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5923 target = V_008DFC_SQ_EXP_PARAM + param_count;
5924 outinfo->vs_output_param_offset[i] = param_count;
5925 param_count++;
5926 } else
5927 continue;
5928
5929 si_llvm_init_export_args(ctx, values, target, &args);
5930
5931 if (target >= V_008DFC_SQ_EXP_POS &&
5932 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5933 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5934 &args, sizeof(args));
5935 } else {
5936 ac_build_export(&ctx->ac, &args);
5937 }
5938 }
5939
5940 if (export_prim_id) {
5941 LLVMValueRef values[4];
5942 target = V_008DFC_SQ_EXP_PARAM + param_count;
5943 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5944 param_count++;
5945
5946 values[0] = ctx->vs_prim_id;
5947 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5948 ctx->shader_info->vs.vgpr_comp_cnt);
5949 for (unsigned j = 1; j < 4; j++)
5950 values[j] = ctx->ac.f32_0;
5951 si_llvm_init_export_args(ctx, values, target, &args);
5952 ac_build_export(&ctx->ac, &args);
5953 outinfo->export_prim_id = true;
5954 }
5955
5956 outinfo->pos_exports = num_pos_exports;
5957 outinfo->param_exports = param_count;
5958 }
5959
5960 static void
5961 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5962 struct ac_es_output_info *outinfo)
5963 {
5964 int j;
5965 uint64_t max_output_written = 0;
5966 LLVMValueRef lds_base = NULL;
5967
5968 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5969 int param_index;
5970 int length = 4;
5971
5972 if (!(ctx->output_mask & (1ull << i)))
5973 continue;
5974
5975 if (i == VARYING_SLOT_CLIP_DIST0)
5976 length = ctx->num_output_clips + ctx->num_output_culls;
5977
5978 param_index = shader_io_get_unique_index(i);
5979
5980 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5981 }
5982
5983 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5984
5985 if (ctx->ac.chip_class >= GFX9) {
5986 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5987 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5988 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5989 LLVMConstInt(ctx->ac.i32, 24, false),
5990 LLVMConstInt(ctx->ac.i32, 4, false), false);
5991 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5992 LLVMBuildMul(ctx->ac.builder, wave_idx,
5993 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5994 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5995 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5996 }
5997
5998 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5999 LLVMValueRef dw_addr;
6000 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6001 int param_index;
6002 int length = 4;
6003
6004 if (!(ctx->output_mask & (1ull << i)))
6005 continue;
6006
6007 if (i == VARYING_SLOT_CLIP_DIST0)
6008 length = ctx->num_output_clips + ctx->num_output_culls;
6009
6010 param_index = shader_io_get_unique_index(i);
6011
6012 if (lds_base) {
6013 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6014 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6015 "");
6016 }
6017 for (j = 0; j < length; j++) {
6018 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6019 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6020
6021 if (ctx->ac.chip_class >= GFX9) {
6022 ac_lds_store(&ctx->ac, dw_addr,
6023 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6024 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6025 } else {
6026 ac_build_buffer_store_dword(&ctx->ac,
6027 ctx->esgs_ring,
6028 out_val, 1,
6029 NULL, ctx->es2gs_offset,
6030 (4 * param_index + j) * 4,
6031 1, 1, true, true);
6032 }
6033 }
6034 }
6035 }
6036
6037 static void
6038 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6039 {
6040 LLVMValueRef vertex_id = ctx->rel_auto_id;
6041 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6042 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6043 vertex_dw_stride, "");
6044
6045 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6046 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6047 int length = 4;
6048
6049 if (!(ctx->output_mask & (1ull << i)))
6050 continue;
6051
6052 if (i == VARYING_SLOT_CLIP_DIST0)
6053 length = ctx->num_output_clips + ctx->num_output_culls;
6054 int param = shader_io_get_unique_index(i);
6055 mark_tess_output(ctx, false, param);
6056 if (length > 4)
6057 mark_tess_output(ctx, false, param + 1);
6058 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6059 LLVMConstInt(ctx->ac.i32, param * 4, false),
6060 "");
6061 for (unsigned j = 0; j < length; j++) {
6062 ac_lds_store(&ctx->ac, dw_addr,
6063 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6064 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6065 }
6066 }
6067 }
6068
6069 struct ac_build_if_state
6070 {
6071 struct nir_to_llvm_context *ctx;
6072 LLVMValueRef condition;
6073 LLVMBasicBlockRef entry_block;
6074 LLVMBasicBlockRef true_block;
6075 LLVMBasicBlockRef false_block;
6076 LLVMBasicBlockRef merge_block;
6077 };
6078
6079 static LLVMBasicBlockRef
6080 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6081 {
6082 LLVMBasicBlockRef current_block;
6083 LLVMBasicBlockRef next_block;
6084 LLVMBasicBlockRef new_block;
6085
6086 /* get current basic block */
6087 current_block = LLVMGetInsertBlock(ctx->builder);
6088
6089 /* chqeck if there's another block after this one */
6090 next_block = LLVMGetNextBasicBlock(current_block);
6091 if (next_block) {
6092 /* insert the new block before the next block */
6093 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6094 }
6095 else {
6096 /* append new block after current block */
6097 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6098 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6099 }
6100 return new_block;
6101 }
6102
6103 static void
6104 ac_nir_build_if(struct ac_build_if_state *ifthen,
6105 struct nir_to_llvm_context *ctx,
6106 LLVMValueRef condition)
6107 {
6108 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6109
6110 memset(ifthen, 0, sizeof *ifthen);
6111 ifthen->ctx = ctx;
6112 ifthen->condition = condition;
6113 ifthen->entry_block = block;
6114
6115 /* create endif/merge basic block for the phi functions */
6116 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6117
6118 /* create/insert true_block before merge_block */
6119 ifthen->true_block =
6120 LLVMInsertBasicBlockInContext(ctx->context,
6121 ifthen->merge_block,
6122 "if-true-block");
6123
6124 /* successive code goes into the true block */
6125 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6126 }
6127
6128 /**
6129 * End a conditional.
6130 */
6131 static void
6132 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6133 {
6134 LLVMBuilderRef builder = ifthen->ctx->builder;
6135
6136 /* Insert branch to the merge block from current block */
6137 LLVMBuildBr(builder, ifthen->merge_block);
6138
6139 /*
6140 * Now patch in the various branch instructions.
6141 */
6142
6143 /* Insert the conditional branch instruction at the end of entry_block */
6144 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6145 if (ifthen->false_block) {
6146 /* we have an else clause */
6147 LLVMBuildCondBr(builder, ifthen->condition,
6148 ifthen->true_block, ifthen->false_block);
6149 }
6150 else {
6151 /* no else clause */
6152 LLVMBuildCondBr(builder, ifthen->condition,
6153 ifthen->true_block, ifthen->merge_block);
6154 }
6155
6156 /* Resume building code at end of the ifthen->merge_block */
6157 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6158 }
6159
6160 static void
6161 write_tess_factors(struct nir_to_llvm_context *ctx)
6162 {
6163 unsigned stride, outer_comps, inner_comps;
6164 struct ac_build_if_state if_ctx, inner_if_ctx;
6165 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6166 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6167 unsigned tess_inner_index, tess_outer_index;
6168 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6169 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6170 int i;
6171 emit_barrier(ctx);
6172
6173 switch (ctx->options->key.tcs.primitive_mode) {
6174 case GL_ISOLINES:
6175 stride = 2;
6176 outer_comps = 2;
6177 inner_comps = 0;
6178 break;
6179 case GL_TRIANGLES:
6180 stride = 4;
6181 outer_comps = 3;
6182 inner_comps = 1;
6183 break;
6184 case GL_QUADS:
6185 stride = 6;
6186 outer_comps = 4;
6187 inner_comps = 2;
6188 break;
6189 default:
6190 return;
6191 }
6192
6193 ac_nir_build_if(&if_ctx, ctx,
6194 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6195 invocation_id, ctx->ac.i32_0, ""));
6196
6197 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6198 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6199
6200 mark_tess_output(ctx, true, tess_inner_index);
6201 mark_tess_output(ctx, true, tess_outer_index);
6202 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6203 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6204 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6205 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6206 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6207
6208 for (i = 0; i < 4; i++) {
6209 inner[i] = LLVMGetUndef(ctx->ac.i32);
6210 outer[i] = LLVMGetUndef(ctx->ac.i32);
6211 }
6212
6213 // LINES reverseal
6214 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6215 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6216 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6217 ctx->ac.i32_1, "");
6218 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6219 } else {
6220 for (i = 0; i < outer_comps; i++) {
6221 outer[i] = out[i] =
6222 ac_lds_load(&ctx->ac, lds_outer);
6223 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6224 ctx->ac.i32_1, "");
6225 }
6226 for (i = 0; i < inner_comps; i++) {
6227 inner[i] = out[outer_comps+i] =
6228 ac_lds_load(&ctx->ac, lds_inner);
6229 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6230 ctx->ac.i32_1, "");
6231 }
6232 }
6233
6234 /* Convert the outputs to vectors for stores. */
6235 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6236 vec1 = NULL;
6237
6238 if (stride > 4)
6239 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6240
6241
6242 buffer = ctx->hs_ring_tess_factor;
6243 tf_base = ctx->tess_factor_offset;
6244 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6245 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6246 unsigned tf_offset = 0;
6247
6248 if (ctx->options->chip_class <= VI) {
6249 ac_nir_build_if(&inner_if_ctx, ctx,
6250 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6251 rel_patch_id, ctx->ac.i32_0, ""));
6252
6253 /* Store the dynamic HS control word. */
6254 ac_build_buffer_store_dword(&ctx->ac, buffer,
6255 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6256 1, ctx->ac.i32_0, tf_base,
6257 0, 1, 0, true, false);
6258 tf_offset += 4;
6259
6260 ac_nir_build_endif(&inner_if_ctx);
6261 }
6262
6263 /* Store the tessellation factors. */
6264 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6265 MIN2(stride, 4), byteoffset, tf_base,
6266 tf_offset, 1, 0, true, false);
6267 if (vec1)
6268 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6269 stride - 4, byteoffset, tf_base,
6270 16 + tf_offset, 1, 0, true, false);
6271
6272 //store to offchip for TES to read - only if TES reads them
6273 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6274 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6275 LLVMValueRef tf_inner_offset;
6276 unsigned param_outer, param_inner;
6277
6278 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6279 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6280 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6281
6282 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6283 util_next_power_of_two(outer_comps));
6284
6285 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6286 outer_comps, tf_outer_offset,
6287 ctx->oc_lds, 0, 1, 0, true, false);
6288 if (inner_comps) {
6289 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6290 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6291 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6292
6293 inner_vec = inner_comps == 1 ? inner[0] :
6294 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6295 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6296 inner_comps, tf_inner_offset,
6297 ctx->oc_lds, 0, 1, 0, true, false);
6298 }
6299 }
6300 ac_nir_build_endif(&if_ctx);
6301 }
6302
6303 static void
6304 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6305 {
6306 write_tess_factors(ctx);
6307 }
6308
6309 static bool
6310 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6311 LLVMValueRef *color, unsigned param, bool is_last,
6312 struct ac_export_args *args)
6313 {
6314 /* Export */
6315 si_llvm_init_export_args(ctx, color, param,
6316 args);
6317
6318 if (is_last) {
6319 args->valid_mask = 1; /* whether the EXEC mask is valid */
6320 args->done = 1; /* DONE bit */
6321 } else if (!args->enabled_channels)
6322 return false; /* unnecessary NULL export */
6323
6324 return true;
6325 }
6326
6327 static void
6328 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6329 LLVMValueRef depth, LLVMValueRef stencil,
6330 LLVMValueRef samplemask)
6331 {
6332 struct ac_export_args args;
6333
6334 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6335
6336 ac_build_export(&ctx->ac, &args);
6337 }
6338
6339 static void
6340 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6341 {
6342 unsigned index = 0;
6343 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6344 struct ac_export_args color_args[8];
6345
6346 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6347 LLVMValueRef values[4];
6348
6349 if (!(ctx->output_mask & (1ull << i)))
6350 continue;
6351
6352 if (i == FRAG_RESULT_DEPTH) {
6353 ctx->shader_info->fs.writes_z = true;
6354 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6355 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6356 } else if (i == FRAG_RESULT_STENCIL) {
6357 ctx->shader_info->fs.writes_stencil = true;
6358 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6359 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6360 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6361 ctx->shader_info->fs.writes_sample_mask = true;
6362 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6363 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6364 } else {
6365 bool last = false;
6366 for (unsigned j = 0; j < 4; j++)
6367 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6368 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6369
6370 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6371 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6372
6373 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6374 if (ret)
6375 index++;
6376 }
6377 }
6378
6379 for (unsigned i = 0; i < index; i++)
6380 ac_build_export(&ctx->ac, &color_args[i]);
6381 if (depth || stencil || samplemask)
6382 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6383 else if (!index) {
6384 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6385 ac_build_export(&ctx->ac, &color_args[0]);
6386 }
6387
6388 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6389 }
6390
6391 static void
6392 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6393 {
6394 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6395 }
6396
6397 static void
6398 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6399 LLVMValueRef *addrs)
6400 {
6401 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6402
6403 switch (ctx->stage) {
6404 case MESA_SHADER_VERTEX:
6405 if (ctx->options->key.vs.as_ls)
6406 handle_ls_outputs_post(ctx);
6407 else if (ctx->options->key.vs.as_es)
6408 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6409 else
6410 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6411 &ctx->shader_info->vs.outinfo);
6412 break;
6413 case MESA_SHADER_FRAGMENT:
6414 handle_fs_outputs_post(ctx);
6415 break;
6416 case MESA_SHADER_GEOMETRY:
6417 emit_gs_epilogue(ctx);
6418 break;
6419 case MESA_SHADER_TESS_CTRL:
6420 handle_tcs_outputs_post(ctx);
6421 break;
6422 case MESA_SHADER_TESS_EVAL:
6423 if (ctx->options->key.tes.as_es)
6424 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6425 else
6426 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6427 &ctx->shader_info->tes.outinfo);
6428 break;
6429 default:
6430 break;
6431 }
6432 }
6433
6434 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6435 {
6436 LLVMPassManagerRef passmgr;
6437 /* Create the pass manager */
6438 passmgr = LLVMCreateFunctionPassManagerForModule(
6439 ctx->module);
6440
6441 /* This pass should eliminate all the load and store instructions */
6442 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6443
6444 /* Add some optimization passes */
6445 LLVMAddScalarReplAggregatesPass(passmgr);
6446 LLVMAddLICMPass(passmgr);
6447 LLVMAddAggressiveDCEPass(passmgr);
6448 LLVMAddCFGSimplificationPass(passmgr);
6449 LLVMAddInstructionCombiningPass(passmgr);
6450
6451 /* Run the pass */
6452 LLVMInitializeFunctionPassManager(passmgr);
6453 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6454 LLVMFinalizeFunctionPassManager(passmgr);
6455
6456 LLVMDisposeBuilder(ctx->builder);
6457 LLVMDisposePassManager(passmgr);
6458 }
6459
6460 static void
6461 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6462 {
6463 struct ac_vs_output_info *outinfo;
6464
6465 switch (ctx->stage) {
6466 case MESA_SHADER_FRAGMENT:
6467 case MESA_SHADER_COMPUTE:
6468 case MESA_SHADER_TESS_CTRL:
6469 case MESA_SHADER_GEOMETRY:
6470 return;
6471 case MESA_SHADER_VERTEX:
6472 if (ctx->options->key.vs.as_ls ||
6473 ctx->options->key.vs.as_es)
6474 return;
6475 outinfo = &ctx->shader_info->vs.outinfo;
6476 break;
6477 case MESA_SHADER_TESS_EVAL:
6478 if (ctx->options->key.vs.as_es)
6479 return;
6480 outinfo = &ctx->shader_info->tes.outinfo;
6481 break;
6482 default:
6483 unreachable("Unhandled shader type");
6484 }
6485
6486 ac_optimize_vs_outputs(&ctx->ac,
6487 ctx->main_function,
6488 outinfo->vs_output_param_offset,
6489 VARYING_SLOT_MAX,
6490 &outinfo->param_exports);
6491 }
6492
6493 static void
6494 ac_setup_rings(struct nir_to_llvm_context *ctx)
6495 {
6496 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6497 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6498 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6499 }
6500
6501 if (ctx->is_gs_copy_shader) {
6502 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6503 }
6504 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6505 LLVMValueRef tmp;
6506 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6507 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6508
6509 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6510
6511 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6512 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6513 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6514 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6515 }
6516
6517 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6518 ctx->stage == MESA_SHADER_TESS_EVAL) {
6519 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6520 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6521 }
6522 }
6523
6524 static unsigned
6525 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6526 const struct nir_shader *nir)
6527 {
6528 switch (nir->info.stage) {
6529 case MESA_SHADER_TESS_CTRL:
6530 return chip_class >= CIK ? 128 : 64;
6531 case MESA_SHADER_GEOMETRY:
6532 return chip_class >= GFX9 ? 128 : 64;
6533 case MESA_SHADER_COMPUTE:
6534 break;
6535 default:
6536 return 0;
6537 }
6538
6539 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6540 nir->info.cs.local_size[1] *
6541 nir->info.cs.local_size[2];
6542 return max_workgroup_size;
6543 }
6544
6545 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6546 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6547 {
6548 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6549 LLVMConstInt(ctx->ac.i32, 8, false),
6550 LLVMConstInt(ctx->ac.i32, 8, false), false);
6551 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6552 ctx->ac.i32_0, "");
6553 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6554 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6555 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6556 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6557 }
6558
6559 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6560 {
6561 for(int i = 5; i >= 0; --i) {
6562 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6563 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6564 LLVMConstInt(ctx->ac.i32, 16, false), false);
6565 }
6566
6567 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6568 LLVMConstInt(ctx->ac.i32, 16, false),
6569 LLVMConstInt(ctx->ac.i32, 8, false), false);
6570 }
6571
6572 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6573 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6574 {
6575 struct ac_nir_context ctx = {};
6576 struct nir_function *func;
6577
6578 ctx.ac = *ac;
6579 ctx.abi = abi;
6580
6581 ctx.nctx = nctx;
6582 if (nctx)
6583 nctx->nir = &ctx;
6584
6585 ctx.stage = nir->info.stage;
6586
6587 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6588
6589 nir_foreach_variable(variable, &nir->outputs)
6590 handle_shader_output_decl(&ctx, nir, variable);
6591
6592 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6593 _mesa_key_pointer_equal);
6594 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6595 _mesa_key_pointer_equal);
6596 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6597 _mesa_key_pointer_equal);
6598
6599 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6600
6601 setup_locals(&ctx, func);
6602
6603 if (nir->info.stage == MESA_SHADER_COMPUTE)
6604 setup_shared(&ctx, nir);
6605
6606 visit_cf_list(&ctx, &func->impl->body);
6607 phi_post_pass(&ctx);
6608
6609 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6610 ctx.outputs);
6611
6612 free(ctx.locals);
6613 ralloc_free(ctx.defs);
6614 ralloc_free(ctx.phis);
6615 ralloc_free(ctx.vars);
6616
6617 if (nctx)
6618 nctx->nir = NULL;
6619 }
6620
6621 static
6622 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6623 struct nir_shader *const *shaders,
6624 int shader_count,
6625 struct ac_shader_variant_info *shader_info,
6626 const struct ac_nir_compiler_options *options)
6627 {
6628 struct nir_to_llvm_context ctx = {0};
6629 unsigned i;
6630 ctx.options = options;
6631 ctx.shader_info = shader_info;
6632 ctx.context = LLVMContextCreate();
6633 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6634
6635 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6636 options->family);
6637 ctx.ac.module = ctx.module;
6638 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6639
6640 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6641 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6642 LLVMSetDataLayout(ctx.module, data_layout_str);
6643 LLVMDisposeTargetData(data_layout);
6644 LLVMDisposeMessage(data_layout_str);
6645
6646 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6647 ctx.ac.builder = ctx.builder;
6648
6649 memset(shader_info, 0, sizeof(*shader_info));
6650
6651 for(int i = 0; i < shader_count; ++i)
6652 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6653
6654 for (i = 0; i < AC_UD_MAX_SETS; i++)
6655 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6656 for (i = 0; i < AC_UD_MAX_UD; i++)
6657 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6658
6659 ctx.max_workgroup_size = 0;
6660 for (int i = 0; i < shader_count; ++i) {
6661 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6662 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6663 shaders[i]));
6664 }
6665
6666 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6667 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6668
6669 ctx.abi.inputs = &ctx.inputs[0];
6670 ctx.abi.emit_outputs = handle_shader_outputs_post;
6671 ctx.abi.emit_vertex = visit_emit_vertex;
6672 ctx.abi.load_ubo = radv_load_ubo;
6673 ctx.abi.load_ssbo = radv_load_ssbo;
6674 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6675 ctx.abi.clamp_shadow_reference = false;
6676
6677 if (shader_count >= 2)
6678 ac_init_exec_full_mask(&ctx.ac);
6679
6680 if (ctx.ac.chip_class == GFX9 &&
6681 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6682 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6683
6684 for(int i = 0; i < shader_count; ++i) {
6685 ctx.stage = shaders[i]->info.stage;
6686 ctx.output_mask = 0;
6687 ctx.tess_outputs_written = 0;
6688 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6689 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6690
6691 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6692 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6693 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6694 ctx.abi.load_inputs = load_gs_input;
6695 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6696 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6697 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6698 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6699 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6700 ctx.abi.load_tess_inputs = load_tes_input;
6701 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6702 if (shader_info->info.vs.needs_instance_id) {
6703 ctx.shader_info->vs.vgpr_comp_cnt =
6704 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6705 }
6706 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6707 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6708 }
6709
6710 if (i)
6711 emit_barrier(&ctx);
6712
6713 ac_setup_rings(&ctx);
6714
6715 LLVMBasicBlockRef merge_block;
6716 if (shader_count >= 2) {
6717 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6718 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6719 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6720
6721 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6722 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6723 LLVMConstInt(ctx.ac.i32, 8, false), false);
6724 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6725 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6726 thread_id, count, "");
6727 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6728
6729 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6730 }
6731
6732 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6733 handle_fs_inputs(&ctx, shaders[i]);
6734 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6735 handle_vs_inputs(&ctx, shaders[i]);
6736 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6737 prepare_gs_input_vgprs(&ctx);
6738
6739 nir_foreach_variable(variable, &shaders[i]->outputs)
6740 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6741
6742 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6743
6744 if (shader_count >= 2) {
6745 LLVMBuildBr(ctx.ac.builder, merge_block);
6746 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6747 }
6748
6749 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6750 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6751 shaders[i]->info.cull_distance_array_size > 4;
6752 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6753 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6754 shaders[i]->info.gs.vertices_out;
6755 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6756 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6757 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6758 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6759 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6760 }
6761 }
6762
6763 LLVMBuildRetVoid(ctx.builder);
6764
6765 ac_llvm_finalize_module(&ctx);
6766
6767 if (shader_count == 1)
6768 ac_nir_eliminate_const_vs_outputs(&ctx);
6769
6770 return ctx.module;
6771 }
6772
6773 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6774 {
6775 unsigned *retval = (unsigned *)context;
6776 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6777 char *description = LLVMGetDiagInfoDescription(di);
6778
6779 if (severity == LLVMDSError) {
6780 *retval = 1;
6781 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6782 description);
6783 }
6784
6785 LLVMDisposeMessage(description);
6786 }
6787
6788 static unsigned ac_llvm_compile(LLVMModuleRef M,
6789 struct ac_shader_binary *binary,
6790 LLVMTargetMachineRef tm)
6791 {
6792 unsigned retval = 0;
6793 char *err;
6794 LLVMContextRef llvm_ctx;
6795 LLVMMemoryBufferRef out_buffer;
6796 unsigned buffer_size;
6797 const char *buffer_data;
6798 LLVMBool mem_err;
6799
6800 /* Setup Diagnostic Handler*/
6801 llvm_ctx = LLVMGetModuleContext(M);
6802
6803 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6804 &retval);
6805
6806 /* Compile IR*/
6807 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6808 &err, &out_buffer);
6809
6810 /* Process Errors/Warnings */
6811 if (mem_err) {
6812 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6813 free(err);
6814 retval = 1;
6815 goto out;
6816 }
6817
6818 /* Extract Shader Code*/
6819 buffer_size = LLVMGetBufferSize(out_buffer);
6820 buffer_data = LLVMGetBufferStart(out_buffer);
6821
6822 ac_elf_read(buffer_data, buffer_size, binary);
6823
6824 /* Clean up */
6825 LLVMDisposeMemoryBuffer(out_buffer);
6826
6827 out:
6828 return retval;
6829 }
6830
6831 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6832 LLVMModuleRef llvm_module,
6833 struct ac_shader_binary *binary,
6834 struct ac_shader_config *config,
6835 struct ac_shader_variant_info *shader_info,
6836 gl_shader_stage stage,
6837 bool dump_shader, bool supports_spill)
6838 {
6839 if (dump_shader)
6840 ac_dump_module(llvm_module);
6841
6842 memset(binary, 0, sizeof(*binary));
6843 int v = ac_llvm_compile(llvm_module, binary, tm);
6844 if (v) {
6845 fprintf(stderr, "compile failed\n");
6846 }
6847
6848 if (dump_shader)
6849 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6850
6851 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6852
6853 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6854 LLVMDisposeModule(llvm_module);
6855 LLVMContextDispose(ctx);
6856
6857 if (stage == MESA_SHADER_FRAGMENT) {
6858 shader_info->num_input_vgprs = 0;
6859 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 2;
6861 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 2;
6863 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 2;
6865 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 3;
6867 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 2;
6869 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 2;
6871 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 2;
6873 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 1;
6875 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 1;
6877 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6878 shader_info->num_input_vgprs += 1;
6879 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6880 shader_info->num_input_vgprs += 1;
6881 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6882 shader_info->num_input_vgprs += 1;
6883 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6884 shader_info->num_input_vgprs += 1;
6885 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6886 shader_info->num_input_vgprs += 1;
6887 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6888 shader_info->num_input_vgprs += 1;
6889 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6890 shader_info->num_input_vgprs += 1;
6891 }
6892 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6893
6894 /* +3 for scratch wave offset and VCC */
6895 config->num_sgprs = MAX2(config->num_sgprs,
6896 shader_info->num_input_sgprs + 3);
6897 }
6898
6899 static void
6900 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6901 {
6902 switch (nir->info.stage) {
6903 case MESA_SHADER_COMPUTE:
6904 for (int i = 0; i < 3; ++i)
6905 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6906 break;
6907 case MESA_SHADER_FRAGMENT:
6908 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6909 break;
6910 case MESA_SHADER_GEOMETRY:
6911 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6912 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6913 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6914 shader_info->gs.invocations = nir->info.gs.invocations;
6915 break;
6916 case MESA_SHADER_TESS_EVAL:
6917 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6918 shader_info->tes.spacing = nir->info.tess.spacing;
6919 shader_info->tes.ccw = nir->info.tess.ccw;
6920 shader_info->tes.point_mode = nir->info.tess.point_mode;
6921 shader_info->tes.as_es = options->key.tes.as_es;
6922 break;
6923 case MESA_SHADER_TESS_CTRL:
6924 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6925 break;
6926 case MESA_SHADER_VERTEX:
6927 shader_info->vs.as_es = options->key.vs.as_es;
6928 shader_info->vs.as_ls = options->key.vs.as_ls;
6929 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6930 if (options->key.vs.as_ls)
6931 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6932 break;
6933 default:
6934 break;
6935 }
6936 }
6937
6938 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6939 struct ac_shader_binary *binary,
6940 struct ac_shader_config *config,
6941 struct ac_shader_variant_info *shader_info,
6942 struct nir_shader *const *nir,
6943 int nir_count,
6944 const struct ac_nir_compiler_options *options,
6945 bool dump_shader)
6946 {
6947
6948 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6949 options);
6950
6951 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6952 for (int i = 0; i < nir_count; ++i)
6953 ac_fill_shader_info(shader_info, nir[i], options);
6954 }
6955
6956 static void
6957 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6958 {
6959 LLVMValueRef args[9];
6960 args[0] = ctx->gsvs_ring;
6961 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6962 args[3] = ctx->ac.i32_0;
6963 args[4] = ctx->ac.i32_1; /* OFFEN */
6964 args[5] = ctx->ac.i32_0; /* IDXEN */
6965 args[6] = ctx->ac.i32_1; /* GLC */
6966 args[7] = ctx->ac.i32_1; /* SLC */
6967 args[8] = ctx->ac.i32_0; /* TFE */
6968
6969 int idx = 0;
6970
6971 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6972 int length = 4;
6973 int slot = idx;
6974 int slot_inc = 1;
6975 if (!(ctx->output_mask & (1ull << i)))
6976 continue;
6977
6978 if (i == VARYING_SLOT_CLIP_DIST0) {
6979 /* unpack clip and cull from a single set of slots */
6980 length = ctx->num_output_clips + ctx->num_output_culls;
6981 if (length > 4)
6982 slot_inc = 2;
6983 }
6984
6985 for (unsigned j = 0; j < length; j++) {
6986 LLVMValueRef value;
6987 args[2] = LLVMConstInt(ctx->ac.i32,
6988 (slot * 4 + j) *
6989 ctx->gs_max_out_vertices * 16 * 4, false);
6990
6991 value = ac_build_intrinsic(&ctx->ac,
6992 "llvm.SI.buffer.load.dword.i32.i32",
6993 ctx->ac.i32, args, 9,
6994 AC_FUNC_ATTR_READONLY |
6995 AC_FUNC_ATTR_LEGACY);
6996
6997 LLVMBuildStore(ctx->builder,
6998 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6999 }
7000 idx += slot_inc;
7001 }
7002 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7003 }
7004
7005 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7006 struct nir_shader *geom_shader,
7007 struct ac_shader_binary *binary,
7008 struct ac_shader_config *config,
7009 struct ac_shader_variant_info *shader_info,
7010 const struct ac_nir_compiler_options *options,
7011 bool dump_shader)
7012 {
7013 struct nir_to_llvm_context ctx = {0};
7014 ctx.context = LLVMContextCreate();
7015 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7016 ctx.options = options;
7017 ctx.shader_info = shader_info;
7018
7019 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7020 options->family);
7021 ctx.ac.module = ctx.module;
7022
7023 ctx.is_gs_copy_shader = true;
7024 LLVMSetTarget(ctx.module, "amdgcn--");
7025
7026 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7027 ctx.ac.builder = ctx.builder;
7028 ctx.stage = MESA_SHADER_VERTEX;
7029
7030 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7031
7032 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7033 ac_setup_rings(&ctx);
7034
7035 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7036 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7037
7038 struct ac_nir_context nir_ctx = {};
7039 nir_ctx.ac = ctx.ac;
7040 nir_ctx.abi = &ctx.abi;
7041
7042 nir_ctx.nctx = &ctx;
7043 ctx.nir = &nir_ctx;
7044
7045 nir_foreach_variable(variable, &geom_shader->outputs) {
7046 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7047 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7048 }
7049
7050 ac_gs_copy_shader_emit(&ctx);
7051
7052 ctx.nir = NULL;
7053
7054 LLVMBuildRetVoid(ctx.builder);
7055
7056 ac_llvm_finalize_module(&ctx);
7057
7058 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7059 MESA_SHADER_VERTEX,
7060 dump_shader, options->supports_spill);
7061 }