2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct ac_nir_context
{
49 struct ac_llvm_context ac
;
50 struct ac_shader_abi
*abi
;
52 gl_shader_stage stage
;
54 struct hash_table
*defs
;
55 struct hash_table
*phis
;
56 struct hash_table
*vars
;
58 LLVMValueRef main_function
;
59 LLVMBasicBlockRef continue_block
;
60 LLVMBasicBlockRef break_block
;
66 struct radv_shader_context
{
67 struct ac_llvm_context ac
;
68 const struct ac_nir_compiler_options
*options
;
69 struct ac_shader_variant_info
*shader_info
;
70 struct ac_shader_abi abi
;
72 unsigned max_workgroup_size
;
73 LLVMContextRef context
;
74 LLVMValueRef main_function
;
76 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
77 LLVMValueRef ring_offsets
;
79 LLVMValueRef vertex_buffers
;
80 LLVMValueRef rel_auto_id
;
81 LLVMValueRef vs_prim_id
;
82 LLVMValueRef ls_out_layout
;
83 LLVMValueRef es2gs_offset
;
85 LLVMValueRef tcs_offchip_layout
;
86 LLVMValueRef tcs_out_offsets
;
87 LLVMValueRef tcs_out_layout
;
88 LLVMValueRef tcs_in_layout
;
90 LLVMValueRef merged_wave_info
;
91 LLVMValueRef tess_factor_offset
;
92 LLVMValueRef tes_rel_patch_id
;
96 LLVMValueRef gsvs_ring_stride
;
97 LLVMValueRef gsvs_num_entries
;
98 LLVMValueRef gs2vs_offset
;
99 LLVMValueRef gs_wave_id
;
100 LLVMValueRef gs_vtx_offset
[6];
102 LLVMValueRef esgs_ring
;
103 LLVMValueRef gsvs_ring
;
104 LLVMValueRef hs_ring_tess_offchip
;
105 LLVMValueRef hs_ring_tess_factor
;
107 LLVMValueRef sample_pos_offset
;
108 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
109 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
111 gl_shader_stage stage
;
113 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
116 uint64_t output_mask
;
117 uint8_t num_output_clips
;
118 uint8_t num_output_culls
;
120 bool is_gs_copy_shader
;
121 LLVMValueRef gs_next_vertex
;
122 unsigned gs_max_out_vertices
;
124 unsigned tes_primitive_mode
;
125 uint64_t tess_outputs_written
;
126 uint64_t tess_patch_outputs_written
;
128 uint32_t tcs_patch_outputs_read
;
129 uint64_t tcs_outputs_read
;
130 uint32_t tcs_vertices_per_patch
;
133 static inline struct radv_shader_context
*
134 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
136 struct radv_shader_context
*ctx
= NULL
;
137 return container_of(abi
, ctx
, abi
);
140 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
141 const nir_deref_var
*deref
,
142 enum ac_descriptor_type desc_type
,
143 const nir_tex_instr
*instr
,
144 bool image
, bool write
);
146 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
148 return (index
* 4) + chan
;
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
153 /* handle patch indices separate */
154 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
156 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
158 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
159 return 2 + (slot
- VARYING_SLOT_PATCH0
);
161 if (slot
== VARYING_SLOT_POS
)
163 if (slot
== VARYING_SLOT_PSIZ
)
165 if (slot
== VARYING_SLOT_CLIP_DIST0
)
167 /* 3 is reserved for clip dist as well */
168 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
169 return 4 + (slot
- VARYING_SLOT_VAR0
);
170 unreachable("illegal slot in get unique index\n");
173 static void set_llvm_calling_convention(LLVMValueRef func
,
174 gl_shader_stage stage
)
176 enum radeon_llvm_calling_convention calling_conv
;
179 case MESA_SHADER_VERTEX
:
180 case MESA_SHADER_TESS_EVAL
:
181 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
183 case MESA_SHADER_GEOMETRY
:
184 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
186 case MESA_SHADER_TESS_CTRL
:
187 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
189 case MESA_SHADER_FRAGMENT
:
190 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
192 case MESA_SHADER_COMPUTE
:
193 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
196 unreachable("Unhandle shader type");
199 LLVMSetFunctionCallConv(func
, calling_conv
);
204 LLVMTypeRef types
[MAX_ARGS
];
205 LLVMValueRef
*assign
[MAX_ARGS
];
206 unsigned array_params_mask
;
209 uint8_t num_sgprs_used
;
210 uint8_t num_vgprs_used
;
213 enum ac_arg_regfile
{
219 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
220 LLVMValueRef
*param_ptr
)
222 assert(info
->count
< MAX_ARGS
);
224 info
->assign
[info
->count
] = param_ptr
;
225 info
->types
[info
->count
] = type
;
228 if (regfile
== ARG_SGPR
) {
229 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
232 assert(regfile
== ARG_VGPR
);
233 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
238 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
240 info
->array_params_mask
|= (1 << info
->count
);
241 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
244 static void assign_arguments(LLVMValueRef main_function
,
245 struct arg_info
*info
)
248 for (i
= 0; i
< info
->count
; i
++) {
250 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
255 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
256 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
257 unsigned num_return_elems
,
258 struct arg_info
*args
,
259 unsigned max_workgroup_size
,
262 LLVMTypeRef main_function_type
, ret_type
;
263 LLVMBasicBlockRef main_function_body
;
265 if (num_return_elems
)
266 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
267 num_return_elems
, true);
269 ret_type
= LLVMVoidTypeInContext(ctx
);
271 /* Setup the function */
273 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
274 LLVMValueRef main_function
=
275 LLVMAddFunction(module
, "main", main_function_type
);
277 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
278 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
280 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
281 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
282 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
284 if (args
->array_params_mask
& (1 << i
)) {
285 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
286 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
287 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
291 if (max_workgroup_size
) {
292 ac_llvm_add_target_dep_function_attr(main_function
,
293 "amdgpu-max-work-group-size",
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function
,
299 "less-precise-fpmad",
301 LLVMAddTargetDependentFunctionAttr(main_function
,
304 LLVMAddTargetDependentFunctionAttr(main_function
,
307 LLVMAddTargetDependentFunctionAttr(main_function
,
310 LLVMAddTargetDependentFunctionAttr(main_function
,
311 "no-signed-zeros-fp-math",
314 return main_function
;
317 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
318 LLVMValueRef param
, unsigned rshift
,
321 LLVMValueRef value
= param
;
323 value
= LLVMBuildLShr(ctx
->builder
, value
,
324 LLVMConstInt(ctx
->i32
, rshift
, false), "");
326 if (rshift
+ bitwidth
< 32) {
327 unsigned mask
= (1 << bitwidth
) - 1;
328 value
= LLVMBuildAnd(ctx
->builder
, value
,
329 LLVMConstInt(ctx
->i32
, mask
, false), "");
334 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
336 switch (ctx
->stage
) {
337 case MESA_SHADER_TESS_CTRL
:
338 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
339 case MESA_SHADER_TESS_EVAL
:
340 return ctx
->tes_rel_patch_id
;
343 unreachable("Illegal stage");
347 /* Tessellation shaders pass outputs to the next shader using LDS.
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
368 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
370 if (ctx
->stage
== MESA_SHADER_VERTEX
)
371 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
372 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
373 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
381 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
383 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
387 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
389 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
393 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
395 return LLVMBuildMul(ctx
->ac
.builder
,
396 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
397 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
403 return LLVMBuildMul(ctx
->ac
.builder
,
404 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
405 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
409 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
411 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
412 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
414 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
418 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
420 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
421 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
422 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
424 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
425 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
433 LLVMValueRef patch0_patch_data_offset
=
434 get_tcs_out_patch0_patch_data_offset(ctx
);
435 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
436 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
438 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
439 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
445 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
446 uint32_t indirect_offset
)
448 ud_info
->sgpr_idx
= *sgpr_idx
;
449 ud_info
->num_sgprs
= num_sgprs
;
450 ud_info
->indirect
= indirect_offset
> 0;
451 ud_info
->indirect_offset
= indirect_offset
;
452 *sgpr_idx
+= num_sgprs
;
456 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
459 struct ac_userdata_info
*ud_info
=
460 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
463 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
467 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
468 uint32_t indirect_offset
)
470 struct ac_userdata_info
*ud_info
=
471 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
474 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
477 struct user_sgpr_info
{
478 bool need_ring_offsets
;
480 bool indirect_all_descriptor_sets
;
483 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
484 gl_shader_stage stage
)
487 case MESA_SHADER_VERTEX
:
488 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
489 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
492 case MESA_SHADER_TESS_EVAL
:
493 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
496 case MESA_SHADER_GEOMETRY
:
497 case MESA_SHADER_TESS_CTRL
:
498 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
508 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
512 count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
513 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
518 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
519 gl_shader_stage stage
,
520 bool has_previous_stage
,
521 gl_shader_stage previous_stage
,
522 bool needs_view_index
,
523 struct user_sgpr_info
*user_sgpr_info
)
525 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage
== MESA_SHADER_GEOMETRY
||
529 stage
== MESA_SHADER_VERTEX
||
530 stage
== MESA_SHADER_TESS_CTRL
||
531 stage
== MESA_SHADER_TESS_EVAL
||
532 ctx
->is_gs_copy_shader
)
533 user_sgpr_info
->need_ring_offsets
= true;
535 if (stage
== MESA_SHADER_FRAGMENT
&&
536 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
537 user_sgpr_info
->need_ring_offsets
= true;
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
541 user_sgpr_info
->sgpr_count
+= 2;
545 case MESA_SHADER_COMPUTE
:
546 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
547 user_sgpr_info
->sgpr_count
+= 3;
549 case MESA_SHADER_FRAGMENT
:
550 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
552 case MESA_SHADER_VERTEX
:
553 if (!ctx
->is_gs_copy_shader
)
554 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
555 if (ctx
->options
->key
.vs
.as_ls
)
556 user_sgpr_info
->sgpr_count
++;
558 case MESA_SHADER_TESS_CTRL
:
559 if (has_previous_stage
) {
560 if (previous_stage
== MESA_SHADER_VERTEX
)
561 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
562 user_sgpr_info
->sgpr_count
++;
564 user_sgpr_info
->sgpr_count
+= 4;
566 case MESA_SHADER_TESS_EVAL
:
567 user_sgpr_info
->sgpr_count
+= 1;
569 case MESA_SHADER_GEOMETRY
:
570 if (has_previous_stage
) {
571 if (previous_stage
== MESA_SHADER_VERTEX
) {
572 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
574 user_sgpr_info
->sgpr_count
++;
577 user_sgpr_info
->sgpr_count
+= 2;
583 if (needs_view_index
)
584 user_sgpr_info
->sgpr_count
++;
586 if (ctx
->shader_info
->info
.loads_push_constants
)
587 user_sgpr_info
->sgpr_count
+= 2;
589 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
590 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
592 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
593 user_sgpr_info
->sgpr_count
+= 2;
594 user_sgpr_info
->indirect_all_descriptor_sets
= true;
596 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
601 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
602 gl_shader_stage stage
,
603 bool has_previous_stage
,
604 gl_shader_stage previous_stage
,
605 const struct user_sgpr_info
*user_sgpr_info
,
606 struct arg_info
*args
,
607 LLVMValueRef
*desc_sets
)
609 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
610 unsigned num_sets
= ctx
->options
->layout
?
611 ctx
->options
->layout
->num_sets
: 0;
612 unsigned stage_mask
= 1 << stage
;
614 if (has_previous_stage
)
615 stage_mask
|= 1 << previous_stage
;
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
619 for (unsigned i
= 0; i
< num_sets
; ++i
) {
620 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
621 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
622 add_array_arg(args
, type
,
623 &ctx
->descriptor_sets
[i
]);
627 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
630 if (ctx
->shader_info
->info
.loads_push_constants
) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
637 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
638 gl_shader_stage stage
,
639 bool has_previous_stage
,
640 gl_shader_stage previous_stage
,
641 struct arg_info
*args
)
643 if (!ctx
->is_gs_copy_shader
&&
644 (stage
== MESA_SHADER_VERTEX
||
645 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
646 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
647 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
648 &ctx
->vertex_buffers
);
650 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
651 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
652 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
653 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
659 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
661 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
662 if (!ctx
->is_gs_copy_shader
) {
663 if (ctx
->options
->key
.vs
.as_ls
) {
664 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
665 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
667 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
668 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
670 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
675 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
677 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
679 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
680 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
684 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
685 bool has_previous_stage
, gl_shader_stage previous_stage
,
686 const struct user_sgpr_info
*user_sgpr_info
,
687 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
689 unsigned num_sets
= ctx
->options
->layout
?
690 ctx
->options
->layout
->num_sets
: 0;
691 unsigned stage_mask
= 1 << stage
;
693 if (has_previous_stage
)
694 stage_mask
|= 1 << previous_stage
;
696 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
697 for (unsigned i
= 0; i
< num_sets
; ++i
) {
698 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
699 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
700 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
702 ctx
->descriptor_sets
[i
] = NULL
;
705 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
708 for (unsigned i
= 0; i
< num_sets
; ++i
) {
709 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
710 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
711 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
712 ctx
->descriptor_sets
[i
] =
713 ac_build_load_to_sgpr(&ctx
->ac
,
715 LLVMConstInt(ctx
->ac
.i32
, i
, false));
718 ctx
->descriptor_sets
[i
] = NULL
;
720 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
723 if (ctx
->shader_info
->info
.loads_push_constants
) {
724 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
729 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
730 gl_shader_stage stage
, bool has_previous_stage
,
731 gl_shader_stage previous_stage
,
732 uint8_t *user_sgpr_idx
)
734 if (!ctx
->is_gs_copy_shader
&&
735 (stage
== MESA_SHADER_VERTEX
||
736 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
737 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
738 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
743 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
746 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
747 user_sgpr_idx
, vs_num
);
751 static void create_function(struct radv_shader_context
*ctx
,
752 gl_shader_stage stage
,
753 bool has_previous_stage
,
754 gl_shader_stage previous_stage
)
756 uint8_t user_sgpr_idx
;
757 struct user_sgpr_info user_sgpr_info
;
758 struct arg_info args
= {};
759 LLVMValueRef desc_sets
;
760 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
761 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
762 previous_stage
, needs_view_index
, &user_sgpr_info
);
764 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
765 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
770 case MESA_SHADER_COMPUTE
:
771 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
772 previous_stage
, &user_sgpr_info
,
775 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
776 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
777 &ctx
->abi
.num_work_groups
);
780 for (int i
= 0; i
< 3; i
++) {
781 ctx
->abi
.workgroup_ids
[i
] = NULL
;
782 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
783 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
784 &ctx
->abi
.workgroup_ids
[i
]);
788 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
789 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
790 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
791 &ctx
->abi
.local_invocation_ids
);
793 case MESA_SHADER_VERTEX
:
794 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
795 previous_stage
, &user_sgpr_info
,
797 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
798 previous_stage
, &args
);
800 if (needs_view_index
)
801 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
802 &ctx
->abi
.view_index
);
803 if (ctx
->options
->key
.vs
.as_es
)
804 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
806 else if (ctx
->options
->key
.vs
.as_ls
)
807 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
808 &ctx
->ls_out_layout
);
810 declare_vs_input_vgprs(ctx
, &args
);
812 case MESA_SHADER_TESS_CTRL
:
813 if (has_previous_stage
) {
814 // First 6 system regs
815 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
816 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
817 &ctx
->merged_wave_info
);
818 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
819 &ctx
->tess_factor_offset
);
821 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
823 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
825 declare_global_input_sgprs(ctx
, stage
,
828 &user_sgpr_info
, &args
,
830 declare_vs_specific_input_sgprs(ctx
, stage
,
832 previous_stage
, &args
);
834 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
835 &ctx
->ls_out_layout
);
837 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
838 &ctx
->tcs_offchip_layout
);
839 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
840 &ctx
->tcs_out_offsets
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
842 &ctx
->tcs_out_layout
);
843 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
844 &ctx
->tcs_in_layout
);
845 if (needs_view_index
)
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->abi
.view_index
);
849 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
850 &ctx
->abi
.tcs_patch_id
);
851 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
852 &ctx
->abi
.tcs_rel_ids
);
854 declare_vs_input_vgprs(ctx
, &args
);
856 declare_global_input_sgprs(ctx
, stage
,
859 &user_sgpr_info
, &args
,
862 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
863 &ctx
->tcs_offchip_layout
);
864 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
865 &ctx
->tcs_out_offsets
);
866 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
867 &ctx
->tcs_out_layout
);
868 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
869 &ctx
->tcs_in_layout
);
870 if (needs_view_index
)
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->abi
.view_index
);
874 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tess_factor_offset
);
877 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
878 &ctx
->abi
.tcs_patch_id
);
879 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
880 &ctx
->abi
.tcs_rel_ids
);
883 case MESA_SHADER_TESS_EVAL
:
884 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
885 previous_stage
, &user_sgpr_info
,
888 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
889 if (needs_view_index
)
890 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
891 &ctx
->abi
.view_index
);
893 if (ctx
->options
->key
.tes
.as_es
) {
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
895 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
896 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
899 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
902 declare_tes_input_vgprs(ctx
, &args
);
904 case MESA_SHADER_GEOMETRY
:
905 if (has_previous_stage
) {
906 // First 6 system regs
907 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
909 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
910 &ctx
->merged_wave_info
);
911 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
914 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
917 declare_global_input_sgprs(ctx
, stage
,
920 &user_sgpr_info
, &args
,
923 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
924 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
925 &ctx
->tcs_offchip_layout
);
927 declare_vs_specific_input_sgprs(ctx
, stage
,
933 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
934 &ctx
->gsvs_ring_stride
);
935 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
936 &ctx
->gsvs_num_entries
);
937 if (needs_view_index
)
938 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
939 &ctx
->abi
.view_index
);
941 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
942 &ctx
->gs_vtx_offset
[0]);
943 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
944 &ctx
->gs_vtx_offset
[2]);
945 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
946 &ctx
->abi
.gs_prim_id
);
947 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
948 &ctx
->abi
.gs_invocation_id
);
949 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
950 &ctx
->gs_vtx_offset
[4]);
952 if (previous_stage
== MESA_SHADER_VERTEX
) {
953 declare_vs_input_vgprs(ctx
, &args
);
955 declare_tes_input_vgprs(ctx
, &args
);
958 declare_global_input_sgprs(ctx
, stage
,
961 &user_sgpr_info
, &args
,
964 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
965 &ctx
->gsvs_ring_stride
);
966 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
967 &ctx
->gsvs_num_entries
);
968 if (needs_view_index
)
969 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
970 &ctx
->abi
.view_index
);
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
973 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
974 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
975 &ctx
->gs_vtx_offset
[0]);
976 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
977 &ctx
->gs_vtx_offset
[1]);
978 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
979 &ctx
->abi
.gs_prim_id
);
980 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
981 &ctx
->gs_vtx_offset
[2]);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->gs_vtx_offset
[3]);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->gs_vtx_offset
[4]);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->gs_vtx_offset
[5]);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
989 &ctx
->abi
.gs_invocation_id
);
992 case MESA_SHADER_FRAGMENT
:
993 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
994 previous_stage
, &user_sgpr_info
,
997 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
998 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
999 &ctx
->sample_pos_offset
);
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1002 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1003 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1004 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1006 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1007 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1020 unreachable("Shader stage not implemented");
1023 ctx
->main_function
= create_llvm_function(
1024 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1025 ctx
->max_workgroup_size
,
1026 ctx
->options
->unsafe_math
);
1027 set_llvm_calling_convention(ctx
->main_function
, stage
);
1030 ctx
->shader_info
->num_input_vgprs
= 0;
1031 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1033 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1035 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1036 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1038 assign_arguments(ctx
->main_function
, &args
);
1042 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1043 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1045 if (ctx
->options
->supports_spill
) {
1046 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1048 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1049 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1050 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage
)
1059 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1060 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1063 case MESA_SHADER_COMPUTE
:
1064 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1065 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1069 case MESA_SHADER_VERTEX
:
1070 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1071 previous_stage
, &user_sgpr_idx
);
1072 if (ctx
->abi
.view_index
)
1073 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1074 if (ctx
->options
->key
.vs
.as_ls
) {
1075 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1079 case MESA_SHADER_TESS_CTRL
:
1080 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1081 previous_stage
, &user_sgpr_idx
);
1082 if (has_previous_stage
)
1083 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1085 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1086 if (ctx
->abi
.view_index
)
1087 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1089 case MESA_SHADER_TESS_EVAL
:
1090 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1091 if (ctx
->abi
.view_index
)
1092 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1094 case MESA_SHADER_GEOMETRY
:
1095 if (has_previous_stage
) {
1096 if (previous_stage
== MESA_SHADER_VERTEX
)
1097 set_vs_specific_input_locs(ctx
, stage
,
1102 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1105 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1107 if (ctx
->abi
.view_index
)
1108 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1110 case MESA_SHADER_FRAGMENT
:
1111 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1112 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1117 unreachable("Shader stage not implemented");
1120 if (stage
== MESA_SHADER_TESS_CTRL
||
1121 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1124 ac_declare_lds_as_pointer(&ctx
->ac
);
1127 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1130 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1131 LLVMValueRef value
, unsigned count
)
1133 unsigned num_components
= ac_get_llvm_num_components(value
);
1134 if (count
== num_components
)
1137 LLVMValueRef masks
[] = {
1138 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1139 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1142 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1145 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1146 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1150 build_store_values_extended(struct ac_llvm_context
*ac
,
1151 LLVMValueRef
*values
,
1152 unsigned value_count
,
1153 unsigned value_stride
,
1156 LLVMBuilderRef builder
= ac
->builder
;
1159 for (i
= 0; i
< value_count
; i
++) {
1160 LLVMValueRef ptr
= values
[i
* value_stride
];
1161 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1162 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1163 LLVMBuildStore(builder
, value
, ptr
);
1167 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1168 const nir_ssa_def
*def
)
1170 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1171 if (def
->num_components
> 1) {
1172 type
= LLVMVectorType(type
, def
->num_components
);
1177 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1180 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1181 return (LLVMValueRef
)entry
->data
;
1185 get_memory_ptr(struct ac_nir_context
*ctx
, nir_src src
)
1187 LLVMValueRef ptr
= get_src(ctx
, src
);
1188 ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ac
.lds
, &ptr
, 1, "");
1189 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1191 return LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1192 LLVMPointerType(ctx
->ac
.i32
, addr_space
), "");
1195 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1196 const struct nir_block
*b
)
1198 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1199 return (LLVMBasicBlockRef
)entry
->data
;
1202 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1204 unsigned num_components
)
1206 LLVMValueRef value
= get_src(ctx
, src
.src
);
1207 bool need_swizzle
= false;
1210 LLVMTypeRef type
= LLVMTypeOf(value
);
1211 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1212 ? LLVMGetVectorSize(type
)
1215 for (unsigned i
= 0; i
< num_components
; ++i
) {
1216 assert(src
.swizzle
[i
] < src_components
);
1217 if (src
.swizzle
[i
] != i
)
1218 need_swizzle
= true;
1221 if (need_swizzle
|| num_components
!= src_components
) {
1222 LLVMValueRef masks
[] = {
1223 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1224 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1225 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1226 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1228 if (src_components
> 1 && num_components
== 1) {
1229 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1231 } else if (src_components
== 1 && num_components
> 1) {
1232 LLVMValueRef values
[] = {value
, value
, value
, value
};
1233 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1235 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1236 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1240 assert(!src
.negate
);
1245 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1246 LLVMIntPredicate pred
, LLVMValueRef src0
,
1249 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1250 return LLVMBuildSelect(ctx
->builder
, result
,
1251 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1255 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1256 LLVMRealPredicate pred
, LLVMValueRef src0
,
1259 LLVMValueRef result
;
1260 src0
= ac_to_float(ctx
, src0
);
1261 src1
= ac_to_float(ctx
, src1
);
1262 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1263 return LLVMBuildSelect(ctx
->builder
, result
,
1264 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1268 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1270 LLVMTypeRef result_type
,
1274 LLVMValueRef params
[] = {
1275 ac_to_float(ctx
, src0
),
1278 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1279 ac_get_elem_bits(ctx
, result_type
));
1280 assert(length
< sizeof(name
));
1281 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1284 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1286 LLVMTypeRef result_type
,
1287 LLVMValueRef src0
, LLVMValueRef src1
)
1290 LLVMValueRef params
[] = {
1291 ac_to_float(ctx
, src0
),
1292 ac_to_float(ctx
, src1
),
1295 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1296 ac_get_elem_bits(ctx
, result_type
));
1297 assert(length
< sizeof(name
));
1298 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1301 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1303 LLVMTypeRef result_type
,
1304 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1307 LLVMValueRef params
[] = {
1308 ac_to_float(ctx
, src0
),
1309 ac_to_float(ctx
, src1
),
1310 ac_to_float(ctx
, src2
),
1313 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1314 ac_get_elem_bits(ctx
, result_type
));
1315 assert(length
< sizeof(name
));
1316 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1319 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1320 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1322 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1324 return LLVMBuildSelect(ctx
->builder
, v
, ac_to_integer(ctx
, src1
),
1325 ac_to_integer(ctx
, src2
), "");
1328 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1329 LLVMIntPredicate pred
,
1330 LLVMValueRef src0
, LLVMValueRef src1
)
1332 return LLVMBuildSelect(ctx
->builder
,
1333 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1338 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1341 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1342 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1345 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1349 LLVMValueRef cmp
, val
, zero
, one
;
1352 if (bitsize
== 32) {
1362 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, zero
, "");
1363 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1364 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, zero
, "");
1365 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(type
, -1.0), "");
1369 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1370 LLVMValueRef src0
, unsigned bitsize
)
1372 LLVMValueRef cmp
, val
, zero
, one
;
1375 if (bitsize
== 32) {
1385 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, zero
, "");
1386 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1387 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, zero
, "");
1388 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(type
, -1, true), "");
1392 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1393 LLVMValueRef src0
, unsigned bitsize
)
1398 if (bitsize
== 32) {
1399 intr
= "llvm.floor.f32";
1402 intr
= "llvm.floor.f64";
1406 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1407 LLVMValueRef params
[] = {
1410 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
, type
, params
, 1,
1411 AC_FUNC_ATTR_READNONE
);
1412 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1415 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1417 LLVMValueRef src0
, LLVMValueRef src1
)
1419 LLVMTypeRef ret_type
;
1420 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1422 LLVMValueRef params
[] = { src0
, src1
};
1423 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1426 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1427 params
, 2, AC_FUNC_ATTR_READNONE
);
1429 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1430 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1434 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1437 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1440 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1443 src0
= ac_to_float(ctx
, src0
);
1444 return LLVMBuildSExt(ctx
->builder
,
1445 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1449 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1453 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1458 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1461 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1464 return LLVMBuildSExt(ctx
->builder
,
1465 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1469 static LLVMValueRef
emit_f2f16(struct ac_llvm_context
*ctx
,
1472 LLVMValueRef result
;
1473 LLVMValueRef cond
= NULL
;
1475 src0
= ac_to_float(ctx
, src0
);
1476 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->f16
, "");
1478 if (ctx
->chip_class
>= VI
) {
1479 LLVMValueRef args
[2];
1480 /* Check if the result is a denormal - and flush to 0 if so. */
1482 args
[1] = LLVMConstInt(ctx
->i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1483 cond
= ac_build_intrinsic(ctx
, "llvm.amdgcn.class.f16", ctx
->i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1486 /* need to convert back up to f32 */
1487 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->f32
, "");
1489 if (ctx
->chip_class
>= VI
)
1490 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1493 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1494 * so compare the result and flush to 0 if it's smaller.
1496 LLVMValueRef temp
, cond2
;
1497 temp
= emit_intrin_1f_param(ctx
, "llvm.fabs", ctx
->f32
, result
);
1498 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1499 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->i32
, 0x38800000, false), ctx
->f32
, ""),
1501 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1502 temp
, ctx
->f32_0
, "");
1503 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1504 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1509 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1510 LLVMValueRef src0
, LLVMValueRef src1
)
1512 LLVMValueRef dst64
, result
;
1513 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1514 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1516 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1517 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1518 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1522 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1523 LLVMValueRef src0
, LLVMValueRef src1
)
1525 LLVMValueRef dst64
, result
;
1526 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1527 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1529 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1530 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1531 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1535 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1537 const LLVMValueRef srcs
[3])
1539 LLVMValueRef result
;
1540 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1542 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1543 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1547 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1548 LLVMValueRef src0
, LLVMValueRef src1
,
1549 LLVMValueRef src2
, LLVMValueRef src3
)
1551 LLVMValueRef bfi_args
[3], result
;
1553 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1554 LLVMBuildSub(ctx
->builder
,
1555 LLVMBuildShl(ctx
->builder
,
1560 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1563 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1566 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1567 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1569 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1570 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1571 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1573 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1577 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1580 LLVMValueRef comp
[2];
1582 src0
= ac_to_float(ctx
, src0
);
1583 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1584 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1586 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1589 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1592 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1593 LLVMValueRef temps
[2], result
, val
;
1596 for (i
= 0; i
< 2; i
++) {
1597 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1598 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1599 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1600 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1603 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1605 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1610 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1616 LLVMValueRef result
;
1618 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1619 mask
= AC_TID_MASK_LEFT
;
1620 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1621 mask
= AC_TID_MASK_TOP
;
1623 mask
= AC_TID_MASK_TOP_LEFT
;
1625 /* for DDX we want to next X pixel, DDY next Y pixel. */
1626 if (op
== nir_op_fddx_fine
||
1627 op
== nir_op_fddx_coarse
||
1633 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1638 * this takes an I,J coordinate pair,
1639 * and works out the X and Y derivatives.
1640 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1642 static LLVMValueRef
emit_ddxy_interp(
1643 struct ac_nir_context
*ctx
,
1644 LLVMValueRef interp_ij
)
1646 LLVMValueRef result
[4], a
;
1649 for (i
= 0; i
< 2; i
++) {
1650 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1651 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1652 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1653 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1655 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1658 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1660 LLVMValueRef src
[4], result
= NULL
;
1661 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1662 unsigned src_components
;
1663 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1665 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1666 switch (instr
->op
) {
1672 case nir_op_pack_half_2x16
:
1675 case nir_op_unpack_half_2x16
:
1679 src_components
= num_components
;
1682 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1683 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1685 switch (instr
->op
) {
1691 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1692 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1695 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1698 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1701 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1704 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1705 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1706 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1709 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1710 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1711 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1714 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1717 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1720 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1723 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1726 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1727 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1728 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1729 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1730 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1731 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1732 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1735 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1736 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1737 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1740 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1743 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1746 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1749 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1750 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1751 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1754 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1755 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1759 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1762 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1765 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1768 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1769 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1770 LLVMTypeOf(src
[0]), ""),
1774 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1775 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1776 LLVMTypeOf(src
[0]), ""),
1780 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1781 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1782 LLVMTypeOf(src
[0]), ""),
1786 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1789 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1792 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1795 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1798 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1801 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1804 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1807 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1810 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1813 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1816 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1817 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1820 result
= emit_iabs(&ctx
->ac
, src
[0]);
1823 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1826 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1829 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1832 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1835 result
= emit_isign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1838 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1839 result
= emit_fsign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1842 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1843 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1846 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1847 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1850 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1851 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1853 case nir_op_fround_even
:
1854 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1855 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1858 result
= emit_ffract(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1861 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1862 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1865 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1866 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1869 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1870 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1873 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1874 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1877 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1878 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1881 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1882 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1883 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1887 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1888 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1891 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1892 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1893 if (ctx
->ac
.chip_class
< GFX9
&&
1894 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1895 /* Only pre-GFX9 chips do not flush denorms. */
1896 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1897 ac_to_float_type(&ctx
->ac
, def_type
),
1902 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1903 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1904 if (ctx
->ac
.chip_class
< GFX9
&&
1905 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1906 /* Only pre-GFX9 chips do not flush denorms. */
1907 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1908 ac_to_float_type(&ctx
->ac
, def_type
),
1913 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1914 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1916 case nir_op_ibitfield_extract
:
1917 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1919 case nir_op_ubitfield_extract
:
1920 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1922 case nir_op_bitfield_insert
:
1923 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1925 case nir_op_bitfield_reverse
:
1926 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1928 case nir_op_bit_count
:
1929 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1930 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1932 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i64", ctx
->ac
.i64
, src
, 1, AC_FUNC_ATTR_READNONE
);
1933 result
= LLVMBuildTrunc(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
1939 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1940 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1941 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1945 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1946 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1950 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1951 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1955 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1956 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1960 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1961 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1964 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1965 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1968 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1969 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1973 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1974 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1975 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1977 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1981 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1982 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1983 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1985 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1988 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1990 case nir_op_find_lsb
:
1991 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1992 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1994 case nir_op_ufind_msb
:
1995 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1996 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1998 case nir_op_ifind_msb
:
1999 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2000 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
2002 case nir_op_uadd_carry
:
2003 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2004 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2005 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
2007 case nir_op_usub_borrow
:
2008 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2009 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2010 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
2013 result
= emit_b2f(&ctx
->ac
, src
[0]);
2016 result
= emit_f2b(&ctx
->ac
, src
[0]);
2019 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
2022 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2023 result
= emit_i2b(&ctx
->ac
, src
[0]);
2025 case nir_op_fquantize2f16
:
2026 result
= emit_f2f16(&ctx
->ac
, src
[0]);
2028 case nir_op_umul_high
:
2029 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2030 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2031 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
2033 case nir_op_imul_high
:
2034 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2035 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2036 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
2038 case nir_op_pack_half_2x16
:
2039 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
2041 case nir_op_unpack_half_2x16
:
2042 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
2046 case nir_op_fddx_fine
:
2047 case nir_op_fddy_fine
:
2048 case nir_op_fddx_coarse
:
2049 case nir_op_fddy_coarse
:
2050 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2053 case nir_op_unpack_64_2x32_split_x
: {
2054 assert(ac_get_llvm_num_components(src
[0]) == 1);
2055 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2058 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2063 case nir_op_unpack_64_2x32_split_y
: {
2064 assert(ac_get_llvm_num_components(src
[0]) == 1);
2065 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2068 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2073 case nir_op_pack_64_2x32_split
: {
2074 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2075 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2076 src
[0], ctx
->ac
.i32_0
, "");
2077 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2078 src
[1], ctx
->ac
.i32_1
, "");
2079 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2084 fprintf(stderr
, "Unknown NIR alu instr: ");
2085 nir_print_instr(&instr
->instr
, stderr
);
2086 fprintf(stderr
, "\n");
2091 assert(instr
->dest
.dest
.is_ssa
);
2092 result
= ac_to_integer(&ctx
->ac
, result
);
2093 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2098 static void visit_load_const(struct ac_nir_context
*ctx
,
2099 const nir_load_const_instr
*instr
)
2101 LLVMValueRef values
[4], value
= NULL
;
2102 LLVMTypeRef element_type
=
2103 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2105 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2106 switch (instr
->def
.bit_size
) {
2108 values
[i
] = LLVMConstInt(element_type
,
2109 instr
->value
.u32
[i
], false);
2112 values
[i
] = LLVMConstInt(element_type
,
2113 instr
->value
.u64
[i
], false);
2117 "unsupported nir load_const bit_size: %d\n",
2118 instr
->def
.bit_size
);
2122 if (instr
->def
.num_components
> 1) {
2123 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2127 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2130 static LLVMValueRef
cast_ptr(struct ac_llvm_context
*ctx
, LLVMValueRef ptr
,
2133 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2134 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2135 LLVMPointerType(type
, addr_space
), "");
2139 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2142 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2143 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2146 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2147 /* On VI, the descriptor contains the size in bytes,
2148 * but TXQ must return the size in elements.
2149 * The stride is always non-zero for resources using TXQ.
2151 LLVMValueRef stride
=
2152 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2154 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2155 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2156 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2157 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2159 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2165 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2168 static void build_int_type_name(
2170 char *buf
, unsigned bufsize
)
2172 assert(bufsize
>= 6);
2174 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2175 snprintf(buf
, bufsize
, "v%ui32",
2176 LLVMGetVectorSize(type
));
2181 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2182 struct ac_image_args
*args
,
2183 const nir_tex_instr
*instr
)
2185 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2186 LLVMValueRef coord
= args
->addr
;
2187 LLVMValueRef half_texel
[2];
2188 LLVMValueRef compare_cube_wa
= NULL
;
2189 LLVMValueRef result
;
2191 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2195 struct ac_image_args txq_args
= { 0 };
2197 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2198 txq_args
.opcode
= ac_image_get_resinfo
;
2199 txq_args
.dmask
= 0xf;
2200 txq_args
.addr
= ctx
->i32_0
;
2201 txq_args
.resource
= args
->resource
;
2202 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2204 for (c
= 0; c
< 2; c
++) {
2205 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2206 LLVMConstInt(ctx
->i32
, c
, false), "");
2207 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2208 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2209 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2210 LLVMConstReal(ctx
->f32
, -0.5), "");
2214 LLVMValueRef orig_coords
= args
->addr
;
2216 for (c
= 0; c
< 2; c
++) {
2218 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2219 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2220 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2221 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2222 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2223 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2228 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2229 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2230 * workaround by sampling using a scaled type and converting.
2231 * This is taken from amdgpu-pro shaders.
2233 /* NOTE this produces some ugly code compared to amdgpu-pro,
2234 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2235 * and then reads them back. -pro generates two selects,
2236 * one s_cmp for the descriptor rewriting
2237 * one v_cmp for the coordinate and result changes.
2239 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2240 LLVMValueRef tmp
, tmp2
;
2242 /* workaround 8/8/8/8 uint/sint cube gather bug */
2243 /* first detect it then change to a scaled read and f2i */
2244 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2247 /* extract the DATA_FORMAT */
2248 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2249 LLVMConstInt(ctx
->i32
, 6, false), false);
2251 /* is the DATA_FORMAT == 8_8_8_8 */
2252 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2254 if (stype
== GLSL_TYPE_UINT
)
2255 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2256 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2257 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2259 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2260 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2261 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2263 /* replace the NUM FORMAT in the descriptor */
2264 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2265 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2267 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2269 /* don't modify the coordinates for this case */
2270 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2273 result
= ac_build_image_opcode(ctx
, args
);
2275 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2276 LLVMValueRef tmp
, tmp2
;
2278 /* if the cube workaround is in place, f2i the result. */
2279 for (c
= 0; c
< 4; c
++) {
2280 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2281 if (stype
== GLSL_TYPE_UINT
)
2282 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2284 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2285 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2286 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2287 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2288 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2289 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2295 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2296 const nir_tex_instr
*instr
,
2298 struct ac_image_args
*args
)
2300 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2301 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2303 return ac_build_buffer_load_format(&ctx
->ac
,
2307 util_last_bit(mask
),
2311 args
->opcode
= ac_image_sample
;
2312 args
->compare
= instr
->is_shadow
;
2314 switch (instr
->op
) {
2316 case nir_texop_txf_ms
:
2317 case nir_texop_samples_identical
:
2318 args
->opcode
= lod_is_zero
||
2319 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2320 ac_image_load
: ac_image_load_mip
;
2321 args
->compare
= false;
2322 args
->offset
= false;
2329 args
->level_zero
= true;
2334 case nir_texop_query_levels
:
2335 args
->opcode
= ac_image_get_resinfo
;
2338 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2339 args
->level_zero
= true;
2345 args
->opcode
= ac_image_gather4
;
2346 args
->level_zero
= true;
2349 args
->opcode
= ac_image_get_lod
;
2350 args
->compare
= false;
2351 args
->offset
= false;
2357 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2358 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2359 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2360 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2363 return ac_build_image_opcode(&ctx
->ac
, args
);
2367 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
2368 unsigned desc_set
, unsigned binding
)
2370 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2371 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2372 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2373 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2374 unsigned base_offset
= layout
->binding
[binding
].offset
;
2375 LLVMValueRef offset
, stride
;
2377 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2378 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2379 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2380 layout
->binding
[binding
].dynamic_offset_offset
;
2381 desc_ptr
= ctx
->abi
.push_constants
;
2382 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2383 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2385 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2387 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2388 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, stride
, "");
2389 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, index
, "");
2391 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2392 desc_ptr
= cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
2393 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2398 static LLVMValueRef
visit_vulkan_resource_reindex(struct ac_nir_context
*ctx
,
2399 nir_intrinsic_instr
*instr
)
2401 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2402 LLVMValueRef index
= get_src(ctx
, instr
->src
[1]);
2404 LLVMValueRef result
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
2405 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2409 static LLVMValueRef
visit_load_push_constant(struct ac_nir_context
*ctx
,
2410 nir_intrinsic_instr
*instr
)
2412 LLVMValueRef ptr
, addr
;
2414 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2415 addr
= LLVMBuildAdd(ctx
->ac
.builder
, addr
,
2416 get_src(ctx
, instr
->src
[0]), "");
2418 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->abi
->push_constants
, addr
);
2419 ptr
= cast_ptr(&ctx
->ac
, ptr
, get_def_type(ctx
, &instr
->dest
.ssa
));
2421 return LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "");
2424 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2425 const nir_intrinsic_instr
*instr
)
2427 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2429 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2432 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2434 uint32_t new_mask
= 0;
2435 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2436 if (mask
& (1u << i
))
2437 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2441 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2442 unsigned start
, unsigned count
)
2444 LLVMTypeRef type
= LLVMTypeOf(src
);
2446 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2452 unsigned src_elements
= LLVMGetVectorSize(type
);
2453 assert(start
< src_elements
);
2454 assert(start
+ count
<= src_elements
);
2456 if (start
== 0 && count
== src_elements
)
2460 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2463 LLVMValueRef indices
[8];
2464 for (unsigned i
= 0; i
< count
; ++i
)
2465 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2467 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2468 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2471 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2472 nir_intrinsic_instr
*instr
)
2474 const char *store_name
;
2475 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2476 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2477 int elem_size_mult
= ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2478 int components_32bit
= elem_size_mult
* instr
->num_components
;
2479 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2480 LLVMValueRef base_data
, base_offset
;
2481 LLVMValueRef params
[6];
2483 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2484 get_src(ctx
, instr
->src
[1]), true);
2485 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2486 params
[4] = ctx
->ac
.i1false
; /* glc */
2487 params
[5] = ctx
->ac
.i1false
; /* slc */
2489 if (components_32bit
> 1)
2490 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2492 writemask
= widen_mask(writemask
, elem_size_mult
);
2494 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2495 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2496 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2498 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2502 LLVMValueRef offset
;
2504 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2506 /* Due to an LLVM limitation, split 3-element writes
2507 * into a 2-element and a 1-element write. */
2509 writemask
|= 1 << (start
+ 2);
2514 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2519 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2520 } else if (count
== 2) {
2521 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2525 store_name
= "llvm.amdgcn.buffer.store.f32";
2527 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2529 offset
= base_offset
;
2531 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2535 ac_build_intrinsic(&ctx
->ac
, store_name
,
2536 ctx
->ac
.voidt
, params
, 6, 0);
2540 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2541 const nir_intrinsic_instr
*instr
)
2544 LLVMValueRef params
[6];
2547 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2548 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2550 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2551 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2552 get_src(ctx
, instr
->src
[0]),
2554 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2555 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2556 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2558 switch (instr
->intrinsic
) {
2559 case nir_intrinsic_ssbo_atomic_add
:
2560 name
= "llvm.amdgcn.buffer.atomic.add";
2562 case nir_intrinsic_ssbo_atomic_imin
:
2563 name
= "llvm.amdgcn.buffer.atomic.smin";
2565 case nir_intrinsic_ssbo_atomic_umin
:
2566 name
= "llvm.amdgcn.buffer.atomic.umin";
2568 case nir_intrinsic_ssbo_atomic_imax
:
2569 name
= "llvm.amdgcn.buffer.atomic.smax";
2571 case nir_intrinsic_ssbo_atomic_umax
:
2572 name
= "llvm.amdgcn.buffer.atomic.umax";
2574 case nir_intrinsic_ssbo_atomic_and
:
2575 name
= "llvm.amdgcn.buffer.atomic.and";
2577 case nir_intrinsic_ssbo_atomic_or
:
2578 name
= "llvm.amdgcn.buffer.atomic.or";
2580 case nir_intrinsic_ssbo_atomic_xor
:
2581 name
= "llvm.amdgcn.buffer.atomic.xor";
2583 case nir_intrinsic_ssbo_atomic_exchange
:
2584 name
= "llvm.amdgcn.buffer.atomic.swap";
2586 case nir_intrinsic_ssbo_atomic_comp_swap
:
2587 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2593 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2596 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2597 const nir_intrinsic_instr
*instr
)
2599 LLVMValueRef results
[2];
2600 int load_components
;
2601 int num_components
= instr
->num_components
;
2602 if (instr
->dest
.ssa
.bit_size
== 64)
2603 num_components
*= 2;
2605 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2606 load_components
= MIN2(num_components
- i
, 4);
2607 const char *load_name
;
2608 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2609 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2610 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2612 if (load_components
== 3)
2613 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2614 else if (load_components
> 1)
2615 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2617 if (load_components
>= 3)
2618 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2619 else if (load_components
== 2)
2620 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2621 else if (load_components
== 1)
2622 load_name
= "llvm.amdgcn.buffer.load.f32";
2624 unreachable("unhandled number of components");
2626 LLVMValueRef params
[] = {
2627 ctx
->abi
->load_ssbo(ctx
->abi
,
2628 get_src(ctx
, instr
->src
[0]),
2636 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2640 LLVMValueRef ret
= results
[0];
2641 if (num_components
> 4 || num_components
== 3) {
2642 LLVMValueRef masks
[] = {
2643 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2644 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2645 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2646 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2649 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2650 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2651 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2654 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2655 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2658 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2659 const nir_intrinsic_instr
*instr
)
2662 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2663 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2664 int num_components
= instr
->num_components
;
2666 if (ctx
->abi
->load_ubo
)
2667 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2669 if (instr
->dest
.ssa
.bit_size
== 64)
2670 num_components
*= 2;
2672 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2673 NULL
, 0, false, false, true, true);
2674 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2675 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2676 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2680 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2681 bool vs_in
, unsigned *vertex_index_out
,
2682 LLVMValueRef
*vertex_index_ref
,
2683 unsigned *const_out
, LLVMValueRef
*indir_out
)
2685 unsigned const_offset
= 0;
2686 nir_deref
*tail
= &deref
->deref
;
2687 LLVMValueRef offset
= NULL
;
2689 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2691 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2692 if (vertex_index_out
)
2693 *vertex_index_out
= deref_array
->base_offset
;
2695 if (vertex_index_ref
) {
2696 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2697 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2698 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2700 *vertex_index_ref
= vtx
;
2704 if (deref
->var
->data
.compact
) {
2705 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2706 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2707 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2708 /* We always lower indirect dereferences for "compact" array vars. */
2709 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2711 const_offset
= deref_array
->base_offset
;
2715 while (tail
->child
!= NULL
) {
2716 const struct glsl_type
*parent_type
= tail
->type
;
2719 if (tail
->deref_type
== nir_deref_type_array
) {
2720 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2721 LLVMValueRef index
, stride
, local_offset
;
2722 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2724 const_offset
+= size
* deref_array
->base_offset
;
2725 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2728 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2729 index
= get_src(ctx
, deref_array
->indirect
);
2730 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2731 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2734 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2736 offset
= local_offset
;
2737 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2738 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2740 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2741 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2742 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2745 unreachable("unsupported deref type");
2749 if (const_offset
&& offset
)
2750 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2751 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2754 *const_out
= const_offset
;
2755 *indir_out
= offset
;
2759 /* The offchip buffer layout for TCS->TES is
2761 * - attribute 0 of patch 0 vertex 0
2762 * - attribute 0 of patch 0 vertex 1
2763 * - attribute 0 of patch 0 vertex 2
2765 * - attribute 0 of patch 1 vertex 0
2766 * - attribute 0 of patch 1 vertex 1
2768 * - attribute 1 of patch 0 vertex 0
2769 * - attribute 1 of patch 0 vertex 1
2771 * - per patch attribute 0 of patch 0
2772 * - per patch attribute 0 of patch 1
2775 * Note that every attribute has 4 components.
2777 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
2778 LLVMValueRef vertex_index
,
2779 LLVMValueRef param_index
)
2781 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
;
2782 LLVMValueRef param_stride
, constant16
;
2783 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2785 vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
2786 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2788 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2790 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2791 vertices_per_patch
, "");
2793 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2796 param_stride
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
2799 base_addr
= rel_patch_id
;
2800 param_stride
= num_patches
;
2803 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2804 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
2805 param_stride
, ""), "");
2807 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
2809 if (!vertex_index
) {
2810 LLVMValueRef patch_data_offset
=
2811 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2813 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2814 patch_data_offset
, "");
2819 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
2821 unsigned const_index
,
2823 LLVMValueRef vertex_index
,
2824 LLVMValueRef indir_index
)
2826 LLVMValueRef param_index
;
2829 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2832 if (const_index
&& !is_compact
)
2833 param
+= const_index
;
2834 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2836 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2840 mark_tess_output(struct radv_shader_context
*ctx
,
2841 bool is_patch
, uint32_t param
)
2845 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2847 ctx
->tess_outputs_written
|= (1ull << param
);
2851 get_dw_address(struct radv_shader_context
*ctx
,
2852 LLVMValueRef dw_addr
,
2854 unsigned const_index
,
2855 bool compact_const_index
,
2856 LLVMValueRef vertex_index
,
2857 LLVMValueRef stride
,
2858 LLVMValueRef indir_index
)
2863 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2864 LLVMBuildMul(ctx
->ac
.builder
,
2870 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2871 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
2872 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2873 else if (const_index
&& !compact_const_index
)
2874 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2875 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2877 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2878 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2880 if (const_index
&& compact_const_index
)
2881 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2882 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2887 load_tcs_varyings(struct ac_shader_abi
*abi
,
2889 LLVMValueRef vertex_index
,
2890 LLVMValueRef indir_index
,
2891 unsigned const_index
,
2893 unsigned driver_location
,
2895 unsigned num_components
,
2900 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2901 LLVMValueRef dw_addr
, stride
;
2902 LLVMValueRef value
[4], result
;
2903 unsigned param
= shader_io_get_unique_index(location
);
2906 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2907 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2910 stride
= get_tcs_out_vertex_stride(ctx
);
2911 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2913 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2918 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2921 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2922 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2923 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2926 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2931 store_tcs_output(struct ac_shader_abi
*abi
,
2932 LLVMValueRef vertex_index
,
2933 LLVMValueRef param_index
,
2934 unsigned const_index
,
2936 unsigned driver_location
,
2943 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2944 LLVMValueRef dw_addr
;
2945 LLVMValueRef stride
= NULL
;
2946 LLVMValueRef buf_addr
= NULL
;
2948 bool store_lds
= true;
2951 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2954 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2958 param
= shader_io_get_unique_index(location
);
2959 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2960 is_compact
&& const_index
> 3) {
2966 stride
= get_tcs_out_vertex_stride(ctx
);
2967 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2969 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2972 mark_tess_output(ctx
, is_patch
, param
);
2974 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2976 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2977 vertex_index
, param_index
);
2979 bool is_tess_factor
= false;
2980 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2981 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2982 is_tess_factor
= true;
2984 unsigned base
= is_compact
? const_index
: 0;
2985 for (unsigned chan
= 0; chan
< 8; chan
++) {
2986 if (!(writemask
& (1 << chan
)))
2988 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2990 if (store_lds
|| is_tess_factor
) {
2991 LLVMValueRef dw_addr_chan
=
2992 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2993 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
2994 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
2997 if (!is_tess_factor
&& writemask
!= 0xF)
2998 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2999 buf_addr
, ctx
->oc_lds
,
3000 4 * (base
+ chan
), 1, 0, true, false);
3003 if (writemask
== 0xF) {
3004 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
3005 buf_addr
, ctx
->oc_lds
,
3006 (base
* 4), 1, 0, true, false);
3011 load_tes_input(struct ac_shader_abi
*abi
,
3013 LLVMValueRef vertex_index
,
3014 LLVMValueRef param_index
,
3015 unsigned const_index
,
3017 unsigned driver_location
,
3019 unsigned num_components
,
3024 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3025 LLVMValueRef buf_addr
;
3026 LLVMValueRef result
;
3027 unsigned param
= shader_io_get_unique_index(location
);
3029 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
3034 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
3035 is_compact
, vertex_index
, param_index
);
3037 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
3038 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
3040 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
3041 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
3042 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3047 load_gs_input(struct ac_shader_abi
*abi
,
3049 unsigned driver_location
,
3051 unsigned num_components
,
3052 unsigned vertex_index
,
3053 unsigned const_index
,
3056 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3057 LLVMValueRef vtx_offset
;
3058 unsigned param
, vtx_offset_param
;
3059 LLVMValueRef value
[4], result
;
3061 vtx_offset_param
= vertex_index
;
3062 assert(vtx_offset_param
< 6);
3063 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3064 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3066 param
= shader_io_get_unique_index(location
);
3068 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3069 if (ctx
->ac
.chip_class
>= GFX9
) {
3070 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3071 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3072 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3073 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3075 LLVMValueRef soffset
=
3076 LLVMConstInt(ctx
->ac
.i32
,
3077 (param
* 4 + i
+ const_index
) * 256,
3080 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
3083 vtx_offset
, soffset
,
3084 0, 1, 0, true, false);
3086 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
],
3090 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3091 result
= ac_to_integer(&ctx
->ac
, result
);
3096 build_gep_for_deref(struct ac_nir_context
*ctx
,
3097 nir_deref_var
*deref
)
3099 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3100 assert(entry
->data
);
3101 LLVMValueRef val
= entry
->data
;
3102 nir_deref
*tail
= deref
->deref
.child
;
3103 while (tail
!= NULL
) {
3104 LLVMValueRef offset
;
3105 switch (tail
->deref_type
) {
3106 case nir_deref_type_array
: {
3107 nir_deref_array
*array
= nir_deref_as_array(tail
);
3108 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3109 if (array
->deref_array_type
==
3110 nir_deref_array_type_indirect
) {
3111 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3118 case nir_deref_type_struct
: {
3119 nir_deref_struct
*deref_struct
=
3120 nir_deref_as_struct(tail
);
3121 offset
= LLVMConstInt(ctx
->ac
.i32
,
3122 deref_struct
->index
, 0);
3126 unreachable("bad deref type");
3128 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3134 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3135 nir_intrinsic_instr
*instr
,
3138 LLVMValueRef result
;
3139 LLVMValueRef vertex_index
= NULL
;
3140 LLVMValueRef indir_index
= NULL
;
3141 unsigned const_index
= 0;
3142 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3143 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3144 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3145 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3147 get_deref_offset(ctx
, instr
->variables
[0],
3148 false, NULL
, is_patch
? NULL
: &vertex_index
,
3149 &const_index
, &indir_index
);
3151 LLVMTypeRef dest_type
= get_def_type(ctx
, &instr
->dest
.ssa
);
3153 LLVMTypeRef src_component_type
;
3154 if (LLVMGetTypeKind(dest_type
) == LLVMVectorTypeKind
)
3155 src_component_type
= LLVMGetElementType(dest_type
);
3157 src_component_type
= dest_type
;
3159 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, src_component_type
,
3160 vertex_index
, indir_index
,
3161 const_index
, location
, driver_location
,
3162 instr
->variables
[0]->var
->data
.location_frac
,
3163 instr
->num_components
,
3164 is_patch
, is_compact
, load_inputs
);
3165 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, dest_type
, "");
3168 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3169 nir_intrinsic_instr
*instr
)
3171 LLVMValueRef values
[8];
3172 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3173 int ve
= instr
->dest
.ssa
.num_components
;
3174 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3175 LLVMValueRef indir_index
;
3177 unsigned const_index
;
3178 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3179 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3180 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3181 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3182 &const_index
, &indir_index
);
3184 if (instr
->dest
.ssa
.bit_size
== 64)
3187 switch (instr
->variables
[0]->var
->data
.mode
) {
3188 case nir_var_shader_in
:
3189 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3190 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3191 return load_tess_varyings(ctx
, instr
, true);
3194 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3195 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3196 LLVMValueRef indir_index
;
3197 unsigned const_index
, vertex_index
;
3198 get_deref_offset(ctx
, instr
->variables
[0],
3199 false, &vertex_index
, NULL
,
3200 &const_index
, &indir_index
);
3202 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3203 instr
->variables
[0]->var
->data
.driver_location
,
3204 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3205 vertex_index
, const_index
, type
);
3208 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3210 unsigned count
= glsl_count_attribute_slots(
3211 instr
->variables
[0]->var
->type
,
3212 ctx
->stage
== MESA_SHADER_VERTEX
);
3214 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3215 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3216 stride
, false, true);
3218 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3222 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3226 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3228 unsigned count
= glsl_count_attribute_slots(
3229 instr
->variables
[0]->var
->type
, false);
3231 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3232 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3233 stride
, true, true);
3235 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3239 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3243 case nir_var_shared
: {
3244 LLVMValueRef address
= build_gep_for_deref(ctx
,
3245 instr
->variables
[0]);
3246 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3247 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3248 get_def_type(ctx
, &instr
->dest
.ssa
),
3251 case nir_var_shader_out
:
3252 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3253 return load_tess_varyings(ctx
, instr
, false);
3256 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3258 unsigned count
= glsl_count_attribute_slots(
3259 instr
->variables
[0]->var
->type
, false);
3261 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3262 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3263 stride
, true, true);
3265 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3269 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3270 ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
],
3276 unreachable("unhandle variable mode");
3278 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3279 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3283 visit_store_var(struct ac_nir_context
*ctx
,
3284 nir_intrinsic_instr
*instr
)
3286 LLVMValueRef temp_ptr
, value
;
3287 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3288 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3289 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3290 int writemask
= instr
->const_index
[0] << comp
;
3291 LLVMValueRef indir_index
;
3292 unsigned const_index
;
3293 get_deref_offset(ctx
, instr
->variables
[0], false,
3294 NULL
, NULL
, &const_index
, &indir_index
);
3296 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3298 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3299 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3302 writemask
= widen_mask(writemask
, 2);
3305 switch (instr
->variables
[0]->var
->data
.mode
) {
3306 case nir_var_shader_out
:
3308 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3309 LLVMValueRef vertex_index
= NULL
;
3310 LLVMValueRef indir_index
= NULL
;
3311 unsigned const_index
= 0;
3312 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3313 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3314 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3315 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3316 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3318 get_deref_offset(ctx
, instr
->variables
[0],
3319 false, NULL
, is_patch
? NULL
: &vertex_index
,
3320 &const_index
, &indir_index
);
3322 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3323 const_index
, location
, driver_location
,
3324 src
, comp
, is_patch
, is_compact
, writemask
);
3328 for (unsigned chan
= 0; chan
< 8; chan
++) {
3330 if (!(writemask
& (1 << chan
)))
3333 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3335 if (instr
->variables
[0]->var
->data
.compact
)
3338 unsigned count
= glsl_count_attribute_slots(
3339 instr
->variables
[0]->var
->type
, false);
3341 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3342 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3343 stride
, true, true);
3345 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3346 value
, indir_index
, "");
3347 build_store_values_extended(&ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
,
3348 count
, stride
, tmp_vec
);
3351 temp_ptr
= ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
];
3353 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3358 for (unsigned chan
= 0; chan
< 8; chan
++) {
3359 if (!(writemask
& (1 << chan
)))
3362 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3364 unsigned count
= glsl_count_attribute_slots(
3365 instr
->variables
[0]->var
->type
, false);
3367 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3368 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3371 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3372 value
, indir_index
, "");
3373 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3376 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3378 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3382 case nir_var_shared
: {
3383 int writemask
= instr
->const_index
[0];
3384 LLVMValueRef address
= build_gep_for_deref(ctx
,
3385 instr
->variables
[0]);
3386 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3387 unsigned components
=
3388 glsl_get_vector_elements(
3389 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3390 if (writemask
== (1 << components
) - 1) {
3391 val
= LLVMBuildBitCast(
3392 ctx
->ac
.builder
, val
,
3393 LLVMGetElementType(LLVMTypeOf(address
)), "");
3394 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3396 for (unsigned chan
= 0; chan
< 4; chan
++) {
3397 if (!(writemask
& (1 << chan
)))
3400 LLVMBuildStructGEP(ctx
->ac
.builder
,
3402 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3404 src
= LLVMBuildBitCast(
3405 ctx
->ac
.builder
, src
,
3406 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3407 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3417 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3420 case GLSL_SAMPLER_DIM_BUF
:
3422 case GLSL_SAMPLER_DIM_1D
:
3423 return array
? 2 : 1;
3424 case GLSL_SAMPLER_DIM_2D
:
3425 return array
? 3 : 2;
3426 case GLSL_SAMPLER_DIM_MS
:
3427 return array
? 4 : 3;
3428 case GLSL_SAMPLER_DIM_3D
:
3429 case GLSL_SAMPLER_DIM_CUBE
:
3431 case GLSL_SAMPLER_DIM_RECT
:
3432 case GLSL_SAMPLER_DIM_SUBPASS
:
3434 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3443 glsl_is_array_image(const struct glsl_type
*type
)
3445 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3447 if (glsl_sampler_type_is_array(type
))
3450 return dim
== GLSL_SAMPLER_DIM_CUBE
||
3451 dim
== GLSL_SAMPLER_DIM_3D
||
3452 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3453 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3457 /* Adjust the sample index according to FMASK.
3459 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3460 * which is the identity mapping. Each nibble says which physical sample
3461 * should be fetched to get that sample.
3463 * For example, 0x11111100 means there are only 2 samples stored and
3464 * the second sample covers 3/4 of the pixel. When reading samples 0
3465 * and 1, return physical sample 0 (determined by the first two 0s
3466 * in FMASK), otherwise return physical sample 1.
3468 * The sample index should be adjusted as follows:
3469 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3471 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3472 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3473 LLVMValueRef coord_z
,
3474 LLVMValueRef sample_index
,
3475 LLVMValueRef fmask_desc_ptr
)
3477 LLVMValueRef fmask_load_address
[4];
3480 fmask_load_address
[0] = coord_x
;
3481 fmask_load_address
[1] = coord_y
;
3483 fmask_load_address
[2] = coord_z
;
3484 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3487 struct ac_image_args args
= {0};
3489 args
.opcode
= ac_image_load
;
3490 args
.da
= coord_z
? true : false;
3491 args
.resource
= fmask_desc_ptr
;
3493 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3495 res
= ac_build_image_opcode(ctx
, &args
);
3497 res
= ac_to_integer(ctx
, res
);
3498 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3499 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3501 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3505 LLVMValueRef sample_index4
=
3506 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3507 LLVMValueRef shifted_fmask
=
3508 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3509 LLVMValueRef final_sample
=
3510 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3512 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3513 * resource descriptor is 0 (invalid),
3515 LLVMValueRef fmask_desc
=
3516 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3519 LLVMValueRef fmask_word1
=
3520 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3523 LLVMValueRef word1_is_nonzero
=
3524 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3525 fmask_word1
, ctx
->i32_0
, "");
3527 /* Replace the MSAA sample index. */
3529 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3530 final_sample
, sample_index
, "");
3531 return sample_index
;
3534 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3535 const nir_intrinsic_instr
*instr
)
3537 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3539 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3540 LLVMValueRef coords
[4];
3541 LLVMValueRef masks
[] = {
3542 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3543 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3546 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3549 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3550 bool is_array
= glsl_sampler_type_is_array(type
);
3551 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3552 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3553 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3554 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3555 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3556 count
= image_type_to_components_count(dim
, is_array
);
3559 LLVMValueRef fmask_load_address
[3];
3562 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3563 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3565 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3567 fmask_load_address
[2] = NULL
;
3569 for (chan
= 0; chan
< 2; ++chan
)
3570 fmask_load_address
[chan
] =
3571 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3572 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3573 ctx
->ac
.i32
, ""), "");
3574 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3576 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3577 fmask_load_address
[0],
3578 fmask_load_address
[1],
3579 fmask_load_address
[2],
3581 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3583 if (count
== 1 && !gfx9_1d
) {
3584 if (instr
->src
[0].ssa
->num_components
)
3585 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3592 for (chan
= 0; chan
< count
; ++chan
) {
3593 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3596 for (chan
= 0; chan
< 2; ++chan
)
3597 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3598 ctx
->ac
.i32
, ""), "");
3599 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3605 coords
[2] = coords
[1];
3606 coords
[1] = ctx
->ac
.i32_0
;
3608 coords
[1] = ctx
->ac
.i32_0
;
3613 coords
[count
] = sample_index
;
3618 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3621 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3626 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3627 const nir_intrinsic_instr
*instr
)
3629 LLVMValueRef params
[7];
3631 char intrinsic_name
[64];
3632 const nir_variable
*var
= instr
->variables
[0]->var
;
3633 const struct glsl_type
*type
= var
->type
;
3635 if(instr
->variables
[0]->deref
.child
)
3636 type
= instr
->variables
[0]->deref
.child
->type
;
3638 type
= glsl_without_array(type
);
3640 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3641 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3642 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
3643 unsigned num_channels
= util_last_bit(mask
);
3644 LLVMValueRef rsrc
, vindex
;
3646 rsrc
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3647 vindex
= LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3650 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3651 res
= ac_build_buffer_load_format(&ctx
->ac
, rsrc
, vindex
,
3652 ctx
->ac
.i32_0
, num_channels
,
3654 res
= ac_build_expand_to_vec4(&ctx
->ac
, res
, num_channels
);
3656 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3657 res
= ac_to_integer(&ctx
->ac
, res
);
3659 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3660 LLVMValueRef slc
= ctx
->ac
.i1false
;
3662 params
[0] = get_image_coords(ctx
, instr
);
3663 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3664 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3665 params
[3] = (var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3666 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3668 params
[5] = ctx
->ac
.i1false
;
3671 ac_get_image_intr_name("llvm.amdgcn.image.load",
3672 ctx
->ac
.v4f32
, /* vdata */
3673 LLVMTypeOf(params
[0]), /* coords */
3674 LLVMTypeOf(params
[1]), /* rsrc */
3675 intrinsic_name
, sizeof(intrinsic_name
));
3677 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3678 params
, 7, AC_FUNC_ATTR_READONLY
);
3680 return ac_to_integer(&ctx
->ac
, res
);
3683 static void visit_image_store(struct ac_nir_context
*ctx
,
3684 nir_intrinsic_instr
*instr
)
3686 LLVMValueRef params
[8];
3687 char intrinsic_name
[64];
3688 const nir_variable
*var
= instr
->variables
[0]->var
;
3689 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3690 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3691 LLVMValueRef glc
= ctx
->ac
.i1false
;
3692 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3694 glc
= ctx
->ac
.i1true
;
3696 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3697 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3698 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3699 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3700 ctx
->ac
.i32_0
, ""); /* vindex */
3701 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3702 params
[4] = glc
; /* glc */
3703 params
[5] = ctx
->ac
.i1false
; /* slc */
3704 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3707 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3708 LLVMValueRef slc
= ctx
->ac
.i1false
;
3710 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3711 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3712 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3713 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3714 params
[4] = (force_glc
|| var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3715 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3717 params
[6] = ctx
->ac
.i1false
;
3720 ac_get_image_intr_name("llvm.amdgcn.image.store",
3721 LLVMTypeOf(params
[0]), /* vdata */
3722 LLVMTypeOf(params
[1]), /* coords */
3723 LLVMTypeOf(params
[2]), /* rsrc */
3724 intrinsic_name
, sizeof(intrinsic_name
));
3726 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3732 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3733 const nir_intrinsic_instr
*instr
)
3735 LLVMValueRef params
[7];
3736 int param_count
= 0;
3737 const nir_variable
*var
= instr
->variables
[0]->var
;
3739 const char *atomic_name
;
3740 char intrinsic_name
[41];
3741 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3742 MAYBE_UNUSED
int length
;
3744 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3746 switch (instr
->intrinsic
) {
3747 case nir_intrinsic_image_atomic_add
:
3748 atomic_name
= "add";
3750 case nir_intrinsic_image_atomic_min
:
3751 atomic_name
= is_unsigned
? "umin" : "smin";
3753 case nir_intrinsic_image_atomic_max
:
3754 atomic_name
= is_unsigned
? "umax" : "smax";
3756 case nir_intrinsic_image_atomic_and
:
3757 atomic_name
= "and";
3759 case nir_intrinsic_image_atomic_or
:
3762 case nir_intrinsic_image_atomic_xor
:
3763 atomic_name
= "xor";
3765 case nir_intrinsic_image_atomic_exchange
:
3766 atomic_name
= "swap";
3768 case nir_intrinsic_image_atomic_comp_swap
:
3769 atomic_name
= "cmpswap";
3775 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3776 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3777 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3779 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3780 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3782 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3783 ctx
->ac
.i32_0
, ""); /* vindex */
3784 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3785 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3787 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3788 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3790 char coords_type
[8];
3792 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3793 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3795 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3796 params
[param_count
++] = glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3797 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3799 build_int_type_name(LLVMTypeOf(coords
),
3800 coords_type
, sizeof(coords_type
));
3802 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3803 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3806 assert(length
< sizeof(intrinsic_name
));
3807 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3810 static LLVMValueRef
visit_image_samples(struct ac_nir_context
*ctx
,
3811 const nir_intrinsic_instr
*instr
)
3813 const nir_variable
*var
= instr
->variables
[0]->var
;
3814 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3816 struct ac_image_args args
= { 0 };
3817 args
.da
= glsl_is_array_image(type
);
3819 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0],
3820 AC_DESC_IMAGE
, NULL
, true, false);
3821 args
.opcode
= ac_image_get_resinfo
;
3822 args
.addr
= ctx
->ac
.i32_0
;
3824 return ac_build_image_opcode(&ctx
->ac
, &args
);
3827 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3828 const nir_intrinsic_instr
*instr
)
3831 const nir_variable
*var
= instr
->variables
[0]->var
;
3832 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3834 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3835 return get_buffer_size(ctx
,
3836 get_sampler_desc(ctx
, instr
->variables
[0],
3837 AC_DESC_BUFFER
, NULL
, true, false), true);
3839 struct ac_image_args args
= { 0 };
3841 args
.da
= glsl_is_array_image(type
);
3843 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3844 args
.opcode
= ac_image_get_resinfo
;
3845 args
.addr
= ctx
->ac
.i32_0
;
3847 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3849 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3851 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3852 glsl_sampler_type_is_array(type
)) {
3853 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3854 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3855 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3856 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3858 if (ctx
->ac
.chip_class
>= GFX9
&&
3859 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3860 glsl_sampler_type_is_array(type
)) {
3861 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3862 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3869 #define NOOP_WAITCNT 0xf7f
3870 #define LGKM_CNT 0x07f
3871 #define VM_CNT 0xf70
3873 static void emit_membar(struct ac_llvm_context
*ac
,
3874 const nir_intrinsic_instr
*instr
)
3876 unsigned waitcnt
= NOOP_WAITCNT
;
3878 switch (instr
->intrinsic
) {
3879 case nir_intrinsic_memory_barrier
:
3880 case nir_intrinsic_group_memory_barrier
:
3881 waitcnt
&= VM_CNT
& LGKM_CNT
;
3883 case nir_intrinsic_memory_barrier_atomic_counter
:
3884 case nir_intrinsic_memory_barrier_buffer
:
3885 case nir_intrinsic_memory_barrier_image
:
3888 case nir_intrinsic_memory_barrier_shared
:
3889 waitcnt
&= LGKM_CNT
;
3894 if (waitcnt
!= NOOP_WAITCNT
)
3895 ac_build_waitcnt(ac
, waitcnt
);
3898 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3900 /* SI only (thanks to a hw bug workaround):
3901 * The real barrier instruction isn’t needed, because an entire patch
3902 * always fits into a single wave.
3904 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3905 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3908 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3909 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3912 static void emit_discard(struct ac_nir_context
*ctx
,
3913 const nir_intrinsic_instr
*instr
)
3917 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3918 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3919 get_src(ctx
, instr
->src
[0]),
3922 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3923 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3926 ac_build_kill_if_false(&ctx
->ac
, cond
);
3930 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3932 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3933 "llvm.amdgcn.ps.live",
3934 ctx
->ac
.i1
, NULL
, 0,
3935 AC_FUNC_ATTR_READNONE
);
3936 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3937 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3941 visit_load_local_invocation_index(struct ac_nir_context
*ctx
)
3943 LLVMValueRef result
;
3944 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3945 result
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3946 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3948 return LLVMBuildAdd(ctx
->ac
.builder
, result
, thread_id
, "");
3952 visit_load_shared(struct ac_nir_context
*ctx
,
3953 const nir_intrinsic_instr
*instr
)
3955 LLVMValueRef values
[4], derived_ptr
, index
, ret
;
3957 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
3959 for (int chan
= 0; chan
< instr
->num_components
; chan
++) {
3960 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3961 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
3962 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
3965 ret
= ac_build_gather_values(&ctx
->ac
, values
, instr
->num_components
);
3966 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3970 visit_store_shared(struct ac_nir_context
*ctx
,
3971 const nir_intrinsic_instr
*instr
)
3973 LLVMValueRef derived_ptr
, data
,index
;
3974 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3976 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[1]);
3977 LLVMValueRef src
= get_src(ctx
, instr
->src
[0]);
3979 int writemask
= nir_intrinsic_write_mask(instr
);
3980 for (int chan
= 0; chan
< 4; chan
++) {
3981 if (!(writemask
& (1 << chan
))) {
3984 data
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3985 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3986 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3987 LLVMBuildStore(builder
, data
, derived_ptr
);
3991 static LLVMValueRef
visit_var_atomic(struct ac_nir_context
*ctx
,
3992 const nir_intrinsic_instr
*instr
,
3995 LLVMValueRef result
;
3996 LLVMValueRef src
= get_src(ctx
, instr
->src
[0]);
3998 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
||
3999 instr
->intrinsic
== nir_intrinsic_shared_atomic_comp_swap
) {
4000 LLVMValueRef src1
= get_src(ctx
, instr
->src
[1]);
4001 result
= LLVMBuildAtomicCmpXchg(ctx
->ac
.builder
,
4003 LLVMAtomicOrderingSequentiallyConsistent
,
4004 LLVMAtomicOrderingSequentiallyConsistent
,
4007 LLVMAtomicRMWBinOp op
;
4008 switch (instr
->intrinsic
) {
4009 case nir_intrinsic_var_atomic_add
:
4010 case nir_intrinsic_shared_atomic_add
:
4011 op
= LLVMAtomicRMWBinOpAdd
;
4013 case nir_intrinsic_var_atomic_umin
:
4014 case nir_intrinsic_shared_atomic_umin
:
4015 op
= LLVMAtomicRMWBinOpUMin
;
4017 case nir_intrinsic_var_atomic_umax
:
4018 case nir_intrinsic_shared_atomic_umax
:
4019 op
= LLVMAtomicRMWBinOpUMax
;
4021 case nir_intrinsic_var_atomic_imin
:
4022 case nir_intrinsic_shared_atomic_imin
:
4023 op
= LLVMAtomicRMWBinOpMin
;
4025 case nir_intrinsic_var_atomic_imax
:
4026 case nir_intrinsic_shared_atomic_imax
:
4027 op
= LLVMAtomicRMWBinOpMax
;
4029 case nir_intrinsic_var_atomic_and
:
4030 case nir_intrinsic_shared_atomic_and
:
4031 op
= LLVMAtomicRMWBinOpAnd
;
4033 case nir_intrinsic_var_atomic_or
:
4034 case nir_intrinsic_shared_atomic_or
:
4035 op
= LLVMAtomicRMWBinOpOr
;
4037 case nir_intrinsic_var_atomic_xor
:
4038 case nir_intrinsic_shared_atomic_xor
:
4039 op
= LLVMAtomicRMWBinOpXor
;
4041 case nir_intrinsic_var_atomic_exchange
:
4042 case nir_intrinsic_shared_atomic_exchange
:
4043 op
= LLVMAtomicRMWBinOpXchg
;
4049 result
= LLVMBuildAtomicRMW(ctx
->ac
.builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
4050 LLVMAtomicOrderingSequentiallyConsistent
,
4056 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
4057 enum glsl_interp_mode interp
, unsigned location
)
4059 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4062 case INTERP_MODE_FLAT
:
4065 case INTERP_MODE_SMOOTH
:
4066 case INTERP_MODE_NONE
:
4067 if (location
== INTERP_CENTER
)
4068 return ctx
->persp_center
;
4069 else if (location
== INTERP_CENTROID
)
4070 return ctx
->persp_centroid
;
4071 else if (location
== INTERP_SAMPLE
)
4072 return ctx
->persp_sample
;
4074 case INTERP_MODE_NOPERSPECTIVE
:
4075 if (location
== INTERP_CENTER
)
4076 return ctx
->linear_center
;
4077 else if (location
== INTERP_CENTROID
)
4078 return ctx
->linear_centroid
;
4079 else if (location
== INTERP_SAMPLE
)
4080 return ctx
->linear_sample
;
4086 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
4087 LLVMValueRef sample_id
)
4089 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4091 LLVMValueRef result
;
4092 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4094 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
4095 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4097 sample_id
= LLVMBuildAdd(ctx
->ac
.builder
, sample_id
, ctx
->sample_pos_offset
, "");
4098 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4103 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4105 LLVMValueRef values
[2];
4107 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0], 32);
4108 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1], 32);
4109 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4112 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
4114 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4115 uint8_t log2_ps_iter_samples
= ctx
->shader_info
->info
.ps
.force_persample
?
4116 ctx
->options
->key
.fs
.log2_num_samples
:
4117 ctx
->options
->key
.fs
.log2_ps_iter_samples
;
4119 /* The bit pattern matches that used by fixed function fragment
4121 static const uint16_t ps_iter_masks
[] = {
4122 0xffff, /* not used */
4128 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4130 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4132 LLVMValueRef result
, sample_id
;
4133 sample_id
= unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
4134 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4135 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
4139 static LLVMValueRef
visit_interp(struct ac_nir_context
*ctx
,
4140 const nir_intrinsic_instr
*instr
)
4142 LLVMValueRef result
[4];
4143 LLVMValueRef interp_param
, attr_number
;
4146 LLVMValueRef src_c0
= NULL
;
4147 LLVMValueRef src_c1
= NULL
;
4148 LLVMValueRef src0
= NULL
;
4149 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4150 switch (instr
->intrinsic
) {
4151 case nir_intrinsic_interp_var_at_centroid
:
4152 location
= INTERP_CENTROID
;
4154 case nir_intrinsic_interp_var_at_sample
:
4155 case nir_intrinsic_interp_var_at_offset
:
4156 location
= INTERP_CENTER
;
4157 src0
= get_src(ctx
, instr
->src
[0]);
4163 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4164 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_0
, ""));
4165 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_1
, ""));
4166 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4167 LLVMValueRef sample_position
;
4168 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4170 /* fetch sample ID */
4171 sample_position
= ctx
->abi
->load_sample_position(ctx
->abi
, src0
);
4173 src_c0
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_0
, "");
4174 src_c0
= LLVMBuildFSub(ctx
->ac
.builder
, src_c0
, halfval
, "");
4175 src_c1
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_1
, "");
4176 src_c1
= LLVMBuildFSub(ctx
->ac
.builder
, src_c1
, halfval
, "");
4178 interp_param
= ctx
->abi
->lookup_interp_param(ctx
->abi
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4179 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4181 if (location
== INTERP_CENTER
) {
4182 LLVMValueRef ij_out
[2];
4183 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
4186 * take the I then J parameters, and the DDX/Y for it, and
4187 * calculate the IJ inputs for the interpolator.
4188 * temp1 = ddx * offset/sample.x + I;
4189 * interp_param.I = ddy * offset/sample.y + temp1;
4190 * temp1 = ddx * offset/sample.x + J;
4191 * interp_param.J = ddy * offset/sample.y + temp1;
4193 for (unsigned i
= 0; i
< 2; i
++) {
4194 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4195 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4196 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4197 ddxy_out
, ix_ll
, "");
4198 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4199 ddxy_out
, iy_ll
, "");
4200 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4201 interp_param
, ix_ll
, "");
4202 LLVMValueRef temp1
, temp2
;
4204 interp_el
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_el
,
4207 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, src_c0
, "");
4208 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4210 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, src_c1
, "");
4211 temp2
= LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4213 ij_out
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4214 temp2
, ctx
->ac
.i32
, "");
4216 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4220 for (chan
= 0; chan
< 4; chan
++) {
4221 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4224 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
,
4225 interp_param
, ctx
->ac
.v2f32
, "");
4226 LLVMValueRef i
= LLVMBuildExtractElement(
4227 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_0
, "");
4228 LLVMValueRef j
= LLVMBuildExtractElement(
4229 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_1
, "");
4231 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4232 llvm_chan
, attr_number
,
4233 ctx
->abi
->prim_mask
, i
, j
);
4235 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4236 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4237 llvm_chan
, attr_number
,
4238 ctx
->abi
->prim_mask
);
4241 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4242 instr
->variables
[0]->var
->data
.location_frac
);
4246 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4248 LLVMValueRef gs_next_vertex
;
4249 LLVMValueRef can_emit
;
4251 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4253 assert(stream
== 0);
4255 /* Write vertex attribute values to GSVS ring */
4256 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4257 ctx
->gs_next_vertex
,
4260 /* If this thread has already emitted the declared maximum number of
4261 * vertices, kill it: excessive vertex emissions are not supposed to
4262 * have any effect, and GS threads have no externally observable
4263 * effects other than emitting vertices.
4265 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4266 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4267 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4269 /* loop num outputs */
4271 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4272 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4277 if (!(ctx
->output_mask
& (1ull << i
)))
4280 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4281 /* pack clip and cull into a single set of slots */
4282 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4286 for (unsigned j
= 0; j
< length
; j
++) {
4287 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
4289 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4290 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4291 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4293 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
4295 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4297 voffset
, ctx
->gs2vs_offset
, 0,
4303 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
4305 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4307 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4311 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4313 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4314 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4318 load_tess_coord(struct ac_shader_abi
*abi
)
4320 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4322 LLVMValueRef coord
[4] = {
4329 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4330 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
4331 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
4333 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
4337 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4339 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4340 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4343 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4344 nir_intrinsic_instr
*instr
)
4346 LLVMValueRef result
= NULL
;
4348 switch (instr
->intrinsic
) {
4349 case nir_intrinsic_ballot
:
4350 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4352 case nir_intrinsic_read_invocation
:
4353 case nir_intrinsic_read_first_invocation
: {
4354 LLVMValueRef args
[2];
4357 args
[0] = get_src(ctx
, instr
->src
[0]);
4360 const char *intr_name
;
4361 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4363 intr_name
= "llvm.amdgcn.readlane";
4366 args
[1] = get_src(ctx
, instr
->src
[1]);
4369 intr_name
= "llvm.amdgcn.readfirstlane";
4372 /* We currently have no other way to prevent LLVM from lifting the icmp
4373 * calls to a dominating basic block.
4375 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4377 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4378 ctx
->ac
.i32
, args
, num_args
,
4379 AC_FUNC_ATTR_READNONE
|
4380 AC_FUNC_ATTR_CONVERGENT
);
4383 case nir_intrinsic_load_subgroup_invocation
:
4384 result
= ac_get_thread_id(&ctx
->ac
);
4386 case nir_intrinsic_load_work_group_id
: {
4387 LLVMValueRef values
[3];
4389 for (int i
= 0; i
< 3; i
++) {
4390 values
[i
] = ctx
->abi
->workgroup_ids
[i
] ?
4391 ctx
->abi
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4394 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4397 case nir_intrinsic_load_base_vertex
: {
4398 result
= ctx
->abi
->base_vertex
;
4401 case nir_intrinsic_load_local_group_size
:
4402 result
= ctx
->abi
->load_local_group_size(ctx
->abi
);
4404 case nir_intrinsic_load_vertex_id_zero_base
: {
4405 result
= ctx
->abi
->vertex_id
;
4408 case nir_intrinsic_load_local_invocation_id
: {
4409 result
= ctx
->abi
->local_invocation_ids
;
4412 case nir_intrinsic_load_base_instance
:
4413 result
= ctx
->abi
->start_instance
;
4415 case nir_intrinsic_load_draw_id
:
4416 result
= ctx
->abi
->draw_id
;
4418 case nir_intrinsic_load_view_index
:
4419 result
= ctx
->abi
->view_index
;
4421 case nir_intrinsic_load_invocation_id
:
4422 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4423 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4425 result
= ctx
->abi
->gs_invocation_id
;
4427 case nir_intrinsic_load_primitive_id
:
4428 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4429 result
= ctx
->abi
->gs_prim_id
;
4430 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4431 result
= ctx
->abi
->tcs_patch_id
;
4432 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4433 result
= ctx
->abi
->tes_patch_id
;
4435 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4437 case nir_intrinsic_load_sample_id
:
4438 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4440 case nir_intrinsic_load_sample_pos
:
4441 result
= load_sample_pos(ctx
);
4443 case nir_intrinsic_load_sample_mask_in
:
4444 result
= ctx
->abi
->load_sample_mask_in(ctx
->abi
);
4446 case nir_intrinsic_load_frag_coord
: {
4447 LLVMValueRef values
[4] = {
4448 ctx
->abi
->frag_pos
[0],
4449 ctx
->abi
->frag_pos
[1],
4450 ctx
->abi
->frag_pos
[2],
4451 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4453 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4456 case nir_intrinsic_load_front_face
:
4457 result
= ctx
->abi
->front_face
;
4459 case nir_intrinsic_load_helper_invocation
:
4460 result
= visit_load_helper_invocation(ctx
);
4462 case nir_intrinsic_load_instance_id
:
4463 result
= ctx
->abi
->instance_id
;
4465 case nir_intrinsic_load_num_work_groups
:
4466 result
= ctx
->abi
->num_work_groups
;
4468 case nir_intrinsic_load_local_invocation_index
:
4469 result
= visit_load_local_invocation_index(ctx
);
4471 case nir_intrinsic_load_push_constant
:
4472 result
= visit_load_push_constant(ctx
, instr
);
4474 case nir_intrinsic_vulkan_resource_index
: {
4475 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
4476 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4477 unsigned binding
= nir_intrinsic_binding(instr
);
4479 result
= ctx
->abi
->load_resource(ctx
->abi
, index
, desc_set
,
4483 case nir_intrinsic_vulkan_resource_reindex
:
4484 result
= visit_vulkan_resource_reindex(ctx
, instr
);
4486 case nir_intrinsic_store_ssbo
:
4487 visit_store_ssbo(ctx
, instr
);
4489 case nir_intrinsic_load_ssbo
:
4490 result
= visit_load_buffer(ctx
, instr
);
4492 case nir_intrinsic_ssbo_atomic_add
:
4493 case nir_intrinsic_ssbo_atomic_imin
:
4494 case nir_intrinsic_ssbo_atomic_umin
:
4495 case nir_intrinsic_ssbo_atomic_imax
:
4496 case nir_intrinsic_ssbo_atomic_umax
:
4497 case nir_intrinsic_ssbo_atomic_and
:
4498 case nir_intrinsic_ssbo_atomic_or
:
4499 case nir_intrinsic_ssbo_atomic_xor
:
4500 case nir_intrinsic_ssbo_atomic_exchange
:
4501 case nir_intrinsic_ssbo_atomic_comp_swap
:
4502 result
= visit_atomic_ssbo(ctx
, instr
);
4504 case nir_intrinsic_load_ubo
:
4505 result
= visit_load_ubo_buffer(ctx
, instr
);
4507 case nir_intrinsic_get_buffer_size
:
4508 result
= visit_get_buffer_size(ctx
, instr
);
4510 case nir_intrinsic_load_var
:
4511 result
= visit_load_var(ctx
, instr
);
4513 case nir_intrinsic_store_var
:
4514 visit_store_var(ctx
, instr
);
4516 case nir_intrinsic_load_shared
:
4517 result
= visit_load_shared(ctx
, instr
);
4519 case nir_intrinsic_store_shared
:
4520 visit_store_shared(ctx
, instr
);
4522 case nir_intrinsic_image_samples
:
4523 result
= visit_image_samples(ctx
, instr
);
4525 case nir_intrinsic_image_load
:
4526 result
= visit_image_load(ctx
, instr
);
4528 case nir_intrinsic_image_store
:
4529 visit_image_store(ctx
, instr
);
4531 case nir_intrinsic_image_atomic_add
:
4532 case nir_intrinsic_image_atomic_min
:
4533 case nir_intrinsic_image_atomic_max
:
4534 case nir_intrinsic_image_atomic_and
:
4535 case nir_intrinsic_image_atomic_or
:
4536 case nir_intrinsic_image_atomic_xor
:
4537 case nir_intrinsic_image_atomic_exchange
:
4538 case nir_intrinsic_image_atomic_comp_swap
:
4539 result
= visit_image_atomic(ctx
, instr
);
4541 case nir_intrinsic_image_size
:
4542 result
= visit_image_size(ctx
, instr
);
4544 case nir_intrinsic_shader_clock
:
4545 result
= ac_build_shader_clock(&ctx
->ac
);
4547 case nir_intrinsic_discard
:
4548 case nir_intrinsic_discard_if
:
4549 emit_discard(ctx
, instr
);
4551 case nir_intrinsic_memory_barrier
:
4552 case nir_intrinsic_group_memory_barrier
:
4553 case nir_intrinsic_memory_barrier_atomic_counter
:
4554 case nir_intrinsic_memory_barrier_buffer
:
4555 case nir_intrinsic_memory_barrier_image
:
4556 case nir_intrinsic_memory_barrier_shared
:
4557 emit_membar(&ctx
->ac
, instr
);
4559 case nir_intrinsic_barrier
:
4560 emit_barrier(&ctx
->ac
, ctx
->stage
);
4562 case nir_intrinsic_shared_atomic_add
:
4563 case nir_intrinsic_shared_atomic_imin
:
4564 case nir_intrinsic_shared_atomic_umin
:
4565 case nir_intrinsic_shared_atomic_imax
:
4566 case nir_intrinsic_shared_atomic_umax
:
4567 case nir_intrinsic_shared_atomic_and
:
4568 case nir_intrinsic_shared_atomic_or
:
4569 case nir_intrinsic_shared_atomic_xor
:
4570 case nir_intrinsic_shared_atomic_exchange
:
4571 case nir_intrinsic_shared_atomic_comp_swap
: {
4572 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[1]);
4573 result
= visit_var_atomic(ctx
, instr
, ptr
);
4576 case nir_intrinsic_var_atomic_add
:
4577 case nir_intrinsic_var_atomic_imin
:
4578 case nir_intrinsic_var_atomic_umin
:
4579 case nir_intrinsic_var_atomic_imax
:
4580 case nir_intrinsic_var_atomic_umax
:
4581 case nir_intrinsic_var_atomic_and
:
4582 case nir_intrinsic_var_atomic_or
:
4583 case nir_intrinsic_var_atomic_xor
:
4584 case nir_intrinsic_var_atomic_exchange
:
4585 case nir_intrinsic_var_atomic_comp_swap
: {
4586 LLVMValueRef ptr
= build_gep_for_deref(ctx
, instr
->variables
[0]);
4587 result
= visit_var_atomic(ctx
, instr
, ptr
);
4590 case nir_intrinsic_interp_var_at_centroid
:
4591 case nir_intrinsic_interp_var_at_sample
:
4592 case nir_intrinsic_interp_var_at_offset
:
4593 result
= visit_interp(ctx
, instr
);
4595 case nir_intrinsic_emit_vertex
:
4596 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->abi
->outputs
);
4598 case nir_intrinsic_end_primitive
:
4599 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4601 case nir_intrinsic_load_tess_coord
:
4602 result
= ctx
->abi
->load_tess_coord(ctx
->abi
);
4604 case nir_intrinsic_load_tess_level_outer
:
4605 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4607 case nir_intrinsic_load_tess_level_inner
:
4608 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4610 case nir_intrinsic_load_patch_vertices_in
:
4611 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4613 case nir_intrinsic_vote_all
: {
4614 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4615 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4618 case nir_intrinsic_vote_any
: {
4619 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4620 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4623 case nir_intrinsic_vote_eq
: {
4624 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4625 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4629 fprintf(stderr
, "Unknown intrinsic: ");
4630 nir_print_instr(&instr
->instr
, stderr
);
4631 fprintf(stderr
, "\n");
4635 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4639 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4640 LLVMValueRef buffer_ptr
, bool write
)
4642 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4643 LLVMValueRef result
;
4645 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4647 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4648 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4653 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4655 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4656 LLVMValueRef result
;
4658 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4660 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4661 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4666 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4667 unsigned descriptor_set
,
4668 unsigned base_index
,
4669 unsigned constant_index
,
4671 enum ac_descriptor_type desc_type
,
4672 bool image
, bool write
)
4674 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4675 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4676 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4677 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4678 unsigned offset
= binding
->offset
;
4679 unsigned stride
= binding
->size
;
4681 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4684 assert(base_index
< layout
->binding_count
);
4686 switch (desc_type
) {
4688 type
= ctx
->ac
.v8i32
;
4692 type
= ctx
->ac
.v8i32
;
4696 case AC_DESC_SAMPLER
:
4697 type
= ctx
->ac
.v4i32
;
4698 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4703 case AC_DESC_BUFFER
:
4704 type
= ctx
->ac
.v4i32
;
4708 unreachable("invalid desc_type\n");
4711 offset
+= constant_index
* stride
;
4713 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4714 (!index
|| binding
->immutable_samplers_equal
)) {
4715 if (binding
->immutable_samplers_equal
)
4718 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4720 LLVMValueRef constants
[] = {
4721 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4722 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4723 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4724 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4726 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4729 assert(stride
% type_size
== 0);
4732 index
= ctx
->ac
.i32_0
;
4734 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4736 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4737 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4739 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4742 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4743 const nir_deref_var
*deref
,
4744 enum ac_descriptor_type desc_type
,
4745 const nir_tex_instr
*tex_instr
,
4746 bool image
, bool write
)
4748 LLVMValueRef index
= NULL
;
4749 unsigned constant_index
= 0;
4750 unsigned descriptor_set
;
4751 unsigned base_index
;
4754 assert(tex_instr
&& !image
);
4756 base_index
= tex_instr
->sampler_index
;
4758 const nir_deref
*tail
= &deref
->deref
;
4759 while (tail
->child
) {
4760 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4761 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4766 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4768 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4769 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4771 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4772 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4777 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4780 constant_index
+= child
->base_offset
* array_size
;
4782 tail
= &child
->deref
;
4784 descriptor_set
= deref
->var
->data
.descriptor_set
;
4785 base_index
= deref
->var
->data
.binding
;
4788 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4791 constant_index
, index
,
4792 desc_type
, image
, write
);
4795 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4796 struct ac_image_args
*args
,
4797 const nir_tex_instr
*instr
,
4799 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4800 LLVMValueRef
*param
, unsigned count
,
4803 unsigned is_rect
= 0;
4804 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4806 if (op
== nir_texop_lod
)
4808 /* Pad to power of two vector */
4809 while (count
< util_next_power_of_two(count
))
4810 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4813 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4815 args
->addr
= param
[0];
4817 args
->resource
= res_ptr
;
4818 args
->sampler
= samp_ptr
;
4820 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4821 args
->addr
= param
[0];
4825 args
->dmask
= dmask
;
4826 args
->unorm
= is_rect
;
4830 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4833 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4834 * filtering manually. The driver sets img7 to a mask clearing
4835 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4836 * s_and_b32 samp0, samp0, img7
4839 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4841 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4842 LLVMValueRef res
, LLVMValueRef samp
)
4844 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4845 LLVMValueRef img7
, samp0
;
4847 if (ctx
->ac
.chip_class
>= VI
)
4850 img7
= LLVMBuildExtractElement(builder
, res
,
4851 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4852 samp0
= LLVMBuildExtractElement(builder
, samp
,
4853 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4854 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4855 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4856 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4859 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4860 nir_tex_instr
*instr
,
4861 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4862 LLVMValueRef
*fmask_ptr
)
4864 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4865 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4867 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4870 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4872 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4873 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4874 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4876 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4877 instr
->op
== nir_texop_samples_identical
))
4878 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4881 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4884 coord
= ac_to_float(ctx
, coord
);
4885 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4886 coord
= ac_to_integer(ctx
, coord
);
4890 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4892 LLVMValueRef result
= NULL
;
4893 struct ac_image_args args
= { 0 };
4894 unsigned dmask
= 0xf;
4895 LLVMValueRef address
[16];
4896 LLVMValueRef coords
[5];
4897 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4898 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4899 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4900 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4901 LLVMValueRef derivs
[6];
4902 unsigned chan
, count
= 0;
4903 unsigned const_src
= 0, num_deriv_comp
= 0;
4904 bool lod_is_zero
= false;
4906 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4908 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4909 switch (instr
->src
[i
].src_type
) {
4910 case nir_tex_src_coord
:
4911 coord
= get_src(ctx
, instr
->src
[i
].src
);
4913 case nir_tex_src_projector
:
4915 case nir_tex_src_comparator
:
4916 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4918 case nir_tex_src_offset
:
4919 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4922 case nir_tex_src_bias
:
4923 bias
= get_src(ctx
, instr
->src
[i
].src
);
4925 case nir_tex_src_lod
: {
4926 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4928 if (val
&& val
->i32
[0] == 0)
4930 lod
= get_src(ctx
, instr
->src
[i
].src
);
4933 case nir_tex_src_ms_index
:
4934 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4936 case nir_tex_src_ms_mcs
:
4938 case nir_tex_src_ddx
:
4939 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4940 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4942 case nir_tex_src_ddy
:
4943 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4945 case nir_tex_src_texture_offset
:
4946 case nir_tex_src_sampler_offset
:
4947 case nir_tex_src_plane
:
4953 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4954 result
= get_buffer_size(ctx
, res_ptr
, true);
4958 if (instr
->op
== nir_texop_texture_samples
) {
4959 LLVMValueRef res
, samples
, is_msaa
;
4960 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4961 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4962 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4963 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4964 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4965 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4966 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4967 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4968 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4970 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4971 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4972 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4973 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4974 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4976 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4983 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4984 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4986 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4987 LLVMValueRef offset
[3], pack
;
4988 for (chan
= 0; chan
< 3; ++chan
)
4989 offset
[chan
] = ctx
->ac
.i32_0
;
4992 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4993 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4994 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4995 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4997 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4998 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
5000 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
5001 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
5002 address
[count
++] = pack
;
5005 /* pack LOD bias value */
5006 if (instr
->op
== nir_texop_txb
&& bias
) {
5007 address
[count
++] = bias
;
5010 /* Pack depth comparison value */
5011 if (instr
->is_shadow
&& comparator
) {
5012 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
5013 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
5015 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5016 * so the depth comparison value isn't clamped for Z16 and
5017 * Z24 anymore. Do it manually here.
5019 * It's unnecessary if the original texture format was
5020 * Z32_FLOAT, but we don't know that here.
5022 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
5023 z
= ac_build_clamp(&ctx
->ac
, z
);
5025 address
[count
++] = z
;
5028 /* pack derivatives */
5030 int num_src_deriv_channels
, num_dest_deriv_channels
;
5031 switch (instr
->sampler_dim
) {
5032 case GLSL_SAMPLER_DIM_3D
:
5033 case GLSL_SAMPLER_DIM_CUBE
:
5035 num_src_deriv_channels
= 3;
5036 num_dest_deriv_channels
= 3;
5038 case GLSL_SAMPLER_DIM_2D
:
5040 num_src_deriv_channels
= 2;
5041 num_dest_deriv_channels
= 2;
5044 case GLSL_SAMPLER_DIM_1D
:
5045 num_src_deriv_channels
= 1;
5046 if (ctx
->ac
.chip_class
>= GFX9
) {
5047 num_dest_deriv_channels
= 2;
5050 num_dest_deriv_channels
= 1;
5056 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
5057 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
5058 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
5060 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
5061 derivs
[i
] = ctx
->ac
.f32_0
;
5062 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
5066 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
5067 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
5068 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
5069 if (instr
->coord_components
== 3)
5070 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5071 ac_prepare_cube_coords(&ctx
->ac
,
5072 instr
->op
== nir_texop_txd
, instr
->is_array
,
5073 instr
->op
== nir_texop_lod
, coords
, derivs
);
5079 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
5080 address
[count
++] = derivs
[i
];
5083 /* Pack texture coordinates */
5085 address
[count
++] = coords
[0];
5086 if (instr
->coord_components
> 1) {
5087 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
5088 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
5090 address
[count
++] = coords
[1];
5092 if (instr
->coord_components
> 2) {
5093 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5094 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
5095 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
5096 instr
->op
!= nir_texop_txf
) {
5097 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
5099 address
[count
++] = coords
[2];
5102 if (ctx
->ac
.chip_class
>= GFX9
) {
5103 LLVMValueRef filler
;
5104 if (instr
->op
== nir_texop_txf
)
5105 filler
= ctx
->ac
.i32_0
;
5107 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
5109 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
5110 /* No nir_texop_lod, because it does not take a slice
5111 * even with array textures. */
5112 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
5113 address
[count
] = address
[count
- 1];
5114 address
[count
- 1] = filler
;
5117 address
[count
++] = filler
;
5123 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
5124 instr
->op
== nir_texop_txf
)) {
5125 address
[count
++] = lod
;
5126 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5127 address
[count
++] = sample_index
;
5128 } else if(instr
->op
== nir_texop_txs
) {
5131 address
[count
++] = lod
;
5133 address
[count
++] = ctx
->ac
.i32_0
;
5136 for (chan
= 0; chan
< count
; chan
++) {
5137 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5138 address
[chan
], ctx
->ac
.i32
, "");
5141 if (instr
->op
== nir_texop_samples_identical
) {
5142 LLVMValueRef txf_address
[4];
5143 struct ac_image_args txf_args
= { 0 };
5144 unsigned txf_count
= count
;
5145 memcpy(txf_address
, address
, sizeof(txf_address
));
5147 if (!instr
->is_array
)
5148 txf_address
[2] = ctx
->ac
.i32_0
;
5149 txf_address
[3] = ctx
->ac
.i32_0
;
5151 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5153 txf_address
, txf_count
, 0xf);
5155 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5157 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5158 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5162 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5163 instr
->op
!= nir_texop_txs
) {
5164 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5165 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5168 instr
->is_array
? address
[2] : NULL
,
5169 address
[sample_chan
],
5173 if (offsets
&& instr
->op
== nir_texop_txf
) {
5174 nir_const_value
*const_offset
=
5175 nir_src_as_const_value(instr
->src
[const_src
].src
);
5176 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5177 assert(const_offset
);
5178 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5179 if (num_offsets
> 2)
5180 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5181 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5182 if (num_offsets
> 1)
5183 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5184 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5185 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5186 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5190 /* TODO TG4 support */
5191 if (instr
->op
== nir_texop_tg4
) {
5192 if (instr
->is_shadow
)
5195 dmask
= 1 << instr
->component
;
5197 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5198 res_ptr
, samp_ptr
, address
, count
, dmask
);
5200 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5202 if (instr
->op
== nir_texop_query_levels
)
5203 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5204 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5205 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5206 instr
->op
!= nir_texop_tg4
)
5207 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5208 else if (instr
->op
== nir_texop_txs
&&
5209 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5211 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5212 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5213 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5214 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5215 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5216 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5217 instr
->op
== nir_texop_txs
&&
5218 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5220 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5221 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5222 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5224 } else if (instr
->dest
.ssa
.num_components
!= 4)
5225 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5229 assert(instr
->dest
.is_ssa
);
5230 result
= ac_to_integer(&ctx
->ac
, result
);
5231 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5236 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5238 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5239 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5241 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5242 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5245 static void visit_post_phi(struct ac_nir_context
*ctx
,
5246 nir_phi_instr
*instr
,
5247 LLVMValueRef llvm_phi
)
5249 nir_foreach_phi_src(src
, instr
) {
5250 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5251 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5253 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5257 static void phi_post_pass(struct ac_nir_context
*ctx
)
5259 struct hash_entry
*entry
;
5260 hash_table_foreach(ctx
->phis
, entry
) {
5261 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5262 (LLVMValueRef
)entry
->data
);
5267 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5268 const nir_ssa_undef_instr
*instr
)
5270 unsigned num_components
= instr
->def
.num_components
;
5271 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5274 if (num_components
== 1)
5275 undef
= LLVMGetUndef(type
);
5277 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5279 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5282 static void visit_jump(struct ac_nir_context
*ctx
,
5283 const nir_jump_instr
*instr
)
5285 switch (instr
->type
) {
5286 case nir_jump_break
:
5287 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5288 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5290 case nir_jump_continue
:
5291 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5292 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5295 fprintf(stderr
, "Unknown NIR jump instr: ");
5296 nir_print_instr(&instr
->instr
, stderr
);
5297 fprintf(stderr
, "\n");
5302 static void visit_cf_list(struct ac_nir_context
*ctx
,
5303 struct exec_list
*list
);
5305 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5307 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5308 nir_foreach_instr(instr
, block
)
5310 switch (instr
->type
) {
5311 case nir_instr_type_alu
:
5312 visit_alu(ctx
, nir_instr_as_alu(instr
));
5314 case nir_instr_type_load_const
:
5315 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5317 case nir_instr_type_intrinsic
:
5318 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5320 case nir_instr_type_tex
:
5321 visit_tex(ctx
, nir_instr_as_tex(instr
));
5323 case nir_instr_type_phi
:
5324 visit_phi(ctx
, nir_instr_as_phi(instr
));
5326 case nir_instr_type_ssa_undef
:
5327 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5329 case nir_instr_type_jump
:
5330 visit_jump(ctx
, nir_instr_as_jump(instr
));
5333 fprintf(stderr
, "Unknown NIR instr type: ");
5334 nir_print_instr(instr
, stderr
);
5335 fprintf(stderr
, "\n");
5340 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5343 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5345 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5347 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5348 LLVMBasicBlockRef merge_block
=
5349 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5350 LLVMBasicBlockRef if_block
=
5351 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5352 LLVMBasicBlockRef else_block
= merge_block
;
5353 if (!exec_list_is_empty(&if_stmt
->else_list
))
5354 else_block
= LLVMAppendBasicBlockInContext(
5355 ctx
->ac
.context
, fn
, "");
5357 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5359 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5361 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5362 visit_cf_list(ctx
, &if_stmt
->then_list
);
5363 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5364 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5366 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5367 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5368 visit_cf_list(ctx
, &if_stmt
->else_list
);
5369 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5370 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5373 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5376 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5378 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5379 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5380 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5382 ctx
->continue_block
=
5383 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5385 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5387 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5388 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5389 visit_cf_list(ctx
, &loop
->body
);
5391 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5392 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5393 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5395 ctx
->continue_block
= continue_parent
;
5396 ctx
->break_block
= break_parent
;
5399 static void visit_cf_list(struct ac_nir_context
*ctx
,
5400 struct exec_list
*list
)
5402 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5404 switch (node
->type
) {
5405 case nir_cf_node_block
:
5406 visit_block(ctx
, nir_cf_node_as_block(node
));
5409 case nir_cf_node_if
:
5410 visit_if(ctx
, nir_cf_node_as_if(node
));
5413 case nir_cf_node_loop
:
5414 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5424 handle_vs_input_decl(struct radv_shader_context
*ctx
,
5425 struct nir_variable
*variable
)
5427 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5428 LLVMValueRef t_offset
;
5429 LLVMValueRef t_list
;
5431 LLVMValueRef buffer_index
;
5432 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5433 int idx
= variable
->data
.location
;
5434 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5435 uint8_t input_usage_mask
=
5436 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
5437 unsigned num_channels
= util_last_bit(input_usage_mask
);
5439 variable
->data
.driver_location
= idx
* 4;
5441 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5442 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5443 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.instance_id
,
5444 ctx
->abi
.start_instance
, "");
5445 if (ctx
->options
->key
.vs
.as_ls
) {
5446 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5447 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5449 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5450 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5453 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
5454 ctx
->abi
.base_vertex
, "");
5455 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5457 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5459 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5462 num_channels
, false, true);
5464 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
5466 for (unsigned chan
= 0; chan
< 4; chan
++) {
5467 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5468 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5469 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
,
5470 input
, llvm_chan
, ""));
5475 static void interp_fs_input(struct radv_shader_context
*ctx
,
5477 LLVMValueRef interp_param
,
5478 LLVMValueRef prim_mask
,
5479 LLVMValueRef result
[4])
5481 LLVMValueRef attr_number
;
5484 bool interp
= interp_param
!= NULL
;
5486 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5488 /* fs.constant returns the param from the middle vertex, so it's not
5489 * really useful for flat shading. It's meant to be used for custom
5490 * interpolation (but the intrinsic can't fetch from the other two
5493 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5494 * to do the right thing. The only reason we use fs.constant is that
5495 * fs.interp cannot be used on integers, because they can be equal
5499 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
5502 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5504 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5508 for (chan
= 0; chan
< 4; chan
++) {
5509 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5512 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5517 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5518 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5527 handle_fs_input_decl(struct radv_shader_context
*ctx
,
5528 struct nir_variable
*variable
)
5530 int idx
= variable
->data
.location
;
5531 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5532 LLVMValueRef interp
;
5534 variable
->data
.driver_location
= idx
* 4;
5535 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5537 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5538 unsigned interp_type
;
5539 if (variable
->data
.sample
)
5540 interp_type
= INTERP_SAMPLE
;
5541 else if (variable
->data
.centroid
)
5542 interp_type
= INTERP_CENTROID
;
5544 interp_type
= INTERP_CENTER
;
5546 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
5550 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5551 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5556 handle_vs_inputs(struct radv_shader_context
*ctx
,
5557 struct nir_shader
*nir
) {
5558 nir_foreach_variable(variable
, &nir
->inputs
)
5559 handle_vs_input_decl(ctx
, variable
);
5563 prepare_interp_optimize(struct radv_shader_context
*ctx
,
5564 struct nir_shader
*nir
)
5566 if (!ctx
->options
->key
.fs
.multisample
)
5569 bool uses_center
= false;
5570 bool uses_centroid
= false;
5571 nir_foreach_variable(variable
, &nir
->inputs
) {
5572 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5573 variable
->data
.sample
)
5576 if (variable
->data
.centroid
)
5577 uses_centroid
= true;
5582 if (uses_center
&& uses_centroid
) {
5583 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
5584 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5585 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5590 handle_fs_inputs(struct radv_shader_context
*ctx
,
5591 struct nir_shader
*nir
)
5593 prepare_interp_optimize(ctx
, nir
);
5595 nir_foreach_variable(variable
, &nir
->inputs
)
5596 handle_fs_input_decl(ctx
, variable
);
5600 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5601 ctx
->shader_info
->info
.needs_multiview_view_index
)
5602 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5604 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5605 LLVMValueRef interp_param
;
5606 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5608 if (!(ctx
->input_mask
& (1ull << i
)))
5611 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5612 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5613 interp_param
= *inputs
;
5614 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
5618 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5620 } else if (i
== VARYING_SLOT_POS
) {
5621 for(int i
= 0; i
< 3; ++i
)
5622 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5624 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5625 ctx
->abi
.frag_pos
[3]);
5628 ctx
->shader_info
->fs
.num_interp
= index
;
5629 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5630 ctx
->shader_info
->fs
.has_pcoord
= true;
5631 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5632 ctx
->shader_info
->fs
.prim_id_input
= true;
5633 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5634 ctx
->shader_info
->fs
.layer_input
= true;
5635 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5637 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5638 ctx
->abi
.view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5642 ac_build_alloca(struct ac_llvm_context
*ac
,
5646 LLVMBuilderRef builder
= ac
->builder
;
5647 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5648 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5649 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5650 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5651 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5655 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5657 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5660 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5661 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5663 LLVMDisposeBuilder(first_builder
);
5668 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5672 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5673 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5678 scan_shader_output_decl(struct radv_shader_context
*ctx
,
5679 struct nir_variable
*variable
,
5680 struct nir_shader
*shader
,
5681 gl_shader_stage stage
)
5683 int idx
= variable
->data
.location
+ variable
->data
.index
;
5684 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5685 uint64_t mask_attribs
;
5687 variable
->data
.driver_location
= idx
* 4;
5689 /* tess ctrl has it's own load/store paths for outputs */
5690 if (stage
== MESA_SHADER_TESS_CTRL
)
5693 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5694 if (stage
== MESA_SHADER_VERTEX
||
5695 stage
== MESA_SHADER_TESS_EVAL
||
5696 stage
== MESA_SHADER_GEOMETRY
) {
5697 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5698 int length
= shader
->info
.clip_distance_array_size
+
5699 shader
->info
.cull_distance_array_size
;
5700 if (stage
== MESA_SHADER_VERTEX
) {
5701 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5702 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5704 if (stage
== MESA_SHADER_TESS_EVAL
) {
5705 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5706 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5713 mask_attribs
= 1ull << idx
;
5717 ctx
->output_mask
|= mask_attribs
;
5721 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5722 struct nir_shader
*nir
,
5723 struct nir_variable
*variable
)
5725 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5726 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5728 /* tess ctrl has it's own load/store paths for outputs */
5729 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5732 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5733 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5734 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5735 int idx
= variable
->data
.location
+ variable
->data
.index
;
5736 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5737 int length
= nir
->info
.clip_distance_array_size
+
5738 nir
->info
.cull_distance_array_size
;
5747 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5748 for (unsigned chan
= 0; chan
< 4; chan
++) {
5749 ctx
->abi
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5750 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5756 glsl_base_to_llvm_type(struct ac_llvm_context
*ac
,
5757 enum glsl_base_type type
)
5761 case GLSL_TYPE_UINT
:
5762 case GLSL_TYPE_BOOL
:
5763 case GLSL_TYPE_SUBROUTINE
:
5765 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5767 case GLSL_TYPE_INT64
:
5768 case GLSL_TYPE_UINT64
:
5770 case GLSL_TYPE_DOUBLE
:
5773 unreachable("unknown GLSL type");
5778 glsl_to_llvm_type(struct ac_llvm_context
*ac
,
5779 const struct glsl_type
*type
)
5781 if (glsl_type_is_scalar(type
)) {
5782 return glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
));
5785 if (glsl_type_is_vector(type
)) {
5786 return LLVMVectorType(
5787 glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
)),
5788 glsl_get_vector_elements(type
));
5791 if (glsl_type_is_matrix(type
)) {
5792 return LLVMArrayType(
5793 glsl_to_llvm_type(ac
, glsl_get_column_type(type
)),
5794 glsl_get_matrix_columns(type
));
5797 if (glsl_type_is_array(type
)) {
5798 return LLVMArrayType(
5799 glsl_to_llvm_type(ac
, glsl_get_array_element(type
)),
5800 glsl_get_length(type
));
5803 assert(glsl_type_is_struct(type
));
5805 LLVMTypeRef member_types
[glsl_get_length(type
)];
5807 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5809 glsl_to_llvm_type(ac
,
5810 glsl_get_struct_field(type
, i
));
5813 return LLVMStructTypeInContext(ac
->context
, member_types
,
5814 glsl_get_length(type
), false);
5818 setup_locals(struct ac_nir_context
*ctx
,
5819 struct nir_function
*func
)
5822 ctx
->num_locals
= 0;
5823 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5824 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5825 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5826 variable
->data
.location_frac
= 0;
5827 ctx
->num_locals
+= attrib_count
;
5829 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5833 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5834 for (j
= 0; j
< 4; j
++) {
5835 ctx
->locals
[i
* 4 + j
] =
5836 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5842 setup_shared(struct ac_nir_context
*ctx
,
5843 struct nir_shader
*nir
)
5845 nir_foreach_variable(variable
, &nir
->shared
) {
5846 LLVMValueRef shared
=
5847 LLVMAddGlobalInAddressSpace(
5848 ctx
->ac
.module
, glsl_to_llvm_type(&ctx
->ac
, variable
->type
),
5849 variable
->name
? variable
->name
: "",
5850 AC_LOCAL_ADDR_SPACE
);
5851 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5855 /* Initialize arguments for the shader export intrinsic */
5857 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
5858 LLVMValueRef
*values
,
5860 struct ac_export_args
*args
)
5862 /* Default is 0xf. Adjusted below depending on the format. */
5863 args
->enabled_channels
= 0xf;
5865 /* Specify whether the EXEC mask represents the valid mask */
5866 args
->valid_mask
= 0;
5868 /* Specify whether this is the last export */
5871 /* Specify the target we are exporting */
5872 args
->target
= target
;
5874 args
->compr
= false;
5875 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5876 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5877 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5878 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5880 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5881 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5882 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5883 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5884 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5887 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
5888 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
5889 unsigned bits
, bool hi
) = NULL
;
5891 switch(col_format
) {
5892 case V_028714_SPI_SHADER_ZERO
:
5893 args
->enabled_channels
= 0; /* writemask */
5894 args
->target
= V_008DFC_SQ_EXP_NULL
;
5897 case V_028714_SPI_SHADER_32_R
:
5898 args
->enabled_channels
= 1;
5899 args
->out
[0] = values
[0];
5902 case V_028714_SPI_SHADER_32_GR
:
5903 args
->enabled_channels
= 0x3;
5904 args
->out
[0] = values
[0];
5905 args
->out
[1] = values
[1];
5908 case V_028714_SPI_SHADER_32_AR
:
5909 args
->enabled_channels
= 0x9;
5910 args
->out
[0] = values
[0];
5911 args
->out
[3] = values
[3];
5914 case V_028714_SPI_SHADER_FP16_ABGR
:
5915 packf
= ac_build_cvt_pkrtz_f16
;
5918 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5919 packf
= ac_build_cvt_pknorm_u16
;
5922 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5923 packf
= ac_build_cvt_pknorm_i16
;
5926 case V_028714_SPI_SHADER_UINT16_ABGR
:
5927 packi
= ac_build_cvt_pk_u16
;
5930 case V_028714_SPI_SHADER_SINT16_ABGR
:
5931 packi
= ac_build_cvt_pk_i16
;
5935 case V_028714_SPI_SHADER_32_ABGR
:
5936 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5940 /* Pack f16 or norm_i16/u16. */
5942 for (chan
= 0; chan
< 2; chan
++) {
5943 LLVMValueRef pack_args
[2] = {
5945 values
[2 * chan
+ 1]
5947 LLVMValueRef packed
;
5949 packed
= packf(&ctx
->ac
, pack_args
);
5950 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5952 args
->compr
= 1; /* COMPR flag */
5957 for (chan
= 0; chan
< 2; chan
++) {
5958 LLVMValueRef pack_args
[2] = {
5959 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
5960 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
5962 LLVMValueRef packed
;
5964 packed
= packi(&ctx
->ac
, pack_args
,
5965 is_int8
? 8 : is_int10
? 10 : 16,
5967 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5969 args
->compr
= 1; /* COMPR flag */
5974 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5976 for (unsigned i
= 0; i
< 4; ++i
)
5977 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5981 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
5982 LLVMValueRef
*values
)
5984 struct ac_export_args args
;
5986 si_llvm_init_export_args(ctx
, values
,
5987 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
5988 ac_build_export(&ctx
->ac
, &args
);
5992 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
5994 LLVMValueRef output
=
5995 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(index
, chan
)];
5997 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
6001 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
6002 bool export_prim_id
,
6003 struct ac_vs_output_info
*outinfo
)
6005 uint32_t param_count
= 0;
6007 unsigned pos_idx
, num_pos_exports
= 0;
6008 struct ac_export_args args
, pos_args
[4] = {};
6009 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
6012 if (ctx
->options
->key
.has_multiview_view_index
) {
6013 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
6015 for(unsigned i
= 0; i
< 4; ++i
)
6016 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
6017 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
6020 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
6021 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
6024 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6025 sizeof(outinfo
->vs_output_param_offset
));
6027 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
6028 LLVMValueRef slots
[8];
6031 if (outinfo
->cull_dist_mask
)
6032 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
6034 i
= VARYING_SLOT_CLIP_DIST0
;
6035 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
6036 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
6038 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
6039 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
6041 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
6042 target
= V_008DFC_SQ_EXP_POS
+ 3;
6043 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
6044 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6045 &args
, sizeof(args
));
6048 target
= V_008DFC_SQ_EXP_POS
+ 2;
6049 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
6050 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6051 &args
, sizeof(args
));
6055 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
6056 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
6057 for (unsigned j
= 0; j
< 4; j
++)
6058 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
6060 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
6062 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
6063 outinfo
->writes_pointsize
= true;
6064 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
6067 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
6068 outinfo
->writes_layer
= true;
6069 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
6072 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
6073 outinfo
->writes_viewport_index
= true;
6074 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
6077 if (outinfo
->writes_pointsize
||
6078 outinfo
->writes_layer
||
6079 outinfo
->writes_viewport_index
) {
6080 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
6081 (outinfo
->writes_layer
== true ? 4 : 0));
6082 pos_args
[1].valid_mask
= 0;
6083 pos_args
[1].done
= 0;
6084 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
6085 pos_args
[1].compr
= 0;
6086 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
6087 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6088 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6089 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6091 if (outinfo
->writes_pointsize
== true)
6092 pos_args
[1].out
[0] = psize_value
;
6093 if (outinfo
->writes_layer
== true)
6094 pos_args
[1].out
[2] = layer_value
;
6095 if (outinfo
->writes_viewport_index
== true) {
6096 if (ctx
->options
->chip_class
>= GFX9
) {
6097 /* GFX9 has the layer in out.z[10:0] and the viewport
6098 * index in out.z[19:16].
6100 LLVMValueRef v
= viewport_index_value
;
6101 v
= ac_to_integer(&ctx
->ac
, v
);
6102 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
6103 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6105 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
6106 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6108 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6109 pos_args
[1].enabled_channels
|= 1 << 2;
6111 pos_args
[1].out
[3] = viewport_index_value
;
6112 pos_args
[1].enabled_channels
|= 1 << 3;
6116 for (i
= 0; i
< 4; i
++) {
6117 if (pos_args
[i
].out
[0])
6122 for (i
= 0; i
< 4; i
++) {
6123 if (!pos_args
[i
].out
[0])
6126 /* Specify the target we are exporting */
6127 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6128 if (pos_idx
== num_pos_exports
)
6129 pos_args
[i
].done
= 1;
6130 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6133 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6134 LLVMValueRef values
[4];
6135 if (!(ctx
->output_mask
& (1ull << i
)))
6138 if (i
!= VARYING_SLOT_LAYER
&&
6139 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
6140 i
< VARYING_SLOT_VAR0
)
6143 for (unsigned j
= 0; j
< 4; j
++)
6144 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
6146 radv_export_param(ctx
, param_count
, values
);
6148 outinfo
->vs_output_param_offset
[i
] = param_count
++;
6151 if (export_prim_id
) {
6152 LLVMValueRef values
[4];
6154 values
[0] = ctx
->vs_prim_id
;
6155 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6156 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6157 for (unsigned j
= 1; j
< 4; j
++)
6158 values
[j
] = ctx
->ac
.f32_0
;
6160 radv_export_param(ctx
, param_count
, values
);
6162 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
6163 outinfo
->export_prim_id
= true;
6166 outinfo
->pos_exports
= num_pos_exports
;
6167 outinfo
->param_exports
= param_count
;
6171 handle_es_outputs_post(struct radv_shader_context
*ctx
,
6172 struct ac_es_output_info
*outinfo
)
6175 uint64_t max_output_written
= 0;
6176 LLVMValueRef lds_base
= NULL
;
6178 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6182 if (!(ctx
->output_mask
& (1ull << i
)))
6185 if (i
== VARYING_SLOT_CLIP_DIST0
)
6186 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6188 param_index
= shader_io_get_unique_index(i
);
6190 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6193 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6195 if (ctx
->ac
.chip_class
>= GFX9
) {
6196 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6197 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6198 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6199 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6200 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6201 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6202 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6203 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6204 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6205 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6208 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6209 LLVMValueRef dw_addr
= NULL
;
6210 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6214 if (!(ctx
->output_mask
& (1ull << i
)))
6217 if (i
== VARYING_SLOT_CLIP_DIST0
)
6218 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6220 param_index
= shader_io_get_unique_index(i
);
6223 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6224 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6227 for (j
= 0; j
< length
; j
++) {
6228 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
6229 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
6231 if (ctx
->ac
.chip_class
>= GFX9
) {
6232 ac_lds_store(&ctx
->ac
, dw_addr
,
6233 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6234 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6236 ac_build_buffer_store_dword(&ctx
->ac
,
6239 NULL
, ctx
->es2gs_offset
,
6240 (4 * param_index
+ j
) * 4,
6248 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
6250 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6251 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6252 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
6253 vertex_dw_stride
, "");
6255 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6256 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6259 if (!(ctx
->output_mask
& (1ull << i
)))
6262 if (i
== VARYING_SLOT_CLIP_DIST0
)
6263 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6264 int param
= shader_io_get_unique_index(i
);
6265 mark_tess_output(ctx
, false, param
);
6267 mark_tess_output(ctx
, false, param
+ 1);
6268 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
6269 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6271 for (unsigned j
= 0; j
< length
; j
++) {
6272 ac_lds_store(&ctx
->ac
, dw_addr
,
6273 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6274 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6279 struct ac_build_if_state
6281 struct radv_shader_context
*ctx
;
6282 LLVMValueRef condition
;
6283 LLVMBasicBlockRef entry_block
;
6284 LLVMBasicBlockRef true_block
;
6285 LLVMBasicBlockRef false_block
;
6286 LLVMBasicBlockRef merge_block
;
6289 static LLVMBasicBlockRef
6290 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
6292 LLVMBasicBlockRef current_block
;
6293 LLVMBasicBlockRef next_block
;
6294 LLVMBasicBlockRef new_block
;
6296 /* get current basic block */
6297 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6299 /* chqeck if there's another block after this one */
6300 next_block
= LLVMGetNextBasicBlock(current_block
);
6302 /* insert the new block before the next block */
6303 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6306 /* append new block after current block */
6307 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6308 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6314 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6315 struct radv_shader_context
*ctx
,
6316 LLVMValueRef condition
)
6318 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6320 memset(ifthen
, 0, sizeof *ifthen
);
6322 ifthen
->condition
= condition
;
6323 ifthen
->entry_block
= block
;
6325 /* create endif/merge basic block for the phi functions */
6326 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6328 /* create/insert true_block before merge_block */
6329 ifthen
->true_block
=
6330 LLVMInsertBasicBlockInContext(ctx
->context
,
6331 ifthen
->merge_block
,
6334 /* successive code goes into the true block */
6335 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
6339 * End a conditional.
6342 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6344 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
6346 /* Insert branch to the merge block from current block */
6347 LLVMBuildBr(builder
, ifthen
->merge_block
);
6350 * Now patch in the various branch instructions.
6353 /* Insert the conditional branch instruction at the end of entry_block */
6354 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6355 if (ifthen
->false_block
) {
6356 /* we have an else clause */
6357 LLVMBuildCondBr(builder
, ifthen
->condition
,
6358 ifthen
->true_block
, ifthen
->false_block
);
6361 /* no else clause */
6362 LLVMBuildCondBr(builder
, ifthen
->condition
,
6363 ifthen
->true_block
, ifthen
->merge_block
);
6366 /* Resume building code at end of the ifthen->merge_block */
6367 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6371 write_tess_factors(struct radv_shader_context
*ctx
)
6373 unsigned stride
, outer_comps
, inner_comps
;
6374 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6375 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6376 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6377 unsigned tess_inner_index
= 0, tess_outer_index
;
6378 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
6379 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6381 emit_barrier(&ctx
->ac
, ctx
->stage
);
6383 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6403 ac_nir_build_if(&if_ctx
, ctx
,
6404 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6405 invocation_id
, ctx
->ac
.i32_0
, ""));
6407 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6410 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6411 mark_tess_output(ctx
, true, tess_inner_index
);
6412 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6413 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6416 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6417 mark_tess_output(ctx
, true, tess_outer_index
);
6418 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6419 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6421 for (i
= 0; i
< 4; i
++) {
6422 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6423 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6427 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6428 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6429 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6431 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6433 for (i
= 0; i
< outer_comps
; i
++) {
6435 ac_lds_load(&ctx
->ac
, lds_outer
);
6436 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6439 for (i
= 0; i
< inner_comps
; i
++) {
6440 inner
[i
] = out
[outer_comps
+i
] =
6441 ac_lds_load(&ctx
->ac
, lds_inner
);
6442 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
6447 /* Convert the outputs to vectors for stores. */
6448 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6452 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6455 buffer
= ctx
->hs_ring_tess_factor
;
6456 tf_base
= ctx
->tess_factor_offset
;
6457 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
6458 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6459 unsigned tf_offset
= 0;
6461 if (ctx
->options
->chip_class
<= VI
) {
6462 ac_nir_build_if(&inner_if_ctx
, ctx
,
6463 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6464 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6466 /* Store the dynamic HS control word. */
6467 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6468 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6469 1, ctx
->ac
.i32_0
, tf_base
,
6470 0, 1, 0, true, false);
6473 ac_nir_build_endif(&inner_if_ctx
);
6476 /* Store the tessellation factors. */
6477 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6478 MIN2(stride
, 4), byteoffset
, tf_base
,
6479 tf_offset
, 1, 0, true, false);
6481 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6482 stride
- 4, byteoffset
, tf_base
,
6483 16 + tf_offset
, 1, 0, true, false);
6485 //store to offchip for TES to read - only if TES reads them
6486 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6487 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6488 LLVMValueRef tf_inner_offset
;
6489 unsigned param_outer
, param_inner
;
6491 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6492 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6493 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6495 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6496 util_next_power_of_two(outer_comps
));
6498 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6499 outer_comps
, tf_outer_offset
,
6500 ctx
->oc_lds
, 0, 1, 0, true, false);
6502 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6503 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6504 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6506 inner_vec
= inner_comps
== 1 ? inner
[0] :
6507 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6508 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6509 inner_comps
, tf_inner_offset
,
6510 ctx
->oc_lds
, 0, 1, 0, true, false);
6513 ac_nir_build_endif(&if_ctx
);
6517 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
6519 write_tess_factors(ctx
);
6523 si_export_mrt_color(struct radv_shader_context
*ctx
,
6524 LLVMValueRef
*color
, unsigned index
, bool is_last
,
6525 struct ac_export_args
*args
)
6528 si_llvm_init_export_args(ctx
, color
,
6529 V_008DFC_SQ_EXP_MRT
+ index
, args
);
6532 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6533 args
->done
= 1; /* DONE bit */
6534 } else if (!args
->enabled_channels
)
6535 return false; /* unnecessary NULL export */
6541 radv_export_mrt_z(struct radv_shader_context
*ctx
,
6542 LLVMValueRef depth
, LLVMValueRef stencil
,
6543 LLVMValueRef samplemask
)
6545 struct ac_export_args args
;
6547 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6549 ac_build_export(&ctx
->ac
, &args
);
6553 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
6556 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6557 struct ac_export_args color_args
[8];
6559 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6560 LLVMValueRef values
[4];
6563 if (!(ctx
->output_mask
& (1ull << i
)))
6566 if (i
< FRAG_RESULT_DATA0
)
6569 for (unsigned j
= 0; j
< 4; j
++)
6570 values
[j
] = ac_to_float(&ctx
->ac
,
6571 radv_load_output(ctx
, i
, j
));
6573 if (!ctx
->shader_info
->info
.ps
.writes_z
&&
6574 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
6575 !ctx
->shader_info
->info
.ps
.writes_sample_mask
)
6576 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6578 bool ret
= si_export_mrt_color(ctx
, values
,
6579 i
- FRAG_RESULT_DATA0
,
6580 last
, &color_args
[index
]);
6585 /* Process depth, stencil, samplemask. */
6586 if (ctx
->shader_info
->info
.ps
.writes_z
) {
6587 depth
= ac_to_float(&ctx
->ac
,
6588 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
6590 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
6591 stencil
= ac_to_float(&ctx
->ac
,
6592 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
6594 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
6595 samplemask
= ac_to_float(&ctx
->ac
,
6596 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
6599 /* Export PS outputs. */
6600 for (unsigned i
= 0; i
< index
; i
++)
6601 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6603 if (depth
|| stencil
|| samplemask
)
6604 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6606 ac_build_export_null(&ctx
->ac
);
6610 emit_gs_epilogue(struct radv_shader_context
*ctx
)
6612 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6616 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6617 LLVMValueRef
*addrs
)
6619 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
6621 switch (ctx
->stage
) {
6622 case MESA_SHADER_VERTEX
:
6623 if (ctx
->options
->key
.vs
.as_ls
)
6624 handle_ls_outputs_post(ctx
);
6625 else if (ctx
->options
->key
.vs
.as_es
)
6626 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6628 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6629 &ctx
->shader_info
->vs
.outinfo
);
6631 case MESA_SHADER_FRAGMENT
:
6632 handle_fs_outputs_post(ctx
);
6634 case MESA_SHADER_GEOMETRY
:
6635 emit_gs_epilogue(ctx
);
6637 case MESA_SHADER_TESS_CTRL
:
6638 handle_tcs_outputs_post(ctx
);
6640 case MESA_SHADER_TESS_EVAL
:
6641 if (ctx
->options
->key
.tes
.as_es
)
6642 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6644 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6645 &ctx
->shader_info
->tes
.outinfo
);
6652 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
)
6654 LLVMPassManagerRef passmgr
;
6655 /* Create the pass manager */
6656 passmgr
= LLVMCreateFunctionPassManagerForModule(
6659 /* This pass should eliminate all the load and store instructions */
6660 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6662 /* Add some optimization passes */
6663 LLVMAddScalarReplAggregatesPass(passmgr
);
6664 LLVMAddLICMPass(passmgr
);
6665 LLVMAddAggressiveDCEPass(passmgr
);
6666 LLVMAddCFGSimplificationPass(passmgr
);
6667 LLVMAddInstructionCombiningPass(passmgr
);
6670 LLVMInitializeFunctionPassManager(passmgr
);
6671 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6672 LLVMFinalizeFunctionPassManager(passmgr
);
6674 LLVMDisposeBuilder(ctx
->ac
.builder
);
6675 LLVMDisposePassManager(passmgr
);
6679 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
6681 struct ac_vs_output_info
*outinfo
;
6683 switch (ctx
->stage
) {
6684 case MESA_SHADER_FRAGMENT
:
6685 case MESA_SHADER_COMPUTE
:
6686 case MESA_SHADER_TESS_CTRL
:
6687 case MESA_SHADER_GEOMETRY
:
6689 case MESA_SHADER_VERTEX
:
6690 if (ctx
->options
->key
.vs
.as_ls
||
6691 ctx
->options
->key
.vs
.as_es
)
6693 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6695 case MESA_SHADER_TESS_EVAL
:
6696 if (ctx
->options
->key
.vs
.as_es
)
6698 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6701 unreachable("Unhandled shader type");
6704 ac_optimize_vs_outputs(&ctx
->ac
,
6706 outinfo
->vs_output_param_offset
,
6708 &outinfo
->param_exports
);
6712 ac_setup_rings(struct radv_shader_context
*ctx
)
6714 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6715 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6716 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6719 if (ctx
->is_gs_copy_shader
) {
6720 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6722 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6724 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6725 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6727 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6729 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6730 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6731 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6732 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6735 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6736 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6737 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6738 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6743 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6744 const struct nir_shader
*nir
)
6746 switch (nir
->info
.stage
) {
6747 case MESA_SHADER_TESS_CTRL
:
6748 return chip_class
>= CIK
? 128 : 64;
6749 case MESA_SHADER_GEOMETRY
:
6750 return chip_class
>= GFX9
? 128 : 64;
6751 case MESA_SHADER_COMPUTE
:
6757 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6758 nir
->info
.cs
.local_size
[1] *
6759 nir
->info
.cs
.local_size
[2];
6760 return max_workgroup_size
;
6763 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6764 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
6766 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6767 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6768 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6769 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6771 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6772 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6773 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6774 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6777 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
6779 for(int i
= 5; i
>= 0; --i
) {
6780 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6781 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6782 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6785 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6786 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6787 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6790 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6791 struct nir_shader
*nir
)
6793 struct ac_nir_context ctx
= {};
6794 struct nir_function
*func
;
6799 ctx
.stage
= nir
->info
.stage
;
6801 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6803 nir_foreach_variable(variable
, &nir
->outputs
)
6804 handle_shader_output_decl(&ctx
, nir
, variable
);
6806 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6807 _mesa_key_pointer_equal
);
6808 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6809 _mesa_key_pointer_equal
);
6810 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6811 _mesa_key_pointer_equal
);
6813 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6815 setup_locals(&ctx
, func
);
6817 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6818 setup_shared(&ctx
, nir
);
6820 visit_cf_list(&ctx
, &func
->impl
->body
);
6821 phi_post_pass(&ctx
);
6823 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
6824 ctx
.abi
->emit_outputs(ctx
.abi
, AC_LLVM_MAX_OUTPUTS
,
6828 ralloc_free(ctx
.defs
);
6829 ralloc_free(ctx
.phis
);
6830 ralloc_free(ctx
.vars
);
6834 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6835 struct nir_shader
*const *shaders
,
6837 struct ac_shader_variant_info
*shader_info
,
6838 const struct ac_nir_compiler_options
*options
)
6840 struct radv_shader_context ctx
= {0};
6842 ctx
.options
= options
;
6843 ctx
.shader_info
= shader_info
;
6844 ctx
.context
= LLVMContextCreate();
6846 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6848 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6849 LLVMSetTarget(ctx
.ac
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6851 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6852 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6853 LLVMSetDataLayout(ctx
.ac
.module
, data_layout_str
);
6854 LLVMDisposeTargetData(data_layout
);
6855 LLVMDisposeMessage(data_layout_str
);
6857 enum ac_float_mode float_mode
=
6858 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6859 AC_FLOAT_MODE_DEFAULT
;
6861 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6863 memset(shader_info
, 0, sizeof(*shader_info
));
6865 for(int i
= 0; i
< shader_count
; ++i
)
6866 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6868 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6869 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6870 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6871 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6873 ctx
.max_workgroup_size
= 0;
6874 for (int i
= 0; i
< shader_count
; ++i
) {
6875 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6876 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6880 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6881 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6883 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6884 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6885 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6886 ctx
.abi
.load_ubo
= radv_load_ubo
;
6887 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6888 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6889 ctx
.abi
.load_resource
= radv_load_resource
;
6890 ctx
.abi
.clamp_shadow_reference
= false;
6892 if (shader_count
>= 2)
6893 ac_init_exec_full_mask(&ctx
.ac
);
6895 if (ctx
.ac
.chip_class
== GFX9
&&
6896 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6897 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6899 for(int i
= 0; i
< shader_count
; ++i
) {
6900 ctx
.stage
= shaders
[i
]->info
.stage
;
6901 ctx
.output_mask
= 0;
6902 ctx
.tess_outputs_written
= 0;
6903 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6904 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6906 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6907 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6908 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6909 ctx
.abi
.load_inputs
= load_gs_input
;
6910 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6911 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6912 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6913 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6914 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6915 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6916 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6917 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6918 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6919 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6920 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6921 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6922 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6923 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6924 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6925 if (shader_info
->info
.vs
.needs_instance_id
) {
6926 if (ctx
.options
->key
.vs
.as_ls
) {
6927 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6928 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6930 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6931 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6934 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6935 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6936 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
6937 ctx
.abi
.load_sample_position
= load_sample_position
;
6938 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
6942 emit_barrier(&ctx
.ac
, ctx
.stage
);
6944 ac_setup_rings(&ctx
);
6946 LLVMBasicBlockRef merge_block
;
6947 if (shader_count
>= 2) {
6948 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6949 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6950 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6952 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6953 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6954 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6955 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6956 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6957 thread_id
, count
, "");
6958 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6960 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6963 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6964 handle_fs_inputs(&ctx
, shaders
[i
]);
6965 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6966 handle_vs_inputs(&ctx
, shaders
[i
]);
6967 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6968 prepare_gs_input_vgprs(&ctx
);
6970 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6971 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6973 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
6975 if (shader_count
>= 2) {
6976 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6977 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6980 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6981 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6982 shaders
[i
]->info
.cull_distance_array_size
> 4;
6983 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6984 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6985 shaders
[i
]->info
.gs
.vertices_out
;
6986 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6987 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6988 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6989 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6990 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6994 LLVMBuildRetVoid(ctx
.ac
.builder
);
6996 if (options
->dump_preoptir
)
6997 ac_dump_module(ctx
.ac
.module
);
6999 ac_llvm_finalize_module(&ctx
);
7001 if (shader_count
== 1)
7002 ac_nir_eliminate_const_vs_outputs(&ctx
);
7004 return ctx
.ac
.module
;
7007 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
7009 unsigned *retval
= (unsigned *)context
;
7010 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
7011 char *description
= LLVMGetDiagInfoDescription(di
);
7013 if (severity
== LLVMDSError
) {
7015 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
7019 LLVMDisposeMessage(description
);
7022 static unsigned ac_llvm_compile(LLVMModuleRef M
,
7023 struct ac_shader_binary
*binary
,
7024 LLVMTargetMachineRef tm
)
7026 unsigned retval
= 0;
7028 LLVMContextRef llvm_ctx
;
7029 LLVMMemoryBufferRef out_buffer
;
7030 unsigned buffer_size
;
7031 const char *buffer_data
;
7034 /* Setup Diagnostic Handler*/
7035 llvm_ctx
= LLVMGetModuleContext(M
);
7037 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
7041 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
7044 /* Process Errors/Warnings */
7046 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
7052 /* Extract Shader Code*/
7053 buffer_size
= LLVMGetBufferSize(out_buffer
);
7054 buffer_data
= LLVMGetBufferStart(out_buffer
);
7056 ac_elf_read(buffer_data
, buffer_size
, binary
);
7059 LLVMDisposeMemoryBuffer(out_buffer
);
7065 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
7066 LLVMModuleRef llvm_module
,
7067 struct ac_shader_binary
*binary
,
7068 struct ac_shader_config
*config
,
7069 struct ac_shader_variant_info
*shader_info
,
7070 gl_shader_stage stage
,
7071 bool dump_shader
, bool supports_spill
)
7074 ac_dump_module(llvm_module
);
7076 memset(binary
, 0, sizeof(*binary
));
7077 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7079 fprintf(stderr
, "compile failed\n");
7083 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7085 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7087 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7088 LLVMDisposeModule(llvm_module
);
7089 LLVMContextDispose(ctx
);
7091 if (stage
== MESA_SHADER_FRAGMENT
) {
7092 shader_info
->num_input_vgprs
= 0;
7093 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7094 shader_info
->num_input_vgprs
+= 2;
7095 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7096 shader_info
->num_input_vgprs
+= 2;
7097 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7098 shader_info
->num_input_vgprs
+= 2;
7099 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7100 shader_info
->num_input_vgprs
+= 3;
7101 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7102 shader_info
->num_input_vgprs
+= 2;
7103 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7104 shader_info
->num_input_vgprs
+= 2;
7105 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7106 shader_info
->num_input_vgprs
+= 2;
7107 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7108 shader_info
->num_input_vgprs
+= 1;
7109 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7110 shader_info
->num_input_vgprs
+= 1;
7111 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7112 shader_info
->num_input_vgprs
+= 1;
7113 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7114 shader_info
->num_input_vgprs
+= 1;
7115 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7116 shader_info
->num_input_vgprs
+= 1;
7117 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7118 shader_info
->num_input_vgprs
+= 1;
7119 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7120 shader_info
->num_input_vgprs
+= 1;
7121 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7122 shader_info
->num_input_vgprs
+= 1;
7123 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7124 shader_info
->num_input_vgprs
+= 1;
7126 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7128 /* +3 for scratch wave offset and VCC */
7129 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7130 shader_info
->num_input_sgprs
+ 3);
7132 /* Enable 64-bit and 16-bit denormals, because there is no performance
7135 * If denormals are enabled, all floating-point output modifiers are
7138 * Don't enable denormals for 32-bit floats, because:
7139 * - Floating-point output modifiers would be ignored by the hw.
7140 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7141 * have to stop using those.
7142 * - SI & CI would be very slow.
7144 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7148 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7150 switch (nir
->info
.stage
) {
7151 case MESA_SHADER_COMPUTE
:
7152 for (int i
= 0; i
< 3; ++i
)
7153 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7155 case MESA_SHADER_FRAGMENT
:
7156 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7158 case MESA_SHADER_GEOMETRY
:
7159 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7160 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7161 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7162 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7164 case MESA_SHADER_TESS_EVAL
:
7165 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7166 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7167 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7168 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7169 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7171 case MESA_SHADER_TESS_CTRL
:
7172 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7174 case MESA_SHADER_VERTEX
:
7175 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7176 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7177 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7178 if (options
->key
.vs
.as_ls
)
7179 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7186 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7187 struct ac_shader_binary
*binary
,
7188 struct ac_shader_config
*config
,
7189 struct ac_shader_variant_info
*shader_info
,
7190 struct nir_shader
*const *nir
,
7192 const struct ac_nir_compiler_options
*options
,
7196 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7199 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7200 for (int i
= 0; i
< nir_count
; ++i
)
7201 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7203 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7204 if (options
->chip_class
== GFX9
) {
7205 if (nir_count
== 2 &&
7206 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7207 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7213 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
7215 LLVMValueRef vtx_offset
=
7216 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
7217 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7220 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
7224 if (!(ctx
->output_mask
& (1ull << i
)))
7227 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7228 /* unpack clip and cull from a single set of slots */
7229 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7234 for (unsigned j
= 0; j
< length
; j
++) {
7235 LLVMValueRef value
, soffset
;
7237 soffset
= LLVMConstInt(ctx
->ac
.i32
,
7239 ctx
->gs_max_out_vertices
* 16 * 4, false);
7241 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
7243 vtx_offset
, soffset
,
7244 0, 1, 1, true, false);
7246 LLVMBuildStore(ctx
->ac
.builder
,
7247 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7251 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7254 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7255 struct nir_shader
*geom_shader
,
7256 struct ac_shader_binary
*binary
,
7257 struct ac_shader_config
*config
,
7258 struct ac_shader_variant_info
*shader_info
,
7259 const struct ac_nir_compiler_options
*options
,
7262 struct radv_shader_context ctx
= {0};
7263 ctx
.context
= LLVMContextCreate();
7264 ctx
.options
= options
;
7265 ctx
.shader_info
= shader_info
;
7267 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7269 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7271 ctx
.is_gs_copy_shader
= true;
7272 LLVMSetTarget(ctx
.ac
.module
, "amdgcn--");
7274 enum ac_float_mode float_mode
=
7275 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7276 AC_FLOAT_MODE_DEFAULT
;
7278 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7279 ctx
.stage
= MESA_SHADER_VERTEX
;
7281 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7283 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7284 ac_setup_rings(&ctx
);
7286 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7287 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7289 struct ac_nir_context nir_ctx
= {};
7290 nir_ctx
.ac
= ctx
.ac
;
7291 nir_ctx
.abi
= &ctx
.abi
;
7293 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7294 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7295 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7298 ac_gs_copy_shader_emit(&ctx
);
7300 LLVMBuildRetVoid(ctx
.ac
.builder
);
7302 ac_llvm_finalize_module(&ctx
);
7304 ac_compile_llvm_module(tm
, ctx
.ac
.module
, binary
, config
, shader_info
,
7306 dump_shader
, options
->supports_spill
);