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ac/nir: remove nir_to_llvm_context::builder
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMValueRef main_function;
84
85 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
86 LLVMValueRef ring_offsets;
87
88 LLVMValueRef vertex_buffers;
89 LLVMValueRef rel_auto_id;
90 LLVMValueRef vs_prim_id;
91 LLVMValueRef ls_out_layout;
92 LLVMValueRef es2gs_offset;
93
94 LLVMValueRef tcs_offchip_layout;
95 LLVMValueRef tcs_out_offsets;
96 LLVMValueRef tcs_out_layout;
97 LLVMValueRef tcs_in_layout;
98 LLVMValueRef oc_lds;
99 LLVMValueRef merged_wave_info;
100 LLVMValueRef tess_factor_offset;
101 LLVMValueRef tes_rel_patch_id;
102 LLVMValueRef tes_u;
103 LLVMValueRef tes_v;
104
105 LLVMValueRef gsvs_ring_stride;
106 LLVMValueRef gsvs_num_entries;
107 LLVMValueRef gs2vs_offset;
108 LLVMValueRef gs_wave_id;
109 LLVMValueRef gs_vtx_offset[6];
110
111 LLVMValueRef esgs_ring;
112 LLVMValueRef gsvs_ring;
113 LLVMValueRef hs_ring_tess_offchip;
114 LLVMValueRef hs_ring_tess_factor;
115
116 LLVMValueRef sample_pos_offset;
117 LLVMValueRef persp_sample, persp_center, persp_centroid;
118 LLVMValueRef linear_sample, linear_center, linear_centroid;
119
120 gl_shader_stage stage;
121
122 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
123
124 uint64_t input_mask;
125 uint64_t output_mask;
126 uint8_t num_output_clips;
127 uint8_t num_output_culls;
128
129 bool is_gs_copy_shader;
130 LLVMValueRef gs_next_vertex;
131 unsigned gs_max_out_vertices;
132
133 unsigned tes_primitive_mode;
134 uint64_t tess_outputs_written;
135 uint64_t tess_patch_outputs_written;
136
137 uint32_t tcs_patch_outputs_read;
138 uint64_t tcs_outputs_read;
139 };
140
141 static inline struct nir_to_llvm_context *
142 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
143 {
144 struct nir_to_llvm_context *ctx = NULL;
145 return container_of(abi, ctx, abi);
146 }
147
148 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
149 const nir_deref_var *deref,
150 enum ac_descriptor_type desc_type,
151 const nir_tex_instr *instr,
152 bool image, bool write);
153
154 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
155 {
156 return (index * 4) + chan;
157 }
158
159 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
160 {
161 /* handle patch indices separate */
162 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
163 return 0;
164 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
165 return 1;
166 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
167 return 2 + (slot - VARYING_SLOT_PATCH0);
168
169 if (slot == VARYING_SLOT_POS)
170 return 0;
171 if (slot == VARYING_SLOT_PSIZ)
172 return 1;
173 if (slot == VARYING_SLOT_CLIP_DIST0)
174 return 2;
175 /* 3 is reserved for clip dist as well */
176 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
177 return 4 + (slot - VARYING_SLOT_VAR0);
178 unreachable("illegal slot in get unique index\n");
179 }
180
181 static void set_llvm_calling_convention(LLVMValueRef func,
182 gl_shader_stage stage)
183 {
184 enum radeon_llvm_calling_convention calling_conv;
185
186 switch (stage) {
187 case MESA_SHADER_VERTEX:
188 case MESA_SHADER_TESS_EVAL:
189 calling_conv = RADEON_LLVM_AMDGPU_VS;
190 break;
191 case MESA_SHADER_GEOMETRY:
192 calling_conv = RADEON_LLVM_AMDGPU_GS;
193 break;
194 case MESA_SHADER_TESS_CTRL:
195 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
196 break;
197 case MESA_SHADER_FRAGMENT:
198 calling_conv = RADEON_LLVM_AMDGPU_PS;
199 break;
200 case MESA_SHADER_COMPUTE:
201 calling_conv = RADEON_LLVM_AMDGPU_CS;
202 break;
203 default:
204 unreachable("Unhandle shader type");
205 }
206
207 LLVMSetFunctionCallConv(func, calling_conv);
208 }
209
210 #define MAX_ARGS 23
211 struct arg_info {
212 LLVMTypeRef types[MAX_ARGS];
213 LLVMValueRef *assign[MAX_ARGS];
214 unsigned array_params_mask;
215 uint8_t count;
216 uint8_t sgpr_count;
217 uint8_t num_sgprs_used;
218 uint8_t num_vgprs_used;
219 };
220
221 enum ac_arg_regfile {
222 ARG_SGPR,
223 ARG_VGPR,
224 };
225
226 static void
227 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
228 LLVMValueRef *param_ptr)
229 {
230 assert(info->count < MAX_ARGS);
231
232 info->assign[info->count] = param_ptr;
233 info->types[info->count] = type;
234 info->count++;
235
236 if (regfile == ARG_SGPR) {
237 info->num_sgprs_used += ac_get_type_size(type) / 4;
238 info->sgpr_count++;
239 } else {
240 assert(regfile == ARG_VGPR);
241 info->num_vgprs_used += ac_get_type_size(type) / 4;
242 }
243 }
244
245 static inline void
246 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
247 {
248 info->array_params_mask |= (1 << info->count);
249 add_arg(info, ARG_SGPR, type, param_ptr);
250 }
251
252 static void assign_arguments(LLVMValueRef main_function,
253 struct arg_info *info)
254 {
255 unsigned i;
256 for (i = 0; i < info->count; i++) {
257 if (info->assign[i])
258 *info->assign[i] = LLVMGetParam(main_function, i);
259 }
260 }
261
262 static LLVMValueRef
263 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
264 LLVMBuilderRef builder, LLVMTypeRef *return_types,
265 unsigned num_return_elems,
266 struct arg_info *args,
267 unsigned max_workgroup_size,
268 bool unsafe_math)
269 {
270 LLVMTypeRef main_function_type, ret_type;
271 LLVMBasicBlockRef main_function_body;
272
273 if (num_return_elems)
274 ret_type = LLVMStructTypeInContext(ctx, return_types,
275 num_return_elems, true);
276 else
277 ret_type = LLVMVoidTypeInContext(ctx);
278
279 /* Setup the function */
280 main_function_type =
281 LLVMFunctionType(ret_type, args->types, args->count, 0);
282 LLVMValueRef main_function =
283 LLVMAddFunction(module, "main", main_function_type);
284 main_function_body =
285 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
286 LLVMPositionBuilderAtEnd(builder, main_function_body);
287
288 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
289 for (unsigned i = 0; i < args->sgpr_count; ++i) {
290 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
291
292 if (args->array_params_mask & (1 << i)) {
293 LLVMValueRef P = LLVMGetParam(main_function, i);
294 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
295 ac_add_attr_dereferenceable(P, UINT64_MAX);
296 }
297 }
298
299 if (max_workgroup_size) {
300 ac_llvm_add_target_dep_function_attr(main_function,
301 "amdgpu-max-work-group-size",
302 max_workgroup_size);
303 }
304 if (unsafe_math) {
305 /* These were copied from some LLVM test. */
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "less-precise-fpmad",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "no-infs-fp-math",
311 "true");
312 LLVMAddTargetDependentFunctionAttr(main_function,
313 "no-nans-fp-math",
314 "true");
315 LLVMAddTargetDependentFunctionAttr(main_function,
316 "unsafe-fp-math",
317 "true");
318 LLVMAddTargetDependentFunctionAttr(main_function,
319 "no-signed-zeros-fp-math",
320 "true");
321 }
322 return main_function;
323 }
324
325 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
326 LLVMValueRef param, unsigned rshift,
327 unsigned bitwidth)
328 {
329 LLVMValueRef value = param;
330 if (rshift)
331 value = LLVMBuildLShr(ctx->builder, value,
332 LLVMConstInt(ctx->i32, rshift, false), "");
333
334 if (rshift + bitwidth < 32) {
335 unsigned mask = (1 << bitwidth) - 1;
336 value = LLVMBuildAnd(ctx->builder, value,
337 LLVMConstInt(ctx->i32, mask, false), "");
338 }
339 return value;
340 }
341
342 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
343 {
344 switch (ctx->stage) {
345 case MESA_SHADER_TESS_CTRL:
346 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
347 case MESA_SHADER_TESS_EVAL:
348 return ctx->tes_rel_patch_id;
349 break;
350 default:
351 unreachable("Illegal stage");
352 }
353 }
354
355 /* Tessellation shaders pass outputs to the next shader using LDS.
356 *
357 * LS outputs = TCS inputs
358 * TCS outputs = TES inputs
359 *
360 * The LDS layout is:
361 * - TCS inputs for patch 0
362 * - TCS inputs for patch 1
363 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
364 * - ...
365 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
366 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
367 * - TCS outputs for patch 1
368 * - Per-patch TCS outputs for patch 1
369 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
370 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
371 * - ...
372 *
373 * All three shaders VS(LS), TCS, TES share the same LDS space.
374 */
375 static LLVMValueRef
376 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
377 {
378 if (ctx->stage == MESA_SHADER_VERTEX)
379 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
380 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
381 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
382 else {
383 assert(0);
384 return NULL;
385 }
386 }
387
388 static LLVMValueRef
389 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
390 {
391 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
392 }
393
394 static LLVMValueRef
395 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
396 {
397 return LLVMBuildMul(ctx->ac.builder,
398 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
399 LLVMConstInt(ctx->ac.i32, 4, false), "");
400 }
401
402 static LLVMValueRef
403 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
404 {
405 return LLVMBuildMul(ctx->ac.builder,
406 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
407 LLVMConstInt(ctx->ac.i32, 4, false), "");
408 }
409
410 static LLVMValueRef
411 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
412 {
413 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
414 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
415
416 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
417 }
418
419 static LLVMValueRef
420 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
421 {
422 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
423 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
424 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
425
426 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
427 LLVMBuildMul(ctx->ac.builder, patch_stride,
428 rel_patch_id, ""),
429 "");
430 }
431
432 static LLVMValueRef
433 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
434 {
435 LLVMValueRef patch0_patch_data_offset =
436 get_tcs_out_patch0_patch_data_offset(ctx);
437 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
438 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
439
440 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
441 LLVMBuildMul(ctx->ac.builder, patch_stride,
442 rel_patch_id, ""),
443 "");
444 }
445
446 static void
447 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
448 uint32_t indirect_offset)
449 {
450 ud_info->sgpr_idx = *sgpr_idx;
451 ud_info->num_sgprs = num_sgprs;
452 ud_info->indirect = indirect_offset > 0;
453 ud_info->indirect_offset = indirect_offset;
454 *sgpr_idx += num_sgprs;
455 }
456
457 static void
458 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
459 uint8_t num_sgprs)
460 {
461 struct ac_userdata_info *ud_info =
462 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
463 assert(ud_info);
464
465 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
466 }
467
468 static void
469 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
470 uint32_t indirect_offset)
471 {
472 struct ac_userdata_info *ud_info =
473 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
474 assert(ud_info);
475
476 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
477 }
478
479 struct user_sgpr_info {
480 bool need_ring_offsets;
481 uint8_t sgpr_count;
482 bool indirect_all_descriptor_sets;
483 };
484
485 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
486 gl_shader_stage stage)
487 {
488 switch (stage) {
489 case MESA_SHADER_VERTEX:
490 if (ctx->shader_info->info.needs_multiview_view_index ||
491 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
492 return true;
493 break;
494 case MESA_SHADER_TESS_EVAL:
495 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
496 return true;
497 break;
498 case MESA_SHADER_GEOMETRY:
499 case MESA_SHADER_TESS_CTRL:
500 if (ctx->shader_info->info.needs_multiview_view_index)
501 return true;
502 break;
503 default:
504 break;
505 }
506 return false;
507 }
508
509 static uint8_t
510 count_vs_user_sgprs(struct nir_to_llvm_context *ctx)
511 {
512 uint8_t count = 0;
513
514 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
515 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
516
517 return count;
518 }
519
520 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
521 gl_shader_stage stage,
522 bool has_previous_stage,
523 gl_shader_stage previous_stage,
524 bool needs_view_index,
525 struct user_sgpr_info *user_sgpr_info)
526 {
527 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
528
529 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
530 if (stage == MESA_SHADER_GEOMETRY ||
531 stage == MESA_SHADER_VERTEX ||
532 stage == MESA_SHADER_TESS_CTRL ||
533 stage == MESA_SHADER_TESS_EVAL ||
534 ctx->is_gs_copy_shader)
535 user_sgpr_info->need_ring_offsets = true;
536
537 if (stage == MESA_SHADER_FRAGMENT &&
538 ctx->shader_info->info.ps.needs_sample_positions)
539 user_sgpr_info->need_ring_offsets = true;
540
541 /* 2 user sgprs will nearly always be allocated for scratch/rings */
542 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
543 user_sgpr_info->sgpr_count += 2;
544 }
545
546 switch (stage) {
547 case MESA_SHADER_COMPUTE:
548 if (ctx->shader_info->info.cs.uses_grid_size)
549 user_sgpr_info->sgpr_count += 3;
550 break;
551 case MESA_SHADER_FRAGMENT:
552 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
553 break;
554 case MESA_SHADER_VERTEX:
555 if (!ctx->is_gs_copy_shader)
556 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
557 if (ctx->options->key.vs.as_ls)
558 user_sgpr_info->sgpr_count++;
559 break;
560 case MESA_SHADER_TESS_CTRL:
561 if (has_previous_stage) {
562 if (previous_stage == MESA_SHADER_VERTEX)
563 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
564 user_sgpr_info->sgpr_count++;
565 }
566 user_sgpr_info->sgpr_count += 4;
567 break;
568 case MESA_SHADER_TESS_EVAL:
569 user_sgpr_info->sgpr_count += 1;
570 break;
571 case MESA_SHADER_GEOMETRY:
572 if (has_previous_stage) {
573 if (previous_stage == MESA_SHADER_VERTEX) {
574 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
575 } else {
576 user_sgpr_info->sgpr_count++;
577 }
578 }
579 user_sgpr_info->sgpr_count += 2;
580 break;
581 default:
582 break;
583 }
584
585 if (needs_view_index)
586 user_sgpr_info->sgpr_count++;
587
588 if (ctx->shader_info->info.loads_push_constants)
589 user_sgpr_info->sgpr_count += 2;
590
591 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
592 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
593
594 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
595 user_sgpr_info->sgpr_count += 2;
596 user_sgpr_info->indirect_all_descriptor_sets = true;
597 } else {
598 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
599 }
600 }
601
602 static void
603 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
604 gl_shader_stage stage,
605 bool has_previous_stage,
606 gl_shader_stage previous_stage,
607 const struct user_sgpr_info *user_sgpr_info,
608 struct arg_info *args,
609 LLVMValueRef *desc_sets)
610 {
611 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
612 unsigned num_sets = ctx->options->layout ?
613 ctx->options->layout->num_sets : 0;
614 unsigned stage_mask = 1 << stage;
615
616 if (has_previous_stage)
617 stage_mask |= 1 << previous_stage;
618
619 /* 1 for each descriptor set */
620 if (!user_sgpr_info->indirect_all_descriptor_sets) {
621 for (unsigned i = 0; i < num_sets; ++i) {
622 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
623 add_array_arg(args, type,
624 &ctx->descriptor_sets[i]);
625 }
626 }
627 } else {
628 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
629 }
630
631 if (ctx->shader_info->info.loads_push_constants) {
632 /* 1 for push constants and dynamic descriptors */
633 add_array_arg(args, type, &ctx->abi.push_constants);
634 }
635 }
636
637 static void
638 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
639 gl_shader_stage stage,
640 bool has_previous_stage,
641 gl_shader_stage previous_stage,
642 struct arg_info *args)
643 {
644 if (!ctx->is_gs_copy_shader &&
645 (stage == MESA_SHADER_VERTEX ||
646 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
647 if (ctx->shader_info->info.vs.has_vertex_buffers) {
648 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
649 &ctx->vertex_buffers);
650 }
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
652 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
653 if (ctx->shader_info->info.vs.needs_draw_id) {
654 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
655 }
656 }
657 }
658
659 static void
660 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
661 {
662 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
663 if (!ctx->is_gs_copy_shader) {
664 if (ctx->options->key.vs.as_ls) {
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
666 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
667 } else {
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
669 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
670 }
671 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
672 }
673 }
674
675 static void
676 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
677 {
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
679 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
682 }
683
684 static void
685 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
686 bool has_previous_stage, gl_shader_stage previous_stage,
687 const struct user_sgpr_info *user_sgpr_info,
688 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
689 {
690 unsigned num_sets = ctx->options->layout ?
691 ctx->options->layout->num_sets : 0;
692 unsigned stage_mask = 1 << stage;
693
694 if (has_previous_stage)
695 stage_mask |= 1 << previous_stage;
696
697 if (!user_sgpr_info->indirect_all_descriptor_sets) {
698 for (unsigned i = 0; i < num_sets; ++i) {
699 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
710 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
711 ctx->descriptor_sets[i] =
712 ac_build_load_to_sgpr(&ctx->ac,
713 desc_sets,
714 LLVMConstInt(ctx->ac.i32, i, false));
715
716 } else
717 ctx->descriptor_sets[i] = NULL;
718 }
719 ctx->shader_info->need_indirect_descriptor_sets = true;
720 }
721
722 if (ctx->shader_info->info.loads_push_constants) {
723 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
724 }
725 }
726
727 static void
728 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
729 gl_shader_stage stage, bool has_previous_stage,
730 gl_shader_stage previous_stage,
731 uint8_t *user_sgpr_idx)
732 {
733 if (!ctx->is_gs_copy_shader &&
734 (stage == MESA_SHADER_VERTEX ||
735 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
736 if (ctx->shader_info->info.vs.has_vertex_buffers) {
737 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
738 user_sgpr_idx, 2);
739 }
740
741 unsigned vs_num = 2;
742 if (ctx->shader_info->info.vs.needs_draw_id)
743 vs_num++;
744
745 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
746 user_sgpr_idx, vs_num);
747 }
748 }
749
750 static void create_function(struct nir_to_llvm_context *ctx,
751 gl_shader_stage stage,
752 bool has_previous_stage,
753 gl_shader_stage previous_stage)
754 {
755 uint8_t user_sgpr_idx;
756 struct user_sgpr_info user_sgpr_info;
757 struct arg_info args = {};
758 LLVMValueRef desc_sets;
759 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
760 allocate_user_sgprs(ctx, stage, has_previous_stage,
761 previous_stage, needs_view_index, &user_sgpr_info);
762
763 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
764 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
765 &ctx->ring_offsets);
766 }
767
768 switch (stage) {
769 case MESA_SHADER_COMPUTE:
770 declare_global_input_sgprs(ctx, stage, has_previous_stage,
771 previous_stage, &user_sgpr_info,
772 &args, &desc_sets);
773
774 if (ctx->shader_info->info.cs.uses_grid_size) {
775 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
776 &ctx->abi.num_work_groups);
777 }
778
779 for (int i = 0; i < 3; i++) {
780 ctx->abi.workgroup_ids[i] = NULL;
781 if (ctx->shader_info->info.cs.uses_block_id[i]) {
782 add_arg(&args, ARG_SGPR, ctx->ac.i32,
783 &ctx->abi.workgroup_ids[i]);
784 }
785 }
786
787 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
788 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
789 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
790 &ctx->abi.local_invocation_ids);
791 break;
792 case MESA_SHADER_VERTEX:
793 declare_global_input_sgprs(ctx, stage, has_previous_stage,
794 previous_stage, &user_sgpr_info,
795 &args, &desc_sets);
796 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
797 previous_stage, &args);
798
799 if (needs_view_index)
800 add_arg(&args, ARG_SGPR, ctx->ac.i32,
801 &ctx->abi.view_index);
802 if (ctx->options->key.vs.as_es)
803 add_arg(&args, ARG_SGPR, ctx->ac.i32,
804 &ctx->es2gs_offset);
805 else if (ctx->options->key.vs.as_ls)
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->ls_out_layout);
808
809 declare_vs_input_vgprs(ctx, &args);
810 break;
811 case MESA_SHADER_TESS_CTRL:
812 if (has_previous_stage) {
813 // First 6 system regs
814 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
815 add_arg(&args, ARG_SGPR, ctx->ac.i32,
816 &ctx->merged_wave_info);
817 add_arg(&args, ARG_SGPR, ctx->ac.i32,
818 &ctx->tess_factor_offset);
819
820 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823
824 declare_global_input_sgprs(ctx, stage,
825 has_previous_stage,
826 previous_stage,
827 &user_sgpr_info, &args,
828 &desc_sets);
829 declare_vs_specific_input_sgprs(ctx, stage,
830 has_previous_stage,
831 previous_stage, &args);
832
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->ls_out_layout);
835
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->tcs_offchip_layout);
838 add_arg(&args, ARG_SGPR, ctx->ac.i32,
839 &ctx->tcs_out_offsets);
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_out_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_in_layout);
844 if (needs_view_index)
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->abi.view_index);
847
848 add_arg(&args, ARG_VGPR, ctx->ac.i32,
849 &ctx->abi.tcs_patch_id);
850 add_arg(&args, ARG_VGPR, ctx->ac.i32,
851 &ctx->abi.tcs_rel_ids);
852
853 declare_vs_input_vgprs(ctx, &args);
854 } else {
855 declare_global_input_sgprs(ctx, stage,
856 has_previous_stage,
857 previous_stage,
858 &user_sgpr_info, &args,
859 &desc_sets);
860
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->tcs_offchip_layout);
863 add_arg(&args, ARG_SGPR, ctx->ac.i32,
864 &ctx->tcs_out_offsets);
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_out_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_in_layout);
869 if (needs_view_index)
870 add_arg(&args, ARG_SGPR, ctx->ac.i32,
871 &ctx->abi.view_index);
872
873 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->tess_factor_offset);
876 add_arg(&args, ARG_VGPR, ctx->ac.i32,
877 &ctx->abi.tcs_patch_id);
878 add_arg(&args, ARG_VGPR, ctx->ac.i32,
879 &ctx->abi.tcs_rel_ids);
880 }
881 break;
882 case MESA_SHADER_TESS_EVAL:
883 declare_global_input_sgprs(ctx, stage, has_previous_stage,
884 previous_stage, &user_sgpr_info,
885 &args, &desc_sets);
886
887 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
888 if (needs_view_index)
889 add_arg(&args, ARG_SGPR, ctx->ac.i32,
890 &ctx->abi.view_index);
891
892 if (ctx->options->key.tes.as_es) {
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->es2gs_offset);
897 } else {
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
900 }
901 declare_tes_input_vgprs(ctx, &args);
902 break;
903 case MESA_SHADER_GEOMETRY:
904 if (has_previous_stage) {
905 // First 6 system regs
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->gs2vs_offset);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32,
909 &ctx->merged_wave_info);
910 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915
916 declare_global_input_sgprs(ctx, stage,
917 has_previous_stage,
918 previous_stage,
919 &user_sgpr_info, &args,
920 &desc_sets);
921
922 if (previous_stage == MESA_SHADER_TESS_EVAL) {
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->tcs_offchip_layout);
925 } else {
926 declare_vs_specific_input_sgprs(ctx, stage,
927 has_previous_stage,
928 previous_stage,
929 &args);
930 }
931
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->gsvs_ring_stride);
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->gsvs_num_entries);
936 if (needs_view_index)
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->abi.view_index);
939
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->gs_vtx_offset[0]);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->abi.gs_prim_id);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->abi.gs_invocation_id);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[4]);
950
951 if (previous_stage == MESA_SHADER_VERTEX) {
952 declare_vs_input_vgprs(ctx, &args);
953 } else {
954 declare_tes_input_vgprs(ctx, &args);
955 }
956 } else {
957 declare_global_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage,
960 &user_sgpr_info, &args,
961 &desc_sets);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32,
964 &ctx->gsvs_ring_stride);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->gsvs_num_entries);
967 if (needs_view_index)
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->abi.view_index);
970
971 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[0]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[1]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_prim_id);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[2]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[3]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[4]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[5]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.gs_invocation_id);
989 }
990 break;
991 case MESA_SHADER_FRAGMENT:
992 declare_global_input_sgprs(ctx, stage, has_previous_stage,
993 previous_stage, &user_sgpr_info,
994 &args, &desc_sets);
995
996 if (ctx->shader_info->info.ps.needs_sample_positions)
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->sample_pos_offset);
999
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1008 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1017 break;
1018 default:
1019 unreachable("Shader stage not implemented");
1020 }
1021
1022 ctx->main_function = create_llvm_function(
1023 ctx->context, ctx->module, ctx->ac.builder, NULL, 0, &args,
1024 ctx->max_workgroup_size,
1025 ctx->options->unsafe_math);
1026 set_llvm_calling_convention(ctx->main_function, stage);
1027
1028
1029 ctx->shader_info->num_input_vgprs = 0;
1030 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1031
1032 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1033
1034 if (ctx->stage != MESA_SHADER_FRAGMENT)
1035 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1036
1037 assign_arguments(ctx->main_function, &args);
1038
1039 user_sgpr_idx = 0;
1040
1041 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1042 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1043 &user_sgpr_idx, 2);
1044 if (ctx->options->supports_spill) {
1045 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1046 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1047 NULL, 0, AC_FUNC_ATTR_READNONE);
1048 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1049 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1050 }
1051 }
1052
1053 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1054 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1055 if (has_previous_stage)
1056 user_sgpr_idx = 0;
1057
1058 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1059 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1060
1061 switch (stage) {
1062 case MESA_SHADER_COMPUTE:
1063 if (ctx->shader_info->info.cs.uses_grid_size) {
1064 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1065 &user_sgpr_idx, 3);
1066 }
1067 break;
1068 case MESA_SHADER_VERTEX:
1069 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1070 previous_stage, &user_sgpr_idx);
1071 if (ctx->abi.view_index)
1072 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 if (ctx->options->key.vs.as_ls) {
1074 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1075 &user_sgpr_idx, 1);
1076 }
1077 if (ctx->options->key.vs.as_ls)
1078 ac_declare_lds_as_pointer(&ctx->ac);
1079 break;
1080 case MESA_SHADER_TESS_CTRL:
1081 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1082 previous_stage, &user_sgpr_idx);
1083 if (has_previous_stage)
1084 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1085 &user_sgpr_idx, 1);
1086 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1087 if (ctx->abi.view_index)
1088 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1089 ac_declare_lds_as_pointer(&ctx->ac);
1090 break;
1091 case MESA_SHADER_TESS_EVAL:
1092 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1093 if (ctx->abi.view_index)
1094 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 break;
1096 case MESA_SHADER_GEOMETRY:
1097 if (has_previous_stage) {
1098 if (previous_stage == MESA_SHADER_VERTEX)
1099 set_vs_specific_input_locs(ctx, stage,
1100 has_previous_stage,
1101 previous_stage,
1102 &user_sgpr_idx);
1103 else
1104 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1105 &user_sgpr_idx, 1);
1106 }
1107 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1108 &user_sgpr_idx, 2);
1109 if (ctx->abi.view_index)
1110 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1111 if (has_previous_stage)
1112 ac_declare_lds_as_pointer(&ctx->ac);
1113 break;
1114 case MESA_SHADER_FRAGMENT:
1115 if (ctx->shader_info->info.ps.needs_sample_positions) {
1116 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1117 &user_sgpr_idx, 1);
1118 }
1119 break;
1120 default:
1121 unreachable("Shader stage not implemented");
1122 }
1123
1124 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1125 }
1126
1127 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1128 LLVMValueRef value, unsigned count)
1129 {
1130 unsigned num_components = ac_get_llvm_num_components(value);
1131 if (count == num_components)
1132 return value;
1133
1134 LLVMValueRef masks[] = {
1135 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1136 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1137
1138 if (count == 1)
1139 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1140 "");
1141
1142 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1143 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1144 }
1145
1146 static void
1147 build_store_values_extended(struct ac_llvm_context *ac,
1148 LLVMValueRef *values,
1149 unsigned value_count,
1150 unsigned value_stride,
1151 LLVMValueRef vec)
1152 {
1153 LLVMBuilderRef builder = ac->builder;
1154 unsigned i;
1155
1156 for (i = 0; i < value_count; i++) {
1157 LLVMValueRef ptr = values[i * value_stride];
1158 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1159 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1160 LLVMBuildStore(builder, value, ptr);
1161 }
1162 }
1163
1164 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1165 const nir_ssa_def *def)
1166 {
1167 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1168 if (def->num_components > 1) {
1169 type = LLVMVectorType(type, def->num_components);
1170 }
1171 return type;
1172 }
1173
1174 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1175 {
1176 assert(src.is_ssa);
1177 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1178 return (LLVMValueRef)entry->data;
1179 }
1180
1181
1182 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1183 const struct nir_block *b)
1184 {
1185 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1186 return (LLVMBasicBlockRef)entry->data;
1187 }
1188
1189 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1190 nir_alu_src src,
1191 unsigned num_components)
1192 {
1193 LLVMValueRef value = get_src(ctx, src.src);
1194 bool need_swizzle = false;
1195
1196 assert(value);
1197 LLVMTypeRef type = LLVMTypeOf(value);
1198 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1199 ? LLVMGetVectorSize(type)
1200 : 1;
1201
1202 for (unsigned i = 0; i < num_components; ++i) {
1203 assert(src.swizzle[i] < src_components);
1204 if (src.swizzle[i] != i)
1205 need_swizzle = true;
1206 }
1207
1208 if (need_swizzle || num_components != src_components) {
1209 LLVMValueRef masks[] = {
1210 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1214
1215 if (src_components > 1 && num_components == 1) {
1216 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1217 masks[0], "");
1218 } else if (src_components == 1 && num_components > 1) {
1219 LLVMValueRef values[] = {value, value, value, value};
1220 value = ac_build_gather_values(&ctx->ac, values, num_components);
1221 } else {
1222 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1223 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1224 swizzle, "");
1225 }
1226 }
1227 assert(!src.negate);
1228 assert(!src.abs);
1229 return value;
1230 }
1231
1232 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1233 LLVMIntPredicate pred, LLVMValueRef src0,
1234 LLVMValueRef src1)
1235 {
1236 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1237 return LLVMBuildSelect(ctx->builder, result,
1238 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1239 ctx->i32_0, "");
1240 }
1241
1242 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1243 LLVMRealPredicate pred, LLVMValueRef src0,
1244 LLVMValueRef src1)
1245 {
1246 LLVMValueRef result;
1247 src0 = ac_to_float(ctx, src0);
1248 src1 = ac_to_float(ctx, src1);
1249 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1256 const char *intrin,
1257 LLVMTypeRef result_type,
1258 LLVMValueRef src0)
1259 {
1260 char name[64];
1261 LLVMValueRef params[] = {
1262 ac_to_float(ctx, src0),
1263 };
1264
1265 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1266 ac_get_elem_bits(ctx, result_type));
1267 assert(length < sizeof(name));
1268 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1269 }
1270
1271 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1272 const char *intrin,
1273 LLVMTypeRef result_type,
1274 LLVMValueRef src0, LLVMValueRef src1)
1275 {
1276 char name[64];
1277 LLVMValueRef params[] = {
1278 ac_to_float(ctx, src0),
1279 ac_to_float(ctx, src1),
1280 };
1281
1282 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1283 ac_get_elem_bits(ctx, result_type));
1284 assert(length < sizeof(name));
1285 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1286 }
1287
1288 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1289 const char *intrin,
1290 LLVMTypeRef result_type,
1291 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1292 {
1293 char name[64];
1294 LLVMValueRef params[] = {
1295 ac_to_float(ctx, src0),
1296 ac_to_float(ctx, src1),
1297 ac_to_float(ctx, src2),
1298 };
1299
1300 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1301 ac_get_elem_bits(ctx, result_type));
1302 assert(length < sizeof(name));
1303 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1304 }
1305
1306 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1307 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1308 {
1309 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1310 ctx->i32_0, "");
1311 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1312 }
1313
1314 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1315 LLVMIntPredicate pred,
1316 LLVMValueRef src0, LLVMValueRef src1)
1317 {
1318 return LLVMBuildSelect(ctx->builder,
1319 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1320 src0,
1321 src1, "");
1322
1323 }
1324 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1328 LLVMBuildNeg(ctx->builder, src0, ""));
1329 }
1330
1331 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0,
1333 unsigned bitsize)
1334 {
1335 LLVMValueRef cmp, val, zero, one;
1336 LLVMTypeRef type;
1337
1338 if (bitsize == 32) {
1339 type = ctx->f32;
1340 zero = ctx->f32_0;
1341 one = ctx->f32_1;
1342 } else {
1343 type = ctx->f64;
1344 zero = ctx->f64_0;
1345 one = ctx->f64_1;
1346 }
1347
1348 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1349 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1350 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1351 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1352 return val;
1353 }
1354
1355 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1356 LLVMValueRef src0, unsigned bitsize)
1357 {
1358 LLVMValueRef cmp, val, zero, one;
1359 LLVMTypeRef type;
1360
1361 if (bitsize == 32) {
1362 type = ctx->i32;
1363 zero = ctx->i32_0;
1364 one = ctx->i32_1;
1365 } else {
1366 type = ctx->i64;
1367 zero = ctx->i64_0;
1368 one = ctx->i64_1;
1369 }
1370
1371 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1372 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1373 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1374 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1375 return val;
1376 }
1377
1378 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1379 LLVMValueRef src0, unsigned bitsize)
1380 {
1381 LLVMTypeRef type;
1382 char *intr;
1383
1384 if (bitsize == 32) {
1385 intr = "llvm.floor.f32";
1386 type = ctx->f32;
1387 } else {
1388 intr = "llvm.floor.f64";
1389 type = ctx->f64;
1390 }
1391
1392 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1393 LLVMValueRef params[] = {
1394 fsrc0,
1395 };
1396 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1397 AC_FUNC_ATTR_READNONE);
1398 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1399 }
1400
1401 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1402 const char *intrin,
1403 LLVMValueRef src0, LLVMValueRef src1)
1404 {
1405 LLVMTypeRef ret_type;
1406 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1407 LLVMValueRef res;
1408 LLVMValueRef params[] = { src0, src1 };
1409 ret_type = LLVMStructTypeInContext(ctx->context, types,
1410 2, true);
1411
1412 res = ac_build_intrinsic(ctx, intrin, ret_type,
1413 params, 2, AC_FUNC_ATTR_READNONE);
1414
1415 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1416 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1417 return res;
1418 }
1419
1420 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1421 LLVMValueRef src0)
1422 {
1423 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1424 }
1425
1426 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 src0 = ac_to_float(ctx, src0);
1430 return LLVMBuildSExt(ctx->builder,
1431 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1432 ctx->i32, "");
1433 }
1434
1435 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1436 LLVMValueRef src0,
1437 unsigned bitsize)
1438 {
1439 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1440
1441 if (bitsize == 32)
1442 return result;
1443
1444 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1445 }
1446
1447 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1448 LLVMValueRef src0)
1449 {
1450 return LLVMBuildSExt(ctx->builder,
1451 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1452 ctx->i32, "");
1453 }
1454
1455 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1456 LLVMValueRef src0)
1457 {
1458 LLVMValueRef result;
1459 LLVMValueRef cond = NULL;
1460
1461 src0 = ac_to_float(ctx, src0);
1462 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1463
1464 if (ctx->chip_class >= VI) {
1465 LLVMValueRef args[2];
1466 /* Check if the result is a denormal - and flush to 0 if so. */
1467 args[0] = result;
1468 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1469 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1470 }
1471
1472 /* need to convert back up to f32 */
1473 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1474
1475 if (ctx->chip_class >= VI)
1476 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1477 else {
1478 /* for SI/CIK */
1479 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1480 * so compare the result and flush to 0 if it's smaller.
1481 */
1482 LLVMValueRef temp, cond2;
1483 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1484 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1485 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1486 temp, "");
1487 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1488 temp, ctx->f32_0, "");
1489 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1490 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1491 }
1492 return result;
1493 }
1494
1495 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1496 LLVMValueRef src0, LLVMValueRef src1)
1497 {
1498 LLVMValueRef dst64, result;
1499 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1500 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1501
1502 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1503 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1504 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1505 return result;
1506 }
1507
1508 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1509 LLVMValueRef src0, LLVMValueRef src1)
1510 {
1511 LLVMValueRef dst64, result;
1512 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1513 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1514
1515 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1516 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1517 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1522 bool is_signed,
1523 const LLVMValueRef srcs[3])
1524 {
1525 LLVMValueRef result;
1526 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1527
1528 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1529 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1530 return result;
1531 }
1532
1533 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1534 LLVMValueRef src0, LLVMValueRef src1,
1535 LLVMValueRef src2, LLVMValueRef src3)
1536 {
1537 LLVMValueRef bfi_args[3], result;
1538
1539 bfi_args[0] = LLVMBuildShl(ctx->builder,
1540 LLVMBuildSub(ctx->builder,
1541 LLVMBuildShl(ctx->builder,
1542 ctx->i32_1,
1543 src3, ""),
1544 ctx->i32_1, ""),
1545 src2, "");
1546 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1547 bfi_args[2] = src0;
1548
1549 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1550
1551 /* Calculate:
1552 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1553 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1554 */
1555 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1556 LLVMBuildAnd(ctx->builder, bfi_args[0],
1557 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1558
1559 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1560 return result;
1561 }
1562
1563 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0)
1565 {
1566 LLVMValueRef comp[2];
1567
1568 src0 = ac_to_float(ctx, src0);
1569 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1570 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1571
1572 return ac_build_cvt_pkrtz_f16(ctx, comp);
1573 }
1574
1575 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1576 LLVMValueRef src0)
1577 {
1578 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1579 LLVMValueRef temps[2], result, val;
1580 int i;
1581
1582 for (i = 0; i < 2; i++) {
1583 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1584 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1585 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1586 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1587 }
1588
1589 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1590 ctx->i32_0, "");
1591 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1592 ctx->i32_1, "");
1593 return result;
1594 }
1595
1596 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1597 nir_op op,
1598 LLVMValueRef src0)
1599 {
1600 unsigned mask;
1601 int idx;
1602 LLVMValueRef result;
1603
1604 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1605 mask = AC_TID_MASK_LEFT;
1606 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1607 mask = AC_TID_MASK_TOP;
1608 else
1609 mask = AC_TID_MASK_TOP_LEFT;
1610
1611 /* for DDX we want to next X pixel, DDY next Y pixel. */
1612 if (op == nir_op_fddx_fine ||
1613 op == nir_op_fddx_coarse ||
1614 op == nir_op_fddx)
1615 idx = 1;
1616 else
1617 idx = 2;
1618
1619 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1620 return result;
1621 }
1622
1623 /*
1624 * this takes an I,J coordinate pair,
1625 * and works out the X and Y derivatives.
1626 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1627 */
1628 static LLVMValueRef emit_ddxy_interp(
1629 struct ac_nir_context *ctx,
1630 LLVMValueRef interp_ij)
1631 {
1632 LLVMValueRef result[4], a;
1633 unsigned i;
1634
1635 for (i = 0; i < 2; i++) {
1636 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1637 LLVMConstInt(ctx->ac.i32, i, false), "");
1638 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1639 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1640 }
1641 return ac_build_gather_values(&ctx->ac, result, 4);
1642 }
1643
1644 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1645 {
1646 LLVMValueRef src[4], result = NULL;
1647 unsigned num_components = instr->dest.dest.ssa.num_components;
1648 unsigned src_components;
1649 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1650
1651 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1652 switch (instr->op) {
1653 case nir_op_vec2:
1654 case nir_op_vec3:
1655 case nir_op_vec4:
1656 src_components = 1;
1657 break;
1658 case nir_op_pack_half_2x16:
1659 src_components = 2;
1660 break;
1661 case nir_op_unpack_half_2x16:
1662 src_components = 1;
1663 break;
1664 default:
1665 src_components = num_components;
1666 break;
1667 }
1668 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1669 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1670
1671 switch (instr->op) {
1672 case nir_op_fmov:
1673 case nir_op_imov:
1674 result = src[0];
1675 break;
1676 case nir_op_fneg:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1679 break;
1680 case nir_op_ineg:
1681 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1682 break;
1683 case nir_op_inot:
1684 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1685 break;
1686 case nir_op_iadd:
1687 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1688 break;
1689 case nir_op_fadd:
1690 src[0] = ac_to_float(&ctx->ac, src[0]);
1691 src[1] = ac_to_float(&ctx->ac, src[1]);
1692 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1693 break;
1694 case nir_op_fsub:
1695 src[0] = ac_to_float(&ctx->ac, src[0]);
1696 src[1] = ac_to_float(&ctx->ac, src[1]);
1697 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_isub:
1700 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_imul:
1703 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1704 break;
1705 case nir_op_imod:
1706 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_umod:
1709 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_fmod:
1712 src[0] = ac_to_float(&ctx->ac, src[0]);
1713 src[1] = ac_to_float(&ctx->ac, src[1]);
1714 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1715 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1716 ac_to_float_type(&ctx->ac, def_type), result);
1717 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1718 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1719 break;
1720 case nir_op_frem:
1721 src[0] = ac_to_float(&ctx->ac, src[0]);
1722 src[1] = ac_to_float(&ctx->ac, src[1]);
1723 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1724 break;
1725 case nir_op_irem:
1726 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1727 break;
1728 case nir_op_idiv:
1729 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1730 break;
1731 case nir_op_udiv:
1732 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1733 break;
1734 case nir_op_fmul:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 src[1] = ac_to_float(&ctx->ac, src[1]);
1737 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_frcp:
1740 src[0] = ac_to_float(&ctx->ac, src[0]);
1741 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1742 src[0]);
1743 break;
1744 case nir_op_iand:
1745 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1746 break;
1747 case nir_op_ior:
1748 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1749 break;
1750 case nir_op_ixor:
1751 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_ishl:
1754 result = LLVMBuildShl(ctx->ac.builder, src[0],
1755 LLVMBuildZExt(ctx->ac.builder, src[1],
1756 LLVMTypeOf(src[0]), ""),
1757 "");
1758 break;
1759 case nir_op_ishr:
1760 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1761 LLVMBuildZExt(ctx->ac.builder, src[1],
1762 LLVMTypeOf(src[0]), ""),
1763 "");
1764 break;
1765 case nir_op_ushr:
1766 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1767 LLVMBuildZExt(ctx->ac.builder, src[1],
1768 LLVMTypeOf(src[0]), ""),
1769 "");
1770 break;
1771 case nir_op_ilt:
1772 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1773 break;
1774 case nir_op_ine:
1775 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1776 break;
1777 case nir_op_ieq:
1778 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1779 break;
1780 case nir_op_ige:
1781 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1782 break;
1783 case nir_op_ult:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1785 break;
1786 case nir_op_uge:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1788 break;
1789 case nir_op_feq:
1790 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1791 break;
1792 case nir_op_fne:
1793 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1794 break;
1795 case nir_op_flt:
1796 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1797 break;
1798 case nir_op_fge:
1799 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1800 break;
1801 case nir_op_fabs:
1802 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1803 ac_to_float_type(&ctx->ac, def_type), src[0]);
1804 break;
1805 case nir_op_iabs:
1806 result = emit_iabs(&ctx->ac, src[0]);
1807 break;
1808 case nir_op_imax:
1809 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1810 break;
1811 case nir_op_imin:
1812 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1813 break;
1814 case nir_op_umax:
1815 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1816 break;
1817 case nir_op_umin:
1818 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1819 break;
1820 case nir_op_isign:
1821 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1822 break;
1823 case nir_op_fsign:
1824 src[0] = ac_to_float(&ctx->ac, src[0]);
1825 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1826 break;
1827 case nir_op_ffloor:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_ftrunc:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1833 ac_to_float_type(&ctx->ac, def_type), src[0]);
1834 break;
1835 case nir_op_fceil:
1836 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1837 ac_to_float_type(&ctx->ac, def_type), src[0]);
1838 break;
1839 case nir_op_fround_even:
1840 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1841 ac_to_float_type(&ctx->ac, def_type),src[0]);
1842 break;
1843 case nir_op_ffract:
1844 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1845 break;
1846 case nir_op_fsin:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1848 ac_to_float_type(&ctx->ac, def_type), src[0]);
1849 break;
1850 case nir_op_fcos:
1851 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1852 ac_to_float_type(&ctx->ac, def_type), src[0]);
1853 break;
1854 case nir_op_fsqrt:
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1856 ac_to_float_type(&ctx->ac, def_type), src[0]);
1857 break;
1858 case nir_op_fexp2:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 break;
1862 case nir_op_flog2:
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1864 ac_to_float_type(&ctx->ac, def_type), src[0]);
1865 break;
1866 case nir_op_frsq:
1867 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1868 ac_to_float_type(&ctx->ac, def_type), src[0]);
1869 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1870 result);
1871 break;
1872 case nir_op_fpow:
1873 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1874 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1875 break;
1876 case nir_op_fmax:
1877 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1878 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1879 if (ctx->ac.chip_class < GFX9 &&
1880 instr->dest.dest.ssa.bit_size == 32) {
1881 /* Only pre-GFX9 chips do not flush denorms. */
1882 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1883 ac_to_float_type(&ctx->ac, def_type),
1884 result);
1885 }
1886 break;
1887 case nir_op_fmin:
1888 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1889 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1890 if (ctx->ac.chip_class < GFX9 &&
1891 instr->dest.dest.ssa.bit_size == 32) {
1892 /* Only pre-GFX9 chips do not flush denorms. */
1893 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1894 ac_to_float_type(&ctx->ac, def_type),
1895 result);
1896 }
1897 break;
1898 case nir_op_ffma:
1899 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1900 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1901 break;
1902 case nir_op_ibitfield_extract:
1903 result = emit_bitfield_extract(&ctx->ac, true, src);
1904 break;
1905 case nir_op_ubitfield_extract:
1906 result = emit_bitfield_extract(&ctx->ac, false, src);
1907 break;
1908 case nir_op_bitfield_insert:
1909 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1910 break;
1911 case nir_op_bitfield_reverse:
1912 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1913 break;
1914 case nir_op_bit_count:
1915 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1916 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1917 else {
1918 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1919 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1920 }
1921 break;
1922 case nir_op_vec2:
1923 case nir_op_vec3:
1924 case nir_op_vec4:
1925 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1926 src[i] = ac_to_integer(&ctx->ac, src[i]);
1927 result = ac_build_gather_values(&ctx->ac, src, num_components);
1928 break;
1929 case nir_op_f2i32:
1930 case nir_op_f2i64:
1931 src[0] = ac_to_float(&ctx->ac, src[0]);
1932 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1933 break;
1934 case nir_op_f2u32:
1935 case nir_op_f2u64:
1936 src[0] = ac_to_float(&ctx->ac, src[0]);
1937 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1938 break;
1939 case nir_op_i2f32:
1940 case nir_op_i2f64:
1941 src[0] = ac_to_integer(&ctx->ac, src[0]);
1942 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1943 break;
1944 case nir_op_u2f32:
1945 case nir_op_u2f64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1948 break;
1949 case nir_op_f2f64:
1950 src[0] = ac_to_float(&ctx->ac, src[0]);
1951 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1952 break;
1953 case nir_op_f2f32:
1954 src[0] = ac_to_float(&ctx->ac, src[0]);
1955 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1956 break;
1957 case nir_op_u2u32:
1958 case nir_op_u2u64:
1959 src[0] = ac_to_integer(&ctx->ac, src[0]);
1960 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1961 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1962 else
1963 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1964 break;
1965 case nir_op_i2i32:
1966 case nir_op_i2i64:
1967 src[0] = ac_to_integer(&ctx->ac, src[0]);
1968 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1969 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1970 else
1971 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1972 break;
1973 case nir_op_bcsel:
1974 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1975 break;
1976 case nir_op_find_lsb:
1977 src[0] = ac_to_integer(&ctx->ac, src[0]);
1978 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1979 break;
1980 case nir_op_ufind_msb:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1983 break;
1984 case nir_op_ifind_msb:
1985 src[0] = ac_to_integer(&ctx->ac, src[0]);
1986 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1987 break;
1988 case nir_op_uadd_carry:
1989 src[0] = ac_to_integer(&ctx->ac, src[0]);
1990 src[1] = ac_to_integer(&ctx->ac, src[1]);
1991 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1992 break;
1993 case nir_op_usub_borrow:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1997 break;
1998 case nir_op_b2f:
1999 result = emit_b2f(&ctx->ac, src[0]);
2000 break;
2001 case nir_op_f2b:
2002 result = emit_f2b(&ctx->ac, src[0]);
2003 break;
2004 case nir_op_b2i:
2005 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2006 break;
2007 case nir_op_i2b:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 result = emit_i2b(&ctx->ac, src[0]);
2010 break;
2011 case nir_op_fquantize2f16:
2012 result = emit_f2f16(&ctx->ac, src[0]);
2013 break;
2014 case nir_op_umul_high:
2015 src[0] = ac_to_integer(&ctx->ac, src[0]);
2016 src[1] = ac_to_integer(&ctx->ac, src[1]);
2017 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2018 break;
2019 case nir_op_imul_high:
2020 src[0] = ac_to_integer(&ctx->ac, src[0]);
2021 src[1] = ac_to_integer(&ctx->ac, src[1]);
2022 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2023 break;
2024 case nir_op_pack_half_2x16:
2025 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2026 break;
2027 case nir_op_unpack_half_2x16:
2028 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2029 break;
2030 case nir_op_fddx:
2031 case nir_op_fddy:
2032 case nir_op_fddx_fine:
2033 case nir_op_fddy_fine:
2034 case nir_op_fddx_coarse:
2035 case nir_op_fddy_coarse:
2036 result = emit_ddxy(ctx, instr->op, src[0]);
2037 break;
2038
2039 case nir_op_unpack_64_2x32_split_x: {
2040 assert(ac_get_llvm_num_components(src[0]) == 1);
2041 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2042 ctx->ac.v2i32,
2043 "");
2044 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2045 ctx->ac.i32_0, "");
2046 break;
2047 }
2048
2049 case nir_op_unpack_64_2x32_split_y: {
2050 assert(ac_get_llvm_num_components(src[0]) == 1);
2051 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2052 ctx->ac.v2i32,
2053 "");
2054 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2055 ctx->ac.i32_1, "");
2056 break;
2057 }
2058
2059 case nir_op_pack_64_2x32_split: {
2060 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2061 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2062 src[0], ctx->ac.i32_0, "");
2063 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2064 src[1], ctx->ac.i32_1, "");
2065 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2066 break;
2067 }
2068
2069 default:
2070 fprintf(stderr, "Unknown NIR alu instr: ");
2071 nir_print_instr(&instr->instr, stderr);
2072 fprintf(stderr, "\n");
2073 abort();
2074 }
2075
2076 if (result) {
2077 assert(instr->dest.dest.is_ssa);
2078 result = ac_to_integer(&ctx->ac, result);
2079 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2080 result);
2081 }
2082 }
2083
2084 static void visit_load_const(struct ac_nir_context *ctx,
2085 const nir_load_const_instr *instr)
2086 {
2087 LLVMValueRef values[4], value = NULL;
2088 LLVMTypeRef element_type =
2089 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2090
2091 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2092 switch (instr->def.bit_size) {
2093 case 32:
2094 values[i] = LLVMConstInt(element_type,
2095 instr->value.u32[i], false);
2096 break;
2097 case 64:
2098 values[i] = LLVMConstInt(element_type,
2099 instr->value.u64[i], false);
2100 break;
2101 default:
2102 fprintf(stderr,
2103 "unsupported nir load_const bit_size: %d\n",
2104 instr->def.bit_size);
2105 abort();
2106 }
2107 }
2108 if (instr->def.num_components > 1) {
2109 value = LLVMConstVector(values, instr->def.num_components);
2110 } else
2111 value = values[0];
2112
2113 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2114 }
2115
2116 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2117 LLVMTypeRef type)
2118 {
2119 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2120 return LLVMBuildBitCast(ctx->builder, ptr,
2121 LLVMPointerType(type, addr_space), "");
2122 }
2123
2124 static LLVMValueRef
2125 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2126 {
2127 LLVMValueRef size =
2128 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2129 LLVMConstInt(ctx->ac.i32, 2, false), "");
2130
2131 /* VI only */
2132 if (ctx->ac.chip_class == VI && in_elements) {
2133 /* On VI, the descriptor contains the size in bytes,
2134 * but TXQ must return the size in elements.
2135 * The stride is always non-zero for resources using TXQ.
2136 */
2137 LLVMValueRef stride =
2138 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2139 ctx->ac.i32_1, "");
2140 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2141 LLVMConstInt(ctx->ac.i32, 16, false), "");
2142 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2143 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2144
2145 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2146 }
2147 return size;
2148 }
2149
2150 /**
2151 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2152 * intrinsic names).
2153 */
2154 static void build_int_type_name(
2155 LLVMTypeRef type,
2156 char *buf, unsigned bufsize)
2157 {
2158 assert(bufsize >= 6);
2159
2160 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2161 snprintf(buf, bufsize, "v%ui32",
2162 LLVMGetVectorSize(type));
2163 else
2164 strcpy(buf, "i32");
2165 }
2166
2167 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2168 struct ac_image_args *args,
2169 const nir_tex_instr *instr)
2170 {
2171 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2172 LLVMValueRef coord = args->addr;
2173 LLVMValueRef half_texel[2];
2174 LLVMValueRef compare_cube_wa = NULL;
2175 LLVMValueRef result;
2176 int c;
2177 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2178
2179 //TODO Rect
2180 {
2181 struct ac_image_args txq_args = { 0 };
2182
2183 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2184 txq_args.opcode = ac_image_get_resinfo;
2185 txq_args.dmask = 0xf;
2186 txq_args.addr = ctx->i32_0;
2187 txq_args.resource = args->resource;
2188 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2189
2190 for (c = 0; c < 2; c++) {
2191 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2192 LLVMConstInt(ctx->i32, c, false), "");
2193 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2194 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2195 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2196 LLVMConstReal(ctx->f32, -0.5), "");
2197 }
2198 }
2199
2200 LLVMValueRef orig_coords = args->addr;
2201
2202 for (c = 0; c < 2; c++) {
2203 LLVMValueRef tmp;
2204 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2205 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2206 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2207 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2208 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2209 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2210 }
2211
2212
2213 /*
2214 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2215 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2216 * workaround by sampling using a scaled type and converting.
2217 * This is taken from amdgpu-pro shaders.
2218 */
2219 /* NOTE this produces some ugly code compared to amdgpu-pro,
2220 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2221 * and then reads them back. -pro generates two selects,
2222 * one s_cmp for the descriptor rewriting
2223 * one v_cmp for the coordinate and result changes.
2224 */
2225 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2226 LLVMValueRef tmp, tmp2;
2227
2228 /* workaround 8/8/8/8 uint/sint cube gather bug */
2229 /* first detect it then change to a scaled read and f2i */
2230 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2231 tmp2 = tmp;
2232
2233 /* extract the DATA_FORMAT */
2234 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2235 LLVMConstInt(ctx->i32, 6, false), false);
2236
2237 /* is the DATA_FORMAT == 8_8_8_8 */
2238 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2239
2240 if (stype == GLSL_TYPE_UINT)
2241 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2242 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2243 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2244 else
2245 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2246 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2247 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2248
2249 /* replace the NUM FORMAT in the descriptor */
2250 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2251 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2252
2253 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2254
2255 /* don't modify the coordinates for this case */
2256 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2257 }
2258 args->addr = coord;
2259 result = ac_build_image_opcode(ctx, args);
2260
2261 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2262 LLVMValueRef tmp, tmp2;
2263
2264 /* if the cube workaround is in place, f2i the result. */
2265 for (c = 0; c < 4; c++) {
2266 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2267 if (stype == GLSL_TYPE_UINT)
2268 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2269 else
2270 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2271 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2272 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2273 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2274 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2275 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2276 }
2277 }
2278 return result;
2279 }
2280
2281 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2282 const nir_tex_instr *instr,
2283 bool lod_is_zero,
2284 struct ac_image_args *args)
2285 {
2286 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2287 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2288
2289 return ac_build_buffer_load_format(&ctx->ac,
2290 args->resource,
2291 args->addr,
2292 ctx->ac.i32_0,
2293 util_last_bit(mask),
2294 false, true);
2295 }
2296
2297 args->opcode = ac_image_sample;
2298 args->compare = instr->is_shadow;
2299
2300 switch (instr->op) {
2301 case nir_texop_txf:
2302 case nir_texop_txf_ms:
2303 case nir_texop_samples_identical:
2304 args->opcode = lod_is_zero ||
2305 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2306 ac_image_load : ac_image_load_mip;
2307 args->compare = false;
2308 args->offset = false;
2309 break;
2310 case nir_texop_txb:
2311 args->bias = true;
2312 break;
2313 case nir_texop_txl:
2314 if (lod_is_zero)
2315 args->level_zero = true;
2316 else
2317 args->lod = true;
2318 break;
2319 case nir_texop_txs:
2320 case nir_texop_query_levels:
2321 args->opcode = ac_image_get_resinfo;
2322 break;
2323 case nir_texop_tex:
2324 if (ctx->stage != MESA_SHADER_FRAGMENT)
2325 args->level_zero = true;
2326 break;
2327 case nir_texop_txd:
2328 args->deriv = true;
2329 break;
2330 case nir_texop_tg4:
2331 args->opcode = ac_image_gather4;
2332 args->level_zero = true;
2333 break;
2334 case nir_texop_lod:
2335 args->opcode = ac_image_get_lod;
2336 args->compare = false;
2337 args->offset = false;
2338 break;
2339 default:
2340 break;
2341 }
2342
2343 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2344 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2345 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2346 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2347 }
2348 }
2349 return ac_build_image_opcode(&ctx->ac, args);
2350 }
2351
2352 static LLVMValueRef
2353 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2354 unsigned desc_set, unsigned binding)
2355 {
2356 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2357 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2358 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2359 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2360 unsigned base_offset = layout->binding[binding].offset;
2361 LLVMValueRef offset, stride;
2362
2363 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2364 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2365 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2366 layout->binding[binding].dynamic_offset_offset;
2367 desc_ptr = ctx->abi.push_constants;
2368 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2369 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2370 } else
2371 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2372
2373 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2374 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2375 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2376
2377 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2378 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2379 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2380
2381 return desc_ptr;
2382 }
2383
2384 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2385 nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2388 LLVMValueRef index = get_src(ctx, instr->src[1]);
2389
2390 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2391 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2392 return result;
2393 }
2394
2395 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2396 nir_intrinsic_instr *instr)
2397 {
2398 LLVMValueRef ptr, addr;
2399
2400 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2401 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2402 get_src(ctx, instr->src[0]), "");
2403
2404 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2405 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2406
2407 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2408 }
2409
2410 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2411 const nir_intrinsic_instr *instr)
2412 {
2413 LLVMValueRef index = get_src(ctx, instr->src[0]);
2414
2415 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2416 }
2417
2418 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2419 {
2420 uint32_t new_mask = 0;
2421 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2422 if (mask & (1u << i))
2423 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2424 return new_mask;
2425 }
2426
2427 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2428 unsigned start, unsigned count)
2429 {
2430 LLVMTypeRef type = LLVMTypeOf(src);
2431
2432 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2433 assert(start == 0);
2434 assert(count == 1);
2435 return src;
2436 }
2437
2438 unsigned src_elements = LLVMGetVectorSize(type);
2439 assert(start < src_elements);
2440 assert(start + count <= src_elements);
2441
2442 if (start == 0 && count == src_elements)
2443 return src;
2444
2445 if (count == 1)
2446 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2447
2448 assert(count <= 8);
2449 LLVMValueRef indices[8];
2450 for (unsigned i = 0; i < count; ++i)
2451 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2452
2453 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2454 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2455 }
2456
2457 static void visit_store_ssbo(struct ac_nir_context *ctx,
2458 nir_intrinsic_instr *instr)
2459 {
2460 const char *store_name;
2461 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2462 LLVMTypeRef data_type = ctx->ac.f32;
2463 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2464 int components_32bit = elem_size_mult * instr->num_components;
2465 unsigned writemask = nir_intrinsic_write_mask(instr);
2466 LLVMValueRef base_data, base_offset;
2467 LLVMValueRef params[6];
2468
2469 params[1] = ctx->abi->load_ssbo(ctx->abi,
2470 get_src(ctx, instr->src[1]), true);
2471 params[2] = ctx->ac.i32_0; /* vindex */
2472 params[4] = ctx->ac.i1false; /* glc */
2473 params[5] = ctx->ac.i1false; /* slc */
2474
2475 if (components_32bit > 1)
2476 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2477
2478 writemask = widen_mask(writemask, elem_size_mult);
2479
2480 base_data = ac_to_float(&ctx->ac, src_data);
2481 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2482 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2483 data_type, "");
2484 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2485 while (writemask) {
2486 int start, count;
2487 LLVMValueRef data;
2488 LLVMValueRef offset;
2489
2490 u_bit_scan_consecutive_range(&writemask, &start, &count);
2491
2492 /* Due to an LLVM limitation, split 3-element writes
2493 * into a 2-element and a 1-element write. */
2494 if (count == 3) {
2495 writemask |= 1 << (start + 2);
2496 count = 2;
2497 }
2498
2499 if (count > 4) {
2500 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2501 count = 4;
2502 }
2503
2504 if (count == 4) {
2505 store_name = "llvm.amdgcn.buffer.store.v4f32";
2506 } else if (count == 2) {
2507 store_name = "llvm.amdgcn.buffer.store.v2f32";
2508
2509 } else {
2510 assert(count == 1);
2511 store_name = "llvm.amdgcn.buffer.store.f32";
2512 }
2513 data = extract_vector_range(&ctx->ac, base_data, start, count);
2514
2515 offset = base_offset;
2516 if (start != 0) {
2517 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2518 }
2519 params[0] = data;
2520 params[3] = offset;
2521 ac_build_intrinsic(&ctx->ac, store_name,
2522 ctx->ac.voidt, params, 6, 0);
2523 }
2524 }
2525
2526 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2527 const nir_intrinsic_instr *instr)
2528 {
2529 const char *name;
2530 LLVMValueRef params[6];
2531 int arg_count = 0;
2532
2533 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2534 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2535 }
2536 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2537 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2538 get_src(ctx, instr->src[0]),
2539 true);
2540 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2541 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2542 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2543
2544 switch (instr->intrinsic) {
2545 case nir_intrinsic_ssbo_atomic_add:
2546 name = "llvm.amdgcn.buffer.atomic.add";
2547 break;
2548 case nir_intrinsic_ssbo_atomic_imin:
2549 name = "llvm.amdgcn.buffer.atomic.smin";
2550 break;
2551 case nir_intrinsic_ssbo_atomic_umin:
2552 name = "llvm.amdgcn.buffer.atomic.umin";
2553 break;
2554 case nir_intrinsic_ssbo_atomic_imax:
2555 name = "llvm.amdgcn.buffer.atomic.smax";
2556 break;
2557 case nir_intrinsic_ssbo_atomic_umax:
2558 name = "llvm.amdgcn.buffer.atomic.umax";
2559 break;
2560 case nir_intrinsic_ssbo_atomic_and:
2561 name = "llvm.amdgcn.buffer.atomic.and";
2562 break;
2563 case nir_intrinsic_ssbo_atomic_or:
2564 name = "llvm.amdgcn.buffer.atomic.or";
2565 break;
2566 case nir_intrinsic_ssbo_atomic_xor:
2567 name = "llvm.amdgcn.buffer.atomic.xor";
2568 break;
2569 case nir_intrinsic_ssbo_atomic_exchange:
2570 name = "llvm.amdgcn.buffer.atomic.swap";
2571 break;
2572 case nir_intrinsic_ssbo_atomic_comp_swap:
2573 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2574 break;
2575 default:
2576 abort();
2577 }
2578
2579 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2580 }
2581
2582 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2583 const nir_intrinsic_instr *instr)
2584 {
2585 LLVMValueRef results[2];
2586 int load_components;
2587 int num_components = instr->num_components;
2588 if (instr->dest.ssa.bit_size == 64)
2589 num_components *= 2;
2590
2591 for (int i = 0; i < num_components; i += load_components) {
2592 load_components = MIN2(num_components - i, 4);
2593 const char *load_name;
2594 LLVMTypeRef data_type = ctx->ac.f32;
2595 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2596 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2597
2598 if (load_components == 3)
2599 data_type = LLVMVectorType(ctx->ac.f32, 4);
2600 else if (load_components > 1)
2601 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2602
2603 if (load_components >= 3)
2604 load_name = "llvm.amdgcn.buffer.load.v4f32";
2605 else if (load_components == 2)
2606 load_name = "llvm.amdgcn.buffer.load.v2f32";
2607 else if (load_components == 1)
2608 load_name = "llvm.amdgcn.buffer.load.f32";
2609 else
2610 unreachable("unhandled number of components");
2611
2612 LLVMValueRef params[] = {
2613 ctx->abi->load_ssbo(ctx->abi,
2614 get_src(ctx, instr->src[0]),
2615 false),
2616 ctx->ac.i32_0,
2617 offset,
2618 ctx->ac.i1false,
2619 ctx->ac.i1false,
2620 };
2621
2622 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2623 }
2624
2625 assume(results[0]);
2626 LLVMValueRef ret = results[0];
2627 if (num_components > 4 || num_components == 3) {
2628 LLVMValueRef masks[] = {
2629 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2630 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2631 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2632 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2633 };
2634
2635 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2636 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2637 results[num_components > 4 ? 1 : 0], swizzle, "");
2638 }
2639
2640 return LLVMBuildBitCast(ctx->ac.builder, ret,
2641 get_def_type(ctx, &instr->dest.ssa), "");
2642 }
2643
2644 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2645 const nir_intrinsic_instr *instr)
2646 {
2647 LLVMValueRef ret;
2648 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2649 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2650 int num_components = instr->num_components;
2651
2652 if (ctx->abi->load_ubo)
2653 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2654
2655 if (instr->dest.ssa.bit_size == 64)
2656 num_components *= 2;
2657
2658 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2659 NULL, 0, false, false, true, true);
2660 ret = trim_vector(&ctx->ac, ret, num_components);
2661 return LLVMBuildBitCast(ctx->ac.builder, ret,
2662 get_def_type(ctx, &instr->dest.ssa), "");
2663 }
2664
2665 static void
2666 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2667 bool vs_in, unsigned *vertex_index_out,
2668 LLVMValueRef *vertex_index_ref,
2669 unsigned *const_out, LLVMValueRef *indir_out)
2670 {
2671 unsigned const_offset = 0;
2672 nir_deref *tail = &deref->deref;
2673 LLVMValueRef offset = NULL;
2674
2675 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2676 tail = tail->child;
2677 nir_deref_array *deref_array = nir_deref_as_array(tail);
2678 if (vertex_index_out)
2679 *vertex_index_out = deref_array->base_offset;
2680
2681 if (vertex_index_ref) {
2682 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2683 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2684 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2685 }
2686 *vertex_index_ref = vtx;
2687 }
2688 }
2689
2690 if (deref->var->data.compact) {
2691 assert(tail->child->deref_type == nir_deref_type_array);
2692 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2693 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2694 /* We always lower indirect dereferences for "compact" array vars. */
2695 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2696
2697 const_offset = deref_array->base_offset;
2698 goto out;
2699 }
2700
2701 while (tail->child != NULL) {
2702 const struct glsl_type *parent_type = tail->type;
2703 tail = tail->child;
2704
2705 if (tail->deref_type == nir_deref_type_array) {
2706 nir_deref_array *deref_array = nir_deref_as_array(tail);
2707 LLVMValueRef index, stride, local_offset;
2708 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2709
2710 const_offset += size * deref_array->base_offset;
2711 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2712 continue;
2713
2714 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2715 index = get_src(ctx, deref_array->indirect);
2716 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2717 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2718
2719 if (offset)
2720 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2721 else
2722 offset = local_offset;
2723 } else if (tail->deref_type == nir_deref_type_struct) {
2724 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2725
2726 for (unsigned i = 0; i < deref_struct->index; i++) {
2727 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2728 const_offset += glsl_count_attribute_slots(ft, vs_in);
2729 }
2730 } else
2731 unreachable("unsupported deref type");
2732
2733 }
2734 out:
2735 if (const_offset && offset)
2736 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2737 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2738 "");
2739
2740 *const_out = const_offset;
2741 *indir_out = offset;
2742 }
2743
2744
2745 /* The offchip buffer layout for TCS->TES is
2746 *
2747 * - attribute 0 of patch 0 vertex 0
2748 * - attribute 0 of patch 0 vertex 1
2749 * - attribute 0 of patch 0 vertex 2
2750 * ...
2751 * - attribute 0 of patch 1 vertex 0
2752 * - attribute 0 of patch 1 vertex 1
2753 * ...
2754 * - attribute 1 of patch 0 vertex 0
2755 * - attribute 1 of patch 0 vertex 1
2756 * ...
2757 * - per patch attribute 0 of patch 0
2758 * - per patch attribute 0 of patch 1
2759 * ...
2760 *
2761 * Note that every attribute has 4 components.
2762 */
2763 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2764 LLVMValueRef vertex_index,
2765 LLVMValueRef param_index)
2766 {
2767 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2768 LLVMValueRef param_stride, constant16;
2769 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2770
2771 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2772 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2773 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2774 num_patches, "");
2775
2776 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2777 if (vertex_index) {
2778 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2779 vertices_per_patch, "");
2780
2781 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2782 vertex_index, "");
2783
2784 param_stride = total_vertices;
2785 } else {
2786 base_addr = rel_patch_id;
2787 param_stride = num_patches;
2788 }
2789
2790 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2791 LLVMBuildMul(ctx->ac.builder, param_index,
2792 param_stride, ""), "");
2793
2794 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2795
2796 if (!vertex_index) {
2797 LLVMValueRef patch_data_offset =
2798 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2799
2800 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2801 patch_data_offset, "");
2802 }
2803 return base_addr;
2804 }
2805
2806 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2807 unsigned param,
2808 unsigned const_index,
2809 bool is_compact,
2810 LLVMValueRef vertex_index,
2811 LLVMValueRef indir_index)
2812 {
2813 LLVMValueRef param_index;
2814
2815 if (indir_index)
2816 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2817 indir_index, "");
2818 else {
2819 if (const_index && !is_compact)
2820 param += const_index;
2821 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2822 }
2823 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2824 }
2825
2826 static void
2827 mark_tess_output(struct nir_to_llvm_context *ctx,
2828 bool is_patch, uint32_t param)
2829
2830 {
2831 if (is_patch) {
2832 ctx->tess_patch_outputs_written |= (1ull << param);
2833 } else
2834 ctx->tess_outputs_written |= (1ull << param);
2835 }
2836
2837 static LLVMValueRef
2838 get_dw_address(struct nir_to_llvm_context *ctx,
2839 LLVMValueRef dw_addr,
2840 unsigned param,
2841 unsigned const_index,
2842 bool compact_const_index,
2843 LLVMValueRef vertex_index,
2844 LLVMValueRef stride,
2845 LLVMValueRef indir_index)
2846
2847 {
2848
2849 if (vertex_index) {
2850 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2851 LLVMBuildMul(ctx->ac.builder,
2852 vertex_index,
2853 stride, ""), "");
2854 }
2855
2856 if (indir_index)
2857 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2858 LLVMBuildMul(ctx->ac.builder, indir_index,
2859 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2860 else if (const_index && !compact_const_index)
2861 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2862 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2863
2864 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2865 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2866
2867 if (const_index && compact_const_index)
2868 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2869 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2870 return dw_addr;
2871 }
2872
2873 static LLVMValueRef
2874 load_tcs_varyings(struct ac_shader_abi *abi,
2875 LLVMValueRef vertex_index,
2876 LLVMValueRef indir_index,
2877 unsigned const_index,
2878 unsigned location,
2879 unsigned driver_location,
2880 unsigned component,
2881 unsigned num_components,
2882 bool is_patch,
2883 bool is_compact,
2884 bool load_input)
2885 {
2886 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2887 LLVMValueRef dw_addr, stride;
2888 LLVMValueRef value[4], result;
2889 unsigned param = shader_io_get_unique_index(location);
2890
2891 if (load_input) {
2892 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2893 dw_addr = get_tcs_in_current_patch_offset(ctx);
2894 } else {
2895 if (!is_patch) {
2896 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2897 dw_addr = get_tcs_out_current_patch_offset(ctx);
2898 } else {
2899 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2900 stride = NULL;
2901 }
2902 }
2903
2904 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2905 indir_index);
2906
2907 for (unsigned i = 0; i < num_components + component; i++) {
2908 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2909 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2910 ctx->ac.i32_1, "");
2911 }
2912 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2913 return result;
2914 }
2915
2916 static void
2917 store_tcs_output(struct ac_shader_abi *abi,
2918 LLVMValueRef vertex_index,
2919 LLVMValueRef param_index,
2920 unsigned const_index,
2921 unsigned location,
2922 unsigned driver_location,
2923 LLVMValueRef src,
2924 unsigned component,
2925 bool is_patch,
2926 bool is_compact,
2927 unsigned writemask)
2928 {
2929 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2930 LLVMValueRef dw_addr;
2931 LLVMValueRef stride = NULL;
2932 LLVMValueRef buf_addr = NULL;
2933 unsigned param;
2934 bool store_lds = true;
2935
2936 if (is_patch) {
2937 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2938 store_lds = false;
2939 } else {
2940 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2941 store_lds = false;
2942 }
2943
2944 param = shader_io_get_unique_index(location);
2945 if (location == VARYING_SLOT_CLIP_DIST0 &&
2946 is_compact && const_index > 3) {
2947 const_index -= 3;
2948 param++;
2949 }
2950
2951 if (!is_patch) {
2952 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2953 dw_addr = get_tcs_out_current_patch_offset(ctx);
2954 } else {
2955 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2956 }
2957
2958 mark_tess_output(ctx, is_patch, param);
2959
2960 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2961 param_index);
2962 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2963 vertex_index, param_index);
2964
2965 bool is_tess_factor = false;
2966 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2967 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2968 is_tess_factor = true;
2969
2970 unsigned base = is_compact ? const_index : 0;
2971 for (unsigned chan = 0; chan < 8; chan++) {
2972 if (!(writemask & (1 << chan)))
2973 continue;
2974 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2975
2976 if (store_lds || is_tess_factor) {
2977 LLVMValueRef dw_addr_chan =
2978 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2979 LLVMConstInt(ctx->ac.i32, chan, false), "");
2980 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2981 }
2982
2983 if (!is_tess_factor && writemask != 0xF)
2984 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2985 buf_addr, ctx->oc_lds,
2986 4 * (base + chan), 1, 0, true, false);
2987 }
2988
2989 if (writemask == 0xF) {
2990 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2991 buf_addr, ctx->oc_lds,
2992 (base * 4), 1, 0, true, false);
2993 }
2994 }
2995
2996 static LLVMValueRef
2997 load_tes_input(struct ac_shader_abi *abi,
2998 LLVMValueRef vertex_index,
2999 LLVMValueRef param_index,
3000 unsigned const_index,
3001 unsigned location,
3002 unsigned driver_location,
3003 unsigned component,
3004 unsigned num_components,
3005 bool is_patch,
3006 bool is_compact,
3007 bool load_input)
3008 {
3009 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3010 LLVMValueRef buf_addr;
3011 LLVMValueRef result;
3012 unsigned param = shader_io_get_unique_index(location);
3013
3014 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3015 const_index -= 3;
3016 param++;
3017 }
3018
3019 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3020 is_compact, vertex_index, param_index);
3021
3022 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3023 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3024
3025 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3026 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3027 result = trim_vector(&ctx->ac, result, num_components);
3028 return result;
3029 }
3030
3031 static LLVMValueRef
3032 load_gs_input(struct ac_shader_abi *abi,
3033 unsigned location,
3034 unsigned driver_location,
3035 unsigned component,
3036 unsigned num_components,
3037 unsigned vertex_index,
3038 unsigned const_index,
3039 LLVMTypeRef type)
3040 {
3041 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3042 LLVMValueRef vtx_offset;
3043 unsigned param, vtx_offset_param;
3044 LLVMValueRef value[4], result;
3045
3046 vtx_offset_param = vertex_index;
3047 assert(vtx_offset_param < 6);
3048 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3049 LLVMConstInt(ctx->ac.i32, 4, false), "");
3050
3051 param = shader_io_get_unique_index(location);
3052
3053 for (unsigned i = component; i < num_components + component; i++) {
3054 if (ctx->ac.chip_class >= GFX9) {
3055 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3056 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3057 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3058 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3059 } else {
3060 LLVMValueRef soffset =
3061 LLVMConstInt(ctx->ac.i32,
3062 (param * 4 + i + const_index) * 256,
3063 false);
3064
3065 value[i] = ac_build_buffer_load(&ctx->ac,
3066 ctx->esgs_ring, 1,
3067 ctx->ac.i32_0,
3068 vtx_offset, soffset,
3069 0, 1, 0, true, false);
3070
3071 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3072 type, "");
3073 }
3074 }
3075 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3076 result = ac_to_integer(&ctx->ac, result);
3077 return result;
3078 }
3079
3080 static LLVMValueRef
3081 build_gep_for_deref(struct ac_nir_context *ctx,
3082 nir_deref_var *deref)
3083 {
3084 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3085 assert(entry->data);
3086 LLVMValueRef val = entry->data;
3087 nir_deref *tail = deref->deref.child;
3088 while (tail != NULL) {
3089 LLVMValueRef offset;
3090 switch (tail->deref_type) {
3091 case nir_deref_type_array: {
3092 nir_deref_array *array = nir_deref_as_array(tail);
3093 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3094 if (array->deref_array_type ==
3095 nir_deref_array_type_indirect) {
3096 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3097 get_src(ctx,
3098 array->indirect),
3099 "");
3100 }
3101 break;
3102 }
3103 case nir_deref_type_struct: {
3104 nir_deref_struct *deref_struct =
3105 nir_deref_as_struct(tail);
3106 offset = LLVMConstInt(ctx->ac.i32,
3107 deref_struct->index, 0);
3108 break;
3109 }
3110 default:
3111 unreachable("bad deref type");
3112 }
3113 val = ac_build_gep0(&ctx->ac, val, offset);
3114 tail = tail->child;
3115 }
3116 return val;
3117 }
3118
3119 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3120 nir_intrinsic_instr *instr,
3121 bool load_inputs)
3122 {
3123 LLVMValueRef result;
3124 LLVMValueRef vertex_index = NULL;
3125 LLVMValueRef indir_index = NULL;
3126 unsigned const_index = 0;
3127 unsigned location = instr->variables[0]->var->data.location;
3128 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3129 const bool is_patch = instr->variables[0]->var->data.patch;
3130 const bool is_compact = instr->variables[0]->var->data.compact;
3131
3132 get_deref_offset(ctx, instr->variables[0],
3133 false, NULL, is_patch ? NULL : &vertex_index,
3134 &const_index, &indir_index);
3135
3136 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3137 const_index, location, driver_location,
3138 instr->variables[0]->var->data.location_frac,
3139 instr->num_components,
3140 is_patch, is_compact, load_inputs);
3141 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3142 }
3143
3144 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3145 nir_intrinsic_instr *instr)
3146 {
3147 LLVMValueRef values[8];
3148 int idx = instr->variables[0]->var->data.driver_location;
3149 int ve = instr->dest.ssa.num_components;
3150 unsigned comp = instr->variables[0]->var->data.location_frac;
3151 LLVMValueRef indir_index;
3152 LLVMValueRef ret;
3153 unsigned const_index;
3154 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3155 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3156 instr->variables[0]->var->data.mode == nir_var_shader_in;
3157 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3158 &const_index, &indir_index);
3159
3160 if (instr->dest.ssa.bit_size == 64)
3161 ve *= 2;
3162
3163 switch (instr->variables[0]->var->data.mode) {
3164 case nir_var_shader_in:
3165 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3166 ctx->stage == MESA_SHADER_TESS_EVAL) {
3167 return load_tess_varyings(ctx, instr, true);
3168 }
3169
3170 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3171 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3172 LLVMValueRef indir_index;
3173 unsigned const_index, vertex_index;
3174 get_deref_offset(ctx, instr->variables[0],
3175 false, &vertex_index, NULL,
3176 &const_index, &indir_index);
3177
3178 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3179 instr->variables[0]->var->data.driver_location,
3180 instr->variables[0]->var->data.location_frac, ve,
3181 vertex_index, const_index, type);
3182 }
3183
3184 for (unsigned chan = comp; chan < ve + comp; chan++) {
3185 if (indir_index) {
3186 unsigned count = glsl_count_attribute_slots(
3187 instr->variables[0]->var->type,
3188 ctx->stage == MESA_SHADER_VERTEX);
3189 count -= chan / 4;
3190 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3191 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3192 stride, false, true);
3193
3194 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3195 tmp_vec,
3196 indir_index, "");
3197 } else
3198 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3199 }
3200 break;
3201 case nir_var_local:
3202 for (unsigned chan = 0; chan < ve; chan++) {
3203 if (indir_index) {
3204 unsigned count = glsl_count_attribute_slots(
3205 instr->variables[0]->var->type, false);
3206 count -= chan / 4;
3207 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3208 &ctx->ac, ctx->locals + idx + chan, count,
3209 stride, true, true);
3210
3211 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3212 tmp_vec,
3213 indir_index, "");
3214 } else {
3215 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3216 }
3217 }
3218 break;
3219 case nir_var_shared: {
3220 LLVMValueRef address = build_gep_for_deref(ctx,
3221 instr->variables[0]);
3222 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3223 return LLVMBuildBitCast(ctx->ac.builder, val,
3224 get_def_type(ctx, &instr->dest.ssa),
3225 "");
3226 }
3227 case nir_var_shader_out:
3228 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3229 return load_tess_varyings(ctx, instr, false);
3230 }
3231
3232 for (unsigned chan = comp; chan < ve + comp; chan++) {
3233 if (indir_index) {
3234 unsigned count = glsl_count_attribute_slots(
3235 instr->variables[0]->var->type, false);
3236 count -= chan / 4;
3237 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3238 &ctx->ac, ctx->outputs + idx + chan, count,
3239 stride, true, true);
3240
3241 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3242 tmp_vec,
3243 indir_index, "");
3244 } else {
3245 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3246 ctx->outputs[idx + chan + const_index * stride],
3247 "");
3248 }
3249 }
3250 break;
3251 default:
3252 unreachable("unhandle variable mode");
3253 }
3254 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3255 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3256 }
3257
3258 static void
3259 visit_store_var(struct ac_nir_context *ctx,
3260 nir_intrinsic_instr *instr)
3261 {
3262 LLVMValueRef temp_ptr, value;
3263 int idx = instr->variables[0]->var->data.driver_location;
3264 unsigned comp = instr->variables[0]->var->data.location_frac;
3265 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3266 int writemask = instr->const_index[0] << comp;
3267 LLVMValueRef indir_index;
3268 unsigned const_index;
3269 get_deref_offset(ctx, instr->variables[0], false,
3270 NULL, NULL, &const_index, &indir_index);
3271
3272 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3273
3274 src = LLVMBuildBitCast(ctx->ac.builder, src,
3275 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3276 "");
3277
3278 writemask = widen_mask(writemask, 2);
3279 }
3280
3281 switch (instr->variables[0]->var->data.mode) {
3282 case nir_var_shader_out:
3283
3284 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3285 LLVMValueRef vertex_index = NULL;
3286 LLVMValueRef indir_index = NULL;
3287 unsigned const_index = 0;
3288 const unsigned location = instr->variables[0]->var->data.location;
3289 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3290 const unsigned comp = instr->variables[0]->var->data.location_frac;
3291 const bool is_patch = instr->variables[0]->var->data.patch;
3292 const bool is_compact = instr->variables[0]->var->data.compact;
3293
3294 get_deref_offset(ctx, instr->variables[0],
3295 false, NULL, is_patch ? NULL : &vertex_index,
3296 &const_index, &indir_index);
3297
3298 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3299 const_index, location, driver_location,
3300 src, comp, is_patch, is_compact, writemask);
3301 return;
3302 }
3303
3304 for (unsigned chan = 0; chan < 8; chan++) {
3305 int stride = 4;
3306 if (!(writemask & (1 << chan)))
3307 continue;
3308
3309 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3310
3311 if (instr->variables[0]->var->data.compact)
3312 stride = 1;
3313 if (indir_index) {
3314 unsigned count = glsl_count_attribute_slots(
3315 instr->variables[0]->var->type, false);
3316 count -= chan / 4;
3317 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3318 &ctx->ac, ctx->outputs + idx + chan, count,
3319 stride, true, true);
3320
3321 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3322 value, indir_index, "");
3323 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3324 count, stride, tmp_vec);
3325
3326 } else {
3327 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3328
3329 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3330 }
3331 }
3332 break;
3333 case nir_var_local:
3334 for (unsigned chan = 0; chan < 8; chan++) {
3335 if (!(writemask & (1 << chan)))
3336 continue;
3337
3338 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3339 if (indir_index) {
3340 unsigned count = glsl_count_attribute_slots(
3341 instr->variables[0]->var->type, false);
3342 count -= chan / 4;
3343 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3344 &ctx->ac, ctx->locals + idx + chan, count,
3345 4, true, true);
3346
3347 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3348 value, indir_index, "");
3349 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3350 count, 4, tmp_vec);
3351 } else {
3352 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3353
3354 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3355 }
3356 }
3357 break;
3358 case nir_var_shared: {
3359 int writemask = instr->const_index[0];
3360 LLVMValueRef address = build_gep_for_deref(ctx,
3361 instr->variables[0]);
3362 LLVMValueRef val = get_src(ctx, instr->src[0]);
3363 unsigned components =
3364 glsl_get_vector_elements(
3365 nir_deref_tail(&instr->variables[0]->deref)->type);
3366 if (writemask == (1 << components) - 1) {
3367 val = LLVMBuildBitCast(
3368 ctx->ac.builder, val,
3369 LLVMGetElementType(LLVMTypeOf(address)), "");
3370 LLVMBuildStore(ctx->ac.builder, val, address);
3371 } else {
3372 for (unsigned chan = 0; chan < 4; chan++) {
3373 if (!(writemask & (1 << chan)))
3374 continue;
3375 LLVMValueRef ptr =
3376 LLVMBuildStructGEP(ctx->ac.builder,
3377 address, chan, "");
3378 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3379 chan);
3380 src = LLVMBuildBitCast(
3381 ctx->ac.builder, src,
3382 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3383 LLVMBuildStore(ctx->ac.builder, src, ptr);
3384 }
3385 }
3386 break;
3387 }
3388 default:
3389 break;
3390 }
3391 }
3392
3393 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3394 {
3395 switch (dim) {
3396 case GLSL_SAMPLER_DIM_BUF:
3397 return 1;
3398 case GLSL_SAMPLER_DIM_1D:
3399 return array ? 2 : 1;
3400 case GLSL_SAMPLER_DIM_2D:
3401 return array ? 3 : 2;
3402 case GLSL_SAMPLER_DIM_MS:
3403 return array ? 4 : 3;
3404 case GLSL_SAMPLER_DIM_3D:
3405 case GLSL_SAMPLER_DIM_CUBE:
3406 return 3;
3407 case GLSL_SAMPLER_DIM_RECT:
3408 case GLSL_SAMPLER_DIM_SUBPASS:
3409 return 2;
3410 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3411 return 3;
3412 default:
3413 break;
3414 }
3415 return 0;
3416 }
3417
3418
3419
3420 /* Adjust the sample index according to FMASK.
3421 *
3422 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3423 * which is the identity mapping. Each nibble says which physical sample
3424 * should be fetched to get that sample.
3425 *
3426 * For example, 0x11111100 means there are only 2 samples stored and
3427 * the second sample covers 3/4 of the pixel. When reading samples 0
3428 * and 1, return physical sample 0 (determined by the first two 0s
3429 * in FMASK), otherwise return physical sample 1.
3430 *
3431 * The sample index should be adjusted as follows:
3432 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3433 */
3434 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3435 LLVMValueRef coord_x, LLVMValueRef coord_y,
3436 LLVMValueRef coord_z,
3437 LLVMValueRef sample_index,
3438 LLVMValueRef fmask_desc_ptr)
3439 {
3440 LLVMValueRef fmask_load_address[4];
3441 LLVMValueRef res;
3442
3443 fmask_load_address[0] = coord_x;
3444 fmask_load_address[1] = coord_y;
3445 if (coord_z) {
3446 fmask_load_address[2] = coord_z;
3447 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3448 }
3449
3450 struct ac_image_args args = {0};
3451
3452 args.opcode = ac_image_load;
3453 args.da = coord_z ? true : false;
3454 args.resource = fmask_desc_ptr;
3455 args.dmask = 0xf;
3456 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3457
3458 res = ac_build_image_opcode(ctx, &args);
3459
3460 res = ac_to_integer(ctx, res);
3461 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3462 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3463
3464 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3465 res,
3466 ctx->i32_0, "");
3467
3468 LLVMValueRef sample_index4 =
3469 LLVMBuildMul(ctx->builder, sample_index, four, "");
3470 LLVMValueRef shifted_fmask =
3471 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3472 LLVMValueRef final_sample =
3473 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3474
3475 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3476 * resource descriptor is 0 (invalid),
3477 */
3478 LLVMValueRef fmask_desc =
3479 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3480 ctx->v8i32, "");
3481
3482 LLVMValueRef fmask_word1 =
3483 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3484 ctx->i32_1, "");
3485
3486 LLVMValueRef word1_is_nonzero =
3487 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3488 fmask_word1, ctx->i32_0, "");
3489
3490 /* Replace the MSAA sample index. */
3491 sample_index =
3492 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3493 final_sample, sample_index, "");
3494 return sample_index;
3495 }
3496
3497 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3498 const nir_intrinsic_instr *instr)
3499 {
3500 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3501
3502 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3503 LLVMValueRef coords[4];
3504 LLVMValueRef masks[] = {
3505 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3506 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3507 };
3508 LLVMValueRef res;
3509 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3510
3511 int count;
3512 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3513 bool is_array = glsl_sampler_type_is_array(type);
3514 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3515 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3516 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3517 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3518 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3519 count = image_type_to_components_count(dim, is_array);
3520
3521 if (is_ms) {
3522 LLVMValueRef fmask_load_address[3];
3523 int chan;
3524
3525 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3526 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3527 if (is_array)
3528 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3529 else
3530 fmask_load_address[2] = NULL;
3531 if (add_frag_pos) {
3532 for (chan = 0; chan < 2; ++chan)
3533 fmask_load_address[chan] =
3534 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3535 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3536 ctx->ac.i32, ""), "");
3537 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3538 }
3539 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3540 fmask_load_address[0],
3541 fmask_load_address[1],
3542 fmask_load_address[2],
3543 sample_index,
3544 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3545 }
3546 if (count == 1 && !gfx9_1d) {
3547 if (instr->src[0].ssa->num_components)
3548 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3549 else
3550 res = src0;
3551 } else {
3552 int chan;
3553 if (is_ms)
3554 count--;
3555 for (chan = 0; chan < count; ++chan) {
3556 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3557 }
3558 if (add_frag_pos) {
3559 for (chan = 0; chan < 2; ++chan)
3560 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3561 ctx->ac.i32, ""), "");
3562 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3563 count++;
3564 }
3565
3566 if (gfx9_1d) {
3567 if (is_array) {
3568 coords[2] = coords[1];
3569 coords[1] = ctx->ac.i32_0;
3570 } else
3571 coords[1] = ctx->ac.i32_0;
3572 count++;
3573 }
3574
3575 if (is_ms) {
3576 coords[count] = sample_index;
3577 count++;
3578 }
3579
3580 if (count == 3) {
3581 coords[3] = LLVMGetUndef(ctx->ac.i32);
3582 count = 4;
3583 }
3584 res = ac_build_gather_values(&ctx->ac, coords, count);
3585 }
3586 return res;
3587 }
3588
3589 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3590 const nir_intrinsic_instr *instr)
3591 {
3592 LLVMValueRef params[7];
3593 LLVMValueRef res;
3594 char intrinsic_name[64];
3595 const nir_variable *var = instr->variables[0]->var;
3596 const struct glsl_type *type = var->type;
3597
3598 if(instr->variables[0]->deref.child)
3599 type = instr->variables[0]->deref.child->type;
3600
3601 type = glsl_without_array(type);
3602
3603 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3604 if (dim == GLSL_SAMPLER_DIM_BUF) {
3605 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3606 unsigned num_channels = util_last_bit(mask);
3607 LLVMValueRef rsrc, vindex;
3608
3609 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3610 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3611 ctx->ac.i32_0, "");
3612
3613 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3614 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3615 ctx->ac.i32_0, num_channels,
3616 false, false);
3617 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3618
3619 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3620 res = ac_to_integer(&ctx->ac, res);
3621 } else {
3622 bool is_da = glsl_sampler_type_is_array(type) ||
3623 dim == GLSL_SAMPLER_DIM_CUBE ||
3624 dim == GLSL_SAMPLER_DIM_3D ||
3625 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3627 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3628 LLVMValueRef glc = ctx->ac.i1false;
3629 LLVMValueRef slc = ctx->ac.i1false;
3630
3631 params[0] = get_image_coords(ctx, instr);
3632 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3633 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3634 params[3] = glc;
3635 params[4] = slc;
3636 params[5] = ctx->ac.i1false;
3637 params[6] = da;
3638
3639 ac_get_image_intr_name("llvm.amdgcn.image.load",
3640 ctx->ac.v4f32, /* vdata */
3641 LLVMTypeOf(params[0]), /* coords */
3642 LLVMTypeOf(params[1]), /* rsrc */
3643 intrinsic_name, sizeof(intrinsic_name));
3644
3645 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3646 params, 7, AC_FUNC_ATTR_READONLY);
3647 }
3648 return ac_to_integer(&ctx->ac, res);
3649 }
3650
3651 static void visit_image_store(struct ac_nir_context *ctx,
3652 nir_intrinsic_instr *instr)
3653 {
3654 LLVMValueRef params[8];
3655 char intrinsic_name[64];
3656 const nir_variable *var = instr->variables[0]->var;
3657 const struct glsl_type *type = glsl_without_array(var->type);
3658 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3659 LLVMValueRef glc = ctx->ac.i1false;
3660 bool force_glc = ctx->ac.chip_class == SI;
3661 if (force_glc)
3662 glc = ctx->ac.i1true;
3663
3664 if (dim == GLSL_SAMPLER_DIM_BUF) {
3665 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3666 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3667 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3668 ctx->ac.i32_0, ""); /* vindex */
3669 params[3] = ctx->ac.i32_0; /* voffset */
3670 params[4] = glc; /* glc */
3671 params[5] = ctx->ac.i1false; /* slc */
3672 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3673 params, 6, 0);
3674 } else {
3675 bool is_da = glsl_sampler_type_is_array(type) ||
3676 dim == GLSL_SAMPLER_DIM_CUBE ||
3677 dim == GLSL_SAMPLER_DIM_3D;
3678 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3679 LLVMValueRef slc = ctx->ac.i1false;
3680
3681 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3682 params[1] = get_image_coords(ctx, instr); /* coords */
3683 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3684 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3685 params[4] = glc;
3686 params[5] = slc;
3687 params[6] = ctx->ac.i1false;
3688 params[7] = da;
3689
3690 ac_get_image_intr_name("llvm.amdgcn.image.store",
3691 LLVMTypeOf(params[0]), /* vdata */
3692 LLVMTypeOf(params[1]), /* coords */
3693 LLVMTypeOf(params[2]), /* rsrc */
3694 intrinsic_name, sizeof(intrinsic_name));
3695
3696 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3697 params, 8, 0);
3698 }
3699
3700 }
3701
3702 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3703 const nir_intrinsic_instr *instr)
3704 {
3705 LLVMValueRef params[7];
3706 int param_count = 0;
3707 const nir_variable *var = instr->variables[0]->var;
3708
3709 const char *atomic_name;
3710 char intrinsic_name[41];
3711 const struct glsl_type *type = glsl_without_array(var->type);
3712 MAYBE_UNUSED int length;
3713
3714 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3715
3716 switch (instr->intrinsic) {
3717 case nir_intrinsic_image_atomic_add:
3718 atomic_name = "add";
3719 break;
3720 case nir_intrinsic_image_atomic_min:
3721 atomic_name = is_unsigned ? "umin" : "smin";
3722 break;
3723 case nir_intrinsic_image_atomic_max:
3724 atomic_name = is_unsigned ? "umax" : "smax";
3725 break;
3726 case nir_intrinsic_image_atomic_and:
3727 atomic_name = "and";
3728 break;
3729 case nir_intrinsic_image_atomic_or:
3730 atomic_name = "or";
3731 break;
3732 case nir_intrinsic_image_atomic_xor:
3733 atomic_name = "xor";
3734 break;
3735 case nir_intrinsic_image_atomic_exchange:
3736 atomic_name = "swap";
3737 break;
3738 case nir_intrinsic_image_atomic_comp_swap:
3739 atomic_name = "cmpswap";
3740 break;
3741 default:
3742 abort();
3743 }
3744
3745 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3746 params[param_count++] = get_src(ctx, instr->src[3]);
3747 params[param_count++] = get_src(ctx, instr->src[2]);
3748
3749 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3750 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3751 NULL, true, true);
3752 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3753 ctx->ac.i32_0, ""); /* vindex */
3754 params[param_count++] = ctx->ac.i32_0; /* voffset */
3755 params[param_count++] = ctx->ac.i1false; /* slc */
3756
3757 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3758 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3759 } else {
3760 char coords_type[8];
3761
3762 bool da = glsl_sampler_type_is_array(type) ||
3763 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3764
3765 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3766 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3767 NULL, true, true);
3768 params[param_count++] = ctx->ac.i1false; /* r128 */
3769 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3770 params[param_count++] = ctx->ac.i1false; /* slc */
3771
3772 build_int_type_name(LLVMTypeOf(coords),
3773 coords_type, sizeof(coords_type));
3774
3775 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3776 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3777 }
3778
3779 assert(length < sizeof(intrinsic_name));
3780 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3781 }
3782
3783 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3784 const nir_intrinsic_instr *instr)
3785 {
3786 LLVMValueRef res;
3787 const nir_variable *var = instr->variables[0]->var;
3788 const struct glsl_type *type = instr->variables[0]->var->type;
3789 bool da = glsl_sampler_type_is_array(var->type) ||
3790 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3791 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3792 if(instr->variables[0]->deref.child)
3793 type = instr->variables[0]->deref.child->type;
3794
3795 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3796 return get_buffer_size(ctx,
3797 get_sampler_desc(ctx, instr->variables[0],
3798 AC_DESC_BUFFER, NULL, true, false), true);
3799
3800 struct ac_image_args args = { 0 };
3801
3802 args.da = da;
3803 args.dmask = 0xf;
3804 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3805 args.opcode = ac_image_get_resinfo;
3806 args.addr = ctx->ac.i32_0;
3807
3808 res = ac_build_image_opcode(&ctx->ac, &args);
3809
3810 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3811
3812 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3813 glsl_sampler_type_is_array(type)) {
3814 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3815 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3816 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3817 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3818 }
3819 if (ctx->ac.chip_class >= GFX9 &&
3820 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3821 glsl_sampler_type_is_array(type)) {
3822 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3823 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3824 ctx->ac.i32_1, "");
3825
3826 }
3827 return res;
3828 }
3829
3830 #define NOOP_WAITCNT 0xf7f
3831 #define LGKM_CNT 0x07f
3832 #define VM_CNT 0xf70
3833
3834 static void emit_membar(struct ac_llvm_context *ac,
3835 const nir_intrinsic_instr *instr)
3836 {
3837 unsigned waitcnt = NOOP_WAITCNT;
3838
3839 switch (instr->intrinsic) {
3840 case nir_intrinsic_memory_barrier:
3841 case nir_intrinsic_group_memory_barrier:
3842 waitcnt &= VM_CNT & LGKM_CNT;
3843 break;
3844 case nir_intrinsic_memory_barrier_atomic_counter:
3845 case nir_intrinsic_memory_barrier_buffer:
3846 case nir_intrinsic_memory_barrier_image:
3847 waitcnt &= VM_CNT;
3848 break;
3849 case nir_intrinsic_memory_barrier_shared:
3850 waitcnt &= LGKM_CNT;
3851 break;
3852 default:
3853 break;
3854 }
3855 if (waitcnt != NOOP_WAITCNT)
3856 ac_build_waitcnt(ac, waitcnt);
3857 }
3858
3859 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3860 {
3861 /* SI only (thanks to a hw bug workaround):
3862 * The real barrier instruction isn’t needed, because an entire patch
3863 * always fits into a single wave.
3864 */
3865 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3866 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3867 return;
3868 }
3869 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3870 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3871 }
3872
3873 static void emit_discard(struct ac_nir_context *ctx,
3874 const nir_intrinsic_instr *instr)
3875 {
3876 LLVMValueRef cond;
3877
3878 if (instr->intrinsic == nir_intrinsic_discard_if) {
3879 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3880 get_src(ctx, instr->src[0]),
3881 ctx->ac.i32_0, "");
3882 } else {
3883 assert(instr->intrinsic == nir_intrinsic_discard);
3884 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3885 }
3886
3887 ac_build_kill_if_false(&ctx->ac, cond);
3888 }
3889
3890 static LLVMValueRef
3891 visit_load_helper_invocation(struct ac_nir_context *ctx)
3892 {
3893 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3894 "llvm.amdgcn.ps.live",
3895 ctx->ac.i1, NULL, 0,
3896 AC_FUNC_ATTR_READNONE);
3897 result = LLVMBuildNot(ctx->ac.builder, result, "");
3898 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3899 }
3900
3901 static LLVMValueRef
3902 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3903 {
3904 LLVMValueRef result;
3905 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3906 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3907 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3908
3909 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3910 }
3911
3912 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3913 const nir_intrinsic_instr *instr)
3914 {
3915 LLVMValueRef ptr, result;
3916 LLVMValueRef src = get_src(ctx, instr->src[0]);
3917 ptr = build_gep_for_deref(ctx, instr->variables[0]);
3918
3919 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3920 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3921 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3922 ptr, src, src1,
3923 LLVMAtomicOrderingSequentiallyConsistent,
3924 LLVMAtomicOrderingSequentiallyConsistent,
3925 false);
3926 } else {
3927 LLVMAtomicRMWBinOp op;
3928 switch (instr->intrinsic) {
3929 case nir_intrinsic_var_atomic_add:
3930 op = LLVMAtomicRMWBinOpAdd;
3931 break;
3932 case nir_intrinsic_var_atomic_umin:
3933 op = LLVMAtomicRMWBinOpUMin;
3934 break;
3935 case nir_intrinsic_var_atomic_umax:
3936 op = LLVMAtomicRMWBinOpUMax;
3937 break;
3938 case nir_intrinsic_var_atomic_imin:
3939 op = LLVMAtomicRMWBinOpMin;
3940 break;
3941 case nir_intrinsic_var_atomic_imax:
3942 op = LLVMAtomicRMWBinOpMax;
3943 break;
3944 case nir_intrinsic_var_atomic_and:
3945 op = LLVMAtomicRMWBinOpAnd;
3946 break;
3947 case nir_intrinsic_var_atomic_or:
3948 op = LLVMAtomicRMWBinOpOr;
3949 break;
3950 case nir_intrinsic_var_atomic_xor:
3951 op = LLVMAtomicRMWBinOpXor;
3952 break;
3953 case nir_intrinsic_var_atomic_exchange:
3954 op = LLVMAtomicRMWBinOpXchg;
3955 break;
3956 default:
3957 return NULL;
3958 }
3959
3960 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
3961 LLVMAtomicOrderingSequentiallyConsistent,
3962 false);
3963 }
3964 return result;
3965 }
3966
3967 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3968 enum glsl_interp_mode interp, unsigned location)
3969 {
3970 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3971
3972 switch (interp) {
3973 case INTERP_MODE_FLAT:
3974 default:
3975 return NULL;
3976 case INTERP_MODE_SMOOTH:
3977 case INTERP_MODE_NONE:
3978 if (location == INTERP_CENTER)
3979 return ctx->persp_center;
3980 else if (location == INTERP_CENTROID)
3981 return ctx->persp_centroid;
3982 else if (location == INTERP_SAMPLE)
3983 return ctx->persp_sample;
3984 break;
3985 case INTERP_MODE_NOPERSPECTIVE:
3986 if (location == INTERP_CENTER)
3987 return ctx->linear_center;
3988 else if (location == INTERP_CENTROID)
3989 return ctx->linear_centroid;
3990 else if (location == INTERP_SAMPLE)
3991 return ctx->linear_sample;
3992 break;
3993 }
3994 return NULL;
3995 }
3996
3997 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
3998 LLVMValueRef sample_id)
3999 {
4000 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4001
4002 LLVMValueRef result;
4003 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4004
4005 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4006 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4007
4008 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4009 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4010
4011 return result;
4012 }
4013
4014 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4015 {
4016 LLVMValueRef values[2];
4017
4018 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4019 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4020 return ac_build_gather_values(&ctx->ac, values, 2);
4021 }
4022
4023 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4024 {
4025 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4026 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4027 ctx->options->key.fs.log2_num_samples :
4028 ctx->options->key.fs.log2_ps_iter_samples;
4029
4030 /* The bit pattern matches that used by fixed function fragment
4031 * processing. */
4032 static const uint16_t ps_iter_masks[] = {
4033 0xffff, /* not used */
4034 0x5555,
4035 0x1111,
4036 0x0101,
4037 0x0001,
4038 };
4039 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4040
4041 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4042
4043 LLVMValueRef result, sample_id;
4044 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4045 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4046 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4047 return result;
4048 }
4049
4050 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4051 const nir_intrinsic_instr *instr)
4052 {
4053 LLVMValueRef result[4];
4054 LLVMValueRef interp_param, attr_number;
4055 unsigned location;
4056 unsigned chan;
4057 LLVMValueRef src_c0 = NULL;
4058 LLVMValueRef src_c1 = NULL;
4059 LLVMValueRef src0 = NULL;
4060 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4061 switch (instr->intrinsic) {
4062 case nir_intrinsic_interp_var_at_centroid:
4063 location = INTERP_CENTROID;
4064 break;
4065 case nir_intrinsic_interp_var_at_sample:
4066 case nir_intrinsic_interp_var_at_offset:
4067 location = INTERP_CENTER;
4068 src0 = get_src(ctx, instr->src[0]);
4069 break;
4070 default:
4071 break;
4072 }
4073
4074 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4075 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4076 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4077 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4078 LLVMValueRef sample_position;
4079 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4080
4081 /* fetch sample ID */
4082 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4083
4084 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4085 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4086 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4087 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4088 }
4089 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4090 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4091
4092 if (location == INTERP_CENTER) {
4093 LLVMValueRef ij_out[2];
4094 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4095
4096 /*
4097 * take the I then J parameters, and the DDX/Y for it, and
4098 * calculate the IJ inputs for the interpolator.
4099 * temp1 = ddx * offset/sample.x + I;
4100 * interp_param.I = ddy * offset/sample.y + temp1;
4101 * temp1 = ddx * offset/sample.x + J;
4102 * interp_param.J = ddy * offset/sample.y + temp1;
4103 */
4104 for (unsigned i = 0; i < 2; i++) {
4105 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4106 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4107 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4108 ddxy_out, ix_ll, "");
4109 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4110 ddxy_out, iy_ll, "");
4111 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4112 interp_param, ix_ll, "");
4113 LLVMValueRef temp1, temp2;
4114
4115 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4116 ctx->ac.f32, "");
4117
4118 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4119 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4120
4121 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4122 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4123
4124 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4125 temp2, ctx->ac.i32, "");
4126 }
4127 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4128
4129 }
4130
4131 for (chan = 0; chan < 4; chan++) {
4132 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4133
4134 if (interp_param) {
4135 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4136 interp_param, ctx->ac.v2f32, "");
4137 LLVMValueRef i = LLVMBuildExtractElement(
4138 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4139 LLVMValueRef j = LLVMBuildExtractElement(
4140 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4141
4142 result[chan] = ac_build_fs_interp(&ctx->ac,
4143 llvm_chan, attr_number,
4144 ctx->abi->prim_mask, i, j);
4145 } else {
4146 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4147 LLVMConstInt(ctx->ac.i32, 2, false),
4148 llvm_chan, attr_number,
4149 ctx->abi->prim_mask);
4150 }
4151 }
4152 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4153 instr->variables[0]->var->data.location_frac);
4154 }
4155
4156 static void
4157 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4158 {
4159 LLVMValueRef gs_next_vertex;
4160 LLVMValueRef can_emit;
4161 int idx;
4162 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4163
4164 assert(stream == 0);
4165
4166 /* Write vertex attribute values to GSVS ring */
4167 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4168 ctx->gs_next_vertex,
4169 "");
4170
4171 /* If this thread has already emitted the declared maximum number of
4172 * vertices, kill it: excessive vertex emissions are not supposed to
4173 * have any effect, and GS threads have no externally observable
4174 * effects other than emitting vertices.
4175 */
4176 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4177 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4178 ac_build_kill_if_false(&ctx->ac, can_emit);
4179
4180 /* loop num outputs */
4181 idx = 0;
4182 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4183 LLVMValueRef *out_ptr = &addrs[i * 4];
4184 int length = 4;
4185 int slot = idx;
4186 int slot_inc = 1;
4187
4188 if (!(ctx->output_mask & (1ull << i)))
4189 continue;
4190
4191 if (i == VARYING_SLOT_CLIP_DIST0) {
4192 /* pack clip and cull into a single set of slots */
4193 length = ctx->num_output_clips + ctx->num_output_culls;
4194 if (length > 4)
4195 slot_inc = 2;
4196 }
4197 for (unsigned j = 0; j < length; j++) {
4198 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4199 out_ptr[j], "");
4200 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4201 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4202 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4203
4204 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4205
4206 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4207 out_val, 1,
4208 voffset, ctx->gs2vs_offset, 0,
4209 1, 1, true, true);
4210 }
4211 idx += slot_inc;
4212 }
4213
4214 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4215 ctx->ac.i32_1, "");
4216 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4217
4218 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4219 }
4220
4221 static void
4222 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4223 {
4224 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4225 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4226 }
4227
4228 static LLVMValueRef
4229 load_tess_coord(struct ac_shader_abi *abi)
4230 {
4231 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4232
4233 LLVMValueRef coord[4] = {
4234 ctx->tes_u,
4235 ctx->tes_v,
4236 ctx->ac.f32_0,
4237 ctx->ac.f32_0,
4238 };
4239
4240 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4241 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4242 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4243
4244 return ac_build_gather_values(&ctx->ac, coord, 3);
4245 }
4246
4247 static LLVMValueRef
4248 load_patch_vertices_in(struct ac_shader_abi *abi)
4249 {
4250 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4251 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4252 }
4253
4254 static void visit_intrinsic(struct ac_nir_context *ctx,
4255 nir_intrinsic_instr *instr)
4256 {
4257 LLVMValueRef result = NULL;
4258
4259 switch (instr->intrinsic) {
4260 case nir_intrinsic_ballot:
4261 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4262 break;
4263 case nir_intrinsic_read_invocation:
4264 case nir_intrinsic_read_first_invocation: {
4265 LLVMValueRef args[2];
4266
4267 /* Value */
4268 args[0] = get_src(ctx, instr->src[0]);
4269
4270 unsigned num_args;
4271 const char *intr_name;
4272 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4273 num_args = 2;
4274 intr_name = "llvm.amdgcn.readlane";
4275
4276 /* Invocation */
4277 args[1] = get_src(ctx, instr->src[1]);
4278 } else {
4279 num_args = 1;
4280 intr_name = "llvm.amdgcn.readfirstlane";
4281 }
4282
4283 /* We currently have no other way to prevent LLVM from lifting the icmp
4284 * calls to a dominating basic block.
4285 */
4286 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4287
4288 result = ac_build_intrinsic(&ctx->ac, intr_name,
4289 ctx->ac.i32, args, num_args,
4290 AC_FUNC_ATTR_READNONE |
4291 AC_FUNC_ATTR_CONVERGENT);
4292 break;
4293 }
4294 case nir_intrinsic_load_subgroup_invocation:
4295 result = ac_get_thread_id(&ctx->ac);
4296 break;
4297 case nir_intrinsic_load_work_group_id: {
4298 LLVMValueRef values[3];
4299
4300 for (int i = 0; i < 3; i++) {
4301 values[i] = ctx->abi->workgroup_ids[i] ?
4302 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4303 }
4304
4305 result = ac_build_gather_values(&ctx->ac, values, 3);
4306 break;
4307 }
4308 case nir_intrinsic_load_base_vertex: {
4309 result = ctx->abi->base_vertex;
4310 break;
4311 }
4312 case nir_intrinsic_load_local_group_size:
4313 result = ctx->abi->load_local_group_size(ctx->abi);
4314 break;
4315 case nir_intrinsic_load_vertex_id_zero_base: {
4316 result = ctx->abi->vertex_id;
4317 break;
4318 }
4319 case nir_intrinsic_load_local_invocation_id: {
4320 result = ctx->abi->local_invocation_ids;
4321 break;
4322 }
4323 case nir_intrinsic_load_base_instance:
4324 result = ctx->abi->start_instance;
4325 break;
4326 case nir_intrinsic_load_draw_id:
4327 result = ctx->abi->draw_id;
4328 break;
4329 case nir_intrinsic_load_view_index:
4330 result = ctx->abi->view_index;
4331 break;
4332 case nir_intrinsic_load_invocation_id:
4333 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4334 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4335 else
4336 result = ctx->abi->gs_invocation_id;
4337 break;
4338 case nir_intrinsic_load_primitive_id:
4339 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4340 result = ctx->abi->gs_prim_id;
4341 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4342 result = ctx->abi->tcs_patch_id;
4343 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4344 result = ctx->abi->tes_patch_id;
4345 } else
4346 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4347 break;
4348 case nir_intrinsic_load_sample_id:
4349 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4350 break;
4351 case nir_intrinsic_load_sample_pos:
4352 result = load_sample_pos(ctx);
4353 break;
4354 case nir_intrinsic_load_sample_mask_in:
4355 result = ctx->abi->load_sample_mask_in(ctx->abi);
4356 break;
4357 case nir_intrinsic_load_frag_coord: {
4358 LLVMValueRef values[4] = {
4359 ctx->abi->frag_pos[0],
4360 ctx->abi->frag_pos[1],
4361 ctx->abi->frag_pos[2],
4362 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4363 };
4364 result = ac_build_gather_values(&ctx->ac, values, 4);
4365 break;
4366 }
4367 case nir_intrinsic_load_front_face:
4368 result = ctx->abi->front_face;
4369 break;
4370 case nir_intrinsic_load_helper_invocation:
4371 result = visit_load_helper_invocation(ctx);
4372 break;
4373 case nir_intrinsic_load_instance_id:
4374 result = ctx->abi->instance_id;
4375 break;
4376 case nir_intrinsic_load_num_work_groups:
4377 result = ctx->abi->num_work_groups;
4378 break;
4379 case nir_intrinsic_load_local_invocation_index:
4380 result = visit_load_local_invocation_index(ctx);
4381 break;
4382 case nir_intrinsic_load_push_constant:
4383 result = visit_load_push_constant(ctx, instr);
4384 break;
4385 case nir_intrinsic_vulkan_resource_index: {
4386 LLVMValueRef index = get_src(ctx, instr->src[0]);
4387 unsigned desc_set = nir_intrinsic_desc_set(instr);
4388 unsigned binding = nir_intrinsic_binding(instr);
4389
4390 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4391 binding);
4392 break;
4393 }
4394 case nir_intrinsic_vulkan_resource_reindex:
4395 result = visit_vulkan_resource_reindex(ctx, instr);
4396 break;
4397 case nir_intrinsic_store_ssbo:
4398 visit_store_ssbo(ctx, instr);
4399 break;
4400 case nir_intrinsic_load_ssbo:
4401 result = visit_load_buffer(ctx, instr);
4402 break;
4403 case nir_intrinsic_ssbo_atomic_add:
4404 case nir_intrinsic_ssbo_atomic_imin:
4405 case nir_intrinsic_ssbo_atomic_umin:
4406 case nir_intrinsic_ssbo_atomic_imax:
4407 case nir_intrinsic_ssbo_atomic_umax:
4408 case nir_intrinsic_ssbo_atomic_and:
4409 case nir_intrinsic_ssbo_atomic_or:
4410 case nir_intrinsic_ssbo_atomic_xor:
4411 case nir_intrinsic_ssbo_atomic_exchange:
4412 case nir_intrinsic_ssbo_atomic_comp_swap:
4413 result = visit_atomic_ssbo(ctx, instr);
4414 break;
4415 case nir_intrinsic_load_ubo:
4416 result = visit_load_ubo_buffer(ctx, instr);
4417 break;
4418 case nir_intrinsic_get_buffer_size:
4419 result = visit_get_buffer_size(ctx, instr);
4420 break;
4421 case nir_intrinsic_load_var:
4422 result = visit_load_var(ctx, instr);
4423 break;
4424 case nir_intrinsic_store_var:
4425 visit_store_var(ctx, instr);
4426 break;
4427 case nir_intrinsic_image_load:
4428 result = visit_image_load(ctx, instr);
4429 break;
4430 case nir_intrinsic_image_store:
4431 visit_image_store(ctx, instr);
4432 break;
4433 case nir_intrinsic_image_atomic_add:
4434 case nir_intrinsic_image_atomic_min:
4435 case nir_intrinsic_image_atomic_max:
4436 case nir_intrinsic_image_atomic_and:
4437 case nir_intrinsic_image_atomic_or:
4438 case nir_intrinsic_image_atomic_xor:
4439 case nir_intrinsic_image_atomic_exchange:
4440 case nir_intrinsic_image_atomic_comp_swap:
4441 result = visit_image_atomic(ctx, instr);
4442 break;
4443 case nir_intrinsic_image_size:
4444 result = visit_image_size(ctx, instr);
4445 break;
4446 case nir_intrinsic_shader_clock:
4447 result = ac_build_shader_clock(&ctx->ac);
4448 break;
4449 case nir_intrinsic_discard:
4450 case nir_intrinsic_discard_if:
4451 emit_discard(ctx, instr);
4452 break;
4453 case nir_intrinsic_memory_barrier:
4454 case nir_intrinsic_group_memory_barrier:
4455 case nir_intrinsic_memory_barrier_atomic_counter:
4456 case nir_intrinsic_memory_barrier_buffer:
4457 case nir_intrinsic_memory_barrier_image:
4458 case nir_intrinsic_memory_barrier_shared:
4459 emit_membar(&ctx->ac, instr);
4460 break;
4461 case nir_intrinsic_barrier:
4462 emit_barrier(&ctx->ac, ctx->stage);
4463 break;
4464 case nir_intrinsic_var_atomic_add:
4465 case nir_intrinsic_var_atomic_imin:
4466 case nir_intrinsic_var_atomic_umin:
4467 case nir_intrinsic_var_atomic_imax:
4468 case nir_intrinsic_var_atomic_umax:
4469 case nir_intrinsic_var_atomic_and:
4470 case nir_intrinsic_var_atomic_or:
4471 case nir_intrinsic_var_atomic_xor:
4472 case nir_intrinsic_var_atomic_exchange:
4473 case nir_intrinsic_var_atomic_comp_swap:
4474 result = visit_var_atomic(ctx, instr);
4475 break;
4476 case nir_intrinsic_interp_var_at_centroid:
4477 case nir_intrinsic_interp_var_at_sample:
4478 case nir_intrinsic_interp_var_at_offset:
4479 result = visit_interp(ctx, instr);
4480 break;
4481 case nir_intrinsic_emit_vertex:
4482 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4483 break;
4484 case nir_intrinsic_end_primitive:
4485 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4486 break;
4487 case nir_intrinsic_load_tess_coord:
4488 result = ctx->abi->load_tess_coord(ctx->abi);
4489 break;
4490 case nir_intrinsic_load_tess_level_outer:
4491 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4492 break;
4493 case nir_intrinsic_load_tess_level_inner:
4494 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4495 break;
4496 case nir_intrinsic_load_patch_vertices_in:
4497 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4498 break;
4499 case nir_intrinsic_vote_all: {
4500 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4501 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4502 break;
4503 }
4504 case nir_intrinsic_vote_any: {
4505 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4506 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4507 break;
4508 }
4509 case nir_intrinsic_vote_eq: {
4510 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4511 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4512 break;
4513 }
4514 default:
4515 fprintf(stderr, "Unknown intrinsic: ");
4516 nir_print_instr(&instr->instr, stderr);
4517 fprintf(stderr, "\n");
4518 break;
4519 }
4520 if (result) {
4521 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4522 }
4523 }
4524
4525 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4526 LLVMValueRef buffer_ptr, bool write)
4527 {
4528 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4529 LLVMValueRef result;
4530
4531 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4532
4533 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4534 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4535
4536 return result;
4537 }
4538
4539 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4540 {
4541 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4542 LLVMValueRef result;
4543
4544 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4545
4546 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4547 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4548
4549 return result;
4550 }
4551
4552 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4553 unsigned descriptor_set,
4554 unsigned base_index,
4555 unsigned constant_index,
4556 LLVMValueRef index,
4557 enum ac_descriptor_type desc_type,
4558 bool image, bool write)
4559 {
4560 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4561 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4562 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4563 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4564 unsigned offset = binding->offset;
4565 unsigned stride = binding->size;
4566 unsigned type_size;
4567 LLVMBuilderRef builder = ctx->ac.builder;
4568 LLVMTypeRef type;
4569
4570 assert(base_index < layout->binding_count);
4571
4572 switch (desc_type) {
4573 case AC_DESC_IMAGE:
4574 type = ctx->ac.v8i32;
4575 type_size = 32;
4576 break;
4577 case AC_DESC_FMASK:
4578 type = ctx->ac.v8i32;
4579 offset += 32;
4580 type_size = 32;
4581 break;
4582 case AC_DESC_SAMPLER:
4583 type = ctx->ac.v4i32;
4584 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4585 offset += 64;
4586
4587 type_size = 16;
4588 break;
4589 case AC_DESC_BUFFER:
4590 type = ctx->ac.v4i32;
4591 type_size = 16;
4592 break;
4593 default:
4594 unreachable("invalid desc_type\n");
4595 }
4596
4597 offset += constant_index * stride;
4598
4599 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4600 (!index || binding->immutable_samplers_equal)) {
4601 if (binding->immutable_samplers_equal)
4602 constant_index = 0;
4603
4604 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4605
4606 LLVMValueRef constants[] = {
4607 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4608 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4609 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4610 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4611 };
4612 return ac_build_gather_values(&ctx->ac, constants, 4);
4613 }
4614
4615 assert(stride % type_size == 0);
4616
4617 if (!index)
4618 index = ctx->ac.i32_0;
4619
4620 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4621
4622 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4623 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4624
4625 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4626 }
4627
4628 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4629 const nir_deref_var *deref,
4630 enum ac_descriptor_type desc_type,
4631 const nir_tex_instr *tex_instr,
4632 bool image, bool write)
4633 {
4634 LLVMValueRef index = NULL;
4635 unsigned constant_index = 0;
4636 unsigned descriptor_set;
4637 unsigned base_index;
4638
4639 if (!deref) {
4640 assert(tex_instr && !image);
4641 descriptor_set = 0;
4642 base_index = tex_instr->sampler_index;
4643 } else {
4644 const nir_deref *tail = &deref->deref;
4645 while (tail->child) {
4646 const nir_deref_array *child = nir_deref_as_array(tail->child);
4647 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4648
4649 if (!array_size)
4650 array_size = 1;
4651
4652 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4653
4654 if (child->deref_array_type == nir_deref_array_type_indirect) {
4655 LLVMValueRef indirect = get_src(ctx, child->indirect);
4656
4657 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4658 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4659
4660 if (!index)
4661 index = indirect;
4662 else
4663 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4664 }
4665
4666 constant_index += child->base_offset * array_size;
4667
4668 tail = &child->deref;
4669 }
4670 descriptor_set = deref->var->data.descriptor_set;
4671 base_index = deref->var->data.binding;
4672 }
4673
4674 return ctx->abi->load_sampler_desc(ctx->abi,
4675 descriptor_set,
4676 base_index,
4677 constant_index, index,
4678 desc_type, image, write);
4679 }
4680
4681 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4682 struct ac_image_args *args,
4683 const nir_tex_instr *instr,
4684 nir_texop op,
4685 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4686 LLVMValueRef *param, unsigned count,
4687 unsigned dmask)
4688 {
4689 unsigned is_rect = 0;
4690 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4691
4692 if (op == nir_texop_lod)
4693 da = false;
4694 /* Pad to power of two vector */
4695 while (count < util_next_power_of_two(count))
4696 param[count++] = LLVMGetUndef(ctx->i32);
4697
4698 if (count > 1)
4699 args->addr = ac_build_gather_values(ctx, param, count);
4700 else
4701 args->addr = param[0];
4702
4703 args->resource = res_ptr;
4704 args->sampler = samp_ptr;
4705
4706 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4707 args->addr = param[0];
4708 return;
4709 }
4710
4711 args->dmask = dmask;
4712 args->unorm = is_rect;
4713 args->da = da;
4714 }
4715
4716 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4717 *
4718 * SI-CI:
4719 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4720 * filtering manually. The driver sets img7 to a mask clearing
4721 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4722 * s_and_b32 samp0, samp0, img7
4723 *
4724 * VI:
4725 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4726 */
4727 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4728 LLVMValueRef res, LLVMValueRef samp)
4729 {
4730 LLVMBuilderRef builder = ctx->ac.builder;
4731 LLVMValueRef img7, samp0;
4732
4733 if (ctx->ac.chip_class >= VI)
4734 return samp;
4735
4736 img7 = LLVMBuildExtractElement(builder, res,
4737 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4738 samp0 = LLVMBuildExtractElement(builder, samp,
4739 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4740 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4741 return LLVMBuildInsertElement(builder, samp, samp0,
4742 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4743 }
4744
4745 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4746 nir_tex_instr *instr,
4747 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4748 LLVMValueRef *fmask_ptr)
4749 {
4750 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4751 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4752 else
4753 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4754 if (samp_ptr) {
4755 if (instr->sampler)
4756 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4757 else
4758 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4759 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4760 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4761 }
4762 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4763 instr->op == nir_texop_samples_identical))
4764 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4765 }
4766
4767 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4768 LLVMValueRef coord)
4769 {
4770 coord = ac_to_float(ctx, coord);
4771 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4772 coord = ac_to_integer(ctx, coord);
4773 return coord;
4774 }
4775
4776 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4777 {
4778 LLVMValueRef result = NULL;
4779 struct ac_image_args args = { 0 };
4780 unsigned dmask = 0xf;
4781 LLVMValueRef address[16];
4782 LLVMValueRef coords[5];
4783 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4784 LLVMValueRef bias = NULL, offsets = NULL;
4785 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4786 LLVMValueRef ddx = NULL, ddy = NULL;
4787 LLVMValueRef derivs[6];
4788 unsigned chan, count = 0;
4789 unsigned const_src = 0, num_deriv_comp = 0;
4790 bool lod_is_zero = false;
4791
4792 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4793
4794 for (unsigned i = 0; i < instr->num_srcs; i++) {
4795 switch (instr->src[i].src_type) {
4796 case nir_tex_src_coord:
4797 coord = get_src(ctx, instr->src[i].src);
4798 break;
4799 case nir_tex_src_projector:
4800 break;
4801 case nir_tex_src_comparator:
4802 comparator = get_src(ctx, instr->src[i].src);
4803 break;
4804 case nir_tex_src_offset:
4805 offsets = get_src(ctx, instr->src[i].src);
4806 const_src = i;
4807 break;
4808 case nir_tex_src_bias:
4809 bias = get_src(ctx, instr->src[i].src);
4810 break;
4811 case nir_tex_src_lod: {
4812 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4813
4814 if (val && val->i32[0] == 0)
4815 lod_is_zero = true;
4816 lod = get_src(ctx, instr->src[i].src);
4817 break;
4818 }
4819 case nir_tex_src_ms_index:
4820 sample_index = get_src(ctx, instr->src[i].src);
4821 break;
4822 case nir_tex_src_ms_mcs:
4823 break;
4824 case nir_tex_src_ddx:
4825 ddx = get_src(ctx, instr->src[i].src);
4826 num_deriv_comp = instr->src[i].src.ssa->num_components;
4827 break;
4828 case nir_tex_src_ddy:
4829 ddy = get_src(ctx, instr->src[i].src);
4830 break;
4831 case nir_tex_src_texture_offset:
4832 case nir_tex_src_sampler_offset:
4833 case nir_tex_src_plane:
4834 default:
4835 break;
4836 }
4837 }
4838
4839 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4840 result = get_buffer_size(ctx, res_ptr, true);
4841 goto write_result;
4842 }
4843
4844 if (instr->op == nir_texop_texture_samples) {
4845 LLVMValueRef res, samples, is_msaa;
4846 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4847 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4848 LLVMConstInt(ctx->ac.i32, 3, false), "");
4849 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4850 LLVMConstInt(ctx->ac.i32, 28, false), "");
4851 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4852 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4853 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4854 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4855
4856 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4857 LLVMConstInt(ctx->ac.i32, 16, false), "");
4858 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4859 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4860 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4861 samples, "");
4862 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4863 ctx->ac.i32_1, "");
4864 result = samples;
4865 goto write_result;
4866 }
4867
4868 if (coord)
4869 for (chan = 0; chan < instr->coord_components; chan++)
4870 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4871
4872 if (offsets && instr->op != nir_texop_txf) {
4873 LLVMValueRef offset[3], pack;
4874 for (chan = 0; chan < 3; ++chan)
4875 offset[chan] = ctx->ac.i32_0;
4876
4877 args.offset = true;
4878 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4879 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4880 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4881 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4882 if (chan)
4883 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4884 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4885 }
4886 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4887 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4888 address[count++] = pack;
4889
4890 }
4891 /* pack LOD bias value */
4892 if (instr->op == nir_texop_txb && bias) {
4893 address[count++] = bias;
4894 }
4895
4896 /* Pack depth comparison value */
4897 if (instr->is_shadow && comparator) {
4898 LLVMValueRef z = ac_to_float(&ctx->ac,
4899 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4900
4901 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4902 * so the depth comparison value isn't clamped for Z16 and
4903 * Z24 anymore. Do it manually here.
4904 *
4905 * It's unnecessary if the original texture format was
4906 * Z32_FLOAT, but we don't know that here.
4907 */
4908 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4909 z = ac_build_clamp(&ctx->ac, z);
4910
4911 address[count++] = z;
4912 }
4913
4914 /* pack derivatives */
4915 if (ddx || ddy) {
4916 int num_src_deriv_channels, num_dest_deriv_channels;
4917 switch (instr->sampler_dim) {
4918 case GLSL_SAMPLER_DIM_3D:
4919 case GLSL_SAMPLER_DIM_CUBE:
4920 num_deriv_comp = 3;
4921 num_src_deriv_channels = 3;
4922 num_dest_deriv_channels = 3;
4923 break;
4924 case GLSL_SAMPLER_DIM_2D:
4925 default:
4926 num_src_deriv_channels = 2;
4927 num_dest_deriv_channels = 2;
4928 num_deriv_comp = 2;
4929 break;
4930 case GLSL_SAMPLER_DIM_1D:
4931 num_src_deriv_channels = 1;
4932 if (ctx->ac.chip_class >= GFX9) {
4933 num_dest_deriv_channels = 2;
4934 num_deriv_comp = 2;
4935 } else {
4936 num_dest_deriv_channels = 1;
4937 num_deriv_comp = 1;
4938 }
4939 break;
4940 }
4941
4942 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4943 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4944 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4945 }
4946 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4947 derivs[i] = ctx->ac.f32_0;
4948 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4949 }
4950 }
4951
4952 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4953 for (chan = 0; chan < instr->coord_components; chan++)
4954 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4955 if (instr->coord_components == 3)
4956 coords[3] = LLVMGetUndef(ctx->ac.f32);
4957 ac_prepare_cube_coords(&ctx->ac,
4958 instr->op == nir_texop_txd, instr->is_array,
4959 instr->op == nir_texop_lod, coords, derivs);
4960 if (num_deriv_comp)
4961 num_deriv_comp--;
4962 }
4963
4964 if (ddx || ddy) {
4965 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4966 address[count++] = derivs[i];
4967 }
4968
4969 /* Pack texture coordinates */
4970 if (coord) {
4971 address[count++] = coords[0];
4972 if (instr->coord_components > 1) {
4973 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4974 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4975 }
4976 address[count++] = coords[1];
4977 }
4978 if (instr->coord_components > 2) {
4979 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4980 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4981 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4982 instr->op != nir_texop_txf) {
4983 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4984 }
4985 address[count++] = coords[2];
4986 }
4987
4988 if (ctx->ac.chip_class >= GFX9) {
4989 LLVMValueRef filler;
4990 if (instr->op == nir_texop_txf)
4991 filler = ctx->ac.i32_0;
4992 else
4993 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4994
4995 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4996 /* No nir_texop_lod, because it does not take a slice
4997 * even with array textures. */
4998 if (instr->is_array && instr->op != nir_texop_lod ) {
4999 address[count] = address[count - 1];
5000 address[count - 1] = filler;
5001 count++;
5002 } else
5003 address[count++] = filler;
5004 }
5005 }
5006 }
5007
5008 /* Pack LOD */
5009 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5010 instr->op == nir_texop_txf)) {
5011 address[count++] = lod;
5012 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5013 address[count++] = sample_index;
5014 } else if(instr->op == nir_texop_txs) {
5015 count = 0;
5016 if (lod)
5017 address[count++] = lod;
5018 else
5019 address[count++] = ctx->ac.i32_0;
5020 }
5021
5022 for (chan = 0; chan < count; chan++) {
5023 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5024 address[chan], ctx->ac.i32, "");
5025 }
5026
5027 if (instr->op == nir_texop_samples_identical) {
5028 LLVMValueRef txf_address[4];
5029 struct ac_image_args txf_args = { 0 };
5030 unsigned txf_count = count;
5031 memcpy(txf_address, address, sizeof(txf_address));
5032
5033 if (!instr->is_array)
5034 txf_address[2] = ctx->ac.i32_0;
5035 txf_address[3] = ctx->ac.i32_0;
5036
5037 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5038 fmask_ptr, NULL,
5039 txf_address, txf_count, 0xf);
5040
5041 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5042
5043 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5044 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5045 goto write_result;
5046 }
5047
5048 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5049 instr->op != nir_texop_txs) {
5050 unsigned sample_chan = instr->is_array ? 3 : 2;
5051 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5052 address[0],
5053 address[1],
5054 instr->is_array ? address[2] : NULL,
5055 address[sample_chan],
5056 fmask_ptr);
5057 }
5058
5059 if (offsets && instr->op == nir_texop_txf) {
5060 nir_const_value *const_offset =
5061 nir_src_as_const_value(instr->src[const_src].src);
5062 int num_offsets = instr->src[const_src].src.ssa->num_components;
5063 assert(const_offset);
5064 num_offsets = MIN2(num_offsets, instr->coord_components);
5065 if (num_offsets > 2)
5066 address[2] = LLVMBuildAdd(ctx->ac.builder,
5067 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5068 if (num_offsets > 1)
5069 address[1] = LLVMBuildAdd(ctx->ac.builder,
5070 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5071 address[0] = LLVMBuildAdd(ctx->ac.builder,
5072 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5073
5074 }
5075
5076 /* TODO TG4 support */
5077 if (instr->op == nir_texop_tg4) {
5078 if (instr->is_shadow)
5079 dmask = 1;
5080 else
5081 dmask = 1 << instr->component;
5082 }
5083 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5084 res_ptr, samp_ptr, address, count, dmask);
5085
5086 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5087
5088 if (instr->op == nir_texop_query_levels)
5089 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5090 else if (instr->is_shadow && instr->is_new_style_shadow &&
5091 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5092 instr->op != nir_texop_tg4)
5093 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5094 else if (instr->op == nir_texop_txs &&
5095 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5096 instr->is_array) {
5097 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5098 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5099 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5100 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5101 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5102 } else if (ctx->ac.chip_class >= GFX9 &&
5103 instr->op == nir_texop_txs &&
5104 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5105 instr->is_array) {
5106 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5107 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5108 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5109 ctx->ac.i32_1, "");
5110 } else if (instr->dest.ssa.num_components != 4)
5111 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5112
5113 write_result:
5114 if (result) {
5115 assert(instr->dest.is_ssa);
5116 result = ac_to_integer(&ctx->ac, result);
5117 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5118 }
5119 }
5120
5121
5122 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5123 {
5124 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5125 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5126
5127 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5128 _mesa_hash_table_insert(ctx->phis, instr, result);
5129 }
5130
5131 static void visit_post_phi(struct ac_nir_context *ctx,
5132 nir_phi_instr *instr,
5133 LLVMValueRef llvm_phi)
5134 {
5135 nir_foreach_phi_src(src, instr) {
5136 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5137 LLVMValueRef llvm_src = get_src(ctx, src->src);
5138
5139 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5140 }
5141 }
5142
5143 static void phi_post_pass(struct ac_nir_context *ctx)
5144 {
5145 struct hash_entry *entry;
5146 hash_table_foreach(ctx->phis, entry) {
5147 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5148 (LLVMValueRef)entry->data);
5149 }
5150 }
5151
5152
5153 static void visit_ssa_undef(struct ac_nir_context *ctx,
5154 const nir_ssa_undef_instr *instr)
5155 {
5156 unsigned num_components = instr->def.num_components;
5157 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5158 LLVMValueRef undef;
5159
5160 if (num_components == 1)
5161 undef = LLVMGetUndef(type);
5162 else {
5163 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5164 }
5165 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5166 }
5167
5168 static void visit_jump(struct ac_nir_context *ctx,
5169 const nir_jump_instr *instr)
5170 {
5171 switch (instr->type) {
5172 case nir_jump_break:
5173 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5174 LLVMClearInsertionPosition(ctx->ac.builder);
5175 break;
5176 case nir_jump_continue:
5177 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5178 LLVMClearInsertionPosition(ctx->ac.builder);
5179 break;
5180 default:
5181 fprintf(stderr, "Unknown NIR jump instr: ");
5182 nir_print_instr(&instr->instr, stderr);
5183 fprintf(stderr, "\n");
5184 abort();
5185 }
5186 }
5187
5188 static void visit_cf_list(struct ac_nir_context *ctx,
5189 struct exec_list *list);
5190
5191 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5192 {
5193 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5194 nir_foreach_instr(instr, block)
5195 {
5196 switch (instr->type) {
5197 case nir_instr_type_alu:
5198 visit_alu(ctx, nir_instr_as_alu(instr));
5199 break;
5200 case nir_instr_type_load_const:
5201 visit_load_const(ctx, nir_instr_as_load_const(instr));
5202 break;
5203 case nir_instr_type_intrinsic:
5204 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5205 break;
5206 case nir_instr_type_tex:
5207 visit_tex(ctx, nir_instr_as_tex(instr));
5208 break;
5209 case nir_instr_type_phi:
5210 visit_phi(ctx, nir_instr_as_phi(instr));
5211 break;
5212 case nir_instr_type_ssa_undef:
5213 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5214 break;
5215 case nir_instr_type_jump:
5216 visit_jump(ctx, nir_instr_as_jump(instr));
5217 break;
5218 default:
5219 fprintf(stderr, "Unknown NIR instr type: ");
5220 nir_print_instr(instr, stderr);
5221 fprintf(stderr, "\n");
5222 abort();
5223 }
5224 }
5225
5226 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5227 }
5228
5229 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5230 {
5231 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5232
5233 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5234 LLVMBasicBlockRef merge_block =
5235 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5236 LLVMBasicBlockRef if_block =
5237 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5238 LLVMBasicBlockRef else_block = merge_block;
5239 if (!exec_list_is_empty(&if_stmt->else_list))
5240 else_block = LLVMAppendBasicBlockInContext(
5241 ctx->ac.context, fn, "");
5242
5243 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5244 ctx->ac.i32_0, "");
5245 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5246
5247 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5248 visit_cf_list(ctx, &if_stmt->then_list);
5249 if (LLVMGetInsertBlock(ctx->ac.builder))
5250 LLVMBuildBr(ctx->ac.builder, merge_block);
5251
5252 if (!exec_list_is_empty(&if_stmt->else_list)) {
5253 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5254 visit_cf_list(ctx, &if_stmt->else_list);
5255 if (LLVMGetInsertBlock(ctx->ac.builder))
5256 LLVMBuildBr(ctx->ac.builder, merge_block);
5257 }
5258
5259 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5260 }
5261
5262 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5263 {
5264 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5265 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5266 LLVMBasicBlockRef break_parent = ctx->break_block;
5267
5268 ctx->continue_block =
5269 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5270 ctx->break_block =
5271 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5272
5273 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5274 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5275 visit_cf_list(ctx, &loop->body);
5276
5277 if (LLVMGetInsertBlock(ctx->ac.builder))
5278 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5279 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5280
5281 ctx->continue_block = continue_parent;
5282 ctx->break_block = break_parent;
5283 }
5284
5285 static void visit_cf_list(struct ac_nir_context *ctx,
5286 struct exec_list *list)
5287 {
5288 foreach_list_typed(nir_cf_node, node, node, list)
5289 {
5290 switch (node->type) {
5291 case nir_cf_node_block:
5292 visit_block(ctx, nir_cf_node_as_block(node));
5293 break;
5294
5295 case nir_cf_node_if:
5296 visit_if(ctx, nir_cf_node_as_if(node));
5297 break;
5298
5299 case nir_cf_node_loop:
5300 visit_loop(ctx, nir_cf_node_as_loop(node));
5301 break;
5302
5303 default:
5304 assert(0);
5305 }
5306 }
5307 }
5308
5309 static void
5310 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5311 struct nir_variable *variable)
5312 {
5313 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5314 LLVMValueRef t_offset;
5315 LLVMValueRef t_list;
5316 LLVMValueRef input;
5317 LLVMValueRef buffer_index;
5318 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5319 int idx = variable->data.location;
5320 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5321 uint8_t input_usage_mask =
5322 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5323 unsigned num_channels = util_last_bit(input_usage_mask);
5324
5325 variable->data.driver_location = idx * 4;
5326
5327 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5328 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5329 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5330 ctx->abi.start_instance, "");
5331 if (ctx->options->key.vs.as_ls) {
5332 ctx->shader_info->vs.vgpr_comp_cnt =
5333 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5334 } else {
5335 ctx->shader_info->vs.vgpr_comp_cnt =
5336 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5337 }
5338 } else
5339 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5340 ctx->abi.base_vertex, "");
5341 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5342
5343 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5344
5345 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5346 buffer_index,
5347 ctx->ac.i32_0,
5348 num_channels, false, true);
5349
5350 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5351
5352 for (unsigned chan = 0; chan < 4; chan++) {
5353 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5354 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5355 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5356 input, llvm_chan, ""));
5357 }
5358 }
5359 }
5360
5361 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5362 unsigned attr,
5363 LLVMValueRef interp_param,
5364 LLVMValueRef prim_mask,
5365 LLVMValueRef result[4])
5366 {
5367 LLVMValueRef attr_number;
5368 unsigned chan;
5369 LLVMValueRef i, j;
5370 bool interp = interp_param != NULL;
5371
5372 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5373
5374 /* fs.constant returns the param from the middle vertex, so it's not
5375 * really useful for flat shading. It's meant to be used for custom
5376 * interpolation (but the intrinsic can't fetch from the other two
5377 * vertices).
5378 *
5379 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5380 * to do the right thing. The only reason we use fs.constant is that
5381 * fs.interp cannot be used on integers, because they can be equal
5382 * to NaN.
5383 */
5384 if (interp) {
5385 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5386 ctx->ac.v2f32, "");
5387
5388 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5389 ctx->ac.i32_0, "");
5390 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5391 ctx->ac.i32_1, "");
5392 }
5393
5394 for (chan = 0; chan < 4; chan++) {
5395 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5396
5397 if (interp) {
5398 result[chan] = ac_build_fs_interp(&ctx->ac,
5399 llvm_chan,
5400 attr_number,
5401 prim_mask, i, j);
5402 } else {
5403 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5404 LLVMConstInt(ctx->ac.i32, 2, false),
5405 llvm_chan,
5406 attr_number,
5407 prim_mask);
5408 }
5409 }
5410 }
5411
5412 static void
5413 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5414 struct nir_variable *variable)
5415 {
5416 int idx = variable->data.location;
5417 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5418 LLVMValueRef interp;
5419
5420 variable->data.driver_location = idx * 4;
5421 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5422
5423 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5424 unsigned interp_type;
5425 if (variable->data.sample) {
5426 interp_type = INTERP_SAMPLE;
5427 ctx->shader_info->info.ps.force_persample = true;
5428 } else if (variable->data.centroid)
5429 interp_type = INTERP_CENTROID;
5430 else
5431 interp_type = INTERP_CENTER;
5432
5433 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5434 } else
5435 interp = NULL;
5436
5437 for (unsigned i = 0; i < attrib_count; ++i)
5438 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5439
5440 }
5441
5442 static void
5443 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5444 struct nir_shader *nir) {
5445 nir_foreach_variable(variable, &nir->inputs)
5446 handle_vs_input_decl(ctx, variable);
5447 }
5448
5449 static void
5450 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5451 struct nir_shader *nir)
5452 {
5453 if (!ctx->options->key.fs.multisample)
5454 return;
5455
5456 bool uses_center = false;
5457 bool uses_centroid = false;
5458 nir_foreach_variable(variable, &nir->inputs) {
5459 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5460 variable->data.sample)
5461 continue;
5462
5463 if (variable->data.centroid)
5464 uses_centroid = true;
5465 else
5466 uses_center = true;
5467 }
5468
5469 if (uses_center && uses_centroid) {
5470 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5471 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5472 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5473 }
5474 }
5475
5476 static void
5477 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5478 struct nir_shader *nir)
5479 {
5480 prepare_interp_optimize(ctx, nir);
5481
5482 nir_foreach_variable(variable, &nir->inputs)
5483 handle_fs_input_decl(ctx, variable);
5484
5485 unsigned index = 0;
5486
5487 if (ctx->shader_info->info.ps.uses_input_attachments ||
5488 ctx->shader_info->info.needs_multiview_view_index)
5489 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5490
5491 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5492 LLVMValueRef interp_param;
5493 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5494
5495 if (!(ctx->input_mask & (1ull << i)))
5496 continue;
5497
5498 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5499 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5500 interp_param = *inputs;
5501 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5502 inputs);
5503
5504 if (!interp_param)
5505 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5506 ++index;
5507 } else if (i == VARYING_SLOT_POS) {
5508 for(int i = 0; i < 3; ++i)
5509 inputs[i] = ctx->abi.frag_pos[i];
5510
5511 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5512 ctx->abi.frag_pos[3]);
5513 }
5514 }
5515 ctx->shader_info->fs.num_interp = index;
5516 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5517 ctx->shader_info->fs.has_pcoord = true;
5518 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5519 ctx->shader_info->fs.prim_id_input = true;
5520 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5521 ctx->shader_info->fs.layer_input = true;
5522 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5523
5524 if (ctx->shader_info->info.needs_multiview_view_index)
5525 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5526 }
5527
5528 static LLVMValueRef
5529 ac_build_alloca(struct ac_llvm_context *ac,
5530 LLVMTypeRef type,
5531 const char *name)
5532 {
5533 LLVMBuilderRef builder = ac->builder;
5534 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5535 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5536 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5537 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5538 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5539 LLVMValueRef res;
5540
5541 if (first_instr) {
5542 LLVMPositionBuilderBefore(first_builder, first_instr);
5543 } else {
5544 LLVMPositionBuilderAtEnd(first_builder, first_block);
5545 }
5546
5547 res = LLVMBuildAlloca(first_builder, type, name);
5548 LLVMBuildStore(builder, LLVMConstNull(type), res);
5549
5550 LLVMDisposeBuilder(first_builder);
5551
5552 return res;
5553 }
5554
5555 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5556 LLVMTypeRef type,
5557 const char *name)
5558 {
5559 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5560 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5561 return ptr;
5562 }
5563
5564 static void
5565 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5566 struct nir_variable *variable,
5567 struct nir_shader *shader,
5568 gl_shader_stage stage)
5569 {
5570 int idx = variable->data.location + variable->data.index;
5571 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5572 uint64_t mask_attribs;
5573
5574 variable->data.driver_location = idx * 4;
5575
5576 /* tess ctrl has it's own load/store paths for outputs */
5577 if (stage == MESA_SHADER_TESS_CTRL)
5578 return;
5579
5580 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5581 if (stage == MESA_SHADER_VERTEX ||
5582 stage == MESA_SHADER_TESS_EVAL ||
5583 stage == MESA_SHADER_GEOMETRY) {
5584 if (idx == VARYING_SLOT_CLIP_DIST0) {
5585 int length = shader->info.clip_distance_array_size +
5586 shader->info.cull_distance_array_size;
5587 if (stage == MESA_SHADER_VERTEX) {
5588 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5589 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5590 }
5591 if (stage == MESA_SHADER_TESS_EVAL) {
5592 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5593 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5594 }
5595
5596 if (length > 4)
5597 attrib_count = 2;
5598 else
5599 attrib_count = 1;
5600 mask_attribs = 1ull << idx;
5601 }
5602 }
5603
5604 ctx->output_mask |= mask_attribs;
5605 }
5606
5607 static void
5608 handle_shader_output_decl(struct ac_nir_context *ctx,
5609 struct nir_shader *nir,
5610 struct nir_variable *variable)
5611 {
5612 unsigned output_loc = variable->data.driver_location / 4;
5613 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5614
5615 /* tess ctrl has it's own load/store paths for outputs */
5616 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5617 return;
5618
5619 if (ctx->stage == MESA_SHADER_VERTEX ||
5620 ctx->stage == MESA_SHADER_TESS_EVAL ||
5621 ctx->stage == MESA_SHADER_GEOMETRY) {
5622 int idx = variable->data.location + variable->data.index;
5623 if (idx == VARYING_SLOT_CLIP_DIST0) {
5624 int length = nir->info.clip_distance_array_size +
5625 nir->info.cull_distance_array_size;
5626
5627 if (length > 4)
5628 attrib_count = 2;
5629 else
5630 attrib_count = 1;
5631 }
5632 }
5633
5634 for (unsigned i = 0; i < attrib_count; ++i) {
5635 for (unsigned chan = 0; chan < 4; chan++) {
5636 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5637 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5638 }
5639 }
5640 }
5641
5642 static LLVMTypeRef
5643 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5644 enum glsl_base_type type)
5645 {
5646 switch (type) {
5647 case GLSL_TYPE_INT:
5648 case GLSL_TYPE_UINT:
5649 case GLSL_TYPE_BOOL:
5650 case GLSL_TYPE_SUBROUTINE:
5651 return ac->i32;
5652 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5653 return ac->f32;
5654 case GLSL_TYPE_INT64:
5655 case GLSL_TYPE_UINT64:
5656 return ac->i64;
5657 case GLSL_TYPE_DOUBLE:
5658 return ac->f64;
5659 default:
5660 unreachable("unknown GLSL type");
5661 }
5662 }
5663
5664 static LLVMTypeRef
5665 glsl_to_llvm_type(struct ac_llvm_context *ac,
5666 const struct glsl_type *type)
5667 {
5668 if (glsl_type_is_scalar(type)) {
5669 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5670 }
5671
5672 if (glsl_type_is_vector(type)) {
5673 return LLVMVectorType(
5674 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5675 glsl_get_vector_elements(type));
5676 }
5677
5678 if (glsl_type_is_matrix(type)) {
5679 return LLVMArrayType(
5680 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5681 glsl_get_matrix_columns(type));
5682 }
5683
5684 if (glsl_type_is_array(type)) {
5685 return LLVMArrayType(
5686 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5687 glsl_get_length(type));
5688 }
5689
5690 assert(glsl_type_is_struct(type));
5691
5692 LLVMTypeRef member_types[glsl_get_length(type)];
5693
5694 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5695 member_types[i] =
5696 glsl_to_llvm_type(ac,
5697 glsl_get_struct_field(type, i));
5698 }
5699
5700 return LLVMStructTypeInContext(ac->context, member_types,
5701 glsl_get_length(type), false);
5702 }
5703
5704 static void
5705 setup_locals(struct ac_nir_context *ctx,
5706 struct nir_function *func)
5707 {
5708 int i, j;
5709 ctx->num_locals = 0;
5710 nir_foreach_variable(variable, &func->impl->locals) {
5711 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5712 variable->data.driver_location = ctx->num_locals * 4;
5713 variable->data.location_frac = 0;
5714 ctx->num_locals += attrib_count;
5715 }
5716 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5717 if (!ctx->locals)
5718 return;
5719
5720 for (i = 0; i < ctx->num_locals; i++) {
5721 for (j = 0; j < 4; j++) {
5722 ctx->locals[i * 4 + j] =
5723 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5724 }
5725 }
5726 }
5727
5728 static void
5729 setup_shared(struct ac_nir_context *ctx,
5730 struct nir_shader *nir)
5731 {
5732 nir_foreach_variable(variable, &nir->shared) {
5733 LLVMValueRef shared =
5734 LLVMAddGlobalInAddressSpace(
5735 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5736 variable->name ? variable->name : "",
5737 AC_LOCAL_ADDR_SPACE);
5738 _mesa_hash_table_insert(ctx->vars, variable, shared);
5739 }
5740 }
5741
5742 /* Initialize arguments for the shader export intrinsic */
5743 static void
5744 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5745 LLVMValueRef *values,
5746 unsigned target,
5747 struct ac_export_args *args)
5748 {
5749 /* Default is 0xf. Adjusted below depending on the format. */
5750 args->enabled_channels = 0xf;
5751
5752 /* Specify whether the EXEC mask represents the valid mask */
5753 args->valid_mask = 0;
5754
5755 /* Specify whether this is the last export */
5756 args->done = 0;
5757
5758 /* Specify the target we are exporting */
5759 args->target = target;
5760
5761 args->compr = false;
5762 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5763 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5764 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5765 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5766
5767 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5768 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5769 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5770 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5771 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5772 unsigned chan;
5773
5774 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5775 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5776 unsigned bits, bool hi) = NULL;
5777
5778 switch(col_format) {
5779 case V_028714_SPI_SHADER_ZERO:
5780 args->enabled_channels = 0; /* writemask */
5781 args->target = V_008DFC_SQ_EXP_NULL;
5782 break;
5783
5784 case V_028714_SPI_SHADER_32_R:
5785 args->enabled_channels = 1;
5786 args->out[0] = values[0];
5787 break;
5788
5789 case V_028714_SPI_SHADER_32_GR:
5790 args->enabled_channels = 0x3;
5791 args->out[0] = values[0];
5792 args->out[1] = values[1];
5793 break;
5794
5795 case V_028714_SPI_SHADER_32_AR:
5796 args->enabled_channels = 0x9;
5797 args->out[0] = values[0];
5798 args->out[3] = values[3];
5799 break;
5800
5801 case V_028714_SPI_SHADER_FP16_ABGR:
5802 packf = ac_build_cvt_pkrtz_f16;
5803 break;
5804
5805 case V_028714_SPI_SHADER_UNORM16_ABGR:
5806 packf = ac_build_cvt_pknorm_u16;
5807 break;
5808
5809 case V_028714_SPI_SHADER_SNORM16_ABGR:
5810 packf = ac_build_cvt_pknorm_i16;
5811 break;
5812
5813 case V_028714_SPI_SHADER_UINT16_ABGR:
5814 packi = ac_build_cvt_pk_u16;
5815 break;
5816
5817 case V_028714_SPI_SHADER_SINT16_ABGR:
5818 packi = ac_build_cvt_pk_i16;
5819 break;
5820
5821 default:
5822 case V_028714_SPI_SHADER_32_ABGR:
5823 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5824 break;
5825 }
5826
5827 /* Pack f16 or norm_i16/u16. */
5828 if (packf) {
5829 for (chan = 0; chan < 2; chan++) {
5830 LLVMValueRef pack_args[2] = {
5831 values[2 * chan],
5832 values[2 * chan + 1]
5833 };
5834 LLVMValueRef packed;
5835
5836 packed = packf(&ctx->ac, pack_args);
5837 args->out[chan] = ac_to_float(&ctx->ac, packed);
5838 }
5839 args->compr = 1; /* COMPR flag */
5840 }
5841
5842 /* Pack i16/u16. */
5843 if (packi) {
5844 for (chan = 0; chan < 2; chan++) {
5845 LLVMValueRef pack_args[2] = {
5846 ac_to_integer(&ctx->ac, values[2 * chan]),
5847 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5848 };
5849 LLVMValueRef packed;
5850
5851 packed = packi(&ctx->ac, pack_args,
5852 is_int8 ? 8 : is_int10 ? 10 : 16,
5853 chan == 1);
5854 args->out[chan] = ac_to_float(&ctx->ac, packed);
5855 }
5856 args->compr = 1; /* COMPR flag */
5857 }
5858 return;
5859 }
5860
5861 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5862
5863 for (unsigned i = 0; i < 4; ++i)
5864 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5865 }
5866
5867 static void
5868 radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
5869 LLVMValueRef *values)
5870 {
5871 struct ac_export_args args;
5872
5873 si_llvm_init_export_args(ctx, values,
5874 V_008DFC_SQ_EXP_PARAM + index, &args);
5875 ac_build_export(&ctx->ac, &args);
5876 }
5877
5878 static LLVMValueRef
5879 radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
5880 {
5881 LLVMValueRef output =
5882 ctx->nir->outputs[radeon_llvm_reg_index_soa(index, chan)];
5883
5884 return LLVMBuildLoad(ctx->ac.builder, output, "");
5885 }
5886
5887 static void
5888 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5889 bool export_prim_id,
5890 struct ac_vs_output_info *outinfo)
5891 {
5892 uint32_t param_count = 0;
5893 unsigned target;
5894 unsigned pos_idx, num_pos_exports = 0;
5895 struct ac_export_args args, pos_args[4] = {};
5896 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5897 int i;
5898
5899 if (ctx->options->key.has_multiview_view_index) {
5900 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5901 if(!*tmp_out) {
5902 for(unsigned i = 0; i < 4; ++i)
5903 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5904 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5905 }
5906
5907 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5908 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5909 }
5910
5911 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5912 sizeof(outinfo->vs_output_param_offset));
5913
5914 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5915 LLVMValueRef slots[8];
5916 unsigned j;
5917
5918 if (outinfo->cull_dist_mask)
5919 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5920
5921 i = VARYING_SLOT_CLIP_DIST0;
5922 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5923 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5924
5925 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5926 slots[i] = LLVMGetUndef(ctx->ac.f32);
5927
5928 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5929 target = V_008DFC_SQ_EXP_POS + 3;
5930 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5931 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5932 &args, sizeof(args));
5933 }
5934
5935 target = V_008DFC_SQ_EXP_POS + 2;
5936 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5937 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5938 &args, sizeof(args));
5939
5940 }
5941
5942 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5943 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5944 for (unsigned j = 0; j < 4; j++)
5945 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5946 }
5947 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5948
5949 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5950 outinfo->writes_pointsize = true;
5951 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5952 }
5953
5954 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5955 outinfo->writes_layer = true;
5956 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5957 }
5958
5959 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5960 outinfo->writes_viewport_index = true;
5961 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
5962 }
5963
5964 if (outinfo->writes_pointsize ||
5965 outinfo->writes_layer ||
5966 outinfo->writes_viewport_index) {
5967 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5968 (outinfo->writes_layer == true ? 4 : 0));
5969 pos_args[1].valid_mask = 0;
5970 pos_args[1].done = 0;
5971 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5972 pos_args[1].compr = 0;
5973 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5974 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5975 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5976 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5977
5978 if (outinfo->writes_pointsize == true)
5979 pos_args[1].out[0] = psize_value;
5980 if (outinfo->writes_layer == true)
5981 pos_args[1].out[2] = layer_value;
5982 if (outinfo->writes_viewport_index == true) {
5983 if (ctx->options->chip_class >= GFX9) {
5984 /* GFX9 has the layer in out.z[10:0] and the viewport
5985 * index in out.z[19:16].
5986 */
5987 LLVMValueRef v = viewport_index_value;
5988 v = ac_to_integer(&ctx->ac, v);
5989 v = LLVMBuildShl(ctx->ac.builder, v,
5990 LLVMConstInt(ctx->ac.i32, 16, false),
5991 "");
5992 v = LLVMBuildOr(ctx->ac.builder, v,
5993 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5994
5995 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5996 pos_args[1].enabled_channels |= 1 << 2;
5997 } else {
5998 pos_args[1].out[3] = viewport_index_value;
5999 pos_args[1].enabled_channels |= 1 << 3;
6000 }
6001 }
6002 }
6003 for (i = 0; i < 4; i++) {
6004 if (pos_args[i].out[0])
6005 num_pos_exports++;
6006 }
6007
6008 pos_idx = 0;
6009 for (i = 0; i < 4; i++) {
6010 if (!pos_args[i].out[0])
6011 continue;
6012
6013 /* Specify the target we are exporting */
6014 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6015 if (pos_idx == num_pos_exports)
6016 pos_args[i].done = 1;
6017 ac_build_export(&ctx->ac, &pos_args[i]);
6018 }
6019
6020 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6021 LLVMValueRef values[4];
6022 if (!(ctx->output_mask & (1ull << i)))
6023 continue;
6024
6025 if (i != VARYING_SLOT_LAYER &&
6026 i != VARYING_SLOT_PRIMITIVE_ID &&
6027 i < VARYING_SLOT_VAR0)
6028 continue;
6029
6030 for (unsigned j = 0; j < 4; j++)
6031 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6032
6033 radv_export_param(ctx, param_count, values);
6034
6035 outinfo->vs_output_param_offset[i] = param_count++;
6036 }
6037
6038 if (export_prim_id) {
6039 LLVMValueRef values[4];
6040
6041 values[0] = ctx->vs_prim_id;
6042 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6043 ctx->shader_info->vs.vgpr_comp_cnt);
6044 for (unsigned j = 1; j < 4; j++)
6045 values[j] = ctx->ac.f32_0;
6046
6047 radv_export_param(ctx, param_count, values);
6048
6049 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6050 outinfo->export_prim_id = true;
6051 }
6052
6053 outinfo->pos_exports = num_pos_exports;
6054 outinfo->param_exports = param_count;
6055 }
6056
6057 static void
6058 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6059 struct ac_es_output_info *outinfo)
6060 {
6061 int j;
6062 uint64_t max_output_written = 0;
6063 LLVMValueRef lds_base = NULL;
6064
6065 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6066 int param_index;
6067 int length = 4;
6068
6069 if (!(ctx->output_mask & (1ull << i)))
6070 continue;
6071
6072 if (i == VARYING_SLOT_CLIP_DIST0)
6073 length = ctx->num_output_clips + ctx->num_output_culls;
6074
6075 param_index = shader_io_get_unique_index(i);
6076
6077 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6078 }
6079
6080 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6081
6082 if (ctx->ac.chip_class >= GFX9) {
6083 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6084 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6085 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6086 LLVMConstInt(ctx->ac.i32, 24, false),
6087 LLVMConstInt(ctx->ac.i32, 4, false), false);
6088 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6089 LLVMBuildMul(ctx->ac.builder, wave_idx,
6090 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6091 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6092 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6093 }
6094
6095 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6096 LLVMValueRef dw_addr;
6097 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6098 int param_index;
6099 int length = 4;
6100
6101 if (!(ctx->output_mask & (1ull << i)))
6102 continue;
6103
6104 if (i == VARYING_SLOT_CLIP_DIST0)
6105 length = ctx->num_output_clips + ctx->num_output_culls;
6106
6107 param_index = shader_io_get_unique_index(i);
6108
6109 if (lds_base) {
6110 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6111 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6112 "");
6113 }
6114 for (j = 0; j < length; j++) {
6115 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6116 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6117
6118 if (ctx->ac.chip_class >= GFX9) {
6119 ac_lds_store(&ctx->ac, dw_addr,
6120 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6121 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6122 } else {
6123 ac_build_buffer_store_dword(&ctx->ac,
6124 ctx->esgs_ring,
6125 out_val, 1,
6126 NULL, ctx->es2gs_offset,
6127 (4 * param_index + j) * 4,
6128 1, 1, true, true);
6129 }
6130 }
6131 }
6132 }
6133
6134 static void
6135 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6136 {
6137 LLVMValueRef vertex_id = ctx->rel_auto_id;
6138 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6139 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6140 vertex_dw_stride, "");
6141
6142 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6143 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6144 int length = 4;
6145
6146 if (!(ctx->output_mask & (1ull << i)))
6147 continue;
6148
6149 if (i == VARYING_SLOT_CLIP_DIST0)
6150 length = ctx->num_output_clips + ctx->num_output_culls;
6151 int param = shader_io_get_unique_index(i);
6152 mark_tess_output(ctx, false, param);
6153 if (length > 4)
6154 mark_tess_output(ctx, false, param + 1);
6155 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6156 LLVMConstInt(ctx->ac.i32, param * 4, false),
6157 "");
6158 for (unsigned j = 0; j < length; j++) {
6159 ac_lds_store(&ctx->ac, dw_addr,
6160 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6161 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6162 }
6163 }
6164 }
6165
6166 struct ac_build_if_state
6167 {
6168 struct nir_to_llvm_context *ctx;
6169 LLVMValueRef condition;
6170 LLVMBasicBlockRef entry_block;
6171 LLVMBasicBlockRef true_block;
6172 LLVMBasicBlockRef false_block;
6173 LLVMBasicBlockRef merge_block;
6174 };
6175
6176 static LLVMBasicBlockRef
6177 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6178 {
6179 LLVMBasicBlockRef current_block;
6180 LLVMBasicBlockRef next_block;
6181 LLVMBasicBlockRef new_block;
6182
6183 /* get current basic block */
6184 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6185
6186 /* chqeck if there's another block after this one */
6187 next_block = LLVMGetNextBasicBlock(current_block);
6188 if (next_block) {
6189 /* insert the new block before the next block */
6190 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6191 }
6192 else {
6193 /* append new block after current block */
6194 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6195 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6196 }
6197 return new_block;
6198 }
6199
6200 static void
6201 ac_nir_build_if(struct ac_build_if_state *ifthen,
6202 struct nir_to_llvm_context *ctx,
6203 LLVMValueRef condition)
6204 {
6205 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6206
6207 memset(ifthen, 0, sizeof *ifthen);
6208 ifthen->ctx = ctx;
6209 ifthen->condition = condition;
6210 ifthen->entry_block = block;
6211
6212 /* create endif/merge basic block for the phi functions */
6213 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6214
6215 /* create/insert true_block before merge_block */
6216 ifthen->true_block =
6217 LLVMInsertBasicBlockInContext(ctx->context,
6218 ifthen->merge_block,
6219 "if-true-block");
6220
6221 /* successive code goes into the true block */
6222 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6223 }
6224
6225 /**
6226 * End a conditional.
6227 */
6228 static void
6229 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6230 {
6231 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6232
6233 /* Insert branch to the merge block from current block */
6234 LLVMBuildBr(builder, ifthen->merge_block);
6235
6236 /*
6237 * Now patch in the various branch instructions.
6238 */
6239
6240 /* Insert the conditional branch instruction at the end of entry_block */
6241 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6242 if (ifthen->false_block) {
6243 /* we have an else clause */
6244 LLVMBuildCondBr(builder, ifthen->condition,
6245 ifthen->true_block, ifthen->false_block);
6246 }
6247 else {
6248 /* no else clause */
6249 LLVMBuildCondBr(builder, ifthen->condition,
6250 ifthen->true_block, ifthen->merge_block);
6251 }
6252
6253 /* Resume building code at end of the ifthen->merge_block */
6254 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6255 }
6256
6257 static void
6258 write_tess_factors(struct nir_to_llvm_context *ctx)
6259 {
6260 unsigned stride, outer_comps, inner_comps;
6261 struct ac_build_if_state if_ctx, inner_if_ctx;
6262 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6263 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6264 unsigned tess_inner_index, tess_outer_index;
6265 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6266 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6267 int i;
6268 emit_barrier(&ctx->ac, ctx->stage);
6269
6270 switch (ctx->options->key.tcs.primitive_mode) {
6271 case GL_ISOLINES:
6272 stride = 2;
6273 outer_comps = 2;
6274 inner_comps = 0;
6275 break;
6276 case GL_TRIANGLES:
6277 stride = 4;
6278 outer_comps = 3;
6279 inner_comps = 1;
6280 break;
6281 case GL_QUADS:
6282 stride = 6;
6283 outer_comps = 4;
6284 inner_comps = 2;
6285 break;
6286 default:
6287 return;
6288 }
6289
6290 ac_nir_build_if(&if_ctx, ctx,
6291 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6292 invocation_id, ctx->ac.i32_0, ""));
6293
6294 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6295 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6296
6297 mark_tess_output(ctx, true, tess_inner_index);
6298 mark_tess_output(ctx, true, tess_outer_index);
6299 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6300 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6301 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6302 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6303 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6304
6305 for (i = 0; i < 4; i++) {
6306 inner[i] = LLVMGetUndef(ctx->ac.i32);
6307 outer[i] = LLVMGetUndef(ctx->ac.i32);
6308 }
6309
6310 // LINES reverseal
6311 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6312 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6313 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6314 ctx->ac.i32_1, "");
6315 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6316 } else {
6317 for (i = 0; i < outer_comps; i++) {
6318 outer[i] = out[i] =
6319 ac_lds_load(&ctx->ac, lds_outer);
6320 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6321 ctx->ac.i32_1, "");
6322 }
6323 for (i = 0; i < inner_comps; i++) {
6324 inner[i] = out[outer_comps+i] =
6325 ac_lds_load(&ctx->ac, lds_inner);
6326 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6327 ctx->ac.i32_1, "");
6328 }
6329 }
6330
6331 /* Convert the outputs to vectors for stores. */
6332 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6333 vec1 = NULL;
6334
6335 if (stride > 4)
6336 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6337
6338
6339 buffer = ctx->hs_ring_tess_factor;
6340 tf_base = ctx->tess_factor_offset;
6341 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6342 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6343 unsigned tf_offset = 0;
6344
6345 if (ctx->options->chip_class <= VI) {
6346 ac_nir_build_if(&inner_if_ctx, ctx,
6347 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6348 rel_patch_id, ctx->ac.i32_0, ""));
6349
6350 /* Store the dynamic HS control word. */
6351 ac_build_buffer_store_dword(&ctx->ac, buffer,
6352 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6353 1, ctx->ac.i32_0, tf_base,
6354 0, 1, 0, true, false);
6355 tf_offset += 4;
6356
6357 ac_nir_build_endif(&inner_if_ctx);
6358 }
6359
6360 /* Store the tessellation factors. */
6361 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6362 MIN2(stride, 4), byteoffset, tf_base,
6363 tf_offset, 1, 0, true, false);
6364 if (vec1)
6365 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6366 stride - 4, byteoffset, tf_base,
6367 16 + tf_offset, 1, 0, true, false);
6368
6369 //store to offchip for TES to read - only if TES reads them
6370 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6371 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6372 LLVMValueRef tf_inner_offset;
6373 unsigned param_outer, param_inner;
6374
6375 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6376 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6377 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6378
6379 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6380 util_next_power_of_two(outer_comps));
6381
6382 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6383 outer_comps, tf_outer_offset,
6384 ctx->oc_lds, 0, 1, 0, true, false);
6385 if (inner_comps) {
6386 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6387 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6388 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6389
6390 inner_vec = inner_comps == 1 ? inner[0] :
6391 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6392 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6393 inner_comps, tf_inner_offset,
6394 ctx->oc_lds, 0, 1, 0, true, false);
6395 }
6396 }
6397 ac_nir_build_endif(&if_ctx);
6398 }
6399
6400 static void
6401 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6402 {
6403 write_tess_factors(ctx);
6404 }
6405
6406 static bool
6407 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6408 LLVMValueRef *color, unsigned index, bool is_last,
6409 struct ac_export_args *args)
6410 {
6411 /* Export */
6412 si_llvm_init_export_args(ctx, color,
6413 V_008DFC_SQ_EXP_MRT + index, args);
6414
6415 if (is_last) {
6416 args->valid_mask = 1; /* whether the EXEC mask is valid */
6417 args->done = 1; /* DONE bit */
6418 } else if (!args->enabled_channels)
6419 return false; /* unnecessary NULL export */
6420
6421 return true;
6422 }
6423
6424 static void
6425 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6426 LLVMValueRef depth, LLVMValueRef stencil,
6427 LLVMValueRef samplemask)
6428 {
6429 struct ac_export_args args;
6430
6431 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6432
6433 ac_build_export(&ctx->ac, &args);
6434 }
6435
6436 static void
6437 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6438 {
6439 unsigned index = 0;
6440 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6441 struct ac_export_args color_args[8];
6442
6443 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6444 LLVMValueRef values[4];
6445 bool last = false;
6446
6447 if (!(ctx->output_mask & (1ull << i)))
6448 continue;
6449
6450 if (i < FRAG_RESULT_DATA0)
6451 continue;
6452
6453 for (unsigned j = 0; j < 4; j++)
6454 values[j] = ac_to_float(&ctx->ac,
6455 radv_load_output(ctx, i, j));
6456
6457 if (!ctx->shader_info->info.ps.writes_z &&
6458 !ctx->shader_info->info.ps.writes_stencil &&
6459 !ctx->shader_info->info.ps.writes_sample_mask)
6460 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6461
6462 bool ret = si_export_mrt_color(ctx, values,
6463 i - FRAG_RESULT_DATA0,
6464 last, &color_args[index]);
6465 if (ret)
6466 index++;
6467 }
6468
6469 /* Process depth, stencil, samplemask. */
6470 if (ctx->shader_info->info.ps.writes_z) {
6471 depth = ac_to_float(&ctx->ac,
6472 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6473 }
6474 if (ctx->shader_info->info.ps.writes_stencil) {
6475 stencil = ac_to_float(&ctx->ac,
6476 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6477 }
6478 if (ctx->shader_info->info.ps.writes_sample_mask) {
6479 samplemask = ac_to_float(&ctx->ac,
6480 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6481 }
6482
6483 /* Export PS outputs. */
6484 for (unsigned i = 0; i < index; i++)
6485 ac_build_export(&ctx->ac, &color_args[i]);
6486
6487 if (depth || stencil || samplemask)
6488 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6489 else if (!index)
6490 ac_build_export_null(&ctx->ac);
6491 }
6492
6493 static void
6494 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6495 {
6496 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6497 }
6498
6499 static void
6500 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6501 LLVMValueRef *addrs)
6502 {
6503 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6504
6505 switch (ctx->stage) {
6506 case MESA_SHADER_VERTEX:
6507 if (ctx->options->key.vs.as_ls)
6508 handle_ls_outputs_post(ctx);
6509 else if (ctx->options->key.vs.as_es)
6510 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6511 else
6512 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6513 &ctx->shader_info->vs.outinfo);
6514 break;
6515 case MESA_SHADER_FRAGMENT:
6516 handle_fs_outputs_post(ctx);
6517 break;
6518 case MESA_SHADER_GEOMETRY:
6519 emit_gs_epilogue(ctx);
6520 break;
6521 case MESA_SHADER_TESS_CTRL:
6522 handle_tcs_outputs_post(ctx);
6523 break;
6524 case MESA_SHADER_TESS_EVAL:
6525 if (ctx->options->key.tes.as_es)
6526 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6527 else
6528 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6529 &ctx->shader_info->tes.outinfo);
6530 break;
6531 default:
6532 break;
6533 }
6534 }
6535
6536 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6537 {
6538 LLVMPassManagerRef passmgr;
6539 /* Create the pass manager */
6540 passmgr = LLVMCreateFunctionPassManagerForModule(
6541 ctx->module);
6542
6543 /* This pass should eliminate all the load and store instructions */
6544 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6545
6546 /* Add some optimization passes */
6547 LLVMAddScalarReplAggregatesPass(passmgr);
6548 LLVMAddLICMPass(passmgr);
6549 LLVMAddAggressiveDCEPass(passmgr);
6550 LLVMAddCFGSimplificationPass(passmgr);
6551 LLVMAddInstructionCombiningPass(passmgr);
6552
6553 /* Run the pass */
6554 LLVMInitializeFunctionPassManager(passmgr);
6555 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6556 LLVMFinalizeFunctionPassManager(passmgr);
6557
6558 LLVMDisposeBuilder(ctx->ac.builder);
6559 LLVMDisposePassManager(passmgr);
6560 }
6561
6562 static void
6563 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6564 {
6565 struct ac_vs_output_info *outinfo;
6566
6567 switch (ctx->stage) {
6568 case MESA_SHADER_FRAGMENT:
6569 case MESA_SHADER_COMPUTE:
6570 case MESA_SHADER_TESS_CTRL:
6571 case MESA_SHADER_GEOMETRY:
6572 return;
6573 case MESA_SHADER_VERTEX:
6574 if (ctx->options->key.vs.as_ls ||
6575 ctx->options->key.vs.as_es)
6576 return;
6577 outinfo = &ctx->shader_info->vs.outinfo;
6578 break;
6579 case MESA_SHADER_TESS_EVAL:
6580 if (ctx->options->key.vs.as_es)
6581 return;
6582 outinfo = &ctx->shader_info->tes.outinfo;
6583 break;
6584 default:
6585 unreachable("Unhandled shader type");
6586 }
6587
6588 ac_optimize_vs_outputs(&ctx->ac,
6589 ctx->main_function,
6590 outinfo->vs_output_param_offset,
6591 VARYING_SLOT_MAX,
6592 &outinfo->param_exports);
6593 }
6594
6595 static void
6596 ac_setup_rings(struct nir_to_llvm_context *ctx)
6597 {
6598 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6599 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6600 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6601 }
6602
6603 if (ctx->is_gs_copy_shader) {
6604 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6605 }
6606 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6607 LLVMValueRef tmp;
6608 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6609 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6610
6611 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6612
6613 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6614 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6615 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6616 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6617 }
6618
6619 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6620 ctx->stage == MESA_SHADER_TESS_EVAL) {
6621 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6622 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6623 }
6624 }
6625
6626 static unsigned
6627 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6628 const struct nir_shader *nir)
6629 {
6630 switch (nir->info.stage) {
6631 case MESA_SHADER_TESS_CTRL:
6632 return chip_class >= CIK ? 128 : 64;
6633 case MESA_SHADER_GEOMETRY:
6634 return chip_class >= GFX9 ? 128 : 64;
6635 case MESA_SHADER_COMPUTE:
6636 break;
6637 default:
6638 return 0;
6639 }
6640
6641 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6642 nir->info.cs.local_size[1] *
6643 nir->info.cs.local_size[2];
6644 return max_workgroup_size;
6645 }
6646
6647 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6648 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6649 {
6650 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6651 LLVMConstInt(ctx->ac.i32, 8, false),
6652 LLVMConstInt(ctx->ac.i32, 8, false), false);
6653 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6654 ctx->ac.i32_0, "");
6655 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6656 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6657 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6658 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6659 }
6660
6661 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6662 {
6663 for(int i = 5; i >= 0; --i) {
6664 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6665 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6666 LLVMConstInt(ctx->ac.i32, 16, false), false);
6667 }
6668
6669 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6670 LLVMConstInt(ctx->ac.i32, 16, false),
6671 LLVMConstInt(ctx->ac.i32, 8, false), false);
6672 }
6673
6674 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6675 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6676 {
6677 struct ac_nir_context ctx = {};
6678 struct nir_function *func;
6679
6680 ctx.ac = *ac;
6681 ctx.abi = abi;
6682
6683 ctx.nctx = nctx;
6684 if (nctx)
6685 nctx->nir = &ctx;
6686
6687 ctx.stage = nir->info.stage;
6688
6689 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6690
6691 nir_foreach_variable(variable, &nir->outputs)
6692 handle_shader_output_decl(&ctx, nir, variable);
6693
6694 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6695 _mesa_key_pointer_equal);
6696 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6697 _mesa_key_pointer_equal);
6698 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6699 _mesa_key_pointer_equal);
6700
6701 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6702
6703 setup_locals(&ctx, func);
6704
6705 if (nir->info.stage == MESA_SHADER_COMPUTE)
6706 setup_shared(&ctx, nir);
6707
6708 visit_cf_list(&ctx, &func->impl->body);
6709 phi_post_pass(&ctx);
6710
6711 if (nir->info.stage != MESA_SHADER_COMPUTE)
6712 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6713 ctx.outputs);
6714
6715 free(ctx.locals);
6716 ralloc_free(ctx.defs);
6717 ralloc_free(ctx.phis);
6718 ralloc_free(ctx.vars);
6719
6720 if (nctx)
6721 nctx->nir = NULL;
6722 }
6723
6724 static
6725 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6726 struct nir_shader *const *shaders,
6727 int shader_count,
6728 struct ac_shader_variant_info *shader_info,
6729 const struct ac_nir_compiler_options *options)
6730 {
6731 struct nir_to_llvm_context ctx = {0};
6732 unsigned i;
6733 ctx.options = options;
6734 ctx.shader_info = shader_info;
6735 ctx.context = LLVMContextCreate();
6736 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6737
6738 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6739 options->family);
6740 ctx.ac.module = ctx.module;
6741 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6742
6743 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6744 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6745 LLVMSetDataLayout(ctx.module, data_layout_str);
6746 LLVMDisposeTargetData(data_layout);
6747 LLVMDisposeMessage(data_layout_str);
6748
6749 enum ac_float_mode float_mode =
6750 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6751 AC_FLOAT_MODE_DEFAULT;
6752
6753 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6754
6755 memset(shader_info, 0, sizeof(*shader_info));
6756
6757 for(int i = 0; i < shader_count; ++i)
6758 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6759
6760 for (i = 0; i < AC_UD_MAX_SETS; i++)
6761 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6762 for (i = 0; i < AC_UD_MAX_UD; i++)
6763 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6764
6765 ctx.max_workgroup_size = 0;
6766 for (int i = 0; i < shader_count; ++i) {
6767 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6768 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6769 shaders[i]));
6770 }
6771
6772 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6773 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6774
6775 ctx.abi.inputs = &ctx.inputs[0];
6776 ctx.abi.emit_outputs = handle_shader_outputs_post;
6777 ctx.abi.emit_vertex = visit_emit_vertex;
6778 ctx.abi.load_ubo = radv_load_ubo;
6779 ctx.abi.load_ssbo = radv_load_ssbo;
6780 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6781 ctx.abi.load_resource = radv_load_resource;
6782 ctx.abi.clamp_shadow_reference = false;
6783
6784 if (shader_count >= 2)
6785 ac_init_exec_full_mask(&ctx.ac);
6786
6787 if (ctx.ac.chip_class == GFX9 &&
6788 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6789 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6790
6791 for(int i = 0; i < shader_count; ++i) {
6792 ctx.stage = shaders[i]->info.stage;
6793 ctx.output_mask = 0;
6794 ctx.tess_outputs_written = 0;
6795 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6796 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6797
6798 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6799 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6800 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6801 ctx.abi.load_inputs = load_gs_input;
6802 ctx.abi.emit_primitive = visit_end_primitive;
6803 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6804 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6805 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6806 ctx.abi.load_tess_varyings = load_tcs_varyings;
6807 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6808 ctx.abi.store_tcs_outputs = store_tcs_output;
6809 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6810 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6811 ctx.abi.load_tess_varyings = load_tes_input;
6812 ctx.abi.load_tess_coord = load_tess_coord;
6813 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6814 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6815 if (shader_info->info.vs.needs_instance_id) {
6816 if (ctx.options->key.vs.as_ls) {
6817 ctx.shader_info->vs.vgpr_comp_cnt =
6818 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6819 } else {
6820 ctx.shader_info->vs.vgpr_comp_cnt =
6821 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6822 }
6823 }
6824 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6825 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6826 ctx.abi.lookup_interp_param = lookup_interp_param;
6827 ctx.abi.load_sample_position = load_sample_position;
6828 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6829 }
6830
6831 if (i)
6832 emit_barrier(&ctx.ac, ctx.stage);
6833
6834 ac_setup_rings(&ctx);
6835
6836 LLVMBasicBlockRef merge_block;
6837 if (shader_count >= 2) {
6838 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6839 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6840 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6841
6842 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6843 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6844 LLVMConstInt(ctx.ac.i32, 8, false), false);
6845 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6846 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6847 thread_id, count, "");
6848 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6849
6850 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6851 }
6852
6853 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6854 handle_fs_inputs(&ctx, shaders[i]);
6855 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6856 handle_vs_inputs(&ctx, shaders[i]);
6857 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6858 prepare_gs_input_vgprs(&ctx);
6859
6860 nir_foreach_variable(variable, &shaders[i]->outputs)
6861 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6862
6863 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6864
6865 if (shader_count >= 2) {
6866 LLVMBuildBr(ctx.ac.builder, merge_block);
6867 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6868 }
6869
6870 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6871 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6872 shaders[i]->info.cull_distance_array_size > 4;
6873 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6874 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6875 shaders[i]->info.gs.vertices_out;
6876 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6877 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6878 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6879 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6880 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6881 }
6882 }
6883
6884 LLVMBuildRetVoid(ctx.ac.builder);
6885
6886 if (options->dump_preoptir)
6887 ac_dump_module(ctx.module);
6888
6889 ac_llvm_finalize_module(&ctx);
6890
6891 if (shader_count == 1)
6892 ac_nir_eliminate_const_vs_outputs(&ctx);
6893
6894 return ctx.module;
6895 }
6896
6897 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6898 {
6899 unsigned *retval = (unsigned *)context;
6900 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6901 char *description = LLVMGetDiagInfoDescription(di);
6902
6903 if (severity == LLVMDSError) {
6904 *retval = 1;
6905 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6906 description);
6907 }
6908
6909 LLVMDisposeMessage(description);
6910 }
6911
6912 static unsigned ac_llvm_compile(LLVMModuleRef M,
6913 struct ac_shader_binary *binary,
6914 LLVMTargetMachineRef tm)
6915 {
6916 unsigned retval = 0;
6917 char *err;
6918 LLVMContextRef llvm_ctx;
6919 LLVMMemoryBufferRef out_buffer;
6920 unsigned buffer_size;
6921 const char *buffer_data;
6922 LLVMBool mem_err;
6923
6924 /* Setup Diagnostic Handler*/
6925 llvm_ctx = LLVMGetModuleContext(M);
6926
6927 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6928 &retval);
6929
6930 /* Compile IR*/
6931 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6932 &err, &out_buffer);
6933
6934 /* Process Errors/Warnings */
6935 if (mem_err) {
6936 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6937 free(err);
6938 retval = 1;
6939 goto out;
6940 }
6941
6942 /* Extract Shader Code*/
6943 buffer_size = LLVMGetBufferSize(out_buffer);
6944 buffer_data = LLVMGetBufferStart(out_buffer);
6945
6946 ac_elf_read(buffer_data, buffer_size, binary);
6947
6948 /* Clean up */
6949 LLVMDisposeMemoryBuffer(out_buffer);
6950
6951 out:
6952 return retval;
6953 }
6954
6955 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6956 LLVMModuleRef llvm_module,
6957 struct ac_shader_binary *binary,
6958 struct ac_shader_config *config,
6959 struct ac_shader_variant_info *shader_info,
6960 gl_shader_stage stage,
6961 bool dump_shader, bool supports_spill)
6962 {
6963 if (dump_shader)
6964 ac_dump_module(llvm_module);
6965
6966 memset(binary, 0, sizeof(*binary));
6967 int v = ac_llvm_compile(llvm_module, binary, tm);
6968 if (v) {
6969 fprintf(stderr, "compile failed\n");
6970 }
6971
6972 if (dump_shader)
6973 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6974
6975 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6976
6977 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6978 LLVMDisposeModule(llvm_module);
6979 LLVMContextDispose(ctx);
6980
6981 if (stage == MESA_SHADER_FRAGMENT) {
6982 shader_info->num_input_vgprs = 0;
6983 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6984 shader_info->num_input_vgprs += 2;
6985 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6986 shader_info->num_input_vgprs += 2;
6987 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6988 shader_info->num_input_vgprs += 2;
6989 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6990 shader_info->num_input_vgprs += 3;
6991 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6992 shader_info->num_input_vgprs += 2;
6993 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6994 shader_info->num_input_vgprs += 2;
6995 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6996 shader_info->num_input_vgprs += 2;
6997 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6998 shader_info->num_input_vgprs += 1;
6999 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7000 shader_info->num_input_vgprs += 1;
7001 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7002 shader_info->num_input_vgprs += 1;
7003 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7004 shader_info->num_input_vgprs += 1;
7005 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7006 shader_info->num_input_vgprs += 1;
7007 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7008 shader_info->num_input_vgprs += 1;
7009 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7010 shader_info->num_input_vgprs += 1;
7011 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7012 shader_info->num_input_vgprs += 1;
7013 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7014 shader_info->num_input_vgprs += 1;
7015 }
7016 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7017
7018 /* +3 for scratch wave offset and VCC */
7019 config->num_sgprs = MAX2(config->num_sgprs,
7020 shader_info->num_input_sgprs + 3);
7021
7022 /* Enable 64-bit and 16-bit denormals, because there is no performance
7023 * cost.
7024 *
7025 * If denormals are enabled, all floating-point output modifiers are
7026 * ignored.
7027 *
7028 * Don't enable denormals for 32-bit floats, because:
7029 * - Floating-point output modifiers would be ignored by the hw.
7030 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7031 * have to stop using those.
7032 * - SI & CI would be very slow.
7033 */
7034 config->float_mode |= V_00B028_FP_64_DENORMS;
7035 }
7036
7037 static void
7038 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7039 {
7040 switch (nir->info.stage) {
7041 case MESA_SHADER_COMPUTE:
7042 for (int i = 0; i < 3; ++i)
7043 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7044 break;
7045 case MESA_SHADER_FRAGMENT:
7046 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7047 break;
7048 case MESA_SHADER_GEOMETRY:
7049 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7050 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7051 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7052 shader_info->gs.invocations = nir->info.gs.invocations;
7053 break;
7054 case MESA_SHADER_TESS_EVAL:
7055 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7056 shader_info->tes.spacing = nir->info.tess.spacing;
7057 shader_info->tes.ccw = nir->info.tess.ccw;
7058 shader_info->tes.point_mode = nir->info.tess.point_mode;
7059 shader_info->tes.as_es = options->key.tes.as_es;
7060 break;
7061 case MESA_SHADER_TESS_CTRL:
7062 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7063 break;
7064 case MESA_SHADER_VERTEX:
7065 shader_info->vs.as_es = options->key.vs.as_es;
7066 shader_info->vs.as_ls = options->key.vs.as_ls;
7067 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7068 if (options->key.vs.as_ls)
7069 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7070 break;
7071 default:
7072 break;
7073 }
7074 }
7075
7076 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7077 struct ac_shader_binary *binary,
7078 struct ac_shader_config *config,
7079 struct ac_shader_variant_info *shader_info,
7080 struct nir_shader *const *nir,
7081 int nir_count,
7082 const struct ac_nir_compiler_options *options,
7083 bool dump_shader)
7084 {
7085
7086 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7087 options);
7088
7089 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7090 for (int i = 0; i < nir_count; ++i)
7091 ac_fill_shader_info(shader_info, nir[i], options);
7092
7093 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7094 if (options->chip_class == GFX9) {
7095 if (nir_count == 2 &&
7096 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7097 shader_info->gs.es_type = nir[0]->info.stage;
7098 }
7099 }
7100 }
7101
7102 static void
7103 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7104 {
7105 LLVMValueRef vtx_offset =
7106 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7107 LLVMConstInt(ctx->ac.i32, 4, false), "");
7108 int idx = 0;
7109
7110 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7111 int length = 4;
7112 int slot = idx;
7113 int slot_inc = 1;
7114 if (!(ctx->output_mask & (1ull << i)))
7115 continue;
7116
7117 if (i == VARYING_SLOT_CLIP_DIST0) {
7118 /* unpack clip and cull from a single set of slots */
7119 length = ctx->num_output_clips + ctx->num_output_culls;
7120 if (length > 4)
7121 slot_inc = 2;
7122 }
7123
7124 for (unsigned j = 0; j < length; j++) {
7125 LLVMValueRef value, soffset;
7126
7127 soffset = LLVMConstInt(ctx->ac.i32,
7128 (slot * 4 + j) *
7129 ctx->gs_max_out_vertices * 16 * 4, false);
7130
7131 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7132 1, ctx->ac.i32_0,
7133 vtx_offset, soffset,
7134 0, 1, 1, true, false);
7135
7136 LLVMBuildStore(ctx->ac.builder,
7137 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7138 }
7139 idx += slot_inc;
7140 }
7141 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7142 }
7143
7144 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7145 struct nir_shader *geom_shader,
7146 struct ac_shader_binary *binary,
7147 struct ac_shader_config *config,
7148 struct ac_shader_variant_info *shader_info,
7149 const struct ac_nir_compiler_options *options,
7150 bool dump_shader)
7151 {
7152 struct nir_to_llvm_context ctx = {0};
7153 ctx.context = LLVMContextCreate();
7154 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7155 ctx.options = options;
7156 ctx.shader_info = shader_info;
7157
7158 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7159 options->family);
7160 ctx.ac.module = ctx.module;
7161
7162 ctx.is_gs_copy_shader = true;
7163 LLVMSetTarget(ctx.module, "amdgcn--");
7164
7165 enum ac_float_mode float_mode =
7166 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7167 AC_FLOAT_MODE_DEFAULT;
7168
7169 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7170 ctx.stage = MESA_SHADER_VERTEX;
7171
7172 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7173
7174 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7175 ac_setup_rings(&ctx);
7176
7177 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7178 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7179
7180 struct ac_nir_context nir_ctx = {};
7181 nir_ctx.ac = ctx.ac;
7182 nir_ctx.abi = &ctx.abi;
7183
7184 nir_ctx.nctx = &ctx;
7185 ctx.nir = &nir_ctx;
7186
7187 nir_foreach_variable(variable, &geom_shader->outputs) {
7188 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7189 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7190 }
7191
7192 ac_gs_copy_shader_emit(&ctx);
7193
7194 ctx.nir = NULL;
7195
7196 LLVMBuildRetVoid(ctx.ac.builder);
7197
7198 ac_llvm_finalize_module(&ctx);
7199
7200 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7201 MESA_SHADER_VERTEX,
7202 dump_shader, options->supports_spill);
7203 }