2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49 struct nir_to_llvm_context
;
51 struct ac_nir_context
{
52 struct ac_llvm_context ac
;
53 struct ac_shader_abi
*abi
;
55 gl_shader_stage stage
;
57 struct hash_table
*defs
;
58 struct hash_table
*phis
;
59 struct hash_table
*vars
;
61 LLVMValueRef main_function
;
62 LLVMBasicBlockRef continue_block
;
63 LLVMBasicBlockRef break_block
;
65 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
70 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
73 struct nir_to_llvm_context
{
74 struct ac_llvm_context ac
;
75 const struct ac_nir_compiler_options
*options
;
76 struct ac_shader_variant_info
*shader_info
;
77 struct ac_shader_abi abi
;
78 struct ac_nir_context
*nir
;
80 unsigned max_workgroup_size
;
81 LLVMContextRef context
;
83 LLVMBuilderRef builder
;
84 LLVMValueRef main_function
;
86 struct hash_table
*defs
;
87 struct hash_table
*phis
;
89 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
90 LLVMValueRef ring_offsets
;
91 LLVMValueRef push_constants
;
92 LLVMValueRef view_index
;
93 LLVMValueRef num_work_groups
;
94 LLVMValueRef workgroup_ids
[3];
95 LLVMValueRef local_invocation_ids
;
98 LLVMValueRef vertex_buffers
;
99 LLVMValueRef rel_auto_id
;
100 LLVMValueRef vs_prim_id
;
101 LLVMValueRef ls_out_layout
;
102 LLVMValueRef es2gs_offset
;
104 LLVMValueRef tcs_offchip_layout
;
105 LLVMValueRef tcs_out_offsets
;
106 LLVMValueRef tcs_out_layout
;
107 LLVMValueRef tcs_in_layout
;
109 LLVMValueRef merged_wave_info
;
110 LLVMValueRef tess_factor_offset
;
111 LLVMValueRef tes_rel_patch_id
;
115 LLVMValueRef gsvs_ring_stride
;
116 LLVMValueRef gsvs_num_entries
;
117 LLVMValueRef gs2vs_offset
;
118 LLVMValueRef gs_wave_id
;
119 LLVMValueRef gs_vtx_offset
[6];
121 LLVMValueRef esgs_ring
;
122 LLVMValueRef gsvs_ring
;
123 LLVMValueRef hs_ring_tess_offchip
;
124 LLVMValueRef hs_ring_tess_factor
;
126 LLVMValueRef sample_pos_offset
;
127 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
128 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
130 gl_shader_stage stage
;
132 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
135 uint64_t output_mask
;
136 uint8_t num_output_clips
;
137 uint8_t num_output_culls
;
139 bool is_gs_copy_shader
;
140 LLVMValueRef gs_next_vertex
;
141 unsigned gs_max_out_vertices
;
143 unsigned tes_primitive_mode
;
144 uint64_t tess_outputs_written
;
145 uint64_t tess_patch_outputs_written
;
147 uint32_t tcs_patch_outputs_read
;
148 uint64_t tcs_outputs_read
;
151 static inline struct nir_to_llvm_context
*
152 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
154 struct nir_to_llvm_context
*ctx
= NULL
;
155 return container_of(abi
, ctx
, abi
);
158 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
159 const nir_deref_var
*deref
,
160 enum ac_descriptor_type desc_type
,
161 const nir_tex_instr
*instr
,
162 bool image
, bool write
);
164 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
166 return (index
* 4) + chan
;
169 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
171 /* handle patch indices separate */
172 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
174 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
176 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
177 return 2 + (slot
- VARYING_SLOT_PATCH0
);
179 if (slot
== VARYING_SLOT_POS
)
181 if (slot
== VARYING_SLOT_PSIZ
)
183 if (slot
== VARYING_SLOT_CLIP_DIST0
)
185 /* 3 is reserved for clip dist as well */
186 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
187 return 4 + (slot
- VARYING_SLOT_VAR0
);
188 unreachable("illegal slot in get unique index\n");
191 static void set_llvm_calling_convention(LLVMValueRef func
,
192 gl_shader_stage stage
)
194 enum radeon_llvm_calling_convention calling_conv
;
197 case MESA_SHADER_VERTEX
:
198 case MESA_SHADER_TESS_EVAL
:
199 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
201 case MESA_SHADER_GEOMETRY
:
202 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
204 case MESA_SHADER_TESS_CTRL
:
205 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
207 case MESA_SHADER_FRAGMENT
:
208 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
210 case MESA_SHADER_COMPUTE
:
211 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
214 unreachable("Unhandle shader type");
217 LLVMSetFunctionCallConv(func
, calling_conv
);
222 LLVMTypeRef types
[MAX_ARGS
];
223 LLVMValueRef
*assign
[MAX_ARGS
];
224 unsigned array_params_mask
;
227 uint8_t num_sgprs_used
;
228 uint8_t num_vgprs_used
;
231 enum ac_arg_regfile
{
237 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
238 LLVMValueRef
*param_ptr
)
240 assert(info
->count
< MAX_ARGS
);
242 info
->assign
[info
->count
] = param_ptr
;
243 info
->types
[info
->count
] = type
;
246 if (regfile
== ARG_SGPR
) {
247 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
250 assert(regfile
== ARG_VGPR
);
251 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
256 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
258 info
->array_params_mask
|= (1 << info
->count
);
259 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
262 static void assign_arguments(LLVMValueRef main_function
,
263 struct arg_info
*info
)
266 for (i
= 0; i
< info
->count
; i
++) {
268 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
273 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
274 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
275 unsigned num_return_elems
,
276 struct arg_info
*args
,
277 unsigned max_workgroup_size
,
280 LLVMTypeRef main_function_type
, ret_type
;
281 LLVMBasicBlockRef main_function_body
;
283 if (num_return_elems
)
284 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
285 num_return_elems
, true);
287 ret_type
= LLVMVoidTypeInContext(ctx
);
289 /* Setup the function */
291 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
292 LLVMValueRef main_function
=
293 LLVMAddFunction(module
, "main", main_function_type
);
295 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
296 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
298 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
299 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
300 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
302 if (args
->array_params_mask
& (1 << i
)) {
303 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
304 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
305 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
309 if (max_workgroup_size
) {
310 ac_llvm_add_target_dep_function_attr(main_function
,
311 "amdgpu-max-work-group-size",
315 /* These were copied from some LLVM test. */
316 LLVMAddTargetDependentFunctionAttr(main_function
,
317 "less-precise-fpmad",
319 LLVMAddTargetDependentFunctionAttr(main_function
,
322 LLVMAddTargetDependentFunctionAttr(main_function
,
325 LLVMAddTargetDependentFunctionAttr(main_function
,
328 LLVMAddTargetDependentFunctionAttr(main_function
,
329 "no-signed-zeros-fp-math",
332 return main_function
;
335 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
337 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
338 type
= LLVMGetElementType(type
);
340 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
341 return LLVMGetIntTypeWidth(type
);
343 if (type
== ctx
->f16
)
345 if (type
== ctx
->f32
)
347 if (type
== ctx
->f64
)
350 unreachable("Unhandled type kind in get_elem_bits");
353 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
354 LLVMValueRef param
, unsigned rshift
,
357 LLVMValueRef value
= param
;
359 value
= LLVMBuildLShr(ctx
->builder
, value
,
360 LLVMConstInt(ctx
->i32
, rshift
, false), "");
362 if (rshift
+ bitwidth
< 32) {
363 unsigned mask
= (1 << bitwidth
) - 1;
364 value
= LLVMBuildAnd(ctx
->builder
, value
,
365 LLVMConstInt(ctx
->i32
, mask
, false), "");
370 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
372 switch (ctx
->stage
) {
373 case MESA_SHADER_TESS_CTRL
:
374 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
375 case MESA_SHADER_TESS_EVAL
:
376 return ctx
->tes_rel_patch_id
;
379 unreachable("Illegal stage");
383 /* Tessellation shaders pass outputs to the next shader using LDS.
385 * LS outputs = TCS inputs
386 * TCS outputs = TES inputs
389 * - TCS inputs for patch 0
390 * - TCS inputs for patch 1
391 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
393 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
394 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
395 * - TCS outputs for patch 1
396 * - Per-patch TCS outputs for patch 1
397 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
398 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
401 * All three shaders VS(LS), TCS, TES share the same LDS space.
404 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
406 if (ctx
->stage
== MESA_SHADER_VERTEX
)
407 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
408 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
409 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
417 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
419 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
423 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
425 return LLVMBuildMul(ctx
->builder
,
426 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
427 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
431 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
433 return LLVMBuildMul(ctx
->builder
,
434 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
435 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
439 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
441 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
442 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
444 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
448 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
450 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
451 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
452 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
454 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
455 LLVMBuildMul(ctx
->builder
, patch_stride
,
461 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
463 LLVMValueRef patch0_patch_data_offset
=
464 get_tcs_out_patch0_patch_data_offset(ctx
);
465 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
466 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
468 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
469 LLVMBuildMul(ctx
->builder
, patch_stride
,
475 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
476 uint32_t indirect_offset
)
478 ud_info
->sgpr_idx
= *sgpr_idx
;
479 ud_info
->num_sgprs
= num_sgprs
;
480 ud_info
->indirect
= indirect_offset
> 0;
481 ud_info
->indirect_offset
= indirect_offset
;
482 *sgpr_idx
+= num_sgprs
;
486 set_loc_shader(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
489 struct ac_userdata_info
*ud_info
=
490 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
493 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
497 set_loc_desc(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
498 uint32_t indirect_offset
)
500 struct ac_userdata_info
*ud_info
=
501 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
504 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
507 struct user_sgpr_info
{
508 bool need_ring_offsets
;
510 bool indirect_all_descriptor_sets
;
513 static bool needs_view_index_sgpr(struct nir_to_llvm_context
*ctx
,
514 gl_shader_stage stage
)
517 case MESA_SHADER_VERTEX
:
518 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
519 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
522 case MESA_SHADER_TESS_EVAL
:
523 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
526 case MESA_SHADER_GEOMETRY
:
527 case MESA_SHADER_TESS_CTRL
:
528 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
537 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
538 gl_shader_stage stage
,
539 bool needs_view_index
,
540 struct user_sgpr_info
*user_sgpr_info
)
542 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
544 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
545 if (stage
== MESA_SHADER_GEOMETRY
||
546 stage
== MESA_SHADER_VERTEX
||
547 stage
== MESA_SHADER_TESS_CTRL
||
548 stage
== MESA_SHADER_TESS_EVAL
||
549 ctx
->is_gs_copy_shader
)
550 user_sgpr_info
->need_ring_offsets
= true;
552 if (stage
== MESA_SHADER_FRAGMENT
&&
553 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
554 user_sgpr_info
->need_ring_offsets
= true;
556 /* 2 user sgprs will nearly always be allocated for scratch/rings */
557 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
558 user_sgpr_info
->sgpr_count
+= 2;
561 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
563 case MESA_SHADER_COMPUTE
:
564 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
565 user_sgpr_info
->sgpr_count
+= 3;
567 case MESA_SHADER_FRAGMENT
:
568 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
570 case MESA_SHADER_VERTEX
:
571 if (!ctx
->is_gs_copy_shader
) {
572 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
573 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
574 user_sgpr_info
->sgpr_count
+= 3;
576 user_sgpr_info
->sgpr_count
+= 2;
579 if (ctx
->options
->key
.vs
.as_ls
)
580 user_sgpr_info
->sgpr_count
++;
582 case MESA_SHADER_TESS_CTRL
:
583 user_sgpr_info
->sgpr_count
+= 4;
585 case MESA_SHADER_TESS_EVAL
:
586 user_sgpr_info
->sgpr_count
+= 1;
588 case MESA_SHADER_GEOMETRY
:
589 user_sgpr_info
->sgpr_count
+= 2;
595 if (needs_view_index
)
596 user_sgpr_info
->sgpr_count
++;
598 if (ctx
->shader_info
->info
.loads_push_constants
)
599 user_sgpr_info
->sgpr_count
+= 2;
601 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
602 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
604 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
605 user_sgpr_info
->sgpr_count
+= 2;
606 user_sgpr_info
->indirect_all_descriptor_sets
= true;
608 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
613 declare_global_input_sgprs(struct nir_to_llvm_context
*ctx
,
614 gl_shader_stage stage
,
615 bool has_previous_stage
,
616 gl_shader_stage previous_stage
,
617 const struct user_sgpr_info
*user_sgpr_info
,
618 struct arg_info
*args
,
619 LLVMValueRef
*desc_sets
)
621 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
622 unsigned num_sets
= ctx
->options
->layout
?
623 ctx
->options
->layout
->num_sets
: 0;
624 unsigned stage_mask
= 1 << stage
;
626 if (has_previous_stage
)
627 stage_mask
|= 1 << previous_stage
;
629 /* 1 for each descriptor set */
630 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
631 for (unsigned i
= 0; i
< num_sets
; ++i
) {
632 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
633 add_array_arg(args
, type
,
634 &ctx
->descriptor_sets
[i
]);
638 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
641 if (ctx
->shader_info
->info
.loads_push_constants
) {
642 /* 1 for push constants and dynamic descriptors */
643 add_array_arg(args
, type
, &ctx
->push_constants
);
648 declare_vs_specific_input_sgprs(struct nir_to_llvm_context
*ctx
,
649 gl_shader_stage stage
,
650 bool has_previous_stage
,
651 gl_shader_stage previous_stage
,
652 struct arg_info
*args
)
654 if (!ctx
->is_gs_copy_shader
&&
655 (stage
== MESA_SHADER_VERTEX
||
656 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
657 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
658 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
659 &ctx
->vertex_buffers
);
661 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
662 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
663 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
664 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
670 declare_vs_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
672 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
673 if (!ctx
->is_gs_copy_shader
) {
674 if (ctx
->options
->key
.vs
.as_ls
) {
675 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
676 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
679 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
681 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
686 declare_tes_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
688 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
689 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
690 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
691 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
695 set_global_input_locs(struct nir_to_llvm_context
*ctx
, gl_shader_stage stage
,
696 bool has_previous_stage
, gl_shader_stage previous_stage
,
697 const struct user_sgpr_info
*user_sgpr_info
,
698 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
700 unsigned num_sets
= ctx
->options
->layout
?
701 ctx
->options
->layout
->num_sets
: 0;
702 unsigned stage_mask
= 1 << stage
;
704 if (has_previous_stage
)
705 stage_mask
|= 1 << previous_stage
;
707 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
708 for (unsigned i
= 0; i
< num_sets
; ++i
) {
709 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
710 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
712 ctx
->descriptor_sets
[i
] = NULL
;
715 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
718 for (unsigned i
= 0; i
< num_sets
; ++i
) {
719 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
720 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
721 ctx
->descriptor_sets
[i
] =
722 ac_build_load_to_sgpr(&ctx
->ac
,
724 LLVMConstInt(ctx
->ac
.i32
, i
, false));
727 ctx
->descriptor_sets
[i
] = NULL
;
729 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
732 if (ctx
->shader_info
->info
.loads_push_constants
) {
733 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
738 set_vs_specific_input_locs(struct nir_to_llvm_context
*ctx
,
739 gl_shader_stage stage
, bool has_previous_stage
,
740 gl_shader_stage previous_stage
,
741 uint8_t *user_sgpr_idx
)
743 if (!ctx
->is_gs_copy_shader
&&
744 (stage
== MESA_SHADER_VERTEX
||
745 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
746 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
747 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
752 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
755 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
756 user_sgpr_idx
, vs_num
);
760 static void create_function(struct nir_to_llvm_context
*ctx
,
761 gl_shader_stage stage
,
762 bool has_previous_stage
,
763 gl_shader_stage previous_stage
)
765 uint8_t user_sgpr_idx
;
766 struct user_sgpr_info user_sgpr_info
;
767 struct arg_info args
= {};
768 LLVMValueRef desc_sets
;
769 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
770 allocate_user_sgprs(ctx
, stage
, needs_view_index
, &user_sgpr_info
);
772 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
773 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
778 case MESA_SHADER_COMPUTE
:
779 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
780 previous_stage
, &user_sgpr_info
,
783 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
784 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
785 &ctx
->num_work_groups
);
788 for (int i
= 0; i
< 3; i
++) {
789 ctx
->workgroup_ids
[i
] = NULL
;
790 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
791 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
792 &ctx
->workgroup_ids
[i
]);
796 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
797 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tg_size
);
798 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
799 &ctx
->local_invocation_ids
);
801 case MESA_SHADER_VERTEX
:
802 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
803 previous_stage
, &user_sgpr_info
,
805 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
806 previous_stage
, &args
);
808 if (needs_view_index
)
809 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
810 if (ctx
->options
->key
.vs
.as_es
)
811 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
813 else if (ctx
->options
->key
.vs
.as_ls
)
814 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
815 &ctx
->ls_out_layout
);
817 declare_vs_input_vgprs(ctx
, &args
);
819 case MESA_SHADER_TESS_CTRL
:
820 if (has_previous_stage
) {
821 // First 6 system regs
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
823 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
824 &ctx
->merged_wave_info
);
825 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
826 &ctx
->tess_factor_offset
);
828 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
829 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
830 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
832 declare_global_input_sgprs(ctx
, stage
,
835 &user_sgpr_info
, &args
,
837 declare_vs_specific_input_sgprs(ctx
, stage
,
839 previous_stage
, &args
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
842 &ctx
->ls_out_layout
);
844 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
845 &ctx
->tcs_offchip_layout
);
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->tcs_out_offsets
);
848 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
849 &ctx
->tcs_out_layout
);
850 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
851 &ctx
->tcs_in_layout
);
852 if (needs_view_index
)
853 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
856 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
857 &ctx
->abi
.tcs_patch_id
);
858 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
859 &ctx
->abi
.tcs_rel_ids
);
861 declare_vs_input_vgprs(ctx
, &args
);
863 declare_global_input_sgprs(ctx
, stage
,
866 &user_sgpr_info
, &args
,
869 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
870 &ctx
->tcs_offchip_layout
);
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->tcs_out_offsets
);
873 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
874 &ctx
->tcs_out_layout
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tcs_in_layout
);
877 if (needs_view_index
)
878 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
881 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
882 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
883 &ctx
->tess_factor_offset
);
884 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
885 &ctx
->abi
.tcs_patch_id
);
886 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
887 &ctx
->abi
.tcs_rel_ids
);
890 case MESA_SHADER_TESS_EVAL
:
891 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
892 previous_stage
, &user_sgpr_info
,
895 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
896 if (needs_view_index
)
897 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
899 if (ctx
->options
->key
.tes
.as_es
) {
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
901 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
902 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
905 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
906 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
908 declare_tes_input_vgprs(ctx
, &args
);
910 case MESA_SHADER_GEOMETRY
:
911 if (has_previous_stage
) {
912 // First 6 system regs
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
916 &ctx
->merged_wave_info
);
917 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
919 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
920 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
921 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
923 declare_global_input_sgprs(ctx
, stage
,
926 &user_sgpr_info
, &args
,
929 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
930 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
931 &ctx
->tcs_offchip_layout
);
933 declare_vs_specific_input_sgprs(ctx
, stage
,
939 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
940 &ctx
->gsvs_ring_stride
);
941 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
942 &ctx
->gsvs_num_entries
);
943 if (needs_view_index
)
944 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
947 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
948 &ctx
->gs_vtx_offset
[0]);
949 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
950 &ctx
->gs_vtx_offset
[2]);
951 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
952 &ctx
->abi
.gs_prim_id
);
953 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
954 &ctx
->abi
.gs_invocation_id
);
955 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
956 &ctx
->gs_vtx_offset
[4]);
958 if (previous_stage
== MESA_SHADER_VERTEX
) {
959 declare_vs_input_vgprs(ctx
, &args
);
961 declare_tes_input_vgprs(ctx
, &args
);
964 declare_global_input_sgprs(ctx
, stage
,
967 &user_sgpr_info
, &args
,
970 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
971 &ctx
->gsvs_ring_stride
);
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
973 &ctx
->gsvs_num_entries
);
974 if (needs_view_index
)
975 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
978 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
979 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
980 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
981 &ctx
->gs_vtx_offset
[0]);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->gs_vtx_offset
[1]);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->abi
.gs_prim_id
);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->gs_vtx_offset
[2]);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
989 &ctx
->gs_vtx_offset
[3]);
990 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
991 &ctx
->gs_vtx_offset
[4]);
992 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
993 &ctx
->gs_vtx_offset
[5]);
994 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
995 &ctx
->abi
.gs_invocation_id
);
998 case MESA_SHADER_FRAGMENT
:
999 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1000 previous_stage
, &user_sgpr_info
,
1003 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
1004 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1005 &ctx
->sample_pos_offset
);
1007 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1018 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1019 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1020 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1021 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1022 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1023 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1026 unreachable("Shader stage not implemented");
1029 ctx
->main_function
= create_llvm_function(
1030 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
1031 ctx
->max_workgroup_size
,
1032 ctx
->options
->unsafe_math
);
1033 set_llvm_calling_convention(ctx
->main_function
, stage
);
1036 ctx
->shader_info
->num_input_vgprs
= 0;
1037 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1039 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1041 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1042 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1044 assign_arguments(ctx
->main_function
, &args
);
1048 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1049 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1051 if (ctx
->options
->supports_spill
) {
1052 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1053 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1054 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1055 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
1056 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1060 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1061 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1062 if (has_previous_stage
)
1065 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1066 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1069 case MESA_SHADER_COMPUTE
:
1070 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1071 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1075 case MESA_SHADER_VERTEX
:
1076 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1077 previous_stage
, &user_sgpr_idx
);
1078 if (ctx
->view_index
)
1079 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1080 if (ctx
->options
->key
.vs
.as_ls
) {
1081 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1084 if (ctx
->options
->key
.vs
.as_ls
)
1085 ac_declare_lds_as_pointer(&ctx
->ac
);
1087 case MESA_SHADER_TESS_CTRL
:
1088 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1089 previous_stage
, &user_sgpr_idx
);
1090 if (has_previous_stage
)
1091 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1093 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1094 if (ctx
->view_index
)
1095 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1096 ac_declare_lds_as_pointer(&ctx
->ac
);
1098 case MESA_SHADER_TESS_EVAL
:
1099 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1100 if (ctx
->view_index
)
1101 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1103 case MESA_SHADER_GEOMETRY
:
1104 if (has_previous_stage
) {
1105 if (previous_stage
== MESA_SHADER_VERTEX
)
1106 set_vs_specific_input_locs(ctx
, stage
,
1111 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1114 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1116 if (ctx
->view_index
)
1117 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1118 if (has_previous_stage
)
1119 ac_declare_lds_as_pointer(&ctx
->ac
);
1121 case MESA_SHADER_FRAGMENT
:
1122 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1123 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1128 unreachable("Shader stage not implemented");
1131 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1134 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1135 LLVMValueRef value
, unsigned count
)
1137 unsigned num_components
= ac_get_llvm_num_components(value
);
1138 if (count
== num_components
)
1141 LLVMValueRef masks
[] = {
1142 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1143 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1146 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1149 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1150 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1154 build_store_values_extended(struct ac_llvm_context
*ac
,
1155 LLVMValueRef
*values
,
1156 unsigned value_count
,
1157 unsigned value_stride
,
1160 LLVMBuilderRef builder
= ac
->builder
;
1163 for (i
= 0; i
< value_count
; i
++) {
1164 LLVMValueRef ptr
= values
[i
* value_stride
];
1165 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1166 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1167 LLVMBuildStore(builder
, value
, ptr
);
1171 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1172 const nir_ssa_def
*def
)
1174 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1175 if (def
->num_components
> 1) {
1176 type
= LLVMVectorType(type
, def
->num_components
);
1181 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1184 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1185 return (LLVMValueRef
)entry
->data
;
1189 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1190 const struct nir_block
*b
)
1192 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1193 return (LLVMBasicBlockRef
)entry
->data
;
1196 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1198 unsigned num_components
)
1200 LLVMValueRef value
= get_src(ctx
, src
.src
);
1201 bool need_swizzle
= false;
1204 LLVMTypeRef type
= LLVMTypeOf(value
);
1205 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1206 ? LLVMGetVectorSize(type
)
1209 for (unsigned i
= 0; i
< num_components
; ++i
) {
1210 assert(src
.swizzle
[i
] < src_components
);
1211 if (src
.swizzle
[i
] != i
)
1212 need_swizzle
= true;
1215 if (need_swizzle
|| num_components
!= src_components
) {
1216 LLVMValueRef masks
[] = {
1217 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1218 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1219 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1220 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1222 if (src_components
> 1 && num_components
== 1) {
1223 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1225 } else if (src_components
== 1 && num_components
> 1) {
1226 LLVMValueRef values
[] = {value
, value
, value
, value
};
1227 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1229 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1230 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1234 assert(!src
.negate
);
1239 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1240 LLVMIntPredicate pred
, LLVMValueRef src0
,
1243 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1244 return LLVMBuildSelect(ctx
->builder
, result
,
1245 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1249 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1250 LLVMRealPredicate pred
, LLVMValueRef src0
,
1253 LLVMValueRef result
;
1254 src0
= ac_to_float(ctx
, src0
);
1255 src1
= ac_to_float(ctx
, src1
);
1256 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1257 return LLVMBuildSelect(ctx
->builder
, result
,
1258 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1262 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1264 LLVMTypeRef result_type
,
1268 LLVMValueRef params
[] = {
1269 ac_to_float(ctx
, src0
),
1272 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1273 get_elem_bits(ctx
, result_type
));
1274 assert(length
< sizeof(name
));
1275 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1278 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1280 LLVMTypeRef result_type
,
1281 LLVMValueRef src0
, LLVMValueRef src1
)
1284 LLVMValueRef params
[] = {
1285 ac_to_float(ctx
, src0
),
1286 ac_to_float(ctx
, src1
),
1289 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1290 get_elem_bits(ctx
, result_type
));
1291 assert(length
< sizeof(name
));
1292 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1295 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1297 LLVMTypeRef result_type
,
1298 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1301 LLVMValueRef params
[] = {
1302 ac_to_float(ctx
, src0
),
1303 ac_to_float(ctx
, src1
),
1304 ac_to_float(ctx
, src2
),
1307 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1308 get_elem_bits(ctx
, result_type
));
1309 assert(length
< sizeof(name
));
1310 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1313 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1314 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1316 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1318 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1321 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1322 LLVMIntPredicate pred
,
1323 LLVMValueRef src0
, LLVMValueRef src1
)
1325 return LLVMBuildSelect(ctx
->builder
,
1326 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1331 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1334 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1335 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1338 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1342 LLVMValueRef cmp
, val
, zero
, one
;
1345 if (bitsize
== 32) {
1355 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, zero
, "");
1356 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1357 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, zero
, "");
1358 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(type
, -1.0), "");
1362 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1363 LLVMValueRef src0
, unsigned bitsize
)
1365 LLVMValueRef cmp
, val
, zero
, one
;
1368 if (bitsize
== 32) {
1378 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, zero
, "");
1379 val
= LLVMBuildSelect(ctx
->builder
, cmp
, one
, src0
, "");
1380 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, zero
, "");
1381 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(type
, -1, true), "");
1385 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1386 LLVMValueRef src0
, unsigned bitsize
)
1391 if (bitsize
== 32) {
1392 intr
= "llvm.floor.f32";
1395 intr
= "llvm.floor.f64";
1399 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1400 LLVMValueRef params
[] = {
1403 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
, type
, params
, 1,
1404 AC_FUNC_ATTR_READNONE
);
1405 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1408 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1410 LLVMValueRef src0
, LLVMValueRef src1
)
1412 LLVMTypeRef ret_type
;
1413 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1415 LLVMValueRef params
[] = { src0
, src1
};
1416 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1419 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1420 params
, 2, AC_FUNC_ATTR_READNONE
);
1422 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1423 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1427 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1430 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1433 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1436 src0
= ac_to_float(ctx
, src0
);
1437 return LLVMBuildSExt(ctx
->builder
,
1438 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1442 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1446 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1451 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1454 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1457 return LLVMBuildSExt(ctx
->builder
,
1458 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1462 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1465 LLVMValueRef result
;
1466 LLVMValueRef cond
= NULL
;
1468 src0
= ac_to_float(&ctx
->ac
, src0
);
1469 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1471 if (ctx
->options
->chip_class
>= VI
) {
1472 LLVMValueRef args
[2];
1473 /* Check if the result is a denormal - and flush to 0 if so. */
1475 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1476 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1479 /* need to convert back up to f32 */
1480 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1482 if (ctx
->options
->chip_class
>= VI
)
1483 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1486 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1487 * so compare the result and flush to 0 if it's smaller.
1489 LLVMValueRef temp
, cond2
;
1490 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1491 ctx
->ac
.f32
, result
);
1492 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1493 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1495 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1496 temp
, ctx
->ac
.f32_0
, "");
1497 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1498 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1503 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1504 LLVMValueRef src0
, LLVMValueRef src1
)
1506 LLVMValueRef dst64
, result
;
1507 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1508 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1510 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1511 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1512 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1516 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1517 LLVMValueRef src0
, LLVMValueRef src1
)
1519 LLVMValueRef dst64
, result
;
1520 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1521 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1523 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1524 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1525 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1529 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1531 const LLVMValueRef srcs
[3])
1533 LLVMValueRef result
;
1534 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1536 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1537 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1541 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1542 LLVMValueRef src0
, LLVMValueRef src1
,
1543 LLVMValueRef src2
, LLVMValueRef src3
)
1545 LLVMValueRef bfi_args
[3], result
;
1547 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1548 LLVMBuildSub(ctx
->builder
,
1549 LLVMBuildShl(ctx
->builder
,
1554 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1557 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1560 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1561 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1563 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1564 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1565 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1567 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1571 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1574 LLVMValueRef comp
[2];
1576 src0
= ac_to_float(ctx
, src0
);
1577 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1578 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1580 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1583 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1586 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1587 LLVMValueRef temps
[2], result
, val
;
1590 for (i
= 0; i
< 2; i
++) {
1591 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1592 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1593 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1594 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1597 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1599 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1604 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1610 LLVMValueRef result
;
1612 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1613 mask
= AC_TID_MASK_LEFT
;
1614 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1615 mask
= AC_TID_MASK_TOP
;
1617 mask
= AC_TID_MASK_TOP_LEFT
;
1619 /* for DDX we want to next X pixel, DDY next Y pixel. */
1620 if (op
== nir_op_fddx_fine
||
1621 op
== nir_op_fddx_coarse
||
1627 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1632 * this takes an I,J coordinate pair,
1633 * and works out the X and Y derivatives.
1634 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1636 static LLVMValueRef
emit_ddxy_interp(
1637 struct ac_nir_context
*ctx
,
1638 LLVMValueRef interp_ij
)
1640 LLVMValueRef result
[4], a
;
1643 for (i
= 0; i
< 2; i
++) {
1644 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1645 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1646 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1647 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1649 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1652 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1654 LLVMValueRef src
[4], result
= NULL
;
1655 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1656 unsigned src_components
;
1657 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1659 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1660 switch (instr
->op
) {
1666 case nir_op_pack_half_2x16
:
1669 case nir_op_unpack_half_2x16
:
1673 src_components
= num_components
;
1676 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1677 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1679 switch (instr
->op
) {
1685 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1686 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1689 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1692 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1695 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1698 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1699 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1700 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1703 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1704 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1705 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1708 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1711 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1714 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1717 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1720 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1721 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1722 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1723 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1724 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1725 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1726 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1729 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1730 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1731 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1734 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1737 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1740 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1743 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1744 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1745 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1748 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1749 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1753 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1756 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1759 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1762 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1763 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1764 LLVMTypeOf(src
[0]), ""),
1768 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1769 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1770 LLVMTypeOf(src
[0]), ""),
1774 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1775 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1776 LLVMTypeOf(src
[0]), ""),
1780 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1783 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1786 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1789 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1792 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1795 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1798 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1801 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1804 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1807 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1810 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1811 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1814 result
= emit_iabs(&ctx
->ac
, src
[0]);
1817 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1820 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1823 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1826 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1829 result
= emit_isign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1832 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1833 result
= emit_fsign(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1836 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1837 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1840 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1841 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1844 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1845 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1847 case nir_op_fround_even
:
1848 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1849 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1852 result
= emit_ffract(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1855 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1856 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1859 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1860 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1863 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1864 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1867 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1868 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1871 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1872 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1875 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1876 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1877 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1881 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1882 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1885 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1886 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1887 if (ctx
->ac
.chip_class
< GFX9
&&
1888 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1889 /* Only pre-GFX9 chips do not flush denorms. */
1890 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1891 ac_to_float_type(&ctx
->ac
, def_type
),
1896 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1897 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1898 if (ctx
->ac
.chip_class
< GFX9
&&
1899 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1900 /* Only pre-GFX9 chips do not flush denorms. */
1901 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1902 ac_to_float_type(&ctx
->ac
, def_type
),
1907 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1908 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1910 case nir_op_ibitfield_extract
:
1911 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1913 case nir_op_ubitfield_extract
:
1914 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1916 case nir_op_bitfield_insert
:
1917 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1919 case nir_op_bitfield_reverse
:
1920 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1922 case nir_op_bit_count
:
1923 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1928 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1929 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1930 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1934 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1935 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1939 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1940 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1944 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1945 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1949 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1950 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1953 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1954 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1957 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1961 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1962 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1963 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1965 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1969 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1970 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1971 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1973 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1976 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1978 case nir_op_find_lsb
:
1979 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1980 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1982 case nir_op_ufind_msb
:
1983 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1984 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1986 case nir_op_ifind_msb
:
1987 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1988 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1990 case nir_op_uadd_carry
:
1991 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1992 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1993 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1995 case nir_op_usub_borrow
:
1996 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1997 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1998 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
2001 result
= emit_b2f(&ctx
->ac
, src
[0]);
2004 result
= emit_f2b(&ctx
->ac
, src
[0]);
2007 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
2010 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2011 result
= emit_i2b(&ctx
->ac
, src
[0]);
2013 case nir_op_fquantize2f16
:
2014 result
= emit_f2f16(ctx
->nctx
, src
[0]);
2016 case nir_op_umul_high
:
2017 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2018 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2019 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
2021 case nir_op_imul_high
:
2022 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
2023 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
2024 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
2026 case nir_op_pack_half_2x16
:
2027 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
2029 case nir_op_unpack_half_2x16
:
2030 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
2034 case nir_op_fddx_fine
:
2035 case nir_op_fddy_fine
:
2036 case nir_op_fddx_coarse
:
2037 case nir_op_fddy_coarse
:
2038 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2041 case nir_op_unpack_64_2x32_split_x
: {
2042 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2043 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2046 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2051 case nir_op_unpack_64_2x32_split_y
: {
2052 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2053 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2056 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2061 case nir_op_pack_64_2x32_split
: {
2062 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2063 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2064 src
[0], ctx
->ac
.i32_0
, "");
2065 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2066 src
[1], ctx
->ac
.i32_1
, "");
2067 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2072 fprintf(stderr
, "Unknown NIR alu instr: ");
2073 nir_print_instr(&instr
->instr
, stderr
);
2074 fprintf(stderr
, "\n");
2079 assert(instr
->dest
.dest
.is_ssa
);
2080 result
= ac_to_integer(&ctx
->ac
, result
);
2081 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2086 static void visit_load_const(struct ac_nir_context
*ctx
,
2087 const nir_load_const_instr
*instr
)
2089 LLVMValueRef values
[4], value
= NULL
;
2090 LLVMTypeRef element_type
=
2091 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2093 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2094 switch (instr
->def
.bit_size
) {
2096 values
[i
] = LLVMConstInt(element_type
,
2097 instr
->value
.u32
[i
], false);
2100 values
[i
] = LLVMConstInt(element_type
,
2101 instr
->value
.u64
[i
], false);
2105 "unsupported nir load_const bit_size: %d\n",
2106 instr
->def
.bit_size
);
2110 if (instr
->def
.num_components
> 1) {
2111 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2115 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2118 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2121 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2122 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2123 LLVMPointerType(type
, addr_space
), "");
2127 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2130 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2131 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2134 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2135 /* On VI, the descriptor contains the size in bytes,
2136 * but TXQ must return the size in elements.
2137 * The stride is always non-zero for resources using TXQ.
2139 LLVMValueRef stride
=
2140 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2142 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2143 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2144 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2145 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2147 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2153 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2156 static void build_int_type_name(
2158 char *buf
, unsigned bufsize
)
2160 assert(bufsize
>= 6);
2162 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2163 snprintf(buf
, bufsize
, "v%ui32",
2164 LLVMGetVectorSize(type
));
2169 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2170 struct ac_image_args
*args
,
2171 const nir_tex_instr
*instr
)
2173 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2174 LLVMValueRef coord
= args
->addr
;
2175 LLVMValueRef half_texel
[2];
2176 LLVMValueRef compare_cube_wa
= NULL
;
2177 LLVMValueRef result
;
2179 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2183 struct ac_image_args txq_args
= { 0 };
2185 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2186 txq_args
.opcode
= ac_image_get_resinfo
;
2187 txq_args
.dmask
= 0xf;
2188 txq_args
.addr
= ctx
->i32_0
;
2189 txq_args
.resource
= args
->resource
;
2190 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2192 for (c
= 0; c
< 2; c
++) {
2193 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2194 LLVMConstInt(ctx
->i32
, c
, false), "");
2195 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2196 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2197 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2198 LLVMConstReal(ctx
->f32
, -0.5), "");
2202 LLVMValueRef orig_coords
= args
->addr
;
2204 for (c
= 0; c
< 2; c
++) {
2206 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2207 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2208 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2209 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2210 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2211 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2216 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2217 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2218 * workaround by sampling using a scaled type and converting.
2219 * This is taken from amdgpu-pro shaders.
2221 /* NOTE this produces some ugly code compared to amdgpu-pro,
2222 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2223 * and then reads them back. -pro generates two selects,
2224 * one s_cmp for the descriptor rewriting
2225 * one v_cmp for the coordinate and result changes.
2227 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2228 LLVMValueRef tmp
, tmp2
;
2230 /* workaround 8/8/8/8 uint/sint cube gather bug */
2231 /* first detect it then change to a scaled read and f2i */
2232 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2235 /* extract the DATA_FORMAT */
2236 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2237 LLVMConstInt(ctx
->i32
, 6, false), false);
2239 /* is the DATA_FORMAT == 8_8_8_8 */
2240 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2242 if (stype
== GLSL_TYPE_UINT
)
2243 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2244 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2245 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2247 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2248 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2249 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2251 /* replace the NUM FORMAT in the descriptor */
2252 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2253 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2255 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2257 /* don't modify the coordinates for this case */
2258 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2261 result
= ac_build_image_opcode(ctx
, args
);
2263 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2264 LLVMValueRef tmp
, tmp2
;
2266 /* if the cube workaround is in place, f2i the result. */
2267 for (c
= 0; c
< 4; c
++) {
2268 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2269 if (stype
== GLSL_TYPE_UINT
)
2270 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2272 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2273 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2274 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2275 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2276 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2277 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2283 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2284 const nir_tex_instr
*instr
,
2286 struct ac_image_args
*args
)
2288 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2289 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2291 return ac_build_buffer_load_format(&ctx
->ac
,
2295 util_last_bit(mask
),
2299 args
->opcode
= ac_image_sample
;
2300 args
->compare
= instr
->is_shadow
;
2302 switch (instr
->op
) {
2304 case nir_texop_txf_ms
:
2305 case nir_texop_samples_identical
:
2306 args
->opcode
= lod_is_zero
||
2307 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2308 ac_image_load
: ac_image_load_mip
;
2309 args
->compare
= false;
2310 args
->offset
= false;
2317 args
->level_zero
= true;
2322 case nir_texop_query_levels
:
2323 args
->opcode
= ac_image_get_resinfo
;
2326 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2327 args
->level_zero
= true;
2333 args
->opcode
= ac_image_gather4
;
2334 args
->level_zero
= true;
2337 args
->opcode
= ac_image_get_lod
;
2338 args
->compare
= false;
2339 args
->offset
= false;
2345 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2346 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2347 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2348 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2351 return ac_build_image_opcode(&ctx
->ac
, args
);
2354 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2355 nir_intrinsic_instr
*instr
)
2357 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2358 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2359 unsigned binding
= nir_intrinsic_binding(instr
);
2360 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2361 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2362 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2363 unsigned base_offset
= layout
->binding
[binding
].offset
;
2364 LLVMValueRef offset
, stride
;
2366 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2367 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2368 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2369 layout
->binding
[binding
].dynamic_offset_offset
;
2370 desc_ptr
= ctx
->push_constants
;
2371 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2372 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2374 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2376 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2377 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2378 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2380 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2381 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2382 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2387 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2388 nir_intrinsic_instr
*instr
)
2390 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2391 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2393 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2394 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2398 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2399 nir_intrinsic_instr
*instr
)
2401 LLVMValueRef ptr
, addr
;
2403 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2404 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2406 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2407 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2409 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2412 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2413 const nir_intrinsic_instr
*instr
)
2415 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2417 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2420 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2422 uint32_t new_mask
= 0;
2423 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2424 if (mask
& (1u << i
))
2425 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2429 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2430 unsigned start
, unsigned count
)
2432 LLVMTypeRef type
= LLVMTypeOf(src
);
2434 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2440 unsigned src_elements
= LLVMGetVectorSize(type
);
2441 assert(start
< src_elements
);
2442 assert(start
+ count
<= src_elements
);
2444 if (start
== 0 && count
== src_elements
)
2448 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2451 LLVMValueRef indices
[8];
2452 for (unsigned i
= 0; i
< count
; ++i
)
2453 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2455 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2456 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2459 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2460 nir_intrinsic_instr
*instr
)
2462 const char *store_name
;
2463 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2464 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2465 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2466 int components_32bit
= elem_size_mult
* instr
->num_components
;
2467 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2468 LLVMValueRef base_data
, base_offset
;
2469 LLVMValueRef params
[6];
2471 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2472 get_src(ctx
, instr
->src
[1]), true);
2473 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2474 params
[4] = ctx
->ac
.i1false
; /* glc */
2475 params
[5] = ctx
->ac
.i1false
; /* slc */
2477 if (components_32bit
> 1)
2478 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2480 writemask
= widen_mask(writemask
, elem_size_mult
);
2482 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2483 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2484 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2486 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2490 LLVMValueRef offset
;
2492 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2494 /* Due to an LLVM limitation, split 3-element writes
2495 * into a 2-element and a 1-element write. */
2497 writemask
|= 1 << (start
+ 2);
2502 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2507 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2508 } else if (count
== 2) {
2509 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2513 store_name
= "llvm.amdgcn.buffer.store.f32";
2515 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2517 offset
= base_offset
;
2519 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2523 ac_build_intrinsic(&ctx
->ac
, store_name
,
2524 ctx
->ac
.voidt
, params
, 6, 0);
2528 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2529 const nir_intrinsic_instr
*instr
)
2532 LLVMValueRef params
[6];
2535 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2536 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2538 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2539 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2540 get_src(ctx
, instr
->src
[0]),
2542 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2543 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2544 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2546 switch (instr
->intrinsic
) {
2547 case nir_intrinsic_ssbo_atomic_add
:
2548 name
= "llvm.amdgcn.buffer.atomic.add";
2550 case nir_intrinsic_ssbo_atomic_imin
:
2551 name
= "llvm.amdgcn.buffer.atomic.smin";
2553 case nir_intrinsic_ssbo_atomic_umin
:
2554 name
= "llvm.amdgcn.buffer.atomic.umin";
2556 case nir_intrinsic_ssbo_atomic_imax
:
2557 name
= "llvm.amdgcn.buffer.atomic.smax";
2559 case nir_intrinsic_ssbo_atomic_umax
:
2560 name
= "llvm.amdgcn.buffer.atomic.umax";
2562 case nir_intrinsic_ssbo_atomic_and
:
2563 name
= "llvm.amdgcn.buffer.atomic.and";
2565 case nir_intrinsic_ssbo_atomic_or
:
2566 name
= "llvm.amdgcn.buffer.atomic.or";
2568 case nir_intrinsic_ssbo_atomic_xor
:
2569 name
= "llvm.amdgcn.buffer.atomic.xor";
2571 case nir_intrinsic_ssbo_atomic_exchange
:
2572 name
= "llvm.amdgcn.buffer.atomic.swap";
2574 case nir_intrinsic_ssbo_atomic_comp_swap
:
2575 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2581 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2584 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2585 const nir_intrinsic_instr
*instr
)
2587 LLVMValueRef results
[2];
2588 int load_components
;
2589 int num_components
= instr
->num_components
;
2590 if (instr
->dest
.ssa
.bit_size
== 64)
2591 num_components
*= 2;
2593 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2594 load_components
= MIN2(num_components
- i
, 4);
2595 const char *load_name
;
2596 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2597 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2598 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2600 if (load_components
== 3)
2601 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2602 else if (load_components
> 1)
2603 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2605 if (load_components
>= 3)
2606 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2607 else if (load_components
== 2)
2608 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2609 else if (load_components
== 1)
2610 load_name
= "llvm.amdgcn.buffer.load.f32";
2612 unreachable("unhandled number of components");
2614 LLVMValueRef params
[] = {
2615 ctx
->abi
->load_ssbo(ctx
->abi
,
2616 get_src(ctx
, instr
->src
[0]),
2624 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2628 LLVMValueRef ret
= results
[0];
2629 if (num_components
> 4 || num_components
== 3) {
2630 LLVMValueRef masks
[] = {
2631 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2632 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2633 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2634 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2637 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2638 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2639 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2642 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2643 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2646 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2647 const nir_intrinsic_instr
*instr
)
2650 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2651 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2652 int num_components
= instr
->num_components
;
2654 if (ctx
->abi
->load_ubo
)
2655 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2657 if (instr
->dest
.ssa
.bit_size
== 64)
2658 num_components
*= 2;
2660 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2661 NULL
, 0, false, false, true, true);
2662 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2663 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2664 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2668 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2669 bool vs_in
, unsigned *vertex_index_out
,
2670 LLVMValueRef
*vertex_index_ref
,
2671 unsigned *const_out
, LLVMValueRef
*indir_out
)
2673 unsigned const_offset
= 0;
2674 nir_deref
*tail
= &deref
->deref
;
2675 LLVMValueRef offset
= NULL
;
2677 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2679 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2680 if (vertex_index_out
)
2681 *vertex_index_out
= deref_array
->base_offset
;
2683 if (vertex_index_ref
) {
2684 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2685 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2686 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2688 *vertex_index_ref
= vtx
;
2692 if (deref
->var
->data
.compact
) {
2693 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2694 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2695 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2696 /* We always lower indirect dereferences for "compact" array vars. */
2697 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2699 const_offset
= deref_array
->base_offset
;
2703 while (tail
->child
!= NULL
) {
2704 const struct glsl_type
*parent_type
= tail
->type
;
2707 if (tail
->deref_type
== nir_deref_type_array
) {
2708 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2709 LLVMValueRef index
, stride
, local_offset
;
2710 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2712 const_offset
+= size
* deref_array
->base_offset
;
2713 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2716 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2717 index
= get_src(ctx
, deref_array
->indirect
);
2718 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2719 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2722 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2724 offset
= local_offset
;
2725 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2726 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2728 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2729 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2730 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2733 unreachable("unsupported deref type");
2737 if (const_offset
&& offset
)
2738 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2739 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2742 *const_out
= const_offset
;
2743 *indir_out
= offset
;
2747 /* The offchip buffer layout for TCS->TES is
2749 * - attribute 0 of patch 0 vertex 0
2750 * - attribute 0 of patch 0 vertex 1
2751 * - attribute 0 of patch 0 vertex 2
2753 * - attribute 0 of patch 1 vertex 0
2754 * - attribute 0 of patch 1 vertex 1
2756 * - attribute 1 of patch 0 vertex 0
2757 * - attribute 1 of patch 0 vertex 1
2759 * - per patch attribute 0 of patch 0
2760 * - per patch attribute 0 of patch 1
2763 * Note that every attribute has 4 components.
2765 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2766 LLVMValueRef vertex_index
,
2767 LLVMValueRef param_index
)
2769 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2770 LLVMValueRef param_stride
, constant16
;
2771 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2773 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2774 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2775 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2778 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2780 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2781 vertices_per_patch
, "");
2783 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2786 param_stride
= total_vertices
;
2788 base_addr
= rel_patch_id
;
2789 param_stride
= num_patches
;
2792 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2793 LLVMBuildMul(ctx
->builder
, param_index
,
2794 param_stride
, ""), "");
2796 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2798 if (!vertex_index
) {
2799 LLVMValueRef patch_data_offset
=
2800 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2802 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2803 patch_data_offset
, "");
2808 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2810 unsigned const_index
,
2812 LLVMValueRef vertex_index
,
2813 LLVMValueRef indir_index
)
2815 LLVMValueRef param_index
;
2818 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2821 if (const_index
&& !is_compact
)
2822 param
+= const_index
;
2823 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2825 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2829 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2830 bool is_patch
, uint32_t param
)
2834 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2836 ctx
->tess_outputs_written
|= (1ull << param
);
2840 get_dw_address(struct nir_to_llvm_context
*ctx
,
2841 LLVMValueRef dw_addr
,
2843 unsigned const_index
,
2844 bool compact_const_index
,
2845 LLVMValueRef vertex_index
,
2846 LLVMValueRef stride
,
2847 LLVMValueRef indir_index
)
2852 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2853 LLVMBuildMul(ctx
->builder
,
2859 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2860 LLVMBuildMul(ctx
->builder
, indir_index
,
2861 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2862 else if (const_index
&& !compact_const_index
)
2863 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2864 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2866 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2867 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2869 if (const_index
&& compact_const_index
)
2870 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2871 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2876 load_tcs_varyings(struct ac_shader_abi
*abi
,
2877 LLVMValueRef vertex_index
,
2878 LLVMValueRef indir_index
,
2879 unsigned const_index
,
2881 unsigned driver_location
,
2883 unsigned num_components
,
2888 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2889 LLVMValueRef dw_addr
, stride
;
2890 LLVMValueRef value
[4], result
;
2891 unsigned param
= shader_io_get_unique_index(location
);
2894 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2895 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2898 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2899 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2901 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2906 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2909 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2910 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2911 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2914 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2919 store_tcs_output(struct ac_shader_abi
*abi
,
2920 LLVMValueRef vertex_index
,
2921 LLVMValueRef param_index
,
2922 unsigned const_index
,
2924 unsigned driver_location
,
2931 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2932 LLVMValueRef dw_addr
;
2933 LLVMValueRef stride
= NULL
;
2934 LLVMValueRef buf_addr
= NULL
;
2936 bool store_lds
= true;
2939 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2942 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2946 param
= shader_io_get_unique_index(location
);
2947 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2948 is_compact
&& const_index
> 3) {
2954 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2955 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2957 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2960 mark_tess_output(ctx
, is_patch
, param
);
2962 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2964 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2965 vertex_index
, param_index
);
2967 bool is_tess_factor
= false;
2968 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2969 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2970 is_tess_factor
= true;
2972 unsigned base
= is_compact
? const_index
: 0;
2973 for (unsigned chan
= 0; chan
< 8; chan
++) {
2974 if (!(writemask
& (1 << chan
)))
2976 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2978 if (store_lds
|| is_tess_factor
) {
2979 LLVMValueRef dw_addr_chan
=
2980 LLVMBuildAdd(ctx
->builder
, dw_addr
,
2981 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
2982 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
2985 if (!is_tess_factor
&& writemask
!= 0xF)
2986 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2987 buf_addr
, ctx
->oc_lds
,
2988 4 * (base
+ chan
), 1, 0, true, false);
2991 if (writemask
== 0xF) {
2992 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2993 buf_addr
, ctx
->oc_lds
,
2994 (base
* 4), 1, 0, true, false);
2999 load_tes_input(struct ac_shader_abi
*abi
,
3000 LLVMValueRef vertex_index
,
3001 LLVMValueRef param_index
,
3002 unsigned const_index
,
3004 unsigned driver_location
,
3006 unsigned num_components
,
3011 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3012 LLVMValueRef buf_addr
;
3013 LLVMValueRef result
;
3014 unsigned param
= shader_io_get_unique_index(location
);
3016 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
3021 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
3022 is_compact
, vertex_index
, param_index
);
3024 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
3025 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
3027 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
3028 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
3029 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3034 load_gs_input(struct ac_shader_abi
*abi
,
3036 unsigned driver_location
,
3038 unsigned num_components
,
3039 unsigned vertex_index
,
3040 unsigned const_index
,
3043 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3044 LLVMValueRef vtx_offset
;
3045 unsigned param
, vtx_offset_param
;
3046 LLVMValueRef value
[4], result
;
3048 vtx_offset_param
= vertex_index
;
3049 assert(vtx_offset_param
< 6);
3050 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3051 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3053 param
= shader_io_get_unique_index(location
);
3055 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3056 if (ctx
->ac
.chip_class
>= GFX9
) {
3057 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3058 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3059 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3060 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3062 LLVMValueRef soffset
=
3063 LLVMConstInt(ctx
->ac
.i32
,
3064 (param
* 4 + i
+ const_index
) * 256,
3067 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
3070 vtx_offset
, soffset
,
3071 0, 1, 0, true, false);
3073 value
[i
] = LLVMBuildBitCast(ctx
->builder
, value
[i
],
3077 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3083 build_gep_for_deref(struct ac_nir_context
*ctx
,
3084 nir_deref_var
*deref
)
3086 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3087 assert(entry
->data
);
3088 LLVMValueRef val
= entry
->data
;
3089 nir_deref
*tail
= deref
->deref
.child
;
3090 while (tail
!= NULL
) {
3091 LLVMValueRef offset
;
3092 switch (tail
->deref_type
) {
3093 case nir_deref_type_array
: {
3094 nir_deref_array
*array
= nir_deref_as_array(tail
);
3095 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3096 if (array
->deref_array_type
==
3097 nir_deref_array_type_indirect
) {
3098 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3105 case nir_deref_type_struct
: {
3106 nir_deref_struct
*deref_struct
=
3107 nir_deref_as_struct(tail
);
3108 offset
= LLVMConstInt(ctx
->ac
.i32
,
3109 deref_struct
->index
, 0);
3113 unreachable("bad deref type");
3115 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3121 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3122 nir_intrinsic_instr
*instr
,
3125 LLVMValueRef result
;
3126 LLVMValueRef vertex_index
= NULL
;
3127 LLVMValueRef indir_index
= NULL
;
3128 unsigned const_index
= 0;
3129 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3130 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3131 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3132 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3134 get_deref_offset(ctx
, instr
->variables
[0],
3135 false, NULL
, is_patch
? NULL
: &vertex_index
,
3136 &const_index
, &indir_index
);
3138 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, vertex_index
, indir_index
,
3139 const_index
, location
, driver_location
,
3140 instr
->variables
[0]->var
->data
.location_frac
,
3141 instr
->num_components
,
3142 is_patch
, is_compact
, load_inputs
);
3143 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3146 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3147 nir_intrinsic_instr
*instr
)
3149 LLVMValueRef values
[8];
3150 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3151 int ve
= instr
->dest
.ssa
.num_components
;
3152 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3153 LLVMValueRef indir_index
;
3155 unsigned const_index
;
3156 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3157 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3158 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3159 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3160 &const_index
, &indir_index
);
3162 if (instr
->dest
.ssa
.bit_size
== 64)
3165 switch (instr
->variables
[0]->var
->data
.mode
) {
3166 case nir_var_shader_in
:
3167 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3168 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3169 return load_tess_varyings(ctx
, instr
, true);
3172 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3173 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3174 LLVMValueRef indir_index
;
3175 unsigned const_index
, vertex_index
;
3176 get_deref_offset(ctx
, instr
->variables
[0],
3177 false, &vertex_index
, NULL
,
3178 &const_index
, &indir_index
);
3180 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3181 instr
->variables
[0]->var
->data
.driver_location
,
3182 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3183 vertex_index
, const_index
, type
);
3186 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3188 unsigned count
= glsl_count_attribute_slots(
3189 instr
->variables
[0]->var
->type
,
3190 ctx
->stage
== MESA_SHADER_VERTEX
);
3192 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3193 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3194 stride
, false, true);
3196 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3200 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3204 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3206 unsigned count
= glsl_count_attribute_slots(
3207 instr
->variables
[0]->var
->type
, false);
3209 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3210 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3211 stride
, true, true);
3213 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3217 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3221 case nir_var_shared
: {
3222 LLVMValueRef address
= build_gep_for_deref(ctx
,
3223 instr
->variables
[0]);
3224 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3225 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3226 get_def_type(ctx
, &instr
->dest
.ssa
),
3229 case nir_var_shader_out
:
3230 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3231 return load_tess_varyings(ctx
, instr
, false);
3234 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3236 unsigned count
= glsl_count_attribute_slots(
3237 instr
->variables
[0]->var
->type
, false);
3239 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3240 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3241 stride
, true, true);
3243 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3247 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3248 ctx
->outputs
[idx
+ chan
+ const_index
* stride
],
3254 unreachable("unhandle variable mode");
3256 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3257 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3261 visit_store_var(struct ac_nir_context
*ctx
,
3262 nir_intrinsic_instr
*instr
)
3264 LLVMValueRef temp_ptr
, value
;
3265 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3266 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3267 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3268 int writemask
= instr
->const_index
[0] << comp
;
3269 LLVMValueRef indir_index
;
3270 unsigned const_index
;
3271 get_deref_offset(ctx
, instr
->variables
[0], false,
3272 NULL
, NULL
, &const_index
, &indir_index
);
3274 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3276 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3277 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3280 writemask
= widen_mask(writemask
, 2);
3283 switch (instr
->variables
[0]->var
->data
.mode
) {
3284 case nir_var_shader_out
:
3286 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3287 LLVMValueRef vertex_index
= NULL
;
3288 LLVMValueRef indir_index
= NULL
;
3289 unsigned const_index
= 0;
3290 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3291 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3292 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3293 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3294 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3296 get_deref_offset(ctx
, instr
->variables
[0],
3297 false, NULL
, is_patch
? NULL
: &vertex_index
,
3298 &const_index
, &indir_index
);
3300 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3301 const_index
, location
, driver_location
,
3302 src
, comp
, is_patch
, is_compact
, writemask
);
3306 for (unsigned chan
= 0; chan
< 8; chan
++) {
3308 if (!(writemask
& (1 << chan
)))
3311 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3313 if (instr
->variables
[0]->var
->data
.compact
)
3316 unsigned count
= glsl_count_attribute_slots(
3317 instr
->variables
[0]->var
->type
, false);
3319 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3320 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3321 stride
, true, true);
3323 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3324 value
, indir_index
, "");
3325 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3326 count
, stride
, tmp_vec
);
3329 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3331 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3336 for (unsigned chan
= 0; chan
< 8; chan
++) {
3337 if (!(writemask
& (1 << chan
)))
3340 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3342 unsigned count
= glsl_count_attribute_slots(
3343 instr
->variables
[0]->var
->type
, false);
3345 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3346 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3349 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3350 value
, indir_index
, "");
3351 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3354 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3356 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3360 case nir_var_shared
: {
3361 int writemask
= instr
->const_index
[0];
3362 LLVMValueRef address
= build_gep_for_deref(ctx
,
3363 instr
->variables
[0]);
3364 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3365 unsigned components
=
3366 glsl_get_vector_elements(
3367 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3368 if (writemask
== (1 << components
) - 1) {
3369 val
= LLVMBuildBitCast(
3370 ctx
->ac
.builder
, val
,
3371 LLVMGetElementType(LLVMTypeOf(address
)), "");
3372 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3374 for (unsigned chan
= 0; chan
< 4; chan
++) {
3375 if (!(writemask
& (1 << chan
)))
3378 LLVMBuildStructGEP(ctx
->ac
.builder
,
3380 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3382 src
= LLVMBuildBitCast(
3383 ctx
->ac
.builder
, src
,
3384 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3385 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3395 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3398 case GLSL_SAMPLER_DIM_BUF
:
3400 case GLSL_SAMPLER_DIM_1D
:
3401 return array
? 2 : 1;
3402 case GLSL_SAMPLER_DIM_2D
:
3403 return array
? 3 : 2;
3404 case GLSL_SAMPLER_DIM_MS
:
3405 return array
? 4 : 3;
3406 case GLSL_SAMPLER_DIM_3D
:
3407 case GLSL_SAMPLER_DIM_CUBE
:
3409 case GLSL_SAMPLER_DIM_RECT
:
3410 case GLSL_SAMPLER_DIM_SUBPASS
:
3412 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3422 /* Adjust the sample index according to FMASK.
3424 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3425 * which is the identity mapping. Each nibble says which physical sample
3426 * should be fetched to get that sample.
3428 * For example, 0x11111100 means there are only 2 samples stored and
3429 * the second sample covers 3/4 of the pixel. When reading samples 0
3430 * and 1, return physical sample 0 (determined by the first two 0s
3431 * in FMASK), otherwise return physical sample 1.
3433 * The sample index should be adjusted as follows:
3434 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3436 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3437 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3438 LLVMValueRef coord_z
,
3439 LLVMValueRef sample_index
,
3440 LLVMValueRef fmask_desc_ptr
)
3442 LLVMValueRef fmask_load_address
[4];
3445 fmask_load_address
[0] = coord_x
;
3446 fmask_load_address
[1] = coord_y
;
3448 fmask_load_address
[2] = coord_z
;
3449 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3452 struct ac_image_args args
= {0};
3454 args
.opcode
= ac_image_load
;
3455 args
.da
= coord_z
? true : false;
3456 args
.resource
= fmask_desc_ptr
;
3458 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3460 res
= ac_build_image_opcode(ctx
, &args
);
3462 res
= ac_to_integer(ctx
, res
);
3463 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3464 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3466 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3470 LLVMValueRef sample_index4
=
3471 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3472 LLVMValueRef shifted_fmask
=
3473 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3474 LLVMValueRef final_sample
=
3475 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3477 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3478 * resource descriptor is 0 (invalid),
3480 LLVMValueRef fmask_desc
=
3481 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3484 LLVMValueRef fmask_word1
=
3485 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3488 LLVMValueRef word1_is_nonzero
=
3489 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3490 fmask_word1
, ctx
->i32_0
, "");
3492 /* Replace the MSAA sample index. */
3494 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3495 final_sample
, sample_index
, "");
3496 return sample_index
;
3499 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3500 const nir_intrinsic_instr
*instr
)
3502 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3504 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3505 LLVMValueRef coords
[4];
3506 LLVMValueRef masks
[] = {
3507 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3508 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3511 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3514 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3515 bool is_array
= glsl_sampler_type_is_array(type
);
3516 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3517 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3518 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3519 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3520 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3521 count
= image_type_to_components_count(dim
, is_array
);
3524 LLVMValueRef fmask_load_address
[3];
3527 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3528 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3530 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3532 fmask_load_address
[2] = NULL
;
3534 for (chan
= 0; chan
< 2; ++chan
)
3535 fmask_load_address
[chan
] =
3536 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3537 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3538 ctx
->ac
.i32
, ""), "");
3539 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3541 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3542 fmask_load_address
[0],
3543 fmask_load_address
[1],
3544 fmask_load_address
[2],
3546 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3548 if (count
== 1 && !gfx9_1d
) {
3549 if (instr
->src
[0].ssa
->num_components
)
3550 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3557 for (chan
= 0; chan
< count
; ++chan
) {
3558 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3561 for (chan
= 0; chan
< 2; ++chan
)
3562 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3563 ctx
->ac
.i32
, ""), "");
3564 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3570 coords
[2] = coords
[1];
3571 coords
[1] = ctx
->ac
.i32_0
;
3573 coords
[1] = ctx
->ac
.i32_0
;
3578 coords
[count
] = sample_index
;
3583 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3586 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3591 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3592 const nir_intrinsic_instr
*instr
)
3594 LLVMValueRef params
[7];
3596 char intrinsic_name
[64];
3597 const nir_variable
*var
= instr
->variables
[0]->var
;
3598 const struct glsl_type
*type
= var
->type
;
3600 if(instr
->variables
[0]->deref
.child
)
3601 type
= instr
->variables
[0]->deref
.child
->type
;
3603 type
= glsl_without_array(type
);
3605 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3606 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3607 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
3608 unsigned num_channels
= util_last_bit(mask
);
3609 LLVMValueRef rsrc
, vindex
;
3611 rsrc
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3612 vindex
= LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3615 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3616 res
= ac_build_buffer_load_format(&ctx
->ac
, rsrc
, vindex
,
3617 ctx
->ac
.i32_0
, num_channels
,
3619 res
= ac_build_expand_to_vec4(&ctx
->ac
, res
, num_channels
);
3621 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3622 res
= ac_to_integer(&ctx
->ac
, res
);
3624 bool is_da
= glsl_sampler_type_is_array(type
) ||
3625 dim
== GLSL_SAMPLER_DIM_CUBE
||
3626 dim
== GLSL_SAMPLER_DIM_3D
||
3627 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3628 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3629 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3630 LLVMValueRef glc
= ctx
->ac
.i1false
;
3631 LLVMValueRef slc
= ctx
->ac
.i1false
;
3633 params
[0] = get_image_coords(ctx
, instr
);
3634 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3635 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3638 params
[5] = ctx
->ac
.i1false
;
3641 ac_get_image_intr_name("llvm.amdgcn.image.load",
3642 ctx
->ac
.v4f32
, /* vdata */
3643 LLVMTypeOf(params
[0]), /* coords */
3644 LLVMTypeOf(params
[1]), /* rsrc */
3645 intrinsic_name
, sizeof(intrinsic_name
));
3647 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3648 params
, 7, AC_FUNC_ATTR_READONLY
);
3650 return ac_to_integer(&ctx
->ac
, res
);
3653 static void visit_image_store(struct ac_nir_context
*ctx
,
3654 nir_intrinsic_instr
*instr
)
3656 LLVMValueRef params
[8];
3657 char intrinsic_name
[64];
3658 const nir_variable
*var
= instr
->variables
[0]->var
;
3659 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3660 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3661 LLVMValueRef glc
= ctx
->ac
.i1false
;
3662 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3664 glc
= ctx
->ac
.i1true
;
3666 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3667 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3668 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3669 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3670 ctx
->ac
.i32_0
, ""); /* vindex */
3671 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3672 params
[4] = glc
; /* glc */
3673 params
[5] = ctx
->ac
.i1false
; /* slc */
3674 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3677 bool is_da
= glsl_sampler_type_is_array(type
) ||
3678 dim
== GLSL_SAMPLER_DIM_CUBE
||
3679 dim
== GLSL_SAMPLER_DIM_3D
;
3680 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3681 LLVMValueRef slc
= ctx
->ac
.i1false
;
3683 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3684 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3685 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3686 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3689 params
[6] = ctx
->ac
.i1false
;
3692 ac_get_image_intr_name("llvm.amdgcn.image.store",
3693 LLVMTypeOf(params
[0]), /* vdata */
3694 LLVMTypeOf(params
[1]), /* coords */
3695 LLVMTypeOf(params
[2]), /* rsrc */
3696 intrinsic_name
, sizeof(intrinsic_name
));
3698 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3704 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3705 const nir_intrinsic_instr
*instr
)
3707 LLVMValueRef params
[7];
3708 int param_count
= 0;
3709 const nir_variable
*var
= instr
->variables
[0]->var
;
3711 const char *atomic_name
;
3712 char intrinsic_name
[41];
3713 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3714 MAYBE_UNUSED
int length
;
3716 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3718 switch (instr
->intrinsic
) {
3719 case nir_intrinsic_image_atomic_add
:
3720 atomic_name
= "add";
3722 case nir_intrinsic_image_atomic_min
:
3723 atomic_name
= is_unsigned
? "umin" : "smin";
3725 case nir_intrinsic_image_atomic_max
:
3726 atomic_name
= is_unsigned
? "umax" : "smax";
3728 case nir_intrinsic_image_atomic_and
:
3729 atomic_name
= "and";
3731 case nir_intrinsic_image_atomic_or
:
3734 case nir_intrinsic_image_atomic_xor
:
3735 atomic_name
= "xor";
3737 case nir_intrinsic_image_atomic_exchange
:
3738 atomic_name
= "swap";
3740 case nir_intrinsic_image_atomic_comp_swap
:
3741 atomic_name
= "cmpswap";
3747 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3748 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3749 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3751 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3752 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3754 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3755 ctx
->ac
.i32_0
, ""); /* vindex */
3756 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3757 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3759 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3760 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3762 char coords_type
[8];
3764 bool da
= glsl_sampler_type_is_array(type
) ||
3765 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3767 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3768 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3770 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3771 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3772 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3774 build_int_type_name(LLVMTypeOf(coords
),
3775 coords_type
, sizeof(coords_type
));
3777 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3778 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3781 assert(length
< sizeof(intrinsic_name
));
3782 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3785 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3786 const nir_intrinsic_instr
*instr
)
3789 const nir_variable
*var
= instr
->variables
[0]->var
;
3790 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3791 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3792 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
||
3793 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_3D
;
3794 if(instr
->variables
[0]->deref
.child
)
3795 type
= instr
->variables
[0]->deref
.child
->type
;
3797 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3798 return get_buffer_size(ctx
,
3799 get_sampler_desc(ctx
, instr
->variables
[0],
3800 AC_DESC_BUFFER
, NULL
, true, false), true);
3802 struct ac_image_args args
= { 0 };
3806 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3807 args
.opcode
= ac_image_get_resinfo
;
3808 args
.addr
= ctx
->ac
.i32_0
;
3810 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3812 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3814 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3815 glsl_sampler_type_is_array(type
)) {
3816 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3817 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3818 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3819 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3821 if (ctx
->ac
.chip_class
>= GFX9
&&
3822 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3823 glsl_sampler_type_is_array(type
)) {
3824 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3825 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3832 #define NOOP_WAITCNT 0xf7f
3833 #define LGKM_CNT 0x07f
3834 #define VM_CNT 0xf70
3836 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3837 const nir_intrinsic_instr
*instr
)
3839 unsigned waitcnt
= NOOP_WAITCNT
;
3841 switch (instr
->intrinsic
) {
3842 case nir_intrinsic_memory_barrier
:
3843 case nir_intrinsic_group_memory_barrier
:
3844 waitcnt
&= VM_CNT
& LGKM_CNT
;
3846 case nir_intrinsic_memory_barrier_atomic_counter
:
3847 case nir_intrinsic_memory_barrier_buffer
:
3848 case nir_intrinsic_memory_barrier_image
:
3851 case nir_intrinsic_memory_barrier_shared
:
3852 waitcnt
&= LGKM_CNT
;
3857 if (waitcnt
!= NOOP_WAITCNT
)
3858 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3861 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3863 /* SI only (thanks to a hw bug workaround):
3864 * The real barrier instruction isn’t needed, because an entire patch
3865 * always fits into a single wave.
3867 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3868 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3871 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3872 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3875 static void emit_discard(struct ac_nir_context
*ctx
,
3876 const nir_intrinsic_instr
*instr
)
3880 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3881 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3882 get_src(ctx
, instr
->src
[0]),
3885 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3886 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3889 ac_build_kill_if_false(&ctx
->ac
, cond
);
3893 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3895 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3896 "llvm.amdgcn.ps.live",
3897 ctx
->ac
.i1
, NULL
, 0,
3898 AC_FUNC_ATTR_READNONE
);
3899 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3900 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3904 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3906 LLVMValueRef result
;
3907 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3908 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3909 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3911 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3914 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3915 const nir_intrinsic_instr
*instr
)
3917 LLVMValueRef ptr
, result
;
3918 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3919 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3921 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3922 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3923 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3925 LLVMAtomicOrderingSequentiallyConsistent
,
3926 LLVMAtomicOrderingSequentiallyConsistent
,
3929 LLVMAtomicRMWBinOp op
;
3930 switch (instr
->intrinsic
) {
3931 case nir_intrinsic_var_atomic_add
:
3932 op
= LLVMAtomicRMWBinOpAdd
;
3934 case nir_intrinsic_var_atomic_umin
:
3935 op
= LLVMAtomicRMWBinOpUMin
;
3937 case nir_intrinsic_var_atomic_umax
:
3938 op
= LLVMAtomicRMWBinOpUMax
;
3940 case nir_intrinsic_var_atomic_imin
:
3941 op
= LLVMAtomicRMWBinOpMin
;
3943 case nir_intrinsic_var_atomic_imax
:
3944 op
= LLVMAtomicRMWBinOpMax
;
3946 case nir_intrinsic_var_atomic_and
:
3947 op
= LLVMAtomicRMWBinOpAnd
;
3949 case nir_intrinsic_var_atomic_or
:
3950 op
= LLVMAtomicRMWBinOpOr
;
3952 case nir_intrinsic_var_atomic_xor
:
3953 op
= LLVMAtomicRMWBinOpXor
;
3955 case nir_intrinsic_var_atomic_exchange
:
3956 op
= LLVMAtomicRMWBinOpXchg
;
3962 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3963 LLVMAtomicOrderingSequentiallyConsistent
,
3969 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
3970 enum glsl_interp_mode interp
, unsigned location
)
3972 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3975 case INTERP_MODE_FLAT
:
3978 case INTERP_MODE_SMOOTH
:
3979 case INTERP_MODE_NONE
:
3980 if (location
== INTERP_CENTER
)
3981 return ctx
->persp_center
;
3982 else if (location
== INTERP_CENTROID
)
3983 return ctx
->persp_centroid
;
3984 else if (location
== INTERP_SAMPLE
)
3985 return ctx
->persp_sample
;
3987 case INTERP_MODE_NOPERSPECTIVE
:
3988 if (location
== INTERP_CENTER
)
3989 return ctx
->linear_center
;
3990 else if (location
== INTERP_CENTROID
)
3991 return ctx
->linear_centroid
;
3992 else if (location
== INTERP_SAMPLE
)
3993 return ctx
->linear_sample
;
3999 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
4000 LLVMValueRef sample_id
)
4002 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4004 LLVMValueRef result
;
4005 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4007 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
4008 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4010 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
4011 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4016 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4018 LLVMValueRef values
[2];
4020 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0], 32);
4021 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1], 32);
4022 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4025 static LLVMValueRef
load_sample_mask_in(struct ac_nir_context
*ctx
)
4027 uint8_t log2_ps_iter_samples
= ctx
->nctx
->shader_info
->info
.ps
.force_persample
? ctx
->nctx
->options
->key
.fs
.log2_num_samples
: ctx
->nctx
->options
->key
.fs
.log2_ps_iter_samples
;
4029 /* The bit pattern matches that used by fixed function fragment
4031 static const uint16_t ps_iter_masks
[] = {
4032 0xffff, /* not used */
4038 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4040 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4042 LLVMValueRef result
, sample_id
;
4043 sample_id
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4044 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4045 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, ctx
->abi
->sample_coverage
, "");
4049 static LLVMValueRef
visit_interp(struct ac_nir_context
*ctx
,
4050 const nir_intrinsic_instr
*instr
)
4052 LLVMValueRef result
[4];
4053 LLVMValueRef interp_param
, attr_number
;
4056 LLVMValueRef src_c0
= NULL
;
4057 LLVMValueRef src_c1
= NULL
;
4058 LLVMValueRef src0
= NULL
;
4059 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4060 switch (instr
->intrinsic
) {
4061 case nir_intrinsic_interp_var_at_centroid
:
4062 location
= INTERP_CENTROID
;
4064 case nir_intrinsic_interp_var_at_sample
:
4065 case nir_intrinsic_interp_var_at_offset
:
4066 location
= INTERP_CENTER
;
4067 src0
= get_src(ctx
, instr
->src
[0]);
4073 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4074 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_0
, ""));
4075 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_1
, ""));
4076 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4077 LLVMValueRef sample_position
;
4078 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4080 /* fetch sample ID */
4081 sample_position
= ctx
->abi
->load_sample_position(ctx
->abi
, src0
);
4083 src_c0
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_0
, "");
4084 src_c0
= LLVMBuildFSub(ctx
->ac
.builder
, src_c0
, halfval
, "");
4085 src_c1
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_1
, "");
4086 src_c1
= LLVMBuildFSub(ctx
->ac
.builder
, src_c1
, halfval
, "");
4088 interp_param
= ctx
->abi
->lookup_interp_param(ctx
->abi
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4089 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4091 if (location
== INTERP_CENTER
) {
4092 LLVMValueRef ij_out
[2];
4093 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
4096 * take the I then J parameters, and the DDX/Y for it, and
4097 * calculate the IJ inputs for the interpolator.
4098 * temp1 = ddx * offset/sample.x + I;
4099 * interp_param.I = ddy * offset/sample.y + temp1;
4100 * temp1 = ddx * offset/sample.x + J;
4101 * interp_param.J = ddy * offset/sample.y + temp1;
4103 for (unsigned i
= 0; i
< 2; i
++) {
4104 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4105 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4106 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4107 ddxy_out
, ix_ll
, "");
4108 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4109 ddxy_out
, iy_ll
, "");
4110 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4111 interp_param
, ix_ll
, "");
4112 LLVMValueRef temp1
, temp2
;
4114 interp_el
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_el
,
4117 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, src_c0
, "");
4118 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4120 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, src_c1
, "");
4121 temp2
= LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4123 ij_out
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4124 temp2
, ctx
->ac
.i32
, "");
4126 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4130 for (chan
= 0; chan
< 4; chan
++) {
4131 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4134 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
,
4135 interp_param
, ctx
->ac
.v2f32
, "");
4136 LLVMValueRef i
= LLVMBuildExtractElement(
4137 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_0
, "");
4138 LLVMValueRef j
= LLVMBuildExtractElement(
4139 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_1
, "");
4141 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4142 llvm_chan
, attr_number
,
4143 ctx
->abi
->prim_mask
, i
, j
);
4145 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4146 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4147 llvm_chan
, attr_number
,
4148 ctx
->abi
->prim_mask
);
4151 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4152 instr
->variables
[0]->var
->data
.location_frac
);
4156 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4158 LLVMValueRef gs_next_vertex
;
4159 LLVMValueRef can_emit
;
4161 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4163 assert(stream
== 0);
4165 /* Write vertex attribute values to GSVS ring */
4166 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4167 ctx
->gs_next_vertex
,
4170 /* If this thread has already emitted the declared maximum number of
4171 * vertices, kill it: excessive vertex emissions are not supposed to
4172 * have any effect, and GS threads have no externally observable
4173 * effects other than emitting vertices.
4175 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4176 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4177 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4179 /* loop num outputs */
4181 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4182 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4187 if (!(ctx
->output_mask
& (1ull << i
)))
4190 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4191 /* pack clip and cull into a single set of slots */
4192 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4196 for (unsigned j
= 0; j
< length
; j
++) {
4197 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4199 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4200 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4201 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4203 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4205 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4207 voffset
, ctx
->gs2vs_offset
, 0,
4213 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4215 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4217 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4221 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4223 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4224 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4228 load_tess_coord(struct ac_shader_abi
*abi
, LLVMTypeRef type
,
4229 unsigned num_components
)
4231 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4233 LLVMValueRef coord
[4] = {
4240 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4241 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4242 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4244 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, num_components
);
4245 return LLVMBuildBitCast(ctx
->builder
, result
, type
, "");
4249 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4251 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4252 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4255 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4256 nir_intrinsic_instr
*instr
)
4258 LLVMValueRef result
= NULL
;
4260 switch (instr
->intrinsic
) {
4261 case nir_intrinsic_ballot
:
4262 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4264 case nir_intrinsic_read_invocation
:
4265 case nir_intrinsic_read_first_invocation
: {
4266 LLVMValueRef args
[2];
4269 args
[0] = get_src(ctx
, instr
->src
[0]);
4272 const char *intr_name
;
4273 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4275 intr_name
= "llvm.amdgcn.readlane";
4278 args
[1] = get_src(ctx
, instr
->src
[1]);
4281 intr_name
= "llvm.amdgcn.readfirstlane";
4284 /* We currently have no other way to prevent LLVM from lifting the icmp
4285 * calls to a dominating basic block.
4287 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4289 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4290 ctx
->ac
.i32
, args
, num_args
,
4291 AC_FUNC_ATTR_READNONE
|
4292 AC_FUNC_ATTR_CONVERGENT
);
4295 case nir_intrinsic_load_subgroup_invocation
:
4296 result
= ac_get_thread_id(&ctx
->ac
);
4298 case nir_intrinsic_load_work_group_id
: {
4299 LLVMValueRef values
[3];
4301 for (int i
= 0; i
< 3; i
++) {
4302 values
[i
] = ctx
->nctx
->workgroup_ids
[i
] ?
4303 ctx
->nctx
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4306 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4309 case nir_intrinsic_load_base_vertex
: {
4310 result
= ctx
->abi
->base_vertex
;
4313 case nir_intrinsic_load_vertex_id_zero_base
: {
4314 result
= ctx
->abi
->vertex_id
;
4317 case nir_intrinsic_load_local_invocation_id
: {
4318 result
= ctx
->nctx
->local_invocation_ids
;
4321 case nir_intrinsic_load_base_instance
:
4322 result
= ctx
->abi
->start_instance
;
4324 case nir_intrinsic_load_draw_id
:
4325 result
= ctx
->abi
->draw_id
;
4327 case nir_intrinsic_load_view_index
:
4328 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4330 case nir_intrinsic_load_invocation_id
:
4331 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4332 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4334 result
= ctx
->abi
->gs_invocation_id
;
4336 case nir_intrinsic_load_primitive_id
:
4337 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4338 result
= ctx
->abi
->gs_prim_id
;
4339 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4340 result
= ctx
->abi
->tcs_patch_id
;
4341 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4342 result
= ctx
->abi
->tes_patch_id
;
4344 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4346 case nir_intrinsic_load_sample_id
:
4347 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4349 case nir_intrinsic_load_sample_pos
:
4350 result
= load_sample_pos(ctx
);
4352 case nir_intrinsic_load_sample_mask_in
:
4354 result
= load_sample_mask_in(ctx
);
4356 result
= ctx
->abi
->sample_coverage
;
4358 case nir_intrinsic_load_frag_coord
: {
4359 LLVMValueRef values
[4] = {
4360 ctx
->abi
->frag_pos
[0],
4361 ctx
->abi
->frag_pos
[1],
4362 ctx
->abi
->frag_pos
[2],
4363 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4365 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4368 case nir_intrinsic_load_front_face
:
4369 result
= ctx
->abi
->front_face
;
4371 case nir_intrinsic_load_helper_invocation
:
4372 result
= visit_load_helper_invocation(ctx
);
4374 case nir_intrinsic_load_instance_id
:
4375 result
= ctx
->abi
->instance_id
;
4377 case nir_intrinsic_load_num_work_groups
:
4378 result
= ctx
->nctx
->num_work_groups
;
4380 case nir_intrinsic_load_local_invocation_index
:
4381 result
= visit_load_local_invocation_index(ctx
->nctx
);
4383 case nir_intrinsic_load_push_constant
:
4384 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4386 case nir_intrinsic_vulkan_resource_index
:
4387 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4389 case nir_intrinsic_vulkan_resource_reindex
:
4390 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4392 case nir_intrinsic_store_ssbo
:
4393 visit_store_ssbo(ctx
, instr
);
4395 case nir_intrinsic_load_ssbo
:
4396 result
= visit_load_buffer(ctx
, instr
);
4398 case nir_intrinsic_ssbo_atomic_add
:
4399 case nir_intrinsic_ssbo_atomic_imin
:
4400 case nir_intrinsic_ssbo_atomic_umin
:
4401 case nir_intrinsic_ssbo_atomic_imax
:
4402 case nir_intrinsic_ssbo_atomic_umax
:
4403 case nir_intrinsic_ssbo_atomic_and
:
4404 case nir_intrinsic_ssbo_atomic_or
:
4405 case nir_intrinsic_ssbo_atomic_xor
:
4406 case nir_intrinsic_ssbo_atomic_exchange
:
4407 case nir_intrinsic_ssbo_atomic_comp_swap
:
4408 result
= visit_atomic_ssbo(ctx
, instr
);
4410 case nir_intrinsic_load_ubo
:
4411 result
= visit_load_ubo_buffer(ctx
, instr
);
4413 case nir_intrinsic_get_buffer_size
:
4414 result
= visit_get_buffer_size(ctx
, instr
);
4416 case nir_intrinsic_load_var
:
4417 result
= visit_load_var(ctx
, instr
);
4419 case nir_intrinsic_store_var
:
4420 visit_store_var(ctx
, instr
);
4422 case nir_intrinsic_image_load
:
4423 result
= visit_image_load(ctx
, instr
);
4425 case nir_intrinsic_image_store
:
4426 visit_image_store(ctx
, instr
);
4428 case nir_intrinsic_image_atomic_add
:
4429 case nir_intrinsic_image_atomic_min
:
4430 case nir_intrinsic_image_atomic_max
:
4431 case nir_intrinsic_image_atomic_and
:
4432 case nir_intrinsic_image_atomic_or
:
4433 case nir_intrinsic_image_atomic_xor
:
4434 case nir_intrinsic_image_atomic_exchange
:
4435 case nir_intrinsic_image_atomic_comp_swap
:
4436 result
= visit_image_atomic(ctx
, instr
);
4438 case nir_intrinsic_image_size
:
4439 result
= visit_image_size(ctx
, instr
);
4441 case nir_intrinsic_discard
:
4442 case nir_intrinsic_discard_if
:
4443 emit_discard(ctx
, instr
);
4445 case nir_intrinsic_memory_barrier
:
4446 case nir_intrinsic_group_memory_barrier
:
4447 case nir_intrinsic_memory_barrier_atomic_counter
:
4448 case nir_intrinsic_memory_barrier_buffer
:
4449 case nir_intrinsic_memory_barrier_image
:
4450 case nir_intrinsic_memory_barrier_shared
:
4451 emit_membar(ctx
->nctx
, instr
);
4453 case nir_intrinsic_barrier
:
4454 emit_barrier(&ctx
->ac
, ctx
->stage
);
4456 case nir_intrinsic_var_atomic_add
:
4457 case nir_intrinsic_var_atomic_imin
:
4458 case nir_intrinsic_var_atomic_umin
:
4459 case nir_intrinsic_var_atomic_imax
:
4460 case nir_intrinsic_var_atomic_umax
:
4461 case nir_intrinsic_var_atomic_and
:
4462 case nir_intrinsic_var_atomic_or
:
4463 case nir_intrinsic_var_atomic_xor
:
4464 case nir_intrinsic_var_atomic_exchange
:
4465 case nir_intrinsic_var_atomic_comp_swap
:
4466 result
= visit_var_atomic(ctx
->nctx
, instr
);
4468 case nir_intrinsic_interp_var_at_centroid
:
4469 case nir_intrinsic_interp_var_at_sample
:
4470 case nir_intrinsic_interp_var_at_offset
:
4471 result
= visit_interp(ctx
, instr
);
4473 case nir_intrinsic_emit_vertex
:
4474 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->outputs
);
4476 case nir_intrinsic_end_primitive
:
4477 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4479 case nir_intrinsic_load_tess_coord
: {
4480 LLVMTypeRef type
= ctx
->nctx
?
4481 get_def_type(ctx
->nctx
->nir
, &instr
->dest
.ssa
) :
4483 result
= ctx
->abi
->load_tess_coord(ctx
->abi
, type
, instr
->num_components
);
4486 case nir_intrinsic_load_tess_level_outer
:
4487 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4489 case nir_intrinsic_load_tess_level_inner
:
4490 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4492 case nir_intrinsic_load_patch_vertices_in
:
4493 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4495 case nir_intrinsic_vote_all
: {
4496 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4497 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4500 case nir_intrinsic_vote_any
: {
4501 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4502 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4505 case nir_intrinsic_vote_eq
: {
4506 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4507 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4511 fprintf(stderr
, "Unknown intrinsic: ");
4512 nir_print_instr(&instr
->instr
, stderr
);
4513 fprintf(stderr
, "\n");
4517 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4521 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4522 LLVMValueRef buffer_ptr
, bool write
)
4524 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4525 LLVMValueRef result
;
4527 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4529 result
= LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4530 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4535 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4537 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4538 LLVMValueRef result
;
4540 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4542 result
= LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4543 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4548 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4549 unsigned descriptor_set
,
4550 unsigned base_index
,
4551 unsigned constant_index
,
4553 enum ac_descriptor_type desc_type
,
4554 bool image
, bool write
)
4556 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4557 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4558 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4559 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4560 unsigned offset
= binding
->offset
;
4561 unsigned stride
= binding
->size
;
4563 LLVMBuilderRef builder
= ctx
->builder
;
4566 assert(base_index
< layout
->binding_count
);
4568 switch (desc_type
) {
4570 type
= ctx
->ac
.v8i32
;
4574 type
= ctx
->ac
.v8i32
;
4578 case AC_DESC_SAMPLER
:
4579 type
= ctx
->ac
.v4i32
;
4580 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4585 case AC_DESC_BUFFER
:
4586 type
= ctx
->ac
.v4i32
;
4590 unreachable("invalid desc_type\n");
4593 offset
+= constant_index
* stride
;
4595 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4596 (!index
|| binding
->immutable_samplers_equal
)) {
4597 if (binding
->immutable_samplers_equal
)
4600 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4602 LLVMValueRef constants
[] = {
4603 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4604 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4605 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4606 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4608 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4611 assert(stride
% type_size
== 0);
4614 index
= ctx
->ac
.i32_0
;
4616 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4618 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4619 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4621 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4624 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4625 const nir_deref_var
*deref
,
4626 enum ac_descriptor_type desc_type
,
4627 const nir_tex_instr
*tex_instr
,
4628 bool image
, bool write
)
4630 LLVMValueRef index
= NULL
;
4631 unsigned constant_index
= 0;
4632 unsigned descriptor_set
;
4633 unsigned base_index
;
4636 assert(tex_instr
&& !image
);
4638 base_index
= tex_instr
->sampler_index
;
4640 const nir_deref
*tail
= &deref
->deref
;
4641 while (tail
->child
) {
4642 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4643 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4648 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4650 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4651 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4653 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4654 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4659 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4662 constant_index
+= child
->base_offset
* array_size
;
4664 tail
= &child
->deref
;
4666 descriptor_set
= deref
->var
->data
.descriptor_set
;
4667 base_index
= deref
->var
->data
.binding
;
4670 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4673 constant_index
, index
,
4674 desc_type
, image
, write
);
4677 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4678 struct ac_image_args
*args
,
4679 const nir_tex_instr
*instr
,
4681 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4682 LLVMValueRef
*param
, unsigned count
,
4685 unsigned is_rect
= 0;
4686 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4688 if (op
== nir_texop_lod
)
4690 /* Pad to power of two vector */
4691 while (count
< util_next_power_of_two(count
))
4692 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4695 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4697 args
->addr
= param
[0];
4699 args
->resource
= res_ptr
;
4700 args
->sampler
= samp_ptr
;
4702 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4703 args
->addr
= param
[0];
4707 args
->dmask
= dmask
;
4708 args
->unorm
= is_rect
;
4712 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4715 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4716 * filtering manually. The driver sets img7 to a mask clearing
4717 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4718 * s_and_b32 samp0, samp0, img7
4721 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4723 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4724 LLVMValueRef res
, LLVMValueRef samp
)
4726 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4727 LLVMValueRef img7
, samp0
;
4729 if (ctx
->ac
.chip_class
>= VI
)
4732 img7
= LLVMBuildExtractElement(builder
, res
,
4733 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4734 samp0
= LLVMBuildExtractElement(builder
, samp
,
4735 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4736 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4737 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4738 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4741 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4742 nir_tex_instr
*instr
,
4743 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4744 LLVMValueRef
*fmask_ptr
)
4746 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4747 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4749 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4752 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4754 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4755 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4756 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4758 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4759 instr
->op
== nir_texop_samples_identical
))
4760 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4763 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4766 coord
= ac_to_float(ctx
, coord
);
4767 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4768 coord
= ac_to_integer(ctx
, coord
);
4772 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4774 LLVMValueRef result
= NULL
;
4775 struct ac_image_args args
= { 0 };
4776 unsigned dmask
= 0xf;
4777 LLVMValueRef address
[16];
4778 LLVMValueRef coords
[5];
4779 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4780 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4781 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4782 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4783 LLVMValueRef derivs
[6];
4784 unsigned chan
, count
= 0;
4785 unsigned const_src
= 0, num_deriv_comp
= 0;
4786 bool lod_is_zero
= false;
4788 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4790 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4791 switch (instr
->src
[i
].src_type
) {
4792 case nir_tex_src_coord
:
4793 coord
= get_src(ctx
, instr
->src
[i
].src
);
4795 case nir_tex_src_projector
:
4797 case nir_tex_src_comparator
:
4798 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4800 case nir_tex_src_offset
:
4801 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4804 case nir_tex_src_bias
:
4805 bias
= get_src(ctx
, instr
->src
[i
].src
);
4807 case nir_tex_src_lod
: {
4808 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4810 if (val
&& val
->i32
[0] == 0)
4812 lod
= get_src(ctx
, instr
->src
[i
].src
);
4815 case nir_tex_src_ms_index
:
4816 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4818 case nir_tex_src_ms_mcs
:
4820 case nir_tex_src_ddx
:
4821 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4822 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4824 case nir_tex_src_ddy
:
4825 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4827 case nir_tex_src_texture_offset
:
4828 case nir_tex_src_sampler_offset
:
4829 case nir_tex_src_plane
:
4835 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4836 result
= get_buffer_size(ctx
, res_ptr
, true);
4840 if (instr
->op
== nir_texop_texture_samples
) {
4841 LLVMValueRef res
, samples
, is_msaa
;
4842 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4843 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4844 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4845 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4846 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4847 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4848 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4849 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4850 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4852 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4853 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4854 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4855 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4856 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4858 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4865 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4866 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4868 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4869 LLVMValueRef offset
[3], pack
;
4870 for (chan
= 0; chan
< 3; ++chan
)
4871 offset
[chan
] = ctx
->ac
.i32_0
;
4874 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4875 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4876 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4877 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4879 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4880 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4882 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4883 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4884 address
[count
++] = pack
;
4887 /* pack LOD bias value */
4888 if (instr
->op
== nir_texop_txb
&& bias
) {
4889 address
[count
++] = bias
;
4892 /* Pack depth comparison value */
4893 if (instr
->is_shadow
&& comparator
) {
4894 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4895 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4897 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4898 * so the depth comparison value isn't clamped for Z16 and
4899 * Z24 anymore. Do it manually here.
4901 * It's unnecessary if the original texture format was
4902 * Z32_FLOAT, but we don't know that here.
4904 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4905 z
= ac_build_clamp(&ctx
->ac
, z
);
4907 address
[count
++] = z
;
4910 /* pack derivatives */
4912 int num_src_deriv_channels
, num_dest_deriv_channels
;
4913 switch (instr
->sampler_dim
) {
4914 case GLSL_SAMPLER_DIM_3D
:
4915 case GLSL_SAMPLER_DIM_CUBE
:
4917 num_src_deriv_channels
= 3;
4918 num_dest_deriv_channels
= 3;
4920 case GLSL_SAMPLER_DIM_2D
:
4922 num_src_deriv_channels
= 2;
4923 num_dest_deriv_channels
= 2;
4926 case GLSL_SAMPLER_DIM_1D
:
4927 num_src_deriv_channels
= 1;
4928 if (ctx
->ac
.chip_class
>= GFX9
) {
4929 num_dest_deriv_channels
= 2;
4932 num_dest_deriv_channels
= 1;
4938 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4939 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4940 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4942 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4943 derivs
[i
] = ctx
->ac
.f32_0
;
4944 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4948 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4949 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4950 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4951 if (instr
->coord_components
== 3)
4952 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4953 ac_prepare_cube_coords(&ctx
->ac
,
4954 instr
->op
== nir_texop_txd
, instr
->is_array
,
4955 instr
->op
== nir_texop_lod
, coords
, derivs
);
4961 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4962 address
[count
++] = derivs
[i
];
4965 /* Pack texture coordinates */
4967 address
[count
++] = coords
[0];
4968 if (instr
->coord_components
> 1) {
4969 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4970 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4972 address
[count
++] = coords
[1];
4974 if (instr
->coord_components
> 2) {
4975 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4976 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4977 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4978 instr
->op
!= nir_texop_txf
) {
4979 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4981 address
[count
++] = coords
[2];
4984 if (ctx
->ac
.chip_class
>= GFX9
) {
4985 LLVMValueRef filler
;
4986 if (instr
->op
== nir_texop_txf
)
4987 filler
= ctx
->ac
.i32_0
;
4989 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4991 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4992 /* No nir_texop_lod, because it does not take a slice
4993 * even with array textures. */
4994 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4995 address
[count
] = address
[count
- 1];
4996 address
[count
- 1] = filler
;
4999 address
[count
++] = filler
;
5005 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
5006 instr
->op
== nir_texop_txf
)) {
5007 address
[count
++] = lod
;
5008 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5009 address
[count
++] = sample_index
;
5010 } else if(instr
->op
== nir_texop_txs
) {
5013 address
[count
++] = lod
;
5015 address
[count
++] = ctx
->ac
.i32_0
;
5018 for (chan
= 0; chan
< count
; chan
++) {
5019 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5020 address
[chan
], ctx
->ac
.i32
, "");
5023 if (instr
->op
== nir_texop_samples_identical
) {
5024 LLVMValueRef txf_address
[4];
5025 struct ac_image_args txf_args
= { 0 };
5026 unsigned txf_count
= count
;
5027 memcpy(txf_address
, address
, sizeof(txf_address
));
5029 if (!instr
->is_array
)
5030 txf_address
[2] = ctx
->ac
.i32_0
;
5031 txf_address
[3] = ctx
->ac
.i32_0
;
5033 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5035 txf_address
, txf_count
, 0xf);
5037 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5039 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5040 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5044 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5045 instr
->op
!= nir_texop_txs
) {
5046 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5047 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5050 instr
->is_array
? address
[2] : NULL
,
5051 address
[sample_chan
],
5055 if (offsets
&& instr
->op
== nir_texop_txf
) {
5056 nir_const_value
*const_offset
=
5057 nir_src_as_const_value(instr
->src
[const_src
].src
);
5058 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5059 assert(const_offset
);
5060 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5061 if (num_offsets
> 2)
5062 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5063 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5064 if (num_offsets
> 1)
5065 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5066 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5067 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5068 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5072 /* TODO TG4 support */
5073 if (instr
->op
== nir_texop_tg4
) {
5074 if (instr
->is_shadow
)
5077 dmask
= 1 << instr
->component
;
5079 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5080 res_ptr
, samp_ptr
, address
, count
, dmask
);
5082 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5084 if (instr
->op
== nir_texop_query_levels
)
5085 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5086 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5087 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5088 instr
->op
!= nir_texop_tg4
)
5089 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5090 else if (instr
->op
== nir_texop_txs
&&
5091 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5093 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5094 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5095 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5096 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5097 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5098 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5099 instr
->op
== nir_texop_txs
&&
5100 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5102 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5103 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5104 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5106 } else if (instr
->dest
.ssa
.num_components
!= 4)
5107 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5111 assert(instr
->dest
.is_ssa
);
5112 result
= ac_to_integer(&ctx
->ac
, result
);
5113 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5118 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5120 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5121 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5123 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5124 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5127 static void visit_post_phi(struct ac_nir_context
*ctx
,
5128 nir_phi_instr
*instr
,
5129 LLVMValueRef llvm_phi
)
5131 nir_foreach_phi_src(src
, instr
) {
5132 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5133 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5135 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5139 static void phi_post_pass(struct ac_nir_context
*ctx
)
5141 struct hash_entry
*entry
;
5142 hash_table_foreach(ctx
->phis
, entry
) {
5143 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5144 (LLVMValueRef
)entry
->data
);
5149 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5150 const nir_ssa_undef_instr
*instr
)
5152 unsigned num_components
= instr
->def
.num_components
;
5153 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5156 if (num_components
== 1)
5157 undef
= LLVMGetUndef(type
);
5159 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5161 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5164 static void visit_jump(struct ac_nir_context
*ctx
,
5165 const nir_jump_instr
*instr
)
5167 switch (instr
->type
) {
5168 case nir_jump_break
:
5169 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5170 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5172 case nir_jump_continue
:
5173 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5174 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5177 fprintf(stderr
, "Unknown NIR jump instr: ");
5178 nir_print_instr(&instr
->instr
, stderr
);
5179 fprintf(stderr
, "\n");
5184 static void visit_cf_list(struct ac_nir_context
*ctx
,
5185 struct exec_list
*list
);
5187 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5189 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5190 nir_foreach_instr(instr
, block
)
5192 switch (instr
->type
) {
5193 case nir_instr_type_alu
:
5194 visit_alu(ctx
, nir_instr_as_alu(instr
));
5196 case nir_instr_type_load_const
:
5197 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5199 case nir_instr_type_intrinsic
:
5200 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5202 case nir_instr_type_tex
:
5203 visit_tex(ctx
, nir_instr_as_tex(instr
));
5205 case nir_instr_type_phi
:
5206 visit_phi(ctx
, nir_instr_as_phi(instr
));
5208 case nir_instr_type_ssa_undef
:
5209 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5211 case nir_instr_type_jump
:
5212 visit_jump(ctx
, nir_instr_as_jump(instr
));
5215 fprintf(stderr
, "Unknown NIR instr type: ");
5216 nir_print_instr(instr
, stderr
);
5217 fprintf(stderr
, "\n");
5222 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5225 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5227 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5229 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5230 LLVMBasicBlockRef merge_block
=
5231 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5232 LLVMBasicBlockRef if_block
=
5233 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5234 LLVMBasicBlockRef else_block
= merge_block
;
5235 if (!exec_list_is_empty(&if_stmt
->else_list
))
5236 else_block
= LLVMAppendBasicBlockInContext(
5237 ctx
->ac
.context
, fn
, "");
5239 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5241 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5243 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5244 visit_cf_list(ctx
, &if_stmt
->then_list
);
5245 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5246 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5248 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5249 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5250 visit_cf_list(ctx
, &if_stmt
->else_list
);
5251 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5252 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5255 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5258 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5260 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5261 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5262 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5264 ctx
->continue_block
=
5265 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5267 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5269 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5270 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5271 visit_cf_list(ctx
, &loop
->body
);
5273 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5274 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5275 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5277 ctx
->continue_block
= continue_parent
;
5278 ctx
->break_block
= break_parent
;
5281 static void visit_cf_list(struct ac_nir_context
*ctx
,
5282 struct exec_list
*list
)
5284 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5286 switch (node
->type
) {
5287 case nir_cf_node_block
:
5288 visit_block(ctx
, nir_cf_node_as_block(node
));
5291 case nir_cf_node_if
:
5292 visit_if(ctx
, nir_cf_node_as_if(node
));
5295 case nir_cf_node_loop
:
5296 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5306 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5307 struct nir_variable
*variable
)
5309 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5310 LLVMValueRef t_offset
;
5311 LLVMValueRef t_list
;
5313 LLVMValueRef buffer_index
;
5314 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5315 int idx
= variable
->data
.location
;
5316 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5318 variable
->data
.driver_location
= idx
* 4;
5320 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5321 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5322 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5323 ctx
->abi
.start_instance
, "");
5324 if (ctx
->options
->key
.vs
.as_ls
) {
5325 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5326 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5328 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5329 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5332 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5333 ctx
->abi
.base_vertex
, "");
5334 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5336 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5338 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5343 for (unsigned chan
= 0; chan
< 4; chan
++) {
5344 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5345 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5346 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5347 input
, llvm_chan
, ""));
5352 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5354 LLVMValueRef interp_param
,
5355 LLVMValueRef prim_mask
,
5356 LLVMValueRef result
[4])
5358 LLVMValueRef attr_number
;
5361 bool interp
= interp_param
!= NULL
;
5363 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5365 /* fs.constant returns the param from the middle vertex, so it's not
5366 * really useful for flat shading. It's meant to be used for custom
5367 * interpolation (but the intrinsic can't fetch from the other two
5370 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5371 * to do the right thing. The only reason we use fs.constant is that
5372 * fs.interp cannot be used on integers, because they can be equal
5376 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5379 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5381 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5385 for (chan
= 0; chan
< 4; chan
++) {
5386 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5389 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5394 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5395 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5404 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5405 struct nir_variable
*variable
)
5407 int idx
= variable
->data
.location
;
5408 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5409 LLVMValueRef interp
;
5411 variable
->data
.driver_location
= idx
* 4;
5412 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5414 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5415 unsigned interp_type
;
5416 if (variable
->data
.sample
) {
5417 interp_type
= INTERP_SAMPLE
;
5418 ctx
->shader_info
->info
.ps
.force_persample
= true;
5419 } else if (variable
->data
.centroid
)
5420 interp_type
= INTERP_CENTROID
;
5422 interp_type
= INTERP_CENTER
;
5424 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
5428 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5429 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5434 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5435 struct nir_shader
*nir
) {
5436 nir_foreach_variable(variable
, &nir
->inputs
)
5437 handle_vs_input_decl(ctx
, variable
);
5441 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5442 struct nir_shader
*nir
)
5444 if (!ctx
->options
->key
.fs
.multisample
)
5447 bool uses_center
= false;
5448 bool uses_centroid
= false;
5449 nir_foreach_variable(variable
, &nir
->inputs
) {
5450 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5451 variable
->data
.sample
)
5454 if (variable
->data
.centroid
)
5455 uses_centroid
= true;
5460 if (uses_center
&& uses_centroid
) {
5461 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
5462 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5463 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5468 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5469 struct nir_shader
*nir
)
5471 prepare_interp_optimize(ctx
, nir
);
5473 nir_foreach_variable(variable
, &nir
->inputs
)
5474 handle_fs_input_decl(ctx
, variable
);
5478 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5479 ctx
->shader_info
->info
.needs_multiview_view_index
)
5480 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5482 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5483 LLVMValueRef interp_param
;
5484 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5486 if (!(ctx
->input_mask
& (1ull << i
)))
5489 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5490 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5491 interp_param
= *inputs
;
5492 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
5496 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5498 } else if (i
== VARYING_SLOT_POS
) {
5499 for(int i
= 0; i
< 3; ++i
)
5500 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5502 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5503 ctx
->abi
.frag_pos
[3]);
5506 ctx
->shader_info
->fs
.num_interp
= index
;
5507 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5508 ctx
->shader_info
->fs
.has_pcoord
= true;
5509 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5510 ctx
->shader_info
->fs
.prim_id_input
= true;
5511 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5512 ctx
->shader_info
->fs
.layer_input
= true;
5513 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5515 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5516 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5520 ac_build_alloca(struct ac_llvm_context
*ac
,
5524 LLVMBuilderRef builder
= ac
->builder
;
5525 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5526 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5527 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5528 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5529 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5533 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5535 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5538 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5539 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5541 LLVMDisposeBuilder(first_builder
);
5546 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5550 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5551 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5556 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5557 struct nir_variable
*variable
,
5558 struct nir_shader
*shader
,
5559 gl_shader_stage stage
)
5561 int idx
= variable
->data
.location
+ variable
->data
.index
;
5562 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5563 uint64_t mask_attribs
;
5565 variable
->data
.driver_location
= idx
* 4;
5567 /* tess ctrl has it's own load/store paths for outputs */
5568 if (stage
== MESA_SHADER_TESS_CTRL
)
5571 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5572 if (stage
== MESA_SHADER_VERTEX
||
5573 stage
== MESA_SHADER_TESS_EVAL
||
5574 stage
== MESA_SHADER_GEOMETRY
) {
5575 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5576 int length
= shader
->info
.clip_distance_array_size
+
5577 shader
->info
.cull_distance_array_size
;
5578 if (stage
== MESA_SHADER_VERTEX
) {
5579 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5580 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5582 if (stage
== MESA_SHADER_TESS_EVAL
) {
5583 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5584 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5591 mask_attribs
= 1ull << idx
;
5595 ctx
->output_mask
|= mask_attribs
;
5599 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5600 struct nir_shader
*nir
,
5601 struct nir_variable
*variable
)
5603 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5604 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5606 /* tess ctrl has it's own load/store paths for outputs */
5607 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5610 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5611 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5612 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5613 int idx
= variable
->data
.location
+ variable
->data
.index
;
5614 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5615 int length
= nir
->info
.clip_distance_array_size
+
5616 nir
->info
.cull_distance_array_size
;
5625 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5626 for (unsigned chan
= 0; chan
< 4; chan
++) {
5627 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5628 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5634 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5635 enum glsl_base_type type
)
5639 case GLSL_TYPE_UINT
:
5640 case GLSL_TYPE_BOOL
:
5641 case GLSL_TYPE_SUBROUTINE
:
5643 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5645 case GLSL_TYPE_INT64
:
5646 case GLSL_TYPE_UINT64
:
5648 case GLSL_TYPE_DOUBLE
:
5651 unreachable("unknown GLSL type");
5656 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5657 const struct glsl_type
*type
)
5659 if (glsl_type_is_scalar(type
)) {
5660 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5663 if (glsl_type_is_vector(type
)) {
5664 return LLVMVectorType(
5665 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5666 glsl_get_vector_elements(type
));
5669 if (glsl_type_is_matrix(type
)) {
5670 return LLVMArrayType(
5671 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5672 glsl_get_matrix_columns(type
));
5675 if (glsl_type_is_array(type
)) {
5676 return LLVMArrayType(
5677 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5678 glsl_get_length(type
));
5681 assert(glsl_type_is_struct(type
));
5683 LLVMTypeRef member_types
[glsl_get_length(type
)];
5685 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5687 glsl_to_llvm_type(ctx
,
5688 glsl_get_struct_field(type
, i
));
5691 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5692 glsl_get_length(type
), false);
5696 setup_locals(struct ac_nir_context
*ctx
,
5697 struct nir_function
*func
)
5700 ctx
->num_locals
= 0;
5701 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5702 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5703 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5704 variable
->data
.location_frac
= 0;
5705 ctx
->num_locals
+= attrib_count
;
5707 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5711 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5712 for (j
= 0; j
< 4; j
++) {
5713 ctx
->locals
[i
* 4 + j
] =
5714 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5720 setup_shared(struct ac_nir_context
*ctx
,
5721 struct nir_shader
*nir
)
5723 nir_foreach_variable(variable
, &nir
->shared
) {
5724 LLVMValueRef shared
=
5725 LLVMAddGlobalInAddressSpace(
5726 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5727 variable
->name
? variable
->name
: "",
5728 AC_LOCAL_ADDR_SPACE
);
5729 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5734 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5736 v
= ac_to_float(ctx
, v
);
5737 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5738 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5742 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5743 LLVMValueRef src0
, LLVMValueRef src1
)
5745 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5746 LLVMValueRef comp
[2];
5748 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5749 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5750 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5751 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5754 /* Initialize arguments for the shader export intrinsic */
5756 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5757 LLVMValueRef
*values
,
5759 struct ac_export_args
*args
)
5761 /* Default is 0xf. Adjusted below depending on the format. */
5762 args
->enabled_channels
= 0xf;
5764 /* Specify whether the EXEC mask represents the valid mask */
5765 args
->valid_mask
= 0;
5767 /* Specify whether this is the last export */
5770 /* Specify the target we are exporting */
5771 args
->target
= target
;
5773 args
->compr
= false;
5774 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5775 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5776 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5777 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5782 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5783 LLVMValueRef val
[4];
5784 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5785 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5786 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5787 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5789 switch(col_format
) {
5790 case V_028714_SPI_SHADER_ZERO
:
5791 args
->enabled_channels
= 0; /* writemask */
5792 args
->target
= V_008DFC_SQ_EXP_NULL
;
5795 case V_028714_SPI_SHADER_32_R
:
5796 args
->enabled_channels
= 1;
5797 args
->out
[0] = values
[0];
5800 case V_028714_SPI_SHADER_32_GR
:
5801 args
->enabled_channels
= 0x3;
5802 args
->out
[0] = values
[0];
5803 args
->out
[1] = values
[1];
5806 case V_028714_SPI_SHADER_32_AR
:
5807 args
->enabled_channels
= 0x9;
5808 args
->out
[0] = values
[0];
5809 args
->out
[3] = values
[3];
5812 case V_028714_SPI_SHADER_FP16_ABGR
:
5815 for (unsigned chan
= 0; chan
< 2; chan
++) {
5816 LLVMValueRef pack_args
[2] = {
5818 values
[2 * chan
+ 1]
5820 LLVMValueRef packed
;
5822 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5823 args
->out
[chan
] = packed
;
5827 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5828 for (unsigned chan
= 0; chan
< 4; chan
++) {
5829 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5830 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5831 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5832 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5833 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5834 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5839 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5840 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5843 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5844 for (unsigned chan
= 0; chan
< 4; chan
++) {
5845 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5846 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5847 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5849 /* If positive, add 0.5, else add -0.5. */
5850 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5851 LLVMBuildSelect(ctx
->builder
,
5852 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5853 val
[chan
], ctx
->ac
.f32_0
, ""),
5854 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5855 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5856 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5860 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5861 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5864 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5865 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5866 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5867 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5869 for (unsigned chan
= 0; chan
< 4; chan
++) {
5870 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5871 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5875 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5876 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5880 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5881 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5882 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5883 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5884 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5885 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5886 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5889 for (unsigned chan
= 0; chan
< 4; chan
++) {
5890 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5891 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5892 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5896 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5897 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5902 case V_028714_SPI_SHADER_32_ABGR
:
5903 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5907 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5909 for (unsigned i
= 0; i
< 4; ++i
)
5910 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5914 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5915 bool export_prim_id
,
5916 struct ac_vs_output_info
*outinfo
)
5918 uint32_t param_count
= 0;
5920 unsigned pos_idx
, num_pos_exports
= 0;
5921 struct ac_export_args args
, pos_args
[4] = {};
5922 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5925 if (ctx
->options
->key
.has_multiview_view_index
) {
5926 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5928 for(unsigned i
= 0; i
< 4; ++i
)
5929 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5930 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5933 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5934 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5937 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5938 sizeof(outinfo
->vs_output_param_offset
));
5940 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5941 LLVMValueRef slots
[8];
5944 if (outinfo
->cull_dist_mask
)
5945 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5947 i
= VARYING_SLOT_CLIP_DIST0
;
5948 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5949 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5950 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5952 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5953 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5955 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5956 target
= V_008DFC_SQ_EXP_POS
+ 3;
5957 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5958 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5959 &args
, sizeof(args
));
5962 target
= V_008DFC_SQ_EXP_POS
+ 2;
5963 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5964 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5965 &args
, sizeof(args
));
5969 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5970 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5971 for (unsigned j
= 0; j
< 4; j
++)
5972 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5973 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5975 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5977 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5978 outinfo
->writes_pointsize
= true;
5979 psize_value
= LLVMBuildLoad(ctx
->builder
,
5980 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5983 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5984 outinfo
->writes_layer
= true;
5985 layer_value
= LLVMBuildLoad(ctx
->builder
,
5986 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5989 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5990 outinfo
->writes_viewport_index
= true;
5991 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5992 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5995 if (outinfo
->writes_pointsize
||
5996 outinfo
->writes_layer
||
5997 outinfo
->writes_viewport_index
) {
5998 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5999 (outinfo
->writes_layer
== true ? 4 : 0));
6000 pos_args
[1].valid_mask
= 0;
6001 pos_args
[1].done
= 0;
6002 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
6003 pos_args
[1].compr
= 0;
6004 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
6005 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6006 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6007 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6009 if (outinfo
->writes_pointsize
== true)
6010 pos_args
[1].out
[0] = psize_value
;
6011 if (outinfo
->writes_layer
== true)
6012 pos_args
[1].out
[2] = layer_value
;
6013 if (outinfo
->writes_viewport_index
== true) {
6014 if (ctx
->options
->chip_class
>= GFX9
) {
6015 /* GFX9 has the layer in out.z[10:0] and the viewport
6016 * index in out.z[19:16].
6018 LLVMValueRef v
= viewport_index_value
;
6019 v
= ac_to_integer(&ctx
->ac
, v
);
6020 v
= LLVMBuildShl(ctx
->builder
, v
,
6021 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6023 v
= LLVMBuildOr(ctx
->builder
, v
,
6024 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6026 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6027 pos_args
[1].enabled_channels
|= 1 << 2;
6029 pos_args
[1].out
[3] = viewport_index_value
;
6030 pos_args
[1].enabled_channels
|= 1 << 3;
6034 for (i
= 0; i
< 4; i
++) {
6035 if (pos_args
[i
].out
[0])
6040 for (i
= 0; i
< 4; i
++) {
6041 if (!pos_args
[i
].out
[0])
6044 /* Specify the target we are exporting */
6045 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6046 if (pos_idx
== num_pos_exports
)
6047 pos_args
[i
].done
= 1;
6048 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6051 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6052 LLVMValueRef values
[4];
6053 if (!(ctx
->output_mask
& (1ull << i
)))
6056 for (unsigned j
= 0; j
< 4; j
++)
6057 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6058 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6060 if (i
== VARYING_SLOT_LAYER
) {
6061 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6062 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
6064 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
6065 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6066 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6068 } else if (i
>= VARYING_SLOT_VAR0
) {
6069 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
6070 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6071 outinfo
->vs_output_param_offset
[i
] = param_count
;
6076 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6078 if (target
>= V_008DFC_SQ_EXP_POS
&&
6079 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
6080 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6081 &args
, sizeof(args
));
6083 ac_build_export(&ctx
->ac
, &args
);
6087 if (export_prim_id
) {
6088 LLVMValueRef values
[4];
6089 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
6090 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
6093 values
[0] = ctx
->vs_prim_id
;
6094 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6095 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6096 for (unsigned j
= 1; j
< 4; j
++)
6097 values
[j
] = ctx
->ac
.f32_0
;
6098 si_llvm_init_export_args(ctx
, values
, target
, &args
);
6099 ac_build_export(&ctx
->ac
, &args
);
6100 outinfo
->export_prim_id
= true;
6103 outinfo
->pos_exports
= num_pos_exports
;
6104 outinfo
->param_exports
= param_count
;
6108 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
6109 struct ac_es_output_info
*outinfo
)
6112 uint64_t max_output_written
= 0;
6113 LLVMValueRef lds_base
= NULL
;
6115 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6119 if (!(ctx
->output_mask
& (1ull << i
)))
6122 if (i
== VARYING_SLOT_CLIP_DIST0
)
6123 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6125 param_index
= shader_io_get_unique_index(i
);
6127 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6130 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6132 if (ctx
->ac
.chip_class
>= GFX9
) {
6133 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6134 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6135 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6136 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6137 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6138 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6139 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6140 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6141 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6142 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6145 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6146 LLVMValueRef dw_addr
;
6147 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6151 if (!(ctx
->output_mask
& (1ull << i
)))
6154 if (i
== VARYING_SLOT_CLIP_DIST0
)
6155 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6157 param_index
= shader_io_get_unique_index(i
);
6160 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6161 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6164 for (j
= 0; j
< length
; j
++) {
6165 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
6166 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
6168 if (ctx
->ac
.chip_class
>= GFX9
) {
6169 ac_lds_store(&ctx
->ac
, dw_addr
,
6170 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6171 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6173 ac_build_buffer_store_dword(&ctx
->ac
,
6176 NULL
, ctx
->es2gs_offset
,
6177 (4 * param_index
+ j
) * 4,
6185 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
6187 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6188 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6189 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
6190 vertex_dw_stride
, "");
6192 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6193 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6196 if (!(ctx
->output_mask
& (1ull << i
)))
6199 if (i
== VARYING_SLOT_CLIP_DIST0
)
6200 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6201 int param
= shader_io_get_unique_index(i
);
6202 mark_tess_output(ctx
, false, param
);
6204 mark_tess_output(ctx
, false, param
+ 1);
6205 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
6206 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6208 for (unsigned j
= 0; j
< length
; j
++) {
6209 ac_lds_store(&ctx
->ac
, dw_addr
,
6210 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6211 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6216 struct ac_build_if_state
6218 struct nir_to_llvm_context
*ctx
;
6219 LLVMValueRef condition
;
6220 LLVMBasicBlockRef entry_block
;
6221 LLVMBasicBlockRef true_block
;
6222 LLVMBasicBlockRef false_block
;
6223 LLVMBasicBlockRef merge_block
;
6226 static LLVMBasicBlockRef
6227 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
6229 LLVMBasicBlockRef current_block
;
6230 LLVMBasicBlockRef next_block
;
6231 LLVMBasicBlockRef new_block
;
6233 /* get current basic block */
6234 current_block
= LLVMGetInsertBlock(ctx
->builder
);
6236 /* chqeck if there's another block after this one */
6237 next_block
= LLVMGetNextBasicBlock(current_block
);
6239 /* insert the new block before the next block */
6240 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6243 /* append new block after current block */
6244 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6245 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6251 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6252 struct nir_to_llvm_context
*ctx
,
6253 LLVMValueRef condition
)
6255 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6257 memset(ifthen
, 0, sizeof *ifthen
);
6259 ifthen
->condition
= condition
;
6260 ifthen
->entry_block
= block
;
6262 /* create endif/merge basic block for the phi functions */
6263 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6265 /* create/insert true_block before merge_block */
6266 ifthen
->true_block
=
6267 LLVMInsertBasicBlockInContext(ctx
->context
,
6268 ifthen
->merge_block
,
6271 /* successive code goes into the true block */
6272 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6276 * End a conditional.
6279 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6281 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6283 /* Insert branch to the merge block from current block */
6284 LLVMBuildBr(builder
, ifthen
->merge_block
);
6287 * Now patch in the various branch instructions.
6290 /* Insert the conditional branch instruction at the end of entry_block */
6291 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6292 if (ifthen
->false_block
) {
6293 /* we have an else clause */
6294 LLVMBuildCondBr(builder
, ifthen
->condition
,
6295 ifthen
->true_block
, ifthen
->false_block
);
6298 /* no else clause */
6299 LLVMBuildCondBr(builder
, ifthen
->condition
,
6300 ifthen
->true_block
, ifthen
->merge_block
);
6303 /* Resume building code at end of the ifthen->merge_block */
6304 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6308 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6310 unsigned stride
, outer_comps
, inner_comps
;
6311 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6312 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6313 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6314 unsigned tess_inner_index
, tess_outer_index
;
6315 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6316 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6318 emit_barrier(&ctx
->ac
, ctx
->stage
);
6320 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6340 ac_nir_build_if(&if_ctx
, ctx
,
6341 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6342 invocation_id
, ctx
->ac
.i32_0
, ""));
6344 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6345 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6347 mark_tess_output(ctx
, true, tess_inner_index
);
6348 mark_tess_output(ctx
, true, tess_outer_index
);
6349 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6350 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6351 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6352 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6353 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6355 for (i
= 0; i
< 4; i
++) {
6356 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6357 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6361 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6362 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6363 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6365 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6367 for (i
= 0; i
< outer_comps
; i
++) {
6369 ac_lds_load(&ctx
->ac
, lds_outer
);
6370 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6373 for (i
= 0; i
< inner_comps
; i
++) {
6374 inner
[i
] = out
[outer_comps
+i
] =
6375 ac_lds_load(&ctx
->ac
, lds_inner
);
6376 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6381 /* Convert the outputs to vectors for stores. */
6382 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6386 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6389 buffer
= ctx
->hs_ring_tess_factor
;
6390 tf_base
= ctx
->tess_factor_offset
;
6391 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6392 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6393 unsigned tf_offset
= 0;
6395 if (ctx
->options
->chip_class
<= VI
) {
6396 ac_nir_build_if(&inner_if_ctx
, ctx
,
6397 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6398 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6400 /* Store the dynamic HS control word. */
6401 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6402 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6403 1, ctx
->ac
.i32_0
, tf_base
,
6404 0, 1, 0, true, false);
6407 ac_nir_build_endif(&inner_if_ctx
);
6410 /* Store the tessellation factors. */
6411 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6412 MIN2(stride
, 4), byteoffset
, tf_base
,
6413 tf_offset
, 1, 0, true, false);
6415 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6416 stride
- 4, byteoffset
, tf_base
,
6417 16 + tf_offset
, 1, 0, true, false);
6419 //store to offchip for TES to read - only if TES reads them
6420 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6421 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6422 LLVMValueRef tf_inner_offset
;
6423 unsigned param_outer
, param_inner
;
6425 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6426 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6427 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6429 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6430 util_next_power_of_two(outer_comps
));
6432 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6433 outer_comps
, tf_outer_offset
,
6434 ctx
->oc_lds
, 0, 1, 0, true, false);
6436 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6437 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6438 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6440 inner_vec
= inner_comps
== 1 ? inner
[0] :
6441 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6442 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6443 inner_comps
, tf_inner_offset
,
6444 ctx
->oc_lds
, 0, 1, 0, true, false);
6447 ac_nir_build_endif(&if_ctx
);
6451 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6453 write_tess_factors(ctx
);
6457 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6458 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6459 struct ac_export_args
*args
)
6462 si_llvm_init_export_args(ctx
, color
, param
,
6466 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6467 args
->done
= 1; /* DONE bit */
6468 } else if (!args
->enabled_channels
)
6469 return false; /* unnecessary NULL export */
6475 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6476 LLVMValueRef depth
, LLVMValueRef stencil
,
6477 LLVMValueRef samplemask
)
6479 struct ac_export_args args
;
6481 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6483 ac_build_export(&ctx
->ac
, &args
);
6487 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6490 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6491 struct ac_export_args color_args
[8];
6493 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6494 LLVMValueRef values
[4];
6496 if (!(ctx
->output_mask
& (1ull << i
)))
6499 if (i
== FRAG_RESULT_DEPTH
) {
6500 ctx
->shader_info
->fs
.writes_z
= true;
6501 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6502 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6503 } else if (i
== FRAG_RESULT_STENCIL
) {
6504 ctx
->shader_info
->fs
.writes_stencil
= true;
6505 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6506 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6507 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6508 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6509 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6510 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6513 for (unsigned j
= 0; j
< 4; j
++)
6514 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6515 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6517 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6518 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6520 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6526 for (unsigned i
= 0; i
< index
; i
++)
6527 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6528 if (depth
|| stencil
|| samplemask
)
6529 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6531 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6532 ac_build_export(&ctx
->ac
, &color_args
[0]);
6537 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6539 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6543 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6544 LLVMValueRef
*addrs
)
6546 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6548 switch (ctx
->stage
) {
6549 case MESA_SHADER_VERTEX
:
6550 if (ctx
->options
->key
.vs
.as_ls
)
6551 handle_ls_outputs_post(ctx
);
6552 else if (ctx
->options
->key
.vs
.as_es
)
6553 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6555 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6556 &ctx
->shader_info
->vs
.outinfo
);
6558 case MESA_SHADER_FRAGMENT
:
6559 handle_fs_outputs_post(ctx
);
6561 case MESA_SHADER_GEOMETRY
:
6562 emit_gs_epilogue(ctx
);
6564 case MESA_SHADER_TESS_CTRL
:
6565 handle_tcs_outputs_post(ctx
);
6567 case MESA_SHADER_TESS_EVAL
:
6568 if (ctx
->options
->key
.tes
.as_es
)
6569 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6571 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6572 &ctx
->shader_info
->tes
.outinfo
);
6579 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6581 LLVMPassManagerRef passmgr
;
6582 /* Create the pass manager */
6583 passmgr
= LLVMCreateFunctionPassManagerForModule(
6586 /* This pass should eliminate all the load and store instructions */
6587 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6589 /* Add some optimization passes */
6590 LLVMAddScalarReplAggregatesPass(passmgr
);
6591 LLVMAddLICMPass(passmgr
);
6592 LLVMAddAggressiveDCEPass(passmgr
);
6593 LLVMAddCFGSimplificationPass(passmgr
);
6594 LLVMAddInstructionCombiningPass(passmgr
);
6597 LLVMInitializeFunctionPassManager(passmgr
);
6598 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6599 LLVMFinalizeFunctionPassManager(passmgr
);
6601 LLVMDisposeBuilder(ctx
->builder
);
6602 LLVMDisposePassManager(passmgr
);
6606 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6608 struct ac_vs_output_info
*outinfo
;
6610 switch (ctx
->stage
) {
6611 case MESA_SHADER_FRAGMENT
:
6612 case MESA_SHADER_COMPUTE
:
6613 case MESA_SHADER_TESS_CTRL
:
6614 case MESA_SHADER_GEOMETRY
:
6616 case MESA_SHADER_VERTEX
:
6617 if (ctx
->options
->key
.vs
.as_ls
||
6618 ctx
->options
->key
.vs
.as_es
)
6620 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6622 case MESA_SHADER_TESS_EVAL
:
6623 if (ctx
->options
->key
.vs
.as_es
)
6625 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6628 unreachable("Unhandled shader type");
6631 ac_optimize_vs_outputs(&ctx
->ac
,
6633 outinfo
->vs_output_param_offset
,
6635 &outinfo
->param_exports
);
6639 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6641 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6642 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6643 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6646 if (ctx
->is_gs_copy_shader
) {
6647 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6649 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6651 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6652 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6654 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6656 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6657 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6658 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6659 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6662 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6663 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6664 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6665 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6670 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6671 const struct nir_shader
*nir
)
6673 switch (nir
->info
.stage
) {
6674 case MESA_SHADER_TESS_CTRL
:
6675 return chip_class
>= CIK
? 128 : 64;
6676 case MESA_SHADER_GEOMETRY
:
6677 return chip_class
>= GFX9
? 128 : 64;
6678 case MESA_SHADER_COMPUTE
:
6684 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6685 nir
->info
.cs
.local_size
[1] *
6686 nir
->info
.cs
.local_size
[2];
6687 return max_workgroup_size
;
6690 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6691 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6693 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6694 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6695 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6696 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6698 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6699 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6700 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6701 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6704 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6706 for(int i
= 5; i
>= 0; --i
) {
6707 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6708 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6709 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6712 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6713 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6714 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6717 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6718 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6720 struct ac_nir_context ctx
= {};
6721 struct nir_function
*func
;
6730 ctx
.stage
= nir
->info
.stage
;
6732 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6734 nir_foreach_variable(variable
, &nir
->outputs
)
6735 handle_shader_output_decl(&ctx
, nir
, variable
);
6737 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6738 _mesa_key_pointer_equal
);
6739 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6740 _mesa_key_pointer_equal
);
6741 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6742 _mesa_key_pointer_equal
);
6744 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6746 setup_locals(&ctx
, func
);
6748 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6749 setup_shared(&ctx
, nir
);
6751 visit_cf_list(&ctx
, &func
->impl
->body
);
6752 phi_post_pass(&ctx
);
6754 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6758 ralloc_free(ctx
.defs
);
6759 ralloc_free(ctx
.phis
);
6760 ralloc_free(ctx
.vars
);
6767 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6768 struct nir_shader
*const *shaders
,
6770 struct ac_shader_variant_info
*shader_info
,
6771 const struct ac_nir_compiler_options
*options
)
6773 struct nir_to_llvm_context ctx
= {0};
6775 ctx
.options
= options
;
6776 ctx
.shader_info
= shader_info
;
6777 ctx
.context
= LLVMContextCreate();
6778 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6780 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6782 ctx
.ac
.module
= ctx
.module
;
6783 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6785 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6786 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6787 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6788 LLVMDisposeTargetData(data_layout
);
6789 LLVMDisposeMessage(data_layout_str
);
6791 enum ac_float_mode float_mode
=
6792 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6793 AC_FLOAT_MODE_DEFAULT
;
6795 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6796 ctx
.ac
.builder
= ctx
.builder
;
6798 memset(shader_info
, 0, sizeof(*shader_info
));
6800 for(int i
= 0; i
< shader_count
; ++i
)
6801 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6803 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6804 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6805 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6806 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6808 ctx
.max_workgroup_size
= 0;
6809 for (int i
= 0; i
< shader_count
; ++i
) {
6810 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6811 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6815 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6816 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6818 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6819 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6820 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6821 ctx
.abi
.load_ubo
= radv_load_ubo
;
6822 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6823 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6824 ctx
.abi
.clamp_shadow_reference
= false;
6826 if (shader_count
>= 2)
6827 ac_init_exec_full_mask(&ctx
.ac
);
6829 if (ctx
.ac
.chip_class
== GFX9
&&
6830 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6831 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6833 for(int i
= 0; i
< shader_count
; ++i
) {
6834 ctx
.stage
= shaders
[i
]->info
.stage
;
6835 ctx
.output_mask
= 0;
6836 ctx
.tess_outputs_written
= 0;
6837 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6838 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6840 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6841 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6842 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6843 ctx
.abi
.load_inputs
= load_gs_input
;
6844 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6845 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6846 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6847 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6848 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6849 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6850 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6851 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6852 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6853 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6854 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6855 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6856 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6857 if (shader_info
->info
.vs
.needs_instance_id
) {
6858 if (ctx
.options
->key
.vs
.as_ls
) {
6859 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6860 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6862 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6863 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6866 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6867 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6868 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
6869 ctx
.abi
.load_sample_position
= load_sample_position
;
6873 emit_barrier(&ctx
.ac
, ctx
.stage
);
6875 ac_setup_rings(&ctx
);
6877 LLVMBasicBlockRef merge_block
;
6878 if (shader_count
>= 2) {
6879 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6880 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6881 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6883 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6884 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6885 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6886 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6887 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6888 thread_id
, count
, "");
6889 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6891 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6894 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6895 handle_fs_inputs(&ctx
, shaders
[i
]);
6896 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6897 handle_vs_inputs(&ctx
, shaders
[i
]);
6898 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6899 prepare_gs_input_vgprs(&ctx
);
6901 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6902 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6904 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6906 if (shader_count
>= 2) {
6907 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6908 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6911 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6912 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6913 shaders
[i
]->info
.cull_distance_array_size
> 4;
6914 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6915 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6916 shaders
[i
]->info
.gs
.vertices_out
;
6917 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6918 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6919 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6920 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6921 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6925 LLVMBuildRetVoid(ctx
.builder
);
6927 if (options
->dump_preoptir
)
6928 ac_dump_module(ctx
.module
);
6930 ac_llvm_finalize_module(&ctx
);
6932 if (shader_count
== 1)
6933 ac_nir_eliminate_const_vs_outputs(&ctx
);
6938 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6940 unsigned *retval
= (unsigned *)context
;
6941 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6942 char *description
= LLVMGetDiagInfoDescription(di
);
6944 if (severity
== LLVMDSError
) {
6946 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6950 LLVMDisposeMessage(description
);
6953 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6954 struct ac_shader_binary
*binary
,
6955 LLVMTargetMachineRef tm
)
6957 unsigned retval
= 0;
6959 LLVMContextRef llvm_ctx
;
6960 LLVMMemoryBufferRef out_buffer
;
6961 unsigned buffer_size
;
6962 const char *buffer_data
;
6965 /* Setup Diagnostic Handler*/
6966 llvm_ctx
= LLVMGetModuleContext(M
);
6968 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6972 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6975 /* Process Errors/Warnings */
6977 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6983 /* Extract Shader Code*/
6984 buffer_size
= LLVMGetBufferSize(out_buffer
);
6985 buffer_data
= LLVMGetBufferStart(out_buffer
);
6987 ac_elf_read(buffer_data
, buffer_size
, binary
);
6990 LLVMDisposeMemoryBuffer(out_buffer
);
6996 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6997 LLVMModuleRef llvm_module
,
6998 struct ac_shader_binary
*binary
,
6999 struct ac_shader_config
*config
,
7000 struct ac_shader_variant_info
*shader_info
,
7001 gl_shader_stage stage
,
7002 bool dump_shader
, bool supports_spill
)
7005 ac_dump_module(llvm_module
);
7007 memset(binary
, 0, sizeof(*binary
));
7008 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7010 fprintf(stderr
, "compile failed\n");
7014 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7016 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7018 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7019 LLVMDisposeModule(llvm_module
);
7020 LLVMContextDispose(ctx
);
7022 if (stage
== MESA_SHADER_FRAGMENT
) {
7023 shader_info
->num_input_vgprs
= 0;
7024 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7025 shader_info
->num_input_vgprs
+= 2;
7026 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7027 shader_info
->num_input_vgprs
+= 2;
7028 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7029 shader_info
->num_input_vgprs
+= 2;
7030 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7031 shader_info
->num_input_vgprs
+= 3;
7032 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7033 shader_info
->num_input_vgprs
+= 2;
7034 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7035 shader_info
->num_input_vgprs
+= 2;
7036 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7037 shader_info
->num_input_vgprs
+= 2;
7038 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7039 shader_info
->num_input_vgprs
+= 1;
7040 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7041 shader_info
->num_input_vgprs
+= 1;
7042 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7043 shader_info
->num_input_vgprs
+= 1;
7044 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7045 shader_info
->num_input_vgprs
+= 1;
7046 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7047 shader_info
->num_input_vgprs
+= 1;
7048 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7049 shader_info
->num_input_vgprs
+= 1;
7050 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7051 shader_info
->num_input_vgprs
+= 1;
7052 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7053 shader_info
->num_input_vgprs
+= 1;
7054 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7055 shader_info
->num_input_vgprs
+= 1;
7057 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7059 /* +3 for scratch wave offset and VCC */
7060 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7061 shader_info
->num_input_sgprs
+ 3);
7063 /* Enable 64-bit and 16-bit denormals, because there is no performance
7066 * If denormals are enabled, all floating-point output modifiers are
7069 * Don't enable denormals for 32-bit floats, because:
7070 * - Floating-point output modifiers would be ignored by the hw.
7071 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7072 * have to stop using those.
7073 * - SI & CI would be very slow.
7075 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7079 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7081 switch (nir
->info
.stage
) {
7082 case MESA_SHADER_COMPUTE
:
7083 for (int i
= 0; i
< 3; ++i
)
7084 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7086 case MESA_SHADER_FRAGMENT
:
7087 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7089 case MESA_SHADER_GEOMETRY
:
7090 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7091 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7092 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7093 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7095 case MESA_SHADER_TESS_EVAL
:
7096 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7097 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7098 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7099 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7100 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7102 case MESA_SHADER_TESS_CTRL
:
7103 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7105 case MESA_SHADER_VERTEX
:
7106 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7107 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7108 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7109 if (options
->key
.vs
.as_ls
)
7110 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7117 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7118 struct ac_shader_binary
*binary
,
7119 struct ac_shader_config
*config
,
7120 struct ac_shader_variant_info
*shader_info
,
7121 struct nir_shader
*const *nir
,
7123 const struct ac_nir_compiler_options
*options
,
7127 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7130 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7131 for (int i
= 0; i
< nir_count
; ++i
)
7132 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7134 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7135 if (options
->chip_class
== GFX9
) {
7136 if (nir_count
== 2 &&
7137 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7138 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7144 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
7146 LLVMValueRef vtx_offset
=
7147 LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
,
7148 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7151 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
7155 if (!(ctx
->output_mask
& (1ull << i
)))
7158 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7159 /* unpack clip and cull from a single set of slots */
7160 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7165 for (unsigned j
= 0; j
< length
; j
++) {
7166 LLVMValueRef value
, soffset
;
7168 soffset
= LLVMConstInt(ctx
->ac
.i32
,
7170 ctx
->gs_max_out_vertices
* 16 * 4, false);
7172 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
7174 vtx_offset
, soffset
,
7175 0, 1, 1, true, false);
7177 LLVMBuildStore(ctx
->builder
,
7178 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7182 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7185 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7186 struct nir_shader
*geom_shader
,
7187 struct ac_shader_binary
*binary
,
7188 struct ac_shader_config
*config
,
7189 struct ac_shader_variant_info
*shader_info
,
7190 const struct ac_nir_compiler_options
*options
,
7193 struct nir_to_llvm_context ctx
= {0};
7194 ctx
.context
= LLVMContextCreate();
7195 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7196 ctx
.options
= options
;
7197 ctx
.shader_info
= shader_info
;
7199 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7201 ctx
.ac
.module
= ctx
.module
;
7203 ctx
.is_gs_copy_shader
= true;
7204 LLVMSetTarget(ctx
.module
, "amdgcn--");
7206 enum ac_float_mode float_mode
=
7207 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7208 AC_FLOAT_MODE_DEFAULT
;
7210 ctx
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7211 ctx
.ac
.builder
= ctx
.builder
;
7212 ctx
.stage
= MESA_SHADER_VERTEX
;
7214 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7216 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7217 ac_setup_rings(&ctx
);
7219 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7220 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7222 struct ac_nir_context nir_ctx
= {};
7223 nir_ctx
.ac
= ctx
.ac
;
7224 nir_ctx
.abi
= &ctx
.abi
;
7226 nir_ctx
.nctx
= &ctx
;
7229 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7230 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7231 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7234 ac_gs_copy_shader_emit(&ctx
);
7238 LLVMBuildRetVoid(ctx
.builder
);
7240 ac_llvm_finalize_module(&ctx
);
7242 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
7244 dump_shader
, options
->supports_spill
);