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ac: add store_tcs_outputs() to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
547 struct user_sgpr_info *user_sgpr_info)
548 {
549 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
550
551 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
552 if (ctx->stage == MESA_SHADER_GEOMETRY ||
553 ctx->stage == MESA_SHADER_VERTEX ||
554 ctx->stage == MESA_SHADER_TESS_CTRL ||
555 ctx->stage == MESA_SHADER_TESS_EVAL ||
556 ctx->is_gs_copy_shader)
557 user_sgpr_info->need_ring_offsets = true;
558
559 if (ctx->stage == MESA_SHADER_FRAGMENT &&
560 ctx->shader_info->info.ps.needs_sample_positions)
561 user_sgpr_info->need_ring_offsets = true;
562
563 /* 2 user sgprs will nearly always be allocated for scratch/rings */
564 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
565 user_sgpr_info->sgpr_count += 2;
566 }
567
568 switch (ctx->stage) {
569 case MESA_SHADER_COMPUTE:
570 if (ctx->shader_info->info.cs.uses_grid_size)
571 user_sgpr_info->sgpr_count += 3;
572 break;
573 case MESA_SHADER_FRAGMENT:
574 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
575 break;
576 case MESA_SHADER_VERTEX:
577 if (!ctx->is_gs_copy_shader) {
578 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
579 if (ctx->shader_info->info.vs.needs_draw_id) {
580 user_sgpr_info->sgpr_count += 3;
581 } else {
582 user_sgpr_info->sgpr_count += 2;
583 }
584 }
585 if (ctx->options->key.vs.as_ls)
586 user_sgpr_info->sgpr_count++;
587 break;
588 case MESA_SHADER_TESS_CTRL:
589 user_sgpr_info->sgpr_count += 4;
590 break;
591 case MESA_SHADER_TESS_EVAL:
592 user_sgpr_info->sgpr_count += 1;
593 break;
594 case MESA_SHADER_GEOMETRY:
595 user_sgpr_info->sgpr_count += 2;
596 break;
597 default:
598 break;
599 }
600
601 if (ctx->shader_info->info.needs_push_constants)
602 user_sgpr_info->sgpr_count += 2;
603
604 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
605 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
606 user_sgpr_info->sgpr_count += 2;
607 user_sgpr_info->indirect_all_descriptor_sets = true;
608 } else {
609 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
610 }
611 }
612
613 static void
614 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
615 gl_shader_stage stage,
616 bool has_previous_stage,
617 gl_shader_stage previous_stage,
618 const struct user_sgpr_info *user_sgpr_info,
619 struct arg_info *args,
620 LLVMValueRef *desc_sets)
621 {
622 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
623 unsigned num_sets = ctx->options->layout ?
624 ctx->options->layout->num_sets : 0;
625 unsigned stage_mask = 1 << stage;
626
627 if (has_previous_stage)
628 stage_mask |= 1 << previous_stage;
629
630 /* 1 for each descriptor set */
631 if (!user_sgpr_info->indirect_all_descriptor_sets) {
632 for (unsigned i = 0; i < num_sets; ++i) {
633 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
634 add_array_arg(args, type,
635 &ctx->descriptor_sets[i]);
636 }
637 }
638 } else {
639 add_array_arg(args, const_array(type, 32), desc_sets);
640 }
641
642 if (ctx->shader_info->info.needs_push_constants) {
643 /* 1 for push constants and dynamic descriptors */
644 add_array_arg(args, type, &ctx->push_constants);
645 }
646 }
647
648 static void
649 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
650 gl_shader_stage stage,
651 bool has_previous_stage,
652 gl_shader_stage previous_stage,
653 struct arg_info *args)
654 {
655 if (!ctx->is_gs_copy_shader &&
656 (stage == MESA_SHADER_VERTEX ||
657 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
658 if (ctx->shader_info->info.vs.has_vertex_buffers) {
659 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
660 &ctx->vertex_buffers);
661 }
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
664 if (ctx->shader_info->info.vs.needs_draw_id) {
665 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
666 }
667 }
668 }
669
670 static void
671 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
672 {
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
674 if (!ctx->is_gs_copy_shader) {
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
678 }
679 }
680
681 static void
682 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
683 {
684 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
685 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
686 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
687 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
688 }
689
690 static void
691 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
692 bool has_previous_stage, gl_shader_stage previous_stage,
693 const struct user_sgpr_info *user_sgpr_info,
694 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
695 {
696 unsigned num_sets = ctx->options->layout ?
697 ctx->options->layout->num_sets : 0;
698 unsigned stage_mask = 1 << stage;
699
700 if (has_previous_stage)
701 stage_mask |= 1 << previous_stage;
702
703 if (!user_sgpr_info->indirect_all_descriptor_sets) {
704 for (unsigned i = 0; i < num_sets; ++i) {
705 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
706 set_loc_desc(ctx, i, user_sgpr_idx, 0);
707 } else
708 ctx->descriptor_sets[i] = NULL;
709 }
710 } else {
711 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
712 user_sgpr_idx, 2);
713
714 for (unsigned i = 0; i < num_sets; ++i) {
715 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
716 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
717 ctx->descriptor_sets[i] =
718 ac_build_load_to_sgpr(&ctx->ac,
719 desc_sets,
720 LLVMConstInt(ctx->ac.i32, i, false));
721
722 } else
723 ctx->descriptor_sets[i] = NULL;
724 }
725 ctx->shader_info->need_indirect_descriptor_sets = true;
726 }
727
728 if (ctx->shader_info->info.needs_push_constants) {
729 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
730 }
731 }
732
733 static void
734 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
735 gl_shader_stage stage, bool has_previous_stage,
736 gl_shader_stage previous_stage,
737 uint8_t *user_sgpr_idx)
738 {
739 if (!ctx->is_gs_copy_shader &&
740 (stage == MESA_SHADER_VERTEX ||
741 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
742 if (ctx->shader_info->info.vs.has_vertex_buffers) {
743 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
744 user_sgpr_idx, 2);
745 }
746
747 unsigned vs_num = 2;
748 if (ctx->shader_info->info.vs.needs_draw_id)
749 vs_num++;
750
751 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
752 user_sgpr_idx, vs_num);
753 }
754 }
755
756 static void create_function(struct nir_to_llvm_context *ctx,
757 gl_shader_stage stage,
758 bool has_previous_stage,
759 gl_shader_stage previous_stage)
760 {
761 uint8_t user_sgpr_idx;
762 struct user_sgpr_info user_sgpr_info;
763 struct arg_info args = {};
764 LLVMValueRef desc_sets;
765
766 allocate_user_sgprs(ctx, &user_sgpr_info);
767
768 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
769 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
770 &ctx->ring_offsets);
771 }
772
773 switch (stage) {
774 case MESA_SHADER_COMPUTE:
775 declare_global_input_sgprs(ctx, stage, has_previous_stage,
776 previous_stage, &user_sgpr_info,
777 &args, &desc_sets);
778
779 if (ctx->shader_info->info.cs.uses_grid_size) {
780 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
781 &ctx->num_work_groups);
782 }
783
784 for (int i = 0; i < 3; i++) {
785 ctx->workgroup_ids[i] = NULL;
786 if (ctx->shader_info->info.cs.uses_block_id[i]) {
787 add_arg(&args, ARG_SGPR, ctx->ac.i32,
788 &ctx->workgroup_ids[i]);
789 }
790 }
791
792 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
793 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
794 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
795 &ctx->local_invocation_ids);
796 break;
797 case MESA_SHADER_VERTEX:
798 declare_global_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &user_sgpr_info,
800 &args, &desc_sets);
801 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
802 previous_stage, &args);
803
804 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
806 if (ctx->options->key.vs.as_es)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->es2gs_offset);
809 else if (ctx->options->key.vs.as_ls)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->ls_out_layout);
812
813 declare_vs_input_vgprs(ctx, &args);
814 break;
815 case MESA_SHADER_TESS_CTRL:
816 if (has_previous_stage) {
817 // First 6 system regs
818 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->merged_wave_info);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->tess_factor_offset);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
825 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
826 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
827
828 declare_global_input_sgprs(ctx, stage,
829 has_previous_stage,
830 previous_stage,
831 &user_sgpr_info, &args,
832 &desc_sets);
833 declare_vs_specific_input_sgprs(ctx, stage,
834 has_previous_stage,
835 previous_stage, &args);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->ls_out_layout);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_offchip_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_out_offsets);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_in_layout);
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->view_index);
851
852 add_arg(&args, ARG_VGPR, ctx->ac.i32,
853 &ctx->tcs_patch_id);
854 add_arg(&args, ARG_VGPR, ctx->ac.i32,
855 &ctx->tcs_rel_ids);
856
857 declare_vs_input_vgprs(ctx, &args);
858 } else {
859 declare_global_input_sgprs(ctx, stage,
860 has_previous_stage,
861 previous_stage,
862 &user_sgpr_info, &args,
863 &desc_sets);
864
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_offchip_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_out_offsets);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_in_layout);
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->view_index);
876
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tess_factor_offset);
880 add_arg(&args, ARG_VGPR, ctx->ac.i32,
881 &ctx->tcs_patch_id);
882 add_arg(&args, ARG_VGPR, ctx->ac.i32,
883 &ctx->tcs_rel_ids);
884 }
885 break;
886 case MESA_SHADER_TESS_EVAL:
887 declare_global_input_sgprs(ctx, stage, has_previous_stage,
888 previous_stage, &user_sgpr_info,
889 &args, &desc_sets);
890
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
892 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
894
895 if (ctx->options->key.tes.as_es) {
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->es2gs_offset);
900 } else {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 }
904 declare_tes_input_vgprs(ctx, &args);
905 break;
906 case MESA_SHADER_GEOMETRY:
907 if (has_previous_stage) {
908 // First 6 system regs
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->gs2vs_offset);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->merged_wave_info);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
914
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918
919 declare_global_input_sgprs(ctx, stage,
920 has_previous_stage,
921 previous_stage,
922 &user_sgpr_info, &args,
923 &desc_sets);
924
925 if (previous_stage == MESA_SHADER_TESS_EVAL) {
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->tcs_offchip_layout);
928 } else {
929 declare_vs_specific_input_sgprs(ctx, stage,
930 has_previous_stage,
931 previous_stage,
932 &args);
933 }
934
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_ring_stride);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->gsvs_num_entries);
939 if (ctx->shader_info->info.needs_multiview_view_index)
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->view_index);
942
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[0]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[2]);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_prim_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->abi.gs_invocation_id);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[4]);
953
954 if (previous_stage == MESA_SHADER_VERTEX) {
955 declare_vs_input_vgprs(ctx, &args);
956 } else {
957 declare_tes_input_vgprs(ctx, &args);
958 }
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_ring_stride);
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->gsvs_num_entries);
970 if (ctx->shader_info->info.needs_multiview_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->view_index);
973
974 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
975 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[0]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[1]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_prim_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[2]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[3]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[5]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->abi.gs_invocation_id);
992 }
993 break;
994 case MESA_SHADER_FRAGMENT:
995 declare_global_input_sgprs(ctx, stage, has_previous_stage,
996 previous_stage, &user_sgpr_info,
997 &args, &desc_sets);
998
999 if (ctx->shader_info->info.ps.needs_sample_positions)
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1001 &ctx->sample_pos_offset);
1002
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1020 break;
1021 default:
1022 unreachable("Shader stage not implemented");
1023 }
1024
1025 ctx->main_function = create_llvm_function(
1026 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1027 ctx->max_workgroup_size,
1028 ctx->options->unsafe_math);
1029 set_llvm_calling_convention(ctx->main_function, stage);
1030
1031
1032 ctx->shader_info->num_input_vgprs = 0;
1033 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1034
1035 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1036
1037 if (ctx->stage != MESA_SHADER_FRAGMENT)
1038 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1039
1040 assign_arguments(ctx->main_function, &args);
1041
1042 user_sgpr_idx = 0;
1043
1044 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1045 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1046 &user_sgpr_idx, 2);
1047 if (ctx->options->supports_spill) {
1048 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1049 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1050 NULL, 0, AC_FUNC_ATTR_READNONE);
1051 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1052 const_array(ctx->ac.v4i32, 16), "");
1053 }
1054 }
1055
1056 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1057 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1058 if (has_previous_stage)
1059 user_sgpr_idx = 0;
1060
1061 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1062 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1063
1064 switch (stage) {
1065 case MESA_SHADER_COMPUTE:
1066 if (ctx->shader_info->info.cs.uses_grid_size) {
1067 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1068 &user_sgpr_idx, 3);
1069 }
1070 break;
1071 case MESA_SHADER_VERTEX:
1072 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1073 previous_stage, &user_sgpr_idx);
1074 if (ctx->view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 if (ctx->options->key.vs.as_ls) {
1077 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1078 &user_sgpr_idx, 1);
1079 }
1080 if (ctx->options->key.vs.as_ls)
1081 ac_declare_lds_as_pointer(&ctx->ac);
1082 break;
1083 case MESA_SHADER_TESS_CTRL:
1084 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1085 previous_stage, &user_sgpr_idx);
1086 if (has_previous_stage)
1087 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1088 &user_sgpr_idx, 1);
1089 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1090 if (ctx->view_index)
1091 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1092 ac_declare_lds_as_pointer(&ctx->ac);
1093 break;
1094 case MESA_SHADER_TESS_EVAL:
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 break;
1099 case MESA_SHADER_GEOMETRY:
1100 if (has_previous_stage) {
1101 if (previous_stage == MESA_SHADER_VERTEX)
1102 set_vs_specific_input_locs(ctx, stage,
1103 has_previous_stage,
1104 previous_stage,
1105 &user_sgpr_idx);
1106 else
1107 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1108 &user_sgpr_idx, 1);
1109 }
1110 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1111 &user_sgpr_idx, 2);
1112 if (ctx->view_index)
1113 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1114 if (has_previous_stage)
1115 ac_declare_lds_as_pointer(&ctx->ac);
1116 break;
1117 case MESA_SHADER_FRAGMENT:
1118 if (ctx->shader_info->info.ps.needs_sample_positions) {
1119 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1120 &user_sgpr_idx, 1);
1121 }
1122 break;
1123 default:
1124 unreachable("Shader stage not implemented");
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static int get_llvm_num_components(LLVMValueRef value)
1131 {
1132 LLVMTypeRef type = LLVMTypeOf(value);
1133 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1134 ? LLVMGetVectorSize(type)
1135 : 1;
1136 return num_components;
1137 }
1138
1139 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1140 LLVMValueRef value,
1141 int index)
1142 {
1143 int count = get_llvm_num_components(value);
1144
1145 if (count == 1)
1146 return value;
1147
1148 return LLVMBuildExtractElement(ac->builder, value,
1149 LLVMConstInt(ac->i32, index, false), "");
1150 }
1151
1152 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1153 LLVMValueRef value, unsigned count)
1154 {
1155 unsigned num_components = get_llvm_num_components(value);
1156 if (count == num_components)
1157 return value;
1158
1159 LLVMValueRef masks[] = {
1160 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1161 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1162
1163 if (count == 1)
1164 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1165 "");
1166
1167 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1168 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1169 }
1170
1171 static void
1172 build_store_values_extended(struct ac_llvm_context *ac,
1173 LLVMValueRef *values,
1174 unsigned value_count,
1175 unsigned value_stride,
1176 LLVMValueRef vec)
1177 {
1178 LLVMBuilderRef builder = ac->builder;
1179 unsigned i;
1180
1181 for (i = 0; i < value_count; i++) {
1182 LLVMValueRef ptr = values[i * value_stride];
1183 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1184 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1185 LLVMBuildStore(builder, value, ptr);
1186 }
1187 }
1188
1189 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1190 const nir_ssa_def *def)
1191 {
1192 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1193 if (def->num_components > 1) {
1194 type = LLVMVectorType(type, def->num_components);
1195 }
1196 return type;
1197 }
1198
1199 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1200 {
1201 assert(src.is_ssa);
1202 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1203 return (LLVMValueRef)entry->data;
1204 }
1205
1206
1207 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1208 const struct nir_block *b)
1209 {
1210 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1211 return (LLVMBasicBlockRef)entry->data;
1212 }
1213
1214 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1215 nir_alu_src src,
1216 unsigned num_components)
1217 {
1218 LLVMValueRef value = get_src(ctx, src.src);
1219 bool need_swizzle = false;
1220
1221 assert(value);
1222 LLVMTypeRef type = LLVMTypeOf(value);
1223 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1224 ? LLVMGetVectorSize(type)
1225 : 1;
1226
1227 for (unsigned i = 0; i < num_components; ++i) {
1228 assert(src.swizzle[i] < src_components);
1229 if (src.swizzle[i] != i)
1230 need_swizzle = true;
1231 }
1232
1233 if (need_swizzle || num_components != src_components) {
1234 LLVMValueRef masks[] = {
1235 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1236 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1237 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1238 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1239
1240 if (src_components > 1 && num_components == 1) {
1241 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1242 masks[0], "");
1243 } else if (src_components == 1 && num_components > 1) {
1244 LLVMValueRef values[] = {value, value, value, value};
1245 value = ac_build_gather_values(&ctx->ac, values, num_components);
1246 } else {
1247 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1248 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1249 swizzle, "");
1250 }
1251 }
1252 assert(!src.negate);
1253 assert(!src.abs);
1254 return value;
1255 }
1256
1257 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1258 LLVMIntPredicate pred, LLVMValueRef src0,
1259 LLVMValueRef src1)
1260 {
1261 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1262 return LLVMBuildSelect(ctx->builder, result,
1263 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1264 ctx->i32_0, "");
1265 }
1266
1267 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1268 LLVMRealPredicate pred, LLVMValueRef src0,
1269 LLVMValueRef src1)
1270 {
1271 LLVMValueRef result;
1272 src0 = ac_to_float(ctx, src0);
1273 src1 = ac_to_float(ctx, src1);
1274 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1275 return LLVMBuildSelect(ctx->builder, result,
1276 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1277 ctx->i32_0, "");
1278 }
1279
1280 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 };
1289
1290 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1291 get_elem_bits(ctx, result_type));
1292 assert(length < sizeof(name));
1293 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1294 }
1295
1296 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1297 const char *intrin,
1298 LLVMTypeRef result_type,
1299 LLVMValueRef src0, LLVMValueRef src1)
1300 {
1301 char name[64];
1302 LLVMValueRef params[] = {
1303 ac_to_float(ctx, src0),
1304 ac_to_float(ctx, src1),
1305 };
1306
1307 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1308 get_elem_bits(ctx, result_type));
1309 assert(length < sizeof(name));
1310 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1311 }
1312
1313 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1314 const char *intrin,
1315 LLVMTypeRef result_type,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 char name[64];
1319 LLVMValueRef params[] = {
1320 ac_to_float(ctx, src0),
1321 ac_to_float(ctx, src1),
1322 ac_to_float(ctx, src2),
1323 };
1324
1325 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1326 get_elem_bits(ctx, result_type));
1327 assert(length < sizeof(name));
1328 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1329 }
1330
1331 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1333 {
1334 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1335 ctx->i32_0, "");
1336 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1337 }
1338
1339 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1340 LLVMIntPredicate pred,
1341 LLVMValueRef src0, LLVMValueRef src1)
1342 {
1343 return LLVMBuildSelect(ctx->builder,
1344 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1345 src0,
1346 src1, "");
1347
1348 }
1349 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1350 LLVMValueRef src0)
1351 {
1352 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1353 LLVMBuildNeg(ctx->builder, src0, ""));
1354 }
1355
1356 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0)
1358 {
1359 LLVMValueRef cmp, val;
1360
1361 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1362 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1363 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1364 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1365 return val;
1366 }
1367
1368 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1369 LLVMValueRef src0)
1370 {
1371 LLVMValueRef cmp, val;
1372
1373 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1374 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1375 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1376 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1377 return val;
1378 }
1379
1380 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1381 LLVMValueRef src0)
1382 {
1383 const char *intr = "llvm.floor.f32";
1384 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1385 LLVMValueRef params[] = {
1386 fsrc0,
1387 };
1388 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1389 ctx->f32, params, 1,
1390 AC_FUNC_ATTR_READNONE);
1391 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1392 }
1393
1394 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1395 const char *intrin,
1396 LLVMValueRef src0, LLVMValueRef src1)
1397 {
1398 LLVMTypeRef ret_type;
1399 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1400 LLVMValueRef res;
1401 LLVMValueRef params[] = { src0, src1 };
1402 ret_type = LLVMStructTypeInContext(ctx->context, types,
1403 2, true);
1404
1405 res = ac_build_intrinsic(ctx, intrin, ret_type,
1406 params, 2, AC_FUNC_ATTR_READNONE);
1407
1408 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1409 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1410 return res;
1411 }
1412
1413 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1414 LLVMValueRef src0)
1415 {
1416 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1417 }
1418
1419 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 src0 = ac_to_float(ctx, src0);
1423 return LLVMBuildSExt(ctx->builder,
1424 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1425 ctx->i32, "");
1426 }
1427
1428 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1429 LLVMValueRef src0)
1430 {
1431 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1432 }
1433
1434 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildSExt(ctx->builder,
1438 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1439 ctx->i32, "");
1440 }
1441
1442 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1443 LLVMValueRef src0)
1444 {
1445 LLVMValueRef result;
1446 LLVMValueRef cond = NULL;
1447
1448 src0 = ac_to_float(&ctx->ac, src0);
1449 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1450
1451 if (ctx->options->chip_class >= VI) {
1452 LLVMValueRef args[2];
1453 /* Check if the result is a denormal - and flush to 0 if so. */
1454 args[0] = result;
1455 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1456 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1457 }
1458
1459 /* need to convert back up to f32 */
1460 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1461
1462 if (ctx->options->chip_class >= VI)
1463 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1464 else {
1465 /* for SI/CIK */
1466 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1467 * so compare the result and flush to 0 if it's smaller.
1468 */
1469 LLVMValueRef temp, cond2;
1470 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1471 ctx->ac.f32, result);
1472 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1473 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1474 temp, "");
1475 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1476 temp, ctx->ac.f32_0, "");
1477 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1478 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1479 }
1480 return result;
1481 }
1482
1483 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1484 LLVMValueRef src0, LLVMValueRef src1)
1485 {
1486 LLVMValueRef dst64, result;
1487 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1488 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1489
1490 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1491 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1492 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1510 bool is_signed,
1511 const LLVMValueRef srcs[3])
1512 {
1513 LLVMValueRef result;
1514 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1515
1516 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1517 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1522 LLVMValueRef src0, LLVMValueRef src1,
1523 LLVMValueRef src2, LLVMValueRef src3)
1524 {
1525 LLVMValueRef bfi_args[3], result;
1526
1527 bfi_args[0] = LLVMBuildShl(ctx->builder,
1528 LLVMBuildSub(ctx->builder,
1529 LLVMBuildShl(ctx->builder,
1530 ctx->i32_1,
1531 src3, ""),
1532 ctx->i32_1, ""),
1533 src2, "");
1534 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1535 bfi_args[2] = src0;
1536
1537 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1538
1539 /* Calculate:
1540 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1541 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1542 */
1543 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1544 LLVMBuildAnd(ctx->builder, bfi_args[0],
1545 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1546
1547 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1548 return result;
1549 }
1550
1551 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1552 LLVMValueRef src0)
1553 {
1554 LLVMValueRef comp[2];
1555
1556 src0 = ac_to_float(ctx, src0);
1557 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1558 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1559
1560 return ac_build_cvt_pkrtz_f16(ctx, comp);
1561 }
1562
1563 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0)
1565 {
1566 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1567 LLVMValueRef temps[2], result, val;
1568 int i;
1569
1570 for (i = 0; i < 2; i++) {
1571 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1572 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1573 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1574 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1575 }
1576
1577 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1578 ctx->i32_0, "");
1579 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1580 ctx->i32_1, "");
1581 return result;
1582 }
1583
1584 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1585 nir_op op,
1586 LLVMValueRef src0)
1587 {
1588 unsigned mask;
1589 int idx;
1590 LLVMValueRef result;
1591
1592 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1593 mask = AC_TID_MASK_LEFT;
1594 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1595 mask = AC_TID_MASK_TOP;
1596 else
1597 mask = AC_TID_MASK_TOP_LEFT;
1598
1599 /* for DDX we want to next X pixel, DDY next Y pixel. */
1600 if (op == nir_op_fddx_fine ||
1601 op == nir_op_fddx_coarse ||
1602 op == nir_op_fddx)
1603 idx = 1;
1604 else
1605 idx = 2;
1606
1607 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1608 return result;
1609 }
1610
1611 /*
1612 * this takes an I,J coordinate pair,
1613 * and works out the X and Y derivatives.
1614 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1615 */
1616 static LLVMValueRef emit_ddxy_interp(
1617 struct ac_nir_context *ctx,
1618 LLVMValueRef interp_ij)
1619 {
1620 LLVMValueRef result[4], a;
1621 unsigned i;
1622
1623 for (i = 0; i < 2; i++) {
1624 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1625 LLVMConstInt(ctx->ac.i32, i, false), "");
1626 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1627 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1628 }
1629 return ac_build_gather_values(&ctx->ac, result, 4);
1630 }
1631
1632 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1633 {
1634 LLVMValueRef src[4], result = NULL;
1635 unsigned num_components = instr->dest.dest.ssa.num_components;
1636 unsigned src_components;
1637 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1638
1639 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1640 switch (instr->op) {
1641 case nir_op_vec2:
1642 case nir_op_vec3:
1643 case nir_op_vec4:
1644 src_components = 1;
1645 break;
1646 case nir_op_pack_half_2x16:
1647 src_components = 2;
1648 break;
1649 case nir_op_unpack_half_2x16:
1650 src_components = 1;
1651 break;
1652 default:
1653 src_components = num_components;
1654 break;
1655 }
1656 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1657 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1658
1659 switch (instr->op) {
1660 case nir_op_fmov:
1661 case nir_op_imov:
1662 result = src[0];
1663 break;
1664 case nir_op_fneg:
1665 src[0] = ac_to_float(&ctx->ac, src[0]);
1666 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1667 break;
1668 case nir_op_ineg:
1669 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1670 break;
1671 case nir_op_inot:
1672 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1673 break;
1674 case nir_op_iadd:
1675 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_fadd:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 src[1] = ac_to_float(&ctx->ac, src[1]);
1680 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1681 break;
1682 case nir_op_fsub:
1683 src[0] = ac_to_float(&ctx->ac, src[0]);
1684 src[1] = ac_to_float(&ctx->ac, src[1]);
1685 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_isub:
1688 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_imul:
1691 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_imod:
1694 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_umod:
1697 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fmod:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1704 ac_to_float_type(&ctx->ac, def_type), result);
1705 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1706 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1707 break;
1708 case nir_op_frem:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_irem:
1714 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_idiv:
1717 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_udiv:
1720 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_fmul:
1723 src[0] = ac_to_float(&ctx->ac, src[0]);
1724 src[1] = ac_to_float(&ctx->ac, src[1]);
1725 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_fdiv:
1728 src[0] = ac_to_float(&ctx->ac, src[0]);
1729 src[1] = ac_to_float(&ctx->ac, src[1]);
1730 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1731 break;
1732 case nir_op_frcp:
1733 src[0] = ac_to_float(&ctx->ac, src[0]);
1734 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1735 break;
1736 case nir_op_iand:
1737 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_ior:
1740 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_ixor:
1743 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_ishl:
1746 result = LLVMBuildShl(ctx->ac.builder, src[0],
1747 LLVMBuildZExt(ctx->ac.builder, src[1],
1748 LLVMTypeOf(src[0]), ""),
1749 "");
1750 break;
1751 case nir_op_ishr:
1752 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1753 LLVMBuildZExt(ctx->ac.builder, src[1],
1754 LLVMTypeOf(src[0]), ""),
1755 "");
1756 break;
1757 case nir_op_ushr:
1758 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1759 LLVMBuildZExt(ctx->ac.builder, src[1],
1760 LLVMTypeOf(src[0]), ""),
1761 "");
1762 break;
1763 case nir_op_ilt:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1765 break;
1766 case nir_op_ine:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1768 break;
1769 case nir_op_ieq:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1771 break;
1772 case nir_op_ige:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1774 break;
1775 case nir_op_ult:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1777 break;
1778 case nir_op_uge:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1780 break;
1781 case nir_op_feq:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1783 break;
1784 case nir_op_fne:
1785 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1786 break;
1787 case nir_op_flt:
1788 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1789 break;
1790 case nir_op_fge:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1792 break;
1793 case nir_op_fabs:
1794 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1795 ac_to_float_type(&ctx->ac, def_type), src[0]);
1796 break;
1797 case nir_op_iabs:
1798 result = emit_iabs(&ctx->ac, src[0]);
1799 break;
1800 case nir_op_imax:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1802 break;
1803 case nir_op_imin:
1804 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1805 break;
1806 case nir_op_umax:
1807 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1808 break;
1809 case nir_op_umin:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1811 break;
1812 case nir_op_isign:
1813 result = emit_isign(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fsign:
1816 src[0] = ac_to_float(&ctx->ac, src[0]);
1817 result = emit_fsign(&ctx->ac, src[0]);
1818 break;
1819 case nir_op_ffloor:
1820 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1821 ac_to_float_type(&ctx->ac, def_type), src[0]);
1822 break;
1823 case nir_op_ftrunc:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fceil:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_fround_even:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1833 ac_to_float_type(&ctx->ac, def_type),src[0]);
1834 break;
1835 case nir_op_ffract:
1836 result = emit_ffract(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_fsin:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_fcos:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 break;
1846 case nir_op_fsqrt:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1848 ac_to_float_type(&ctx->ac, def_type), src[0]);
1849 break;
1850 case nir_op_fexp2:
1851 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1852 ac_to_float_type(&ctx->ac, def_type), src[0]);
1853 break;
1854 case nir_op_flog2:
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1856 ac_to_float_type(&ctx->ac, def_type), src[0]);
1857 break;
1858 case nir_op_frsq:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1862 break;
1863 case nir_op_fpow:
1864 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1865 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1866 break;
1867 case nir_op_fmax:
1868 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1869 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1870 if (instr->dest.dest.ssa.bit_size == 32)
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1872 ac_to_float_type(&ctx->ac, def_type),
1873 result);
1874 break;
1875 case nir_op_fmin:
1876 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1877 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1878 if (instr->dest.dest.ssa.bit_size == 32)
1879 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1880 ac_to_float_type(&ctx->ac, def_type),
1881 result);
1882 break;
1883 case nir_op_ffma:
1884 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1885 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1886 break;
1887 case nir_op_ibitfield_extract:
1888 result = emit_bitfield_extract(&ctx->ac, true, src);
1889 break;
1890 case nir_op_ubitfield_extract:
1891 result = emit_bitfield_extract(&ctx->ac, false, src);
1892 break;
1893 case nir_op_bitfield_insert:
1894 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1895 break;
1896 case nir_op_bitfield_reverse:
1897 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1898 break;
1899 case nir_op_bit_count:
1900 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1901 break;
1902 case nir_op_vec2:
1903 case nir_op_vec3:
1904 case nir_op_vec4:
1905 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1906 src[i] = ac_to_integer(&ctx->ac, src[i]);
1907 result = ac_build_gather_values(&ctx->ac, src, num_components);
1908 break;
1909 case nir_op_f2i32:
1910 case nir_op_f2i64:
1911 src[0] = ac_to_float(&ctx->ac, src[0]);
1912 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1913 break;
1914 case nir_op_f2u32:
1915 case nir_op_f2u64:
1916 src[0] = ac_to_float(&ctx->ac, src[0]);
1917 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2f32:
1920 case nir_op_i2f64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1923 break;
1924 case nir_op_u2f32:
1925 case nir_op_u2f64:
1926 src[0] = ac_to_integer(&ctx->ac, src[0]);
1927 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1928 break;
1929 case nir_op_f2f64:
1930 src[0] = ac_to_float(&ctx->ac, src[0]);
1931 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1932 break;
1933 case nir_op_f2f32:
1934 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1935 break;
1936 case nir_op_u2u32:
1937 case nir_op_u2u64:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1940 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1941 else
1942 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1943 break;
1944 case nir_op_i2i32:
1945 case nir_op_i2i64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1948 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1949 else
1950 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1951 break;
1952 case nir_op_bcsel:
1953 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1954 break;
1955 case nir_op_find_lsb:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1958 break;
1959 case nir_op_ufind_msb:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1962 break;
1963 case nir_op_ifind_msb:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1966 break;
1967 case nir_op_uadd_carry:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 src[1] = ac_to_integer(&ctx->ac, src[1]);
1970 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1971 break;
1972 case nir_op_usub_borrow:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 src[1] = ac_to_integer(&ctx->ac, src[1]);
1975 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1976 break;
1977 case nir_op_b2f:
1978 result = emit_b2f(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_f2b:
1981 result = emit_f2b(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_b2i:
1984 result = emit_b2i(&ctx->ac, src[0]);
1985 break;
1986 case nir_op_i2b:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = emit_i2b(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_fquantize2f16:
1991 result = emit_f2f16(ctx->nctx, src[0]);
1992 break;
1993 case nir_op_umul_high:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1997 break;
1998 case nir_op_imul_high:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 src[1] = ac_to_integer(&ctx->ac, src[1]);
2001 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2002 break;
2003 case nir_op_pack_half_2x16:
2004 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_unpack_half_2x16:
2007 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2008 break;
2009 case nir_op_fddx:
2010 case nir_op_fddy:
2011 case nir_op_fddx_fine:
2012 case nir_op_fddy_fine:
2013 case nir_op_fddx_coarse:
2014 case nir_op_fddy_coarse:
2015 result = emit_ddxy(ctx, instr->op, src[0]);
2016 break;
2017
2018 case nir_op_unpack_64_2x32_split_x: {
2019 assert(instr->src[0].src.ssa->num_components == 1);
2020 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2021 ctx->ac.v2i32,
2022 "");
2023 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2024 ctx->ac.i32_0, "");
2025 break;
2026 }
2027
2028 case nir_op_unpack_64_2x32_split_y: {
2029 assert(instr->src[0].src.ssa->num_components == 1);
2030 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2031 ctx->ac.v2i32,
2032 "");
2033 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2034 ctx->ac.i32_1, "");
2035 break;
2036 }
2037
2038 case nir_op_pack_64_2x32_split: {
2039 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2040 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2041 src[0], ctx->ac.i32_0, "");
2042 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2043 src[1], ctx->ac.i32_1, "");
2044 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2045 break;
2046 }
2047
2048 default:
2049 fprintf(stderr, "Unknown NIR alu instr: ");
2050 nir_print_instr(&instr->instr, stderr);
2051 fprintf(stderr, "\n");
2052 abort();
2053 }
2054
2055 if (result) {
2056 assert(instr->dest.dest.is_ssa);
2057 result = ac_to_integer(&ctx->ac, result);
2058 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2059 result);
2060 }
2061 }
2062
2063 static void visit_load_const(struct ac_nir_context *ctx,
2064 const nir_load_const_instr *instr)
2065 {
2066 LLVMValueRef values[4], value = NULL;
2067 LLVMTypeRef element_type =
2068 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2069
2070 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2071 switch (instr->def.bit_size) {
2072 case 32:
2073 values[i] = LLVMConstInt(element_type,
2074 instr->value.u32[i], false);
2075 break;
2076 case 64:
2077 values[i] = LLVMConstInt(element_type,
2078 instr->value.u64[i], false);
2079 break;
2080 default:
2081 fprintf(stderr,
2082 "unsupported nir load_const bit_size: %d\n",
2083 instr->def.bit_size);
2084 abort();
2085 }
2086 }
2087 if (instr->def.num_components > 1) {
2088 value = LLVMConstVector(values, instr->def.num_components);
2089 } else
2090 value = values[0];
2091
2092 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2093 }
2094
2095 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2096 LLVMTypeRef type)
2097 {
2098 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2099 return LLVMBuildBitCast(ctx->builder, ptr,
2100 LLVMPointerType(type, addr_space), "");
2101 }
2102
2103 static LLVMValueRef
2104 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2105 {
2106 LLVMValueRef size =
2107 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2108 LLVMConstInt(ctx->ac.i32, 2, false), "");
2109
2110 /* VI only */
2111 if (ctx->ac.chip_class == VI && in_elements) {
2112 /* On VI, the descriptor contains the size in bytes,
2113 * but TXQ must return the size in elements.
2114 * The stride is always non-zero for resources using TXQ.
2115 */
2116 LLVMValueRef stride =
2117 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2118 ctx->ac.i32_1, "");
2119 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2120 LLVMConstInt(ctx->ac.i32, 16, false), "");
2121 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2122 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2123
2124 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2125 }
2126 return size;
2127 }
2128
2129 /**
2130 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2131 * intrinsic names).
2132 */
2133 static void build_int_type_name(
2134 LLVMTypeRef type,
2135 char *buf, unsigned bufsize)
2136 {
2137 assert(bufsize >= 6);
2138
2139 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2140 snprintf(buf, bufsize, "v%ui32",
2141 LLVMGetVectorSize(type));
2142 else
2143 strcpy(buf, "i32");
2144 }
2145
2146 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2147 struct ac_image_args *args,
2148 const nir_tex_instr *instr)
2149 {
2150 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2151 LLVMValueRef coord = args->addr;
2152 LLVMValueRef half_texel[2];
2153 LLVMValueRef compare_cube_wa = NULL;
2154 LLVMValueRef result;
2155 int c;
2156 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2157
2158 //TODO Rect
2159 {
2160 struct ac_image_args txq_args = { 0 };
2161
2162 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2163 txq_args.opcode = ac_image_get_resinfo;
2164 txq_args.dmask = 0xf;
2165 txq_args.addr = ctx->i32_0;
2166 txq_args.resource = args->resource;
2167 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2168
2169 for (c = 0; c < 2; c++) {
2170 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2171 LLVMConstInt(ctx->i32, c, false), "");
2172 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2173 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2174 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2175 LLVMConstReal(ctx->f32, -0.5), "");
2176 }
2177 }
2178
2179 LLVMValueRef orig_coords = args->addr;
2180
2181 for (c = 0; c < 2; c++) {
2182 LLVMValueRef tmp;
2183 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2184 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2185 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2186 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2187 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2188 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2189 }
2190
2191
2192 /*
2193 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2194 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2195 * workaround by sampling using a scaled type and converting.
2196 * This is taken from amdgpu-pro shaders.
2197 */
2198 /* NOTE this produces some ugly code compared to amdgpu-pro,
2199 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2200 * and then reads them back. -pro generates two selects,
2201 * one s_cmp for the descriptor rewriting
2202 * one v_cmp for the coordinate and result changes.
2203 */
2204 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2205 LLVMValueRef tmp, tmp2;
2206
2207 /* workaround 8/8/8/8 uint/sint cube gather bug */
2208 /* first detect it then change to a scaled read and f2i */
2209 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2210 tmp2 = tmp;
2211
2212 /* extract the DATA_FORMAT */
2213 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2214 LLVMConstInt(ctx->i32, 6, false), false);
2215
2216 /* is the DATA_FORMAT == 8_8_8_8 */
2217 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2218
2219 if (stype == GLSL_TYPE_UINT)
2220 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2221 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2222 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2223 else
2224 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2225 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2226 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2227
2228 /* replace the NUM FORMAT in the descriptor */
2229 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2230 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2231
2232 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2233
2234 /* don't modify the coordinates for this case */
2235 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2236 }
2237 args->addr = coord;
2238 result = ac_build_image_opcode(ctx, args);
2239
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2241 LLVMValueRef tmp, tmp2;
2242
2243 /* if the cube workaround is in place, f2i the result. */
2244 for (c = 0; c < 4; c++) {
2245 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2246 if (stype == GLSL_TYPE_UINT)
2247 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2248 else
2249 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2250 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2251 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2252 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2253 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2254 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2255 }
2256 }
2257 return result;
2258 }
2259
2260 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2261 const nir_tex_instr *instr,
2262 bool lod_is_zero,
2263 struct ac_image_args *args)
2264 {
2265 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2266 return ac_build_buffer_load_format(&ctx->ac,
2267 args->resource,
2268 args->addr,
2269 ctx->ac.i32_0,
2270 true);
2271 }
2272
2273 args->opcode = ac_image_sample;
2274 args->compare = instr->is_shadow;
2275
2276 switch (instr->op) {
2277 case nir_texop_txf:
2278 case nir_texop_txf_ms:
2279 case nir_texop_samples_identical:
2280 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2281 args->compare = false;
2282 args->offset = false;
2283 break;
2284 case nir_texop_txb:
2285 args->bias = true;
2286 break;
2287 case nir_texop_txl:
2288 if (lod_is_zero)
2289 args->level_zero = true;
2290 else
2291 args->lod = true;
2292 break;
2293 case nir_texop_txs:
2294 case nir_texop_query_levels:
2295 args->opcode = ac_image_get_resinfo;
2296 break;
2297 case nir_texop_tex:
2298 if (ctx->stage != MESA_SHADER_FRAGMENT)
2299 args->level_zero = true;
2300 break;
2301 case nir_texop_txd:
2302 args->deriv = true;
2303 break;
2304 case nir_texop_tg4:
2305 args->opcode = ac_image_gather4;
2306 args->level_zero = true;
2307 break;
2308 case nir_texop_lod:
2309 args->opcode = ac_image_get_lod;
2310 args->compare = false;
2311 args->offset = false;
2312 break;
2313 default:
2314 break;
2315 }
2316
2317 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2318 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2319 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2320 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2321 }
2322 }
2323 return ac_build_image_opcode(&ctx->ac, args);
2324 }
2325
2326 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2327 nir_intrinsic_instr *instr)
2328 {
2329 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2330 unsigned desc_set = nir_intrinsic_desc_set(instr);
2331 unsigned binding = nir_intrinsic_binding(instr);
2332 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2333 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2334 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2335 unsigned base_offset = layout->binding[binding].offset;
2336 LLVMValueRef offset, stride;
2337
2338 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2339 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2340 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2341 layout->binding[binding].dynamic_offset_offset;
2342 desc_ptr = ctx->push_constants;
2343 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2344 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2345 } else
2346 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2347
2348 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2349 index = LLVMBuildMul(ctx->builder, index, stride, "");
2350 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2351
2352 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2353 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2354 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2355
2356 return desc_ptr;
2357 }
2358
2359 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2360 nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2363 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2364
2365 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2366 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2367 return result;
2368 }
2369
2370 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2371 nir_intrinsic_instr *instr)
2372 {
2373 LLVMValueRef ptr, addr;
2374
2375 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2376 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2377
2378 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2379 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2380
2381 return LLVMBuildLoad(ctx->builder, ptr, "");
2382 }
2383
2384 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2388
2389 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2390 }
2391 static void visit_store_ssbo(struct ac_nir_context *ctx,
2392 nir_intrinsic_instr *instr)
2393 {
2394 const char *store_name;
2395 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2396 LLVMTypeRef data_type = ctx->ac.f32;
2397 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2398 int components_32bit = elem_size_mult * instr->num_components;
2399 unsigned writemask = nir_intrinsic_write_mask(instr);
2400 LLVMValueRef base_data, base_offset;
2401 LLVMValueRef params[6];
2402
2403 params[1] = ctx->abi->load_ssbo(ctx->abi,
2404 get_src(ctx, instr->src[1]), true);
2405 params[2] = ctx->ac.i32_0; /* vindex */
2406 params[4] = ctx->ac.i1false; /* glc */
2407 params[5] = ctx->ac.i1false; /* slc */
2408
2409 if (components_32bit > 1)
2410 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2411
2412 base_data = ac_to_float(&ctx->ac, src_data);
2413 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2414 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2415 data_type, "");
2416 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2417 while (writemask) {
2418 int start, count;
2419 LLVMValueRef data;
2420 LLVMValueRef offset;
2421 LLVMValueRef tmp;
2422 u_bit_scan_consecutive_range(&writemask, &start, &count);
2423
2424 /* Due to an LLVM limitation, split 3-element writes
2425 * into a 2-element and a 1-element write. */
2426 if (count == 3) {
2427 writemask |= 1 << (start + 2);
2428 count = 2;
2429 }
2430
2431 start *= elem_size_mult;
2432 count *= elem_size_mult;
2433
2434 if (count > 4) {
2435 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2436 count = 4;
2437 }
2438
2439 if (count == 4) {
2440 store_name = "llvm.amdgcn.buffer.store.v4f32";
2441 data = base_data;
2442 } else if (count == 2) {
2443 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2444 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2445 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2446 ctx->ac.i32_0, "");
2447
2448 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2449 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2450 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2451 ctx->ac.i32_1, "");
2452 store_name = "llvm.amdgcn.buffer.store.v2f32";
2453
2454 } else {
2455 assert(count == 1);
2456 if (get_llvm_num_components(base_data) > 1)
2457 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2458 LLVMConstInt(ctx->ac.i32, start, false), "");
2459 else
2460 data = base_data;
2461 store_name = "llvm.amdgcn.buffer.store.f32";
2462 }
2463
2464 offset = base_offset;
2465 if (start != 0) {
2466 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2467 }
2468 params[0] = data;
2469 params[3] = offset;
2470 ac_build_intrinsic(&ctx->ac, store_name,
2471 ctx->ac.voidt, params, 6, 0);
2472 }
2473 }
2474
2475 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 const char *name;
2479 LLVMValueRef params[6];
2480 int arg_count = 0;
2481
2482 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2483 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2484 }
2485 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2486 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2487 get_src(ctx, instr->src[0]),
2488 true);
2489 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2490 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2491 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2492
2493 switch (instr->intrinsic) {
2494 case nir_intrinsic_ssbo_atomic_add:
2495 name = "llvm.amdgcn.buffer.atomic.add";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_imin:
2498 name = "llvm.amdgcn.buffer.atomic.smin";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_umin:
2501 name = "llvm.amdgcn.buffer.atomic.umin";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_imax:
2504 name = "llvm.amdgcn.buffer.atomic.smax";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_umax:
2507 name = "llvm.amdgcn.buffer.atomic.umax";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_and:
2510 name = "llvm.amdgcn.buffer.atomic.and";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_or:
2513 name = "llvm.amdgcn.buffer.atomic.or";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_xor:
2516 name = "llvm.amdgcn.buffer.atomic.xor";
2517 break;
2518 case nir_intrinsic_ssbo_atomic_exchange:
2519 name = "llvm.amdgcn.buffer.atomic.swap";
2520 break;
2521 case nir_intrinsic_ssbo_atomic_comp_swap:
2522 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2523 break;
2524 default:
2525 abort();
2526 }
2527
2528 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2529 }
2530
2531 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2532 const nir_intrinsic_instr *instr)
2533 {
2534 LLVMValueRef results[2];
2535 int load_components;
2536 int num_components = instr->num_components;
2537 if (instr->dest.ssa.bit_size == 64)
2538 num_components *= 2;
2539
2540 for (int i = 0; i < num_components; i += load_components) {
2541 load_components = MIN2(num_components - i, 4);
2542 const char *load_name;
2543 LLVMTypeRef data_type = ctx->ac.f32;
2544 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2545 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2546
2547 if (load_components == 3)
2548 data_type = LLVMVectorType(ctx->ac.f32, 4);
2549 else if (load_components > 1)
2550 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2551
2552 if (load_components >= 3)
2553 load_name = "llvm.amdgcn.buffer.load.v4f32";
2554 else if (load_components == 2)
2555 load_name = "llvm.amdgcn.buffer.load.v2f32";
2556 else if (load_components == 1)
2557 load_name = "llvm.amdgcn.buffer.load.f32";
2558 else
2559 unreachable("unhandled number of components");
2560
2561 LLVMValueRef params[] = {
2562 ctx->abi->load_ssbo(ctx->abi,
2563 get_src(ctx, instr->src[0]),
2564 false),
2565 ctx->ac.i32_0,
2566 offset,
2567 ctx->ac.i1false,
2568 ctx->ac.i1false,
2569 };
2570
2571 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2572
2573 }
2574
2575 assume(results[0]);
2576 LLVMValueRef ret = results[0];
2577 if (num_components > 4 || num_components == 3) {
2578 LLVMValueRef masks[] = {
2579 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2580 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2581 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2582 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2583 };
2584
2585 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2586 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2587 results[num_components > 4 ? 1 : 0], swizzle, "");
2588 }
2589
2590 return LLVMBuildBitCast(ctx->ac.builder, ret,
2591 get_def_type(ctx, &instr->dest.ssa), "");
2592 }
2593
2594 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2595 const nir_intrinsic_instr *instr)
2596 {
2597 LLVMValueRef results[8], ret;
2598 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2599 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2600 int num_components = instr->num_components;
2601
2602 if (ctx->abi->load_ubo)
2603 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2604
2605 if (instr->dest.ssa.bit_size == 64)
2606 num_components *= 2;
2607
2608 for (unsigned i = 0; i < num_components; ++i) {
2609 LLVMValueRef params[] = {
2610 rsrc,
2611 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2612 offset, "")
2613 };
2614 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2615 params, 2,
2616 AC_FUNC_ATTR_READNONE |
2617 AC_FUNC_ATTR_LEGACY);
2618 }
2619
2620
2621 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2622 return LLVMBuildBitCast(ctx->ac.builder, ret,
2623 get_def_type(ctx, &instr->dest.ssa), "");
2624 }
2625
2626 static void
2627 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2628 bool vs_in, unsigned *vertex_index_out,
2629 LLVMValueRef *vertex_index_ref,
2630 unsigned *const_out, LLVMValueRef *indir_out)
2631 {
2632 unsigned const_offset = 0;
2633 nir_deref *tail = &deref->deref;
2634 LLVMValueRef offset = NULL;
2635
2636 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2637 tail = tail->child;
2638 nir_deref_array *deref_array = nir_deref_as_array(tail);
2639 if (vertex_index_out)
2640 *vertex_index_out = deref_array->base_offset;
2641
2642 if (vertex_index_ref) {
2643 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2644 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2645 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2646 }
2647 *vertex_index_ref = vtx;
2648 }
2649 }
2650
2651 if (deref->var->data.compact) {
2652 assert(tail->child->deref_type == nir_deref_type_array);
2653 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2654 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2655 /* We always lower indirect dereferences for "compact" array vars. */
2656 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2657
2658 const_offset = deref_array->base_offset;
2659 goto out;
2660 }
2661
2662 while (tail->child != NULL) {
2663 const struct glsl_type *parent_type = tail->type;
2664 tail = tail->child;
2665
2666 if (tail->deref_type == nir_deref_type_array) {
2667 nir_deref_array *deref_array = nir_deref_as_array(tail);
2668 LLVMValueRef index, stride, local_offset;
2669 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2670
2671 const_offset += size * deref_array->base_offset;
2672 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2673 continue;
2674
2675 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2676 index = get_src(ctx, deref_array->indirect);
2677 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2678 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2679
2680 if (offset)
2681 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2682 else
2683 offset = local_offset;
2684 } else if (tail->deref_type == nir_deref_type_struct) {
2685 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2686
2687 for (unsigned i = 0; i < deref_struct->index; i++) {
2688 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2689 const_offset += glsl_count_attribute_slots(ft, vs_in);
2690 }
2691 } else
2692 unreachable("unsupported deref type");
2693
2694 }
2695 out:
2696 if (const_offset && offset)
2697 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2698 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2699 "");
2700
2701 *const_out = const_offset;
2702 *indir_out = offset;
2703 }
2704
2705
2706 /* The offchip buffer layout for TCS->TES is
2707 *
2708 * - attribute 0 of patch 0 vertex 0
2709 * - attribute 0 of patch 0 vertex 1
2710 * - attribute 0 of patch 0 vertex 2
2711 * ...
2712 * - attribute 0 of patch 1 vertex 0
2713 * - attribute 0 of patch 1 vertex 1
2714 * ...
2715 * - attribute 1 of patch 0 vertex 0
2716 * - attribute 1 of patch 0 vertex 1
2717 * ...
2718 * - per patch attribute 0 of patch 0
2719 * - per patch attribute 0 of patch 1
2720 * ...
2721 *
2722 * Note that every attribute has 4 components.
2723 */
2724 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2725 LLVMValueRef vertex_index,
2726 LLVMValueRef param_index)
2727 {
2728 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2729 LLVMValueRef param_stride, constant16;
2730 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2731
2732 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2733 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2734 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2735 num_patches, "");
2736
2737 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2738 if (vertex_index) {
2739 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2740 vertices_per_patch, "");
2741
2742 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2743 vertex_index, "");
2744
2745 param_stride = total_vertices;
2746 } else {
2747 base_addr = rel_patch_id;
2748 param_stride = num_patches;
2749 }
2750
2751 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2752 LLVMBuildMul(ctx->builder, param_index,
2753 param_stride, ""), "");
2754
2755 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2756
2757 if (!vertex_index) {
2758 LLVMValueRef patch_data_offset =
2759 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2760
2761 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2762 patch_data_offset, "");
2763 }
2764 return base_addr;
2765 }
2766
2767 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2768 unsigned param,
2769 unsigned const_index,
2770 bool is_compact,
2771 LLVMValueRef vertex_index,
2772 LLVMValueRef indir_index)
2773 {
2774 LLVMValueRef param_index;
2775
2776 if (indir_index)
2777 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2778 indir_index, "");
2779 else {
2780 if (const_index && !is_compact)
2781 param += const_index;
2782 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2783 }
2784 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2785 }
2786
2787 static void
2788 mark_tess_output(struct nir_to_llvm_context *ctx,
2789 bool is_patch, uint32_t param)
2790
2791 {
2792 if (is_patch) {
2793 ctx->tess_patch_outputs_written |= (1ull << param);
2794 } else
2795 ctx->tess_outputs_written |= (1ull << param);
2796 }
2797
2798 static LLVMValueRef
2799 get_dw_address(struct nir_to_llvm_context *ctx,
2800 LLVMValueRef dw_addr,
2801 unsigned param,
2802 unsigned const_index,
2803 bool compact_const_index,
2804 LLVMValueRef vertex_index,
2805 LLVMValueRef stride,
2806 LLVMValueRef indir_index)
2807
2808 {
2809
2810 if (vertex_index) {
2811 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2812 LLVMBuildMul(ctx->builder,
2813 vertex_index,
2814 stride, ""), "");
2815 }
2816
2817 if (indir_index)
2818 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2819 LLVMBuildMul(ctx->builder, indir_index,
2820 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2821 else if (const_index && !compact_const_index)
2822 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2823 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2824
2825 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2826 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2827
2828 if (const_index && compact_const_index)
2829 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2830 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2831 return dw_addr;
2832 }
2833
2834 static LLVMValueRef
2835 load_tcs_input(struct ac_shader_abi *abi,
2836 LLVMValueRef vertex_index,
2837 LLVMValueRef indir_index,
2838 unsigned const_index,
2839 unsigned location,
2840 unsigned driver_location,
2841 unsigned component,
2842 unsigned num_components,
2843 bool is_patch,
2844 bool is_compact)
2845 {
2846 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2847 LLVMValueRef dw_addr, stride;
2848 LLVMValueRef value[4], result;
2849 unsigned param = shader_io_get_unique_index(location);
2850
2851 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2852 dw_addr = get_tcs_in_current_patch_offset(ctx);
2853 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2854 indir_index);
2855
2856 for (unsigned i = 0; i < num_components + component; i++) {
2857 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2858 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2859 ctx->ac.i32_1, "");
2860 }
2861 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2862 return result;
2863 }
2864
2865 static LLVMValueRef
2866 load_tcs_output(struct nir_to_llvm_context *ctx,
2867 nir_intrinsic_instr *instr)
2868 {
2869 LLVMValueRef dw_addr;
2870 LLVMValueRef stride = NULL;
2871 LLVMValueRef value[4], result;
2872 LLVMValueRef vertex_index = NULL;
2873 LLVMValueRef indir_index = NULL;
2874 unsigned const_index = 0;
2875 unsigned param;
2876 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2877 const bool is_compact = instr->variables[0]->var->data.compact;
2878 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2879 get_deref_offset(ctx->nir, instr->variables[0],
2880 false, NULL, per_vertex ? &vertex_index : NULL,
2881 &const_index, &indir_index);
2882
2883 if (!instr->variables[0]->var->data.patch) {
2884 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2885 dw_addr = get_tcs_out_current_patch_offset(ctx);
2886 } else {
2887 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2888 }
2889
2890 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2891 indir_index);
2892
2893 unsigned comp = instr->variables[0]->var->data.location_frac;
2894 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2895 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2896 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2897 ctx->ac.i32_1, "");
2898 }
2899 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2900 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2901 return result;
2902 }
2903
2904 static void
2905 store_tcs_output(struct ac_shader_abi *abi,
2906 LLVMValueRef vertex_index,
2907 LLVMValueRef param_index,
2908 unsigned const_index,
2909 unsigned location,
2910 unsigned driver_location,
2911 LLVMValueRef src,
2912 unsigned component,
2913 bool is_patch,
2914 bool is_compact,
2915 unsigned writemask)
2916 {
2917 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2918 LLVMValueRef dw_addr;
2919 LLVMValueRef stride = NULL;
2920 LLVMValueRef buf_addr = NULL;
2921 unsigned param;
2922 bool store_lds = true;
2923
2924 if (is_patch) {
2925 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2926 store_lds = false;
2927 } else {
2928 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2929 store_lds = false;
2930 }
2931
2932 param = shader_io_get_unique_index(location);
2933 if (location == VARYING_SLOT_CLIP_DIST0 &&
2934 is_compact && const_index > 3) {
2935 const_index -= 3;
2936 param++;
2937 }
2938
2939 if (!is_patch) {
2940 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2941 dw_addr = get_tcs_out_current_patch_offset(ctx);
2942 } else {
2943 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2944 }
2945
2946 mark_tess_output(ctx, is_patch, param);
2947
2948 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2949 param_index);
2950 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2951 vertex_index, param_index);
2952
2953 bool is_tess_factor = false;
2954 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2955 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2956 is_tess_factor = true;
2957
2958 unsigned base = is_compact ? const_index : 0;
2959 for (unsigned chan = 0; chan < 8; chan++) {
2960 if (!(writemask & (1 << chan)))
2961 continue;
2962 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - component);
2963
2964 if (store_lds || is_tess_factor)
2965 ac_lds_store(&ctx->ac, dw_addr, value);
2966
2967 if (!is_tess_factor && writemask != 0xF)
2968 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2969 buf_addr, ctx->oc_lds,
2970 4 * (base + chan), 1, 0, true, false);
2971
2972 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2973 ctx->ac.i32_1, "");
2974 }
2975
2976 if (writemask == 0xF) {
2977 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2978 buf_addr, ctx->oc_lds,
2979 (base * 4), 1, 0, true, false);
2980 }
2981 }
2982
2983 static LLVMValueRef
2984 load_tes_input(struct ac_shader_abi *abi,
2985 LLVMValueRef vertex_index,
2986 LLVMValueRef param_index,
2987 unsigned const_index,
2988 unsigned location,
2989 unsigned driver_location,
2990 unsigned component,
2991 unsigned num_components,
2992 bool is_patch,
2993 bool is_compact)
2994 {
2995 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2996 LLVMValueRef buf_addr;
2997 LLVMValueRef result;
2998 unsigned param = shader_io_get_unique_index(location);
2999
3000 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3001 const_index -= 3;
3002 param++;
3003 }
3004
3005 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3006 is_compact, vertex_index, param_index);
3007
3008 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3009 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3010
3011 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3012 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3013 result = trim_vector(&ctx->ac, result, num_components);
3014 return result;
3015 }
3016
3017 static LLVMValueRef
3018 load_gs_input(struct ac_shader_abi *abi,
3019 unsigned location,
3020 unsigned driver_location,
3021 unsigned component,
3022 unsigned num_components,
3023 unsigned vertex_index,
3024 unsigned const_index,
3025 LLVMTypeRef type)
3026 {
3027 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3028 LLVMValueRef vtx_offset;
3029 LLVMValueRef args[9];
3030 unsigned param, vtx_offset_param;
3031 LLVMValueRef value[4], result;
3032
3033 vtx_offset_param = vertex_index;
3034 assert(vtx_offset_param < 6);
3035 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3036 LLVMConstInt(ctx->ac.i32, 4, false), "");
3037
3038 param = shader_io_get_unique_index(location);
3039
3040 for (unsigned i = component; i < num_components + component; i++) {
3041 if (ctx->ac.chip_class >= GFX9) {
3042 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3043 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3044 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3045 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3046 } else {
3047 args[0] = ctx->esgs_ring;
3048 args[1] = vtx_offset;
3049 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3050 args[3] = ctx->ac.i32_0;
3051 args[4] = ctx->ac.i32_1; /* OFFEN */
3052 args[5] = ctx->ac.i32_0; /* IDXEN */
3053 args[6] = ctx->ac.i32_1; /* GLC */
3054 args[7] = ctx->ac.i32_0; /* SLC */
3055 args[8] = ctx->ac.i32_0; /* TFE */
3056
3057 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3058 ctx->ac.i32, args, 9,
3059 AC_FUNC_ATTR_READONLY |
3060 AC_FUNC_ATTR_LEGACY);
3061 }
3062 }
3063 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3064
3065 return result;
3066 }
3067
3068 static LLVMValueRef
3069 build_gep_for_deref(struct ac_nir_context *ctx,
3070 nir_deref_var *deref)
3071 {
3072 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3073 assert(entry->data);
3074 LLVMValueRef val = entry->data;
3075 nir_deref *tail = deref->deref.child;
3076 while (tail != NULL) {
3077 LLVMValueRef offset;
3078 switch (tail->deref_type) {
3079 case nir_deref_type_array: {
3080 nir_deref_array *array = nir_deref_as_array(tail);
3081 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3082 if (array->deref_array_type ==
3083 nir_deref_array_type_indirect) {
3084 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3085 get_src(ctx,
3086 array->indirect),
3087 "");
3088 }
3089 break;
3090 }
3091 case nir_deref_type_struct: {
3092 nir_deref_struct *deref_struct =
3093 nir_deref_as_struct(tail);
3094 offset = LLVMConstInt(ctx->ac.i32,
3095 deref_struct->index, 0);
3096 break;
3097 }
3098 default:
3099 unreachable("bad deref type");
3100 }
3101 val = ac_build_gep0(&ctx->ac, val, offset);
3102 tail = tail->child;
3103 }
3104 return val;
3105 }
3106
3107 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3108 nir_intrinsic_instr *instr)
3109 {
3110 LLVMValueRef values[8];
3111 int idx = instr->variables[0]->var->data.driver_location;
3112 int ve = instr->dest.ssa.num_components;
3113 unsigned comp = instr->variables[0]->var->data.location_frac;
3114 LLVMValueRef indir_index;
3115 LLVMValueRef ret;
3116 unsigned const_index;
3117 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3118 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3119 instr->variables[0]->var->data.mode == nir_var_shader_in;
3120 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3121 &const_index, &indir_index);
3122
3123 if (instr->dest.ssa.bit_size == 64)
3124 ve *= 2;
3125
3126 switch (instr->variables[0]->var->data.mode) {
3127 case nir_var_shader_in:
3128 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3129 ctx->stage == MESA_SHADER_TESS_EVAL) {
3130 LLVMValueRef result;
3131 LLVMValueRef vertex_index = NULL;
3132 LLVMValueRef indir_index = NULL;
3133 unsigned const_index = 0;
3134 unsigned location = instr->variables[0]->var->data.location;
3135 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3136 const bool is_patch = instr->variables[0]->var->data.patch;
3137 const bool is_compact = instr->variables[0]->var->data.compact;
3138
3139 get_deref_offset(ctx, instr->variables[0],
3140 false, NULL, is_patch ? NULL : &vertex_index,
3141 &const_index, &indir_index);
3142
3143 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3144 const_index, location, driver_location,
3145 instr->variables[0]->var->data.location_frac,
3146 instr->num_components,
3147 is_patch, is_compact);
3148 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3149 }
3150
3151 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3152 LLVMValueRef indir_index;
3153 unsigned const_index, vertex_index;
3154 get_deref_offset(ctx, instr->variables[0],
3155 false, &vertex_index, NULL,
3156 &const_index, &indir_index);
3157 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3158 instr->variables[0]->var->data.driver_location,
3159 instr->variables[0]->var->data.location_frac, ve,
3160 vertex_index, const_index,
3161 nir2llvmtype(ctx, instr->variables[0]->var->type));
3162 }
3163
3164 for (unsigned chan = comp; chan < ve + comp; chan++) {
3165 if (indir_index) {
3166 unsigned count = glsl_count_attribute_slots(
3167 instr->variables[0]->var->type,
3168 ctx->stage == MESA_SHADER_VERTEX);
3169 count -= chan / 4;
3170 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3171 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3172 stride, false, true);
3173
3174 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3175 tmp_vec,
3176 indir_index, "");
3177 } else
3178 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3179 }
3180 break;
3181 case nir_var_local:
3182 for (unsigned chan = 0; chan < ve; chan++) {
3183 if (indir_index) {
3184 unsigned count = glsl_count_attribute_slots(
3185 instr->variables[0]->var->type, false);
3186 count -= chan / 4;
3187 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3188 &ctx->ac, ctx->locals + idx + chan, count,
3189 stride, true, true);
3190
3191 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3192 tmp_vec,
3193 indir_index, "");
3194 } else {
3195 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3196 }
3197 }
3198 break;
3199 case nir_var_shared: {
3200 LLVMValueRef address = build_gep_for_deref(ctx,
3201 instr->variables[0]);
3202 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3203 return LLVMBuildBitCast(ctx->ac.builder, val,
3204 get_def_type(ctx, &instr->dest.ssa),
3205 "");
3206 }
3207 case nir_var_shader_out:
3208 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3209 return load_tcs_output(ctx->nctx, instr);
3210
3211 for (unsigned chan = comp; chan < ve + comp; chan++) {
3212 if (indir_index) {
3213 unsigned count = glsl_count_attribute_slots(
3214 instr->variables[0]->var->type, false);
3215 count -= chan / 4;
3216 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3217 &ctx->ac, ctx->outputs + idx + chan, count,
3218 stride, true, true);
3219
3220 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3221 tmp_vec,
3222 indir_index, "");
3223 } else {
3224 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3225 ctx->outputs[idx + chan + const_index * stride],
3226 "");
3227 }
3228 }
3229 break;
3230 default:
3231 unreachable("unhandle variable mode");
3232 }
3233 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3234 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3235 }
3236
3237 static void
3238 visit_store_var(struct ac_nir_context *ctx,
3239 nir_intrinsic_instr *instr)
3240 {
3241 LLVMValueRef temp_ptr, value;
3242 int idx = instr->variables[0]->var->data.driver_location;
3243 unsigned comp = instr->variables[0]->var->data.location_frac;
3244 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3245 int writemask = instr->const_index[0] << comp;
3246 LLVMValueRef indir_index;
3247 unsigned const_index;
3248 get_deref_offset(ctx, instr->variables[0], false,
3249 NULL, NULL, &const_index, &indir_index);
3250
3251 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3252 int old_writemask = writemask;
3253
3254 src = LLVMBuildBitCast(ctx->ac.builder, src,
3255 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3256 "");
3257
3258 writemask = 0;
3259 for (unsigned chan = 0; chan < 4; chan++) {
3260 if (old_writemask & (1 << chan))
3261 writemask |= 3u << (2 * chan);
3262 }
3263 }
3264
3265 switch (instr->variables[0]->var->data.mode) {
3266 case nir_var_shader_out:
3267
3268 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3269 LLVMValueRef vertex_index = NULL;
3270 LLVMValueRef indir_index = NULL;
3271 unsigned const_index = 0;
3272 const unsigned location = instr->variables[0]->var->data.location;
3273 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3274 const unsigned comp = instr->variables[0]->var->data.location_frac;
3275 const bool is_patch = instr->variables[0]->var->data.patch;
3276 const bool is_compact = instr->variables[0]->var->data.compact;
3277
3278 get_deref_offset(ctx, instr->variables[0],
3279 false, NULL, is_patch ? NULL : &vertex_index,
3280 &const_index, &indir_index);
3281
3282 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3283 const_index, location, driver_location,
3284 src, comp, is_patch, is_compact, writemask);
3285 return;
3286 }
3287
3288 for (unsigned chan = 0; chan < 8; chan++) {
3289 int stride = 4;
3290 if (!(writemask & (1 << chan)))
3291 continue;
3292
3293 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3294
3295 if (instr->variables[0]->var->data.compact)
3296 stride = 1;
3297 if (indir_index) {
3298 unsigned count = glsl_count_attribute_slots(
3299 instr->variables[0]->var->type, false);
3300 count -= chan / 4;
3301 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3302 &ctx->ac, ctx->outputs + idx + chan, count,
3303 stride, true, true);
3304
3305 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3306 value, indir_index, "");
3307 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3308 count, stride, tmp_vec);
3309
3310 } else {
3311 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3312
3313 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3314 }
3315 }
3316 break;
3317 case nir_var_local:
3318 for (unsigned chan = 0; chan < 8; chan++) {
3319 if (!(writemask & (1 << chan)))
3320 continue;
3321
3322 value = llvm_extract_elem(&ctx->ac, src, chan);
3323 if (indir_index) {
3324 unsigned count = glsl_count_attribute_slots(
3325 instr->variables[0]->var->type, false);
3326 count -= chan / 4;
3327 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3328 &ctx->ac, ctx->locals + idx + chan, count,
3329 4, true, true);
3330
3331 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3332 value, indir_index, "");
3333 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3334 count, 4, tmp_vec);
3335 } else {
3336 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3337
3338 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3339 }
3340 }
3341 break;
3342 case nir_var_shared: {
3343 int writemask = instr->const_index[0];
3344 LLVMValueRef address = build_gep_for_deref(ctx,
3345 instr->variables[0]);
3346 LLVMValueRef val = get_src(ctx, instr->src[0]);
3347 unsigned components =
3348 glsl_get_vector_elements(
3349 nir_deref_tail(&instr->variables[0]->deref)->type);
3350 if (writemask == (1 << components) - 1) {
3351 val = LLVMBuildBitCast(
3352 ctx->ac.builder, val,
3353 LLVMGetElementType(LLVMTypeOf(address)), "");
3354 LLVMBuildStore(ctx->ac.builder, val, address);
3355 } else {
3356 for (unsigned chan = 0; chan < 4; chan++) {
3357 if (!(writemask & (1 << chan)))
3358 continue;
3359 LLVMValueRef ptr =
3360 LLVMBuildStructGEP(ctx->ac.builder,
3361 address, chan, "");
3362 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3363 chan);
3364 src = LLVMBuildBitCast(
3365 ctx->ac.builder, src,
3366 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3367 LLVMBuildStore(ctx->ac.builder, src, ptr);
3368 }
3369 }
3370 break;
3371 }
3372 default:
3373 break;
3374 }
3375 }
3376
3377 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3378 {
3379 switch (dim) {
3380 case GLSL_SAMPLER_DIM_BUF:
3381 return 1;
3382 case GLSL_SAMPLER_DIM_1D:
3383 return array ? 2 : 1;
3384 case GLSL_SAMPLER_DIM_2D:
3385 return array ? 3 : 2;
3386 case GLSL_SAMPLER_DIM_MS:
3387 return array ? 4 : 3;
3388 case GLSL_SAMPLER_DIM_3D:
3389 case GLSL_SAMPLER_DIM_CUBE:
3390 return 3;
3391 case GLSL_SAMPLER_DIM_RECT:
3392 case GLSL_SAMPLER_DIM_SUBPASS:
3393 return 2;
3394 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3395 return 3;
3396 default:
3397 break;
3398 }
3399 return 0;
3400 }
3401
3402
3403
3404 /* Adjust the sample index according to FMASK.
3405 *
3406 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3407 * which is the identity mapping. Each nibble says which physical sample
3408 * should be fetched to get that sample.
3409 *
3410 * For example, 0x11111100 means there are only 2 samples stored and
3411 * the second sample covers 3/4 of the pixel. When reading samples 0
3412 * and 1, return physical sample 0 (determined by the first two 0s
3413 * in FMASK), otherwise return physical sample 1.
3414 *
3415 * The sample index should be adjusted as follows:
3416 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3417 */
3418 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3419 LLVMValueRef coord_x, LLVMValueRef coord_y,
3420 LLVMValueRef coord_z,
3421 LLVMValueRef sample_index,
3422 LLVMValueRef fmask_desc_ptr)
3423 {
3424 LLVMValueRef fmask_load_address[4];
3425 LLVMValueRef res;
3426
3427 fmask_load_address[0] = coord_x;
3428 fmask_load_address[1] = coord_y;
3429 if (coord_z) {
3430 fmask_load_address[2] = coord_z;
3431 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3432 }
3433
3434 struct ac_image_args args = {0};
3435
3436 args.opcode = ac_image_load;
3437 args.da = coord_z ? true : false;
3438 args.resource = fmask_desc_ptr;
3439 args.dmask = 0xf;
3440 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3441
3442 res = ac_build_image_opcode(ctx, &args);
3443
3444 res = ac_to_integer(ctx, res);
3445 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3446 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3447
3448 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3449 res,
3450 ctx->i32_0, "");
3451
3452 LLVMValueRef sample_index4 =
3453 LLVMBuildMul(ctx->builder, sample_index, four, "");
3454 LLVMValueRef shifted_fmask =
3455 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3456 LLVMValueRef final_sample =
3457 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3458
3459 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3460 * resource descriptor is 0 (invalid),
3461 */
3462 LLVMValueRef fmask_desc =
3463 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3464 ctx->v8i32, "");
3465
3466 LLVMValueRef fmask_word1 =
3467 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3468 ctx->i32_1, "");
3469
3470 LLVMValueRef word1_is_nonzero =
3471 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3472 fmask_word1, ctx->i32_0, "");
3473
3474 /* Replace the MSAA sample index. */
3475 sample_index =
3476 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3477 final_sample, sample_index, "");
3478 return sample_index;
3479 }
3480
3481 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3482 const nir_intrinsic_instr *instr)
3483 {
3484 const struct glsl_type *type = instr->variables[0]->var->type;
3485 if(instr->variables[0]->deref.child)
3486 type = instr->variables[0]->deref.child->type;
3487
3488 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3489 LLVMValueRef coords[4];
3490 LLVMValueRef masks[] = {
3491 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3492 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3493 };
3494 LLVMValueRef res;
3495 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3496
3497 int count;
3498 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3499 bool is_array = glsl_sampler_type_is_array(type);
3500 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3501 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3502 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3503 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3504 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3505 count = image_type_to_components_count(dim, is_array);
3506
3507 if (is_ms) {
3508 LLVMValueRef fmask_load_address[3];
3509 int chan;
3510
3511 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3512 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3513 if (is_array)
3514 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3515 else
3516 fmask_load_address[2] = NULL;
3517 if (add_frag_pos) {
3518 for (chan = 0; chan < 2; ++chan)
3519 fmask_load_address[chan] =
3520 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3521 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3522 ctx->ac.i32, ""), "");
3523 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3524 }
3525 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3526 fmask_load_address[0],
3527 fmask_load_address[1],
3528 fmask_load_address[2],
3529 sample_index,
3530 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3531 }
3532 if (count == 1 && !gfx9_1d) {
3533 if (instr->src[0].ssa->num_components)
3534 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3535 else
3536 res = src0;
3537 } else {
3538 int chan;
3539 if (is_ms)
3540 count--;
3541 for (chan = 0; chan < count; ++chan) {
3542 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3543 }
3544 if (add_frag_pos) {
3545 for (chan = 0; chan < 2; ++chan)
3546 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3547 ctx->ac.i32, ""), "");
3548 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3549 count++;
3550 }
3551
3552 if (gfx9_1d) {
3553 if (is_array) {
3554 coords[2] = coords[1];
3555 coords[1] = ctx->ac.i32_0;
3556 } else
3557 coords[1] = ctx->ac.i32_0;
3558 count++;
3559 }
3560
3561 if (is_ms) {
3562 coords[count] = sample_index;
3563 count++;
3564 }
3565
3566 if (count == 3) {
3567 coords[3] = LLVMGetUndef(ctx->ac.i32);
3568 count = 4;
3569 }
3570 res = ac_build_gather_values(&ctx->ac, coords, count);
3571 }
3572 return res;
3573 }
3574
3575 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3576 const nir_intrinsic_instr *instr)
3577 {
3578 LLVMValueRef params[7];
3579 LLVMValueRef res;
3580 char intrinsic_name[64];
3581 const nir_variable *var = instr->variables[0]->var;
3582 const struct glsl_type *type = var->type;
3583
3584 if(instr->variables[0]->deref.child)
3585 type = instr->variables[0]->deref.child->type;
3586
3587 type = glsl_without_array(type);
3588 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3589 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3590 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3591 ctx->ac.i32_0, ""); /* vindex */
3592 params[2] = ctx->ac.i32_0; /* voffset */
3593 params[3] = ctx->ac.i1false; /* glc */
3594 params[4] = ctx->ac.i1false; /* slc */
3595 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3596 params, 5, 0);
3597
3598 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3599 res = ac_to_integer(&ctx->ac, res);
3600 } else {
3601 bool is_da = glsl_sampler_type_is_array(type) ||
3602 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3603 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3604 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3605 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3606 LLVMValueRef glc = ctx->ac.i1false;
3607 LLVMValueRef slc = ctx->ac.i1false;
3608
3609 params[0] = get_image_coords(ctx, instr);
3610 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3611 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3612 if (HAVE_LLVM <= 0x0309) {
3613 params[3] = ctx->ac.i1false; /* r128 */
3614 params[4] = da;
3615 params[5] = glc;
3616 params[6] = slc;
3617 } else {
3618 LLVMValueRef lwe = ctx->ac.i1false;
3619 params[3] = glc;
3620 params[4] = slc;
3621 params[5] = lwe;
3622 params[6] = da;
3623 }
3624
3625 ac_get_image_intr_name("llvm.amdgcn.image.load",
3626 ctx->ac.v4f32, /* vdata */
3627 LLVMTypeOf(params[0]), /* coords */
3628 LLVMTypeOf(params[1]), /* rsrc */
3629 intrinsic_name, sizeof(intrinsic_name));
3630
3631 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3632 params, 7, AC_FUNC_ATTR_READONLY);
3633 }
3634 return ac_to_integer(&ctx->ac, res);
3635 }
3636
3637 static void visit_image_store(struct ac_nir_context *ctx,
3638 nir_intrinsic_instr *instr)
3639 {
3640 LLVMValueRef params[8];
3641 char intrinsic_name[64];
3642 const nir_variable *var = instr->variables[0]->var;
3643 const struct glsl_type *type = glsl_without_array(var->type);
3644 LLVMValueRef glc = ctx->ac.i1false;
3645 bool force_glc = ctx->ac.chip_class == SI;
3646 if (force_glc)
3647 glc = ctx->ac.i1true;
3648
3649 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3650 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3651 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3652 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3653 ctx->ac.i32_0, ""); /* vindex */
3654 params[3] = ctx->ac.i32_0; /* voffset */
3655 params[4] = glc; /* glc */
3656 params[5] = ctx->ac.i1false; /* slc */
3657 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3658 params, 6, 0);
3659 } else {
3660 bool is_da = glsl_sampler_type_is_array(type) ||
3661 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3662 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3663 LLVMValueRef slc = ctx->ac.i1false;
3664
3665 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3666 params[1] = get_image_coords(ctx, instr); /* coords */
3667 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3668 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3669 if (HAVE_LLVM <= 0x0309) {
3670 params[4] = ctx->ac.i1false; /* r128 */
3671 params[5] = da;
3672 params[6] = glc;
3673 params[7] = slc;
3674 } else {
3675 LLVMValueRef lwe = ctx->ac.i1false;
3676 params[4] = glc;
3677 params[5] = slc;
3678 params[6] = lwe;
3679 params[7] = da;
3680 }
3681
3682 ac_get_image_intr_name("llvm.amdgcn.image.store",
3683 LLVMTypeOf(params[0]), /* vdata */
3684 LLVMTypeOf(params[1]), /* coords */
3685 LLVMTypeOf(params[2]), /* rsrc */
3686 intrinsic_name, sizeof(intrinsic_name));
3687
3688 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3689 params, 8, 0);
3690 }
3691
3692 }
3693
3694 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3695 const nir_intrinsic_instr *instr)
3696 {
3697 LLVMValueRef params[7];
3698 int param_count = 0;
3699 const nir_variable *var = instr->variables[0]->var;
3700
3701 const char *atomic_name;
3702 char intrinsic_name[41];
3703 const struct glsl_type *type = glsl_without_array(var->type);
3704 MAYBE_UNUSED int length;
3705
3706 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3707
3708 switch (instr->intrinsic) {
3709 case nir_intrinsic_image_atomic_add:
3710 atomic_name = "add";
3711 break;
3712 case nir_intrinsic_image_atomic_min:
3713 atomic_name = is_unsigned ? "umin" : "smin";
3714 break;
3715 case nir_intrinsic_image_atomic_max:
3716 atomic_name = is_unsigned ? "umax" : "smax";
3717 break;
3718 case nir_intrinsic_image_atomic_and:
3719 atomic_name = "and";
3720 break;
3721 case nir_intrinsic_image_atomic_or:
3722 atomic_name = "or";
3723 break;
3724 case nir_intrinsic_image_atomic_xor:
3725 atomic_name = "xor";
3726 break;
3727 case nir_intrinsic_image_atomic_exchange:
3728 atomic_name = "swap";
3729 break;
3730 case nir_intrinsic_image_atomic_comp_swap:
3731 atomic_name = "cmpswap";
3732 break;
3733 default:
3734 abort();
3735 }
3736
3737 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3738 params[param_count++] = get_src(ctx, instr->src[3]);
3739 params[param_count++] = get_src(ctx, instr->src[2]);
3740
3741 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3742 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3743 NULL, true, true);
3744 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3745 ctx->ac.i32_0, ""); /* vindex */
3746 params[param_count++] = ctx->ac.i32_0; /* voffset */
3747 params[param_count++] = ctx->ac.i1false; /* slc */
3748
3749 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3750 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3751 } else {
3752 char coords_type[8];
3753
3754 bool da = glsl_sampler_type_is_array(type) ||
3755 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3756
3757 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3758 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3759 NULL, true, true);
3760 params[param_count++] = ctx->ac.i1false; /* r128 */
3761 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3762 params[param_count++] = ctx->ac.i1false; /* slc */
3763
3764 build_int_type_name(LLVMTypeOf(coords),
3765 coords_type, sizeof(coords_type));
3766
3767 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3768 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3769 }
3770
3771 assert(length < sizeof(intrinsic_name));
3772 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3773 }
3774
3775 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3776 const nir_intrinsic_instr *instr)
3777 {
3778 LLVMValueRef res;
3779 const nir_variable *var = instr->variables[0]->var;
3780 const struct glsl_type *type = instr->variables[0]->var->type;
3781 bool da = glsl_sampler_type_is_array(var->type) ||
3782 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3783 if(instr->variables[0]->deref.child)
3784 type = instr->variables[0]->deref.child->type;
3785
3786 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3787 return get_buffer_size(ctx,
3788 get_sampler_desc(ctx, instr->variables[0],
3789 AC_DESC_BUFFER, NULL, true, false), true);
3790
3791 struct ac_image_args args = { 0 };
3792
3793 args.da = da;
3794 args.dmask = 0xf;
3795 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3796 args.opcode = ac_image_get_resinfo;
3797 args.addr = ctx->ac.i32_0;
3798
3799 res = ac_build_image_opcode(&ctx->ac, &args);
3800
3801 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3802
3803 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3804 glsl_sampler_type_is_array(type)) {
3805 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3806 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3807 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3808 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3809 }
3810 if (ctx->ac.chip_class >= GFX9 &&
3811 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3812 glsl_sampler_type_is_array(type)) {
3813 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3814 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3815 ctx->ac.i32_1, "");
3816
3817 }
3818 return res;
3819 }
3820
3821 #define NOOP_WAITCNT 0xf7f
3822 #define LGKM_CNT 0x07f
3823 #define VM_CNT 0xf70
3824
3825 static void emit_membar(struct nir_to_llvm_context *ctx,
3826 const nir_intrinsic_instr *instr)
3827 {
3828 unsigned waitcnt = NOOP_WAITCNT;
3829
3830 switch (instr->intrinsic) {
3831 case nir_intrinsic_memory_barrier:
3832 case nir_intrinsic_group_memory_barrier:
3833 waitcnt &= VM_CNT & LGKM_CNT;
3834 break;
3835 case nir_intrinsic_memory_barrier_atomic_counter:
3836 case nir_intrinsic_memory_barrier_buffer:
3837 case nir_intrinsic_memory_barrier_image:
3838 waitcnt &= VM_CNT;
3839 break;
3840 case nir_intrinsic_memory_barrier_shared:
3841 waitcnt &= LGKM_CNT;
3842 break;
3843 default:
3844 break;
3845 }
3846 if (waitcnt != NOOP_WAITCNT)
3847 ac_build_waitcnt(&ctx->ac, waitcnt);
3848 }
3849
3850 static void emit_barrier(struct nir_to_llvm_context *ctx)
3851 {
3852 /* SI only (thanks to a hw bug workaround):
3853 * The real barrier instruction isn’t needed, because an entire patch
3854 * always fits into a single wave.
3855 */
3856 if (ctx->options->chip_class == SI &&
3857 ctx->stage == MESA_SHADER_TESS_CTRL) {
3858 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3859 return;
3860 }
3861 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3862 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3863 }
3864
3865 static void emit_discard_if(struct ac_nir_context *ctx,
3866 const nir_intrinsic_instr *instr)
3867 {
3868 LLVMValueRef cond;
3869
3870 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3871 get_src(ctx, instr->src[0]),
3872 ctx->ac.i32_0, "");
3873 ac_build_kill_if_false(&ctx->ac, cond);
3874 }
3875
3876 static LLVMValueRef
3877 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3878 {
3879 LLVMValueRef result;
3880 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3881 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3882 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3883
3884 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3885 }
3886
3887 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3888 const nir_intrinsic_instr *instr)
3889 {
3890 LLVMValueRef ptr, result;
3891 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3892 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3893
3894 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3895 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3896 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3897 ptr, src, src1,
3898 LLVMAtomicOrderingSequentiallyConsistent,
3899 LLVMAtomicOrderingSequentiallyConsistent,
3900 false);
3901 } else {
3902 LLVMAtomicRMWBinOp op;
3903 switch (instr->intrinsic) {
3904 case nir_intrinsic_var_atomic_add:
3905 op = LLVMAtomicRMWBinOpAdd;
3906 break;
3907 case nir_intrinsic_var_atomic_umin:
3908 op = LLVMAtomicRMWBinOpUMin;
3909 break;
3910 case nir_intrinsic_var_atomic_umax:
3911 op = LLVMAtomicRMWBinOpUMax;
3912 break;
3913 case nir_intrinsic_var_atomic_imin:
3914 op = LLVMAtomicRMWBinOpMin;
3915 break;
3916 case nir_intrinsic_var_atomic_imax:
3917 op = LLVMAtomicRMWBinOpMax;
3918 break;
3919 case nir_intrinsic_var_atomic_and:
3920 op = LLVMAtomicRMWBinOpAnd;
3921 break;
3922 case nir_intrinsic_var_atomic_or:
3923 op = LLVMAtomicRMWBinOpOr;
3924 break;
3925 case nir_intrinsic_var_atomic_xor:
3926 op = LLVMAtomicRMWBinOpXor;
3927 break;
3928 case nir_intrinsic_var_atomic_exchange:
3929 op = LLVMAtomicRMWBinOpXchg;
3930 break;
3931 default:
3932 return NULL;
3933 }
3934
3935 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3936 LLVMAtomicOrderingSequentiallyConsistent,
3937 false);
3938 }
3939 return result;
3940 }
3941
3942 #define INTERP_CENTER 0
3943 #define INTERP_CENTROID 1
3944 #define INTERP_SAMPLE 2
3945
3946 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3947 enum glsl_interp_mode interp, unsigned location)
3948 {
3949 switch (interp) {
3950 case INTERP_MODE_FLAT:
3951 default:
3952 return NULL;
3953 case INTERP_MODE_SMOOTH:
3954 case INTERP_MODE_NONE:
3955 if (location == INTERP_CENTER)
3956 return ctx->persp_center;
3957 else if (location == INTERP_CENTROID)
3958 return ctx->persp_centroid;
3959 else if (location == INTERP_SAMPLE)
3960 return ctx->persp_sample;
3961 break;
3962 case INTERP_MODE_NOPERSPECTIVE:
3963 if (location == INTERP_CENTER)
3964 return ctx->linear_center;
3965 else if (location == INTERP_CENTROID)
3966 return ctx->linear_centroid;
3967 else if (location == INTERP_SAMPLE)
3968 return ctx->linear_sample;
3969 break;
3970 }
3971 return NULL;
3972 }
3973
3974 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3975 LLVMValueRef sample_id)
3976 {
3977 LLVMValueRef result;
3978 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3979
3980 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3981 const_array(ctx->ac.v2f32, 64), "");
3982
3983 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3984 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3985
3986 return result;
3987 }
3988
3989 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3990 {
3991 LLVMValueRef values[2];
3992
3993 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3994 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3995 return ac_build_gather_values(&ctx->ac, values, 2);
3996 }
3997
3998 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3999 const nir_intrinsic_instr *instr)
4000 {
4001 LLVMValueRef result[4];
4002 LLVMValueRef interp_param, attr_number;
4003 unsigned location;
4004 unsigned chan;
4005 LLVMValueRef src_c0 = NULL;
4006 LLVMValueRef src_c1 = NULL;
4007 LLVMValueRef src0 = NULL;
4008 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4009 switch (instr->intrinsic) {
4010 case nir_intrinsic_interp_var_at_centroid:
4011 location = INTERP_CENTROID;
4012 break;
4013 case nir_intrinsic_interp_var_at_sample:
4014 case nir_intrinsic_interp_var_at_offset:
4015 location = INTERP_CENTER;
4016 src0 = get_src(ctx->nir, instr->src[0]);
4017 break;
4018 default:
4019 break;
4020 }
4021
4022 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4023 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4024 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4025 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4026 LLVMValueRef sample_position;
4027 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4028
4029 /* fetch sample ID */
4030 sample_position = load_sample_position(ctx, src0);
4031
4032 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4033 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4034 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4035 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4036 }
4037 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4038 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4039
4040 if (location == INTERP_CENTER) {
4041 LLVMValueRef ij_out[2];
4042 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4043
4044 /*
4045 * take the I then J parameters, and the DDX/Y for it, and
4046 * calculate the IJ inputs for the interpolator.
4047 * temp1 = ddx * offset/sample.x + I;
4048 * interp_param.I = ddy * offset/sample.y + temp1;
4049 * temp1 = ddx * offset/sample.x + J;
4050 * interp_param.J = ddy * offset/sample.y + temp1;
4051 */
4052 for (unsigned i = 0; i < 2; i++) {
4053 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4054 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4055 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4056 ddxy_out, ix_ll, "");
4057 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4058 ddxy_out, iy_ll, "");
4059 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4060 interp_param, ix_ll, "");
4061 LLVMValueRef temp1, temp2;
4062
4063 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4064 ctx->ac.f32, "");
4065
4066 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4067 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4068
4069 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4070 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4071
4072 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4073 temp2, ctx->ac.i32, "");
4074 }
4075 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4076
4077 }
4078
4079 for (chan = 0; chan < 4; chan++) {
4080 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4081
4082 if (interp_param) {
4083 interp_param = LLVMBuildBitCast(ctx->builder,
4084 interp_param, ctx->ac.v2f32, "");
4085 LLVMValueRef i = LLVMBuildExtractElement(
4086 ctx->builder, interp_param, ctx->ac.i32_0, "");
4087 LLVMValueRef j = LLVMBuildExtractElement(
4088 ctx->builder, interp_param, ctx->ac.i32_1, "");
4089
4090 result[chan] = ac_build_fs_interp(&ctx->ac,
4091 llvm_chan, attr_number,
4092 ctx->prim_mask, i, j);
4093 } else {
4094 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4095 LLVMConstInt(ctx->ac.i32, 2, false),
4096 llvm_chan, attr_number,
4097 ctx->prim_mask);
4098 }
4099 }
4100 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4101 instr->variables[0]->var->data.location_frac);
4102 }
4103
4104 static void
4105 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4106 {
4107 LLVMValueRef gs_next_vertex;
4108 LLVMValueRef can_emit;
4109 int idx;
4110 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4111
4112 /* Write vertex attribute values to GSVS ring */
4113 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4114 ctx->gs_next_vertex,
4115 "");
4116
4117 /* If this thread has already emitted the declared maximum number of
4118 * vertices, kill it: excessive vertex emissions are not supposed to
4119 * have any effect, and GS threads have no externally observable
4120 * effects other than emitting vertices.
4121 */
4122 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4123 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4124 ac_build_kill_if_false(&ctx->ac, can_emit);
4125
4126 /* loop num outputs */
4127 idx = 0;
4128 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4129 LLVMValueRef *out_ptr = &addrs[i * 4];
4130 int length = 4;
4131 int slot = idx;
4132 int slot_inc = 1;
4133
4134 if (!(ctx->output_mask & (1ull << i)))
4135 continue;
4136
4137 if (i == VARYING_SLOT_CLIP_DIST0) {
4138 /* pack clip and cull into a single set of slots */
4139 length = ctx->num_output_clips + ctx->num_output_culls;
4140 if (length > 4)
4141 slot_inc = 2;
4142 }
4143 for (unsigned j = 0; j < length; j++) {
4144 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4145 out_ptr[j], "");
4146 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4147 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4148 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4149
4150 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4151
4152 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4153 out_val, 1,
4154 voffset, ctx->gs2vs_offset, 0,
4155 1, 1, true, true);
4156 }
4157 idx += slot_inc;
4158 }
4159
4160 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4161 ctx->ac.i32_1, "");
4162 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4163
4164 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4165 }
4166
4167 static void
4168 visit_end_primitive(struct nir_to_llvm_context *ctx,
4169 const nir_intrinsic_instr *instr)
4170 {
4171 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4172 }
4173
4174 static LLVMValueRef
4175 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4176 const nir_intrinsic_instr *instr)
4177 {
4178 LLVMValueRef coord[4] = {
4179 ctx->tes_u,
4180 ctx->tes_v,
4181 ctx->ac.f32_0,
4182 ctx->ac.f32_0,
4183 };
4184
4185 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4186 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4187 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4188
4189 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4190 return LLVMBuildBitCast(ctx->builder, result,
4191 get_def_type(ctx->nir, &instr->dest.ssa), "");
4192 }
4193
4194 static void visit_intrinsic(struct ac_nir_context *ctx,
4195 nir_intrinsic_instr *instr)
4196 {
4197 LLVMValueRef result = NULL;
4198
4199 switch (instr->intrinsic) {
4200 case nir_intrinsic_load_work_group_id: {
4201 LLVMValueRef values[3];
4202
4203 for (int i = 0; i < 3; i++) {
4204 values[i] = ctx->nctx->workgroup_ids[i] ?
4205 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4206 }
4207
4208 result = ac_build_gather_values(&ctx->ac, values, 3);
4209 break;
4210 }
4211 case nir_intrinsic_load_base_vertex: {
4212 result = ctx->abi->base_vertex;
4213 break;
4214 }
4215 case nir_intrinsic_load_vertex_id_zero_base: {
4216 result = ctx->abi->vertex_id;
4217 break;
4218 }
4219 case nir_intrinsic_load_local_invocation_id: {
4220 result = ctx->nctx->local_invocation_ids;
4221 break;
4222 }
4223 case nir_intrinsic_load_base_instance:
4224 result = ctx->abi->start_instance;
4225 break;
4226 case nir_intrinsic_load_draw_id:
4227 result = ctx->abi->draw_id;
4228 break;
4229 case nir_intrinsic_load_view_index:
4230 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4231 break;
4232 case nir_intrinsic_load_invocation_id:
4233 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4234 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4235 else
4236 result = ctx->abi->gs_invocation_id;
4237 break;
4238 case nir_intrinsic_load_primitive_id:
4239 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4240 result = ctx->abi->gs_prim_id;
4241 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4242 result = ctx->nctx->tcs_patch_id;
4243 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4244 result = ctx->nctx->tes_patch_id;
4245 } else
4246 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4247 break;
4248 case nir_intrinsic_load_sample_id:
4249 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4250 break;
4251 case nir_intrinsic_load_sample_pos:
4252 result = load_sample_pos(ctx);
4253 break;
4254 case nir_intrinsic_load_sample_mask_in:
4255 result = ctx->abi->sample_coverage;
4256 break;
4257 case nir_intrinsic_load_frag_coord: {
4258 LLVMValueRef values[4] = {
4259 ctx->abi->frag_pos[0],
4260 ctx->abi->frag_pos[1],
4261 ctx->abi->frag_pos[2],
4262 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4263 };
4264 result = ac_build_gather_values(&ctx->ac, values, 4);
4265 break;
4266 }
4267 case nir_intrinsic_load_front_face:
4268 result = ctx->abi->front_face;
4269 break;
4270 case nir_intrinsic_load_instance_id:
4271 result = ctx->abi->instance_id;
4272 break;
4273 case nir_intrinsic_load_num_work_groups:
4274 result = ctx->nctx->num_work_groups;
4275 break;
4276 case nir_intrinsic_load_local_invocation_index:
4277 result = visit_load_local_invocation_index(ctx->nctx);
4278 break;
4279 case nir_intrinsic_load_push_constant:
4280 result = visit_load_push_constant(ctx->nctx, instr);
4281 break;
4282 case nir_intrinsic_vulkan_resource_index:
4283 result = visit_vulkan_resource_index(ctx->nctx, instr);
4284 break;
4285 case nir_intrinsic_vulkan_resource_reindex:
4286 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4287 break;
4288 case nir_intrinsic_store_ssbo:
4289 visit_store_ssbo(ctx, instr);
4290 break;
4291 case nir_intrinsic_load_ssbo:
4292 result = visit_load_buffer(ctx, instr);
4293 break;
4294 case nir_intrinsic_ssbo_atomic_add:
4295 case nir_intrinsic_ssbo_atomic_imin:
4296 case nir_intrinsic_ssbo_atomic_umin:
4297 case nir_intrinsic_ssbo_atomic_imax:
4298 case nir_intrinsic_ssbo_atomic_umax:
4299 case nir_intrinsic_ssbo_atomic_and:
4300 case nir_intrinsic_ssbo_atomic_or:
4301 case nir_intrinsic_ssbo_atomic_xor:
4302 case nir_intrinsic_ssbo_atomic_exchange:
4303 case nir_intrinsic_ssbo_atomic_comp_swap:
4304 result = visit_atomic_ssbo(ctx, instr);
4305 break;
4306 case nir_intrinsic_load_ubo:
4307 result = visit_load_ubo_buffer(ctx, instr);
4308 break;
4309 case nir_intrinsic_get_buffer_size:
4310 result = visit_get_buffer_size(ctx, instr);
4311 break;
4312 case nir_intrinsic_load_var:
4313 result = visit_load_var(ctx, instr);
4314 break;
4315 case nir_intrinsic_store_var:
4316 visit_store_var(ctx, instr);
4317 break;
4318 case nir_intrinsic_image_load:
4319 result = visit_image_load(ctx, instr);
4320 break;
4321 case nir_intrinsic_image_store:
4322 visit_image_store(ctx, instr);
4323 break;
4324 case nir_intrinsic_image_atomic_add:
4325 case nir_intrinsic_image_atomic_min:
4326 case nir_intrinsic_image_atomic_max:
4327 case nir_intrinsic_image_atomic_and:
4328 case nir_intrinsic_image_atomic_or:
4329 case nir_intrinsic_image_atomic_xor:
4330 case nir_intrinsic_image_atomic_exchange:
4331 case nir_intrinsic_image_atomic_comp_swap:
4332 result = visit_image_atomic(ctx, instr);
4333 break;
4334 case nir_intrinsic_image_size:
4335 result = visit_image_size(ctx, instr);
4336 break;
4337 case nir_intrinsic_discard:
4338 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4339 LLVMVoidTypeInContext(ctx->ac.context),
4340 NULL, 0, AC_FUNC_ATTR_LEGACY);
4341 break;
4342 case nir_intrinsic_discard_if:
4343 emit_discard_if(ctx, instr);
4344 break;
4345 case nir_intrinsic_memory_barrier:
4346 case nir_intrinsic_group_memory_barrier:
4347 case nir_intrinsic_memory_barrier_atomic_counter:
4348 case nir_intrinsic_memory_barrier_buffer:
4349 case nir_intrinsic_memory_barrier_image:
4350 case nir_intrinsic_memory_barrier_shared:
4351 emit_membar(ctx->nctx, instr);
4352 break;
4353 case nir_intrinsic_barrier:
4354 emit_barrier(ctx->nctx);
4355 break;
4356 case nir_intrinsic_var_atomic_add:
4357 case nir_intrinsic_var_atomic_imin:
4358 case nir_intrinsic_var_atomic_umin:
4359 case nir_intrinsic_var_atomic_imax:
4360 case nir_intrinsic_var_atomic_umax:
4361 case nir_intrinsic_var_atomic_and:
4362 case nir_intrinsic_var_atomic_or:
4363 case nir_intrinsic_var_atomic_xor:
4364 case nir_intrinsic_var_atomic_exchange:
4365 case nir_intrinsic_var_atomic_comp_swap:
4366 result = visit_var_atomic(ctx->nctx, instr);
4367 break;
4368 case nir_intrinsic_interp_var_at_centroid:
4369 case nir_intrinsic_interp_var_at_sample:
4370 case nir_intrinsic_interp_var_at_offset:
4371 result = visit_interp(ctx->nctx, instr);
4372 break;
4373 case nir_intrinsic_emit_vertex:
4374 assert(instr->const_index[0] == 0);
4375 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4376 break;
4377 case nir_intrinsic_end_primitive:
4378 visit_end_primitive(ctx->nctx, instr);
4379 break;
4380 case nir_intrinsic_load_tess_coord:
4381 result = visit_load_tess_coord(ctx->nctx, instr);
4382 break;
4383 case nir_intrinsic_load_patch_vertices_in:
4384 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4385 break;
4386 default:
4387 fprintf(stderr, "Unknown intrinsic: ");
4388 nir_print_instr(&instr->instr, stderr);
4389 fprintf(stderr, "\n");
4390 break;
4391 }
4392 if (result) {
4393 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4394 }
4395 }
4396
4397 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4398 LLVMValueRef buffer_ptr, bool write)
4399 {
4400 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4401
4402 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4403 ctx->shader_info->fs.writes_memory = true;
4404
4405 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4406 }
4407
4408 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4409 {
4410 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4411
4412 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4413 }
4414
4415 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4416 unsigned descriptor_set,
4417 unsigned base_index,
4418 unsigned constant_index,
4419 LLVMValueRef index,
4420 enum ac_descriptor_type desc_type,
4421 bool image, bool write)
4422 {
4423 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4424 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4425 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4426 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4427 unsigned offset = binding->offset;
4428 unsigned stride = binding->size;
4429 unsigned type_size;
4430 LLVMBuilderRef builder = ctx->builder;
4431 LLVMTypeRef type;
4432
4433 assert(base_index < layout->binding_count);
4434
4435 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4436 ctx->shader_info->fs.writes_memory = true;
4437
4438 switch (desc_type) {
4439 case AC_DESC_IMAGE:
4440 type = ctx->ac.v8i32;
4441 type_size = 32;
4442 break;
4443 case AC_DESC_FMASK:
4444 type = ctx->ac.v8i32;
4445 offset += 32;
4446 type_size = 32;
4447 break;
4448 case AC_DESC_SAMPLER:
4449 type = ctx->ac.v4i32;
4450 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4451 offset += 64;
4452
4453 type_size = 16;
4454 break;
4455 case AC_DESC_BUFFER:
4456 type = ctx->ac.v4i32;
4457 type_size = 16;
4458 break;
4459 default:
4460 unreachable("invalid desc_type\n");
4461 }
4462
4463 offset += constant_index * stride;
4464
4465 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4466 (!index || binding->immutable_samplers_equal)) {
4467 if (binding->immutable_samplers_equal)
4468 constant_index = 0;
4469
4470 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4471
4472 LLVMValueRef constants[] = {
4473 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4474 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4475 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4476 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4477 };
4478 return ac_build_gather_values(&ctx->ac, constants, 4);
4479 }
4480
4481 assert(stride % type_size == 0);
4482
4483 if (!index)
4484 index = ctx->ac.i32_0;
4485
4486 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4487
4488 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4489 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4490
4491 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4492 }
4493
4494 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4495 const nir_deref_var *deref,
4496 enum ac_descriptor_type desc_type,
4497 const nir_tex_instr *tex_instr,
4498 bool image, bool write)
4499 {
4500 LLVMValueRef index = NULL;
4501 unsigned constant_index = 0;
4502 unsigned descriptor_set;
4503 unsigned base_index;
4504
4505 if (!deref) {
4506 assert(tex_instr && !image);
4507 descriptor_set = 0;
4508 base_index = tex_instr->sampler_index;
4509 } else {
4510 const nir_deref *tail = &deref->deref;
4511 while (tail->child) {
4512 const nir_deref_array *child = nir_deref_as_array(tail->child);
4513 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4514
4515 if (!array_size)
4516 array_size = 1;
4517
4518 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4519
4520 if (child->deref_array_type == nir_deref_array_type_indirect) {
4521 LLVMValueRef indirect = get_src(ctx, child->indirect);
4522
4523 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4524 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4525
4526 if (!index)
4527 index = indirect;
4528 else
4529 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4530 }
4531
4532 constant_index += child->base_offset * array_size;
4533
4534 tail = &child->deref;
4535 }
4536 descriptor_set = deref->var->data.descriptor_set;
4537 base_index = deref->var->data.binding;
4538 }
4539
4540 return ctx->abi->load_sampler_desc(ctx->abi,
4541 descriptor_set,
4542 base_index,
4543 constant_index, index,
4544 desc_type, image, write);
4545 }
4546
4547 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4548 struct ac_image_args *args,
4549 const nir_tex_instr *instr,
4550 nir_texop op,
4551 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4552 LLVMValueRef *param, unsigned count,
4553 unsigned dmask)
4554 {
4555 unsigned is_rect = 0;
4556 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4557
4558 if (op == nir_texop_lod)
4559 da = false;
4560 /* Pad to power of two vector */
4561 while (count < util_next_power_of_two(count))
4562 param[count++] = LLVMGetUndef(ctx->i32);
4563
4564 if (count > 1)
4565 args->addr = ac_build_gather_values(ctx, param, count);
4566 else
4567 args->addr = param[0];
4568
4569 args->resource = res_ptr;
4570 args->sampler = samp_ptr;
4571
4572 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4573 args->addr = param[0];
4574 return;
4575 }
4576
4577 args->dmask = dmask;
4578 args->unorm = is_rect;
4579 args->da = da;
4580 }
4581
4582 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4583 *
4584 * SI-CI:
4585 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4586 * filtering manually. The driver sets img7 to a mask clearing
4587 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4588 * s_and_b32 samp0, samp0, img7
4589 *
4590 * VI:
4591 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4592 */
4593 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4594 LLVMValueRef res, LLVMValueRef samp)
4595 {
4596 LLVMBuilderRef builder = ctx->ac.builder;
4597 LLVMValueRef img7, samp0;
4598
4599 if (ctx->ac.chip_class >= VI)
4600 return samp;
4601
4602 img7 = LLVMBuildExtractElement(builder, res,
4603 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4604 samp0 = LLVMBuildExtractElement(builder, samp,
4605 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4606 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4607 return LLVMBuildInsertElement(builder, samp, samp0,
4608 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4609 }
4610
4611 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4612 nir_tex_instr *instr,
4613 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4614 LLVMValueRef *fmask_ptr)
4615 {
4616 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4617 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4618 else
4619 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4620 if (samp_ptr) {
4621 if (instr->sampler)
4622 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4623 else
4624 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4625 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4626 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4627 }
4628 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4629 instr->op == nir_texop_samples_identical))
4630 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4631 }
4632
4633 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4634 LLVMValueRef coord)
4635 {
4636 coord = ac_to_float(ctx, coord);
4637 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4638 coord = ac_to_integer(ctx, coord);
4639 return coord;
4640 }
4641
4642 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4643 {
4644 LLVMValueRef result = NULL;
4645 struct ac_image_args args = { 0 };
4646 unsigned dmask = 0xf;
4647 LLVMValueRef address[16];
4648 LLVMValueRef coords[5];
4649 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4650 LLVMValueRef bias = NULL, offsets = NULL;
4651 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4652 LLVMValueRef ddx = NULL, ddy = NULL;
4653 LLVMValueRef derivs[6];
4654 unsigned chan, count = 0;
4655 unsigned const_src = 0, num_deriv_comp = 0;
4656 bool lod_is_zero = false;
4657
4658 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4659
4660 for (unsigned i = 0; i < instr->num_srcs; i++) {
4661 switch (instr->src[i].src_type) {
4662 case nir_tex_src_coord:
4663 coord = get_src(ctx, instr->src[i].src);
4664 break;
4665 case nir_tex_src_projector:
4666 break;
4667 case nir_tex_src_comparator:
4668 comparator = get_src(ctx, instr->src[i].src);
4669 break;
4670 case nir_tex_src_offset:
4671 offsets = get_src(ctx, instr->src[i].src);
4672 const_src = i;
4673 break;
4674 case nir_tex_src_bias:
4675 bias = get_src(ctx, instr->src[i].src);
4676 break;
4677 case nir_tex_src_lod: {
4678 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4679
4680 if (val && val->i32[0] == 0)
4681 lod_is_zero = true;
4682 lod = get_src(ctx, instr->src[i].src);
4683 break;
4684 }
4685 case nir_tex_src_ms_index:
4686 sample_index = get_src(ctx, instr->src[i].src);
4687 break;
4688 case nir_tex_src_ms_mcs:
4689 break;
4690 case nir_tex_src_ddx:
4691 ddx = get_src(ctx, instr->src[i].src);
4692 num_deriv_comp = instr->src[i].src.ssa->num_components;
4693 break;
4694 case nir_tex_src_ddy:
4695 ddy = get_src(ctx, instr->src[i].src);
4696 break;
4697 case nir_tex_src_texture_offset:
4698 case nir_tex_src_sampler_offset:
4699 case nir_tex_src_plane:
4700 default:
4701 break;
4702 }
4703 }
4704
4705 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4706 result = get_buffer_size(ctx, res_ptr, true);
4707 goto write_result;
4708 }
4709
4710 if (instr->op == nir_texop_texture_samples) {
4711 LLVMValueRef res, samples, is_msaa;
4712 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4713 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4714 LLVMConstInt(ctx->ac.i32, 3, false), "");
4715 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4716 LLVMConstInt(ctx->ac.i32, 28, false), "");
4717 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4718 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4719 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4720 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4721
4722 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4723 LLVMConstInt(ctx->ac.i32, 16, false), "");
4724 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4725 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4726 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4727 samples, "");
4728 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4729 ctx->ac.i32_1, "");
4730 result = samples;
4731 goto write_result;
4732 }
4733
4734 if (coord)
4735 for (chan = 0; chan < instr->coord_components; chan++)
4736 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4737
4738 if (offsets && instr->op != nir_texop_txf) {
4739 LLVMValueRef offset[3], pack;
4740 for (chan = 0; chan < 3; ++chan)
4741 offset[chan] = ctx->ac.i32_0;
4742
4743 args.offset = true;
4744 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4745 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4746 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4747 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4748 if (chan)
4749 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4750 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4751 }
4752 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4753 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4754 address[count++] = pack;
4755
4756 }
4757 /* pack LOD bias value */
4758 if (instr->op == nir_texop_txb && bias) {
4759 address[count++] = bias;
4760 }
4761
4762 /* Pack depth comparison value */
4763 if (instr->is_shadow && comparator) {
4764 LLVMValueRef z = ac_to_float(&ctx->ac,
4765 llvm_extract_elem(&ctx->ac, comparator, 0));
4766
4767 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4768 * so the depth comparison value isn't clamped for Z16 and
4769 * Z24 anymore. Do it manually here.
4770 *
4771 * It's unnecessary if the original texture format was
4772 * Z32_FLOAT, but we don't know that here.
4773 */
4774 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4775 z = ac_build_clamp(&ctx->ac, z);
4776
4777 address[count++] = z;
4778 }
4779
4780 /* pack derivatives */
4781 if (ddx || ddy) {
4782 int num_src_deriv_channels, num_dest_deriv_channels;
4783 switch (instr->sampler_dim) {
4784 case GLSL_SAMPLER_DIM_3D:
4785 case GLSL_SAMPLER_DIM_CUBE:
4786 num_deriv_comp = 3;
4787 num_src_deriv_channels = 3;
4788 num_dest_deriv_channels = 3;
4789 break;
4790 case GLSL_SAMPLER_DIM_2D:
4791 default:
4792 num_src_deriv_channels = 2;
4793 num_dest_deriv_channels = 2;
4794 num_deriv_comp = 2;
4795 break;
4796 case GLSL_SAMPLER_DIM_1D:
4797 num_src_deriv_channels = 1;
4798 if (ctx->ac.chip_class >= GFX9) {
4799 num_dest_deriv_channels = 2;
4800 num_deriv_comp = 2;
4801 } else {
4802 num_dest_deriv_channels = 1;
4803 num_deriv_comp = 1;
4804 }
4805 break;
4806 }
4807
4808 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4809 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4810 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4811 }
4812 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4813 derivs[i] = ctx->ac.f32_0;
4814 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4815 }
4816 }
4817
4818 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4819 for (chan = 0; chan < instr->coord_components; chan++)
4820 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4821 if (instr->coord_components == 3)
4822 coords[3] = LLVMGetUndef(ctx->ac.f32);
4823 ac_prepare_cube_coords(&ctx->ac,
4824 instr->op == nir_texop_txd, instr->is_array,
4825 instr->op == nir_texop_lod, coords, derivs);
4826 if (num_deriv_comp)
4827 num_deriv_comp--;
4828 }
4829
4830 if (ddx || ddy) {
4831 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4832 address[count++] = derivs[i];
4833 }
4834
4835 /* Pack texture coordinates */
4836 if (coord) {
4837 address[count++] = coords[0];
4838 if (instr->coord_components > 1) {
4839 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4840 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4841 }
4842 address[count++] = coords[1];
4843 }
4844 if (instr->coord_components > 2) {
4845 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4846 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4847 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4848 instr->op != nir_texop_txf) {
4849 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4850 }
4851 address[count++] = coords[2];
4852 }
4853
4854 if (ctx->ac.chip_class >= GFX9) {
4855 LLVMValueRef filler;
4856 if (instr->op == nir_texop_txf)
4857 filler = ctx->ac.i32_0;
4858 else
4859 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4860
4861 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4862 /* No nir_texop_lod, because it does not take a slice
4863 * even with array textures. */
4864 if (instr->is_array && instr->op != nir_texop_lod ) {
4865 address[count] = address[count - 1];
4866 address[count - 1] = filler;
4867 count++;
4868 } else
4869 address[count++] = filler;
4870 }
4871 }
4872 }
4873
4874 /* Pack LOD */
4875 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4876 instr->op == nir_texop_txf)) {
4877 address[count++] = lod;
4878 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4879 address[count++] = sample_index;
4880 } else if(instr->op == nir_texop_txs) {
4881 count = 0;
4882 if (lod)
4883 address[count++] = lod;
4884 else
4885 address[count++] = ctx->ac.i32_0;
4886 }
4887
4888 for (chan = 0; chan < count; chan++) {
4889 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4890 address[chan], ctx->ac.i32, "");
4891 }
4892
4893 if (instr->op == nir_texop_samples_identical) {
4894 LLVMValueRef txf_address[4];
4895 struct ac_image_args txf_args = { 0 };
4896 unsigned txf_count = count;
4897 memcpy(txf_address, address, sizeof(txf_address));
4898
4899 if (!instr->is_array)
4900 txf_address[2] = ctx->ac.i32_0;
4901 txf_address[3] = ctx->ac.i32_0;
4902
4903 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4904 fmask_ptr, NULL,
4905 txf_address, txf_count, 0xf);
4906
4907 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4908
4909 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4910 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4911 goto write_result;
4912 }
4913
4914 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4915 instr->op != nir_texop_txs) {
4916 unsigned sample_chan = instr->is_array ? 3 : 2;
4917 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4918 address[0],
4919 address[1],
4920 instr->is_array ? address[2] : NULL,
4921 address[sample_chan],
4922 fmask_ptr);
4923 }
4924
4925 if (offsets && instr->op == nir_texop_txf) {
4926 nir_const_value *const_offset =
4927 nir_src_as_const_value(instr->src[const_src].src);
4928 int num_offsets = instr->src[const_src].src.ssa->num_components;
4929 assert(const_offset);
4930 num_offsets = MIN2(num_offsets, instr->coord_components);
4931 if (num_offsets > 2)
4932 address[2] = LLVMBuildAdd(ctx->ac.builder,
4933 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4934 if (num_offsets > 1)
4935 address[1] = LLVMBuildAdd(ctx->ac.builder,
4936 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4937 address[0] = LLVMBuildAdd(ctx->ac.builder,
4938 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4939
4940 }
4941
4942 /* TODO TG4 support */
4943 if (instr->op == nir_texop_tg4) {
4944 if (instr->is_shadow)
4945 dmask = 1;
4946 else
4947 dmask = 1 << instr->component;
4948 }
4949 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4950 res_ptr, samp_ptr, address, count, dmask);
4951
4952 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4953
4954 if (instr->op == nir_texop_query_levels)
4955 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4956 else if (instr->is_shadow && instr->is_new_style_shadow &&
4957 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4958 instr->op != nir_texop_tg4)
4959 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4960 else if (instr->op == nir_texop_txs &&
4961 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4962 instr->is_array) {
4963 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4964 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4965 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4966 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4967 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4968 } else if (ctx->ac.chip_class >= GFX9 &&
4969 instr->op == nir_texop_txs &&
4970 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4971 instr->is_array) {
4972 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4973 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4974 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4975 ctx->ac.i32_1, "");
4976 } else if (instr->dest.ssa.num_components != 4)
4977 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4978
4979 write_result:
4980 if (result) {
4981 assert(instr->dest.is_ssa);
4982 result = ac_to_integer(&ctx->ac, result);
4983 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4984 }
4985 }
4986
4987
4988 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4989 {
4990 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4991 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4992
4993 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4994 _mesa_hash_table_insert(ctx->phis, instr, result);
4995 }
4996
4997 static void visit_post_phi(struct ac_nir_context *ctx,
4998 nir_phi_instr *instr,
4999 LLVMValueRef llvm_phi)
5000 {
5001 nir_foreach_phi_src(src, instr) {
5002 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5003 LLVMValueRef llvm_src = get_src(ctx, src->src);
5004
5005 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5006 }
5007 }
5008
5009 static void phi_post_pass(struct ac_nir_context *ctx)
5010 {
5011 struct hash_entry *entry;
5012 hash_table_foreach(ctx->phis, entry) {
5013 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5014 (LLVMValueRef)entry->data);
5015 }
5016 }
5017
5018
5019 static void visit_ssa_undef(struct ac_nir_context *ctx,
5020 const nir_ssa_undef_instr *instr)
5021 {
5022 unsigned num_components = instr->def.num_components;
5023 LLVMValueRef undef;
5024
5025 if (num_components == 1)
5026 undef = LLVMGetUndef(ctx->ac.i32);
5027 else {
5028 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5029 }
5030 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5031 }
5032
5033 static void visit_jump(struct ac_nir_context *ctx,
5034 const nir_jump_instr *instr)
5035 {
5036 switch (instr->type) {
5037 case nir_jump_break:
5038 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5039 LLVMClearInsertionPosition(ctx->ac.builder);
5040 break;
5041 case nir_jump_continue:
5042 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5043 LLVMClearInsertionPosition(ctx->ac.builder);
5044 break;
5045 default:
5046 fprintf(stderr, "Unknown NIR jump instr: ");
5047 nir_print_instr(&instr->instr, stderr);
5048 fprintf(stderr, "\n");
5049 abort();
5050 }
5051 }
5052
5053 static void visit_cf_list(struct ac_nir_context *ctx,
5054 struct exec_list *list);
5055
5056 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5057 {
5058 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5059 nir_foreach_instr(instr, block)
5060 {
5061 switch (instr->type) {
5062 case nir_instr_type_alu:
5063 visit_alu(ctx, nir_instr_as_alu(instr));
5064 break;
5065 case nir_instr_type_load_const:
5066 visit_load_const(ctx, nir_instr_as_load_const(instr));
5067 break;
5068 case nir_instr_type_intrinsic:
5069 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5070 break;
5071 case nir_instr_type_tex:
5072 visit_tex(ctx, nir_instr_as_tex(instr));
5073 break;
5074 case nir_instr_type_phi:
5075 visit_phi(ctx, nir_instr_as_phi(instr));
5076 break;
5077 case nir_instr_type_ssa_undef:
5078 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5079 break;
5080 case nir_instr_type_jump:
5081 visit_jump(ctx, nir_instr_as_jump(instr));
5082 break;
5083 default:
5084 fprintf(stderr, "Unknown NIR instr type: ");
5085 nir_print_instr(instr, stderr);
5086 fprintf(stderr, "\n");
5087 abort();
5088 }
5089 }
5090
5091 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5092 }
5093
5094 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5095 {
5096 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5097
5098 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5099 LLVMBasicBlockRef merge_block =
5100 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5101 LLVMBasicBlockRef if_block =
5102 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5103 LLVMBasicBlockRef else_block = merge_block;
5104 if (!exec_list_is_empty(&if_stmt->else_list))
5105 else_block = LLVMAppendBasicBlockInContext(
5106 ctx->ac.context, fn, "");
5107
5108 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5109 ctx->ac.i32_0, "");
5110 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5111
5112 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5113 visit_cf_list(ctx, &if_stmt->then_list);
5114 if (LLVMGetInsertBlock(ctx->ac.builder))
5115 LLVMBuildBr(ctx->ac.builder, merge_block);
5116
5117 if (!exec_list_is_empty(&if_stmt->else_list)) {
5118 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5119 visit_cf_list(ctx, &if_stmt->else_list);
5120 if (LLVMGetInsertBlock(ctx->ac.builder))
5121 LLVMBuildBr(ctx->ac.builder, merge_block);
5122 }
5123
5124 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5125 }
5126
5127 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5128 {
5129 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5130 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5131 LLVMBasicBlockRef break_parent = ctx->break_block;
5132
5133 ctx->continue_block =
5134 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5135 ctx->break_block =
5136 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5137
5138 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5139 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5140 visit_cf_list(ctx, &loop->body);
5141
5142 if (LLVMGetInsertBlock(ctx->ac.builder))
5143 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5144 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5145
5146 ctx->continue_block = continue_parent;
5147 ctx->break_block = break_parent;
5148 }
5149
5150 static void visit_cf_list(struct ac_nir_context *ctx,
5151 struct exec_list *list)
5152 {
5153 foreach_list_typed(nir_cf_node, node, node, list)
5154 {
5155 switch (node->type) {
5156 case nir_cf_node_block:
5157 visit_block(ctx, nir_cf_node_as_block(node));
5158 break;
5159
5160 case nir_cf_node_if:
5161 visit_if(ctx, nir_cf_node_as_if(node));
5162 break;
5163
5164 case nir_cf_node_loop:
5165 visit_loop(ctx, nir_cf_node_as_loop(node));
5166 break;
5167
5168 default:
5169 assert(0);
5170 }
5171 }
5172 }
5173
5174 static void
5175 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5176 struct nir_variable *variable)
5177 {
5178 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5179 LLVMValueRef t_offset;
5180 LLVMValueRef t_list;
5181 LLVMValueRef input;
5182 LLVMValueRef buffer_index;
5183 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5184 int idx = variable->data.location;
5185 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5186
5187 variable->data.driver_location = idx * 4;
5188
5189 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5190 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5191 ctx->abi.start_instance, "");
5192 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5193 ctx->shader_info->vs.vgpr_comp_cnt);
5194 } else
5195 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5196 ctx->abi.base_vertex, "");
5197
5198 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5199 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5200
5201 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5202
5203 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5204 buffer_index,
5205 ctx->ac.i32_0,
5206 true);
5207
5208 for (unsigned chan = 0; chan < 4; chan++) {
5209 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5210 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5211 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5212 input, llvm_chan, ""));
5213 }
5214 }
5215 }
5216
5217 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5218 unsigned attr,
5219 LLVMValueRef interp_param,
5220 LLVMValueRef prim_mask,
5221 LLVMValueRef result[4])
5222 {
5223 LLVMValueRef attr_number;
5224 unsigned chan;
5225 LLVMValueRef i, j;
5226 bool interp = interp_param != NULL;
5227
5228 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5229
5230 /* fs.constant returns the param from the middle vertex, so it's not
5231 * really useful for flat shading. It's meant to be used for custom
5232 * interpolation (but the intrinsic can't fetch from the other two
5233 * vertices).
5234 *
5235 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5236 * to do the right thing. The only reason we use fs.constant is that
5237 * fs.interp cannot be used on integers, because they can be equal
5238 * to NaN.
5239 */
5240 if (interp) {
5241 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5242 ctx->ac.v2f32, "");
5243
5244 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5245 ctx->ac.i32_0, "");
5246 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5247 ctx->ac.i32_1, "");
5248 }
5249
5250 for (chan = 0; chan < 4; chan++) {
5251 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5252
5253 if (interp) {
5254 result[chan] = ac_build_fs_interp(&ctx->ac,
5255 llvm_chan,
5256 attr_number,
5257 prim_mask, i, j);
5258 } else {
5259 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5260 LLVMConstInt(ctx->ac.i32, 2, false),
5261 llvm_chan,
5262 attr_number,
5263 prim_mask);
5264 }
5265 }
5266 }
5267
5268 static void
5269 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5270 struct nir_variable *variable)
5271 {
5272 int idx = variable->data.location;
5273 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5274 LLVMValueRef interp;
5275
5276 variable->data.driver_location = idx * 4;
5277 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5278
5279 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5280 unsigned interp_type;
5281 if (variable->data.sample) {
5282 interp_type = INTERP_SAMPLE;
5283 ctx->shader_info->info.ps.force_persample = true;
5284 } else if (variable->data.centroid)
5285 interp_type = INTERP_CENTROID;
5286 else
5287 interp_type = INTERP_CENTER;
5288
5289 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5290 } else
5291 interp = NULL;
5292
5293 for (unsigned i = 0; i < attrib_count; ++i)
5294 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5295
5296 }
5297
5298 static void
5299 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5300 struct nir_shader *nir) {
5301 nir_foreach_variable(variable, &nir->inputs)
5302 handle_vs_input_decl(ctx, variable);
5303 }
5304
5305 static void
5306 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5307 struct nir_shader *nir)
5308 {
5309 if (!ctx->options->key.fs.multisample)
5310 return;
5311
5312 bool uses_center = false;
5313 bool uses_centroid = false;
5314 nir_foreach_variable(variable, &nir->inputs) {
5315 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5316 variable->data.sample)
5317 continue;
5318
5319 if (variable->data.centroid)
5320 uses_centroid = true;
5321 else
5322 uses_center = true;
5323 }
5324
5325 if (uses_center && uses_centroid) {
5326 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5327 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5328 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5329 }
5330 }
5331
5332 static void
5333 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5334 struct nir_shader *nir)
5335 {
5336 prepare_interp_optimize(ctx, nir);
5337
5338 nir_foreach_variable(variable, &nir->inputs)
5339 handle_fs_input_decl(ctx, variable);
5340
5341 unsigned index = 0;
5342
5343 if (ctx->shader_info->info.ps.uses_input_attachments ||
5344 ctx->shader_info->info.needs_multiview_view_index)
5345 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5346
5347 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5348 LLVMValueRef interp_param;
5349 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5350
5351 if (!(ctx->input_mask & (1ull << i)))
5352 continue;
5353
5354 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5355 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5356 interp_param = *inputs;
5357 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5358 inputs);
5359
5360 if (!interp_param)
5361 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5362 ++index;
5363 } else if (i == VARYING_SLOT_POS) {
5364 for(int i = 0; i < 3; ++i)
5365 inputs[i] = ctx->abi.frag_pos[i];
5366
5367 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5368 ctx->abi.frag_pos[3]);
5369 }
5370 }
5371 ctx->shader_info->fs.num_interp = index;
5372 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5373 ctx->shader_info->fs.has_pcoord = true;
5374 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5375 ctx->shader_info->fs.prim_id_input = true;
5376 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5377 ctx->shader_info->fs.layer_input = true;
5378 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5379
5380 if (ctx->shader_info->info.needs_multiview_view_index)
5381 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5382 }
5383
5384 static LLVMValueRef
5385 ac_build_alloca(struct ac_llvm_context *ac,
5386 LLVMTypeRef type,
5387 const char *name)
5388 {
5389 LLVMBuilderRef builder = ac->builder;
5390 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5391 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5392 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5393 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5394 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5395 LLVMValueRef res;
5396
5397 if (first_instr) {
5398 LLVMPositionBuilderBefore(first_builder, first_instr);
5399 } else {
5400 LLVMPositionBuilderAtEnd(first_builder, first_block);
5401 }
5402
5403 res = LLVMBuildAlloca(first_builder, type, name);
5404 LLVMBuildStore(builder, LLVMConstNull(type), res);
5405
5406 LLVMDisposeBuilder(first_builder);
5407
5408 return res;
5409 }
5410
5411 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5412 LLVMTypeRef type,
5413 const char *name)
5414 {
5415 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5416 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5417 return ptr;
5418 }
5419
5420 static void
5421 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5422 struct nir_variable *variable,
5423 struct nir_shader *shader,
5424 gl_shader_stage stage)
5425 {
5426 int idx = variable->data.location + variable->data.index;
5427 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5428 uint64_t mask_attribs;
5429
5430 variable->data.driver_location = idx * 4;
5431
5432 /* tess ctrl has it's own load/store paths for outputs */
5433 if (stage == MESA_SHADER_TESS_CTRL)
5434 return;
5435
5436 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5437 if (stage == MESA_SHADER_VERTEX ||
5438 stage == MESA_SHADER_TESS_EVAL ||
5439 stage == MESA_SHADER_GEOMETRY) {
5440 if (idx == VARYING_SLOT_CLIP_DIST0) {
5441 int length = shader->info.clip_distance_array_size +
5442 shader->info.cull_distance_array_size;
5443 if (stage == MESA_SHADER_VERTEX) {
5444 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5445 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5446 }
5447 if (stage == MESA_SHADER_TESS_EVAL) {
5448 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5449 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5450 }
5451
5452 if (length > 4)
5453 attrib_count = 2;
5454 else
5455 attrib_count = 1;
5456 mask_attribs = 1ull << idx;
5457 }
5458 }
5459
5460 ctx->output_mask |= mask_attribs;
5461 }
5462
5463 static void
5464 handle_shader_output_decl(struct ac_nir_context *ctx,
5465 struct nir_shader *nir,
5466 struct nir_variable *variable)
5467 {
5468 unsigned output_loc = variable->data.driver_location / 4;
5469 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5470
5471 /* tess ctrl has it's own load/store paths for outputs */
5472 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5473 return;
5474
5475 if (ctx->stage == MESA_SHADER_VERTEX ||
5476 ctx->stage == MESA_SHADER_TESS_EVAL ||
5477 ctx->stage == MESA_SHADER_GEOMETRY) {
5478 int idx = variable->data.location + variable->data.index;
5479 if (idx == VARYING_SLOT_CLIP_DIST0) {
5480 int length = nir->info.clip_distance_array_size +
5481 nir->info.cull_distance_array_size;
5482
5483 if (length > 4)
5484 attrib_count = 2;
5485 else
5486 attrib_count = 1;
5487 }
5488 }
5489
5490 for (unsigned i = 0; i < attrib_count; ++i) {
5491 for (unsigned chan = 0; chan < 4; chan++) {
5492 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5493 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5494 }
5495 }
5496 }
5497
5498 static LLVMTypeRef
5499 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5500 enum glsl_base_type type)
5501 {
5502 switch (type) {
5503 case GLSL_TYPE_INT:
5504 case GLSL_TYPE_UINT:
5505 case GLSL_TYPE_BOOL:
5506 case GLSL_TYPE_SUBROUTINE:
5507 return ctx->ac.i32;
5508 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5509 return ctx->ac.f32;
5510 case GLSL_TYPE_INT64:
5511 case GLSL_TYPE_UINT64:
5512 return ctx->ac.i64;
5513 case GLSL_TYPE_DOUBLE:
5514 return ctx->ac.f64;
5515 default:
5516 unreachable("unknown GLSL type");
5517 }
5518 }
5519
5520 static LLVMTypeRef
5521 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5522 const struct glsl_type *type)
5523 {
5524 if (glsl_type_is_scalar(type)) {
5525 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5526 }
5527
5528 if (glsl_type_is_vector(type)) {
5529 return LLVMVectorType(
5530 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5531 glsl_get_vector_elements(type));
5532 }
5533
5534 if (glsl_type_is_matrix(type)) {
5535 return LLVMArrayType(
5536 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5537 glsl_get_matrix_columns(type));
5538 }
5539
5540 if (glsl_type_is_array(type)) {
5541 return LLVMArrayType(
5542 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5543 glsl_get_length(type));
5544 }
5545
5546 assert(glsl_type_is_struct(type));
5547
5548 LLVMTypeRef member_types[glsl_get_length(type)];
5549
5550 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5551 member_types[i] =
5552 glsl_to_llvm_type(ctx,
5553 glsl_get_struct_field(type, i));
5554 }
5555
5556 return LLVMStructTypeInContext(ctx->context, member_types,
5557 glsl_get_length(type), false);
5558 }
5559
5560 static void
5561 setup_locals(struct ac_nir_context *ctx,
5562 struct nir_function *func)
5563 {
5564 int i, j;
5565 ctx->num_locals = 0;
5566 nir_foreach_variable(variable, &func->impl->locals) {
5567 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5568 variable->data.driver_location = ctx->num_locals * 4;
5569 ctx->num_locals += attrib_count;
5570 }
5571 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5572 if (!ctx->locals)
5573 return;
5574
5575 for (i = 0; i < ctx->num_locals; i++) {
5576 for (j = 0; j < 4; j++) {
5577 ctx->locals[i * 4 + j] =
5578 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5579 }
5580 }
5581 }
5582
5583 static void
5584 setup_shared(struct ac_nir_context *ctx,
5585 struct nir_shader *nir)
5586 {
5587 nir_foreach_variable(variable, &nir->shared) {
5588 LLVMValueRef shared =
5589 LLVMAddGlobalInAddressSpace(
5590 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5591 variable->name ? variable->name : "",
5592 LOCAL_ADDR_SPACE);
5593 _mesa_hash_table_insert(ctx->vars, variable, shared);
5594 }
5595 }
5596
5597 static LLVMValueRef
5598 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5599 {
5600 v = ac_to_float(ctx, v);
5601 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5602 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5603 }
5604
5605
5606 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5607 LLVMValueRef src0, LLVMValueRef src1)
5608 {
5609 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5610 LLVMValueRef comp[2];
5611
5612 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5613 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5614 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5615 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5616 }
5617
5618 /* Initialize arguments for the shader export intrinsic */
5619 static void
5620 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5621 LLVMValueRef *values,
5622 unsigned target,
5623 struct ac_export_args *args)
5624 {
5625 /* Default is 0xf. Adjusted below depending on the format. */
5626 args->enabled_channels = 0xf;
5627
5628 /* Specify whether the EXEC mask represents the valid mask */
5629 args->valid_mask = 0;
5630
5631 /* Specify whether this is the last export */
5632 args->done = 0;
5633
5634 /* Specify the target we are exporting */
5635 args->target = target;
5636
5637 args->compr = false;
5638 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5639 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5640 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5641 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5642
5643 if (!values)
5644 return;
5645
5646 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5647 LLVMValueRef val[4];
5648 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5649 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5650 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5651 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5652
5653 switch(col_format) {
5654 case V_028714_SPI_SHADER_ZERO:
5655 args->enabled_channels = 0; /* writemask */
5656 args->target = V_008DFC_SQ_EXP_NULL;
5657 break;
5658
5659 case V_028714_SPI_SHADER_32_R:
5660 args->enabled_channels = 1;
5661 args->out[0] = values[0];
5662 break;
5663
5664 case V_028714_SPI_SHADER_32_GR:
5665 args->enabled_channels = 0x3;
5666 args->out[0] = values[0];
5667 args->out[1] = values[1];
5668 break;
5669
5670 case V_028714_SPI_SHADER_32_AR:
5671 args->enabled_channels = 0x9;
5672 args->out[0] = values[0];
5673 args->out[3] = values[3];
5674 break;
5675
5676 case V_028714_SPI_SHADER_FP16_ABGR:
5677 args->compr = 1;
5678
5679 for (unsigned chan = 0; chan < 2; chan++) {
5680 LLVMValueRef pack_args[2] = {
5681 values[2 * chan],
5682 values[2 * chan + 1]
5683 };
5684 LLVMValueRef packed;
5685
5686 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5687 args->out[chan] = packed;
5688 }
5689 break;
5690
5691 case V_028714_SPI_SHADER_UNORM16_ABGR:
5692 for (unsigned chan = 0; chan < 4; chan++) {
5693 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5694 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5695 LLVMConstReal(ctx->ac.f32, 65535), "");
5696 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5697 LLVMConstReal(ctx->ac.f32, 0.5), "");
5698 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5699 ctx->ac.i32, "");
5700 }
5701
5702 args->compr = 1;
5703 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5704 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5705 break;
5706
5707 case V_028714_SPI_SHADER_SNORM16_ABGR:
5708 for (unsigned chan = 0; chan < 4; chan++) {
5709 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5710 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5711 LLVMConstReal(ctx->ac.f32, 32767), "");
5712
5713 /* If positive, add 0.5, else add -0.5. */
5714 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5715 LLVMBuildSelect(ctx->builder,
5716 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5717 val[chan], ctx->ac.f32_0, ""),
5718 LLVMConstReal(ctx->ac.f32, 0.5),
5719 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5720 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5721 }
5722
5723 args->compr = 1;
5724 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5725 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5726 break;
5727
5728 case V_028714_SPI_SHADER_UINT16_ABGR: {
5729 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5730 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5731 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5732
5733 for (unsigned chan = 0; chan < 4; chan++) {
5734 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5735 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5736 }
5737
5738 args->compr = 1;
5739 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5740 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5741 break;
5742 }
5743
5744 case V_028714_SPI_SHADER_SINT16_ABGR: {
5745 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5746 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5747 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5748 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5749 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5750 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5751
5752 /* Clamp. */
5753 for (unsigned chan = 0; chan < 4; chan++) {
5754 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5755 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5756 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5757 }
5758
5759 args->compr = 1;
5760 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5761 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5762 break;
5763 }
5764
5765 default:
5766 case V_028714_SPI_SHADER_32_ABGR:
5767 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5768 break;
5769 }
5770 } else
5771 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5772
5773 for (unsigned i = 0; i < 4; ++i)
5774 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5775 }
5776
5777 static void
5778 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5779 bool export_prim_id,
5780 struct ac_vs_output_info *outinfo)
5781 {
5782 uint32_t param_count = 0;
5783 unsigned target;
5784 unsigned pos_idx, num_pos_exports = 0;
5785 struct ac_export_args args, pos_args[4] = {};
5786 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5787 int i;
5788
5789 if (ctx->options->key.has_multiview_view_index) {
5790 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5791 if(!*tmp_out) {
5792 for(unsigned i = 0; i < 4; ++i)
5793 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5794 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5795 }
5796
5797 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5798 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5799 }
5800
5801 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5802 sizeof(outinfo->vs_output_param_offset));
5803
5804 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5805 LLVMValueRef slots[8];
5806 unsigned j;
5807
5808 if (outinfo->cull_dist_mask)
5809 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5810
5811 i = VARYING_SLOT_CLIP_DIST0;
5812 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5813 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5814 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5815
5816 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5817 slots[i] = LLVMGetUndef(ctx->ac.f32);
5818
5819 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5820 target = V_008DFC_SQ_EXP_POS + 3;
5821 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5822 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5823 &args, sizeof(args));
5824 }
5825
5826 target = V_008DFC_SQ_EXP_POS + 2;
5827 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5828 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5829 &args, sizeof(args));
5830
5831 }
5832
5833 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5834 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5835 for (unsigned j = 0; j < 4; j++)
5836 pos_values[j] = LLVMBuildLoad(ctx->builder,
5837 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5838 }
5839 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5840
5841 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5842 outinfo->writes_pointsize = true;
5843 psize_value = LLVMBuildLoad(ctx->builder,
5844 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5845 }
5846
5847 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5848 outinfo->writes_layer = true;
5849 layer_value = LLVMBuildLoad(ctx->builder,
5850 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5851 }
5852
5853 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5854 outinfo->writes_viewport_index = true;
5855 viewport_index_value = LLVMBuildLoad(ctx->builder,
5856 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5857 }
5858
5859 if (outinfo->writes_pointsize ||
5860 outinfo->writes_layer ||
5861 outinfo->writes_viewport_index) {
5862 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5863 (outinfo->writes_layer == true ? 4 : 0));
5864 pos_args[1].valid_mask = 0;
5865 pos_args[1].done = 0;
5866 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5867 pos_args[1].compr = 0;
5868 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5869 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5870 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5871 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5872
5873 if (outinfo->writes_pointsize == true)
5874 pos_args[1].out[0] = psize_value;
5875 if (outinfo->writes_layer == true)
5876 pos_args[1].out[2] = layer_value;
5877 if (outinfo->writes_viewport_index == true) {
5878 if (ctx->options->chip_class >= GFX9) {
5879 /* GFX9 has the layer in out.z[10:0] and the viewport
5880 * index in out.z[19:16].
5881 */
5882 LLVMValueRef v = viewport_index_value;
5883 v = ac_to_integer(&ctx->ac, v);
5884 v = LLVMBuildShl(ctx->builder, v,
5885 LLVMConstInt(ctx->ac.i32, 16, false),
5886 "");
5887 v = LLVMBuildOr(ctx->builder, v,
5888 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5889
5890 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5891 pos_args[1].enabled_channels |= 1 << 2;
5892 } else {
5893 pos_args[1].out[3] = viewport_index_value;
5894 pos_args[1].enabled_channels |= 1 << 3;
5895 }
5896 }
5897 }
5898 for (i = 0; i < 4; i++) {
5899 if (pos_args[i].out[0])
5900 num_pos_exports++;
5901 }
5902
5903 pos_idx = 0;
5904 for (i = 0; i < 4; i++) {
5905 if (!pos_args[i].out[0])
5906 continue;
5907
5908 /* Specify the target we are exporting */
5909 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5910 if (pos_idx == num_pos_exports)
5911 pos_args[i].done = 1;
5912 ac_build_export(&ctx->ac, &pos_args[i]);
5913 }
5914
5915 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5916 LLVMValueRef values[4];
5917 if (!(ctx->output_mask & (1ull << i)))
5918 continue;
5919
5920 for (unsigned j = 0; j < 4; j++)
5921 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5922 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5923
5924 if (i == VARYING_SLOT_LAYER) {
5925 target = V_008DFC_SQ_EXP_PARAM + param_count;
5926 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5927 param_count++;
5928 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5929 target = V_008DFC_SQ_EXP_PARAM + param_count;
5930 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5931 param_count++;
5932 } else if (i >= VARYING_SLOT_VAR0) {
5933 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5934 target = V_008DFC_SQ_EXP_PARAM + param_count;
5935 outinfo->vs_output_param_offset[i] = param_count;
5936 param_count++;
5937 } else
5938 continue;
5939
5940 si_llvm_init_export_args(ctx, values, target, &args);
5941
5942 if (target >= V_008DFC_SQ_EXP_POS &&
5943 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5944 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5945 &args, sizeof(args));
5946 } else {
5947 ac_build_export(&ctx->ac, &args);
5948 }
5949 }
5950
5951 if (export_prim_id) {
5952 LLVMValueRef values[4];
5953 target = V_008DFC_SQ_EXP_PARAM + param_count;
5954 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5955 param_count++;
5956
5957 values[0] = ctx->vs_prim_id;
5958 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5959 ctx->shader_info->vs.vgpr_comp_cnt);
5960 for (unsigned j = 1; j < 4; j++)
5961 values[j] = ctx->ac.f32_0;
5962 si_llvm_init_export_args(ctx, values, target, &args);
5963 ac_build_export(&ctx->ac, &args);
5964 outinfo->export_prim_id = true;
5965 }
5966
5967 outinfo->pos_exports = num_pos_exports;
5968 outinfo->param_exports = param_count;
5969 }
5970
5971 static void
5972 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5973 struct ac_es_output_info *outinfo)
5974 {
5975 int j;
5976 uint64_t max_output_written = 0;
5977 LLVMValueRef lds_base = NULL;
5978
5979 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5980 int param_index;
5981 int length = 4;
5982
5983 if (!(ctx->output_mask & (1ull << i)))
5984 continue;
5985
5986 if (i == VARYING_SLOT_CLIP_DIST0)
5987 length = ctx->num_output_clips + ctx->num_output_culls;
5988
5989 param_index = shader_io_get_unique_index(i);
5990
5991 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5992 }
5993
5994 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5995
5996 if (ctx->ac.chip_class >= GFX9) {
5997 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5998 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5999 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6000 LLVMConstInt(ctx->ac.i32, 24, false),
6001 LLVMConstInt(ctx->ac.i32, 4, false), false);
6002 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6003 LLVMBuildMul(ctx->ac.builder, wave_idx,
6004 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6005 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6006 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6007 }
6008
6009 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6010 LLVMValueRef dw_addr;
6011 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6012 int param_index;
6013 int length = 4;
6014
6015 if (!(ctx->output_mask & (1ull << i)))
6016 continue;
6017
6018 if (i == VARYING_SLOT_CLIP_DIST0)
6019 length = ctx->num_output_clips + ctx->num_output_culls;
6020
6021 param_index = shader_io_get_unique_index(i);
6022
6023 if (lds_base) {
6024 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6025 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6026 "");
6027 }
6028 for (j = 0; j < length; j++) {
6029 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6030 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6031
6032 if (ctx->ac.chip_class >= GFX9) {
6033 ac_lds_store(&ctx->ac, dw_addr,
6034 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6035 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6036 } else {
6037 ac_build_buffer_store_dword(&ctx->ac,
6038 ctx->esgs_ring,
6039 out_val, 1,
6040 NULL, ctx->es2gs_offset,
6041 (4 * param_index + j) * 4,
6042 1, 1, true, true);
6043 }
6044 }
6045 }
6046 }
6047
6048 static void
6049 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6050 {
6051 LLVMValueRef vertex_id = ctx->rel_auto_id;
6052 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6053 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6054 vertex_dw_stride, "");
6055
6056 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6057 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6058 int length = 4;
6059
6060 if (!(ctx->output_mask & (1ull << i)))
6061 continue;
6062
6063 if (i == VARYING_SLOT_CLIP_DIST0)
6064 length = ctx->num_output_clips + ctx->num_output_culls;
6065 int param = shader_io_get_unique_index(i);
6066 mark_tess_output(ctx, false, param);
6067 if (length > 4)
6068 mark_tess_output(ctx, false, param + 1);
6069 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6070 LLVMConstInt(ctx->ac.i32, param * 4, false),
6071 "");
6072 for (unsigned j = 0; j < length; j++) {
6073 ac_lds_store(&ctx->ac, dw_addr,
6074 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6075 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6076 }
6077 }
6078 }
6079
6080 struct ac_build_if_state
6081 {
6082 struct nir_to_llvm_context *ctx;
6083 LLVMValueRef condition;
6084 LLVMBasicBlockRef entry_block;
6085 LLVMBasicBlockRef true_block;
6086 LLVMBasicBlockRef false_block;
6087 LLVMBasicBlockRef merge_block;
6088 };
6089
6090 static LLVMBasicBlockRef
6091 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6092 {
6093 LLVMBasicBlockRef current_block;
6094 LLVMBasicBlockRef next_block;
6095 LLVMBasicBlockRef new_block;
6096
6097 /* get current basic block */
6098 current_block = LLVMGetInsertBlock(ctx->builder);
6099
6100 /* chqeck if there's another block after this one */
6101 next_block = LLVMGetNextBasicBlock(current_block);
6102 if (next_block) {
6103 /* insert the new block before the next block */
6104 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6105 }
6106 else {
6107 /* append new block after current block */
6108 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6109 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6110 }
6111 return new_block;
6112 }
6113
6114 static void
6115 ac_nir_build_if(struct ac_build_if_state *ifthen,
6116 struct nir_to_llvm_context *ctx,
6117 LLVMValueRef condition)
6118 {
6119 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6120
6121 memset(ifthen, 0, sizeof *ifthen);
6122 ifthen->ctx = ctx;
6123 ifthen->condition = condition;
6124 ifthen->entry_block = block;
6125
6126 /* create endif/merge basic block for the phi functions */
6127 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6128
6129 /* create/insert true_block before merge_block */
6130 ifthen->true_block =
6131 LLVMInsertBasicBlockInContext(ctx->context,
6132 ifthen->merge_block,
6133 "if-true-block");
6134
6135 /* successive code goes into the true block */
6136 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6137 }
6138
6139 /**
6140 * End a conditional.
6141 */
6142 static void
6143 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6144 {
6145 LLVMBuilderRef builder = ifthen->ctx->builder;
6146
6147 /* Insert branch to the merge block from current block */
6148 LLVMBuildBr(builder, ifthen->merge_block);
6149
6150 /*
6151 * Now patch in the various branch instructions.
6152 */
6153
6154 /* Insert the conditional branch instruction at the end of entry_block */
6155 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6156 if (ifthen->false_block) {
6157 /* we have an else clause */
6158 LLVMBuildCondBr(builder, ifthen->condition,
6159 ifthen->true_block, ifthen->false_block);
6160 }
6161 else {
6162 /* no else clause */
6163 LLVMBuildCondBr(builder, ifthen->condition,
6164 ifthen->true_block, ifthen->merge_block);
6165 }
6166
6167 /* Resume building code at end of the ifthen->merge_block */
6168 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6169 }
6170
6171 static void
6172 write_tess_factors(struct nir_to_llvm_context *ctx)
6173 {
6174 unsigned stride, outer_comps, inner_comps;
6175 struct ac_build_if_state if_ctx, inner_if_ctx;
6176 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6177 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6178 unsigned tess_inner_index, tess_outer_index;
6179 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6180 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6181 int i;
6182 emit_barrier(ctx);
6183
6184 switch (ctx->options->key.tcs.primitive_mode) {
6185 case GL_ISOLINES:
6186 stride = 2;
6187 outer_comps = 2;
6188 inner_comps = 0;
6189 break;
6190 case GL_TRIANGLES:
6191 stride = 4;
6192 outer_comps = 3;
6193 inner_comps = 1;
6194 break;
6195 case GL_QUADS:
6196 stride = 6;
6197 outer_comps = 4;
6198 inner_comps = 2;
6199 break;
6200 default:
6201 return;
6202 }
6203
6204 ac_nir_build_if(&if_ctx, ctx,
6205 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6206 invocation_id, ctx->ac.i32_0, ""));
6207
6208 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6209 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6210
6211 mark_tess_output(ctx, true, tess_inner_index);
6212 mark_tess_output(ctx, true, tess_outer_index);
6213 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6214 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6215 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6216 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6217 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6218
6219 for (i = 0; i < 4; i++) {
6220 inner[i] = LLVMGetUndef(ctx->ac.i32);
6221 outer[i] = LLVMGetUndef(ctx->ac.i32);
6222 }
6223
6224 // LINES reverseal
6225 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6226 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6227 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6228 ctx->ac.i32_1, "");
6229 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6230 } else {
6231 for (i = 0; i < outer_comps; i++) {
6232 outer[i] = out[i] =
6233 ac_lds_load(&ctx->ac, lds_outer);
6234 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6235 ctx->ac.i32_1, "");
6236 }
6237 for (i = 0; i < inner_comps; i++) {
6238 inner[i] = out[outer_comps+i] =
6239 ac_lds_load(&ctx->ac, lds_inner);
6240 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6241 ctx->ac.i32_1, "");
6242 }
6243 }
6244
6245 /* Convert the outputs to vectors for stores. */
6246 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6247 vec1 = NULL;
6248
6249 if (stride > 4)
6250 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6251
6252
6253 buffer = ctx->hs_ring_tess_factor;
6254 tf_base = ctx->tess_factor_offset;
6255 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6256 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6257 unsigned tf_offset = 0;
6258
6259 if (ctx->options->chip_class <= VI) {
6260 ac_nir_build_if(&inner_if_ctx, ctx,
6261 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6262 rel_patch_id, ctx->ac.i32_0, ""));
6263
6264 /* Store the dynamic HS control word. */
6265 ac_build_buffer_store_dword(&ctx->ac, buffer,
6266 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6267 1, ctx->ac.i32_0, tf_base,
6268 0, 1, 0, true, false);
6269 tf_offset += 4;
6270
6271 ac_nir_build_endif(&inner_if_ctx);
6272 }
6273
6274 /* Store the tessellation factors. */
6275 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6276 MIN2(stride, 4), byteoffset, tf_base,
6277 tf_offset, 1, 0, true, false);
6278 if (vec1)
6279 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6280 stride - 4, byteoffset, tf_base,
6281 16 + tf_offset, 1, 0, true, false);
6282
6283 //store to offchip for TES to read - only if TES reads them
6284 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6285 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6286 LLVMValueRef tf_inner_offset;
6287 unsigned param_outer, param_inner;
6288
6289 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6290 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6291 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6292
6293 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6294 util_next_power_of_two(outer_comps));
6295
6296 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6297 outer_comps, tf_outer_offset,
6298 ctx->oc_lds, 0, 1, 0, true, false);
6299 if (inner_comps) {
6300 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6301 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6302 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6303
6304 inner_vec = inner_comps == 1 ? inner[0] :
6305 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6306 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6307 inner_comps, tf_inner_offset,
6308 ctx->oc_lds, 0, 1, 0, true, false);
6309 }
6310 }
6311 ac_nir_build_endif(&if_ctx);
6312 }
6313
6314 static void
6315 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6316 {
6317 write_tess_factors(ctx);
6318 }
6319
6320 static bool
6321 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6322 LLVMValueRef *color, unsigned param, bool is_last,
6323 struct ac_export_args *args)
6324 {
6325 /* Export */
6326 si_llvm_init_export_args(ctx, color, param,
6327 args);
6328
6329 if (is_last) {
6330 args->valid_mask = 1; /* whether the EXEC mask is valid */
6331 args->done = 1; /* DONE bit */
6332 } else if (!args->enabled_channels)
6333 return false; /* unnecessary NULL export */
6334
6335 return true;
6336 }
6337
6338 static void
6339 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6340 LLVMValueRef depth, LLVMValueRef stencil,
6341 LLVMValueRef samplemask)
6342 {
6343 struct ac_export_args args;
6344
6345 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6346
6347 ac_build_export(&ctx->ac, &args);
6348 }
6349
6350 static void
6351 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6352 {
6353 unsigned index = 0;
6354 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6355 struct ac_export_args color_args[8];
6356
6357 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6358 LLVMValueRef values[4];
6359
6360 if (!(ctx->output_mask & (1ull << i)))
6361 continue;
6362
6363 if (i == FRAG_RESULT_DEPTH) {
6364 ctx->shader_info->fs.writes_z = true;
6365 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6366 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6367 } else if (i == FRAG_RESULT_STENCIL) {
6368 ctx->shader_info->fs.writes_stencil = true;
6369 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6370 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6371 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6372 ctx->shader_info->fs.writes_sample_mask = true;
6373 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6374 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6375 } else {
6376 bool last = false;
6377 for (unsigned j = 0; j < 4; j++)
6378 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6379 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6380
6381 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6382 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6383
6384 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6385 if (ret)
6386 index++;
6387 }
6388 }
6389
6390 for (unsigned i = 0; i < index; i++)
6391 ac_build_export(&ctx->ac, &color_args[i]);
6392 if (depth || stencil || samplemask)
6393 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6394 else if (!index) {
6395 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6396 ac_build_export(&ctx->ac, &color_args[0]);
6397 }
6398
6399 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6400 }
6401
6402 static void
6403 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6404 {
6405 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6406 }
6407
6408 static void
6409 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6410 LLVMValueRef *addrs)
6411 {
6412 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6413
6414 switch (ctx->stage) {
6415 case MESA_SHADER_VERTEX:
6416 if (ctx->options->key.vs.as_ls)
6417 handle_ls_outputs_post(ctx);
6418 else if (ctx->options->key.vs.as_es)
6419 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6420 else
6421 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6422 &ctx->shader_info->vs.outinfo);
6423 break;
6424 case MESA_SHADER_FRAGMENT:
6425 handle_fs_outputs_post(ctx);
6426 break;
6427 case MESA_SHADER_GEOMETRY:
6428 emit_gs_epilogue(ctx);
6429 break;
6430 case MESA_SHADER_TESS_CTRL:
6431 handle_tcs_outputs_post(ctx);
6432 break;
6433 case MESA_SHADER_TESS_EVAL:
6434 if (ctx->options->key.tes.as_es)
6435 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6436 else
6437 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6438 &ctx->shader_info->tes.outinfo);
6439 break;
6440 default:
6441 break;
6442 }
6443 }
6444
6445 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6446 {
6447 LLVMPassManagerRef passmgr;
6448 /* Create the pass manager */
6449 passmgr = LLVMCreateFunctionPassManagerForModule(
6450 ctx->module);
6451
6452 /* This pass should eliminate all the load and store instructions */
6453 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6454
6455 /* Add some optimization passes */
6456 LLVMAddScalarReplAggregatesPass(passmgr);
6457 LLVMAddLICMPass(passmgr);
6458 LLVMAddAggressiveDCEPass(passmgr);
6459 LLVMAddCFGSimplificationPass(passmgr);
6460 LLVMAddInstructionCombiningPass(passmgr);
6461
6462 /* Run the pass */
6463 LLVMInitializeFunctionPassManager(passmgr);
6464 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6465 LLVMFinalizeFunctionPassManager(passmgr);
6466
6467 LLVMDisposeBuilder(ctx->builder);
6468 LLVMDisposePassManager(passmgr);
6469 }
6470
6471 static void
6472 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6473 {
6474 struct ac_vs_output_info *outinfo;
6475
6476 switch (ctx->stage) {
6477 case MESA_SHADER_FRAGMENT:
6478 case MESA_SHADER_COMPUTE:
6479 case MESA_SHADER_TESS_CTRL:
6480 case MESA_SHADER_GEOMETRY:
6481 return;
6482 case MESA_SHADER_VERTEX:
6483 if (ctx->options->key.vs.as_ls ||
6484 ctx->options->key.vs.as_es)
6485 return;
6486 outinfo = &ctx->shader_info->vs.outinfo;
6487 break;
6488 case MESA_SHADER_TESS_EVAL:
6489 if (ctx->options->key.vs.as_es)
6490 return;
6491 outinfo = &ctx->shader_info->tes.outinfo;
6492 break;
6493 default:
6494 unreachable("Unhandled shader type");
6495 }
6496
6497 ac_optimize_vs_outputs(&ctx->ac,
6498 ctx->main_function,
6499 outinfo->vs_output_param_offset,
6500 VARYING_SLOT_MAX,
6501 &outinfo->param_exports);
6502 }
6503
6504 static void
6505 ac_setup_rings(struct nir_to_llvm_context *ctx)
6506 {
6507 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6508 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6509 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6510 }
6511
6512 if (ctx->is_gs_copy_shader) {
6513 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6514 }
6515 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6516 LLVMValueRef tmp;
6517 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6518 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6519
6520 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6521
6522 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6523 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6524 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6525 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6526 }
6527
6528 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6529 ctx->stage == MESA_SHADER_TESS_EVAL) {
6530 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6531 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6532 }
6533 }
6534
6535 static unsigned
6536 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6537 const struct nir_shader *nir)
6538 {
6539 switch (nir->info.stage) {
6540 case MESA_SHADER_TESS_CTRL:
6541 return chip_class >= CIK ? 128 : 64;
6542 case MESA_SHADER_GEOMETRY:
6543 return chip_class >= GFX9 ? 128 : 64;
6544 case MESA_SHADER_COMPUTE:
6545 break;
6546 default:
6547 return 0;
6548 }
6549
6550 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6551 nir->info.cs.local_size[1] *
6552 nir->info.cs.local_size[2];
6553 return max_workgroup_size;
6554 }
6555
6556 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6557 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6558 {
6559 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6560 LLVMConstInt(ctx->ac.i32, 8, false),
6561 LLVMConstInt(ctx->ac.i32, 8, false), false);
6562 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6563 ctx->ac.i32_0, "");
6564 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6565 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6566 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6567 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6568 }
6569
6570 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6571 {
6572 for(int i = 5; i >= 0; --i) {
6573 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6574 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6575 LLVMConstInt(ctx->ac.i32, 16, false), false);
6576 }
6577
6578 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6579 LLVMConstInt(ctx->ac.i32, 16, false),
6580 LLVMConstInt(ctx->ac.i32, 8, false), false);
6581 }
6582
6583 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6584 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6585 {
6586 struct ac_nir_context ctx = {};
6587 struct nir_function *func;
6588
6589 ctx.ac = *ac;
6590 ctx.abi = abi;
6591
6592 ctx.nctx = nctx;
6593 if (nctx)
6594 nctx->nir = &ctx;
6595
6596 ctx.stage = nir->info.stage;
6597
6598 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6599
6600 nir_foreach_variable(variable, &nir->outputs)
6601 handle_shader_output_decl(&ctx, nir, variable);
6602
6603 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6604 _mesa_key_pointer_equal);
6605 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6606 _mesa_key_pointer_equal);
6607 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6608 _mesa_key_pointer_equal);
6609
6610 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6611
6612 setup_locals(&ctx, func);
6613
6614 if (nir->info.stage == MESA_SHADER_COMPUTE)
6615 setup_shared(&ctx, nir);
6616
6617 visit_cf_list(&ctx, &func->impl->body);
6618 phi_post_pass(&ctx);
6619
6620 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6621 ctx.outputs);
6622
6623 free(ctx.locals);
6624 ralloc_free(ctx.defs);
6625 ralloc_free(ctx.phis);
6626 ralloc_free(ctx.vars);
6627
6628 if (nctx)
6629 nctx->nir = NULL;
6630 }
6631
6632 static
6633 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6634 struct nir_shader *const *shaders,
6635 int shader_count,
6636 struct ac_shader_variant_info *shader_info,
6637 const struct ac_nir_compiler_options *options)
6638 {
6639 struct nir_to_llvm_context ctx = {0};
6640 unsigned i;
6641 ctx.options = options;
6642 ctx.shader_info = shader_info;
6643 ctx.context = LLVMContextCreate();
6644 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6645
6646 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6647 options->family);
6648 ctx.ac.module = ctx.module;
6649 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6650
6651 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6652 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6653 LLVMSetDataLayout(ctx.module, data_layout_str);
6654 LLVMDisposeTargetData(data_layout);
6655 LLVMDisposeMessage(data_layout_str);
6656
6657 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6658 ctx.ac.builder = ctx.builder;
6659
6660 memset(shader_info, 0, sizeof(*shader_info));
6661
6662 for(int i = 0; i < shader_count; ++i)
6663 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6664
6665 for (i = 0; i < AC_UD_MAX_SETS; i++)
6666 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6667 for (i = 0; i < AC_UD_MAX_UD; i++)
6668 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6669
6670 ctx.max_workgroup_size = 0;
6671 for (int i = 0; i < shader_count; ++i) {
6672 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6673 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6674 shaders[i]));
6675 }
6676
6677 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6678 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6679
6680 ctx.abi.inputs = &ctx.inputs[0];
6681 ctx.abi.emit_outputs = handle_shader_outputs_post;
6682 ctx.abi.emit_vertex = visit_emit_vertex;
6683 ctx.abi.load_ubo = radv_load_ubo;
6684 ctx.abi.load_ssbo = radv_load_ssbo;
6685 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6686 ctx.abi.clamp_shadow_reference = false;
6687
6688 if (shader_count >= 2)
6689 ac_init_exec_full_mask(&ctx.ac);
6690
6691 if (ctx.ac.chip_class == GFX9 &&
6692 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6693 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6694
6695 for(int i = 0; i < shader_count; ++i) {
6696 ctx.stage = shaders[i]->info.stage;
6697 ctx.output_mask = 0;
6698 ctx.tess_outputs_written = 0;
6699 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6700 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6701
6702 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6703 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6704 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6705 ctx.abi.load_inputs = load_gs_input;
6706 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6707 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6708 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6709 ctx.abi.load_tess_inputs = load_tcs_input;
6710 ctx.abi.store_tcs_outputs = store_tcs_output;
6711 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6712 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6713 ctx.abi.load_tess_inputs = load_tes_input;
6714 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6715 if (shader_info->info.vs.needs_instance_id) {
6716 ctx.shader_info->vs.vgpr_comp_cnt =
6717 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6718 }
6719 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6720 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6721 }
6722
6723 if (i)
6724 emit_barrier(&ctx);
6725
6726 ac_setup_rings(&ctx);
6727
6728 LLVMBasicBlockRef merge_block;
6729 if (shader_count >= 2) {
6730 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6731 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6732 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6733
6734 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6735 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6736 LLVMConstInt(ctx.ac.i32, 8, false), false);
6737 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6738 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6739 thread_id, count, "");
6740 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6741
6742 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6743 }
6744
6745 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6746 handle_fs_inputs(&ctx, shaders[i]);
6747 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6748 handle_vs_inputs(&ctx, shaders[i]);
6749 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6750 prepare_gs_input_vgprs(&ctx);
6751
6752 nir_foreach_variable(variable, &shaders[i]->outputs)
6753 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6754
6755 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6756
6757 if (shader_count >= 2) {
6758 LLVMBuildBr(ctx.ac.builder, merge_block);
6759 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6760 }
6761
6762 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6763 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6764 shaders[i]->info.cull_distance_array_size > 4;
6765 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6766 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6767 shaders[i]->info.gs.vertices_out;
6768 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6769 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6770 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6771 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6772 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6773 }
6774 }
6775
6776 LLVMBuildRetVoid(ctx.builder);
6777
6778 ac_llvm_finalize_module(&ctx);
6779
6780 if (shader_count == 1)
6781 ac_nir_eliminate_const_vs_outputs(&ctx);
6782
6783 return ctx.module;
6784 }
6785
6786 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6787 {
6788 unsigned *retval = (unsigned *)context;
6789 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6790 char *description = LLVMGetDiagInfoDescription(di);
6791
6792 if (severity == LLVMDSError) {
6793 *retval = 1;
6794 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6795 description);
6796 }
6797
6798 LLVMDisposeMessage(description);
6799 }
6800
6801 static unsigned ac_llvm_compile(LLVMModuleRef M,
6802 struct ac_shader_binary *binary,
6803 LLVMTargetMachineRef tm)
6804 {
6805 unsigned retval = 0;
6806 char *err;
6807 LLVMContextRef llvm_ctx;
6808 LLVMMemoryBufferRef out_buffer;
6809 unsigned buffer_size;
6810 const char *buffer_data;
6811 LLVMBool mem_err;
6812
6813 /* Setup Diagnostic Handler*/
6814 llvm_ctx = LLVMGetModuleContext(M);
6815
6816 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6817 &retval);
6818
6819 /* Compile IR*/
6820 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6821 &err, &out_buffer);
6822
6823 /* Process Errors/Warnings */
6824 if (mem_err) {
6825 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6826 free(err);
6827 retval = 1;
6828 goto out;
6829 }
6830
6831 /* Extract Shader Code*/
6832 buffer_size = LLVMGetBufferSize(out_buffer);
6833 buffer_data = LLVMGetBufferStart(out_buffer);
6834
6835 ac_elf_read(buffer_data, buffer_size, binary);
6836
6837 /* Clean up */
6838 LLVMDisposeMemoryBuffer(out_buffer);
6839
6840 out:
6841 return retval;
6842 }
6843
6844 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6845 LLVMModuleRef llvm_module,
6846 struct ac_shader_binary *binary,
6847 struct ac_shader_config *config,
6848 struct ac_shader_variant_info *shader_info,
6849 gl_shader_stage stage,
6850 bool dump_shader, bool supports_spill)
6851 {
6852 if (dump_shader)
6853 ac_dump_module(llvm_module);
6854
6855 memset(binary, 0, sizeof(*binary));
6856 int v = ac_llvm_compile(llvm_module, binary, tm);
6857 if (v) {
6858 fprintf(stderr, "compile failed\n");
6859 }
6860
6861 if (dump_shader)
6862 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6863
6864 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6865
6866 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6867 LLVMDisposeModule(llvm_module);
6868 LLVMContextDispose(ctx);
6869
6870 if (stage == MESA_SHADER_FRAGMENT) {
6871 shader_info->num_input_vgprs = 0;
6872 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6873 shader_info->num_input_vgprs += 2;
6874 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6875 shader_info->num_input_vgprs += 2;
6876 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6877 shader_info->num_input_vgprs += 2;
6878 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6879 shader_info->num_input_vgprs += 3;
6880 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6881 shader_info->num_input_vgprs += 2;
6882 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6883 shader_info->num_input_vgprs += 2;
6884 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6885 shader_info->num_input_vgprs += 2;
6886 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6887 shader_info->num_input_vgprs += 1;
6888 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6889 shader_info->num_input_vgprs += 1;
6890 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6891 shader_info->num_input_vgprs += 1;
6892 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6893 shader_info->num_input_vgprs += 1;
6894 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6895 shader_info->num_input_vgprs += 1;
6896 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6897 shader_info->num_input_vgprs += 1;
6898 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6899 shader_info->num_input_vgprs += 1;
6900 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6901 shader_info->num_input_vgprs += 1;
6902 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6903 shader_info->num_input_vgprs += 1;
6904 }
6905 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6906
6907 /* +3 for scratch wave offset and VCC */
6908 config->num_sgprs = MAX2(config->num_sgprs,
6909 shader_info->num_input_sgprs + 3);
6910 }
6911
6912 static void
6913 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6914 {
6915 switch (nir->info.stage) {
6916 case MESA_SHADER_COMPUTE:
6917 for (int i = 0; i < 3; ++i)
6918 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6919 break;
6920 case MESA_SHADER_FRAGMENT:
6921 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6922 break;
6923 case MESA_SHADER_GEOMETRY:
6924 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6925 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6926 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6927 shader_info->gs.invocations = nir->info.gs.invocations;
6928 break;
6929 case MESA_SHADER_TESS_EVAL:
6930 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6931 shader_info->tes.spacing = nir->info.tess.spacing;
6932 shader_info->tes.ccw = nir->info.tess.ccw;
6933 shader_info->tes.point_mode = nir->info.tess.point_mode;
6934 shader_info->tes.as_es = options->key.tes.as_es;
6935 break;
6936 case MESA_SHADER_TESS_CTRL:
6937 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6938 break;
6939 case MESA_SHADER_VERTEX:
6940 shader_info->vs.as_es = options->key.vs.as_es;
6941 shader_info->vs.as_ls = options->key.vs.as_ls;
6942 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6943 if (options->key.vs.as_ls)
6944 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6945 break;
6946 default:
6947 break;
6948 }
6949 }
6950
6951 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6952 struct ac_shader_binary *binary,
6953 struct ac_shader_config *config,
6954 struct ac_shader_variant_info *shader_info,
6955 struct nir_shader *const *nir,
6956 int nir_count,
6957 const struct ac_nir_compiler_options *options,
6958 bool dump_shader)
6959 {
6960
6961 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6962 options);
6963
6964 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6965 for (int i = 0; i < nir_count; ++i)
6966 ac_fill_shader_info(shader_info, nir[i], options);
6967 }
6968
6969 static void
6970 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6971 {
6972 LLVMValueRef args[9];
6973 args[0] = ctx->gsvs_ring;
6974 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6975 args[3] = ctx->ac.i32_0;
6976 args[4] = ctx->ac.i32_1; /* OFFEN */
6977 args[5] = ctx->ac.i32_0; /* IDXEN */
6978 args[6] = ctx->ac.i32_1; /* GLC */
6979 args[7] = ctx->ac.i32_1; /* SLC */
6980 args[8] = ctx->ac.i32_0; /* TFE */
6981
6982 int idx = 0;
6983
6984 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6985 int length = 4;
6986 int slot = idx;
6987 int slot_inc = 1;
6988 if (!(ctx->output_mask & (1ull << i)))
6989 continue;
6990
6991 if (i == VARYING_SLOT_CLIP_DIST0) {
6992 /* unpack clip and cull from a single set of slots */
6993 length = ctx->num_output_clips + ctx->num_output_culls;
6994 if (length > 4)
6995 slot_inc = 2;
6996 }
6997
6998 for (unsigned j = 0; j < length; j++) {
6999 LLVMValueRef value;
7000 args[2] = LLVMConstInt(ctx->ac.i32,
7001 (slot * 4 + j) *
7002 ctx->gs_max_out_vertices * 16 * 4, false);
7003
7004 value = ac_build_intrinsic(&ctx->ac,
7005 "llvm.SI.buffer.load.dword.i32.i32",
7006 ctx->ac.i32, args, 9,
7007 AC_FUNC_ATTR_READONLY |
7008 AC_FUNC_ATTR_LEGACY);
7009
7010 LLVMBuildStore(ctx->builder,
7011 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7012 }
7013 idx += slot_inc;
7014 }
7015 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7016 }
7017
7018 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7019 struct nir_shader *geom_shader,
7020 struct ac_shader_binary *binary,
7021 struct ac_shader_config *config,
7022 struct ac_shader_variant_info *shader_info,
7023 const struct ac_nir_compiler_options *options,
7024 bool dump_shader)
7025 {
7026 struct nir_to_llvm_context ctx = {0};
7027 ctx.context = LLVMContextCreate();
7028 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7029 ctx.options = options;
7030 ctx.shader_info = shader_info;
7031
7032 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7033 options->family);
7034 ctx.ac.module = ctx.module;
7035
7036 ctx.is_gs_copy_shader = true;
7037 LLVMSetTarget(ctx.module, "amdgcn--");
7038
7039 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7040 ctx.ac.builder = ctx.builder;
7041 ctx.stage = MESA_SHADER_VERTEX;
7042
7043 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7044
7045 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7046 ac_setup_rings(&ctx);
7047
7048 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7049 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7050
7051 struct ac_nir_context nir_ctx = {};
7052 nir_ctx.ac = ctx.ac;
7053 nir_ctx.abi = &ctx.abi;
7054
7055 nir_ctx.nctx = &ctx;
7056 ctx.nir = &nir_ctx;
7057
7058 nir_foreach_variable(variable, &geom_shader->outputs) {
7059 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7060 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7061 }
7062
7063 ac_gs_copy_shader_emit(&ctx);
7064
7065 ctx.nir = NULL;
7066
7067 LLVMBuildRetVoid(ctx.builder);
7068
7069 ac_llvm_finalize_module(&ctx);
7070
7071 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7072 MESA_SHADER_VERTEX,
7073 dump_shader, options->supports_spill);
7074 }