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ac/nir: account for view index in the user sgpr allocation.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "no-signed-zeros-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
547 gl_shader_stage stage)
548 {
549 switch (stage) {
550 case MESA_SHADER_VERTEX:
551 if (ctx->shader_info->info.needs_multiview_view_index ||
552 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
553 return true;
554 break;
555 case MESA_SHADER_TESS_EVAL:
556 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
557 return true;
558 case MESA_SHADER_GEOMETRY:
559 case MESA_SHADER_TESS_CTRL:
560 if (ctx->shader_info->info.needs_multiview_view_index)
561 return true;
562 default:
563 break;
564 }
565 return false;
566 }
567
568 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
569 gl_shader_stage stage,
570 bool needs_view_index,
571 struct user_sgpr_info *user_sgpr_info)
572 {
573 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
574
575 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
576 if (stage == MESA_SHADER_GEOMETRY ||
577 stage == MESA_SHADER_VERTEX ||
578 stage == MESA_SHADER_TESS_CTRL ||
579 stage == MESA_SHADER_TESS_EVAL ||
580 ctx->is_gs_copy_shader)
581 user_sgpr_info->need_ring_offsets = true;
582
583 if (stage == MESA_SHADER_FRAGMENT &&
584 ctx->shader_info->info.ps.needs_sample_positions)
585 user_sgpr_info->need_ring_offsets = true;
586
587 /* 2 user sgprs will nearly always be allocated for scratch/rings */
588 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
589 user_sgpr_info->sgpr_count += 2;
590 }
591
592 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
593 switch (stage) {
594 case MESA_SHADER_COMPUTE:
595 if (ctx->shader_info->info.cs.uses_grid_size)
596 user_sgpr_info->sgpr_count += 3;
597 break;
598 case MESA_SHADER_FRAGMENT:
599 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
600 break;
601 case MESA_SHADER_VERTEX:
602 if (!ctx->is_gs_copy_shader) {
603 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
604 if (ctx->shader_info->info.vs.needs_draw_id) {
605 user_sgpr_info->sgpr_count += 3;
606 } else {
607 user_sgpr_info->sgpr_count += 2;
608 }
609 }
610 if (ctx->options->key.vs.as_ls)
611 user_sgpr_info->sgpr_count++;
612 break;
613 case MESA_SHADER_TESS_CTRL:
614 user_sgpr_info->sgpr_count += 4;
615 break;
616 case MESA_SHADER_TESS_EVAL:
617 user_sgpr_info->sgpr_count += 1;
618 break;
619 case MESA_SHADER_GEOMETRY:
620 user_sgpr_info->sgpr_count += 2;
621 break;
622 default:
623 break;
624 }
625
626 if (needs_view_index)
627 user_sgpr_info->sgpr_count++;
628
629 if (ctx->shader_info->info.loads_push_constants)
630 user_sgpr_info->sgpr_count += 2;
631
632 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
633 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
634
635 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
636 user_sgpr_info->sgpr_count += 2;
637 user_sgpr_info->indirect_all_descriptor_sets = true;
638 } else {
639 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
640 }
641 }
642
643 static void
644 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
645 gl_shader_stage stage,
646 bool has_previous_stage,
647 gl_shader_stage previous_stage,
648 const struct user_sgpr_info *user_sgpr_info,
649 struct arg_info *args,
650 LLVMValueRef *desc_sets)
651 {
652 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
653 unsigned num_sets = ctx->options->layout ?
654 ctx->options->layout->num_sets : 0;
655 unsigned stage_mask = 1 << stage;
656
657 if (has_previous_stage)
658 stage_mask |= 1 << previous_stage;
659
660 /* 1 for each descriptor set */
661 if (!user_sgpr_info->indirect_all_descriptor_sets) {
662 for (unsigned i = 0; i < num_sets; ++i) {
663 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
664 add_array_arg(args, type,
665 &ctx->descriptor_sets[i]);
666 }
667 }
668 } else {
669 add_array_arg(args, const_array(type, 32), desc_sets);
670 }
671
672 if (ctx->shader_info->info.loads_push_constants) {
673 /* 1 for push constants and dynamic descriptors */
674 add_array_arg(args, type, &ctx->push_constants);
675 }
676 }
677
678 static void
679 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
680 gl_shader_stage stage,
681 bool has_previous_stage,
682 gl_shader_stage previous_stage,
683 struct arg_info *args)
684 {
685 if (!ctx->is_gs_copy_shader &&
686 (stage == MESA_SHADER_VERTEX ||
687 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
688 if (ctx->shader_info->info.vs.has_vertex_buffers) {
689 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
690 &ctx->vertex_buffers);
691 }
692 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
693 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
694 if (ctx->shader_info->info.vs.needs_draw_id) {
695 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
696 }
697 }
698 }
699
700 static void
701 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
702 {
703 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
704 if (!ctx->is_gs_copy_shader) {
705 if (ctx->options->key.vs.as_ls) {
706 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
707 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
708 } else {
709 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
710 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
711 }
712 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
713 }
714 }
715
716 static void
717 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
718 {
719 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
720 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
721 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
722 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
723 }
724
725 static void
726 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
727 bool has_previous_stage, gl_shader_stage previous_stage,
728 const struct user_sgpr_info *user_sgpr_info,
729 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
730 {
731 unsigned num_sets = ctx->options->layout ?
732 ctx->options->layout->num_sets : 0;
733 unsigned stage_mask = 1 << stage;
734
735 if (has_previous_stage)
736 stage_mask |= 1 << previous_stage;
737
738 if (!user_sgpr_info->indirect_all_descriptor_sets) {
739 for (unsigned i = 0; i < num_sets; ++i) {
740 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
741 set_loc_desc(ctx, i, user_sgpr_idx, 0);
742 } else
743 ctx->descriptor_sets[i] = NULL;
744 }
745 } else {
746 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
747 user_sgpr_idx, 2);
748
749 for (unsigned i = 0; i < num_sets; ++i) {
750 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
751 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
752 ctx->descriptor_sets[i] =
753 ac_build_load_to_sgpr(&ctx->ac,
754 desc_sets,
755 LLVMConstInt(ctx->ac.i32, i, false));
756
757 } else
758 ctx->descriptor_sets[i] = NULL;
759 }
760 ctx->shader_info->need_indirect_descriptor_sets = true;
761 }
762
763 if (ctx->shader_info->info.loads_push_constants) {
764 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
765 }
766 }
767
768 static void
769 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
770 gl_shader_stage stage, bool has_previous_stage,
771 gl_shader_stage previous_stage,
772 uint8_t *user_sgpr_idx)
773 {
774 if (!ctx->is_gs_copy_shader &&
775 (stage == MESA_SHADER_VERTEX ||
776 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
777 if (ctx->shader_info->info.vs.has_vertex_buffers) {
778 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
779 user_sgpr_idx, 2);
780 }
781
782 unsigned vs_num = 2;
783 if (ctx->shader_info->info.vs.needs_draw_id)
784 vs_num++;
785
786 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
787 user_sgpr_idx, vs_num);
788 }
789 }
790
791 static void create_function(struct nir_to_llvm_context *ctx,
792 gl_shader_stage stage,
793 bool has_previous_stage,
794 gl_shader_stage previous_stage)
795 {
796 uint8_t user_sgpr_idx;
797 struct user_sgpr_info user_sgpr_info;
798 struct arg_info args = {};
799 LLVMValueRef desc_sets;
800 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
801 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
802
803 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
804 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
805 &ctx->ring_offsets);
806 }
807
808 switch (stage) {
809 case MESA_SHADER_COMPUTE:
810 declare_global_input_sgprs(ctx, stage, has_previous_stage,
811 previous_stage, &user_sgpr_info,
812 &args, &desc_sets);
813
814 if (ctx->shader_info->info.cs.uses_grid_size) {
815 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
816 &ctx->num_work_groups);
817 }
818
819 for (int i = 0; i < 3; i++) {
820 ctx->workgroup_ids[i] = NULL;
821 if (ctx->shader_info->info.cs.uses_block_id[i]) {
822 add_arg(&args, ARG_SGPR, ctx->ac.i32,
823 &ctx->workgroup_ids[i]);
824 }
825 }
826
827 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
829 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
830 &ctx->local_invocation_ids);
831 break;
832 case MESA_SHADER_VERTEX:
833 declare_global_input_sgprs(ctx, stage, has_previous_stage,
834 previous_stage, &user_sgpr_info,
835 &args, &desc_sets);
836 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
837 previous_stage, &args);
838
839 if (needs_view_index)
840 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
841 if (ctx->options->key.vs.as_es)
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->es2gs_offset);
844 else if (ctx->options->key.vs.as_ls)
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->ls_out_layout);
847
848 declare_vs_input_vgprs(ctx, &args);
849 break;
850 case MESA_SHADER_TESS_CTRL:
851 if (has_previous_stage) {
852 // First 6 system regs
853 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->merged_wave_info);
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->tess_factor_offset);
858
859 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
860 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
861 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
862
863 declare_global_input_sgprs(ctx, stage,
864 has_previous_stage,
865 previous_stage,
866 &user_sgpr_info, &args,
867 &desc_sets);
868 declare_vs_specific_input_sgprs(ctx, stage,
869 has_previous_stage,
870 previous_stage, &args);
871
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->ls_out_layout);
874
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_offchip_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_out_offsets);
879 add_arg(&args, ARG_SGPR, ctx->ac.i32,
880 &ctx->tcs_out_layout);
881 add_arg(&args, ARG_SGPR, ctx->ac.i32,
882 &ctx->tcs_in_layout);
883 if (needs_view_index)
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->view_index);
886
887 add_arg(&args, ARG_VGPR, ctx->ac.i32,
888 &ctx->abi.tcs_patch_id);
889 add_arg(&args, ARG_VGPR, ctx->ac.i32,
890 &ctx->abi.tcs_rel_ids);
891
892 declare_vs_input_vgprs(ctx, &args);
893 } else {
894 declare_global_input_sgprs(ctx, stage,
895 has_previous_stage,
896 previous_stage,
897 &user_sgpr_info, &args,
898 &desc_sets);
899
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->tcs_offchip_layout);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->tcs_out_offsets);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->tcs_out_layout);
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->tcs_in_layout);
908 if (needs_view_index)
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->view_index);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->tess_factor_offset);
915 add_arg(&args, ARG_VGPR, ctx->ac.i32,
916 &ctx->abi.tcs_patch_id);
917 add_arg(&args, ARG_VGPR, ctx->ac.i32,
918 &ctx->abi.tcs_rel_ids);
919 }
920 break;
921 case MESA_SHADER_TESS_EVAL:
922 declare_global_input_sgprs(ctx, stage, has_previous_stage,
923 previous_stage, &user_sgpr_info,
924 &args, &desc_sets);
925
926 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
927 if (needs_view_index)
928 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
929
930 if (ctx->options->key.tes.as_es) {
931 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
932 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->es2gs_offset);
935 } else {
936 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
938 }
939 declare_tes_input_vgprs(ctx, &args);
940 break;
941 case MESA_SHADER_GEOMETRY:
942 if (has_previous_stage) {
943 // First 6 system regs
944 add_arg(&args, ARG_SGPR, ctx->ac.i32,
945 &ctx->gs2vs_offset);
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->merged_wave_info);
948 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
949
950 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
951 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
952 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
953
954 declare_global_input_sgprs(ctx, stage,
955 has_previous_stage,
956 previous_stage,
957 &user_sgpr_info, &args,
958 &desc_sets);
959
960 if (previous_stage == MESA_SHADER_TESS_EVAL) {
961 add_arg(&args, ARG_SGPR, ctx->ac.i32,
962 &ctx->tcs_offchip_layout);
963 } else {
964 declare_vs_specific_input_sgprs(ctx, stage,
965 has_previous_stage,
966 previous_stage,
967 &args);
968 }
969
970 add_arg(&args, ARG_SGPR, ctx->ac.i32,
971 &ctx->gsvs_ring_stride);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_num_entries);
974 if (needs_view_index)
975 add_arg(&args, ARG_SGPR, ctx->ac.i32,
976 &ctx->view_index);
977
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[0]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->abi.gs_prim_id);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->abi.gs_invocation_id);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988
989 if (previous_stage == MESA_SHADER_VERTEX) {
990 declare_vs_input_vgprs(ctx, &args);
991 } else {
992 declare_tes_input_vgprs(ctx, &args);
993 }
994 } else {
995 declare_global_input_sgprs(ctx, stage,
996 has_previous_stage,
997 previous_stage,
998 &user_sgpr_info, &args,
999 &desc_sets);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1002 &ctx->gsvs_ring_stride);
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1004 &ctx->gsvs_num_entries);
1005 if (needs_view_index)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->view_index);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1011 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1012 &ctx->gs_vtx_offset[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1014 &ctx->gs_vtx_offset[1]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1016 &ctx->abi.gs_prim_id);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1018 &ctx->gs_vtx_offset[2]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1020 &ctx->gs_vtx_offset[3]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1022 &ctx->gs_vtx_offset[4]);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1024 &ctx->gs_vtx_offset[5]);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1026 &ctx->abi.gs_invocation_id);
1027 }
1028 break;
1029 case MESA_SHADER_FRAGMENT:
1030 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1031 previous_stage, &user_sgpr_info,
1032 &args, &desc_sets);
1033
1034 if (ctx->shader_info->info.ps.needs_sample_positions)
1035 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1036 &ctx->sample_pos_offset);
1037
1038 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1039 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1040 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1041 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1042 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1043 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1044 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1045 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1046 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1047 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1048 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1049 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1050 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1051 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1052 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1053 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1054 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1055 break;
1056 default:
1057 unreachable("Shader stage not implemented");
1058 }
1059
1060 ctx->main_function = create_llvm_function(
1061 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1062 ctx->max_workgroup_size,
1063 ctx->options->unsafe_math);
1064 set_llvm_calling_convention(ctx->main_function, stage);
1065
1066
1067 ctx->shader_info->num_input_vgprs = 0;
1068 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1069
1070 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1071
1072 if (ctx->stage != MESA_SHADER_FRAGMENT)
1073 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1074
1075 assign_arguments(ctx->main_function, &args);
1076
1077 user_sgpr_idx = 0;
1078
1079 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1080 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1081 &user_sgpr_idx, 2);
1082 if (ctx->options->supports_spill) {
1083 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1084 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1085 NULL, 0, AC_FUNC_ATTR_READNONE);
1086 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1087 const_array(ctx->ac.v4i32, 16), "");
1088 }
1089 }
1090
1091 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1092 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1093 if (has_previous_stage)
1094 user_sgpr_idx = 0;
1095
1096 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1097 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1098
1099 switch (stage) {
1100 case MESA_SHADER_COMPUTE:
1101 if (ctx->shader_info->info.cs.uses_grid_size) {
1102 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1103 &user_sgpr_idx, 3);
1104 }
1105 break;
1106 case MESA_SHADER_VERTEX:
1107 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1108 previous_stage, &user_sgpr_idx);
1109 if (ctx->view_index)
1110 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1111 if (ctx->options->key.vs.as_ls) {
1112 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1113 &user_sgpr_idx, 1);
1114 }
1115 if (ctx->options->key.vs.as_ls)
1116 ac_declare_lds_as_pointer(&ctx->ac);
1117 break;
1118 case MESA_SHADER_TESS_CTRL:
1119 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1120 previous_stage, &user_sgpr_idx);
1121 if (has_previous_stage)
1122 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1123 &user_sgpr_idx, 1);
1124 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1125 if (ctx->view_index)
1126 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1127 ac_declare_lds_as_pointer(&ctx->ac);
1128 break;
1129 case MESA_SHADER_TESS_EVAL:
1130 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1131 if (ctx->view_index)
1132 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1133 break;
1134 case MESA_SHADER_GEOMETRY:
1135 if (has_previous_stage) {
1136 if (previous_stage == MESA_SHADER_VERTEX)
1137 set_vs_specific_input_locs(ctx, stage,
1138 has_previous_stage,
1139 previous_stage,
1140 &user_sgpr_idx);
1141 else
1142 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1143 &user_sgpr_idx, 1);
1144 }
1145 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1146 &user_sgpr_idx, 2);
1147 if (ctx->view_index)
1148 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1149 if (has_previous_stage)
1150 ac_declare_lds_as_pointer(&ctx->ac);
1151 break;
1152 case MESA_SHADER_FRAGMENT:
1153 if (ctx->shader_info->info.ps.needs_sample_positions) {
1154 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1155 &user_sgpr_idx, 1);
1156 }
1157 break;
1158 default:
1159 unreachable("Shader stage not implemented");
1160 }
1161
1162 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1163 }
1164
1165 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1166 LLVMValueRef value, unsigned count)
1167 {
1168 unsigned num_components = ac_get_llvm_num_components(value);
1169 if (count == num_components)
1170 return value;
1171
1172 LLVMValueRef masks[] = {
1173 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1174 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1175
1176 if (count == 1)
1177 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1178 "");
1179
1180 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1181 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1182 }
1183
1184 static void
1185 build_store_values_extended(struct ac_llvm_context *ac,
1186 LLVMValueRef *values,
1187 unsigned value_count,
1188 unsigned value_stride,
1189 LLVMValueRef vec)
1190 {
1191 LLVMBuilderRef builder = ac->builder;
1192 unsigned i;
1193
1194 for (i = 0; i < value_count; i++) {
1195 LLVMValueRef ptr = values[i * value_stride];
1196 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1197 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1198 LLVMBuildStore(builder, value, ptr);
1199 }
1200 }
1201
1202 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1203 const nir_ssa_def *def)
1204 {
1205 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1206 if (def->num_components > 1) {
1207 type = LLVMVectorType(type, def->num_components);
1208 }
1209 return type;
1210 }
1211
1212 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1213 {
1214 assert(src.is_ssa);
1215 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1216 return (LLVMValueRef)entry->data;
1217 }
1218
1219
1220 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1221 const struct nir_block *b)
1222 {
1223 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1224 return (LLVMBasicBlockRef)entry->data;
1225 }
1226
1227 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1228 nir_alu_src src,
1229 unsigned num_components)
1230 {
1231 LLVMValueRef value = get_src(ctx, src.src);
1232 bool need_swizzle = false;
1233
1234 assert(value);
1235 LLVMTypeRef type = LLVMTypeOf(value);
1236 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1237 ? LLVMGetVectorSize(type)
1238 : 1;
1239
1240 for (unsigned i = 0; i < num_components; ++i) {
1241 assert(src.swizzle[i] < src_components);
1242 if (src.swizzle[i] != i)
1243 need_swizzle = true;
1244 }
1245
1246 if (need_swizzle || num_components != src_components) {
1247 LLVMValueRef masks[] = {
1248 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1249 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1250 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1251 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1252
1253 if (src_components > 1 && num_components == 1) {
1254 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1255 masks[0], "");
1256 } else if (src_components == 1 && num_components > 1) {
1257 LLVMValueRef values[] = {value, value, value, value};
1258 value = ac_build_gather_values(&ctx->ac, values, num_components);
1259 } else {
1260 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1261 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1262 swizzle, "");
1263 }
1264 }
1265 assert(!src.negate);
1266 assert(!src.abs);
1267 return value;
1268 }
1269
1270 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1271 LLVMIntPredicate pred, LLVMValueRef src0,
1272 LLVMValueRef src1)
1273 {
1274 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1275 return LLVMBuildSelect(ctx->builder, result,
1276 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1277 ctx->i32_0, "");
1278 }
1279
1280 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1281 LLVMRealPredicate pred, LLVMValueRef src0,
1282 LLVMValueRef src1)
1283 {
1284 LLVMValueRef result;
1285 src0 = ac_to_float(ctx, src0);
1286 src1 = ac_to_float(ctx, src1);
1287 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1288 return LLVMBuildSelect(ctx->builder, result,
1289 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1290 ctx->i32_0, "");
1291 }
1292
1293 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1294 const char *intrin,
1295 LLVMTypeRef result_type,
1296 LLVMValueRef src0)
1297 {
1298 char name[64];
1299 LLVMValueRef params[] = {
1300 ac_to_float(ctx, src0),
1301 };
1302
1303 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1304 get_elem_bits(ctx, result_type));
1305 assert(length < sizeof(name));
1306 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1307 }
1308
1309 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1310 const char *intrin,
1311 LLVMTypeRef result_type,
1312 LLVMValueRef src0, LLVMValueRef src1)
1313 {
1314 char name[64];
1315 LLVMValueRef params[] = {
1316 ac_to_float(ctx, src0),
1317 ac_to_float(ctx, src1),
1318 };
1319
1320 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1321 get_elem_bits(ctx, result_type));
1322 assert(length < sizeof(name));
1323 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1324 }
1325
1326 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1327 const char *intrin,
1328 LLVMTypeRef result_type,
1329 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1330 {
1331 char name[64];
1332 LLVMValueRef params[] = {
1333 ac_to_float(ctx, src0),
1334 ac_to_float(ctx, src1),
1335 ac_to_float(ctx, src2),
1336 };
1337
1338 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1339 get_elem_bits(ctx, result_type));
1340 assert(length < sizeof(name));
1341 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1342 }
1343
1344 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1346 {
1347 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1348 ctx->i32_0, "");
1349 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1350 }
1351
1352 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1353 LLVMIntPredicate pred,
1354 LLVMValueRef src0, LLVMValueRef src1)
1355 {
1356 return LLVMBuildSelect(ctx->builder,
1357 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1358 src0,
1359 src1, "");
1360
1361 }
1362 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0)
1364 {
1365 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1366 LLVMBuildNeg(ctx->builder, src0, ""));
1367 }
1368
1369 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0,
1371 unsigned bitsize)
1372 {
1373 LLVMValueRef cmp, val, zero, one;
1374 LLVMTypeRef type;
1375
1376 if (bitsize == 32) {
1377 type = ctx->f32;
1378 zero = ctx->f32_0;
1379 one = ctx->f32_1;
1380 } else {
1381 type = ctx->f64;
1382 zero = ctx->f64_0;
1383 one = ctx->f64_1;
1384 }
1385
1386 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1387 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1388 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1389 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1390 return val;
1391 }
1392
1393 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1394 LLVMValueRef src0, unsigned bitsize)
1395 {
1396 LLVMValueRef cmp, val, zero, one;
1397 LLVMTypeRef type;
1398
1399 if (bitsize == 32) {
1400 type = ctx->i32;
1401 zero = ctx->i32_0;
1402 one = ctx->i32_1;
1403 } else {
1404 type = ctx->i64;
1405 zero = ctx->i64_0;
1406 one = ctx->i64_1;
1407 }
1408
1409 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1410 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1411 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1412 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1413 return val;
1414 }
1415
1416 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1417 LLVMValueRef src0)
1418 {
1419 const char *intr = "llvm.floor.f32";
1420 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1421 LLVMValueRef params[] = {
1422 fsrc0,
1423 };
1424 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1425 ctx->f32, params, 1,
1426 AC_FUNC_ATTR_READNONE);
1427 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1428 }
1429
1430 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1431 const char *intrin,
1432 LLVMValueRef src0, LLVMValueRef src1)
1433 {
1434 LLVMTypeRef ret_type;
1435 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1436 LLVMValueRef res;
1437 LLVMValueRef params[] = { src0, src1 };
1438 ret_type = LLVMStructTypeInContext(ctx->context, types,
1439 2, true);
1440
1441 res = ac_build_intrinsic(ctx, intrin, ret_type,
1442 params, 2, AC_FUNC_ATTR_READNONE);
1443
1444 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1445 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1446 return res;
1447 }
1448
1449 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0)
1451 {
1452 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1453 }
1454
1455 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1456 LLVMValueRef src0)
1457 {
1458 src0 = ac_to_float(ctx, src0);
1459 return LLVMBuildSExt(ctx->builder,
1460 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1461 ctx->i32, "");
1462 }
1463
1464 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1465 LLVMValueRef src0,
1466 unsigned bitsize)
1467 {
1468 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1469
1470 if (bitsize == 32)
1471 return result;
1472
1473 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1474 }
1475
1476 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1477 LLVMValueRef src0)
1478 {
1479 return LLVMBuildSExt(ctx->builder,
1480 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1481 ctx->i32, "");
1482 }
1483
1484 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1485 LLVMValueRef src0)
1486 {
1487 LLVMValueRef result;
1488 LLVMValueRef cond = NULL;
1489
1490 src0 = ac_to_float(&ctx->ac, src0);
1491 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1492
1493 if (ctx->options->chip_class >= VI) {
1494 LLVMValueRef args[2];
1495 /* Check if the result is a denormal - and flush to 0 if so. */
1496 args[0] = result;
1497 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1498 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1499 }
1500
1501 /* need to convert back up to f32 */
1502 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1503
1504 if (ctx->options->chip_class >= VI)
1505 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1506 else {
1507 /* for SI/CIK */
1508 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1509 * so compare the result and flush to 0 if it's smaller.
1510 */
1511 LLVMValueRef temp, cond2;
1512 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1513 ctx->ac.f32, result);
1514 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1515 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1516 temp, "");
1517 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1518 temp, ctx->ac.f32_0, "");
1519 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1520 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1521 }
1522 return result;
1523 }
1524
1525 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1526 LLVMValueRef src0, LLVMValueRef src1)
1527 {
1528 LLVMValueRef dst64, result;
1529 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1530 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1531
1532 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1533 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1534 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0, LLVMValueRef src1)
1540 {
1541 LLVMValueRef dst64, result;
1542 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1543 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1544
1545 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1546 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1547 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1548 return result;
1549 }
1550
1551 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1552 bool is_signed,
1553 const LLVMValueRef srcs[3])
1554 {
1555 LLVMValueRef result;
1556 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1557
1558 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1559 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1560 return result;
1561 }
1562
1563 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0, LLVMValueRef src1,
1565 LLVMValueRef src2, LLVMValueRef src3)
1566 {
1567 LLVMValueRef bfi_args[3], result;
1568
1569 bfi_args[0] = LLVMBuildShl(ctx->builder,
1570 LLVMBuildSub(ctx->builder,
1571 LLVMBuildShl(ctx->builder,
1572 ctx->i32_1,
1573 src3, ""),
1574 ctx->i32_1, ""),
1575 src2, "");
1576 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1577 bfi_args[2] = src0;
1578
1579 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1580
1581 /* Calculate:
1582 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1583 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1584 */
1585 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1586 LLVMBuildAnd(ctx->builder, bfi_args[0],
1587 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1588
1589 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1590 return result;
1591 }
1592
1593 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1594 LLVMValueRef src0)
1595 {
1596 LLVMValueRef comp[2];
1597
1598 src0 = ac_to_float(ctx, src0);
1599 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1600 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1601
1602 return ac_build_cvt_pkrtz_f16(ctx, comp);
1603 }
1604
1605 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1606 LLVMValueRef src0)
1607 {
1608 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1609 LLVMValueRef temps[2], result, val;
1610 int i;
1611
1612 for (i = 0; i < 2; i++) {
1613 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1614 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1615 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1616 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1617 }
1618
1619 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1620 ctx->i32_0, "");
1621 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1622 ctx->i32_1, "");
1623 return result;
1624 }
1625
1626 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1627 nir_op op,
1628 LLVMValueRef src0)
1629 {
1630 unsigned mask;
1631 int idx;
1632 LLVMValueRef result;
1633
1634 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1635 mask = AC_TID_MASK_LEFT;
1636 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1637 mask = AC_TID_MASK_TOP;
1638 else
1639 mask = AC_TID_MASK_TOP_LEFT;
1640
1641 /* for DDX we want to next X pixel, DDY next Y pixel. */
1642 if (op == nir_op_fddx_fine ||
1643 op == nir_op_fddx_coarse ||
1644 op == nir_op_fddx)
1645 idx = 1;
1646 else
1647 idx = 2;
1648
1649 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1650 return result;
1651 }
1652
1653 /*
1654 * this takes an I,J coordinate pair,
1655 * and works out the X and Y derivatives.
1656 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1657 */
1658 static LLVMValueRef emit_ddxy_interp(
1659 struct ac_nir_context *ctx,
1660 LLVMValueRef interp_ij)
1661 {
1662 LLVMValueRef result[4], a;
1663 unsigned i;
1664
1665 for (i = 0; i < 2; i++) {
1666 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1667 LLVMConstInt(ctx->ac.i32, i, false), "");
1668 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1669 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1670 }
1671 return ac_build_gather_values(&ctx->ac, result, 4);
1672 }
1673
1674 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1675 {
1676 LLVMValueRef src[4], result = NULL;
1677 unsigned num_components = instr->dest.dest.ssa.num_components;
1678 unsigned src_components;
1679 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1680
1681 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1682 switch (instr->op) {
1683 case nir_op_vec2:
1684 case nir_op_vec3:
1685 case nir_op_vec4:
1686 src_components = 1;
1687 break;
1688 case nir_op_pack_half_2x16:
1689 src_components = 2;
1690 break;
1691 case nir_op_unpack_half_2x16:
1692 src_components = 1;
1693 break;
1694 default:
1695 src_components = num_components;
1696 break;
1697 }
1698 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1699 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1700
1701 switch (instr->op) {
1702 case nir_op_fmov:
1703 case nir_op_imov:
1704 result = src[0];
1705 break;
1706 case nir_op_fneg:
1707 src[0] = ac_to_float(&ctx->ac, src[0]);
1708 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1709 break;
1710 case nir_op_ineg:
1711 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1712 break;
1713 case nir_op_inot:
1714 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1715 break;
1716 case nir_op_iadd:
1717 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_fadd:
1720 src[0] = ac_to_float(&ctx->ac, src[0]);
1721 src[1] = ac_to_float(&ctx->ac, src[1]);
1722 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_fsub:
1725 src[0] = ac_to_float(&ctx->ac, src[0]);
1726 src[1] = ac_to_float(&ctx->ac, src[1]);
1727 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_isub:
1730 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_imul:
1733 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_imod:
1736 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1737 break;
1738 case nir_op_umod:
1739 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1740 break;
1741 case nir_op_fmod:
1742 src[0] = ac_to_float(&ctx->ac, src[0]);
1743 src[1] = ac_to_float(&ctx->ac, src[1]);
1744 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1745 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1746 ac_to_float_type(&ctx->ac, def_type), result);
1747 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1748 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1749 break;
1750 case nir_op_frem:
1751 src[0] = ac_to_float(&ctx->ac, src[0]);
1752 src[1] = ac_to_float(&ctx->ac, src[1]);
1753 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1754 break;
1755 case nir_op_irem:
1756 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1757 break;
1758 case nir_op_idiv:
1759 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_udiv:
1762 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1763 break;
1764 case nir_op_fmul:
1765 src[0] = ac_to_float(&ctx->ac, src[0]);
1766 src[1] = ac_to_float(&ctx->ac, src[1]);
1767 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1768 break;
1769 case nir_op_fdiv:
1770 src[0] = ac_to_float(&ctx->ac, src[0]);
1771 src[1] = ac_to_float(&ctx->ac, src[1]);
1772 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1773 break;
1774 case nir_op_frcp:
1775 src[0] = ac_to_float(&ctx->ac, src[0]);
1776 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1777 src[0]);
1778 break;
1779 case nir_op_iand:
1780 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1781 break;
1782 case nir_op_ior:
1783 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1784 break;
1785 case nir_op_ixor:
1786 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1787 break;
1788 case nir_op_ishl:
1789 result = LLVMBuildShl(ctx->ac.builder, src[0],
1790 LLVMBuildZExt(ctx->ac.builder, src[1],
1791 LLVMTypeOf(src[0]), ""),
1792 "");
1793 break;
1794 case nir_op_ishr:
1795 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1796 LLVMBuildZExt(ctx->ac.builder, src[1],
1797 LLVMTypeOf(src[0]), ""),
1798 "");
1799 break;
1800 case nir_op_ushr:
1801 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1802 LLVMBuildZExt(ctx->ac.builder, src[1],
1803 LLVMTypeOf(src[0]), ""),
1804 "");
1805 break;
1806 case nir_op_ilt:
1807 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1808 break;
1809 case nir_op_ine:
1810 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1811 break;
1812 case nir_op_ieq:
1813 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1814 break;
1815 case nir_op_ige:
1816 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1817 break;
1818 case nir_op_ult:
1819 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1820 break;
1821 case nir_op_uge:
1822 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1823 break;
1824 case nir_op_feq:
1825 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1826 break;
1827 case nir_op_fne:
1828 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1829 break;
1830 case nir_op_flt:
1831 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1832 break;
1833 case nir_op_fge:
1834 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1835 break;
1836 case nir_op_fabs:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_iabs:
1841 result = emit_iabs(&ctx->ac, src[0]);
1842 break;
1843 case nir_op_imax:
1844 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1845 break;
1846 case nir_op_imin:
1847 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1848 break;
1849 case nir_op_umax:
1850 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1851 break;
1852 case nir_op_umin:
1853 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1854 break;
1855 case nir_op_isign:
1856 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1857 break;
1858 case nir_op_fsign:
1859 src[0] = ac_to_float(&ctx->ac, src[0]);
1860 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1861 break;
1862 case nir_op_ffloor:
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1864 ac_to_float_type(&ctx->ac, def_type), src[0]);
1865 break;
1866 case nir_op_ftrunc:
1867 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1868 ac_to_float_type(&ctx->ac, def_type), src[0]);
1869 break;
1870 case nir_op_fceil:
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1872 ac_to_float_type(&ctx->ac, def_type), src[0]);
1873 break;
1874 case nir_op_fround_even:
1875 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1876 ac_to_float_type(&ctx->ac, def_type),src[0]);
1877 break;
1878 case nir_op_ffract:
1879 result = emit_ffract(&ctx->ac, src[0]);
1880 break;
1881 case nir_op_fsin:
1882 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1883 ac_to_float_type(&ctx->ac, def_type), src[0]);
1884 break;
1885 case nir_op_fcos:
1886 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1887 ac_to_float_type(&ctx->ac, def_type), src[0]);
1888 break;
1889 case nir_op_fsqrt:
1890 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1891 ac_to_float_type(&ctx->ac, def_type), src[0]);
1892 break;
1893 case nir_op_fexp2:
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1895 ac_to_float_type(&ctx->ac, def_type), src[0]);
1896 break;
1897 case nir_op_flog2:
1898 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1899 ac_to_float_type(&ctx->ac, def_type), src[0]);
1900 break;
1901 case nir_op_frsq:
1902 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1903 ac_to_float_type(&ctx->ac, def_type), src[0]);
1904 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1905 result);
1906 break;
1907 case nir_op_fpow:
1908 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1909 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1910 break;
1911 case nir_op_fmax:
1912 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1913 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1914 if (instr->dest.dest.ssa.bit_size == 32)
1915 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1916 ac_to_float_type(&ctx->ac, def_type),
1917 result);
1918 break;
1919 case nir_op_fmin:
1920 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1921 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1922 if (instr->dest.dest.ssa.bit_size == 32)
1923 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1924 ac_to_float_type(&ctx->ac, def_type),
1925 result);
1926 break;
1927 case nir_op_ffma:
1928 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1929 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1930 break;
1931 case nir_op_ibitfield_extract:
1932 result = emit_bitfield_extract(&ctx->ac, true, src);
1933 break;
1934 case nir_op_ubitfield_extract:
1935 result = emit_bitfield_extract(&ctx->ac, false, src);
1936 break;
1937 case nir_op_bitfield_insert:
1938 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1939 break;
1940 case nir_op_bitfield_reverse:
1941 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1942 break;
1943 case nir_op_bit_count:
1944 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1945 break;
1946 case nir_op_vec2:
1947 case nir_op_vec3:
1948 case nir_op_vec4:
1949 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1950 src[i] = ac_to_integer(&ctx->ac, src[i]);
1951 result = ac_build_gather_values(&ctx->ac, src, num_components);
1952 break;
1953 case nir_op_f2i32:
1954 case nir_op_f2i64:
1955 src[0] = ac_to_float(&ctx->ac, src[0]);
1956 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1957 break;
1958 case nir_op_f2u32:
1959 case nir_op_f2u64:
1960 src[0] = ac_to_float(&ctx->ac, src[0]);
1961 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1962 break;
1963 case nir_op_i2f32:
1964 case nir_op_i2f64:
1965 src[0] = ac_to_integer(&ctx->ac, src[0]);
1966 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1967 break;
1968 case nir_op_u2f32:
1969 case nir_op_u2f64:
1970 src[0] = ac_to_integer(&ctx->ac, src[0]);
1971 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1972 break;
1973 case nir_op_f2f64:
1974 src[0] = ac_to_float(&ctx->ac, src[0]);
1975 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1976 break;
1977 case nir_op_f2f32:
1978 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1979 break;
1980 case nir_op_u2u32:
1981 case nir_op_u2u64:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1984 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1985 else
1986 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1987 break;
1988 case nir_op_i2i32:
1989 case nir_op_i2i64:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1992 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1993 else
1994 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1995 break;
1996 case nir_op_bcsel:
1997 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1998 break;
1999 case nir_op_find_lsb:
2000 src[0] = ac_to_integer(&ctx->ac, src[0]);
2001 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
2002 break;
2003 case nir_op_ufind_msb:
2004 src[0] = ac_to_integer(&ctx->ac, src[0]);
2005 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
2006 break;
2007 case nir_op_ifind_msb:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2010 break;
2011 case nir_op_uadd_carry:
2012 src[0] = ac_to_integer(&ctx->ac, src[0]);
2013 src[1] = ac_to_integer(&ctx->ac, src[1]);
2014 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2015 break;
2016 case nir_op_usub_borrow:
2017 src[0] = ac_to_integer(&ctx->ac, src[0]);
2018 src[1] = ac_to_integer(&ctx->ac, src[1]);
2019 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2020 break;
2021 case nir_op_b2f:
2022 result = emit_b2f(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_f2b:
2025 result = emit_f2b(&ctx->ac, src[0]);
2026 break;
2027 case nir_op_b2i:
2028 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2029 break;
2030 case nir_op_i2b:
2031 src[0] = ac_to_integer(&ctx->ac, src[0]);
2032 result = emit_i2b(&ctx->ac, src[0]);
2033 break;
2034 case nir_op_fquantize2f16:
2035 result = emit_f2f16(ctx->nctx, src[0]);
2036 break;
2037 case nir_op_umul_high:
2038 src[0] = ac_to_integer(&ctx->ac, src[0]);
2039 src[1] = ac_to_integer(&ctx->ac, src[1]);
2040 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2041 break;
2042 case nir_op_imul_high:
2043 src[0] = ac_to_integer(&ctx->ac, src[0]);
2044 src[1] = ac_to_integer(&ctx->ac, src[1]);
2045 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2046 break;
2047 case nir_op_pack_half_2x16:
2048 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2049 break;
2050 case nir_op_unpack_half_2x16:
2051 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2052 break;
2053 case nir_op_fddx:
2054 case nir_op_fddy:
2055 case nir_op_fddx_fine:
2056 case nir_op_fddy_fine:
2057 case nir_op_fddx_coarse:
2058 case nir_op_fddy_coarse:
2059 result = emit_ddxy(ctx, instr->op, src[0]);
2060 break;
2061
2062 case nir_op_unpack_64_2x32_split_x: {
2063 assert(instr->src[0].src.ssa->num_components == 1);
2064 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2065 ctx->ac.v2i32,
2066 "");
2067 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2068 ctx->ac.i32_0, "");
2069 break;
2070 }
2071
2072 case nir_op_unpack_64_2x32_split_y: {
2073 assert(instr->src[0].src.ssa->num_components == 1);
2074 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2075 ctx->ac.v2i32,
2076 "");
2077 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2078 ctx->ac.i32_1, "");
2079 break;
2080 }
2081
2082 case nir_op_pack_64_2x32_split: {
2083 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2084 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2085 src[0], ctx->ac.i32_0, "");
2086 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2087 src[1], ctx->ac.i32_1, "");
2088 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2089 break;
2090 }
2091
2092 default:
2093 fprintf(stderr, "Unknown NIR alu instr: ");
2094 nir_print_instr(&instr->instr, stderr);
2095 fprintf(stderr, "\n");
2096 abort();
2097 }
2098
2099 if (result) {
2100 assert(instr->dest.dest.is_ssa);
2101 result = ac_to_integer(&ctx->ac, result);
2102 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2103 result);
2104 }
2105 }
2106
2107 static void visit_load_const(struct ac_nir_context *ctx,
2108 const nir_load_const_instr *instr)
2109 {
2110 LLVMValueRef values[4], value = NULL;
2111 LLVMTypeRef element_type =
2112 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2113
2114 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2115 switch (instr->def.bit_size) {
2116 case 32:
2117 values[i] = LLVMConstInt(element_type,
2118 instr->value.u32[i], false);
2119 break;
2120 case 64:
2121 values[i] = LLVMConstInt(element_type,
2122 instr->value.u64[i], false);
2123 break;
2124 default:
2125 fprintf(stderr,
2126 "unsupported nir load_const bit_size: %d\n",
2127 instr->def.bit_size);
2128 abort();
2129 }
2130 }
2131 if (instr->def.num_components > 1) {
2132 value = LLVMConstVector(values, instr->def.num_components);
2133 } else
2134 value = values[0];
2135
2136 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2137 }
2138
2139 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2140 LLVMTypeRef type)
2141 {
2142 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2143 return LLVMBuildBitCast(ctx->builder, ptr,
2144 LLVMPointerType(type, addr_space), "");
2145 }
2146
2147 static LLVMValueRef
2148 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2149 {
2150 LLVMValueRef size =
2151 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2152 LLVMConstInt(ctx->ac.i32, 2, false), "");
2153
2154 /* VI only */
2155 if (ctx->ac.chip_class == VI && in_elements) {
2156 /* On VI, the descriptor contains the size in bytes,
2157 * but TXQ must return the size in elements.
2158 * The stride is always non-zero for resources using TXQ.
2159 */
2160 LLVMValueRef stride =
2161 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2162 ctx->ac.i32_1, "");
2163 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2164 LLVMConstInt(ctx->ac.i32, 16, false), "");
2165 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2166 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2167
2168 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2169 }
2170 return size;
2171 }
2172
2173 /**
2174 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2175 * intrinsic names).
2176 */
2177 static void build_int_type_name(
2178 LLVMTypeRef type,
2179 char *buf, unsigned bufsize)
2180 {
2181 assert(bufsize >= 6);
2182
2183 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2184 snprintf(buf, bufsize, "v%ui32",
2185 LLVMGetVectorSize(type));
2186 else
2187 strcpy(buf, "i32");
2188 }
2189
2190 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2191 struct ac_image_args *args,
2192 const nir_tex_instr *instr)
2193 {
2194 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2195 LLVMValueRef coord = args->addr;
2196 LLVMValueRef half_texel[2];
2197 LLVMValueRef compare_cube_wa = NULL;
2198 LLVMValueRef result;
2199 int c;
2200 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2201
2202 //TODO Rect
2203 {
2204 struct ac_image_args txq_args = { 0 };
2205
2206 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2207 txq_args.opcode = ac_image_get_resinfo;
2208 txq_args.dmask = 0xf;
2209 txq_args.addr = ctx->i32_0;
2210 txq_args.resource = args->resource;
2211 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2212
2213 for (c = 0; c < 2; c++) {
2214 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2215 LLVMConstInt(ctx->i32, c, false), "");
2216 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2217 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2218 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2219 LLVMConstReal(ctx->f32, -0.5), "");
2220 }
2221 }
2222
2223 LLVMValueRef orig_coords = args->addr;
2224
2225 for (c = 0; c < 2; c++) {
2226 LLVMValueRef tmp;
2227 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2228 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2229 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2230 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2231 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2232 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2233 }
2234
2235
2236 /*
2237 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2238 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2239 * workaround by sampling using a scaled type and converting.
2240 * This is taken from amdgpu-pro shaders.
2241 */
2242 /* NOTE this produces some ugly code compared to amdgpu-pro,
2243 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2244 * and then reads them back. -pro generates two selects,
2245 * one s_cmp for the descriptor rewriting
2246 * one v_cmp for the coordinate and result changes.
2247 */
2248 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2249 LLVMValueRef tmp, tmp2;
2250
2251 /* workaround 8/8/8/8 uint/sint cube gather bug */
2252 /* first detect it then change to a scaled read and f2i */
2253 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2254 tmp2 = tmp;
2255
2256 /* extract the DATA_FORMAT */
2257 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2258 LLVMConstInt(ctx->i32, 6, false), false);
2259
2260 /* is the DATA_FORMAT == 8_8_8_8 */
2261 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2262
2263 if (stype == GLSL_TYPE_UINT)
2264 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2265 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2266 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2267 else
2268 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2269 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2270 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2271
2272 /* replace the NUM FORMAT in the descriptor */
2273 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2274 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2275
2276 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2277
2278 /* don't modify the coordinates for this case */
2279 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2280 }
2281 args->addr = coord;
2282 result = ac_build_image_opcode(ctx, args);
2283
2284 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2285 LLVMValueRef tmp, tmp2;
2286
2287 /* if the cube workaround is in place, f2i the result. */
2288 for (c = 0; c < 4; c++) {
2289 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2290 if (stype == GLSL_TYPE_UINT)
2291 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2292 else
2293 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2294 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2295 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2296 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2297 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2298 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2299 }
2300 }
2301 return result;
2302 }
2303
2304 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2305 const nir_tex_instr *instr,
2306 bool lod_is_zero,
2307 struct ac_image_args *args)
2308 {
2309 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2310 return ac_build_buffer_load_format(&ctx->ac,
2311 args->resource,
2312 args->addr,
2313 ctx->ac.i32_0,
2314 true);
2315 }
2316
2317 args->opcode = ac_image_sample;
2318 args->compare = instr->is_shadow;
2319
2320 switch (instr->op) {
2321 case nir_texop_txf:
2322 case nir_texop_txf_ms:
2323 case nir_texop_samples_identical:
2324 args->opcode = lod_is_zero ||
2325 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2326 ac_image_load : ac_image_load_mip;
2327 args->compare = false;
2328 args->offset = false;
2329 break;
2330 case nir_texop_txb:
2331 args->bias = true;
2332 break;
2333 case nir_texop_txl:
2334 if (lod_is_zero)
2335 args->level_zero = true;
2336 else
2337 args->lod = true;
2338 break;
2339 case nir_texop_txs:
2340 case nir_texop_query_levels:
2341 args->opcode = ac_image_get_resinfo;
2342 break;
2343 case nir_texop_tex:
2344 if (ctx->stage != MESA_SHADER_FRAGMENT)
2345 args->level_zero = true;
2346 break;
2347 case nir_texop_txd:
2348 args->deriv = true;
2349 break;
2350 case nir_texop_tg4:
2351 args->opcode = ac_image_gather4;
2352 args->level_zero = true;
2353 break;
2354 case nir_texop_lod:
2355 args->opcode = ac_image_get_lod;
2356 args->compare = false;
2357 args->offset = false;
2358 break;
2359 default:
2360 break;
2361 }
2362
2363 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2364 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2365 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2366 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2367 }
2368 }
2369 return ac_build_image_opcode(&ctx->ac, args);
2370 }
2371
2372 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2373 nir_intrinsic_instr *instr)
2374 {
2375 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2376 unsigned desc_set = nir_intrinsic_desc_set(instr);
2377 unsigned binding = nir_intrinsic_binding(instr);
2378 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2379 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2380 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2381 unsigned base_offset = layout->binding[binding].offset;
2382 LLVMValueRef offset, stride;
2383
2384 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2385 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2386 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2387 layout->binding[binding].dynamic_offset_offset;
2388 desc_ptr = ctx->push_constants;
2389 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2390 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2391 } else
2392 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2393
2394 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2395 index = LLVMBuildMul(ctx->builder, index, stride, "");
2396 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2397
2398 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2399 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2400 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2401
2402 return desc_ptr;
2403 }
2404
2405 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2406 nir_intrinsic_instr *instr)
2407 {
2408 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2409 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2410
2411 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2412 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2413 return result;
2414 }
2415
2416 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2417 nir_intrinsic_instr *instr)
2418 {
2419 LLVMValueRef ptr, addr;
2420
2421 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2422 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2423
2424 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2425 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2426
2427 return LLVMBuildLoad(ctx->builder, ptr, "");
2428 }
2429
2430 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2431 const nir_intrinsic_instr *instr)
2432 {
2433 LLVMValueRef index = get_src(ctx, instr->src[0]);
2434
2435 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2436 }
2437 static void visit_store_ssbo(struct ac_nir_context *ctx,
2438 nir_intrinsic_instr *instr)
2439 {
2440 const char *store_name;
2441 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2442 LLVMTypeRef data_type = ctx->ac.f32;
2443 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2444 int components_32bit = elem_size_mult * instr->num_components;
2445 unsigned writemask = nir_intrinsic_write_mask(instr);
2446 LLVMValueRef base_data, base_offset;
2447 LLVMValueRef params[6];
2448
2449 params[1] = ctx->abi->load_ssbo(ctx->abi,
2450 get_src(ctx, instr->src[1]), true);
2451 params[2] = ctx->ac.i32_0; /* vindex */
2452 params[4] = ctx->ac.i1false; /* glc */
2453 params[5] = ctx->ac.i1false; /* slc */
2454
2455 if (components_32bit > 1)
2456 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2457
2458 base_data = ac_to_float(&ctx->ac, src_data);
2459 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2460 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2461 data_type, "");
2462 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2463 while (writemask) {
2464 int start, count;
2465 LLVMValueRef data;
2466 LLVMValueRef offset;
2467 LLVMValueRef tmp;
2468 u_bit_scan_consecutive_range(&writemask, &start, &count);
2469
2470 /* Due to an LLVM limitation, split 3-element writes
2471 * into a 2-element and a 1-element write. */
2472 if (count == 3) {
2473 writemask |= 1 << (start + 2);
2474 count = 2;
2475 }
2476
2477 start *= elem_size_mult;
2478 count *= elem_size_mult;
2479
2480 if (count > 4) {
2481 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2482 count = 4;
2483 }
2484
2485 if (count == 4) {
2486 store_name = "llvm.amdgcn.buffer.store.v4f32";
2487 data = base_data;
2488 } else if (count == 2) {
2489 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2490 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2491 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2492 ctx->ac.i32_0, "");
2493
2494 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2495 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2496 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2497 ctx->ac.i32_1, "");
2498 store_name = "llvm.amdgcn.buffer.store.v2f32";
2499
2500 } else {
2501 assert(count == 1);
2502 if (ac_get_llvm_num_components(base_data) > 1)
2503 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2504 LLVMConstInt(ctx->ac.i32, start, false), "");
2505 else
2506 data = base_data;
2507 store_name = "llvm.amdgcn.buffer.store.f32";
2508 }
2509
2510 offset = base_offset;
2511 if (start != 0) {
2512 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2513 }
2514 params[0] = data;
2515 params[3] = offset;
2516 ac_build_intrinsic(&ctx->ac, store_name,
2517 ctx->ac.voidt, params, 6, 0);
2518 }
2519 }
2520
2521 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2522 const nir_intrinsic_instr *instr)
2523 {
2524 const char *name;
2525 LLVMValueRef params[6];
2526 int arg_count = 0;
2527
2528 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2529 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2530 }
2531 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2532 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2533 get_src(ctx, instr->src[0]),
2534 true);
2535 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2536 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2537 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2538
2539 switch (instr->intrinsic) {
2540 case nir_intrinsic_ssbo_atomic_add:
2541 name = "llvm.amdgcn.buffer.atomic.add";
2542 break;
2543 case nir_intrinsic_ssbo_atomic_imin:
2544 name = "llvm.amdgcn.buffer.atomic.smin";
2545 break;
2546 case nir_intrinsic_ssbo_atomic_umin:
2547 name = "llvm.amdgcn.buffer.atomic.umin";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_imax:
2550 name = "llvm.amdgcn.buffer.atomic.smax";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_umax:
2553 name = "llvm.amdgcn.buffer.atomic.umax";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_and:
2556 name = "llvm.amdgcn.buffer.atomic.and";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_or:
2559 name = "llvm.amdgcn.buffer.atomic.or";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_xor:
2562 name = "llvm.amdgcn.buffer.atomic.xor";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_exchange:
2565 name = "llvm.amdgcn.buffer.atomic.swap";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_comp_swap:
2568 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2569 break;
2570 default:
2571 abort();
2572 }
2573
2574 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2575 }
2576
2577 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2578 const nir_intrinsic_instr *instr)
2579 {
2580 LLVMValueRef results[2];
2581 int load_components;
2582 int num_components = instr->num_components;
2583 if (instr->dest.ssa.bit_size == 64)
2584 num_components *= 2;
2585
2586 for (int i = 0; i < num_components; i += load_components) {
2587 load_components = MIN2(num_components - i, 4);
2588 const char *load_name;
2589 LLVMTypeRef data_type = ctx->ac.f32;
2590 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2591 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2592
2593 if (load_components == 3)
2594 data_type = LLVMVectorType(ctx->ac.f32, 4);
2595 else if (load_components > 1)
2596 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2597
2598 if (load_components >= 3)
2599 load_name = "llvm.amdgcn.buffer.load.v4f32";
2600 else if (load_components == 2)
2601 load_name = "llvm.amdgcn.buffer.load.v2f32";
2602 else if (load_components == 1)
2603 load_name = "llvm.amdgcn.buffer.load.f32";
2604 else
2605 unreachable("unhandled number of components");
2606
2607 LLVMValueRef params[] = {
2608 ctx->abi->load_ssbo(ctx->abi,
2609 get_src(ctx, instr->src[0]),
2610 false),
2611 ctx->ac.i32_0,
2612 offset,
2613 ctx->ac.i1false,
2614 ctx->ac.i1false,
2615 };
2616
2617 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2618 }
2619
2620 assume(results[0]);
2621 LLVMValueRef ret = results[0];
2622 if (num_components > 4 || num_components == 3) {
2623 LLVMValueRef masks[] = {
2624 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2625 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2626 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2627 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2628 };
2629
2630 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2631 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2632 results[num_components > 4 ? 1 : 0], swizzle, "");
2633 }
2634
2635 return LLVMBuildBitCast(ctx->ac.builder, ret,
2636 get_def_type(ctx, &instr->dest.ssa), "");
2637 }
2638
2639 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2640 const nir_intrinsic_instr *instr)
2641 {
2642 LLVMValueRef ret;
2643 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2644 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2645 int num_components = instr->num_components;
2646
2647 if (ctx->abi->load_ubo)
2648 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2649
2650 if (instr->dest.ssa.bit_size == 64)
2651 num_components *= 2;
2652
2653 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2654 NULL, 0, false, false, true, true);
2655 ret = trim_vector(&ctx->ac, ret, num_components);
2656 return LLVMBuildBitCast(ctx->ac.builder, ret,
2657 get_def_type(ctx, &instr->dest.ssa), "");
2658 }
2659
2660 static void
2661 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2662 bool vs_in, unsigned *vertex_index_out,
2663 LLVMValueRef *vertex_index_ref,
2664 unsigned *const_out, LLVMValueRef *indir_out)
2665 {
2666 unsigned const_offset = 0;
2667 nir_deref *tail = &deref->deref;
2668 LLVMValueRef offset = NULL;
2669
2670 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2671 tail = tail->child;
2672 nir_deref_array *deref_array = nir_deref_as_array(tail);
2673 if (vertex_index_out)
2674 *vertex_index_out = deref_array->base_offset;
2675
2676 if (vertex_index_ref) {
2677 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2678 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2679 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2680 }
2681 *vertex_index_ref = vtx;
2682 }
2683 }
2684
2685 if (deref->var->data.compact) {
2686 assert(tail->child->deref_type == nir_deref_type_array);
2687 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2688 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2689 /* We always lower indirect dereferences for "compact" array vars. */
2690 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2691
2692 const_offset = deref_array->base_offset;
2693 goto out;
2694 }
2695
2696 while (tail->child != NULL) {
2697 const struct glsl_type *parent_type = tail->type;
2698 tail = tail->child;
2699
2700 if (tail->deref_type == nir_deref_type_array) {
2701 nir_deref_array *deref_array = nir_deref_as_array(tail);
2702 LLVMValueRef index, stride, local_offset;
2703 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2704
2705 const_offset += size * deref_array->base_offset;
2706 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2707 continue;
2708
2709 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2710 index = get_src(ctx, deref_array->indirect);
2711 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2712 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2713
2714 if (offset)
2715 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2716 else
2717 offset = local_offset;
2718 } else if (tail->deref_type == nir_deref_type_struct) {
2719 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2720
2721 for (unsigned i = 0; i < deref_struct->index; i++) {
2722 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2723 const_offset += glsl_count_attribute_slots(ft, vs_in);
2724 }
2725 } else
2726 unreachable("unsupported deref type");
2727
2728 }
2729 out:
2730 if (const_offset && offset)
2731 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2732 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2733 "");
2734
2735 *const_out = const_offset;
2736 *indir_out = offset;
2737 }
2738
2739
2740 /* The offchip buffer layout for TCS->TES is
2741 *
2742 * - attribute 0 of patch 0 vertex 0
2743 * - attribute 0 of patch 0 vertex 1
2744 * - attribute 0 of patch 0 vertex 2
2745 * ...
2746 * - attribute 0 of patch 1 vertex 0
2747 * - attribute 0 of patch 1 vertex 1
2748 * ...
2749 * - attribute 1 of patch 0 vertex 0
2750 * - attribute 1 of patch 0 vertex 1
2751 * ...
2752 * - per patch attribute 0 of patch 0
2753 * - per patch attribute 0 of patch 1
2754 * ...
2755 *
2756 * Note that every attribute has 4 components.
2757 */
2758 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2759 LLVMValueRef vertex_index,
2760 LLVMValueRef param_index)
2761 {
2762 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2763 LLVMValueRef param_stride, constant16;
2764 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2765
2766 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2767 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2768 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2769 num_patches, "");
2770
2771 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2772 if (vertex_index) {
2773 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2774 vertices_per_patch, "");
2775
2776 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2777 vertex_index, "");
2778
2779 param_stride = total_vertices;
2780 } else {
2781 base_addr = rel_patch_id;
2782 param_stride = num_patches;
2783 }
2784
2785 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2786 LLVMBuildMul(ctx->builder, param_index,
2787 param_stride, ""), "");
2788
2789 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2790
2791 if (!vertex_index) {
2792 LLVMValueRef patch_data_offset =
2793 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2794
2795 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2796 patch_data_offset, "");
2797 }
2798 return base_addr;
2799 }
2800
2801 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2802 unsigned param,
2803 unsigned const_index,
2804 bool is_compact,
2805 LLVMValueRef vertex_index,
2806 LLVMValueRef indir_index)
2807 {
2808 LLVMValueRef param_index;
2809
2810 if (indir_index)
2811 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2812 indir_index, "");
2813 else {
2814 if (const_index && !is_compact)
2815 param += const_index;
2816 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2817 }
2818 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2819 }
2820
2821 static void
2822 mark_tess_output(struct nir_to_llvm_context *ctx,
2823 bool is_patch, uint32_t param)
2824
2825 {
2826 if (is_patch) {
2827 ctx->tess_patch_outputs_written |= (1ull << param);
2828 } else
2829 ctx->tess_outputs_written |= (1ull << param);
2830 }
2831
2832 static LLVMValueRef
2833 get_dw_address(struct nir_to_llvm_context *ctx,
2834 LLVMValueRef dw_addr,
2835 unsigned param,
2836 unsigned const_index,
2837 bool compact_const_index,
2838 LLVMValueRef vertex_index,
2839 LLVMValueRef stride,
2840 LLVMValueRef indir_index)
2841
2842 {
2843
2844 if (vertex_index) {
2845 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2846 LLVMBuildMul(ctx->builder,
2847 vertex_index,
2848 stride, ""), "");
2849 }
2850
2851 if (indir_index)
2852 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2853 LLVMBuildMul(ctx->builder, indir_index,
2854 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2855 else if (const_index && !compact_const_index)
2856 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2857 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2858
2859 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2860 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2861
2862 if (const_index && compact_const_index)
2863 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2864 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2865 return dw_addr;
2866 }
2867
2868 static LLVMValueRef
2869 load_tcs_varyings(struct ac_shader_abi *abi,
2870 LLVMValueRef vertex_index,
2871 LLVMValueRef indir_index,
2872 unsigned const_index,
2873 unsigned location,
2874 unsigned driver_location,
2875 unsigned component,
2876 unsigned num_components,
2877 bool is_patch,
2878 bool is_compact,
2879 bool load_input)
2880 {
2881 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2882 LLVMValueRef dw_addr, stride;
2883 LLVMValueRef value[4], result;
2884 unsigned param = shader_io_get_unique_index(location);
2885
2886 if (load_input) {
2887 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2888 dw_addr = get_tcs_in_current_patch_offset(ctx);
2889 } else {
2890 if (!is_patch) {
2891 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2892 dw_addr = get_tcs_out_current_patch_offset(ctx);
2893 } else {
2894 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2895 stride = NULL;
2896 }
2897 }
2898
2899 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2900 indir_index);
2901
2902 for (unsigned i = 0; i < num_components + component; i++) {
2903 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2904 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2905 ctx->ac.i32_1, "");
2906 }
2907 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2908 return result;
2909 }
2910
2911 static void
2912 store_tcs_output(struct ac_shader_abi *abi,
2913 LLVMValueRef vertex_index,
2914 LLVMValueRef param_index,
2915 unsigned const_index,
2916 unsigned location,
2917 unsigned driver_location,
2918 LLVMValueRef src,
2919 unsigned component,
2920 bool is_patch,
2921 bool is_compact,
2922 unsigned writemask)
2923 {
2924 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2925 LLVMValueRef dw_addr;
2926 LLVMValueRef stride = NULL;
2927 LLVMValueRef buf_addr = NULL;
2928 unsigned param;
2929 bool store_lds = true;
2930
2931 if (is_patch) {
2932 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2933 store_lds = false;
2934 } else {
2935 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2936 store_lds = false;
2937 }
2938
2939 param = shader_io_get_unique_index(location);
2940 if (location == VARYING_SLOT_CLIP_DIST0 &&
2941 is_compact && const_index > 3) {
2942 const_index -= 3;
2943 param++;
2944 }
2945
2946 if (!is_patch) {
2947 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2948 dw_addr = get_tcs_out_current_patch_offset(ctx);
2949 } else {
2950 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2951 }
2952
2953 mark_tess_output(ctx, is_patch, param);
2954
2955 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2956 param_index);
2957 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2958 vertex_index, param_index);
2959
2960 bool is_tess_factor = false;
2961 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2962 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2963 is_tess_factor = true;
2964
2965 unsigned base = is_compact ? const_index : 0;
2966 for (unsigned chan = 0; chan < 8; chan++) {
2967 if (!(writemask & (1 << chan)))
2968 continue;
2969 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2970
2971 if (store_lds || is_tess_factor)
2972 ac_lds_store(&ctx->ac, dw_addr, value);
2973
2974 if (!is_tess_factor && writemask != 0xF)
2975 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2976 buf_addr, ctx->oc_lds,
2977 4 * (base + chan), 1, 0, true, false);
2978
2979 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2980 ctx->ac.i32_1, "");
2981 }
2982
2983 if (writemask == 0xF) {
2984 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2985 buf_addr, ctx->oc_lds,
2986 (base * 4), 1, 0, true, false);
2987 }
2988 }
2989
2990 static LLVMValueRef
2991 load_tes_input(struct ac_shader_abi *abi,
2992 LLVMValueRef vertex_index,
2993 LLVMValueRef param_index,
2994 unsigned const_index,
2995 unsigned location,
2996 unsigned driver_location,
2997 unsigned component,
2998 unsigned num_components,
2999 bool is_patch,
3000 bool is_compact,
3001 bool load_input)
3002 {
3003 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3004 LLVMValueRef buf_addr;
3005 LLVMValueRef result;
3006 unsigned param = shader_io_get_unique_index(location);
3007
3008 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3009 const_index -= 3;
3010 param++;
3011 }
3012
3013 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3014 is_compact, vertex_index, param_index);
3015
3016 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3017 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3018
3019 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3020 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3021 result = trim_vector(&ctx->ac, result, num_components);
3022 return result;
3023 }
3024
3025 static LLVMValueRef
3026 load_gs_input(struct ac_shader_abi *abi,
3027 unsigned location,
3028 unsigned driver_location,
3029 unsigned component,
3030 unsigned num_components,
3031 unsigned vertex_index,
3032 unsigned const_index,
3033 LLVMTypeRef type)
3034 {
3035 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3036 LLVMValueRef vtx_offset;
3037 LLVMValueRef args[9];
3038 unsigned param, vtx_offset_param;
3039 LLVMValueRef value[4], result;
3040
3041 vtx_offset_param = vertex_index;
3042 assert(vtx_offset_param < 6);
3043 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3044 LLVMConstInt(ctx->ac.i32, 4, false), "");
3045
3046 param = shader_io_get_unique_index(location);
3047
3048 for (unsigned i = component; i < num_components + component; i++) {
3049 if (ctx->ac.chip_class >= GFX9) {
3050 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3051 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3052 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3053 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3054 } else {
3055 args[0] = ctx->esgs_ring;
3056 args[1] = vtx_offset;
3057 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3058 args[3] = ctx->ac.i32_0;
3059 args[4] = ctx->ac.i32_1; /* OFFEN */
3060 args[5] = ctx->ac.i32_0; /* IDXEN */
3061 args[6] = ctx->ac.i32_1; /* GLC */
3062 args[7] = ctx->ac.i32_0; /* SLC */
3063 args[8] = ctx->ac.i32_0; /* TFE */
3064
3065 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3066 ctx->ac.i32, args, 9,
3067 AC_FUNC_ATTR_READONLY |
3068 AC_FUNC_ATTR_LEGACY);
3069 }
3070 }
3071 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3072
3073 return result;
3074 }
3075
3076 static LLVMValueRef
3077 build_gep_for_deref(struct ac_nir_context *ctx,
3078 nir_deref_var *deref)
3079 {
3080 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3081 assert(entry->data);
3082 LLVMValueRef val = entry->data;
3083 nir_deref *tail = deref->deref.child;
3084 while (tail != NULL) {
3085 LLVMValueRef offset;
3086 switch (tail->deref_type) {
3087 case nir_deref_type_array: {
3088 nir_deref_array *array = nir_deref_as_array(tail);
3089 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3090 if (array->deref_array_type ==
3091 nir_deref_array_type_indirect) {
3092 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3093 get_src(ctx,
3094 array->indirect),
3095 "");
3096 }
3097 break;
3098 }
3099 case nir_deref_type_struct: {
3100 nir_deref_struct *deref_struct =
3101 nir_deref_as_struct(tail);
3102 offset = LLVMConstInt(ctx->ac.i32,
3103 deref_struct->index, 0);
3104 break;
3105 }
3106 default:
3107 unreachable("bad deref type");
3108 }
3109 val = ac_build_gep0(&ctx->ac, val, offset);
3110 tail = tail->child;
3111 }
3112 return val;
3113 }
3114
3115 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3116 nir_intrinsic_instr *instr,
3117 bool load_inputs)
3118 {
3119 LLVMValueRef result;
3120 LLVMValueRef vertex_index = NULL;
3121 LLVMValueRef indir_index = NULL;
3122 unsigned const_index = 0;
3123 unsigned location = instr->variables[0]->var->data.location;
3124 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3125 const bool is_patch = instr->variables[0]->var->data.patch;
3126 const bool is_compact = instr->variables[0]->var->data.compact;
3127
3128 get_deref_offset(ctx, instr->variables[0],
3129 false, NULL, is_patch ? NULL : &vertex_index,
3130 &const_index, &indir_index);
3131
3132 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3133 const_index, location, driver_location,
3134 instr->variables[0]->var->data.location_frac,
3135 instr->num_components,
3136 is_patch, is_compact, load_inputs);
3137 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3138 }
3139
3140 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3141 nir_intrinsic_instr *instr)
3142 {
3143 LLVMValueRef values[8];
3144 int idx = instr->variables[0]->var->data.driver_location;
3145 int ve = instr->dest.ssa.num_components;
3146 unsigned comp = instr->variables[0]->var->data.location_frac;
3147 LLVMValueRef indir_index;
3148 LLVMValueRef ret;
3149 unsigned const_index;
3150 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3151 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3152 instr->variables[0]->var->data.mode == nir_var_shader_in;
3153 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3154 &const_index, &indir_index);
3155
3156 if (instr->dest.ssa.bit_size == 64)
3157 ve *= 2;
3158
3159 switch (instr->variables[0]->var->data.mode) {
3160 case nir_var_shader_in:
3161 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3162 ctx->stage == MESA_SHADER_TESS_EVAL) {
3163 return load_tess_varyings(ctx, instr, true);
3164 }
3165
3166 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3167 LLVMValueRef indir_index;
3168 unsigned const_index, vertex_index;
3169 get_deref_offset(ctx, instr->variables[0],
3170 false, &vertex_index, NULL,
3171 &const_index, &indir_index);
3172 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3173 instr->variables[0]->var->data.driver_location,
3174 instr->variables[0]->var->data.location_frac, ve,
3175 vertex_index, const_index,
3176 nir2llvmtype(ctx, instr->variables[0]->var->type));
3177 }
3178
3179 for (unsigned chan = comp; chan < ve + comp; chan++) {
3180 if (indir_index) {
3181 unsigned count = glsl_count_attribute_slots(
3182 instr->variables[0]->var->type,
3183 ctx->stage == MESA_SHADER_VERTEX);
3184 count -= chan / 4;
3185 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3186 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3187 stride, false, true);
3188
3189 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3190 tmp_vec,
3191 indir_index, "");
3192 } else
3193 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3194 }
3195 break;
3196 case nir_var_local:
3197 for (unsigned chan = 0; chan < ve; chan++) {
3198 if (indir_index) {
3199 unsigned count = glsl_count_attribute_slots(
3200 instr->variables[0]->var->type, false);
3201 count -= chan / 4;
3202 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3203 &ctx->ac, ctx->locals + idx + chan, count,
3204 stride, true, true);
3205
3206 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3207 tmp_vec,
3208 indir_index, "");
3209 } else {
3210 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3211 }
3212 }
3213 break;
3214 case nir_var_shared: {
3215 LLVMValueRef address = build_gep_for_deref(ctx,
3216 instr->variables[0]);
3217 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3218 return LLVMBuildBitCast(ctx->ac.builder, val,
3219 get_def_type(ctx, &instr->dest.ssa),
3220 "");
3221 }
3222 case nir_var_shader_out:
3223 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3224 return load_tess_varyings(ctx, instr, false);
3225 }
3226
3227 for (unsigned chan = comp; chan < ve + comp; chan++) {
3228 if (indir_index) {
3229 unsigned count = glsl_count_attribute_slots(
3230 instr->variables[0]->var->type, false);
3231 count -= chan / 4;
3232 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3233 &ctx->ac, ctx->outputs + idx + chan, count,
3234 stride, true, true);
3235
3236 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3237 tmp_vec,
3238 indir_index, "");
3239 } else {
3240 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3241 ctx->outputs[idx + chan + const_index * stride],
3242 "");
3243 }
3244 }
3245 break;
3246 default:
3247 unreachable("unhandle variable mode");
3248 }
3249 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3250 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3251 }
3252
3253 static void
3254 visit_store_var(struct ac_nir_context *ctx,
3255 nir_intrinsic_instr *instr)
3256 {
3257 LLVMValueRef temp_ptr, value;
3258 int idx = instr->variables[0]->var->data.driver_location;
3259 unsigned comp = instr->variables[0]->var->data.location_frac;
3260 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3261 int writemask = instr->const_index[0] << comp;
3262 LLVMValueRef indir_index;
3263 unsigned const_index;
3264 get_deref_offset(ctx, instr->variables[0], false,
3265 NULL, NULL, &const_index, &indir_index);
3266
3267 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3268 int old_writemask = writemask;
3269
3270 src = LLVMBuildBitCast(ctx->ac.builder, src,
3271 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3272 "");
3273
3274 writemask = 0;
3275 for (unsigned chan = 0; chan < 4; chan++) {
3276 if (old_writemask & (1 << chan))
3277 writemask |= 3u << (2 * chan);
3278 }
3279 }
3280
3281 switch (instr->variables[0]->var->data.mode) {
3282 case nir_var_shader_out:
3283
3284 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3285 LLVMValueRef vertex_index = NULL;
3286 LLVMValueRef indir_index = NULL;
3287 unsigned const_index = 0;
3288 const unsigned location = instr->variables[0]->var->data.location;
3289 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3290 const unsigned comp = instr->variables[0]->var->data.location_frac;
3291 const bool is_patch = instr->variables[0]->var->data.patch;
3292 const bool is_compact = instr->variables[0]->var->data.compact;
3293
3294 get_deref_offset(ctx, instr->variables[0],
3295 false, NULL, is_patch ? NULL : &vertex_index,
3296 &const_index, &indir_index);
3297
3298 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3299 const_index, location, driver_location,
3300 src, comp, is_patch, is_compact, writemask);
3301 return;
3302 }
3303
3304 for (unsigned chan = 0; chan < 8; chan++) {
3305 int stride = 4;
3306 if (!(writemask & (1 << chan)))
3307 continue;
3308
3309 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3310
3311 if (instr->variables[0]->var->data.compact)
3312 stride = 1;
3313 if (indir_index) {
3314 unsigned count = glsl_count_attribute_slots(
3315 instr->variables[0]->var->type, false);
3316 count -= chan / 4;
3317 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3318 &ctx->ac, ctx->outputs + idx + chan, count,
3319 stride, true, true);
3320
3321 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3322 value, indir_index, "");
3323 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3324 count, stride, tmp_vec);
3325
3326 } else {
3327 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3328
3329 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3330 }
3331 }
3332 break;
3333 case nir_var_local:
3334 for (unsigned chan = 0; chan < 8; chan++) {
3335 if (!(writemask & (1 << chan)))
3336 continue;
3337
3338 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3339 if (indir_index) {
3340 unsigned count = glsl_count_attribute_slots(
3341 instr->variables[0]->var->type, false);
3342 count -= chan / 4;
3343 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3344 &ctx->ac, ctx->locals + idx + chan, count,
3345 4, true, true);
3346
3347 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3348 value, indir_index, "");
3349 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3350 count, 4, tmp_vec);
3351 } else {
3352 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3353
3354 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3355 }
3356 }
3357 break;
3358 case nir_var_shared: {
3359 int writemask = instr->const_index[0];
3360 LLVMValueRef address = build_gep_for_deref(ctx,
3361 instr->variables[0]);
3362 LLVMValueRef val = get_src(ctx, instr->src[0]);
3363 unsigned components =
3364 glsl_get_vector_elements(
3365 nir_deref_tail(&instr->variables[0]->deref)->type);
3366 if (writemask == (1 << components) - 1) {
3367 val = LLVMBuildBitCast(
3368 ctx->ac.builder, val,
3369 LLVMGetElementType(LLVMTypeOf(address)), "");
3370 LLVMBuildStore(ctx->ac.builder, val, address);
3371 } else {
3372 for (unsigned chan = 0; chan < 4; chan++) {
3373 if (!(writemask & (1 << chan)))
3374 continue;
3375 LLVMValueRef ptr =
3376 LLVMBuildStructGEP(ctx->ac.builder,
3377 address, chan, "");
3378 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3379 chan);
3380 src = LLVMBuildBitCast(
3381 ctx->ac.builder, src,
3382 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3383 LLVMBuildStore(ctx->ac.builder, src, ptr);
3384 }
3385 }
3386 break;
3387 }
3388 default:
3389 break;
3390 }
3391 }
3392
3393 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3394 {
3395 switch (dim) {
3396 case GLSL_SAMPLER_DIM_BUF:
3397 return 1;
3398 case GLSL_SAMPLER_DIM_1D:
3399 return array ? 2 : 1;
3400 case GLSL_SAMPLER_DIM_2D:
3401 return array ? 3 : 2;
3402 case GLSL_SAMPLER_DIM_MS:
3403 return array ? 4 : 3;
3404 case GLSL_SAMPLER_DIM_3D:
3405 case GLSL_SAMPLER_DIM_CUBE:
3406 return 3;
3407 case GLSL_SAMPLER_DIM_RECT:
3408 case GLSL_SAMPLER_DIM_SUBPASS:
3409 return 2;
3410 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3411 return 3;
3412 default:
3413 break;
3414 }
3415 return 0;
3416 }
3417
3418
3419
3420 /* Adjust the sample index according to FMASK.
3421 *
3422 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3423 * which is the identity mapping. Each nibble says which physical sample
3424 * should be fetched to get that sample.
3425 *
3426 * For example, 0x11111100 means there are only 2 samples stored and
3427 * the second sample covers 3/4 of the pixel. When reading samples 0
3428 * and 1, return physical sample 0 (determined by the first two 0s
3429 * in FMASK), otherwise return physical sample 1.
3430 *
3431 * The sample index should be adjusted as follows:
3432 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3433 */
3434 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3435 LLVMValueRef coord_x, LLVMValueRef coord_y,
3436 LLVMValueRef coord_z,
3437 LLVMValueRef sample_index,
3438 LLVMValueRef fmask_desc_ptr)
3439 {
3440 LLVMValueRef fmask_load_address[4];
3441 LLVMValueRef res;
3442
3443 fmask_load_address[0] = coord_x;
3444 fmask_load_address[1] = coord_y;
3445 if (coord_z) {
3446 fmask_load_address[2] = coord_z;
3447 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3448 }
3449
3450 struct ac_image_args args = {0};
3451
3452 args.opcode = ac_image_load;
3453 args.da = coord_z ? true : false;
3454 args.resource = fmask_desc_ptr;
3455 args.dmask = 0xf;
3456 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3457
3458 res = ac_build_image_opcode(ctx, &args);
3459
3460 res = ac_to_integer(ctx, res);
3461 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3462 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3463
3464 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3465 res,
3466 ctx->i32_0, "");
3467
3468 LLVMValueRef sample_index4 =
3469 LLVMBuildMul(ctx->builder, sample_index, four, "");
3470 LLVMValueRef shifted_fmask =
3471 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3472 LLVMValueRef final_sample =
3473 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3474
3475 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3476 * resource descriptor is 0 (invalid),
3477 */
3478 LLVMValueRef fmask_desc =
3479 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3480 ctx->v8i32, "");
3481
3482 LLVMValueRef fmask_word1 =
3483 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3484 ctx->i32_1, "");
3485
3486 LLVMValueRef word1_is_nonzero =
3487 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3488 fmask_word1, ctx->i32_0, "");
3489
3490 /* Replace the MSAA sample index. */
3491 sample_index =
3492 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3493 final_sample, sample_index, "");
3494 return sample_index;
3495 }
3496
3497 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3498 const nir_intrinsic_instr *instr)
3499 {
3500 const struct glsl_type *type = instr->variables[0]->var->type;
3501 if(instr->variables[0]->deref.child)
3502 type = instr->variables[0]->deref.child->type;
3503
3504 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3505 LLVMValueRef coords[4];
3506 LLVMValueRef masks[] = {
3507 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3508 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3509 };
3510 LLVMValueRef res;
3511 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3512
3513 int count;
3514 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3515 bool is_array = glsl_sampler_type_is_array(type);
3516 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3517 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3518 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3519 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3520 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3521 count = image_type_to_components_count(dim, is_array);
3522
3523 if (is_ms) {
3524 LLVMValueRef fmask_load_address[3];
3525 int chan;
3526
3527 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3528 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3529 if (is_array)
3530 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3531 else
3532 fmask_load_address[2] = NULL;
3533 if (add_frag_pos) {
3534 for (chan = 0; chan < 2; ++chan)
3535 fmask_load_address[chan] =
3536 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3537 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3538 ctx->ac.i32, ""), "");
3539 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3540 }
3541 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3542 fmask_load_address[0],
3543 fmask_load_address[1],
3544 fmask_load_address[2],
3545 sample_index,
3546 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3547 }
3548 if (count == 1 && !gfx9_1d) {
3549 if (instr->src[0].ssa->num_components)
3550 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3551 else
3552 res = src0;
3553 } else {
3554 int chan;
3555 if (is_ms)
3556 count--;
3557 for (chan = 0; chan < count; ++chan) {
3558 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3559 }
3560 if (add_frag_pos) {
3561 for (chan = 0; chan < 2; ++chan)
3562 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3563 ctx->ac.i32, ""), "");
3564 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3565 count++;
3566 }
3567
3568 if (gfx9_1d) {
3569 if (is_array) {
3570 coords[2] = coords[1];
3571 coords[1] = ctx->ac.i32_0;
3572 } else
3573 coords[1] = ctx->ac.i32_0;
3574 count++;
3575 }
3576
3577 if (is_ms) {
3578 coords[count] = sample_index;
3579 count++;
3580 }
3581
3582 if (count == 3) {
3583 coords[3] = LLVMGetUndef(ctx->ac.i32);
3584 count = 4;
3585 }
3586 res = ac_build_gather_values(&ctx->ac, coords, count);
3587 }
3588 return res;
3589 }
3590
3591 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3592 const nir_intrinsic_instr *instr)
3593 {
3594 LLVMValueRef params[7];
3595 LLVMValueRef res;
3596 char intrinsic_name[64];
3597 const nir_variable *var = instr->variables[0]->var;
3598 const struct glsl_type *type = var->type;
3599
3600 if(instr->variables[0]->deref.child)
3601 type = instr->variables[0]->deref.child->type;
3602
3603 type = glsl_without_array(type);
3604 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3605 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3606 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3607 ctx->ac.i32_0, ""); /* vindex */
3608 params[2] = ctx->ac.i32_0; /* voffset */
3609 params[3] = ctx->ac.i1false; /* glc */
3610 params[4] = ctx->ac.i1false; /* slc */
3611 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3612 params, 5, 0);
3613
3614 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3615 res = ac_to_integer(&ctx->ac, res);
3616 } else {
3617 bool is_da = glsl_sampler_type_is_array(type) ||
3618 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3619 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3620 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3621 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3622 LLVMValueRef glc = ctx->ac.i1false;
3623 LLVMValueRef slc = ctx->ac.i1false;
3624
3625 params[0] = get_image_coords(ctx, instr);
3626 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3627 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3628 if (HAVE_LLVM <= 0x0309) {
3629 params[3] = ctx->ac.i1false; /* r128 */
3630 params[4] = da;
3631 params[5] = glc;
3632 params[6] = slc;
3633 } else {
3634 LLVMValueRef lwe = ctx->ac.i1false;
3635 params[3] = glc;
3636 params[4] = slc;
3637 params[5] = lwe;
3638 params[6] = da;
3639 }
3640
3641 ac_get_image_intr_name("llvm.amdgcn.image.load",
3642 ctx->ac.v4f32, /* vdata */
3643 LLVMTypeOf(params[0]), /* coords */
3644 LLVMTypeOf(params[1]), /* rsrc */
3645 intrinsic_name, sizeof(intrinsic_name));
3646
3647 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3648 params, 7, AC_FUNC_ATTR_READONLY);
3649 }
3650 return ac_to_integer(&ctx->ac, res);
3651 }
3652
3653 static void visit_image_store(struct ac_nir_context *ctx,
3654 nir_intrinsic_instr *instr)
3655 {
3656 LLVMValueRef params[8];
3657 char intrinsic_name[64];
3658 const nir_variable *var = instr->variables[0]->var;
3659 const struct glsl_type *type = glsl_without_array(var->type);
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 bool force_glc = ctx->ac.chip_class == SI;
3662 if (force_glc)
3663 glc = ctx->ac.i1true;
3664
3665 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3666 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3667 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3668 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3669 ctx->ac.i32_0, ""); /* vindex */
3670 params[3] = ctx->ac.i32_0; /* voffset */
3671 params[4] = glc; /* glc */
3672 params[5] = ctx->ac.i1false; /* slc */
3673 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3674 params, 6, 0);
3675 } else {
3676 bool is_da = glsl_sampler_type_is_array(type) ||
3677 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3678 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3679 LLVMValueRef slc = ctx->ac.i1false;
3680
3681 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3682 params[1] = get_image_coords(ctx, instr); /* coords */
3683 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3684 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3685 if (HAVE_LLVM <= 0x0309) {
3686 params[4] = ctx->ac.i1false; /* r128 */
3687 params[5] = da;
3688 params[6] = glc;
3689 params[7] = slc;
3690 } else {
3691 LLVMValueRef lwe = ctx->ac.i1false;
3692 params[4] = glc;
3693 params[5] = slc;
3694 params[6] = lwe;
3695 params[7] = da;
3696 }
3697
3698 ac_get_image_intr_name("llvm.amdgcn.image.store",
3699 LLVMTypeOf(params[0]), /* vdata */
3700 LLVMTypeOf(params[1]), /* coords */
3701 LLVMTypeOf(params[2]), /* rsrc */
3702 intrinsic_name, sizeof(intrinsic_name));
3703
3704 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3705 params, 8, 0);
3706 }
3707
3708 }
3709
3710 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3711 const nir_intrinsic_instr *instr)
3712 {
3713 LLVMValueRef params[7];
3714 int param_count = 0;
3715 const nir_variable *var = instr->variables[0]->var;
3716
3717 const char *atomic_name;
3718 char intrinsic_name[41];
3719 const struct glsl_type *type = glsl_without_array(var->type);
3720 MAYBE_UNUSED int length;
3721
3722 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3723
3724 switch (instr->intrinsic) {
3725 case nir_intrinsic_image_atomic_add:
3726 atomic_name = "add";
3727 break;
3728 case nir_intrinsic_image_atomic_min:
3729 atomic_name = is_unsigned ? "umin" : "smin";
3730 break;
3731 case nir_intrinsic_image_atomic_max:
3732 atomic_name = is_unsigned ? "umax" : "smax";
3733 break;
3734 case nir_intrinsic_image_atomic_and:
3735 atomic_name = "and";
3736 break;
3737 case nir_intrinsic_image_atomic_or:
3738 atomic_name = "or";
3739 break;
3740 case nir_intrinsic_image_atomic_xor:
3741 atomic_name = "xor";
3742 break;
3743 case nir_intrinsic_image_atomic_exchange:
3744 atomic_name = "swap";
3745 break;
3746 case nir_intrinsic_image_atomic_comp_swap:
3747 atomic_name = "cmpswap";
3748 break;
3749 default:
3750 abort();
3751 }
3752
3753 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3754 params[param_count++] = get_src(ctx, instr->src[3]);
3755 params[param_count++] = get_src(ctx, instr->src[2]);
3756
3757 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3758 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3759 NULL, true, true);
3760 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3761 ctx->ac.i32_0, ""); /* vindex */
3762 params[param_count++] = ctx->ac.i32_0; /* voffset */
3763 params[param_count++] = ctx->ac.i1false; /* slc */
3764
3765 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3766 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3767 } else {
3768 char coords_type[8];
3769
3770 bool da = glsl_sampler_type_is_array(type) ||
3771 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3772
3773 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3774 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3775 NULL, true, true);
3776 params[param_count++] = ctx->ac.i1false; /* r128 */
3777 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3778 params[param_count++] = ctx->ac.i1false; /* slc */
3779
3780 build_int_type_name(LLVMTypeOf(coords),
3781 coords_type, sizeof(coords_type));
3782
3783 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3784 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3785 }
3786
3787 assert(length < sizeof(intrinsic_name));
3788 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3789 }
3790
3791 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3792 const nir_intrinsic_instr *instr)
3793 {
3794 LLVMValueRef res;
3795 const nir_variable *var = instr->variables[0]->var;
3796 const struct glsl_type *type = instr->variables[0]->var->type;
3797 bool da = glsl_sampler_type_is_array(var->type) ||
3798 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3799 if(instr->variables[0]->deref.child)
3800 type = instr->variables[0]->deref.child->type;
3801
3802 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3803 return get_buffer_size(ctx,
3804 get_sampler_desc(ctx, instr->variables[0],
3805 AC_DESC_BUFFER, NULL, true, false), true);
3806
3807 struct ac_image_args args = { 0 };
3808
3809 args.da = da;
3810 args.dmask = 0xf;
3811 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3812 args.opcode = ac_image_get_resinfo;
3813 args.addr = ctx->ac.i32_0;
3814
3815 res = ac_build_image_opcode(&ctx->ac, &args);
3816
3817 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3818
3819 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3820 glsl_sampler_type_is_array(type)) {
3821 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3822 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3823 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3824 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3825 }
3826 if (ctx->ac.chip_class >= GFX9 &&
3827 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3828 glsl_sampler_type_is_array(type)) {
3829 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3830 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3831 ctx->ac.i32_1, "");
3832
3833 }
3834 return res;
3835 }
3836
3837 #define NOOP_WAITCNT 0xf7f
3838 #define LGKM_CNT 0x07f
3839 #define VM_CNT 0xf70
3840
3841 static void emit_membar(struct nir_to_llvm_context *ctx,
3842 const nir_intrinsic_instr *instr)
3843 {
3844 unsigned waitcnt = NOOP_WAITCNT;
3845
3846 switch (instr->intrinsic) {
3847 case nir_intrinsic_memory_barrier:
3848 case nir_intrinsic_group_memory_barrier:
3849 waitcnt &= VM_CNT & LGKM_CNT;
3850 break;
3851 case nir_intrinsic_memory_barrier_atomic_counter:
3852 case nir_intrinsic_memory_barrier_buffer:
3853 case nir_intrinsic_memory_barrier_image:
3854 waitcnt &= VM_CNT;
3855 break;
3856 case nir_intrinsic_memory_barrier_shared:
3857 waitcnt &= LGKM_CNT;
3858 break;
3859 default:
3860 break;
3861 }
3862 if (waitcnt != NOOP_WAITCNT)
3863 ac_build_waitcnt(&ctx->ac, waitcnt);
3864 }
3865
3866 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3867 {
3868 /* SI only (thanks to a hw bug workaround):
3869 * The real barrier instruction isn’t needed, because an entire patch
3870 * always fits into a single wave.
3871 */
3872 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3873 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3874 return;
3875 }
3876 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3877 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3878 }
3879
3880 static void emit_discard(struct ac_nir_context *ctx,
3881 const nir_intrinsic_instr *instr)
3882 {
3883 LLVMValueRef cond;
3884
3885 if (instr->intrinsic == nir_intrinsic_discard_if) {
3886 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3887 get_src(ctx, instr->src[0]),
3888 ctx->ac.i32_0, "");
3889 } else {
3890 assert(instr->intrinsic == nir_intrinsic_discard);
3891 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3892 }
3893
3894 ac_build_kill_if_false(&ctx->ac, cond);
3895 }
3896
3897 static LLVMValueRef
3898 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3899 {
3900 LLVMValueRef result;
3901 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3902 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3903 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3904
3905 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3906 }
3907
3908 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3909 const nir_intrinsic_instr *instr)
3910 {
3911 LLVMValueRef ptr, result;
3912 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3913 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3914
3915 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3916 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3917 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3918 ptr, src, src1,
3919 LLVMAtomicOrderingSequentiallyConsistent,
3920 LLVMAtomicOrderingSequentiallyConsistent,
3921 false);
3922 } else {
3923 LLVMAtomicRMWBinOp op;
3924 switch (instr->intrinsic) {
3925 case nir_intrinsic_var_atomic_add:
3926 op = LLVMAtomicRMWBinOpAdd;
3927 break;
3928 case nir_intrinsic_var_atomic_umin:
3929 op = LLVMAtomicRMWBinOpUMin;
3930 break;
3931 case nir_intrinsic_var_atomic_umax:
3932 op = LLVMAtomicRMWBinOpUMax;
3933 break;
3934 case nir_intrinsic_var_atomic_imin:
3935 op = LLVMAtomicRMWBinOpMin;
3936 break;
3937 case nir_intrinsic_var_atomic_imax:
3938 op = LLVMAtomicRMWBinOpMax;
3939 break;
3940 case nir_intrinsic_var_atomic_and:
3941 op = LLVMAtomicRMWBinOpAnd;
3942 break;
3943 case nir_intrinsic_var_atomic_or:
3944 op = LLVMAtomicRMWBinOpOr;
3945 break;
3946 case nir_intrinsic_var_atomic_xor:
3947 op = LLVMAtomicRMWBinOpXor;
3948 break;
3949 case nir_intrinsic_var_atomic_exchange:
3950 op = LLVMAtomicRMWBinOpXchg;
3951 break;
3952 default:
3953 return NULL;
3954 }
3955
3956 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3957 LLVMAtomicOrderingSequentiallyConsistent,
3958 false);
3959 }
3960 return result;
3961 }
3962
3963 #define INTERP_CENTER 0
3964 #define INTERP_CENTROID 1
3965 #define INTERP_SAMPLE 2
3966
3967 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3968 enum glsl_interp_mode interp, unsigned location)
3969 {
3970 switch (interp) {
3971 case INTERP_MODE_FLAT:
3972 default:
3973 return NULL;
3974 case INTERP_MODE_SMOOTH:
3975 case INTERP_MODE_NONE:
3976 if (location == INTERP_CENTER)
3977 return ctx->persp_center;
3978 else if (location == INTERP_CENTROID)
3979 return ctx->persp_centroid;
3980 else if (location == INTERP_SAMPLE)
3981 return ctx->persp_sample;
3982 break;
3983 case INTERP_MODE_NOPERSPECTIVE:
3984 if (location == INTERP_CENTER)
3985 return ctx->linear_center;
3986 else if (location == INTERP_CENTROID)
3987 return ctx->linear_centroid;
3988 else if (location == INTERP_SAMPLE)
3989 return ctx->linear_sample;
3990 break;
3991 }
3992 return NULL;
3993 }
3994
3995 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3996 LLVMValueRef sample_id)
3997 {
3998 LLVMValueRef result;
3999 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4000
4001 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4002 const_array(ctx->ac.v2f32, 64), "");
4003
4004 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4005 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4006
4007 return result;
4008 }
4009
4010 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4011 {
4012 LLVMValueRef values[2];
4013
4014 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
4015 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
4016 return ac_build_gather_values(&ctx->ac, values, 2);
4017 }
4018
4019 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
4020 const nir_intrinsic_instr *instr)
4021 {
4022 LLVMValueRef result[4];
4023 LLVMValueRef interp_param, attr_number;
4024 unsigned location;
4025 unsigned chan;
4026 LLVMValueRef src_c0 = NULL;
4027 LLVMValueRef src_c1 = NULL;
4028 LLVMValueRef src0 = NULL;
4029 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4030 switch (instr->intrinsic) {
4031 case nir_intrinsic_interp_var_at_centroid:
4032 location = INTERP_CENTROID;
4033 break;
4034 case nir_intrinsic_interp_var_at_sample:
4035 case nir_intrinsic_interp_var_at_offset:
4036 location = INTERP_CENTER;
4037 src0 = get_src(ctx->nir, instr->src[0]);
4038 break;
4039 default:
4040 break;
4041 }
4042
4043 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4044 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4045 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4046 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4047 LLVMValueRef sample_position;
4048 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4049
4050 /* fetch sample ID */
4051 sample_position = load_sample_position(ctx, src0);
4052
4053 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4054 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4055 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4056 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4057 }
4058 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4059 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4060
4061 if (location == INTERP_CENTER) {
4062 LLVMValueRef ij_out[2];
4063 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4064
4065 /*
4066 * take the I then J parameters, and the DDX/Y for it, and
4067 * calculate the IJ inputs for the interpolator.
4068 * temp1 = ddx * offset/sample.x + I;
4069 * interp_param.I = ddy * offset/sample.y + temp1;
4070 * temp1 = ddx * offset/sample.x + J;
4071 * interp_param.J = ddy * offset/sample.y + temp1;
4072 */
4073 for (unsigned i = 0; i < 2; i++) {
4074 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4075 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4076 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4077 ddxy_out, ix_ll, "");
4078 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4079 ddxy_out, iy_ll, "");
4080 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4081 interp_param, ix_ll, "");
4082 LLVMValueRef temp1, temp2;
4083
4084 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4085 ctx->ac.f32, "");
4086
4087 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4088 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4089
4090 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4091 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4092
4093 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4094 temp2, ctx->ac.i32, "");
4095 }
4096 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4097
4098 }
4099
4100 for (chan = 0; chan < 4; chan++) {
4101 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4102
4103 if (interp_param) {
4104 interp_param = LLVMBuildBitCast(ctx->builder,
4105 interp_param, ctx->ac.v2f32, "");
4106 LLVMValueRef i = LLVMBuildExtractElement(
4107 ctx->builder, interp_param, ctx->ac.i32_0, "");
4108 LLVMValueRef j = LLVMBuildExtractElement(
4109 ctx->builder, interp_param, ctx->ac.i32_1, "");
4110
4111 result[chan] = ac_build_fs_interp(&ctx->ac,
4112 llvm_chan, attr_number,
4113 ctx->prim_mask, i, j);
4114 } else {
4115 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4116 LLVMConstInt(ctx->ac.i32, 2, false),
4117 llvm_chan, attr_number,
4118 ctx->prim_mask);
4119 }
4120 }
4121 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4122 instr->variables[0]->var->data.location_frac);
4123 }
4124
4125 static void
4126 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4127 {
4128 LLVMValueRef gs_next_vertex;
4129 LLVMValueRef can_emit;
4130 int idx;
4131 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4132
4133 /* Write vertex attribute values to GSVS ring */
4134 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4135 ctx->gs_next_vertex,
4136 "");
4137
4138 /* If this thread has already emitted the declared maximum number of
4139 * vertices, kill it: excessive vertex emissions are not supposed to
4140 * have any effect, and GS threads have no externally observable
4141 * effects other than emitting vertices.
4142 */
4143 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4144 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4145 ac_build_kill_if_false(&ctx->ac, can_emit);
4146
4147 /* loop num outputs */
4148 idx = 0;
4149 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4150 LLVMValueRef *out_ptr = &addrs[i * 4];
4151 int length = 4;
4152 int slot = idx;
4153 int slot_inc = 1;
4154
4155 if (!(ctx->output_mask & (1ull << i)))
4156 continue;
4157
4158 if (i == VARYING_SLOT_CLIP_DIST0) {
4159 /* pack clip and cull into a single set of slots */
4160 length = ctx->num_output_clips + ctx->num_output_culls;
4161 if (length > 4)
4162 slot_inc = 2;
4163 }
4164 for (unsigned j = 0; j < length; j++) {
4165 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4166 out_ptr[j], "");
4167 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4168 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4169 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4170
4171 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4172
4173 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4174 out_val, 1,
4175 voffset, ctx->gs2vs_offset, 0,
4176 1, 1, true, true);
4177 }
4178 idx += slot_inc;
4179 }
4180
4181 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4182 ctx->ac.i32_1, "");
4183 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4184
4185 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4186 }
4187
4188 static void
4189 visit_end_primitive(struct nir_to_llvm_context *ctx,
4190 const nir_intrinsic_instr *instr)
4191 {
4192 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4193 }
4194
4195 static LLVMValueRef
4196 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4197 unsigned num_components)
4198 {
4199 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4200
4201 LLVMValueRef coord[4] = {
4202 ctx->tes_u,
4203 ctx->tes_v,
4204 ctx->ac.f32_0,
4205 ctx->ac.f32_0,
4206 };
4207
4208 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4209 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4210 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4211
4212 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4213 return LLVMBuildBitCast(ctx->builder, result, type, "");
4214 }
4215
4216 static LLVMValueRef
4217 load_patch_vertices_in(struct ac_shader_abi *abi)
4218 {
4219 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4220 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4221 }
4222
4223 static void visit_intrinsic(struct ac_nir_context *ctx,
4224 nir_intrinsic_instr *instr)
4225 {
4226 LLVMValueRef result = NULL;
4227
4228 switch (instr->intrinsic) {
4229 case nir_intrinsic_load_work_group_id: {
4230 LLVMValueRef values[3];
4231
4232 for (int i = 0; i < 3; i++) {
4233 values[i] = ctx->nctx->workgroup_ids[i] ?
4234 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4235 }
4236
4237 result = ac_build_gather_values(&ctx->ac, values, 3);
4238 break;
4239 }
4240 case nir_intrinsic_load_base_vertex: {
4241 result = ctx->abi->base_vertex;
4242 break;
4243 }
4244 case nir_intrinsic_load_vertex_id_zero_base: {
4245 result = ctx->abi->vertex_id;
4246 break;
4247 }
4248 case nir_intrinsic_load_local_invocation_id: {
4249 result = ctx->nctx->local_invocation_ids;
4250 break;
4251 }
4252 case nir_intrinsic_load_base_instance:
4253 result = ctx->abi->start_instance;
4254 break;
4255 case nir_intrinsic_load_draw_id:
4256 result = ctx->abi->draw_id;
4257 break;
4258 case nir_intrinsic_load_view_index:
4259 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4260 break;
4261 case nir_intrinsic_load_invocation_id:
4262 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4263 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4264 else
4265 result = ctx->abi->gs_invocation_id;
4266 break;
4267 case nir_intrinsic_load_primitive_id:
4268 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4269 result = ctx->abi->gs_prim_id;
4270 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4271 result = ctx->abi->tcs_patch_id;
4272 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4273 result = ctx->abi->tes_patch_id;
4274 } else
4275 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4276 break;
4277 case nir_intrinsic_load_sample_id:
4278 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4279 break;
4280 case nir_intrinsic_load_sample_pos:
4281 result = load_sample_pos(ctx);
4282 break;
4283 case nir_intrinsic_load_sample_mask_in:
4284 result = ctx->abi->sample_coverage;
4285 break;
4286 case nir_intrinsic_load_frag_coord: {
4287 LLVMValueRef values[4] = {
4288 ctx->abi->frag_pos[0],
4289 ctx->abi->frag_pos[1],
4290 ctx->abi->frag_pos[2],
4291 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4292 };
4293 result = ac_build_gather_values(&ctx->ac, values, 4);
4294 break;
4295 }
4296 case nir_intrinsic_load_front_face:
4297 result = ctx->abi->front_face;
4298 break;
4299 case nir_intrinsic_load_instance_id:
4300 result = ctx->abi->instance_id;
4301 break;
4302 case nir_intrinsic_load_num_work_groups:
4303 result = ctx->nctx->num_work_groups;
4304 break;
4305 case nir_intrinsic_load_local_invocation_index:
4306 result = visit_load_local_invocation_index(ctx->nctx);
4307 break;
4308 case nir_intrinsic_load_push_constant:
4309 result = visit_load_push_constant(ctx->nctx, instr);
4310 break;
4311 case nir_intrinsic_vulkan_resource_index:
4312 result = visit_vulkan_resource_index(ctx->nctx, instr);
4313 break;
4314 case nir_intrinsic_vulkan_resource_reindex:
4315 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4316 break;
4317 case nir_intrinsic_store_ssbo:
4318 visit_store_ssbo(ctx, instr);
4319 break;
4320 case nir_intrinsic_load_ssbo:
4321 result = visit_load_buffer(ctx, instr);
4322 break;
4323 case nir_intrinsic_ssbo_atomic_add:
4324 case nir_intrinsic_ssbo_atomic_imin:
4325 case nir_intrinsic_ssbo_atomic_umin:
4326 case nir_intrinsic_ssbo_atomic_imax:
4327 case nir_intrinsic_ssbo_atomic_umax:
4328 case nir_intrinsic_ssbo_atomic_and:
4329 case nir_intrinsic_ssbo_atomic_or:
4330 case nir_intrinsic_ssbo_atomic_xor:
4331 case nir_intrinsic_ssbo_atomic_exchange:
4332 case nir_intrinsic_ssbo_atomic_comp_swap:
4333 result = visit_atomic_ssbo(ctx, instr);
4334 break;
4335 case nir_intrinsic_load_ubo:
4336 result = visit_load_ubo_buffer(ctx, instr);
4337 break;
4338 case nir_intrinsic_get_buffer_size:
4339 result = visit_get_buffer_size(ctx, instr);
4340 break;
4341 case nir_intrinsic_load_var:
4342 result = visit_load_var(ctx, instr);
4343 break;
4344 case nir_intrinsic_store_var:
4345 visit_store_var(ctx, instr);
4346 break;
4347 case nir_intrinsic_image_load:
4348 result = visit_image_load(ctx, instr);
4349 break;
4350 case nir_intrinsic_image_store:
4351 visit_image_store(ctx, instr);
4352 break;
4353 case nir_intrinsic_image_atomic_add:
4354 case nir_intrinsic_image_atomic_min:
4355 case nir_intrinsic_image_atomic_max:
4356 case nir_intrinsic_image_atomic_and:
4357 case nir_intrinsic_image_atomic_or:
4358 case nir_intrinsic_image_atomic_xor:
4359 case nir_intrinsic_image_atomic_exchange:
4360 case nir_intrinsic_image_atomic_comp_swap:
4361 result = visit_image_atomic(ctx, instr);
4362 break;
4363 case nir_intrinsic_image_size:
4364 result = visit_image_size(ctx, instr);
4365 break;
4366 case nir_intrinsic_discard:
4367 case nir_intrinsic_discard_if:
4368 emit_discard(ctx, instr);
4369 break;
4370 case nir_intrinsic_memory_barrier:
4371 case nir_intrinsic_group_memory_barrier:
4372 case nir_intrinsic_memory_barrier_atomic_counter:
4373 case nir_intrinsic_memory_barrier_buffer:
4374 case nir_intrinsic_memory_barrier_image:
4375 case nir_intrinsic_memory_barrier_shared:
4376 emit_membar(ctx->nctx, instr);
4377 break;
4378 case nir_intrinsic_barrier:
4379 emit_barrier(&ctx->ac, ctx->stage);
4380 break;
4381 case nir_intrinsic_var_atomic_add:
4382 case nir_intrinsic_var_atomic_imin:
4383 case nir_intrinsic_var_atomic_umin:
4384 case nir_intrinsic_var_atomic_imax:
4385 case nir_intrinsic_var_atomic_umax:
4386 case nir_intrinsic_var_atomic_and:
4387 case nir_intrinsic_var_atomic_or:
4388 case nir_intrinsic_var_atomic_xor:
4389 case nir_intrinsic_var_atomic_exchange:
4390 case nir_intrinsic_var_atomic_comp_swap:
4391 result = visit_var_atomic(ctx->nctx, instr);
4392 break;
4393 case nir_intrinsic_interp_var_at_centroid:
4394 case nir_intrinsic_interp_var_at_sample:
4395 case nir_intrinsic_interp_var_at_offset:
4396 result = visit_interp(ctx->nctx, instr);
4397 break;
4398 case nir_intrinsic_emit_vertex:
4399 assert(instr->const_index[0] == 0);
4400 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4401 break;
4402 case nir_intrinsic_end_primitive:
4403 visit_end_primitive(ctx->nctx, instr);
4404 break;
4405 case nir_intrinsic_load_tess_coord: {
4406 LLVMTypeRef type = ctx->nctx ?
4407 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4408 NULL;
4409 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4410 break;
4411 }
4412 case nir_intrinsic_load_tess_level_outer:
4413 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4414 break;
4415 case nir_intrinsic_load_tess_level_inner:
4416 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4417 break;
4418 case nir_intrinsic_load_patch_vertices_in:
4419 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4420 break;
4421 default:
4422 fprintf(stderr, "Unknown intrinsic: ");
4423 nir_print_instr(&instr->instr, stderr);
4424 fprintf(stderr, "\n");
4425 break;
4426 }
4427 if (result) {
4428 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4429 }
4430 }
4431
4432 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4433 LLVMValueRef buffer_ptr, bool write)
4434 {
4435 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4436
4437 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4438 ctx->shader_info->fs.writes_memory = true;
4439
4440 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4441 }
4442
4443 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4444 {
4445 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4446
4447 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4448 }
4449
4450 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4451 unsigned descriptor_set,
4452 unsigned base_index,
4453 unsigned constant_index,
4454 LLVMValueRef index,
4455 enum ac_descriptor_type desc_type,
4456 bool image, bool write)
4457 {
4458 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4459 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4460 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4461 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4462 unsigned offset = binding->offset;
4463 unsigned stride = binding->size;
4464 unsigned type_size;
4465 LLVMBuilderRef builder = ctx->builder;
4466 LLVMTypeRef type;
4467
4468 assert(base_index < layout->binding_count);
4469
4470 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4471 ctx->shader_info->fs.writes_memory = true;
4472
4473 switch (desc_type) {
4474 case AC_DESC_IMAGE:
4475 type = ctx->ac.v8i32;
4476 type_size = 32;
4477 break;
4478 case AC_DESC_FMASK:
4479 type = ctx->ac.v8i32;
4480 offset += 32;
4481 type_size = 32;
4482 break;
4483 case AC_DESC_SAMPLER:
4484 type = ctx->ac.v4i32;
4485 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4486 offset += 64;
4487
4488 type_size = 16;
4489 break;
4490 case AC_DESC_BUFFER:
4491 type = ctx->ac.v4i32;
4492 type_size = 16;
4493 break;
4494 default:
4495 unreachable("invalid desc_type\n");
4496 }
4497
4498 offset += constant_index * stride;
4499
4500 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4501 (!index || binding->immutable_samplers_equal)) {
4502 if (binding->immutable_samplers_equal)
4503 constant_index = 0;
4504
4505 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4506
4507 LLVMValueRef constants[] = {
4508 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4509 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4510 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4511 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4512 };
4513 return ac_build_gather_values(&ctx->ac, constants, 4);
4514 }
4515
4516 assert(stride % type_size == 0);
4517
4518 if (!index)
4519 index = ctx->ac.i32_0;
4520
4521 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4522
4523 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4524 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4525
4526 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4527 }
4528
4529 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4530 const nir_deref_var *deref,
4531 enum ac_descriptor_type desc_type,
4532 const nir_tex_instr *tex_instr,
4533 bool image, bool write)
4534 {
4535 LLVMValueRef index = NULL;
4536 unsigned constant_index = 0;
4537 unsigned descriptor_set;
4538 unsigned base_index;
4539
4540 if (!deref) {
4541 assert(tex_instr && !image);
4542 descriptor_set = 0;
4543 base_index = tex_instr->sampler_index;
4544 } else {
4545 const nir_deref *tail = &deref->deref;
4546 while (tail->child) {
4547 const nir_deref_array *child = nir_deref_as_array(tail->child);
4548 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4549
4550 if (!array_size)
4551 array_size = 1;
4552
4553 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4554
4555 if (child->deref_array_type == nir_deref_array_type_indirect) {
4556 LLVMValueRef indirect = get_src(ctx, child->indirect);
4557
4558 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4559 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4560
4561 if (!index)
4562 index = indirect;
4563 else
4564 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4565 }
4566
4567 constant_index += child->base_offset * array_size;
4568
4569 tail = &child->deref;
4570 }
4571 descriptor_set = deref->var->data.descriptor_set;
4572 base_index = deref->var->data.binding;
4573 }
4574
4575 return ctx->abi->load_sampler_desc(ctx->abi,
4576 descriptor_set,
4577 base_index,
4578 constant_index, index,
4579 desc_type, image, write);
4580 }
4581
4582 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4583 struct ac_image_args *args,
4584 const nir_tex_instr *instr,
4585 nir_texop op,
4586 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4587 LLVMValueRef *param, unsigned count,
4588 unsigned dmask)
4589 {
4590 unsigned is_rect = 0;
4591 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4592
4593 if (op == nir_texop_lod)
4594 da = false;
4595 /* Pad to power of two vector */
4596 while (count < util_next_power_of_two(count))
4597 param[count++] = LLVMGetUndef(ctx->i32);
4598
4599 if (count > 1)
4600 args->addr = ac_build_gather_values(ctx, param, count);
4601 else
4602 args->addr = param[0];
4603
4604 args->resource = res_ptr;
4605 args->sampler = samp_ptr;
4606
4607 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4608 args->addr = param[0];
4609 return;
4610 }
4611
4612 args->dmask = dmask;
4613 args->unorm = is_rect;
4614 args->da = da;
4615 }
4616
4617 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4618 *
4619 * SI-CI:
4620 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4621 * filtering manually. The driver sets img7 to a mask clearing
4622 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4623 * s_and_b32 samp0, samp0, img7
4624 *
4625 * VI:
4626 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4627 */
4628 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4629 LLVMValueRef res, LLVMValueRef samp)
4630 {
4631 LLVMBuilderRef builder = ctx->ac.builder;
4632 LLVMValueRef img7, samp0;
4633
4634 if (ctx->ac.chip_class >= VI)
4635 return samp;
4636
4637 img7 = LLVMBuildExtractElement(builder, res,
4638 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4639 samp0 = LLVMBuildExtractElement(builder, samp,
4640 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4641 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4642 return LLVMBuildInsertElement(builder, samp, samp0,
4643 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4644 }
4645
4646 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4647 nir_tex_instr *instr,
4648 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4649 LLVMValueRef *fmask_ptr)
4650 {
4651 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4652 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4653 else
4654 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4655 if (samp_ptr) {
4656 if (instr->sampler)
4657 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4658 else
4659 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4660 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4661 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4662 }
4663 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4664 instr->op == nir_texop_samples_identical))
4665 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4666 }
4667
4668 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4669 LLVMValueRef coord)
4670 {
4671 coord = ac_to_float(ctx, coord);
4672 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4673 coord = ac_to_integer(ctx, coord);
4674 return coord;
4675 }
4676
4677 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4678 {
4679 LLVMValueRef result = NULL;
4680 struct ac_image_args args = { 0 };
4681 unsigned dmask = 0xf;
4682 LLVMValueRef address[16];
4683 LLVMValueRef coords[5];
4684 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4685 LLVMValueRef bias = NULL, offsets = NULL;
4686 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4687 LLVMValueRef ddx = NULL, ddy = NULL;
4688 LLVMValueRef derivs[6];
4689 unsigned chan, count = 0;
4690 unsigned const_src = 0, num_deriv_comp = 0;
4691 bool lod_is_zero = false;
4692
4693 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4694
4695 for (unsigned i = 0; i < instr->num_srcs; i++) {
4696 switch (instr->src[i].src_type) {
4697 case nir_tex_src_coord:
4698 coord = get_src(ctx, instr->src[i].src);
4699 break;
4700 case nir_tex_src_projector:
4701 break;
4702 case nir_tex_src_comparator:
4703 comparator = get_src(ctx, instr->src[i].src);
4704 break;
4705 case nir_tex_src_offset:
4706 offsets = get_src(ctx, instr->src[i].src);
4707 const_src = i;
4708 break;
4709 case nir_tex_src_bias:
4710 bias = get_src(ctx, instr->src[i].src);
4711 break;
4712 case nir_tex_src_lod: {
4713 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4714
4715 if (val && val->i32[0] == 0)
4716 lod_is_zero = true;
4717 lod = get_src(ctx, instr->src[i].src);
4718 break;
4719 }
4720 case nir_tex_src_ms_index:
4721 sample_index = get_src(ctx, instr->src[i].src);
4722 break;
4723 case nir_tex_src_ms_mcs:
4724 break;
4725 case nir_tex_src_ddx:
4726 ddx = get_src(ctx, instr->src[i].src);
4727 num_deriv_comp = instr->src[i].src.ssa->num_components;
4728 break;
4729 case nir_tex_src_ddy:
4730 ddy = get_src(ctx, instr->src[i].src);
4731 break;
4732 case nir_tex_src_texture_offset:
4733 case nir_tex_src_sampler_offset:
4734 case nir_tex_src_plane:
4735 default:
4736 break;
4737 }
4738 }
4739
4740 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4741 result = get_buffer_size(ctx, res_ptr, true);
4742 goto write_result;
4743 }
4744
4745 if (instr->op == nir_texop_texture_samples) {
4746 LLVMValueRef res, samples, is_msaa;
4747 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4748 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4749 LLVMConstInt(ctx->ac.i32, 3, false), "");
4750 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4751 LLVMConstInt(ctx->ac.i32, 28, false), "");
4752 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4753 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4754 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4755 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4756
4757 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4758 LLVMConstInt(ctx->ac.i32, 16, false), "");
4759 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4760 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4761 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4762 samples, "");
4763 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4764 ctx->ac.i32_1, "");
4765 result = samples;
4766 goto write_result;
4767 }
4768
4769 if (coord)
4770 for (chan = 0; chan < instr->coord_components; chan++)
4771 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4772
4773 if (offsets && instr->op != nir_texop_txf) {
4774 LLVMValueRef offset[3], pack;
4775 for (chan = 0; chan < 3; ++chan)
4776 offset[chan] = ctx->ac.i32_0;
4777
4778 args.offset = true;
4779 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4780 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4781 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4782 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4783 if (chan)
4784 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4785 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4786 }
4787 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4788 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4789 address[count++] = pack;
4790
4791 }
4792 /* pack LOD bias value */
4793 if (instr->op == nir_texop_txb && bias) {
4794 address[count++] = bias;
4795 }
4796
4797 /* Pack depth comparison value */
4798 if (instr->is_shadow && comparator) {
4799 LLVMValueRef z = ac_to_float(&ctx->ac,
4800 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4801
4802 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4803 * so the depth comparison value isn't clamped for Z16 and
4804 * Z24 anymore. Do it manually here.
4805 *
4806 * It's unnecessary if the original texture format was
4807 * Z32_FLOAT, but we don't know that here.
4808 */
4809 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4810 z = ac_build_clamp(&ctx->ac, z);
4811
4812 address[count++] = z;
4813 }
4814
4815 /* pack derivatives */
4816 if (ddx || ddy) {
4817 int num_src_deriv_channels, num_dest_deriv_channels;
4818 switch (instr->sampler_dim) {
4819 case GLSL_SAMPLER_DIM_3D:
4820 case GLSL_SAMPLER_DIM_CUBE:
4821 num_deriv_comp = 3;
4822 num_src_deriv_channels = 3;
4823 num_dest_deriv_channels = 3;
4824 break;
4825 case GLSL_SAMPLER_DIM_2D:
4826 default:
4827 num_src_deriv_channels = 2;
4828 num_dest_deriv_channels = 2;
4829 num_deriv_comp = 2;
4830 break;
4831 case GLSL_SAMPLER_DIM_1D:
4832 num_src_deriv_channels = 1;
4833 if (ctx->ac.chip_class >= GFX9) {
4834 num_dest_deriv_channels = 2;
4835 num_deriv_comp = 2;
4836 } else {
4837 num_dest_deriv_channels = 1;
4838 num_deriv_comp = 1;
4839 }
4840 break;
4841 }
4842
4843 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4844 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4845 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4846 }
4847 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4848 derivs[i] = ctx->ac.f32_0;
4849 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4850 }
4851 }
4852
4853 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4854 for (chan = 0; chan < instr->coord_components; chan++)
4855 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4856 if (instr->coord_components == 3)
4857 coords[3] = LLVMGetUndef(ctx->ac.f32);
4858 ac_prepare_cube_coords(&ctx->ac,
4859 instr->op == nir_texop_txd, instr->is_array,
4860 instr->op == nir_texop_lod, coords, derivs);
4861 if (num_deriv_comp)
4862 num_deriv_comp--;
4863 }
4864
4865 if (ddx || ddy) {
4866 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4867 address[count++] = derivs[i];
4868 }
4869
4870 /* Pack texture coordinates */
4871 if (coord) {
4872 address[count++] = coords[0];
4873 if (instr->coord_components > 1) {
4874 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4875 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4876 }
4877 address[count++] = coords[1];
4878 }
4879 if (instr->coord_components > 2) {
4880 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4881 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4882 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4883 instr->op != nir_texop_txf) {
4884 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4885 }
4886 address[count++] = coords[2];
4887 }
4888
4889 if (ctx->ac.chip_class >= GFX9) {
4890 LLVMValueRef filler;
4891 if (instr->op == nir_texop_txf)
4892 filler = ctx->ac.i32_0;
4893 else
4894 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4895
4896 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4897 /* No nir_texop_lod, because it does not take a slice
4898 * even with array textures. */
4899 if (instr->is_array && instr->op != nir_texop_lod ) {
4900 address[count] = address[count - 1];
4901 address[count - 1] = filler;
4902 count++;
4903 } else
4904 address[count++] = filler;
4905 }
4906 }
4907 }
4908
4909 /* Pack LOD */
4910 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4911 instr->op == nir_texop_txf)) {
4912 address[count++] = lod;
4913 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4914 address[count++] = sample_index;
4915 } else if(instr->op == nir_texop_txs) {
4916 count = 0;
4917 if (lod)
4918 address[count++] = lod;
4919 else
4920 address[count++] = ctx->ac.i32_0;
4921 }
4922
4923 for (chan = 0; chan < count; chan++) {
4924 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4925 address[chan], ctx->ac.i32, "");
4926 }
4927
4928 if (instr->op == nir_texop_samples_identical) {
4929 LLVMValueRef txf_address[4];
4930 struct ac_image_args txf_args = { 0 };
4931 unsigned txf_count = count;
4932 memcpy(txf_address, address, sizeof(txf_address));
4933
4934 if (!instr->is_array)
4935 txf_address[2] = ctx->ac.i32_0;
4936 txf_address[3] = ctx->ac.i32_0;
4937
4938 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4939 fmask_ptr, NULL,
4940 txf_address, txf_count, 0xf);
4941
4942 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4943
4944 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4945 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4946 goto write_result;
4947 }
4948
4949 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4950 instr->op != nir_texop_txs) {
4951 unsigned sample_chan = instr->is_array ? 3 : 2;
4952 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4953 address[0],
4954 address[1],
4955 instr->is_array ? address[2] : NULL,
4956 address[sample_chan],
4957 fmask_ptr);
4958 }
4959
4960 if (offsets && instr->op == nir_texop_txf) {
4961 nir_const_value *const_offset =
4962 nir_src_as_const_value(instr->src[const_src].src);
4963 int num_offsets = instr->src[const_src].src.ssa->num_components;
4964 assert(const_offset);
4965 num_offsets = MIN2(num_offsets, instr->coord_components);
4966 if (num_offsets > 2)
4967 address[2] = LLVMBuildAdd(ctx->ac.builder,
4968 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4969 if (num_offsets > 1)
4970 address[1] = LLVMBuildAdd(ctx->ac.builder,
4971 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4972 address[0] = LLVMBuildAdd(ctx->ac.builder,
4973 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4974
4975 }
4976
4977 /* TODO TG4 support */
4978 if (instr->op == nir_texop_tg4) {
4979 if (instr->is_shadow)
4980 dmask = 1;
4981 else
4982 dmask = 1 << instr->component;
4983 }
4984 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4985 res_ptr, samp_ptr, address, count, dmask);
4986
4987 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4988
4989 if (instr->op == nir_texop_query_levels)
4990 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4991 else if (instr->is_shadow && instr->is_new_style_shadow &&
4992 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4993 instr->op != nir_texop_tg4)
4994 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4995 else if (instr->op == nir_texop_txs &&
4996 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4997 instr->is_array) {
4998 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4999 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5000 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5001 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5002 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5003 } else if (ctx->ac.chip_class >= GFX9 &&
5004 instr->op == nir_texop_txs &&
5005 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5006 instr->is_array) {
5007 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5008 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5009 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5010 ctx->ac.i32_1, "");
5011 } else if (instr->dest.ssa.num_components != 4)
5012 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5013
5014 write_result:
5015 if (result) {
5016 assert(instr->dest.is_ssa);
5017 result = ac_to_integer(&ctx->ac, result);
5018 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5019 }
5020 }
5021
5022
5023 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5024 {
5025 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5026 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5027
5028 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5029 _mesa_hash_table_insert(ctx->phis, instr, result);
5030 }
5031
5032 static void visit_post_phi(struct ac_nir_context *ctx,
5033 nir_phi_instr *instr,
5034 LLVMValueRef llvm_phi)
5035 {
5036 nir_foreach_phi_src(src, instr) {
5037 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5038 LLVMValueRef llvm_src = get_src(ctx, src->src);
5039
5040 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5041 }
5042 }
5043
5044 static void phi_post_pass(struct ac_nir_context *ctx)
5045 {
5046 struct hash_entry *entry;
5047 hash_table_foreach(ctx->phis, entry) {
5048 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5049 (LLVMValueRef)entry->data);
5050 }
5051 }
5052
5053
5054 static void visit_ssa_undef(struct ac_nir_context *ctx,
5055 const nir_ssa_undef_instr *instr)
5056 {
5057 unsigned num_components = instr->def.num_components;
5058 LLVMValueRef undef;
5059
5060 if (num_components == 1)
5061 undef = LLVMGetUndef(ctx->ac.i32);
5062 else {
5063 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5064 }
5065 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5066 }
5067
5068 static void visit_jump(struct ac_nir_context *ctx,
5069 const nir_jump_instr *instr)
5070 {
5071 switch (instr->type) {
5072 case nir_jump_break:
5073 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5074 LLVMClearInsertionPosition(ctx->ac.builder);
5075 break;
5076 case nir_jump_continue:
5077 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5078 LLVMClearInsertionPosition(ctx->ac.builder);
5079 break;
5080 default:
5081 fprintf(stderr, "Unknown NIR jump instr: ");
5082 nir_print_instr(&instr->instr, stderr);
5083 fprintf(stderr, "\n");
5084 abort();
5085 }
5086 }
5087
5088 static void visit_cf_list(struct ac_nir_context *ctx,
5089 struct exec_list *list);
5090
5091 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5092 {
5093 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5094 nir_foreach_instr(instr, block)
5095 {
5096 switch (instr->type) {
5097 case nir_instr_type_alu:
5098 visit_alu(ctx, nir_instr_as_alu(instr));
5099 break;
5100 case nir_instr_type_load_const:
5101 visit_load_const(ctx, nir_instr_as_load_const(instr));
5102 break;
5103 case nir_instr_type_intrinsic:
5104 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5105 break;
5106 case nir_instr_type_tex:
5107 visit_tex(ctx, nir_instr_as_tex(instr));
5108 break;
5109 case nir_instr_type_phi:
5110 visit_phi(ctx, nir_instr_as_phi(instr));
5111 break;
5112 case nir_instr_type_ssa_undef:
5113 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5114 break;
5115 case nir_instr_type_jump:
5116 visit_jump(ctx, nir_instr_as_jump(instr));
5117 break;
5118 default:
5119 fprintf(stderr, "Unknown NIR instr type: ");
5120 nir_print_instr(instr, stderr);
5121 fprintf(stderr, "\n");
5122 abort();
5123 }
5124 }
5125
5126 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5127 }
5128
5129 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5130 {
5131 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5132
5133 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5134 LLVMBasicBlockRef merge_block =
5135 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5136 LLVMBasicBlockRef if_block =
5137 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5138 LLVMBasicBlockRef else_block = merge_block;
5139 if (!exec_list_is_empty(&if_stmt->else_list))
5140 else_block = LLVMAppendBasicBlockInContext(
5141 ctx->ac.context, fn, "");
5142
5143 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5144 ctx->ac.i32_0, "");
5145 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5146
5147 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5148 visit_cf_list(ctx, &if_stmt->then_list);
5149 if (LLVMGetInsertBlock(ctx->ac.builder))
5150 LLVMBuildBr(ctx->ac.builder, merge_block);
5151
5152 if (!exec_list_is_empty(&if_stmt->else_list)) {
5153 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5154 visit_cf_list(ctx, &if_stmt->else_list);
5155 if (LLVMGetInsertBlock(ctx->ac.builder))
5156 LLVMBuildBr(ctx->ac.builder, merge_block);
5157 }
5158
5159 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5160 }
5161
5162 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5163 {
5164 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5165 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5166 LLVMBasicBlockRef break_parent = ctx->break_block;
5167
5168 ctx->continue_block =
5169 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5170 ctx->break_block =
5171 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5172
5173 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5174 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5175 visit_cf_list(ctx, &loop->body);
5176
5177 if (LLVMGetInsertBlock(ctx->ac.builder))
5178 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5179 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5180
5181 ctx->continue_block = continue_parent;
5182 ctx->break_block = break_parent;
5183 }
5184
5185 static void visit_cf_list(struct ac_nir_context *ctx,
5186 struct exec_list *list)
5187 {
5188 foreach_list_typed(nir_cf_node, node, node, list)
5189 {
5190 switch (node->type) {
5191 case nir_cf_node_block:
5192 visit_block(ctx, nir_cf_node_as_block(node));
5193 break;
5194
5195 case nir_cf_node_if:
5196 visit_if(ctx, nir_cf_node_as_if(node));
5197 break;
5198
5199 case nir_cf_node_loop:
5200 visit_loop(ctx, nir_cf_node_as_loop(node));
5201 break;
5202
5203 default:
5204 assert(0);
5205 }
5206 }
5207 }
5208
5209 static void
5210 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5211 struct nir_variable *variable)
5212 {
5213 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5214 LLVMValueRef t_offset;
5215 LLVMValueRef t_list;
5216 LLVMValueRef input;
5217 LLVMValueRef buffer_index;
5218 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5219 int idx = variable->data.location;
5220 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5221
5222 variable->data.driver_location = idx * 4;
5223
5224 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5225 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5226 ctx->abi.start_instance, "");
5227 if (ctx->options->key.vs.as_ls) {
5228 ctx->shader_info->vs.vgpr_comp_cnt =
5229 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5230 } else {
5231 ctx->shader_info->vs.vgpr_comp_cnt =
5232 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5233 }
5234 } else
5235 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5236 ctx->abi.base_vertex, "");
5237
5238 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5239 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5240
5241 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5242
5243 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5244 buffer_index,
5245 ctx->ac.i32_0,
5246 true);
5247
5248 for (unsigned chan = 0; chan < 4; chan++) {
5249 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5250 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5251 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5252 input, llvm_chan, ""));
5253 }
5254 }
5255 }
5256
5257 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5258 unsigned attr,
5259 LLVMValueRef interp_param,
5260 LLVMValueRef prim_mask,
5261 LLVMValueRef result[4])
5262 {
5263 LLVMValueRef attr_number;
5264 unsigned chan;
5265 LLVMValueRef i, j;
5266 bool interp = interp_param != NULL;
5267
5268 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5269
5270 /* fs.constant returns the param from the middle vertex, so it's not
5271 * really useful for flat shading. It's meant to be used for custom
5272 * interpolation (but the intrinsic can't fetch from the other two
5273 * vertices).
5274 *
5275 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5276 * to do the right thing. The only reason we use fs.constant is that
5277 * fs.interp cannot be used on integers, because they can be equal
5278 * to NaN.
5279 */
5280 if (interp) {
5281 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5282 ctx->ac.v2f32, "");
5283
5284 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5285 ctx->ac.i32_0, "");
5286 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5287 ctx->ac.i32_1, "");
5288 }
5289
5290 for (chan = 0; chan < 4; chan++) {
5291 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5292
5293 if (interp) {
5294 result[chan] = ac_build_fs_interp(&ctx->ac,
5295 llvm_chan,
5296 attr_number,
5297 prim_mask, i, j);
5298 } else {
5299 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5300 LLVMConstInt(ctx->ac.i32, 2, false),
5301 llvm_chan,
5302 attr_number,
5303 prim_mask);
5304 }
5305 }
5306 }
5307
5308 static void
5309 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5310 struct nir_variable *variable)
5311 {
5312 int idx = variable->data.location;
5313 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5314 LLVMValueRef interp;
5315
5316 variable->data.driver_location = idx * 4;
5317 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5318
5319 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5320 unsigned interp_type;
5321 if (variable->data.sample) {
5322 interp_type = INTERP_SAMPLE;
5323 ctx->shader_info->info.ps.force_persample = true;
5324 } else if (variable->data.centroid)
5325 interp_type = INTERP_CENTROID;
5326 else
5327 interp_type = INTERP_CENTER;
5328
5329 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5330 } else
5331 interp = NULL;
5332
5333 for (unsigned i = 0; i < attrib_count; ++i)
5334 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5335
5336 }
5337
5338 static void
5339 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5340 struct nir_shader *nir) {
5341 nir_foreach_variable(variable, &nir->inputs)
5342 handle_vs_input_decl(ctx, variable);
5343 }
5344
5345 static void
5346 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5347 struct nir_shader *nir)
5348 {
5349 if (!ctx->options->key.fs.multisample)
5350 return;
5351
5352 bool uses_center = false;
5353 bool uses_centroid = false;
5354 nir_foreach_variable(variable, &nir->inputs) {
5355 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5356 variable->data.sample)
5357 continue;
5358
5359 if (variable->data.centroid)
5360 uses_centroid = true;
5361 else
5362 uses_center = true;
5363 }
5364
5365 if (uses_center && uses_centroid) {
5366 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5367 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5368 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5369 }
5370 }
5371
5372 static void
5373 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5374 struct nir_shader *nir)
5375 {
5376 prepare_interp_optimize(ctx, nir);
5377
5378 nir_foreach_variable(variable, &nir->inputs)
5379 handle_fs_input_decl(ctx, variable);
5380
5381 unsigned index = 0;
5382
5383 if (ctx->shader_info->info.ps.uses_input_attachments ||
5384 ctx->shader_info->info.needs_multiview_view_index)
5385 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5386
5387 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5388 LLVMValueRef interp_param;
5389 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5390
5391 if (!(ctx->input_mask & (1ull << i)))
5392 continue;
5393
5394 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5395 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5396 interp_param = *inputs;
5397 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5398 inputs);
5399
5400 if (!interp_param)
5401 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5402 ++index;
5403 } else if (i == VARYING_SLOT_POS) {
5404 for(int i = 0; i < 3; ++i)
5405 inputs[i] = ctx->abi.frag_pos[i];
5406
5407 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5408 ctx->abi.frag_pos[3]);
5409 }
5410 }
5411 ctx->shader_info->fs.num_interp = index;
5412 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5413 ctx->shader_info->fs.has_pcoord = true;
5414 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5415 ctx->shader_info->fs.prim_id_input = true;
5416 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5417 ctx->shader_info->fs.layer_input = true;
5418 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5419
5420 if (ctx->shader_info->info.needs_multiview_view_index)
5421 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5422 }
5423
5424 static LLVMValueRef
5425 ac_build_alloca(struct ac_llvm_context *ac,
5426 LLVMTypeRef type,
5427 const char *name)
5428 {
5429 LLVMBuilderRef builder = ac->builder;
5430 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5431 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5432 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5433 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5434 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5435 LLVMValueRef res;
5436
5437 if (first_instr) {
5438 LLVMPositionBuilderBefore(first_builder, first_instr);
5439 } else {
5440 LLVMPositionBuilderAtEnd(first_builder, first_block);
5441 }
5442
5443 res = LLVMBuildAlloca(first_builder, type, name);
5444 LLVMBuildStore(builder, LLVMConstNull(type), res);
5445
5446 LLVMDisposeBuilder(first_builder);
5447
5448 return res;
5449 }
5450
5451 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5452 LLVMTypeRef type,
5453 const char *name)
5454 {
5455 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5456 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5457 return ptr;
5458 }
5459
5460 static void
5461 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5462 struct nir_variable *variable,
5463 struct nir_shader *shader,
5464 gl_shader_stage stage)
5465 {
5466 int idx = variable->data.location + variable->data.index;
5467 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5468 uint64_t mask_attribs;
5469
5470 variable->data.driver_location = idx * 4;
5471
5472 /* tess ctrl has it's own load/store paths for outputs */
5473 if (stage == MESA_SHADER_TESS_CTRL)
5474 return;
5475
5476 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5477 if (stage == MESA_SHADER_VERTEX ||
5478 stage == MESA_SHADER_TESS_EVAL ||
5479 stage == MESA_SHADER_GEOMETRY) {
5480 if (idx == VARYING_SLOT_CLIP_DIST0) {
5481 int length = shader->info.clip_distance_array_size +
5482 shader->info.cull_distance_array_size;
5483 if (stage == MESA_SHADER_VERTEX) {
5484 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5485 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5486 }
5487 if (stage == MESA_SHADER_TESS_EVAL) {
5488 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5489 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5490 }
5491
5492 if (length > 4)
5493 attrib_count = 2;
5494 else
5495 attrib_count = 1;
5496 mask_attribs = 1ull << idx;
5497 }
5498 }
5499
5500 ctx->output_mask |= mask_attribs;
5501 }
5502
5503 static void
5504 handle_shader_output_decl(struct ac_nir_context *ctx,
5505 struct nir_shader *nir,
5506 struct nir_variable *variable)
5507 {
5508 unsigned output_loc = variable->data.driver_location / 4;
5509 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5510
5511 /* tess ctrl has it's own load/store paths for outputs */
5512 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5513 return;
5514
5515 if (ctx->stage == MESA_SHADER_VERTEX ||
5516 ctx->stage == MESA_SHADER_TESS_EVAL ||
5517 ctx->stage == MESA_SHADER_GEOMETRY) {
5518 int idx = variable->data.location + variable->data.index;
5519 if (idx == VARYING_SLOT_CLIP_DIST0) {
5520 int length = nir->info.clip_distance_array_size +
5521 nir->info.cull_distance_array_size;
5522
5523 if (length > 4)
5524 attrib_count = 2;
5525 else
5526 attrib_count = 1;
5527 }
5528 }
5529
5530 for (unsigned i = 0; i < attrib_count; ++i) {
5531 for (unsigned chan = 0; chan < 4; chan++) {
5532 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5533 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5534 }
5535 }
5536 }
5537
5538 static LLVMTypeRef
5539 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5540 enum glsl_base_type type)
5541 {
5542 switch (type) {
5543 case GLSL_TYPE_INT:
5544 case GLSL_TYPE_UINT:
5545 case GLSL_TYPE_BOOL:
5546 case GLSL_TYPE_SUBROUTINE:
5547 return ctx->ac.i32;
5548 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5549 return ctx->ac.f32;
5550 case GLSL_TYPE_INT64:
5551 case GLSL_TYPE_UINT64:
5552 return ctx->ac.i64;
5553 case GLSL_TYPE_DOUBLE:
5554 return ctx->ac.f64;
5555 default:
5556 unreachable("unknown GLSL type");
5557 }
5558 }
5559
5560 static LLVMTypeRef
5561 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5562 const struct glsl_type *type)
5563 {
5564 if (glsl_type_is_scalar(type)) {
5565 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5566 }
5567
5568 if (glsl_type_is_vector(type)) {
5569 return LLVMVectorType(
5570 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5571 glsl_get_vector_elements(type));
5572 }
5573
5574 if (glsl_type_is_matrix(type)) {
5575 return LLVMArrayType(
5576 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5577 glsl_get_matrix_columns(type));
5578 }
5579
5580 if (glsl_type_is_array(type)) {
5581 return LLVMArrayType(
5582 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5583 glsl_get_length(type));
5584 }
5585
5586 assert(glsl_type_is_struct(type));
5587
5588 LLVMTypeRef member_types[glsl_get_length(type)];
5589
5590 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5591 member_types[i] =
5592 glsl_to_llvm_type(ctx,
5593 glsl_get_struct_field(type, i));
5594 }
5595
5596 return LLVMStructTypeInContext(ctx->context, member_types,
5597 glsl_get_length(type), false);
5598 }
5599
5600 static void
5601 setup_locals(struct ac_nir_context *ctx,
5602 struct nir_function *func)
5603 {
5604 int i, j;
5605 ctx->num_locals = 0;
5606 nir_foreach_variable(variable, &func->impl->locals) {
5607 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5608 variable->data.driver_location = ctx->num_locals * 4;
5609 variable->data.location_frac = 0;
5610 ctx->num_locals += attrib_count;
5611 }
5612 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5613 if (!ctx->locals)
5614 return;
5615
5616 for (i = 0; i < ctx->num_locals; i++) {
5617 for (j = 0; j < 4; j++) {
5618 ctx->locals[i * 4 + j] =
5619 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5620 }
5621 }
5622 }
5623
5624 static void
5625 setup_shared(struct ac_nir_context *ctx,
5626 struct nir_shader *nir)
5627 {
5628 nir_foreach_variable(variable, &nir->shared) {
5629 LLVMValueRef shared =
5630 LLVMAddGlobalInAddressSpace(
5631 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5632 variable->name ? variable->name : "",
5633 LOCAL_ADDR_SPACE);
5634 _mesa_hash_table_insert(ctx->vars, variable, shared);
5635 }
5636 }
5637
5638 static LLVMValueRef
5639 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5640 {
5641 v = ac_to_float(ctx, v);
5642 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5643 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5644 }
5645
5646
5647 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5648 LLVMValueRef src0, LLVMValueRef src1)
5649 {
5650 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5651 LLVMValueRef comp[2];
5652
5653 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5654 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5655 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5656 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5657 }
5658
5659 /* Initialize arguments for the shader export intrinsic */
5660 static void
5661 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5662 LLVMValueRef *values,
5663 unsigned target,
5664 struct ac_export_args *args)
5665 {
5666 /* Default is 0xf. Adjusted below depending on the format. */
5667 args->enabled_channels = 0xf;
5668
5669 /* Specify whether the EXEC mask represents the valid mask */
5670 args->valid_mask = 0;
5671
5672 /* Specify whether this is the last export */
5673 args->done = 0;
5674
5675 /* Specify the target we are exporting */
5676 args->target = target;
5677
5678 args->compr = false;
5679 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5680 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5681 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5682 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5683
5684 if (!values)
5685 return;
5686
5687 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5688 LLVMValueRef val[4];
5689 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5690 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5691 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5692 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5693
5694 switch(col_format) {
5695 case V_028714_SPI_SHADER_ZERO:
5696 args->enabled_channels = 0; /* writemask */
5697 args->target = V_008DFC_SQ_EXP_NULL;
5698 break;
5699
5700 case V_028714_SPI_SHADER_32_R:
5701 args->enabled_channels = 1;
5702 args->out[0] = values[0];
5703 break;
5704
5705 case V_028714_SPI_SHADER_32_GR:
5706 args->enabled_channels = 0x3;
5707 args->out[0] = values[0];
5708 args->out[1] = values[1];
5709 break;
5710
5711 case V_028714_SPI_SHADER_32_AR:
5712 args->enabled_channels = 0x9;
5713 args->out[0] = values[0];
5714 args->out[3] = values[3];
5715 break;
5716
5717 case V_028714_SPI_SHADER_FP16_ABGR:
5718 args->compr = 1;
5719
5720 for (unsigned chan = 0; chan < 2; chan++) {
5721 LLVMValueRef pack_args[2] = {
5722 values[2 * chan],
5723 values[2 * chan + 1]
5724 };
5725 LLVMValueRef packed;
5726
5727 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5728 args->out[chan] = packed;
5729 }
5730 break;
5731
5732 case V_028714_SPI_SHADER_UNORM16_ABGR:
5733 for (unsigned chan = 0; chan < 4; chan++) {
5734 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5735 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5736 LLVMConstReal(ctx->ac.f32, 65535), "");
5737 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5738 LLVMConstReal(ctx->ac.f32, 0.5), "");
5739 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5740 ctx->ac.i32, "");
5741 }
5742
5743 args->compr = 1;
5744 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5745 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5746 break;
5747
5748 case V_028714_SPI_SHADER_SNORM16_ABGR:
5749 for (unsigned chan = 0; chan < 4; chan++) {
5750 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5751 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5752 LLVMConstReal(ctx->ac.f32, 32767), "");
5753
5754 /* If positive, add 0.5, else add -0.5. */
5755 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5756 LLVMBuildSelect(ctx->builder,
5757 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5758 val[chan], ctx->ac.f32_0, ""),
5759 LLVMConstReal(ctx->ac.f32, 0.5),
5760 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5761 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5762 }
5763
5764 args->compr = 1;
5765 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5766 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5767 break;
5768
5769 case V_028714_SPI_SHADER_UINT16_ABGR: {
5770 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5771 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5772 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5773
5774 for (unsigned chan = 0; chan < 4; chan++) {
5775 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5776 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5777 }
5778
5779 args->compr = 1;
5780 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5781 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5782 break;
5783 }
5784
5785 case V_028714_SPI_SHADER_SINT16_ABGR: {
5786 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5787 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5788 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5789 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5790 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5791 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5792
5793 /* Clamp. */
5794 for (unsigned chan = 0; chan < 4; chan++) {
5795 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5796 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5797 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5798 }
5799
5800 args->compr = 1;
5801 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5802 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5803 break;
5804 }
5805
5806 default:
5807 case V_028714_SPI_SHADER_32_ABGR:
5808 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5809 break;
5810 }
5811 } else
5812 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5813
5814 for (unsigned i = 0; i < 4; ++i)
5815 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5816 }
5817
5818 static void
5819 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5820 bool export_prim_id,
5821 struct ac_vs_output_info *outinfo)
5822 {
5823 uint32_t param_count = 0;
5824 unsigned target;
5825 unsigned pos_idx, num_pos_exports = 0;
5826 struct ac_export_args args, pos_args[4] = {};
5827 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5828 int i;
5829
5830 if (ctx->options->key.has_multiview_view_index) {
5831 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5832 if(!*tmp_out) {
5833 for(unsigned i = 0; i < 4; ++i)
5834 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5835 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5836 }
5837
5838 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5839 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5840 }
5841
5842 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5843 sizeof(outinfo->vs_output_param_offset));
5844
5845 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5846 LLVMValueRef slots[8];
5847 unsigned j;
5848
5849 if (outinfo->cull_dist_mask)
5850 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5851
5852 i = VARYING_SLOT_CLIP_DIST0;
5853 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5854 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5855 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5856
5857 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5858 slots[i] = LLVMGetUndef(ctx->ac.f32);
5859
5860 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5861 target = V_008DFC_SQ_EXP_POS + 3;
5862 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5863 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5864 &args, sizeof(args));
5865 }
5866
5867 target = V_008DFC_SQ_EXP_POS + 2;
5868 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5869 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5870 &args, sizeof(args));
5871
5872 }
5873
5874 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5875 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5876 for (unsigned j = 0; j < 4; j++)
5877 pos_values[j] = LLVMBuildLoad(ctx->builder,
5878 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5879 }
5880 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5881
5882 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5883 outinfo->writes_pointsize = true;
5884 psize_value = LLVMBuildLoad(ctx->builder,
5885 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5886 }
5887
5888 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5889 outinfo->writes_layer = true;
5890 layer_value = LLVMBuildLoad(ctx->builder,
5891 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5892 }
5893
5894 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5895 outinfo->writes_viewport_index = true;
5896 viewport_index_value = LLVMBuildLoad(ctx->builder,
5897 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5898 }
5899
5900 if (outinfo->writes_pointsize ||
5901 outinfo->writes_layer ||
5902 outinfo->writes_viewport_index) {
5903 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5904 (outinfo->writes_layer == true ? 4 : 0));
5905 pos_args[1].valid_mask = 0;
5906 pos_args[1].done = 0;
5907 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5908 pos_args[1].compr = 0;
5909 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5910 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5911 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5912 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5913
5914 if (outinfo->writes_pointsize == true)
5915 pos_args[1].out[0] = psize_value;
5916 if (outinfo->writes_layer == true)
5917 pos_args[1].out[2] = layer_value;
5918 if (outinfo->writes_viewport_index == true) {
5919 if (ctx->options->chip_class >= GFX9) {
5920 /* GFX9 has the layer in out.z[10:0] and the viewport
5921 * index in out.z[19:16].
5922 */
5923 LLVMValueRef v = viewport_index_value;
5924 v = ac_to_integer(&ctx->ac, v);
5925 v = LLVMBuildShl(ctx->builder, v,
5926 LLVMConstInt(ctx->ac.i32, 16, false),
5927 "");
5928 v = LLVMBuildOr(ctx->builder, v,
5929 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5930
5931 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5932 pos_args[1].enabled_channels |= 1 << 2;
5933 } else {
5934 pos_args[1].out[3] = viewport_index_value;
5935 pos_args[1].enabled_channels |= 1 << 3;
5936 }
5937 }
5938 }
5939 for (i = 0; i < 4; i++) {
5940 if (pos_args[i].out[0])
5941 num_pos_exports++;
5942 }
5943
5944 pos_idx = 0;
5945 for (i = 0; i < 4; i++) {
5946 if (!pos_args[i].out[0])
5947 continue;
5948
5949 /* Specify the target we are exporting */
5950 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5951 if (pos_idx == num_pos_exports)
5952 pos_args[i].done = 1;
5953 ac_build_export(&ctx->ac, &pos_args[i]);
5954 }
5955
5956 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5957 LLVMValueRef values[4];
5958 if (!(ctx->output_mask & (1ull << i)))
5959 continue;
5960
5961 for (unsigned j = 0; j < 4; j++)
5962 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5963 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5964
5965 if (i == VARYING_SLOT_LAYER) {
5966 target = V_008DFC_SQ_EXP_PARAM + param_count;
5967 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5968 param_count++;
5969 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5970 target = V_008DFC_SQ_EXP_PARAM + param_count;
5971 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5972 param_count++;
5973 } else if (i >= VARYING_SLOT_VAR0) {
5974 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5975 target = V_008DFC_SQ_EXP_PARAM + param_count;
5976 outinfo->vs_output_param_offset[i] = param_count;
5977 param_count++;
5978 } else
5979 continue;
5980
5981 si_llvm_init_export_args(ctx, values, target, &args);
5982
5983 if (target >= V_008DFC_SQ_EXP_POS &&
5984 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5985 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5986 &args, sizeof(args));
5987 } else {
5988 ac_build_export(&ctx->ac, &args);
5989 }
5990 }
5991
5992 if (export_prim_id) {
5993 LLVMValueRef values[4];
5994 target = V_008DFC_SQ_EXP_PARAM + param_count;
5995 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5996 param_count++;
5997
5998 values[0] = ctx->vs_prim_id;
5999 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6000 ctx->shader_info->vs.vgpr_comp_cnt);
6001 for (unsigned j = 1; j < 4; j++)
6002 values[j] = ctx->ac.f32_0;
6003 si_llvm_init_export_args(ctx, values, target, &args);
6004 ac_build_export(&ctx->ac, &args);
6005 outinfo->export_prim_id = true;
6006 }
6007
6008 outinfo->pos_exports = num_pos_exports;
6009 outinfo->param_exports = param_count;
6010 }
6011
6012 static void
6013 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6014 struct ac_es_output_info *outinfo)
6015 {
6016 int j;
6017 uint64_t max_output_written = 0;
6018 LLVMValueRef lds_base = NULL;
6019
6020 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6021 int param_index;
6022 int length = 4;
6023
6024 if (!(ctx->output_mask & (1ull << i)))
6025 continue;
6026
6027 if (i == VARYING_SLOT_CLIP_DIST0)
6028 length = ctx->num_output_clips + ctx->num_output_culls;
6029
6030 param_index = shader_io_get_unique_index(i);
6031
6032 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6033 }
6034
6035 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6036
6037 if (ctx->ac.chip_class >= GFX9) {
6038 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6039 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6040 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6041 LLVMConstInt(ctx->ac.i32, 24, false),
6042 LLVMConstInt(ctx->ac.i32, 4, false), false);
6043 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6044 LLVMBuildMul(ctx->ac.builder, wave_idx,
6045 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6046 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6047 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6048 }
6049
6050 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6051 LLVMValueRef dw_addr;
6052 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6053 int param_index;
6054 int length = 4;
6055
6056 if (!(ctx->output_mask & (1ull << i)))
6057 continue;
6058
6059 if (i == VARYING_SLOT_CLIP_DIST0)
6060 length = ctx->num_output_clips + ctx->num_output_culls;
6061
6062 param_index = shader_io_get_unique_index(i);
6063
6064 if (lds_base) {
6065 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6066 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6067 "");
6068 }
6069 for (j = 0; j < length; j++) {
6070 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6071 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6072
6073 if (ctx->ac.chip_class >= GFX9) {
6074 ac_lds_store(&ctx->ac, dw_addr,
6075 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6076 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6077 } else {
6078 ac_build_buffer_store_dword(&ctx->ac,
6079 ctx->esgs_ring,
6080 out_val, 1,
6081 NULL, ctx->es2gs_offset,
6082 (4 * param_index + j) * 4,
6083 1, 1, true, true);
6084 }
6085 }
6086 }
6087 }
6088
6089 static void
6090 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6091 {
6092 LLVMValueRef vertex_id = ctx->rel_auto_id;
6093 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6094 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6095 vertex_dw_stride, "");
6096
6097 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6098 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6099 int length = 4;
6100
6101 if (!(ctx->output_mask & (1ull << i)))
6102 continue;
6103
6104 if (i == VARYING_SLOT_CLIP_DIST0)
6105 length = ctx->num_output_clips + ctx->num_output_culls;
6106 int param = shader_io_get_unique_index(i);
6107 mark_tess_output(ctx, false, param);
6108 if (length > 4)
6109 mark_tess_output(ctx, false, param + 1);
6110 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6111 LLVMConstInt(ctx->ac.i32, param * 4, false),
6112 "");
6113 for (unsigned j = 0; j < length; j++) {
6114 ac_lds_store(&ctx->ac, dw_addr,
6115 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6116 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6117 }
6118 }
6119 }
6120
6121 struct ac_build_if_state
6122 {
6123 struct nir_to_llvm_context *ctx;
6124 LLVMValueRef condition;
6125 LLVMBasicBlockRef entry_block;
6126 LLVMBasicBlockRef true_block;
6127 LLVMBasicBlockRef false_block;
6128 LLVMBasicBlockRef merge_block;
6129 };
6130
6131 static LLVMBasicBlockRef
6132 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6133 {
6134 LLVMBasicBlockRef current_block;
6135 LLVMBasicBlockRef next_block;
6136 LLVMBasicBlockRef new_block;
6137
6138 /* get current basic block */
6139 current_block = LLVMGetInsertBlock(ctx->builder);
6140
6141 /* chqeck if there's another block after this one */
6142 next_block = LLVMGetNextBasicBlock(current_block);
6143 if (next_block) {
6144 /* insert the new block before the next block */
6145 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6146 }
6147 else {
6148 /* append new block after current block */
6149 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6150 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6151 }
6152 return new_block;
6153 }
6154
6155 static void
6156 ac_nir_build_if(struct ac_build_if_state *ifthen,
6157 struct nir_to_llvm_context *ctx,
6158 LLVMValueRef condition)
6159 {
6160 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6161
6162 memset(ifthen, 0, sizeof *ifthen);
6163 ifthen->ctx = ctx;
6164 ifthen->condition = condition;
6165 ifthen->entry_block = block;
6166
6167 /* create endif/merge basic block for the phi functions */
6168 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6169
6170 /* create/insert true_block before merge_block */
6171 ifthen->true_block =
6172 LLVMInsertBasicBlockInContext(ctx->context,
6173 ifthen->merge_block,
6174 "if-true-block");
6175
6176 /* successive code goes into the true block */
6177 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6178 }
6179
6180 /**
6181 * End a conditional.
6182 */
6183 static void
6184 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6185 {
6186 LLVMBuilderRef builder = ifthen->ctx->builder;
6187
6188 /* Insert branch to the merge block from current block */
6189 LLVMBuildBr(builder, ifthen->merge_block);
6190
6191 /*
6192 * Now patch in the various branch instructions.
6193 */
6194
6195 /* Insert the conditional branch instruction at the end of entry_block */
6196 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6197 if (ifthen->false_block) {
6198 /* we have an else clause */
6199 LLVMBuildCondBr(builder, ifthen->condition,
6200 ifthen->true_block, ifthen->false_block);
6201 }
6202 else {
6203 /* no else clause */
6204 LLVMBuildCondBr(builder, ifthen->condition,
6205 ifthen->true_block, ifthen->merge_block);
6206 }
6207
6208 /* Resume building code at end of the ifthen->merge_block */
6209 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6210 }
6211
6212 static void
6213 write_tess_factors(struct nir_to_llvm_context *ctx)
6214 {
6215 unsigned stride, outer_comps, inner_comps;
6216 struct ac_build_if_state if_ctx, inner_if_ctx;
6217 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6218 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6219 unsigned tess_inner_index, tess_outer_index;
6220 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6221 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6222 int i;
6223 emit_barrier(&ctx->ac, ctx->stage);
6224
6225 switch (ctx->options->key.tcs.primitive_mode) {
6226 case GL_ISOLINES:
6227 stride = 2;
6228 outer_comps = 2;
6229 inner_comps = 0;
6230 break;
6231 case GL_TRIANGLES:
6232 stride = 4;
6233 outer_comps = 3;
6234 inner_comps = 1;
6235 break;
6236 case GL_QUADS:
6237 stride = 6;
6238 outer_comps = 4;
6239 inner_comps = 2;
6240 break;
6241 default:
6242 return;
6243 }
6244
6245 ac_nir_build_if(&if_ctx, ctx,
6246 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6247 invocation_id, ctx->ac.i32_0, ""));
6248
6249 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6250 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6251
6252 mark_tess_output(ctx, true, tess_inner_index);
6253 mark_tess_output(ctx, true, tess_outer_index);
6254 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6255 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6256 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6257 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6258 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6259
6260 for (i = 0; i < 4; i++) {
6261 inner[i] = LLVMGetUndef(ctx->ac.i32);
6262 outer[i] = LLVMGetUndef(ctx->ac.i32);
6263 }
6264
6265 // LINES reverseal
6266 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6267 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6268 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6269 ctx->ac.i32_1, "");
6270 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6271 } else {
6272 for (i = 0; i < outer_comps; i++) {
6273 outer[i] = out[i] =
6274 ac_lds_load(&ctx->ac, lds_outer);
6275 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6276 ctx->ac.i32_1, "");
6277 }
6278 for (i = 0; i < inner_comps; i++) {
6279 inner[i] = out[outer_comps+i] =
6280 ac_lds_load(&ctx->ac, lds_inner);
6281 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6282 ctx->ac.i32_1, "");
6283 }
6284 }
6285
6286 /* Convert the outputs to vectors for stores. */
6287 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6288 vec1 = NULL;
6289
6290 if (stride > 4)
6291 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6292
6293
6294 buffer = ctx->hs_ring_tess_factor;
6295 tf_base = ctx->tess_factor_offset;
6296 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6297 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6298 unsigned tf_offset = 0;
6299
6300 if (ctx->options->chip_class <= VI) {
6301 ac_nir_build_if(&inner_if_ctx, ctx,
6302 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6303 rel_patch_id, ctx->ac.i32_0, ""));
6304
6305 /* Store the dynamic HS control word. */
6306 ac_build_buffer_store_dword(&ctx->ac, buffer,
6307 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6308 1, ctx->ac.i32_0, tf_base,
6309 0, 1, 0, true, false);
6310 tf_offset += 4;
6311
6312 ac_nir_build_endif(&inner_if_ctx);
6313 }
6314
6315 /* Store the tessellation factors. */
6316 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6317 MIN2(stride, 4), byteoffset, tf_base,
6318 tf_offset, 1, 0, true, false);
6319 if (vec1)
6320 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6321 stride - 4, byteoffset, tf_base,
6322 16 + tf_offset, 1, 0, true, false);
6323
6324 //store to offchip for TES to read - only if TES reads them
6325 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6326 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6327 LLVMValueRef tf_inner_offset;
6328 unsigned param_outer, param_inner;
6329
6330 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6331 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6332 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6333
6334 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6335 util_next_power_of_two(outer_comps));
6336
6337 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6338 outer_comps, tf_outer_offset,
6339 ctx->oc_lds, 0, 1, 0, true, false);
6340 if (inner_comps) {
6341 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6342 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6343 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6344
6345 inner_vec = inner_comps == 1 ? inner[0] :
6346 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6347 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6348 inner_comps, tf_inner_offset,
6349 ctx->oc_lds, 0, 1, 0, true, false);
6350 }
6351 }
6352 ac_nir_build_endif(&if_ctx);
6353 }
6354
6355 static void
6356 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6357 {
6358 write_tess_factors(ctx);
6359 }
6360
6361 static bool
6362 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6363 LLVMValueRef *color, unsigned param, bool is_last,
6364 struct ac_export_args *args)
6365 {
6366 /* Export */
6367 si_llvm_init_export_args(ctx, color, param,
6368 args);
6369
6370 if (is_last) {
6371 args->valid_mask = 1; /* whether the EXEC mask is valid */
6372 args->done = 1; /* DONE bit */
6373 } else if (!args->enabled_channels)
6374 return false; /* unnecessary NULL export */
6375
6376 return true;
6377 }
6378
6379 static void
6380 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6381 LLVMValueRef depth, LLVMValueRef stencil,
6382 LLVMValueRef samplemask)
6383 {
6384 struct ac_export_args args;
6385
6386 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6387
6388 ac_build_export(&ctx->ac, &args);
6389 }
6390
6391 static void
6392 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6393 {
6394 unsigned index = 0;
6395 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6396 struct ac_export_args color_args[8];
6397
6398 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6399 LLVMValueRef values[4];
6400
6401 if (!(ctx->output_mask & (1ull << i)))
6402 continue;
6403
6404 if (i == FRAG_RESULT_DEPTH) {
6405 ctx->shader_info->fs.writes_z = true;
6406 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6407 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6408 } else if (i == FRAG_RESULT_STENCIL) {
6409 ctx->shader_info->fs.writes_stencil = true;
6410 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6411 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6412 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6413 ctx->shader_info->fs.writes_sample_mask = true;
6414 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6415 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6416 } else {
6417 bool last = false;
6418 for (unsigned j = 0; j < 4; j++)
6419 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6420 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6421
6422 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6423 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6424
6425 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6426 if (ret)
6427 index++;
6428 }
6429 }
6430
6431 for (unsigned i = 0; i < index; i++)
6432 ac_build_export(&ctx->ac, &color_args[i]);
6433 if (depth || stencil || samplemask)
6434 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6435 else if (!index) {
6436 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6437 ac_build_export(&ctx->ac, &color_args[0]);
6438 }
6439 }
6440
6441 static void
6442 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6443 {
6444 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6445 }
6446
6447 static void
6448 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6449 LLVMValueRef *addrs)
6450 {
6451 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6452
6453 switch (ctx->stage) {
6454 case MESA_SHADER_VERTEX:
6455 if (ctx->options->key.vs.as_ls)
6456 handle_ls_outputs_post(ctx);
6457 else if (ctx->options->key.vs.as_es)
6458 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6459 else
6460 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6461 &ctx->shader_info->vs.outinfo);
6462 break;
6463 case MESA_SHADER_FRAGMENT:
6464 handle_fs_outputs_post(ctx);
6465 break;
6466 case MESA_SHADER_GEOMETRY:
6467 emit_gs_epilogue(ctx);
6468 break;
6469 case MESA_SHADER_TESS_CTRL:
6470 handle_tcs_outputs_post(ctx);
6471 break;
6472 case MESA_SHADER_TESS_EVAL:
6473 if (ctx->options->key.tes.as_es)
6474 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6475 else
6476 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6477 &ctx->shader_info->tes.outinfo);
6478 break;
6479 default:
6480 break;
6481 }
6482 }
6483
6484 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6485 {
6486 LLVMPassManagerRef passmgr;
6487 /* Create the pass manager */
6488 passmgr = LLVMCreateFunctionPassManagerForModule(
6489 ctx->module);
6490
6491 /* This pass should eliminate all the load and store instructions */
6492 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6493
6494 /* Add some optimization passes */
6495 LLVMAddScalarReplAggregatesPass(passmgr);
6496 LLVMAddLICMPass(passmgr);
6497 LLVMAddAggressiveDCEPass(passmgr);
6498 LLVMAddCFGSimplificationPass(passmgr);
6499 LLVMAddInstructionCombiningPass(passmgr);
6500
6501 /* Run the pass */
6502 LLVMInitializeFunctionPassManager(passmgr);
6503 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6504 LLVMFinalizeFunctionPassManager(passmgr);
6505
6506 LLVMDisposeBuilder(ctx->builder);
6507 LLVMDisposePassManager(passmgr);
6508 }
6509
6510 static void
6511 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6512 {
6513 struct ac_vs_output_info *outinfo;
6514
6515 switch (ctx->stage) {
6516 case MESA_SHADER_FRAGMENT:
6517 case MESA_SHADER_COMPUTE:
6518 case MESA_SHADER_TESS_CTRL:
6519 case MESA_SHADER_GEOMETRY:
6520 return;
6521 case MESA_SHADER_VERTEX:
6522 if (ctx->options->key.vs.as_ls ||
6523 ctx->options->key.vs.as_es)
6524 return;
6525 outinfo = &ctx->shader_info->vs.outinfo;
6526 break;
6527 case MESA_SHADER_TESS_EVAL:
6528 if (ctx->options->key.vs.as_es)
6529 return;
6530 outinfo = &ctx->shader_info->tes.outinfo;
6531 break;
6532 default:
6533 unreachable("Unhandled shader type");
6534 }
6535
6536 ac_optimize_vs_outputs(&ctx->ac,
6537 ctx->main_function,
6538 outinfo->vs_output_param_offset,
6539 VARYING_SLOT_MAX,
6540 &outinfo->param_exports);
6541 }
6542
6543 static void
6544 ac_setup_rings(struct nir_to_llvm_context *ctx)
6545 {
6546 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6547 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6548 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6549 }
6550
6551 if (ctx->is_gs_copy_shader) {
6552 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6553 }
6554 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6555 LLVMValueRef tmp;
6556 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6557 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6558
6559 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6560
6561 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6562 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6563 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6564 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6565 }
6566
6567 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6568 ctx->stage == MESA_SHADER_TESS_EVAL) {
6569 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6570 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6571 }
6572 }
6573
6574 static unsigned
6575 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6576 const struct nir_shader *nir)
6577 {
6578 switch (nir->info.stage) {
6579 case MESA_SHADER_TESS_CTRL:
6580 return chip_class >= CIK ? 128 : 64;
6581 case MESA_SHADER_GEOMETRY:
6582 return chip_class >= GFX9 ? 128 : 64;
6583 case MESA_SHADER_COMPUTE:
6584 break;
6585 default:
6586 return 0;
6587 }
6588
6589 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6590 nir->info.cs.local_size[1] *
6591 nir->info.cs.local_size[2];
6592 return max_workgroup_size;
6593 }
6594
6595 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6596 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6597 {
6598 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6599 LLVMConstInt(ctx->ac.i32, 8, false),
6600 LLVMConstInt(ctx->ac.i32, 8, false), false);
6601 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6602 ctx->ac.i32_0, "");
6603 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6604 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6605 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6606 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6607 }
6608
6609 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6610 {
6611 for(int i = 5; i >= 0; --i) {
6612 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6613 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6614 LLVMConstInt(ctx->ac.i32, 16, false), false);
6615 }
6616
6617 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6618 LLVMConstInt(ctx->ac.i32, 16, false),
6619 LLVMConstInt(ctx->ac.i32, 8, false), false);
6620 }
6621
6622 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6623 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6624 {
6625 struct ac_nir_context ctx = {};
6626 struct nir_function *func;
6627
6628 ctx.ac = *ac;
6629 ctx.abi = abi;
6630
6631 ctx.nctx = nctx;
6632 if (nctx)
6633 nctx->nir = &ctx;
6634
6635 ctx.stage = nir->info.stage;
6636
6637 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6638
6639 nir_foreach_variable(variable, &nir->outputs)
6640 handle_shader_output_decl(&ctx, nir, variable);
6641
6642 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6643 _mesa_key_pointer_equal);
6644 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6645 _mesa_key_pointer_equal);
6646 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6647 _mesa_key_pointer_equal);
6648
6649 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6650
6651 setup_locals(&ctx, func);
6652
6653 if (nir->info.stage == MESA_SHADER_COMPUTE)
6654 setup_shared(&ctx, nir);
6655
6656 visit_cf_list(&ctx, &func->impl->body);
6657 phi_post_pass(&ctx);
6658
6659 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6660 ctx.outputs);
6661
6662 free(ctx.locals);
6663 ralloc_free(ctx.defs);
6664 ralloc_free(ctx.phis);
6665 ralloc_free(ctx.vars);
6666
6667 if (nctx)
6668 nctx->nir = NULL;
6669 }
6670
6671 static
6672 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6673 struct nir_shader *const *shaders,
6674 int shader_count,
6675 struct ac_shader_variant_info *shader_info,
6676 const struct ac_nir_compiler_options *options)
6677 {
6678 struct nir_to_llvm_context ctx = {0};
6679 unsigned i;
6680 ctx.options = options;
6681 ctx.shader_info = shader_info;
6682 ctx.context = LLVMContextCreate();
6683 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6684
6685 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6686 options->family);
6687 ctx.ac.module = ctx.module;
6688 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6689
6690 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6691 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6692 LLVMSetDataLayout(ctx.module, data_layout_str);
6693 LLVMDisposeTargetData(data_layout);
6694 LLVMDisposeMessage(data_layout_str);
6695
6696 enum ac_float_mode float_mode =
6697 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6698 AC_FLOAT_MODE_DEFAULT;
6699
6700 ctx.builder = ac_create_builder(ctx.context, float_mode);
6701 ctx.ac.builder = ctx.builder;
6702
6703 memset(shader_info, 0, sizeof(*shader_info));
6704
6705 for(int i = 0; i < shader_count; ++i)
6706 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6707
6708 for (i = 0; i < AC_UD_MAX_SETS; i++)
6709 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6710 for (i = 0; i < AC_UD_MAX_UD; i++)
6711 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6712
6713 ctx.max_workgroup_size = 0;
6714 for (int i = 0; i < shader_count; ++i) {
6715 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6716 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6717 shaders[i]));
6718 }
6719
6720 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6721 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6722
6723 ctx.abi.inputs = &ctx.inputs[0];
6724 ctx.abi.emit_outputs = handle_shader_outputs_post;
6725 ctx.abi.emit_vertex = visit_emit_vertex;
6726 ctx.abi.load_ubo = radv_load_ubo;
6727 ctx.abi.load_ssbo = radv_load_ssbo;
6728 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6729 ctx.abi.clamp_shadow_reference = false;
6730
6731 if (shader_count >= 2)
6732 ac_init_exec_full_mask(&ctx.ac);
6733
6734 if (ctx.ac.chip_class == GFX9 &&
6735 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6736 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6737
6738 for(int i = 0; i < shader_count; ++i) {
6739 ctx.stage = shaders[i]->info.stage;
6740 ctx.output_mask = 0;
6741 ctx.tess_outputs_written = 0;
6742 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6743 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6744
6745 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6746 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6747 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6748 ctx.abi.load_inputs = load_gs_input;
6749 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6750 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6751 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6752 ctx.abi.load_tess_varyings = load_tcs_varyings;
6753 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6754 ctx.abi.store_tcs_outputs = store_tcs_output;
6755 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6756 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6757 ctx.abi.load_tess_varyings = load_tes_input;
6758 ctx.abi.load_tess_coord = load_tess_coord;
6759 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6760 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6761 if (shader_info->info.vs.needs_instance_id) {
6762 if (ctx.options->key.vs.as_ls) {
6763 ctx.shader_info->vs.vgpr_comp_cnt =
6764 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6765 } else {
6766 ctx.shader_info->vs.vgpr_comp_cnt =
6767 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6768 }
6769 }
6770 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6771 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6772 }
6773
6774 if (i)
6775 emit_barrier(&ctx.ac, ctx.stage);
6776
6777 ac_setup_rings(&ctx);
6778
6779 LLVMBasicBlockRef merge_block;
6780 if (shader_count >= 2) {
6781 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6782 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6783 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6784
6785 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6786 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6787 LLVMConstInt(ctx.ac.i32, 8, false), false);
6788 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6789 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6790 thread_id, count, "");
6791 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6792
6793 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6794 }
6795
6796 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6797 handle_fs_inputs(&ctx, shaders[i]);
6798 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6799 handle_vs_inputs(&ctx, shaders[i]);
6800 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6801 prepare_gs_input_vgprs(&ctx);
6802
6803 nir_foreach_variable(variable, &shaders[i]->outputs)
6804 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6805
6806 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6807
6808 if (shader_count >= 2) {
6809 LLVMBuildBr(ctx.ac.builder, merge_block);
6810 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6811 }
6812
6813 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6814 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6815 shaders[i]->info.cull_distance_array_size > 4;
6816 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6817 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6818 shaders[i]->info.gs.vertices_out;
6819 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6820 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6821 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6822 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6823 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6824 }
6825 }
6826
6827 LLVMBuildRetVoid(ctx.builder);
6828
6829 ac_llvm_finalize_module(&ctx);
6830
6831 if (shader_count == 1)
6832 ac_nir_eliminate_const_vs_outputs(&ctx);
6833
6834 return ctx.module;
6835 }
6836
6837 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6838 {
6839 unsigned *retval = (unsigned *)context;
6840 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6841 char *description = LLVMGetDiagInfoDescription(di);
6842
6843 if (severity == LLVMDSError) {
6844 *retval = 1;
6845 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6846 description);
6847 }
6848
6849 LLVMDisposeMessage(description);
6850 }
6851
6852 static unsigned ac_llvm_compile(LLVMModuleRef M,
6853 struct ac_shader_binary *binary,
6854 LLVMTargetMachineRef tm)
6855 {
6856 unsigned retval = 0;
6857 char *err;
6858 LLVMContextRef llvm_ctx;
6859 LLVMMemoryBufferRef out_buffer;
6860 unsigned buffer_size;
6861 const char *buffer_data;
6862 LLVMBool mem_err;
6863
6864 /* Setup Diagnostic Handler*/
6865 llvm_ctx = LLVMGetModuleContext(M);
6866
6867 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6868 &retval);
6869
6870 /* Compile IR*/
6871 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6872 &err, &out_buffer);
6873
6874 /* Process Errors/Warnings */
6875 if (mem_err) {
6876 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6877 free(err);
6878 retval = 1;
6879 goto out;
6880 }
6881
6882 /* Extract Shader Code*/
6883 buffer_size = LLVMGetBufferSize(out_buffer);
6884 buffer_data = LLVMGetBufferStart(out_buffer);
6885
6886 ac_elf_read(buffer_data, buffer_size, binary);
6887
6888 /* Clean up */
6889 LLVMDisposeMemoryBuffer(out_buffer);
6890
6891 out:
6892 return retval;
6893 }
6894
6895 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6896 LLVMModuleRef llvm_module,
6897 struct ac_shader_binary *binary,
6898 struct ac_shader_config *config,
6899 struct ac_shader_variant_info *shader_info,
6900 gl_shader_stage stage,
6901 bool dump_shader, bool supports_spill)
6902 {
6903 if (dump_shader)
6904 ac_dump_module(llvm_module);
6905
6906 memset(binary, 0, sizeof(*binary));
6907 int v = ac_llvm_compile(llvm_module, binary, tm);
6908 if (v) {
6909 fprintf(stderr, "compile failed\n");
6910 }
6911
6912 if (dump_shader)
6913 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6914
6915 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6916
6917 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6918 LLVMDisposeModule(llvm_module);
6919 LLVMContextDispose(ctx);
6920
6921 if (stage == MESA_SHADER_FRAGMENT) {
6922 shader_info->num_input_vgprs = 0;
6923 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6924 shader_info->num_input_vgprs += 2;
6925 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6926 shader_info->num_input_vgprs += 2;
6927 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6928 shader_info->num_input_vgprs += 2;
6929 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6930 shader_info->num_input_vgprs += 3;
6931 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6932 shader_info->num_input_vgprs += 2;
6933 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6934 shader_info->num_input_vgprs += 2;
6935 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6936 shader_info->num_input_vgprs += 2;
6937 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6938 shader_info->num_input_vgprs += 1;
6939 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6940 shader_info->num_input_vgprs += 1;
6941 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6942 shader_info->num_input_vgprs += 1;
6943 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6944 shader_info->num_input_vgprs += 1;
6945 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6946 shader_info->num_input_vgprs += 1;
6947 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6948 shader_info->num_input_vgprs += 1;
6949 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6950 shader_info->num_input_vgprs += 1;
6951 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6952 shader_info->num_input_vgprs += 1;
6953 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6954 shader_info->num_input_vgprs += 1;
6955 }
6956 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6957
6958 /* +3 for scratch wave offset and VCC */
6959 config->num_sgprs = MAX2(config->num_sgprs,
6960 shader_info->num_input_sgprs + 3);
6961
6962 /* Enable 64-bit and 16-bit denormals, because there is no performance
6963 * cost.
6964 *
6965 * If denormals are enabled, all floating-point output modifiers are
6966 * ignored.
6967 *
6968 * Don't enable denormals for 32-bit floats, because:
6969 * - Floating-point output modifiers would be ignored by the hw.
6970 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6971 * have to stop using those.
6972 * - SI & CI would be very slow.
6973 */
6974 config->float_mode |= V_00B028_FP_64_DENORMS;
6975 }
6976
6977 static void
6978 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6979 {
6980 switch (nir->info.stage) {
6981 case MESA_SHADER_COMPUTE:
6982 for (int i = 0; i < 3; ++i)
6983 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6984 break;
6985 case MESA_SHADER_FRAGMENT:
6986 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6987 break;
6988 case MESA_SHADER_GEOMETRY:
6989 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6990 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6991 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6992 shader_info->gs.invocations = nir->info.gs.invocations;
6993 break;
6994 case MESA_SHADER_TESS_EVAL:
6995 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6996 shader_info->tes.spacing = nir->info.tess.spacing;
6997 shader_info->tes.ccw = nir->info.tess.ccw;
6998 shader_info->tes.point_mode = nir->info.tess.point_mode;
6999 shader_info->tes.as_es = options->key.tes.as_es;
7000 break;
7001 case MESA_SHADER_TESS_CTRL:
7002 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7003 break;
7004 case MESA_SHADER_VERTEX:
7005 shader_info->vs.as_es = options->key.vs.as_es;
7006 shader_info->vs.as_ls = options->key.vs.as_ls;
7007 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7008 if (options->key.vs.as_ls)
7009 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7010 break;
7011 default:
7012 break;
7013 }
7014 }
7015
7016 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7017 struct ac_shader_binary *binary,
7018 struct ac_shader_config *config,
7019 struct ac_shader_variant_info *shader_info,
7020 struct nir_shader *const *nir,
7021 int nir_count,
7022 const struct ac_nir_compiler_options *options,
7023 bool dump_shader)
7024 {
7025
7026 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7027 options);
7028
7029 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7030 for (int i = 0; i < nir_count; ++i)
7031 ac_fill_shader_info(shader_info, nir[i], options);
7032
7033 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7034 if (options->chip_class == GFX9) {
7035 if (nir_count == 2 &&
7036 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7037 shader_info->gs.es_type = nir[0]->info.stage;
7038 }
7039 }
7040 }
7041
7042 static void
7043 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7044 {
7045 LLVMValueRef args[9];
7046 args[0] = ctx->gsvs_ring;
7047 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7048 args[3] = ctx->ac.i32_0;
7049 args[4] = ctx->ac.i32_1; /* OFFEN */
7050 args[5] = ctx->ac.i32_0; /* IDXEN */
7051 args[6] = ctx->ac.i32_1; /* GLC */
7052 args[7] = ctx->ac.i32_1; /* SLC */
7053 args[8] = ctx->ac.i32_0; /* TFE */
7054
7055 int idx = 0;
7056
7057 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7058 int length = 4;
7059 int slot = idx;
7060 int slot_inc = 1;
7061 if (!(ctx->output_mask & (1ull << i)))
7062 continue;
7063
7064 if (i == VARYING_SLOT_CLIP_DIST0) {
7065 /* unpack clip and cull from a single set of slots */
7066 length = ctx->num_output_clips + ctx->num_output_culls;
7067 if (length > 4)
7068 slot_inc = 2;
7069 }
7070
7071 for (unsigned j = 0; j < length; j++) {
7072 LLVMValueRef value;
7073 args[2] = LLVMConstInt(ctx->ac.i32,
7074 (slot * 4 + j) *
7075 ctx->gs_max_out_vertices * 16 * 4, false);
7076
7077 value = ac_build_intrinsic(&ctx->ac,
7078 "llvm.SI.buffer.load.dword.i32.i32",
7079 ctx->ac.i32, args, 9,
7080 AC_FUNC_ATTR_READONLY |
7081 AC_FUNC_ATTR_LEGACY);
7082
7083 LLVMBuildStore(ctx->builder,
7084 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7085 }
7086 idx += slot_inc;
7087 }
7088 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7089 }
7090
7091 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7092 struct nir_shader *geom_shader,
7093 struct ac_shader_binary *binary,
7094 struct ac_shader_config *config,
7095 struct ac_shader_variant_info *shader_info,
7096 const struct ac_nir_compiler_options *options,
7097 bool dump_shader)
7098 {
7099 struct nir_to_llvm_context ctx = {0};
7100 ctx.context = LLVMContextCreate();
7101 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7102 ctx.options = options;
7103 ctx.shader_info = shader_info;
7104
7105 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7106 options->family);
7107 ctx.ac.module = ctx.module;
7108
7109 ctx.is_gs_copy_shader = true;
7110 LLVMSetTarget(ctx.module, "amdgcn--");
7111
7112 enum ac_float_mode float_mode =
7113 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7114 AC_FLOAT_MODE_DEFAULT;
7115
7116 ctx.builder = ac_create_builder(ctx.context, float_mode);
7117 ctx.ac.builder = ctx.builder;
7118 ctx.stage = MESA_SHADER_VERTEX;
7119
7120 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7121
7122 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7123 ac_setup_rings(&ctx);
7124
7125 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7126 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7127
7128 struct ac_nir_context nir_ctx = {};
7129 nir_ctx.ac = ctx.ac;
7130 nir_ctx.abi = &ctx.abi;
7131
7132 nir_ctx.nctx = &ctx;
7133 ctx.nir = &nir_ctx;
7134
7135 nir_foreach_variable(variable, &geom_shader->outputs) {
7136 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7137 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7138 }
7139
7140 ac_gs_copy_shader_emit(&ctx);
7141
7142 ctx.nir = NULL;
7143
7144 LLVMBuildRetVoid(ctx.builder);
7145
7146 ac_llvm_finalize_module(&ctx);
7147
7148 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7149 MESA_SHADER_VERTEX,
7150 dump_shader, options->supports_spill);
7151 }