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ac: remove unused i16 llvm type
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 LLVMTypeRef i64;
138 LLVMTypeRef v2i32;
139 LLVMTypeRef v3i32;
140 LLVMTypeRef v4i32;
141 LLVMTypeRef v8i32;
142 LLVMTypeRef f64;
143 LLVMTypeRef f32;
144 LLVMTypeRef f16;
145 LLVMTypeRef v2f32;
146 LLVMTypeRef v4f32;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
153
154 uint64_t input_mask;
155 uint64_t output_mask;
156 uint8_t num_output_clips;
157 uint8_t num_output_culls;
158
159 bool is_gs_copy_shader;
160 LLVMValueRef gs_next_vertex;
161 unsigned gs_max_out_vertices;
162
163 unsigned tes_primitive_mode;
164 uint64_t tess_outputs_written;
165 uint64_t tess_patch_outputs_written;
166 };
167
168 static inline struct nir_to_llvm_context *
169 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
170 {
171 struct nir_to_llvm_context *ctx = NULL;
172 return container_of(abi, ctx, abi);
173 }
174
175 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
176 const nir_deref_var *deref,
177 enum ac_descriptor_type desc_type,
178 const nir_tex_instr *instr,
179 bool image, bool write);
180
181 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
182 {
183 return (index * 4) + chan;
184 }
185
186 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
187 {
188 /* handle patch indices separate */
189 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
190 return 0;
191 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
192 return 1;
193 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
194 return 2 + (slot - VARYING_SLOT_PATCH0);
195
196 if (slot == VARYING_SLOT_POS)
197 return 0;
198 if (slot == VARYING_SLOT_PSIZ)
199 return 1;
200 if (slot == VARYING_SLOT_CLIP_DIST0)
201 return 2;
202 /* 3 is reserved for clip dist as well */
203 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
204 return 4 + (slot - VARYING_SLOT_VAR0);
205 unreachable("illegal slot in get unique index\n");
206 }
207
208 static void set_llvm_calling_convention(LLVMValueRef func,
209 gl_shader_stage stage)
210 {
211 enum radeon_llvm_calling_convention calling_conv;
212
213 switch (stage) {
214 case MESA_SHADER_VERTEX:
215 case MESA_SHADER_TESS_EVAL:
216 calling_conv = RADEON_LLVM_AMDGPU_VS;
217 break;
218 case MESA_SHADER_GEOMETRY:
219 calling_conv = RADEON_LLVM_AMDGPU_GS;
220 break;
221 case MESA_SHADER_TESS_CTRL:
222 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
223 break;
224 case MESA_SHADER_FRAGMENT:
225 calling_conv = RADEON_LLVM_AMDGPU_PS;
226 break;
227 case MESA_SHADER_COMPUTE:
228 calling_conv = RADEON_LLVM_AMDGPU_CS;
229 break;
230 default:
231 unreachable("Unhandle shader type");
232 }
233
234 LLVMSetFunctionCallConv(func, calling_conv);
235 }
236
237 #define MAX_ARGS 23
238 struct arg_info {
239 LLVMTypeRef types[MAX_ARGS];
240 LLVMValueRef *assign[MAX_ARGS];
241 unsigned array_params_mask;
242 uint8_t count;
243 uint8_t user_sgpr_count;
244 uint8_t sgpr_count;
245 uint8_t num_user_sgprs_used;
246 uint8_t num_sgprs_used;
247 uint8_t num_vgprs_used;
248 };
249
250 static inline void
251 add_argument(struct arg_info *info,
252 LLVMTypeRef type, LLVMValueRef *param_ptr)
253 {
254 assert(info->count < MAX_ARGS);
255 info->assign[info->count] = param_ptr;
256 info->types[info->count] = type;
257 info->count++;
258 }
259
260 static inline void
261 add_sgpr_argument(struct arg_info *info,
262 LLVMTypeRef type, LLVMValueRef *param_ptr)
263 {
264 add_argument(info, type, param_ptr);
265 info->num_sgprs_used += ac_get_type_size(type) / 4;
266 info->sgpr_count++;
267 }
268
269 static inline void
270 add_user_sgpr_argument(struct arg_info *info,
271 LLVMTypeRef type,
272 LLVMValueRef *param_ptr)
273 {
274 add_sgpr_argument(info, type, param_ptr);
275 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
276 info->user_sgpr_count++;
277 }
278
279 static inline void
280 add_vgpr_argument(struct arg_info *info,
281 LLVMTypeRef type,
282 LLVMValueRef *param_ptr)
283 {
284 add_argument(info, type, param_ptr);
285 info->num_vgprs_used += ac_get_type_size(type) / 4;
286 }
287
288 static inline void
289 add_user_sgpr_array_argument(struct arg_info *info,
290 LLVMTypeRef type,
291 LLVMValueRef *param_ptr)
292 {
293 info->array_params_mask |= (1 << info->count);
294 add_user_sgpr_argument(info, type, param_ptr);
295 }
296
297 static void assign_arguments(LLVMValueRef main_function,
298 struct arg_info *info)
299 {
300 unsigned i;
301 for (i = 0; i < info->count; i++) {
302 if (info->assign[i])
303 *info->assign[i] = LLVMGetParam(main_function, i);
304 }
305 }
306
307 static LLVMValueRef
308 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
309 LLVMBuilderRef builder, LLVMTypeRef *return_types,
310 unsigned num_return_elems,
311 struct arg_info *args,
312 unsigned max_workgroup_size,
313 bool unsafe_math)
314 {
315 LLVMTypeRef main_function_type, ret_type;
316 LLVMBasicBlockRef main_function_body;
317
318 if (num_return_elems)
319 ret_type = LLVMStructTypeInContext(ctx, return_types,
320 num_return_elems, true);
321 else
322 ret_type = LLVMVoidTypeInContext(ctx);
323
324 /* Setup the function */
325 main_function_type =
326 LLVMFunctionType(ret_type, args->types, args->count, 0);
327 LLVMValueRef main_function =
328 LLVMAddFunction(module, "main", main_function_type);
329 main_function_body =
330 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
331 LLVMPositionBuilderAtEnd(builder, main_function_body);
332
333 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
334 for (unsigned i = 0; i < args->sgpr_count; ++i) {
335 if (args->array_params_mask & (1 << i)) {
336 LLVMValueRef P = LLVMGetParam(main_function, i);
337 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
338 ac_add_attr_dereferenceable(P, UINT64_MAX);
339 }
340 else {
341 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
342 }
343 }
344
345 if (max_workgroup_size) {
346 ac_llvm_add_target_dep_function_attr(main_function,
347 "amdgpu-max-work-group-size",
348 max_workgroup_size);
349 }
350 if (unsafe_math) {
351 /* These were copied from some LLVM test. */
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "less-precise-fpmad",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "no-infs-fp-math",
357 "true");
358 LLVMAddTargetDependentFunctionAttr(main_function,
359 "no-nans-fp-math",
360 "true");
361 LLVMAddTargetDependentFunctionAttr(main_function,
362 "unsafe-fp-math",
363 "true");
364 }
365 return main_function;
366 }
367
368 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
369 {
370 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
371 CONST_ADDR_SPACE);
372 }
373
374 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
375 {
376 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
377 type = LLVMGetElementType(type);
378
379 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
380 return LLVMGetIntTypeWidth(type);
381
382 if (type == ctx->f16)
383 return 16;
384 if (type == ctx->f32)
385 return 32;
386 if (type == ctx->f64)
387 return 64;
388
389 unreachable("Unhandled type kind in get_elem_bits");
390 }
391
392 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
393 LLVMValueRef param, unsigned rshift,
394 unsigned bitwidth)
395 {
396 LLVMValueRef value = param;
397 if (rshift)
398 value = LLVMBuildLShr(ctx->builder, value,
399 LLVMConstInt(ctx->i32, rshift, false), "");
400
401 if (rshift + bitwidth < 32) {
402 unsigned mask = (1 << bitwidth) - 1;
403 value = LLVMBuildAnd(ctx->builder, value,
404 LLVMConstInt(ctx->i32, mask, false), "");
405 }
406 return value;
407 }
408
409 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
410 {
411 switch (ctx->stage) {
412 case MESA_SHADER_TESS_CTRL:
413 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
414 case MESA_SHADER_TESS_EVAL:
415 return ctx->tes_rel_patch_id;
416 break;
417 default:
418 unreachable("Illegal stage");
419 }
420 }
421
422 /* Tessellation shaders pass outputs to the next shader using LDS.
423 *
424 * LS outputs = TCS inputs
425 * TCS outputs = TES inputs
426 *
427 * The LDS layout is:
428 * - TCS inputs for patch 0
429 * - TCS inputs for patch 1
430 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
431 * - ...
432 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
433 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
434 * - TCS outputs for patch 1
435 * - Per-patch TCS outputs for patch 1
436 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
437 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
438 * - ...
439 *
440 * All three shaders VS(LS), TCS, TES share the same LDS space.
441 */
442 static LLVMValueRef
443 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
444 {
445 if (ctx->stage == MESA_SHADER_VERTEX)
446 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
447 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
448 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
449 else {
450 assert(0);
451 return NULL;
452 }
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
459 }
460
461 static LLVMValueRef
462 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
463 {
464 return LLVMBuildMul(ctx->builder,
465 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
466 LLVMConstInt(ctx->ac.i32, 4, false), "");
467 }
468
469 static LLVMValueRef
470 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
471 {
472 return LLVMBuildMul(ctx->builder,
473 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
474 LLVMConstInt(ctx->ac.i32, 4, false), "");
475 }
476
477 static LLVMValueRef
478 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
481 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
482
483 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
484 }
485
486 static LLVMValueRef
487 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
488 {
489 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
490 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
491 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
492
493 return LLVMBuildAdd(ctx->builder, patch0_offset,
494 LLVMBuildMul(ctx->builder, patch_stride,
495 rel_patch_id, ""),
496 "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_patch_data_offset =
503 get_tcs_out_patch0_patch_data_offset(ctx);
504 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
505 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
506
507 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
508 LLVMBuildMul(ctx->builder, patch_stride,
509 rel_patch_id, ""),
510 "");
511 }
512
513 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
514 {
515 ud_info->sgpr_idx = *sgpr_idx;
516 ud_info->num_sgprs = num_sgprs;
517 ud_info->indirect = false;
518 ud_info->indirect_offset = 0;
519 *sgpr_idx += num_sgprs;
520 }
521
522 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
523 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
524 {
525 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
526 }
527
528
529 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
530 uint32_t indirect_offset)
531 {
532 ud_info->sgpr_idx = sgpr_idx;
533 ud_info->num_sgprs = num_sgprs;
534 ud_info->indirect = true;
535 ud_info->indirect_offset = indirect_offset;
536 }
537
538 struct user_sgpr_info {
539 bool need_ring_offsets;
540 uint8_t sgpr_count;
541 bool indirect_all_descriptor_sets;
542 };
543
544 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (ctx->stage == MESA_SHADER_GEOMETRY ||
551 ctx->stage == MESA_SHADER_VERTEX ||
552 ctx->stage == MESA_SHADER_TESS_CTRL ||
553 ctx->stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (ctx->stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 switch (ctx->stage) {
567 case MESA_SHADER_COMPUTE:
568 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
569 break;
570 case MESA_SHADER_FRAGMENT:
571 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
572 break;
573 case MESA_SHADER_VERTEX:
574 if (!ctx->is_gs_copy_shader) {
575 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
576 if (ctx->shader_info->info.vs.needs_draw_id) {
577 user_sgpr_info->sgpr_count += 3;
578 } else {
579 user_sgpr_info->sgpr_count += 2;
580 }
581 }
582 if (ctx->options->key.vs.as_ls)
583 user_sgpr_info->sgpr_count++;
584 break;
585 case MESA_SHADER_TESS_CTRL:
586 user_sgpr_info->sgpr_count += 4;
587 break;
588 case MESA_SHADER_TESS_EVAL:
589 user_sgpr_info->sgpr_count += 1;
590 break;
591 case MESA_SHADER_GEOMETRY:
592 user_sgpr_info->sgpr_count += 2;
593 break;
594 default:
595 break;
596 }
597
598 if (ctx->shader_info->info.needs_push_constants)
599 user_sgpr_info->sgpr_count += 2;
600
601 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
602 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
603 user_sgpr_info->sgpr_count += 2;
604 user_sgpr_info->indirect_all_descriptor_sets = true;
605 } else {
606 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
607 }
608 }
609
610 static void
611 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
612 gl_shader_stage stage,
613 bool has_previous_stage,
614 gl_shader_stage previous_stage,
615 const struct user_sgpr_info *user_sgpr_info,
616 struct arg_info *args,
617 LLVMValueRef *desc_sets)
618 {
619 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
620 unsigned stage_mask = 1 << stage;
621 if (has_previous_stage)
622 stage_mask |= 1 << previous_stage;
623
624 /* 1 for each descriptor set */
625 if (!user_sgpr_info->indirect_all_descriptor_sets) {
626 for (unsigned i = 0; i < num_sets; ++i) {
627 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
628 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
629 }
630 }
631 } else
632 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
633
634 if (ctx->shader_info->info.needs_push_constants) {
635 /* 1 for push constants and dynamic descriptors */
636 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
637 }
638 }
639
640 static void
641 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
642 gl_shader_stage stage,
643 bool has_previous_stage,
644 gl_shader_stage previous_stage,
645 const struct user_sgpr_info *user_sgpr_info,
646 LLVMValueRef desc_sets,
647 uint8_t *user_sgpr_idx)
648 {
649 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
650 unsigned stage_mask = 1 << stage;
651 if (has_previous_stage)
652 stage_mask |= 1 << previous_stage;
653
654 if (!user_sgpr_info->indirect_all_descriptor_sets) {
655 for (unsigned i = 0; i < num_sets; ++i) {
656 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
657 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
658 } else
659 ctx->descriptor_sets[i] = NULL;
660 }
661 } else {
662 uint32_t desc_sgpr_idx = *user_sgpr_idx;
663 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
664
665 for (unsigned i = 0; i < num_sets; ++i) {
666 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
667 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
668 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
669
670 } else
671 ctx->descriptor_sets[i] = NULL;
672 }
673 ctx->shader_info->need_indirect_descriptor_sets = true;
674 }
675
676 if (ctx->shader_info->info.needs_push_constants) {
677 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
678 }
679 }
680
681 static void
682 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
683 gl_shader_stage stage,
684 bool has_previous_stage,
685 gl_shader_stage previous_stage,
686 struct arg_info *args)
687 {
688 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
689 if (ctx->shader_info->info.vs.has_vertex_buffers)
690 add_user_sgpr_argument(args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
691 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
692 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
693 if (ctx->shader_info->info.vs.needs_draw_id)
694 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
695 }
696 }
697
698 static void
699 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
700 gl_shader_stage stage,
701 bool has_previous_stage,
702 gl_shader_stage previous_stage,
703 uint8_t *user_sgpr_idx)
704 {
705 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
706 if (ctx->shader_info->info.vs.has_vertex_buffers) {
707 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
708 }
709 unsigned vs_num = 2;
710 if (ctx->shader_info->info.vs.needs_draw_id)
711 vs_num++;
712
713 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
714 }
715 }
716
717
718 static void create_function(struct nir_to_llvm_context *ctx,
719 gl_shader_stage stage,
720 bool has_previous_stage,
721 gl_shader_stage previous_stage)
722 {
723 uint8_t user_sgpr_idx;
724 struct user_sgpr_info user_sgpr_info;
725 struct arg_info args = {};
726 LLVMValueRef desc_sets;
727
728 allocate_user_sgprs(ctx, &user_sgpr_info);
729
730 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
731 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
732 }
733
734 switch (stage) {
735 case MESA_SHADER_COMPUTE:
736 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
737 if (ctx->shader_info->info.cs.grid_components_used)
738 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
739 add_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, 3), &ctx->workgroup_ids);
740 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
741 add_vgpr_argument(&args, LLVMVectorType(ctx->ac.i32, 3), &ctx->local_invocation_ids);
742 break;
743 case MESA_SHADER_VERTEX:
744 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
745 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
746 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
747 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
748 if (ctx->options->key.vs.as_es)
749 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
750 else if (ctx->options->key.vs.as_ls)
751 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
752 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
753 if (!ctx->is_gs_copy_shader) {
754 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
755 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
756 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
757 }
758 break;
759 case MESA_SHADER_TESS_CTRL:
760 if (has_previous_stage) {
761 // First 6 system regs
762 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
763 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
764 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
765
766 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
767 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
768 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
769
770 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
771 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
772 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
773
774 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
775 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
776 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
777 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
778 if (ctx->shader_info->info.needs_multiview_view_index)
779 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
780
781 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
782 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
783 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
784 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
785 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
786 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
787 } else {
788 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
789 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
791 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
792 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
793 if (ctx->shader_info->info.needs_multiview_view_index)
794 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
795 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
796 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
797 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
798 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
799 }
800 break;
801 case MESA_SHADER_TESS_EVAL:
802 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
803 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
804 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
805 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
806 if (ctx->options->key.tes.as_es) {
807 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
808 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
809 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
810 } else {
811 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
812 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
813 }
814 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
815 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
816 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
817 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
818 break;
819 case MESA_SHADER_GEOMETRY:
820 if (has_previous_stage) {
821 // First 6 system regs
822 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
823 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
824 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
825
826 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
827 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
828 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
829
830 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
831 if (previous_stage == MESA_SHADER_TESS_EVAL)
832 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
833 else
834 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
835 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
836 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
837 if (ctx->shader_info->info.needs_multiview_view_index)
838 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
839
840 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
841 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
842 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_prim_id); // prim id
843 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_invocation_id);
844 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
845
846 if (previous_stage == MESA_SHADER_VERTEX) {
847 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
848 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
849 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
850 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
851 } else {
852 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
853 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
854 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
856 }
857 } else {
858 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
859 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
860 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
861 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
862 if (ctx->shader_info->info.needs_multiview_view_index)
863 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
864 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
865 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
867 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
868 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_prim_id); // prim id
869 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
870 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
871 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
872 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
873 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_invocation_id);
874 }
875 break;
876 case MESA_SHADER_FRAGMENT:
877 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
878 if (ctx->shader_info->info.ps.needs_sample_positions)
879 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
880 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
881 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
882 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
883 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
884 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
885 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
886 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
887 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
888 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
889 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
890 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
891 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
892 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
893 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
894 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
895 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
896 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
897 break;
898 default:
899 unreachable("Shader stage not implemented");
900 }
901
902 ctx->main_function = create_llvm_function(
903 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
904 ctx->max_workgroup_size,
905 ctx->options->unsafe_math);
906 set_llvm_calling_convention(ctx->main_function, stage);
907
908
909 ctx->shader_info->num_input_vgprs = 0;
910 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
911
912 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
913
914 if (ctx->stage != MESA_SHADER_FRAGMENT)
915 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
916
917 assign_arguments(ctx->main_function, &args);
918
919 user_sgpr_idx = 0;
920
921 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
922 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
923 if (ctx->options->supports_spill) {
924 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
925 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
926 NULL, 0, AC_FUNC_ATTR_READNONE);
927 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
928 const_array(ctx->v4i32, 16), "");
929 }
930 }
931
932 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
933 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
934 if (has_previous_stage)
935 user_sgpr_idx = 0;
936
937 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
938
939 switch (stage) {
940 case MESA_SHADER_COMPUTE:
941 if (ctx->shader_info->info.cs.grid_components_used) {
942 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
943 }
944 break;
945 case MESA_SHADER_VERTEX:
946 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
947 if (ctx->view_index)
948 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
949 if (ctx->options->key.vs.as_ls) {
950 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
951 }
952 if (ctx->options->key.vs.as_ls)
953 ac_declare_lds_as_pointer(&ctx->ac);
954 break;
955 case MESA_SHADER_TESS_CTRL:
956 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
957 if (has_previous_stage)
958 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
959 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
960 if (ctx->view_index)
961 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
962 ac_declare_lds_as_pointer(&ctx->ac);
963 break;
964 case MESA_SHADER_TESS_EVAL:
965 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
966 if (ctx->view_index)
967 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
968 break;
969 case MESA_SHADER_GEOMETRY:
970 if (has_previous_stage) {
971 if (previous_stage == MESA_SHADER_VERTEX)
972 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
973 else
974 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
975 }
976 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
977 if (ctx->view_index)
978 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
979 if (has_previous_stage)
980 ac_declare_lds_as_pointer(&ctx->ac);
981 break;
982 case MESA_SHADER_FRAGMENT:
983 if (ctx->shader_info->info.ps.needs_sample_positions) {
984 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
985 }
986 break;
987 default:
988 unreachable("Shader stage not implemented");
989 }
990
991 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
992 }
993
994 static void setup_types(struct nir_to_llvm_context *ctx)
995 {
996 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
997 ctx->v2i32 = LLVMVectorType(ctx->ac.i32, 2);
998 ctx->v3i32 = LLVMVectorType(ctx->ac.i32, 3);
999 ctx->v4i32 = LLVMVectorType(ctx->ac.i32, 4);
1000 ctx->v8i32 = LLVMVectorType(ctx->ac.i32, 8);
1001 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
1002 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
1003 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
1004 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
1005 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
1006
1007 ctx->uniform_md_kind =
1008 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1009 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1010 }
1011
1012 static int get_llvm_num_components(LLVMValueRef value)
1013 {
1014 LLVMTypeRef type = LLVMTypeOf(value);
1015 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1016 ? LLVMGetVectorSize(type)
1017 : 1;
1018 return num_components;
1019 }
1020
1021 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1022 LLVMValueRef value,
1023 int index)
1024 {
1025 int count = get_llvm_num_components(value);
1026
1027 if (count == 1)
1028 return value;
1029
1030 return LLVMBuildExtractElement(ac->builder, value,
1031 LLVMConstInt(ac->i32, index, false), "");
1032 }
1033
1034 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1035 LLVMValueRef value, unsigned count)
1036 {
1037 unsigned num_components = get_llvm_num_components(value);
1038 if (count == num_components)
1039 return value;
1040
1041 LLVMValueRef masks[] = {
1042 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1043 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1044
1045 if (count == 1)
1046 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1047 "");
1048
1049 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1050 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1051 }
1052
1053 static void
1054 build_store_values_extended(struct ac_llvm_context *ac,
1055 LLVMValueRef *values,
1056 unsigned value_count,
1057 unsigned value_stride,
1058 LLVMValueRef vec)
1059 {
1060 LLVMBuilderRef builder = ac->builder;
1061 unsigned i;
1062
1063 for (i = 0; i < value_count; i++) {
1064 LLVMValueRef ptr = values[i * value_stride];
1065 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1066 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1067 LLVMBuildStore(builder, value, ptr);
1068 }
1069 }
1070
1071 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1072 const nir_ssa_def *def)
1073 {
1074 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1075 if (def->num_components > 1) {
1076 type = LLVMVectorType(type, def->num_components);
1077 }
1078 return type;
1079 }
1080
1081 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1082 {
1083 assert(src.is_ssa);
1084 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1085 return (LLVMValueRef)entry->data;
1086 }
1087
1088
1089 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1090 const struct nir_block *b)
1091 {
1092 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1093 return (LLVMBasicBlockRef)entry->data;
1094 }
1095
1096 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1097 nir_alu_src src,
1098 unsigned num_components)
1099 {
1100 LLVMValueRef value = get_src(ctx, src.src);
1101 bool need_swizzle = false;
1102
1103 assert(value);
1104 LLVMTypeRef type = LLVMTypeOf(value);
1105 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1106 ? LLVMGetVectorSize(type)
1107 : 1;
1108
1109 for (unsigned i = 0; i < num_components; ++i) {
1110 assert(src.swizzle[i] < src_components);
1111 if (src.swizzle[i] != i)
1112 need_swizzle = true;
1113 }
1114
1115 if (need_swizzle || num_components != src_components) {
1116 LLVMValueRef masks[] = {
1117 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1118 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1119 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1120 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1121
1122 if (src_components > 1 && num_components == 1) {
1123 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1124 masks[0], "");
1125 } else if (src_components == 1 && num_components > 1) {
1126 LLVMValueRef values[] = {value, value, value, value};
1127 value = ac_build_gather_values(&ctx->ac, values, num_components);
1128 } else {
1129 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1130 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1131 swizzle, "");
1132 }
1133 }
1134 assert(!src.negate);
1135 assert(!src.abs);
1136 return value;
1137 }
1138
1139 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1140 LLVMIntPredicate pred, LLVMValueRef src0,
1141 LLVMValueRef src1)
1142 {
1143 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1144 return LLVMBuildSelect(ctx->builder, result,
1145 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1146 LLVMConstInt(ctx->i32, 0, false), "");
1147 }
1148
1149 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1150 LLVMRealPredicate pred, LLVMValueRef src0,
1151 LLVMValueRef src1)
1152 {
1153 LLVMValueRef result;
1154 src0 = ac_to_float(ctx, src0);
1155 src1 = ac_to_float(ctx, src1);
1156 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1157 return LLVMBuildSelect(ctx->builder, result,
1158 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1159 LLVMConstInt(ctx->i32, 0, false), "");
1160 }
1161
1162 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1163 const char *intrin,
1164 LLVMTypeRef result_type,
1165 LLVMValueRef src0)
1166 {
1167 char name[64];
1168 LLVMValueRef params[] = {
1169 ac_to_float(ctx, src0),
1170 };
1171
1172 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1173 get_elem_bits(ctx, result_type));
1174 assert(length < sizeof(name));
1175 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1176 }
1177
1178 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1179 const char *intrin,
1180 LLVMTypeRef result_type,
1181 LLVMValueRef src0, LLVMValueRef src1)
1182 {
1183 char name[64];
1184 LLVMValueRef params[] = {
1185 ac_to_float(ctx, src0),
1186 ac_to_float(ctx, src1),
1187 };
1188
1189 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1190 get_elem_bits(ctx, result_type));
1191 assert(length < sizeof(name));
1192 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1193 }
1194
1195 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1196 const char *intrin,
1197 LLVMTypeRef result_type,
1198 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1199 {
1200 char name[64];
1201 LLVMValueRef params[] = {
1202 ac_to_float(ctx, src0),
1203 ac_to_float(ctx, src1),
1204 ac_to_float(ctx, src2),
1205 };
1206
1207 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1208 get_elem_bits(ctx, result_type));
1209 assert(length < sizeof(name));
1210 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1211 }
1212
1213 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1214 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1215 {
1216 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1217 ctx->i32_0, "");
1218 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1219 }
1220
1221 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1222 LLVMIntPredicate pred,
1223 LLVMValueRef src0, LLVMValueRef src1)
1224 {
1225 return LLVMBuildSelect(ctx->builder,
1226 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1227 src0,
1228 src1, "");
1229
1230 }
1231 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1235 LLVMBuildNeg(ctx->builder, src0, ""));
1236 }
1237
1238 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1239 LLVMValueRef src0)
1240 {
1241 LLVMValueRef cmp, val;
1242
1243 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1244 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1245 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1246 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1247 return val;
1248 }
1249
1250 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1251 LLVMValueRef src0)
1252 {
1253 LLVMValueRef cmp, val;
1254
1255 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1256 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1257 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1258 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1259 return val;
1260 }
1261
1262 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1263 LLVMValueRef src0)
1264 {
1265 const char *intr = "llvm.floor.f32";
1266 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1267 LLVMValueRef params[] = {
1268 fsrc0,
1269 };
1270 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1271 ctx->f32, params, 1,
1272 AC_FUNC_ATTR_READNONE);
1273 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1274 }
1275
1276 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1277 const char *intrin,
1278 LLVMValueRef src0, LLVMValueRef src1)
1279 {
1280 LLVMTypeRef ret_type;
1281 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1282 LLVMValueRef res;
1283 LLVMValueRef params[] = { src0, src1 };
1284 ret_type = LLVMStructTypeInContext(ctx->context, types,
1285 2, true);
1286
1287 res = ac_build_intrinsic(ctx, intrin, ret_type,
1288 params, 2, AC_FUNC_ATTR_READNONE);
1289
1290 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1291 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1292 return res;
1293 }
1294
1295 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1296 LLVMValueRef src0)
1297 {
1298 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1299 }
1300
1301 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1302 LLVMValueRef src0)
1303 {
1304 src0 = ac_to_float(ctx, src0);
1305 return LLVMBuildSExt(ctx->builder,
1306 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1307 ctx->i32, "");
1308 }
1309
1310 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1311 LLVMValueRef src0)
1312 {
1313 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1314 }
1315
1316 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1317 LLVMValueRef src0)
1318 {
1319 return LLVMBuildSExt(ctx->builder,
1320 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1321 ctx->i32, "");
1322 }
1323
1324 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 LLVMValueRef result;
1328 LLVMValueRef cond = NULL;
1329
1330 src0 = ac_to_float(&ctx->ac, src0);
1331 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1332
1333 if (ctx->options->chip_class >= VI) {
1334 LLVMValueRef args[2];
1335 /* Check if the result is a denormal - and flush to 0 if so. */
1336 args[0] = result;
1337 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1338 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1339 }
1340
1341 /* need to convert back up to f32 */
1342 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1343
1344 if (ctx->options->chip_class >= VI)
1345 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1346 else {
1347 /* for SI/CIK */
1348 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1349 * so compare the result and flush to 0 if it's smaller.
1350 */
1351 LLVMValueRef temp, cond2;
1352 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1353 ctx->f32, result);
1354 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1355 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->f32, ""),
1356 temp, "");
1357 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1358 temp, ctx->ac.f32_0, "");
1359 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1360 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1361 }
1362 return result;
1363 }
1364
1365 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1366 LLVMValueRef src0, LLVMValueRef src1)
1367 {
1368 LLVMValueRef dst64, result;
1369 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1370 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1371
1372 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1373 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1374 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1375 return result;
1376 }
1377
1378 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1379 LLVMValueRef src0, LLVMValueRef src1)
1380 {
1381 LLVMValueRef dst64, result;
1382 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1383 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1384
1385 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1386 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1387 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1388 return result;
1389 }
1390
1391 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1392 bool is_signed,
1393 const LLVMValueRef srcs[3])
1394 {
1395 LLVMValueRef result;
1396 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1397
1398 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1399 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1400 return result;
1401 }
1402
1403 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0, LLVMValueRef src1,
1405 LLVMValueRef src2, LLVMValueRef src3)
1406 {
1407 LLVMValueRef bfi_args[3], result;
1408
1409 bfi_args[0] = LLVMBuildShl(ctx->builder,
1410 LLVMBuildSub(ctx->builder,
1411 LLVMBuildShl(ctx->builder,
1412 ctx->i32_1,
1413 src3, ""),
1414 ctx->i32_1, ""),
1415 src2, "");
1416 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1417 bfi_args[2] = src0;
1418
1419 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1420
1421 /* Calculate:
1422 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1423 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1424 */
1425 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1426 LLVMBuildAnd(ctx->builder, bfi_args[0],
1427 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1428
1429 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1430 return result;
1431 }
1432
1433 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1437 int i;
1438 LLVMValueRef comp[2];
1439
1440 src0 = ac_to_float(ctx, src0);
1441 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1442 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1443 for (i = 0; i < 2; i++) {
1444 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1445 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1446 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1447 }
1448
1449 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1450 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1451
1452 return comp[0];
1453 }
1454
1455 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1456 LLVMValueRef src0)
1457 {
1458 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1459 LLVMValueRef temps[2], result, val;
1460 int i;
1461
1462 for (i = 0; i < 2; i++) {
1463 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1464 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1465 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1466 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1467 }
1468
1469 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1470 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1471 ctx->i32_0, "");
1472 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1473 ctx->i32_1, "");
1474 return result;
1475 }
1476
1477 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1478 nir_op op,
1479 LLVMValueRef src0)
1480 {
1481 unsigned mask;
1482 int idx;
1483 LLVMValueRef result;
1484
1485 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1486 mask = AC_TID_MASK_LEFT;
1487 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1488 mask = AC_TID_MASK_TOP;
1489 else
1490 mask = AC_TID_MASK_TOP_LEFT;
1491
1492 /* for DDX we want to next X pixel, DDY next Y pixel. */
1493 if (op == nir_op_fddx_fine ||
1494 op == nir_op_fddx_coarse ||
1495 op == nir_op_fddx)
1496 idx = 1;
1497 else
1498 idx = 2;
1499
1500 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1501 return result;
1502 }
1503
1504 /*
1505 * this takes an I,J coordinate pair,
1506 * and works out the X and Y derivatives.
1507 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1508 */
1509 static LLVMValueRef emit_ddxy_interp(
1510 struct ac_nir_context *ctx,
1511 LLVMValueRef interp_ij)
1512 {
1513 LLVMValueRef result[4], a;
1514 unsigned i;
1515
1516 for (i = 0; i < 2; i++) {
1517 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1518 LLVMConstInt(ctx->ac.i32, i, false), "");
1519 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1520 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1521 }
1522 return ac_build_gather_values(&ctx->ac, result, 4);
1523 }
1524
1525 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1526 {
1527 LLVMValueRef src[4], result = NULL;
1528 unsigned num_components = instr->dest.dest.ssa.num_components;
1529 unsigned src_components;
1530 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1531
1532 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1533 switch (instr->op) {
1534 case nir_op_vec2:
1535 case nir_op_vec3:
1536 case nir_op_vec4:
1537 src_components = 1;
1538 break;
1539 case nir_op_pack_half_2x16:
1540 src_components = 2;
1541 break;
1542 case nir_op_unpack_half_2x16:
1543 src_components = 1;
1544 break;
1545 default:
1546 src_components = num_components;
1547 break;
1548 }
1549 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1550 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1551
1552 switch (instr->op) {
1553 case nir_op_fmov:
1554 case nir_op_imov:
1555 result = src[0];
1556 break;
1557 case nir_op_fneg:
1558 src[0] = ac_to_float(&ctx->ac, src[0]);
1559 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1560 break;
1561 case nir_op_ineg:
1562 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1563 break;
1564 case nir_op_inot:
1565 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1566 break;
1567 case nir_op_iadd:
1568 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_fadd:
1571 src[0] = ac_to_float(&ctx->ac, src[0]);
1572 src[1] = ac_to_float(&ctx->ac, src[1]);
1573 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_fsub:
1576 src[0] = ac_to_float(&ctx->ac, src[0]);
1577 src[1] = ac_to_float(&ctx->ac, src[1]);
1578 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1579 break;
1580 case nir_op_isub:
1581 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1582 break;
1583 case nir_op_imul:
1584 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1585 break;
1586 case nir_op_imod:
1587 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1588 break;
1589 case nir_op_umod:
1590 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1591 break;
1592 case nir_op_fmod:
1593 src[0] = ac_to_float(&ctx->ac, src[0]);
1594 src[1] = ac_to_float(&ctx->ac, src[1]);
1595 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1596 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1597 ac_to_float_type(&ctx->ac, def_type), result);
1598 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1599 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1600 break;
1601 case nir_op_frem:
1602 src[0] = ac_to_float(&ctx->ac, src[0]);
1603 src[1] = ac_to_float(&ctx->ac, src[1]);
1604 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_irem:
1607 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1608 break;
1609 case nir_op_idiv:
1610 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1611 break;
1612 case nir_op_udiv:
1613 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1614 break;
1615 case nir_op_fmul:
1616 src[0] = ac_to_float(&ctx->ac, src[0]);
1617 src[1] = ac_to_float(&ctx->ac, src[1]);
1618 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1619 break;
1620 case nir_op_fdiv:
1621 src[0] = ac_to_float(&ctx->ac, src[0]);
1622 src[1] = ac_to_float(&ctx->ac, src[1]);
1623 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1624 break;
1625 case nir_op_frcp:
1626 src[0] = ac_to_float(&ctx->ac, src[0]);
1627 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1628 break;
1629 case nir_op_iand:
1630 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1631 break;
1632 case nir_op_ior:
1633 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1634 break;
1635 case nir_op_ixor:
1636 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1637 break;
1638 case nir_op_ishl:
1639 result = LLVMBuildShl(ctx->ac.builder, src[0],
1640 LLVMBuildZExt(ctx->ac.builder, src[1],
1641 LLVMTypeOf(src[0]), ""),
1642 "");
1643 break;
1644 case nir_op_ishr:
1645 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1646 LLVMBuildZExt(ctx->ac.builder, src[1],
1647 LLVMTypeOf(src[0]), ""),
1648 "");
1649 break;
1650 case nir_op_ushr:
1651 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1652 LLVMBuildZExt(ctx->ac.builder, src[1],
1653 LLVMTypeOf(src[0]), ""),
1654 "");
1655 break;
1656 case nir_op_ilt:
1657 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1658 break;
1659 case nir_op_ine:
1660 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1661 break;
1662 case nir_op_ieq:
1663 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1664 break;
1665 case nir_op_ige:
1666 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1667 break;
1668 case nir_op_ult:
1669 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1670 break;
1671 case nir_op_uge:
1672 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1673 break;
1674 case nir_op_feq:
1675 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1676 break;
1677 case nir_op_fne:
1678 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1679 break;
1680 case nir_op_flt:
1681 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1682 break;
1683 case nir_op_fge:
1684 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1685 break;
1686 case nir_op_fabs:
1687 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1688 ac_to_float_type(&ctx->ac, def_type), src[0]);
1689 break;
1690 case nir_op_iabs:
1691 result = emit_iabs(&ctx->ac, src[0]);
1692 break;
1693 case nir_op_imax:
1694 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1695 break;
1696 case nir_op_imin:
1697 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1698 break;
1699 case nir_op_umax:
1700 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1701 break;
1702 case nir_op_umin:
1703 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1704 break;
1705 case nir_op_isign:
1706 result = emit_isign(&ctx->ac, src[0]);
1707 break;
1708 case nir_op_fsign:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 result = emit_fsign(&ctx->ac, src[0]);
1711 break;
1712 case nir_op_ffloor:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1714 ac_to_float_type(&ctx->ac, def_type), src[0]);
1715 break;
1716 case nir_op_ftrunc:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1718 ac_to_float_type(&ctx->ac, def_type), src[0]);
1719 break;
1720 case nir_op_fceil:
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1722 ac_to_float_type(&ctx->ac, def_type), src[0]);
1723 break;
1724 case nir_op_fround_even:
1725 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1726 ac_to_float_type(&ctx->ac, def_type),src[0]);
1727 break;
1728 case nir_op_ffract:
1729 result = emit_ffract(&ctx->ac, src[0]);
1730 break;
1731 case nir_op_fsin:
1732 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1733 ac_to_float_type(&ctx->ac, def_type), src[0]);
1734 break;
1735 case nir_op_fcos:
1736 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1737 ac_to_float_type(&ctx->ac, def_type), src[0]);
1738 break;
1739 case nir_op_fsqrt:
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1741 ac_to_float_type(&ctx->ac, def_type), src[0]);
1742 break;
1743 case nir_op_fexp2:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1745 ac_to_float_type(&ctx->ac, def_type), src[0]);
1746 break;
1747 case nir_op_flog2:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_frsq:
1752 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1753 ac_to_float_type(&ctx->ac, def_type), src[0]);
1754 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1755 break;
1756 case nir_op_fpow:
1757 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1758 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1759 break;
1760 case nir_op_fmax:
1761 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1762 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1763 if (instr->dest.dest.ssa.bit_size == 32)
1764 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1765 ac_to_float_type(&ctx->ac, def_type),
1766 result);
1767 break;
1768 case nir_op_fmin:
1769 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1770 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1771 if (instr->dest.dest.ssa.bit_size == 32)
1772 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1773 ac_to_float_type(&ctx->ac, def_type),
1774 result);
1775 break;
1776 case nir_op_ffma:
1777 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1778 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1779 break;
1780 case nir_op_ibitfield_extract:
1781 result = emit_bitfield_extract(&ctx->ac, true, src);
1782 break;
1783 case nir_op_ubitfield_extract:
1784 result = emit_bitfield_extract(&ctx->ac, false, src);
1785 break;
1786 case nir_op_bitfield_insert:
1787 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1788 break;
1789 case nir_op_bitfield_reverse:
1790 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1791 break;
1792 case nir_op_bit_count:
1793 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1794 break;
1795 case nir_op_vec2:
1796 case nir_op_vec3:
1797 case nir_op_vec4:
1798 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1799 src[i] = ac_to_integer(&ctx->ac, src[i]);
1800 result = ac_build_gather_values(&ctx->ac, src, num_components);
1801 break;
1802 case nir_op_f2i32:
1803 case nir_op_f2i64:
1804 src[0] = ac_to_float(&ctx->ac, src[0]);
1805 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1806 break;
1807 case nir_op_f2u32:
1808 case nir_op_f2u64:
1809 src[0] = ac_to_float(&ctx->ac, src[0]);
1810 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1811 break;
1812 case nir_op_i2f32:
1813 case nir_op_i2f64:
1814 src[0] = ac_to_integer(&ctx->ac, src[0]);
1815 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1816 break;
1817 case nir_op_u2f32:
1818 case nir_op_u2f64:
1819 src[0] = ac_to_integer(&ctx->ac, src[0]);
1820 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1821 break;
1822 case nir_op_f2f64:
1823 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1824 break;
1825 case nir_op_f2f32:
1826 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1827 break;
1828 case nir_op_u2u32:
1829 case nir_op_u2u64:
1830 src[0] = ac_to_integer(&ctx->ac, src[0]);
1831 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1832 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1833 else
1834 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1835 break;
1836 case nir_op_i2i32:
1837 case nir_op_i2i64:
1838 src[0] = ac_to_integer(&ctx->ac, src[0]);
1839 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1840 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1841 else
1842 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1843 break;
1844 case nir_op_bcsel:
1845 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1846 break;
1847 case nir_op_find_lsb:
1848 src[0] = ac_to_integer(&ctx->ac, src[0]);
1849 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1850 break;
1851 case nir_op_ufind_msb:
1852 src[0] = ac_to_integer(&ctx->ac, src[0]);
1853 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1854 break;
1855 case nir_op_ifind_msb:
1856 src[0] = ac_to_integer(&ctx->ac, src[0]);
1857 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1858 break;
1859 case nir_op_uadd_carry:
1860 src[0] = ac_to_integer(&ctx->ac, src[0]);
1861 src[1] = ac_to_integer(&ctx->ac, src[1]);
1862 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1863 break;
1864 case nir_op_usub_borrow:
1865 src[0] = ac_to_integer(&ctx->ac, src[0]);
1866 src[1] = ac_to_integer(&ctx->ac, src[1]);
1867 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1868 break;
1869 case nir_op_b2f:
1870 result = emit_b2f(&ctx->ac, src[0]);
1871 break;
1872 case nir_op_f2b:
1873 result = emit_f2b(&ctx->ac, src[0]);
1874 break;
1875 case nir_op_b2i:
1876 result = emit_b2i(&ctx->ac, src[0]);
1877 break;
1878 case nir_op_i2b:
1879 src[0] = ac_to_integer(&ctx->ac, src[0]);
1880 result = emit_i2b(&ctx->ac, src[0]);
1881 break;
1882 case nir_op_fquantize2f16:
1883 result = emit_f2f16(ctx->nctx, src[0]);
1884 break;
1885 case nir_op_umul_high:
1886 src[0] = ac_to_integer(&ctx->ac, src[0]);
1887 src[1] = ac_to_integer(&ctx->ac, src[1]);
1888 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1889 break;
1890 case nir_op_imul_high:
1891 src[0] = ac_to_integer(&ctx->ac, src[0]);
1892 src[1] = ac_to_integer(&ctx->ac, src[1]);
1893 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1894 break;
1895 case nir_op_pack_half_2x16:
1896 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1897 break;
1898 case nir_op_unpack_half_2x16:
1899 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1900 break;
1901 case nir_op_fddx:
1902 case nir_op_fddy:
1903 case nir_op_fddx_fine:
1904 case nir_op_fddy_fine:
1905 case nir_op_fddx_coarse:
1906 case nir_op_fddy_coarse:
1907 result = emit_ddxy(ctx, instr->op, src[0]);
1908 break;
1909
1910 case nir_op_unpack_64_2x32_split_x: {
1911 assert(instr->src[0].src.ssa->num_components == 1);
1912 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1913 LLVMVectorType(ctx->ac.i32, 2),
1914 "");
1915 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1916 ctx->ac.i32_0, "");
1917 break;
1918 }
1919
1920 case nir_op_unpack_64_2x32_split_y: {
1921 assert(instr->src[0].src.ssa->num_components == 1);
1922 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1923 LLVMVectorType(ctx->ac.i32, 2),
1924 "");
1925 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1926 ctx->ac.i32_1, "");
1927 break;
1928 }
1929
1930 case nir_op_pack_64_2x32_split: {
1931 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1932 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1933 src[0], ctx->ac.i32_0, "");
1934 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1935 src[1], ctx->ac.i32_1, "");
1936 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1937 break;
1938 }
1939
1940 default:
1941 fprintf(stderr, "Unknown NIR alu instr: ");
1942 nir_print_instr(&instr->instr, stderr);
1943 fprintf(stderr, "\n");
1944 abort();
1945 }
1946
1947 if (result) {
1948 assert(instr->dest.dest.is_ssa);
1949 result = ac_to_integer(&ctx->ac, result);
1950 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1951 result);
1952 }
1953 }
1954
1955 static void visit_load_const(struct ac_nir_context *ctx,
1956 const nir_load_const_instr *instr)
1957 {
1958 LLVMValueRef values[4], value = NULL;
1959 LLVMTypeRef element_type =
1960 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1961
1962 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1963 switch (instr->def.bit_size) {
1964 case 32:
1965 values[i] = LLVMConstInt(element_type,
1966 instr->value.u32[i], false);
1967 break;
1968 case 64:
1969 values[i] = LLVMConstInt(element_type,
1970 instr->value.u64[i], false);
1971 break;
1972 default:
1973 fprintf(stderr,
1974 "unsupported nir load_const bit_size: %d\n",
1975 instr->def.bit_size);
1976 abort();
1977 }
1978 }
1979 if (instr->def.num_components > 1) {
1980 value = LLVMConstVector(values, instr->def.num_components);
1981 } else
1982 value = values[0];
1983
1984 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1985 }
1986
1987 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1988 LLVMTypeRef type)
1989 {
1990 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1991 return LLVMBuildBitCast(ctx->builder, ptr,
1992 LLVMPointerType(type, addr_space), "");
1993 }
1994
1995 static LLVMValueRef
1996 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1997 {
1998 LLVMValueRef size =
1999 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2000 LLVMConstInt(ctx->ac.i32, 2, false), "");
2001
2002 /* VI only */
2003 if (ctx->ac.chip_class == VI && in_elements) {
2004 /* On VI, the descriptor contains the size in bytes,
2005 * but TXQ must return the size in elements.
2006 * The stride is always non-zero for resources using TXQ.
2007 */
2008 LLVMValueRef stride =
2009 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2010 LLVMConstInt(ctx->ac.i32, 1, false), "");
2011 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2012 LLVMConstInt(ctx->ac.i32, 16, false), "");
2013 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2014 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2015
2016 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2017 }
2018 return size;
2019 }
2020
2021 /**
2022 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2023 * intrinsic names).
2024 */
2025 static void build_int_type_name(
2026 LLVMTypeRef type,
2027 char *buf, unsigned bufsize)
2028 {
2029 assert(bufsize >= 6);
2030
2031 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2032 snprintf(buf, bufsize, "v%ui32",
2033 LLVMGetVectorSize(type));
2034 else
2035 strcpy(buf, "i32");
2036 }
2037
2038 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2039 struct ac_image_args *args,
2040 const nir_tex_instr *instr)
2041 {
2042 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2043 LLVMValueRef coord = args->addr;
2044 LLVMValueRef half_texel[2];
2045 LLVMValueRef compare_cube_wa = NULL;
2046 LLVMValueRef result;
2047 int c;
2048 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2049
2050 //TODO Rect
2051 {
2052 struct ac_image_args txq_args = { 0 };
2053
2054 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2055 txq_args.opcode = ac_image_get_resinfo;
2056 txq_args.dmask = 0xf;
2057 txq_args.addr = ctx->i32_0;
2058 txq_args.resource = args->resource;
2059 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2060
2061 for (c = 0; c < 2; c++) {
2062 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2063 LLVMConstInt(ctx->i32, c, false), "");
2064 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2065 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2066 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2067 LLVMConstReal(ctx->f32, -0.5), "");
2068 }
2069 }
2070
2071 LLVMValueRef orig_coords = args->addr;
2072
2073 for (c = 0; c < 2; c++) {
2074 LLVMValueRef tmp;
2075 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2076 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2077 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2078 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2079 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2080 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2081 }
2082
2083
2084 /*
2085 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2086 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2087 * workaround by sampling using a scaled type and converting.
2088 * This is taken from amdgpu-pro shaders.
2089 */
2090 /* NOTE this produces some ugly code compared to amdgpu-pro,
2091 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2092 * and then reads them back. -pro generates two selects,
2093 * one s_cmp for the descriptor rewriting
2094 * one v_cmp for the coordinate and result changes.
2095 */
2096 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2097 LLVMValueRef tmp, tmp2;
2098
2099 /* workaround 8/8/8/8 uint/sint cube gather bug */
2100 /* first detect it then change to a scaled read and f2i */
2101 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2102 tmp2 = tmp;
2103
2104 /* extract the DATA_FORMAT */
2105 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2106 LLVMConstInt(ctx->i32, 6, false), false);
2107
2108 /* is the DATA_FORMAT == 8_8_8_8 */
2109 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2110
2111 if (stype == GLSL_TYPE_UINT)
2112 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2113 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2114 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2115 else
2116 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2117 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2118 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2119
2120 /* replace the NUM FORMAT in the descriptor */
2121 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2122 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2123
2124 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2125
2126 /* don't modify the coordinates for this case */
2127 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2128 }
2129 args->addr = coord;
2130 result = ac_build_image_opcode(ctx, args);
2131
2132 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2133 LLVMValueRef tmp, tmp2;
2134
2135 /* if the cube workaround is in place, f2i the result. */
2136 for (c = 0; c < 4; c++) {
2137 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2138 if (stype == GLSL_TYPE_UINT)
2139 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2140 else
2141 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2142 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2143 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2144 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2145 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2146 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2147 }
2148 }
2149 return result;
2150 }
2151
2152 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2153 const nir_tex_instr *instr,
2154 bool lod_is_zero,
2155 struct ac_image_args *args)
2156 {
2157 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2158 return ac_build_buffer_load_format(&ctx->ac,
2159 args->resource,
2160 args->addr,
2161 LLVMConstInt(ctx->ac.i32, 0, false),
2162 true);
2163 }
2164
2165 args->opcode = ac_image_sample;
2166 args->compare = instr->is_shadow;
2167
2168 switch (instr->op) {
2169 case nir_texop_txf:
2170 case nir_texop_txf_ms:
2171 case nir_texop_samples_identical:
2172 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2173 args->compare = false;
2174 args->offset = false;
2175 break;
2176 case nir_texop_txb:
2177 args->bias = true;
2178 break;
2179 case nir_texop_txl:
2180 if (lod_is_zero)
2181 args->level_zero = true;
2182 else
2183 args->lod = true;
2184 break;
2185 case nir_texop_txs:
2186 case nir_texop_query_levels:
2187 args->opcode = ac_image_get_resinfo;
2188 break;
2189 case nir_texop_tex:
2190 if (ctx->stage != MESA_SHADER_FRAGMENT)
2191 args->level_zero = true;
2192 break;
2193 case nir_texop_txd:
2194 args->deriv = true;
2195 break;
2196 case nir_texop_tg4:
2197 args->opcode = ac_image_gather4;
2198 args->level_zero = true;
2199 break;
2200 case nir_texop_lod:
2201 args->opcode = ac_image_get_lod;
2202 args->compare = false;
2203 args->offset = false;
2204 break;
2205 default:
2206 break;
2207 }
2208
2209 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2210 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2211 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2212 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2213 }
2214 }
2215 return ac_build_image_opcode(&ctx->ac, args);
2216 }
2217
2218 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2219 nir_intrinsic_instr *instr)
2220 {
2221 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2222 unsigned desc_set = nir_intrinsic_desc_set(instr);
2223 unsigned binding = nir_intrinsic_binding(instr);
2224 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2225 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2226 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2227 unsigned base_offset = layout->binding[binding].offset;
2228 LLVMValueRef offset, stride;
2229
2230 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2231 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2232 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2233 layout->binding[binding].dynamic_offset_offset;
2234 desc_ptr = ctx->push_constants;
2235 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2236 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2237 } else
2238 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2239
2240 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2241 index = LLVMBuildMul(ctx->builder, index, stride, "");
2242 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2243
2244 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2245 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2246 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2247
2248 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2249 }
2250
2251 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2252 nir_intrinsic_instr *instr)
2253 {
2254 LLVMValueRef ptr, addr;
2255
2256 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2257 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2258
2259 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2260 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2261
2262 return LLVMBuildLoad(ctx->builder, ptr, "");
2263 }
2264
2265 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2266 const nir_intrinsic_instr *instr)
2267 {
2268 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2269
2270 return get_buffer_size(ctx, desc, false);
2271 }
2272 static void visit_store_ssbo(struct ac_nir_context *ctx,
2273 nir_intrinsic_instr *instr)
2274 {
2275 const char *store_name;
2276 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2277 LLVMTypeRef data_type = ctx->ac.f32;
2278 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2279 int components_32bit = elem_size_mult * instr->num_components;
2280 unsigned writemask = nir_intrinsic_write_mask(instr);
2281 LLVMValueRef base_data, base_offset;
2282 LLVMValueRef params[6];
2283
2284 params[1] = ctx->abi->load_ssbo(ctx->abi,
2285 get_src(ctx, instr->src[1]), true);
2286 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2287 params[4] = ctx->ac.i1false; /* glc */
2288 params[5] = ctx->ac.i1false; /* slc */
2289
2290 if (components_32bit > 1)
2291 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2292
2293 base_data = ac_to_float(&ctx->ac, src_data);
2294 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2295 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2296 data_type, "");
2297 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2298 while (writemask) {
2299 int start, count;
2300 LLVMValueRef data;
2301 LLVMValueRef offset;
2302 LLVMValueRef tmp;
2303 u_bit_scan_consecutive_range(&writemask, &start, &count);
2304
2305 /* Due to an LLVM limitation, split 3-element writes
2306 * into a 2-element and a 1-element write. */
2307 if (count == 3) {
2308 writemask |= 1 << (start + 2);
2309 count = 2;
2310 }
2311
2312 start *= elem_size_mult;
2313 count *= elem_size_mult;
2314
2315 if (count > 4) {
2316 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2317 count = 4;
2318 }
2319
2320 if (count == 4) {
2321 store_name = "llvm.amdgcn.buffer.store.v4f32";
2322 data = base_data;
2323 } else if (count == 2) {
2324 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2325
2326 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2327 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2328 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2329 ctx->ac.i32_0, "");
2330
2331 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2332 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2333 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2334 ctx->ac.i32_1, "");
2335 store_name = "llvm.amdgcn.buffer.store.v2f32";
2336
2337 } else {
2338 assert(count == 1);
2339 if (get_llvm_num_components(base_data) > 1)
2340 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2341 LLVMConstInt(ctx->ac.i32, start, false), "");
2342 else
2343 data = base_data;
2344 store_name = "llvm.amdgcn.buffer.store.f32";
2345 }
2346
2347 offset = base_offset;
2348 if (start != 0) {
2349 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2350 }
2351 params[0] = data;
2352 params[3] = offset;
2353 ac_build_intrinsic(&ctx->ac, store_name,
2354 ctx->ac.voidt, params, 6, 0);
2355 }
2356 }
2357
2358 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2359 const nir_intrinsic_instr *instr)
2360 {
2361 const char *name;
2362 LLVMValueRef params[6];
2363 int arg_count = 0;
2364
2365 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2366 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2367 }
2368 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2369 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2370 get_src(ctx, instr->src[0]),
2371 true);
2372 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2373 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2374 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2375
2376 switch (instr->intrinsic) {
2377 case nir_intrinsic_ssbo_atomic_add:
2378 name = "llvm.amdgcn.buffer.atomic.add";
2379 break;
2380 case nir_intrinsic_ssbo_atomic_imin:
2381 name = "llvm.amdgcn.buffer.atomic.smin";
2382 break;
2383 case nir_intrinsic_ssbo_atomic_umin:
2384 name = "llvm.amdgcn.buffer.atomic.umin";
2385 break;
2386 case nir_intrinsic_ssbo_atomic_imax:
2387 name = "llvm.amdgcn.buffer.atomic.smax";
2388 break;
2389 case nir_intrinsic_ssbo_atomic_umax:
2390 name = "llvm.amdgcn.buffer.atomic.umax";
2391 break;
2392 case nir_intrinsic_ssbo_atomic_and:
2393 name = "llvm.amdgcn.buffer.atomic.and";
2394 break;
2395 case nir_intrinsic_ssbo_atomic_or:
2396 name = "llvm.amdgcn.buffer.atomic.or";
2397 break;
2398 case nir_intrinsic_ssbo_atomic_xor:
2399 name = "llvm.amdgcn.buffer.atomic.xor";
2400 break;
2401 case nir_intrinsic_ssbo_atomic_exchange:
2402 name = "llvm.amdgcn.buffer.atomic.swap";
2403 break;
2404 case nir_intrinsic_ssbo_atomic_comp_swap:
2405 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2406 break;
2407 default:
2408 abort();
2409 }
2410
2411 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2412 }
2413
2414 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2415 const nir_intrinsic_instr *instr)
2416 {
2417 LLVMValueRef results[2];
2418 int load_components;
2419 int num_components = instr->num_components;
2420 if (instr->dest.ssa.bit_size == 64)
2421 num_components *= 2;
2422
2423 for (int i = 0; i < num_components; i += load_components) {
2424 load_components = MIN2(num_components - i, 4);
2425 const char *load_name;
2426 LLVMTypeRef data_type = ctx->ac.f32;
2427 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2428 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2429
2430 if (load_components == 3)
2431 data_type = LLVMVectorType(ctx->ac.f32, 4);
2432 else if (load_components > 1)
2433 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2434
2435 if (load_components >= 3)
2436 load_name = "llvm.amdgcn.buffer.load.v4f32";
2437 else if (load_components == 2)
2438 load_name = "llvm.amdgcn.buffer.load.v2f32";
2439 else if (load_components == 1)
2440 load_name = "llvm.amdgcn.buffer.load.f32";
2441 else
2442 unreachable("unhandled number of components");
2443
2444 LLVMValueRef params[] = {
2445 ctx->abi->load_ssbo(ctx->abi,
2446 get_src(ctx, instr->src[0]),
2447 false),
2448 LLVMConstInt(ctx->ac.i32, 0, false),
2449 offset,
2450 ctx->ac.i1false,
2451 ctx->ac.i1false,
2452 };
2453
2454 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2455
2456 }
2457
2458 assume(results[0]);
2459 LLVMValueRef ret = results[0];
2460 if (num_components > 4 || num_components == 3) {
2461 LLVMValueRef masks[] = {
2462 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2463 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2464 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2465 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2466 };
2467
2468 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2469 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2470 results[num_components > 4 ? 1 : 0], swizzle, "");
2471 }
2472
2473 return LLVMBuildBitCast(ctx->ac.builder, ret,
2474 get_def_type(ctx, &instr->dest.ssa), "");
2475 }
2476
2477 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2478 const nir_intrinsic_instr *instr)
2479 {
2480 LLVMValueRef results[8], ret;
2481 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2482 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2483 int num_components = instr->num_components;
2484
2485 if (ctx->abi->load_ubo)
2486 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2487
2488 if (instr->dest.ssa.bit_size == 64)
2489 num_components *= 2;
2490
2491 for (unsigned i = 0; i < num_components; ++i) {
2492 LLVMValueRef params[] = {
2493 rsrc,
2494 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2495 offset, "")
2496 };
2497 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2498 params, 2,
2499 AC_FUNC_ATTR_READNONE |
2500 AC_FUNC_ATTR_LEGACY);
2501 }
2502
2503
2504 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2505 return LLVMBuildBitCast(ctx->ac.builder, ret,
2506 get_def_type(ctx, &instr->dest.ssa), "");
2507 }
2508
2509 static void
2510 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2511 bool vs_in, unsigned *vertex_index_out,
2512 LLVMValueRef *vertex_index_ref,
2513 unsigned *const_out, LLVMValueRef *indir_out)
2514 {
2515 unsigned const_offset = 0;
2516 nir_deref *tail = &deref->deref;
2517 LLVMValueRef offset = NULL;
2518
2519 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2520 tail = tail->child;
2521 nir_deref_array *deref_array = nir_deref_as_array(tail);
2522 if (vertex_index_out)
2523 *vertex_index_out = deref_array->base_offset;
2524
2525 if (vertex_index_ref) {
2526 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2527 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2528 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2529 }
2530 *vertex_index_ref = vtx;
2531 }
2532 }
2533
2534 if (deref->var->data.compact) {
2535 assert(tail->child->deref_type == nir_deref_type_array);
2536 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2537 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2538 /* We always lower indirect dereferences for "compact" array vars. */
2539 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2540
2541 const_offset = deref_array->base_offset;
2542 goto out;
2543 }
2544
2545 while (tail->child != NULL) {
2546 const struct glsl_type *parent_type = tail->type;
2547 tail = tail->child;
2548
2549 if (tail->deref_type == nir_deref_type_array) {
2550 nir_deref_array *deref_array = nir_deref_as_array(tail);
2551 LLVMValueRef index, stride, local_offset;
2552 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2553
2554 const_offset += size * deref_array->base_offset;
2555 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2556 continue;
2557
2558 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2559 index = get_src(ctx, deref_array->indirect);
2560 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2561 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2562
2563 if (offset)
2564 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2565 else
2566 offset = local_offset;
2567 } else if (tail->deref_type == nir_deref_type_struct) {
2568 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2569
2570 for (unsigned i = 0; i < deref_struct->index; i++) {
2571 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2572 const_offset += glsl_count_attribute_slots(ft, vs_in);
2573 }
2574 } else
2575 unreachable("unsupported deref type");
2576
2577 }
2578 out:
2579 if (const_offset && offset)
2580 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2581 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2582 "");
2583
2584 *const_out = const_offset;
2585 *indir_out = offset;
2586 }
2587
2588
2589 /* The offchip buffer layout for TCS->TES is
2590 *
2591 * - attribute 0 of patch 0 vertex 0
2592 * - attribute 0 of patch 0 vertex 1
2593 * - attribute 0 of patch 0 vertex 2
2594 * ...
2595 * - attribute 0 of patch 1 vertex 0
2596 * - attribute 0 of patch 1 vertex 1
2597 * ...
2598 * - attribute 1 of patch 0 vertex 0
2599 * - attribute 1 of patch 0 vertex 1
2600 * ...
2601 * - per patch attribute 0 of patch 0
2602 * - per patch attribute 0 of patch 1
2603 * ...
2604 *
2605 * Note that every attribute has 4 components.
2606 */
2607 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2608 LLVMValueRef vertex_index,
2609 LLVMValueRef param_index)
2610 {
2611 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2612 LLVMValueRef param_stride, constant16;
2613 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2614
2615 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2616 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2617 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2618 num_patches, "");
2619
2620 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2621 if (vertex_index) {
2622 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2623 vertices_per_patch, "");
2624
2625 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2626 vertex_index, "");
2627
2628 param_stride = total_vertices;
2629 } else {
2630 base_addr = rel_patch_id;
2631 param_stride = num_patches;
2632 }
2633
2634 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2635 LLVMBuildMul(ctx->builder, param_index,
2636 param_stride, ""), "");
2637
2638 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2639
2640 if (!vertex_index) {
2641 LLVMValueRef patch_data_offset =
2642 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2643
2644 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2645 patch_data_offset, "");
2646 }
2647 return base_addr;
2648 }
2649
2650 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2651 unsigned param,
2652 unsigned const_index,
2653 bool is_compact,
2654 LLVMValueRef vertex_index,
2655 LLVMValueRef indir_index)
2656 {
2657 LLVMValueRef param_index;
2658
2659 if (indir_index)
2660 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2661 indir_index, "");
2662 else {
2663 if (const_index && !is_compact)
2664 param += const_index;
2665 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2666 }
2667 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2668 }
2669
2670 static void
2671 mark_tess_output(struct nir_to_llvm_context *ctx,
2672 bool is_patch, uint32_t param)
2673
2674 {
2675 if (is_patch) {
2676 ctx->tess_patch_outputs_written |= (1ull << param);
2677 } else
2678 ctx->tess_outputs_written |= (1ull << param);
2679 }
2680
2681 static LLVMValueRef
2682 get_dw_address(struct nir_to_llvm_context *ctx,
2683 LLVMValueRef dw_addr,
2684 unsigned param,
2685 unsigned const_index,
2686 bool compact_const_index,
2687 LLVMValueRef vertex_index,
2688 LLVMValueRef stride,
2689 LLVMValueRef indir_index)
2690
2691 {
2692
2693 if (vertex_index) {
2694 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2695 LLVMBuildMul(ctx->builder,
2696 vertex_index,
2697 stride, ""), "");
2698 }
2699
2700 if (indir_index)
2701 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2702 LLVMBuildMul(ctx->builder, indir_index,
2703 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2704 else if (const_index && !compact_const_index)
2705 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2706 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2707
2708 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2709 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2710
2711 if (const_index && compact_const_index)
2712 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2713 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2714 return dw_addr;
2715 }
2716
2717 static LLVMValueRef
2718 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2719 unsigned value_count, unsigned component)
2720 {
2721 LLVMValueRef vec = NULL;
2722
2723 if (value_count == 1) {
2724 return values[component];
2725 } else if (!value_count)
2726 unreachable("value_count is 0");
2727
2728 for (unsigned i = component; i < value_count + component; i++) {
2729 LLVMValueRef value = values[i];
2730
2731 if (!i)
2732 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2733 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2734 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2735 }
2736 return vec;
2737 }
2738
2739 static LLVMValueRef
2740 load_tcs_input(struct nir_to_llvm_context *ctx,
2741 nir_intrinsic_instr *instr)
2742 {
2743 LLVMValueRef dw_addr, stride;
2744 unsigned const_index;
2745 LLVMValueRef vertex_index;
2746 LLVMValueRef indir_index;
2747 unsigned param;
2748 LLVMValueRef value[4], result;
2749 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2750 const bool is_compact = instr->variables[0]->var->data.compact;
2751 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2752 get_deref_offset(ctx->nir, instr->variables[0],
2753 false, NULL, per_vertex ? &vertex_index : NULL,
2754 &const_index, &indir_index);
2755
2756 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2757 dw_addr = get_tcs_in_current_patch_offset(ctx);
2758 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2759 indir_index);
2760
2761 unsigned comp = instr->variables[0]->var->data.location_frac;
2762 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2763 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2764 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2765 ctx->ac.i32_1, "");
2766 }
2767 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2768 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2769 return result;
2770 }
2771
2772 static LLVMValueRef
2773 load_tcs_output(struct nir_to_llvm_context *ctx,
2774 nir_intrinsic_instr *instr)
2775 {
2776 LLVMValueRef dw_addr;
2777 LLVMValueRef stride = NULL;
2778 LLVMValueRef value[4], result;
2779 LLVMValueRef vertex_index = NULL;
2780 LLVMValueRef indir_index = NULL;
2781 unsigned const_index = 0;
2782 unsigned param;
2783 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2784 const bool is_compact = instr->variables[0]->var->data.compact;
2785 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2786 get_deref_offset(ctx->nir, instr->variables[0],
2787 false, NULL, per_vertex ? &vertex_index : NULL,
2788 &const_index, &indir_index);
2789
2790 if (!instr->variables[0]->var->data.patch) {
2791 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2792 dw_addr = get_tcs_out_current_patch_offset(ctx);
2793 } else {
2794 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2795 }
2796
2797 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2798 indir_index);
2799
2800 unsigned comp = instr->variables[0]->var->data.location_frac;
2801 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2802 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2803 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2804 ctx->ac.i32_1, "");
2805 }
2806 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2807 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2808 return result;
2809 }
2810
2811 static void
2812 store_tcs_output(struct nir_to_llvm_context *ctx,
2813 nir_intrinsic_instr *instr,
2814 LLVMValueRef src,
2815 unsigned writemask)
2816 {
2817 LLVMValueRef dw_addr;
2818 LLVMValueRef stride = NULL;
2819 LLVMValueRef buf_addr = NULL;
2820 LLVMValueRef vertex_index = NULL;
2821 LLVMValueRef indir_index = NULL;
2822 unsigned const_index = 0;
2823 unsigned param;
2824 const unsigned comp = instr->variables[0]->var->data.location_frac;
2825 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2826 const bool is_compact = instr->variables[0]->var->data.compact;
2827
2828 get_deref_offset(ctx->nir, instr->variables[0],
2829 false, NULL, per_vertex ? &vertex_index : NULL,
2830 &const_index, &indir_index);
2831
2832 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2833 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2834 is_compact && const_index > 3) {
2835 const_index -= 3;
2836 param++;
2837 }
2838
2839 if (!instr->variables[0]->var->data.patch) {
2840 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2841 dw_addr = get_tcs_out_current_patch_offset(ctx);
2842 } else {
2843 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2844 }
2845
2846 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2847
2848 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2849 indir_index);
2850 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2851 vertex_index, indir_index);
2852
2853 bool is_tess_factor = false;
2854 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2855 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2856 is_tess_factor = true;
2857
2858 unsigned base = is_compact ? const_index : 0;
2859 for (unsigned chan = 0; chan < 8; chan++) {
2860 if (!(writemask & (1 << chan)))
2861 continue;
2862 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2863
2864 ac_lds_store(&ctx->ac, dw_addr, value);
2865
2866 if (!is_tess_factor && writemask != 0xF)
2867 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2868 buf_addr, ctx->oc_lds,
2869 4 * (base + chan), 1, 0, true, false);
2870
2871 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2872 ctx->ac.i32_1, "");
2873 }
2874
2875 if (writemask == 0xF) {
2876 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2877 buf_addr, ctx->oc_lds,
2878 (base * 4), 1, 0, true, false);
2879 }
2880 }
2881
2882 static LLVMValueRef
2883 load_tes_input(struct nir_to_llvm_context *ctx,
2884 const nir_intrinsic_instr *instr)
2885 {
2886 LLVMValueRef buf_addr;
2887 LLVMValueRef result;
2888 LLVMValueRef vertex_index = NULL;
2889 LLVMValueRef indir_index = NULL;
2890 unsigned const_index = 0;
2891 unsigned param;
2892 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2893 const bool is_compact = instr->variables[0]->var->data.compact;
2894
2895 get_deref_offset(ctx->nir, instr->variables[0],
2896 false, NULL, per_vertex ? &vertex_index : NULL,
2897 &const_index, &indir_index);
2898 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2899 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2900 is_compact && const_index > 3) {
2901 const_index -= 3;
2902 param++;
2903 }
2904
2905 unsigned comp = instr->variables[0]->var->data.location_frac;
2906 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2907 is_compact, vertex_index, indir_index);
2908
2909 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2910 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2911
2912 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2913 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2914 result = trim_vector(&ctx->ac, result, instr->num_components);
2915 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2916 return result;
2917 }
2918
2919 static LLVMValueRef
2920 load_gs_input(struct nir_to_llvm_context *ctx,
2921 nir_intrinsic_instr *instr)
2922 {
2923 LLVMValueRef indir_index, vtx_offset;
2924 unsigned const_index;
2925 LLVMValueRef args[9];
2926 unsigned param, vtx_offset_param;
2927 LLVMValueRef value[4], result;
2928 unsigned vertex_index;
2929 get_deref_offset(ctx->nir, instr->variables[0],
2930 false, &vertex_index, NULL,
2931 &const_index, &indir_index);
2932 vtx_offset_param = vertex_index;
2933 assert(vtx_offset_param < 6);
2934 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2935 LLVMConstInt(ctx->ac.i32, 4, false), "");
2936
2937 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2938
2939 unsigned comp = instr->variables[0]->var->data.location_frac;
2940 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2941 if (ctx->ac.chip_class >= GFX9) {
2942 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2943 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2944 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2945 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2946 } else {
2947 args[0] = ctx->esgs_ring;
2948 args[1] = vtx_offset;
2949 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2950 args[3] = ctx->ac.i32_0;
2951 args[4] = ctx->ac.i32_1; /* OFFEN */
2952 args[5] = ctx->ac.i32_0; /* IDXEN */
2953 args[6] = ctx->ac.i32_1; /* GLC */
2954 args[7] = ctx->ac.i32_0; /* SLC */
2955 args[8] = ctx->ac.i32_0; /* TFE */
2956
2957 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2958 ctx->ac.i32, args, 9,
2959 AC_FUNC_ATTR_READONLY |
2960 AC_FUNC_ATTR_LEGACY);
2961 }
2962 }
2963 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2964
2965 return result;
2966 }
2967
2968 static LLVMValueRef
2969 build_gep_for_deref(struct ac_nir_context *ctx,
2970 nir_deref_var *deref)
2971 {
2972 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2973 assert(entry->data);
2974 LLVMValueRef val = entry->data;
2975 nir_deref *tail = deref->deref.child;
2976 while (tail != NULL) {
2977 LLVMValueRef offset;
2978 switch (tail->deref_type) {
2979 case nir_deref_type_array: {
2980 nir_deref_array *array = nir_deref_as_array(tail);
2981 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2982 if (array->deref_array_type ==
2983 nir_deref_array_type_indirect) {
2984 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2985 get_src(ctx,
2986 array->indirect),
2987 "");
2988 }
2989 break;
2990 }
2991 case nir_deref_type_struct: {
2992 nir_deref_struct *deref_struct =
2993 nir_deref_as_struct(tail);
2994 offset = LLVMConstInt(ctx->ac.i32,
2995 deref_struct->index, 0);
2996 break;
2997 }
2998 default:
2999 unreachable("bad deref type");
3000 }
3001 val = ac_build_gep0(&ctx->ac, val, offset);
3002 tail = tail->child;
3003 }
3004 return val;
3005 }
3006
3007 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3008 nir_intrinsic_instr *instr)
3009 {
3010 LLVMValueRef values[8];
3011 int idx = instr->variables[0]->var->data.driver_location;
3012 int ve = instr->dest.ssa.num_components;
3013 unsigned comp = instr->variables[0]->var->data.location_frac;
3014 LLVMValueRef indir_index;
3015 LLVMValueRef ret;
3016 unsigned const_index;
3017 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3018 instr->variables[0]->var->data.mode == nir_var_shader_in;
3019 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3020 &const_index, &indir_index);
3021
3022 if (instr->dest.ssa.bit_size == 64)
3023 ve *= 2;
3024
3025 switch (instr->variables[0]->var->data.mode) {
3026 case nir_var_shader_in:
3027 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3028 return load_tcs_input(ctx->nctx, instr);
3029 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3030 return load_tes_input(ctx->nctx, instr);
3031 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3032 return load_gs_input(ctx->nctx, instr);
3033 }
3034
3035 for (unsigned chan = comp; chan < ve + comp; chan++) {
3036 if (indir_index) {
3037 unsigned count = glsl_count_attribute_slots(
3038 instr->variables[0]->var->type,
3039 ctx->stage == MESA_SHADER_VERTEX);
3040 count -= chan / 4;
3041 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3042 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3043 4, false, true);
3044
3045 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3046 tmp_vec,
3047 indir_index, "");
3048 } else
3049 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3050 }
3051 break;
3052 case nir_var_local:
3053 for (unsigned chan = 0; chan < ve; chan++) {
3054 if (indir_index) {
3055 unsigned count = glsl_count_attribute_slots(
3056 instr->variables[0]->var->type, false);
3057 count -= chan / 4;
3058 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3059 &ctx->ac, ctx->locals + idx + chan, count,
3060 4, true, true);
3061
3062 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3063 tmp_vec,
3064 indir_index, "");
3065 } else {
3066 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3067 }
3068 }
3069 break;
3070 case nir_var_shared: {
3071 LLVMValueRef address = build_gep_for_deref(ctx,
3072 instr->variables[0]);
3073 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3074 return LLVMBuildBitCast(ctx->ac.builder, val,
3075 get_def_type(ctx, &instr->dest.ssa),
3076 "");
3077 }
3078 case nir_var_shader_out:
3079 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3080 return load_tcs_output(ctx->nctx, instr);
3081
3082 for (unsigned chan = comp; chan < ve + comp; chan++) {
3083 if (indir_index) {
3084 unsigned count = glsl_count_attribute_slots(
3085 instr->variables[0]->var->type, false);
3086 count -= chan / 4;
3087 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3088 &ctx->ac, ctx->outputs + idx + chan, count,
3089 4, true, true);
3090
3091 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3092 tmp_vec,
3093 indir_index, "");
3094 } else {
3095 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3096 ctx->outputs[idx + chan + const_index * 4],
3097 "");
3098 }
3099 }
3100 break;
3101 default:
3102 unreachable("unhandle variable mode");
3103 }
3104 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3105 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3106 }
3107
3108 static void
3109 visit_store_var(struct ac_nir_context *ctx,
3110 nir_intrinsic_instr *instr)
3111 {
3112 LLVMValueRef temp_ptr, value;
3113 int idx = instr->variables[0]->var->data.driver_location;
3114 unsigned comp = instr->variables[0]->var->data.location_frac;
3115 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3116 int writemask = instr->const_index[0] << comp;
3117 LLVMValueRef indir_index;
3118 unsigned const_index;
3119 get_deref_offset(ctx, instr->variables[0], false,
3120 NULL, NULL, &const_index, &indir_index);
3121
3122 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3123 int old_writemask = writemask;
3124
3125 src = LLVMBuildBitCast(ctx->ac.builder, src,
3126 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3127 "");
3128
3129 writemask = 0;
3130 for (unsigned chan = 0; chan < 4; chan++) {
3131 if (old_writemask & (1 << chan))
3132 writemask |= 3u << (2 * chan);
3133 }
3134 }
3135
3136 switch (instr->variables[0]->var->data.mode) {
3137 case nir_var_shader_out:
3138
3139 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3140 store_tcs_output(ctx->nctx, instr, src, writemask);
3141 return;
3142 }
3143
3144 for (unsigned chan = 0; chan < 8; chan++) {
3145 int stride = 4;
3146 if (!(writemask & (1 << chan)))
3147 continue;
3148
3149 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3150
3151 if (instr->variables[0]->var->data.compact)
3152 stride = 1;
3153 if (indir_index) {
3154 unsigned count = glsl_count_attribute_slots(
3155 instr->variables[0]->var->type, false);
3156 count -= chan / 4;
3157 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3158 &ctx->ac, ctx->outputs + idx + chan, count,
3159 stride, true, true);
3160
3161 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3162 value, indir_index, "");
3163 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3164 count, stride, tmp_vec);
3165
3166 } else {
3167 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3168
3169 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3170 }
3171 }
3172 break;
3173 case nir_var_local:
3174 for (unsigned chan = 0; chan < 8; chan++) {
3175 if (!(writemask & (1 << chan)))
3176 continue;
3177
3178 value = llvm_extract_elem(&ctx->ac, src, chan);
3179 if (indir_index) {
3180 unsigned count = glsl_count_attribute_slots(
3181 instr->variables[0]->var->type, false);
3182 count -= chan / 4;
3183 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3184 &ctx->ac, ctx->locals + idx + chan, count,
3185 4, true, true);
3186
3187 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3188 value, indir_index, "");
3189 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3190 count, 4, tmp_vec);
3191 } else {
3192 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3193
3194 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3195 }
3196 }
3197 break;
3198 case nir_var_shared: {
3199 int writemask = instr->const_index[0];
3200 LLVMValueRef address = build_gep_for_deref(ctx,
3201 instr->variables[0]);
3202 LLVMValueRef val = get_src(ctx, instr->src[0]);
3203 unsigned components =
3204 glsl_get_vector_elements(
3205 nir_deref_tail(&instr->variables[0]->deref)->type);
3206 if (writemask == (1 << components) - 1) {
3207 val = LLVMBuildBitCast(
3208 ctx->ac.builder, val,
3209 LLVMGetElementType(LLVMTypeOf(address)), "");
3210 LLVMBuildStore(ctx->ac.builder, val, address);
3211 } else {
3212 for (unsigned chan = 0; chan < 4; chan++) {
3213 if (!(writemask & (1 << chan)))
3214 continue;
3215 LLVMValueRef ptr =
3216 LLVMBuildStructGEP(ctx->ac.builder,
3217 address, chan, "");
3218 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3219 chan);
3220 src = LLVMBuildBitCast(
3221 ctx->ac.builder, src,
3222 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3223 LLVMBuildStore(ctx->ac.builder, src, ptr);
3224 }
3225 }
3226 break;
3227 }
3228 default:
3229 break;
3230 }
3231 }
3232
3233 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3234 {
3235 switch (dim) {
3236 case GLSL_SAMPLER_DIM_BUF:
3237 return 1;
3238 case GLSL_SAMPLER_DIM_1D:
3239 return array ? 2 : 1;
3240 case GLSL_SAMPLER_DIM_2D:
3241 return array ? 3 : 2;
3242 case GLSL_SAMPLER_DIM_MS:
3243 return array ? 4 : 3;
3244 case GLSL_SAMPLER_DIM_3D:
3245 case GLSL_SAMPLER_DIM_CUBE:
3246 return 3;
3247 case GLSL_SAMPLER_DIM_RECT:
3248 case GLSL_SAMPLER_DIM_SUBPASS:
3249 return 2;
3250 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3251 return 3;
3252 default:
3253 break;
3254 }
3255 return 0;
3256 }
3257
3258
3259
3260 /* Adjust the sample index according to FMASK.
3261 *
3262 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3263 * which is the identity mapping. Each nibble says which physical sample
3264 * should be fetched to get that sample.
3265 *
3266 * For example, 0x11111100 means there are only 2 samples stored and
3267 * the second sample covers 3/4 of the pixel. When reading samples 0
3268 * and 1, return physical sample 0 (determined by the first two 0s
3269 * in FMASK), otherwise return physical sample 1.
3270 *
3271 * The sample index should be adjusted as follows:
3272 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3273 */
3274 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3275 LLVMValueRef coord_x, LLVMValueRef coord_y,
3276 LLVMValueRef coord_z,
3277 LLVMValueRef sample_index,
3278 LLVMValueRef fmask_desc_ptr)
3279 {
3280 LLVMValueRef fmask_load_address[4];
3281 LLVMValueRef res;
3282
3283 fmask_load_address[0] = coord_x;
3284 fmask_load_address[1] = coord_y;
3285 if (coord_z) {
3286 fmask_load_address[2] = coord_z;
3287 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3288 }
3289
3290 struct ac_image_args args = {0};
3291
3292 args.opcode = ac_image_load;
3293 args.da = coord_z ? true : false;
3294 args.resource = fmask_desc_ptr;
3295 args.dmask = 0xf;
3296 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3297
3298 res = ac_build_image_opcode(ctx, &args);
3299
3300 res = ac_to_integer(ctx, res);
3301 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3302 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3303
3304 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3305 res,
3306 ctx->i32_0, "");
3307
3308 LLVMValueRef sample_index4 =
3309 LLVMBuildMul(ctx->builder, sample_index, four, "");
3310 LLVMValueRef shifted_fmask =
3311 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3312 LLVMValueRef final_sample =
3313 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3314
3315 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3316 * resource descriptor is 0 (invalid),
3317 */
3318 LLVMValueRef fmask_desc =
3319 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3320 ctx->v8i32, "");
3321
3322 LLVMValueRef fmask_word1 =
3323 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3324 ctx->i32_1, "");
3325
3326 LLVMValueRef word1_is_nonzero =
3327 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3328 fmask_word1, ctx->i32_0, "");
3329
3330 /* Replace the MSAA sample index. */
3331 sample_index =
3332 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3333 final_sample, sample_index, "");
3334 return sample_index;
3335 }
3336
3337 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3338 const nir_intrinsic_instr *instr)
3339 {
3340 const struct glsl_type *type = instr->variables[0]->var->type;
3341 if(instr->variables[0]->deref.child)
3342 type = instr->variables[0]->deref.child->type;
3343
3344 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3345 LLVMValueRef coords[4];
3346 LLVMValueRef masks[] = {
3347 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3348 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3349 };
3350 LLVMValueRef res;
3351 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3352
3353 int count;
3354 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3355 bool is_array = glsl_sampler_type_is_array(type);
3356 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3357 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3358 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3359 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3360 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3361 count = image_type_to_components_count(dim, is_array);
3362
3363 if (is_ms) {
3364 LLVMValueRef fmask_load_address[3];
3365 int chan;
3366
3367 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3368 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3369 if (is_array)
3370 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3371 else
3372 fmask_load_address[2] = NULL;
3373 if (add_frag_pos) {
3374 for (chan = 0; chan < 2; ++chan)
3375 fmask_load_address[chan] =
3376 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3377 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3378 ctx->ac.i32, ""), "");
3379 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3380 }
3381 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3382 fmask_load_address[0],
3383 fmask_load_address[1],
3384 fmask_load_address[2],
3385 sample_index,
3386 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3387 }
3388 if (count == 1 && !gfx9_1d) {
3389 if (instr->src[0].ssa->num_components)
3390 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3391 else
3392 res = src0;
3393 } else {
3394 int chan;
3395 if (is_ms)
3396 count--;
3397 for (chan = 0; chan < count; ++chan) {
3398 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3399 }
3400 if (add_frag_pos) {
3401 for (chan = 0; chan < 2; ++chan)
3402 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3403 ctx->ac.i32, ""), "");
3404 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3405 count++;
3406 }
3407
3408 if (gfx9_1d) {
3409 if (is_array) {
3410 coords[2] = coords[1];
3411 coords[1] = ctx->ac.i32_0;
3412 } else
3413 coords[1] = ctx->ac.i32_0;
3414 count++;
3415 }
3416
3417 if (is_ms) {
3418 coords[count] = sample_index;
3419 count++;
3420 }
3421
3422 if (count == 3) {
3423 coords[3] = LLVMGetUndef(ctx->ac.i32);
3424 count = 4;
3425 }
3426 res = ac_build_gather_values(&ctx->ac, coords, count);
3427 }
3428 return res;
3429 }
3430
3431 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3432 const nir_intrinsic_instr *instr)
3433 {
3434 LLVMValueRef params[7];
3435 LLVMValueRef res;
3436 char intrinsic_name[64];
3437 const nir_variable *var = instr->variables[0]->var;
3438 const struct glsl_type *type = var->type;
3439
3440 if(instr->variables[0]->deref.child)
3441 type = instr->variables[0]->deref.child->type;
3442
3443 type = glsl_without_array(type);
3444 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3445 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3446 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3447 ctx->ac.i32_0, ""); /* vindex */
3448 params[2] = ctx->ac.i32_0; /* voffset */
3449 params[3] = ctx->ac.i1false; /* glc */
3450 params[4] = ctx->ac.i1false; /* slc */
3451 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3452 params, 5, 0);
3453
3454 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3455 res = ac_to_integer(&ctx->ac, res);
3456 } else {
3457 bool is_da = glsl_sampler_type_is_array(type) ||
3458 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3459 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3460 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3461 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3462 LLVMValueRef glc = ctx->ac.i1false;
3463 LLVMValueRef slc = ctx->ac.i1false;
3464
3465 params[0] = get_image_coords(ctx, instr);
3466 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3467 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3468 if (HAVE_LLVM <= 0x0309) {
3469 params[3] = ctx->ac.i1false; /* r128 */
3470 params[4] = da;
3471 params[5] = glc;
3472 params[6] = slc;
3473 } else {
3474 LLVMValueRef lwe = ctx->ac.i1false;
3475 params[3] = glc;
3476 params[4] = slc;
3477 params[5] = lwe;
3478 params[6] = da;
3479 }
3480
3481 ac_get_image_intr_name("llvm.amdgcn.image.load",
3482 ctx->ac.v4f32, /* vdata */
3483 LLVMTypeOf(params[0]), /* coords */
3484 LLVMTypeOf(params[1]), /* rsrc */
3485 intrinsic_name, sizeof(intrinsic_name));
3486
3487 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3488 params, 7, AC_FUNC_ATTR_READONLY);
3489 }
3490 return ac_to_integer(&ctx->ac, res);
3491 }
3492
3493 static void visit_image_store(struct ac_nir_context *ctx,
3494 nir_intrinsic_instr *instr)
3495 {
3496 LLVMValueRef params[8];
3497 char intrinsic_name[64];
3498 const nir_variable *var = instr->variables[0]->var;
3499 const struct glsl_type *type = glsl_without_array(var->type);
3500 LLVMValueRef glc = ctx->ac.i1false;
3501 bool force_glc = ctx->ac.chip_class == SI;
3502 if (force_glc)
3503 glc = ctx->ac.i1true;
3504
3505 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3506 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3507 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3508 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3509 ctx->ac.i32_0, ""); /* vindex */
3510 params[3] = ctx->ac.i32_0; /* voffset */
3511 params[4] = glc; /* glc */
3512 params[5] = ctx->ac.i1false; /* slc */
3513 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3514 params, 6, 0);
3515 } else {
3516 bool is_da = glsl_sampler_type_is_array(type) ||
3517 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3518 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3519 LLVMValueRef slc = ctx->ac.i1false;
3520
3521 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3522 params[1] = get_image_coords(ctx, instr); /* coords */
3523 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3524 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3525 if (HAVE_LLVM <= 0x0309) {
3526 params[4] = ctx->ac.i1false; /* r128 */
3527 params[5] = da;
3528 params[6] = glc;
3529 params[7] = slc;
3530 } else {
3531 LLVMValueRef lwe = ctx->ac.i1false;
3532 params[4] = glc;
3533 params[5] = slc;
3534 params[6] = lwe;
3535 params[7] = da;
3536 }
3537
3538 ac_get_image_intr_name("llvm.amdgcn.image.store",
3539 LLVMTypeOf(params[0]), /* vdata */
3540 LLVMTypeOf(params[1]), /* coords */
3541 LLVMTypeOf(params[2]), /* rsrc */
3542 intrinsic_name, sizeof(intrinsic_name));
3543
3544 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3545 params, 8, 0);
3546 }
3547
3548 }
3549
3550 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3551 const nir_intrinsic_instr *instr)
3552 {
3553 LLVMValueRef params[7];
3554 int param_count = 0;
3555 const nir_variable *var = instr->variables[0]->var;
3556
3557 const char *atomic_name;
3558 char intrinsic_name[41];
3559 const struct glsl_type *type = glsl_without_array(var->type);
3560 MAYBE_UNUSED int length;
3561
3562 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3563
3564 switch (instr->intrinsic) {
3565 case nir_intrinsic_image_atomic_add:
3566 atomic_name = "add";
3567 break;
3568 case nir_intrinsic_image_atomic_min:
3569 atomic_name = is_unsigned ? "umin" : "smin";
3570 break;
3571 case nir_intrinsic_image_atomic_max:
3572 atomic_name = is_unsigned ? "umax" : "smax";
3573 break;
3574 case nir_intrinsic_image_atomic_and:
3575 atomic_name = "and";
3576 break;
3577 case nir_intrinsic_image_atomic_or:
3578 atomic_name = "or";
3579 break;
3580 case nir_intrinsic_image_atomic_xor:
3581 atomic_name = "xor";
3582 break;
3583 case nir_intrinsic_image_atomic_exchange:
3584 atomic_name = "swap";
3585 break;
3586 case nir_intrinsic_image_atomic_comp_swap:
3587 atomic_name = "cmpswap";
3588 break;
3589 default:
3590 abort();
3591 }
3592
3593 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3594 params[param_count++] = get_src(ctx, instr->src[3]);
3595 params[param_count++] = get_src(ctx, instr->src[2]);
3596
3597 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3598 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3599 NULL, true, true);
3600 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3601 ctx->ac.i32_0, ""); /* vindex */
3602 params[param_count++] = ctx->ac.i32_0; /* voffset */
3603 params[param_count++] = ctx->ac.i1false; /* slc */
3604
3605 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3606 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3607 } else {
3608 char coords_type[8];
3609
3610 bool da = glsl_sampler_type_is_array(type) ||
3611 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3612
3613 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3614 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3615 NULL, true, true);
3616 params[param_count++] = ctx->ac.i1false; /* r128 */
3617 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3618 params[param_count++] = ctx->ac.i1false; /* slc */
3619
3620 build_int_type_name(LLVMTypeOf(coords),
3621 coords_type, sizeof(coords_type));
3622
3623 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3624 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3625 }
3626
3627 assert(length < sizeof(intrinsic_name));
3628 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3629 }
3630
3631 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3632 const nir_intrinsic_instr *instr)
3633 {
3634 LLVMValueRef res;
3635 const nir_variable *var = instr->variables[0]->var;
3636 const struct glsl_type *type = instr->variables[0]->var->type;
3637 bool da = glsl_sampler_type_is_array(var->type) ||
3638 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3639 if(instr->variables[0]->deref.child)
3640 type = instr->variables[0]->deref.child->type;
3641
3642 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3643 return get_buffer_size(ctx,
3644 get_sampler_desc(ctx, instr->variables[0],
3645 AC_DESC_BUFFER, NULL, true, false), true);
3646
3647 struct ac_image_args args = { 0 };
3648
3649 args.da = da;
3650 args.dmask = 0xf;
3651 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3652 args.opcode = ac_image_get_resinfo;
3653 args.addr = ctx->ac.i32_0;
3654
3655 res = ac_build_image_opcode(&ctx->ac, &args);
3656
3657 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3658
3659 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3660 glsl_sampler_type_is_array(type)) {
3661 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3662 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3663 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3664 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3665 }
3666 if (ctx->ac.chip_class >= GFX9 &&
3667 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3668 glsl_sampler_type_is_array(type)) {
3669 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3670 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3671 ctx->ac.i32_1, "");
3672
3673 }
3674 return res;
3675 }
3676
3677 #define NOOP_WAITCNT 0xf7f
3678 #define LGKM_CNT 0x07f
3679 #define VM_CNT 0xf70
3680
3681 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3682 unsigned simm16)
3683 {
3684 LLVMValueRef args[1] = {
3685 LLVMConstInt(ctx->ac.i32, simm16, false),
3686 };
3687 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3688 ctx->ac.voidt, args, 1, 0);
3689 }
3690
3691 static void emit_barrier(struct nir_to_llvm_context *ctx)
3692 {
3693 /* SI only (thanks to a hw bug workaround):
3694 * The real barrier instruction isn’t needed, because an entire patch
3695 * always fits into a single wave.
3696 */
3697 if (ctx->options->chip_class == SI &&
3698 ctx->stage == MESA_SHADER_TESS_CTRL) {
3699 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3700 return;
3701 }
3702 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3703 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3704 }
3705
3706 static void emit_discard_if(struct ac_nir_context *ctx,
3707 const nir_intrinsic_instr *instr)
3708 {
3709 LLVMValueRef cond;
3710
3711 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3712 get_src(ctx, instr->src[0]),
3713 ctx->ac.i32_0, "");
3714 ac_build_kill_if_false(&ctx->ac, cond);
3715 }
3716
3717 static LLVMValueRef
3718 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3719 {
3720 LLVMValueRef result;
3721 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3722 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3723 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3724
3725 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3726 }
3727
3728 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3729 const nir_intrinsic_instr *instr)
3730 {
3731 LLVMValueRef ptr, result;
3732 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3733 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3734
3735 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3736 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3737 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3738 ptr, src, src1,
3739 LLVMAtomicOrderingSequentiallyConsistent,
3740 LLVMAtomicOrderingSequentiallyConsistent,
3741 false);
3742 } else {
3743 LLVMAtomicRMWBinOp op;
3744 switch (instr->intrinsic) {
3745 case nir_intrinsic_var_atomic_add:
3746 op = LLVMAtomicRMWBinOpAdd;
3747 break;
3748 case nir_intrinsic_var_atomic_umin:
3749 op = LLVMAtomicRMWBinOpUMin;
3750 break;
3751 case nir_intrinsic_var_atomic_umax:
3752 op = LLVMAtomicRMWBinOpUMax;
3753 break;
3754 case nir_intrinsic_var_atomic_imin:
3755 op = LLVMAtomicRMWBinOpMin;
3756 break;
3757 case nir_intrinsic_var_atomic_imax:
3758 op = LLVMAtomicRMWBinOpMax;
3759 break;
3760 case nir_intrinsic_var_atomic_and:
3761 op = LLVMAtomicRMWBinOpAnd;
3762 break;
3763 case nir_intrinsic_var_atomic_or:
3764 op = LLVMAtomicRMWBinOpOr;
3765 break;
3766 case nir_intrinsic_var_atomic_xor:
3767 op = LLVMAtomicRMWBinOpXor;
3768 break;
3769 case nir_intrinsic_var_atomic_exchange:
3770 op = LLVMAtomicRMWBinOpXchg;
3771 break;
3772 default:
3773 return NULL;
3774 }
3775
3776 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3777 LLVMAtomicOrderingSequentiallyConsistent,
3778 false);
3779 }
3780 return result;
3781 }
3782
3783 #define INTERP_CENTER 0
3784 #define INTERP_CENTROID 1
3785 #define INTERP_SAMPLE 2
3786
3787 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3788 enum glsl_interp_mode interp, unsigned location)
3789 {
3790 switch (interp) {
3791 case INTERP_MODE_FLAT:
3792 default:
3793 return NULL;
3794 case INTERP_MODE_SMOOTH:
3795 case INTERP_MODE_NONE:
3796 if (location == INTERP_CENTER)
3797 return ctx->persp_center;
3798 else if (location == INTERP_CENTROID)
3799 return ctx->persp_centroid;
3800 else if (location == INTERP_SAMPLE)
3801 return ctx->persp_sample;
3802 break;
3803 case INTERP_MODE_NOPERSPECTIVE:
3804 if (location == INTERP_CENTER)
3805 return ctx->linear_center;
3806 else if (location == INTERP_CENTROID)
3807 return ctx->linear_centroid;
3808 else if (location == INTERP_SAMPLE)
3809 return ctx->linear_sample;
3810 break;
3811 }
3812 return NULL;
3813 }
3814
3815 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3816 LLVMValueRef sample_id)
3817 {
3818 LLVMValueRef result;
3819 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3820
3821 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3822 const_array(ctx->v2f32, 64), "");
3823
3824 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3825 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3826
3827 return result;
3828 }
3829
3830 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3831 {
3832 LLVMValueRef values[2];
3833
3834 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3835 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3836 return ac_build_gather_values(&ctx->ac, values, 2);
3837 }
3838
3839 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3840 const nir_intrinsic_instr *instr)
3841 {
3842 LLVMValueRef result[4];
3843 LLVMValueRef interp_param, attr_number;
3844 unsigned location;
3845 unsigned chan;
3846 LLVMValueRef src_c0 = NULL;
3847 LLVMValueRef src_c1 = NULL;
3848 LLVMValueRef src0 = NULL;
3849 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3850 switch (instr->intrinsic) {
3851 case nir_intrinsic_interp_var_at_centroid:
3852 location = INTERP_CENTROID;
3853 break;
3854 case nir_intrinsic_interp_var_at_sample:
3855 case nir_intrinsic_interp_var_at_offset:
3856 location = INTERP_CENTER;
3857 src0 = get_src(ctx->nir, instr->src[0]);
3858 break;
3859 default:
3860 break;
3861 }
3862
3863 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3864 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3865 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3866 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3867 LLVMValueRef sample_position;
3868 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3869
3870 /* fetch sample ID */
3871 sample_position = load_sample_position(ctx, src0);
3872
3873 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3874 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3875 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3876 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3877 }
3878 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3879 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3880
3881 if (location == INTERP_CENTER) {
3882 LLVMValueRef ij_out[2];
3883 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3884
3885 /*
3886 * take the I then J parameters, and the DDX/Y for it, and
3887 * calculate the IJ inputs for the interpolator.
3888 * temp1 = ddx * offset/sample.x + I;
3889 * interp_param.I = ddy * offset/sample.y + temp1;
3890 * temp1 = ddx * offset/sample.x + J;
3891 * interp_param.J = ddy * offset/sample.y + temp1;
3892 */
3893 for (unsigned i = 0; i < 2; i++) {
3894 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3895 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3896 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3897 ddxy_out, ix_ll, "");
3898 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3899 ddxy_out, iy_ll, "");
3900 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3901 interp_param, ix_ll, "");
3902 LLVMValueRef temp1, temp2;
3903
3904 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3905 ctx->f32, "");
3906
3907 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3908 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3909
3910 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3911 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3912
3913 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3914 temp2, ctx->ac.i32, "");
3915 }
3916 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3917
3918 }
3919
3920 for (chan = 0; chan < 4; chan++) {
3921 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3922
3923 if (interp_param) {
3924 interp_param = LLVMBuildBitCast(ctx->builder,
3925 interp_param, LLVMVectorType(ctx->f32, 2), "");
3926 LLVMValueRef i = LLVMBuildExtractElement(
3927 ctx->builder, interp_param, ctx->ac.i32_0, "");
3928 LLVMValueRef j = LLVMBuildExtractElement(
3929 ctx->builder, interp_param, ctx->ac.i32_1, "");
3930
3931 result[chan] = ac_build_fs_interp(&ctx->ac,
3932 llvm_chan, attr_number,
3933 ctx->prim_mask, i, j);
3934 } else {
3935 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3936 LLVMConstInt(ctx->ac.i32, 2, false),
3937 llvm_chan, attr_number,
3938 ctx->prim_mask);
3939 }
3940 }
3941 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
3942 instr->variables[0]->var->data.location_frac);
3943 }
3944
3945 static void
3946 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3947 const nir_intrinsic_instr *instr)
3948 {
3949 LLVMValueRef gs_next_vertex;
3950 LLVMValueRef can_emit;
3951 int idx;
3952
3953 assert(instr->const_index[0] == 0);
3954 /* Write vertex attribute values to GSVS ring */
3955 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3956 ctx->gs_next_vertex,
3957 "");
3958
3959 /* If this thread has already emitted the declared maximum number of
3960 * vertices, kill it: excessive vertex emissions are not supposed to
3961 * have any effect, and GS threads have no externally observable
3962 * effects other than emitting vertices.
3963 */
3964 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3965 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3966 ac_build_kill_if_false(&ctx->ac, can_emit);
3967
3968 /* loop num outputs */
3969 idx = 0;
3970 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3971 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3972 int length = 4;
3973 int slot = idx;
3974 int slot_inc = 1;
3975
3976 if (!(ctx->output_mask & (1ull << i)))
3977 continue;
3978
3979 if (i == VARYING_SLOT_CLIP_DIST0) {
3980 /* pack clip and cull into a single set of slots */
3981 length = ctx->num_output_clips + ctx->num_output_culls;
3982 if (length > 4)
3983 slot_inc = 2;
3984 }
3985 for (unsigned j = 0; j < length; j++) {
3986 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3987 out_ptr[j], "");
3988 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3989 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3990 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
3991
3992 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
3993
3994 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3995 out_val, 1,
3996 voffset, ctx->gs2vs_offset, 0,
3997 1, 1, true, true);
3998 }
3999 idx += slot_inc;
4000 }
4001
4002 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4003 ctx->ac.i32_1, "");
4004 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4005
4006 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4007 }
4008
4009 static void
4010 visit_end_primitive(struct nir_to_llvm_context *ctx,
4011 const nir_intrinsic_instr *instr)
4012 {
4013 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4014 }
4015
4016 static LLVMValueRef
4017 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4018 const nir_intrinsic_instr *instr)
4019 {
4020 LLVMValueRef coord[4] = {
4021 ctx->tes_u,
4022 ctx->tes_v,
4023 ctx->ac.f32_0,
4024 ctx->ac.f32_0,
4025 };
4026
4027 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4028 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4029 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4030
4031 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4032 return LLVMBuildBitCast(ctx->builder, result,
4033 get_def_type(ctx->nir, &instr->dest.ssa), "");
4034 }
4035
4036 static void visit_intrinsic(struct ac_nir_context *ctx,
4037 nir_intrinsic_instr *instr)
4038 {
4039 LLVMValueRef result = NULL;
4040
4041 switch (instr->intrinsic) {
4042 case nir_intrinsic_load_work_group_id: {
4043 result = ctx->nctx->workgroup_ids;
4044 break;
4045 }
4046 case nir_intrinsic_load_base_vertex: {
4047 result = ctx->abi->base_vertex;
4048 break;
4049 }
4050 case nir_intrinsic_load_vertex_id_zero_base: {
4051 result = ctx->abi->vertex_id;
4052 break;
4053 }
4054 case nir_intrinsic_load_local_invocation_id: {
4055 result = ctx->nctx->local_invocation_ids;
4056 break;
4057 }
4058 case nir_intrinsic_load_base_instance:
4059 result = ctx->abi->start_instance;
4060 break;
4061 case nir_intrinsic_load_draw_id:
4062 result = ctx->abi->draw_id;
4063 break;
4064 case nir_intrinsic_load_view_index:
4065 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4066 break;
4067 case nir_intrinsic_load_invocation_id:
4068 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4069 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4070 else
4071 result = ctx->nctx->gs_invocation_id;
4072 break;
4073 case nir_intrinsic_load_primitive_id:
4074 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4075 ctx->nctx->shader_info->gs.uses_prim_id = true;
4076 result = ctx->nctx->gs_prim_id;
4077 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4078 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4079 result = ctx->nctx->tcs_patch_id;
4080 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4081 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4082 result = ctx->nctx->tes_patch_id;
4083 } else
4084 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4085 break;
4086 case nir_intrinsic_load_sample_id:
4087 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4088 break;
4089 case nir_intrinsic_load_sample_pos:
4090 result = load_sample_pos(ctx);
4091 break;
4092 case nir_intrinsic_load_sample_mask_in:
4093 result = ctx->abi->sample_coverage;
4094 break;
4095 case nir_intrinsic_load_frag_coord: {
4096 LLVMValueRef values[4] = {
4097 ctx->abi->frag_pos[0],
4098 ctx->abi->frag_pos[1],
4099 ctx->abi->frag_pos[2],
4100 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4101 };
4102 result = ac_build_gather_values(&ctx->ac, values, 4);
4103 break;
4104 }
4105 case nir_intrinsic_load_front_face:
4106 result = ctx->abi->front_face;
4107 break;
4108 case nir_intrinsic_load_instance_id:
4109 result = ctx->abi->instance_id;
4110 break;
4111 case nir_intrinsic_load_num_work_groups:
4112 result = ctx->nctx->num_work_groups;
4113 break;
4114 case nir_intrinsic_load_local_invocation_index:
4115 result = visit_load_local_invocation_index(ctx->nctx);
4116 break;
4117 case nir_intrinsic_load_push_constant:
4118 result = visit_load_push_constant(ctx->nctx, instr);
4119 break;
4120 case nir_intrinsic_vulkan_resource_index:
4121 result = visit_vulkan_resource_index(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_store_ssbo:
4124 visit_store_ssbo(ctx, instr);
4125 break;
4126 case nir_intrinsic_load_ssbo:
4127 result = visit_load_buffer(ctx, instr);
4128 break;
4129 case nir_intrinsic_ssbo_atomic_add:
4130 case nir_intrinsic_ssbo_atomic_imin:
4131 case nir_intrinsic_ssbo_atomic_umin:
4132 case nir_intrinsic_ssbo_atomic_imax:
4133 case nir_intrinsic_ssbo_atomic_umax:
4134 case nir_intrinsic_ssbo_atomic_and:
4135 case nir_intrinsic_ssbo_atomic_or:
4136 case nir_intrinsic_ssbo_atomic_xor:
4137 case nir_intrinsic_ssbo_atomic_exchange:
4138 case nir_intrinsic_ssbo_atomic_comp_swap:
4139 result = visit_atomic_ssbo(ctx, instr);
4140 break;
4141 case nir_intrinsic_load_ubo:
4142 result = visit_load_ubo_buffer(ctx, instr);
4143 break;
4144 case nir_intrinsic_get_buffer_size:
4145 result = visit_get_buffer_size(ctx, instr);
4146 break;
4147 case nir_intrinsic_load_var:
4148 result = visit_load_var(ctx, instr);
4149 break;
4150 case nir_intrinsic_store_var:
4151 visit_store_var(ctx, instr);
4152 break;
4153 case nir_intrinsic_image_load:
4154 result = visit_image_load(ctx, instr);
4155 break;
4156 case nir_intrinsic_image_store:
4157 visit_image_store(ctx, instr);
4158 break;
4159 case nir_intrinsic_image_atomic_add:
4160 case nir_intrinsic_image_atomic_min:
4161 case nir_intrinsic_image_atomic_max:
4162 case nir_intrinsic_image_atomic_and:
4163 case nir_intrinsic_image_atomic_or:
4164 case nir_intrinsic_image_atomic_xor:
4165 case nir_intrinsic_image_atomic_exchange:
4166 case nir_intrinsic_image_atomic_comp_swap:
4167 result = visit_image_atomic(ctx, instr);
4168 break;
4169 case nir_intrinsic_image_size:
4170 result = visit_image_size(ctx, instr);
4171 break;
4172 case nir_intrinsic_discard:
4173 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4174 LLVMVoidTypeInContext(ctx->ac.context),
4175 NULL, 0, AC_FUNC_ATTR_LEGACY);
4176 break;
4177 case nir_intrinsic_discard_if:
4178 emit_discard_if(ctx, instr);
4179 break;
4180 case nir_intrinsic_memory_barrier:
4181 emit_waitcnt(ctx->nctx, VM_CNT);
4182 break;
4183 case nir_intrinsic_barrier:
4184 emit_barrier(ctx->nctx);
4185 break;
4186 case nir_intrinsic_var_atomic_add:
4187 case nir_intrinsic_var_atomic_imin:
4188 case nir_intrinsic_var_atomic_umin:
4189 case nir_intrinsic_var_atomic_imax:
4190 case nir_intrinsic_var_atomic_umax:
4191 case nir_intrinsic_var_atomic_and:
4192 case nir_intrinsic_var_atomic_or:
4193 case nir_intrinsic_var_atomic_xor:
4194 case nir_intrinsic_var_atomic_exchange:
4195 case nir_intrinsic_var_atomic_comp_swap:
4196 result = visit_var_atomic(ctx->nctx, instr);
4197 break;
4198 case nir_intrinsic_interp_var_at_centroid:
4199 case nir_intrinsic_interp_var_at_sample:
4200 case nir_intrinsic_interp_var_at_offset:
4201 result = visit_interp(ctx->nctx, instr);
4202 break;
4203 case nir_intrinsic_emit_vertex:
4204 visit_emit_vertex(ctx->nctx, instr);
4205 break;
4206 case nir_intrinsic_end_primitive:
4207 visit_end_primitive(ctx->nctx, instr);
4208 break;
4209 case nir_intrinsic_load_tess_coord:
4210 result = visit_load_tess_coord(ctx->nctx, instr);
4211 break;
4212 case nir_intrinsic_load_patch_vertices_in:
4213 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4214 break;
4215 default:
4216 fprintf(stderr, "Unknown intrinsic: ");
4217 nir_print_instr(&instr->instr, stderr);
4218 fprintf(stderr, "\n");
4219 break;
4220 }
4221 if (result) {
4222 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4223 }
4224 }
4225
4226 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4227 LLVMValueRef buffer, bool write)
4228 {
4229 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4230
4231 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4232 ctx->shader_info->fs.writes_memory = true;
4233
4234 return buffer;
4235 }
4236
4237 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4238 unsigned descriptor_set,
4239 unsigned base_index,
4240 unsigned constant_index,
4241 LLVMValueRef index,
4242 enum ac_descriptor_type desc_type,
4243 bool image, bool write)
4244 {
4245 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4246 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4247 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4248 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4249 unsigned offset = binding->offset;
4250 unsigned stride = binding->size;
4251 unsigned type_size;
4252 LLVMBuilderRef builder = ctx->builder;
4253 LLVMTypeRef type;
4254
4255 assert(base_index < layout->binding_count);
4256
4257 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4258 ctx->shader_info->fs.writes_memory = true;
4259
4260 switch (desc_type) {
4261 case AC_DESC_IMAGE:
4262 type = ctx->v8i32;
4263 type_size = 32;
4264 break;
4265 case AC_DESC_FMASK:
4266 type = ctx->v8i32;
4267 offset += 32;
4268 type_size = 32;
4269 break;
4270 case AC_DESC_SAMPLER:
4271 type = ctx->v4i32;
4272 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4273 offset += 64;
4274
4275 type_size = 16;
4276 break;
4277 case AC_DESC_BUFFER:
4278 type = ctx->v4i32;
4279 type_size = 16;
4280 break;
4281 default:
4282 unreachable("invalid desc_type\n");
4283 }
4284
4285 offset += constant_index * stride;
4286
4287 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4288 (!index || binding->immutable_samplers_equal)) {
4289 if (binding->immutable_samplers_equal)
4290 constant_index = 0;
4291
4292 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4293
4294 LLVMValueRef constants[] = {
4295 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4296 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4297 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4298 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4299 };
4300 return ac_build_gather_values(&ctx->ac, constants, 4);
4301 }
4302
4303 assert(stride % type_size == 0);
4304
4305 if (!index)
4306 index = ctx->ac.i32_0;
4307
4308 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4309
4310 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4311 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4312
4313 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4314 }
4315
4316 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4317 const nir_deref_var *deref,
4318 enum ac_descriptor_type desc_type,
4319 const nir_tex_instr *tex_instr,
4320 bool image, bool write)
4321 {
4322 LLVMValueRef index = NULL;
4323 unsigned constant_index = 0;
4324 unsigned descriptor_set;
4325 unsigned base_index;
4326
4327 if (!deref) {
4328 assert(tex_instr && !image);
4329 descriptor_set = 0;
4330 base_index = tex_instr->sampler_index;
4331 } else {
4332 const nir_deref *tail = &deref->deref;
4333 while (tail->child) {
4334 const nir_deref_array *child = nir_deref_as_array(tail->child);
4335 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4336
4337 if (!array_size)
4338 array_size = 1;
4339
4340 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4341
4342 if (child->deref_array_type == nir_deref_array_type_indirect) {
4343 LLVMValueRef indirect = get_src(ctx, child->indirect);
4344
4345 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4346 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4347
4348 if (!index)
4349 index = indirect;
4350 else
4351 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4352 }
4353
4354 constant_index += child->base_offset * array_size;
4355
4356 tail = &child->deref;
4357 }
4358 descriptor_set = deref->var->data.descriptor_set;
4359 base_index = deref->var->data.binding;
4360 }
4361
4362 return ctx->abi->load_sampler_desc(ctx->abi,
4363 descriptor_set,
4364 base_index,
4365 constant_index, index,
4366 desc_type, image, write);
4367 }
4368
4369 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4370 struct ac_image_args *args,
4371 const nir_tex_instr *instr,
4372 nir_texop op,
4373 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4374 LLVMValueRef *param, unsigned count,
4375 unsigned dmask)
4376 {
4377 unsigned is_rect = 0;
4378 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4379
4380 if (op == nir_texop_lod)
4381 da = false;
4382 /* Pad to power of two vector */
4383 while (count < util_next_power_of_two(count))
4384 param[count++] = LLVMGetUndef(ctx->i32);
4385
4386 if (count > 1)
4387 args->addr = ac_build_gather_values(ctx, param, count);
4388 else
4389 args->addr = param[0];
4390
4391 args->resource = res_ptr;
4392 args->sampler = samp_ptr;
4393
4394 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4395 args->addr = param[0];
4396 return;
4397 }
4398
4399 args->dmask = dmask;
4400 args->unorm = is_rect;
4401 args->da = da;
4402 }
4403
4404 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4405 *
4406 * SI-CI:
4407 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4408 * filtering manually. The driver sets img7 to a mask clearing
4409 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4410 * s_and_b32 samp0, samp0, img7
4411 *
4412 * VI:
4413 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4414 */
4415 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4416 LLVMValueRef res, LLVMValueRef samp)
4417 {
4418 LLVMBuilderRef builder = ctx->ac.builder;
4419 LLVMValueRef img7, samp0;
4420
4421 if (ctx->ac.chip_class >= VI)
4422 return samp;
4423
4424 img7 = LLVMBuildExtractElement(builder, res,
4425 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4426 samp0 = LLVMBuildExtractElement(builder, samp,
4427 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4428 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4429 return LLVMBuildInsertElement(builder, samp, samp0,
4430 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4431 }
4432
4433 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4434 nir_tex_instr *instr,
4435 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4436 LLVMValueRef *fmask_ptr)
4437 {
4438 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4439 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4440 else
4441 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4442 if (samp_ptr) {
4443 if (instr->sampler)
4444 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4445 else
4446 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4447 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4448 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4449 }
4450 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4451 instr->op == nir_texop_samples_identical))
4452 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4453 }
4454
4455 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4456 LLVMValueRef coord)
4457 {
4458 coord = ac_to_float(ctx, coord);
4459 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4460 coord = ac_to_integer(ctx, coord);
4461 return coord;
4462 }
4463
4464 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4465 {
4466 LLVMValueRef result = NULL;
4467 struct ac_image_args args = { 0 };
4468 unsigned dmask = 0xf;
4469 LLVMValueRef address[16];
4470 LLVMValueRef coords[5];
4471 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4472 LLVMValueRef bias = NULL, offsets = NULL;
4473 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4474 LLVMValueRef ddx = NULL, ddy = NULL;
4475 LLVMValueRef derivs[6];
4476 unsigned chan, count = 0;
4477 unsigned const_src = 0, num_deriv_comp = 0;
4478 bool lod_is_zero = false;
4479
4480 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4481
4482 for (unsigned i = 0; i < instr->num_srcs; i++) {
4483 switch (instr->src[i].src_type) {
4484 case nir_tex_src_coord:
4485 coord = get_src(ctx, instr->src[i].src);
4486 break;
4487 case nir_tex_src_projector:
4488 break;
4489 case nir_tex_src_comparator:
4490 comparator = get_src(ctx, instr->src[i].src);
4491 break;
4492 case nir_tex_src_offset:
4493 offsets = get_src(ctx, instr->src[i].src);
4494 const_src = i;
4495 break;
4496 case nir_tex_src_bias:
4497 bias = get_src(ctx, instr->src[i].src);
4498 break;
4499 case nir_tex_src_lod: {
4500 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4501
4502 if (val && val->i32[0] == 0)
4503 lod_is_zero = true;
4504 lod = get_src(ctx, instr->src[i].src);
4505 break;
4506 }
4507 case nir_tex_src_ms_index:
4508 sample_index = get_src(ctx, instr->src[i].src);
4509 break;
4510 case nir_tex_src_ms_mcs:
4511 break;
4512 case nir_tex_src_ddx:
4513 ddx = get_src(ctx, instr->src[i].src);
4514 num_deriv_comp = instr->src[i].src.ssa->num_components;
4515 break;
4516 case nir_tex_src_ddy:
4517 ddy = get_src(ctx, instr->src[i].src);
4518 break;
4519 case nir_tex_src_texture_offset:
4520 case nir_tex_src_sampler_offset:
4521 case nir_tex_src_plane:
4522 default:
4523 break;
4524 }
4525 }
4526
4527 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4528 result = get_buffer_size(ctx, res_ptr, true);
4529 goto write_result;
4530 }
4531
4532 if (instr->op == nir_texop_texture_samples) {
4533 LLVMValueRef res, samples, is_msaa;
4534 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4535 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4536 LLVMConstInt(ctx->ac.i32, 3, false), "");
4537 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4538 LLVMConstInt(ctx->ac.i32, 28, false), "");
4539 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4540 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4541 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4542 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4543
4544 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4545 LLVMConstInt(ctx->ac.i32, 16, false), "");
4546 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4547 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4548 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4549 samples, "");
4550 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4551 ctx->ac.i32_1, "");
4552 result = samples;
4553 goto write_result;
4554 }
4555
4556 if (coord)
4557 for (chan = 0; chan < instr->coord_components; chan++)
4558 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4559
4560 if (offsets && instr->op != nir_texop_txf) {
4561 LLVMValueRef offset[3], pack;
4562 for (chan = 0; chan < 3; ++chan)
4563 offset[chan] = ctx->ac.i32_0;
4564
4565 args.offset = true;
4566 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4567 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4568 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4569 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4570 if (chan)
4571 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4572 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4573 }
4574 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4575 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4576 address[count++] = pack;
4577
4578 }
4579 /* pack LOD bias value */
4580 if (instr->op == nir_texop_txb && bias) {
4581 address[count++] = bias;
4582 }
4583
4584 /* Pack depth comparison value */
4585 if (instr->is_shadow && comparator) {
4586 LLVMValueRef z = ac_to_float(&ctx->ac,
4587 llvm_extract_elem(&ctx->ac, comparator, 0));
4588
4589 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4590 * so the depth comparison value isn't clamped for Z16 and
4591 * Z24 anymore. Do it manually here.
4592 *
4593 * It's unnecessary if the original texture format was
4594 * Z32_FLOAT, but we don't know that here.
4595 */
4596 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4597 z = ac_build_clamp(&ctx->ac, z);
4598
4599 address[count++] = z;
4600 }
4601
4602 /* pack derivatives */
4603 if (ddx || ddy) {
4604 int num_src_deriv_channels, num_dest_deriv_channels;
4605 switch (instr->sampler_dim) {
4606 case GLSL_SAMPLER_DIM_3D:
4607 case GLSL_SAMPLER_DIM_CUBE:
4608 num_deriv_comp = 3;
4609 num_src_deriv_channels = 3;
4610 num_dest_deriv_channels = 3;
4611 break;
4612 case GLSL_SAMPLER_DIM_2D:
4613 default:
4614 num_src_deriv_channels = 2;
4615 num_dest_deriv_channels = 2;
4616 num_deriv_comp = 2;
4617 break;
4618 case GLSL_SAMPLER_DIM_1D:
4619 num_src_deriv_channels = 1;
4620 if (ctx->ac.chip_class >= GFX9) {
4621 num_dest_deriv_channels = 2;
4622 num_deriv_comp = 2;
4623 } else {
4624 num_dest_deriv_channels = 1;
4625 num_deriv_comp = 1;
4626 }
4627 break;
4628 }
4629
4630 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4631 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4632 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4633 }
4634 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4635 derivs[i] = ctx->ac.f32_0;
4636 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4637 }
4638 }
4639
4640 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4641 for (chan = 0; chan < instr->coord_components; chan++)
4642 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4643 if (instr->coord_components == 3)
4644 coords[3] = LLVMGetUndef(ctx->ac.f32);
4645 ac_prepare_cube_coords(&ctx->ac,
4646 instr->op == nir_texop_txd, instr->is_array,
4647 instr->op == nir_texop_lod, coords, derivs);
4648 if (num_deriv_comp)
4649 num_deriv_comp--;
4650 }
4651
4652 if (ddx || ddy) {
4653 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4654 address[count++] = derivs[i];
4655 }
4656
4657 /* Pack texture coordinates */
4658 if (coord) {
4659 address[count++] = coords[0];
4660 if (instr->coord_components > 1) {
4661 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4662 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4663 }
4664 address[count++] = coords[1];
4665 }
4666 if (instr->coord_components > 2) {
4667 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4668 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4669 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4670 instr->op != nir_texop_txf) {
4671 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4672 }
4673 address[count++] = coords[2];
4674 }
4675
4676 if (ctx->ac.chip_class >= GFX9) {
4677 LLVMValueRef filler;
4678 if (instr->op == nir_texop_txf)
4679 filler = ctx->ac.i32_0;
4680 else
4681 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4682
4683 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4684 /* No nir_texop_lod, because it does not take a slice
4685 * even with array textures. */
4686 if (instr->is_array && instr->op != nir_texop_lod ) {
4687 address[count] = address[count - 1];
4688 address[count - 1] = filler;
4689 count++;
4690 } else
4691 address[count++] = filler;
4692 }
4693 }
4694 }
4695
4696 /* Pack LOD */
4697 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4698 instr->op == nir_texop_txf)) {
4699 address[count++] = lod;
4700 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4701 address[count++] = sample_index;
4702 } else if(instr->op == nir_texop_txs) {
4703 count = 0;
4704 if (lod)
4705 address[count++] = lod;
4706 else
4707 address[count++] = ctx->ac.i32_0;
4708 }
4709
4710 for (chan = 0; chan < count; chan++) {
4711 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4712 address[chan], ctx->ac.i32, "");
4713 }
4714
4715 if (instr->op == nir_texop_samples_identical) {
4716 LLVMValueRef txf_address[4];
4717 struct ac_image_args txf_args = { 0 };
4718 unsigned txf_count = count;
4719 memcpy(txf_address, address, sizeof(txf_address));
4720
4721 if (!instr->is_array)
4722 txf_address[2] = ctx->ac.i32_0;
4723 txf_address[3] = ctx->ac.i32_0;
4724
4725 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4726 fmask_ptr, NULL,
4727 txf_address, txf_count, 0xf);
4728
4729 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4730
4731 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4732 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4733 goto write_result;
4734 }
4735
4736 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4737 instr->op != nir_texop_txs) {
4738 unsigned sample_chan = instr->is_array ? 3 : 2;
4739 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4740 address[0],
4741 address[1],
4742 instr->is_array ? address[2] : NULL,
4743 address[sample_chan],
4744 fmask_ptr);
4745 }
4746
4747 if (offsets && instr->op == nir_texop_txf) {
4748 nir_const_value *const_offset =
4749 nir_src_as_const_value(instr->src[const_src].src);
4750 int num_offsets = instr->src[const_src].src.ssa->num_components;
4751 assert(const_offset);
4752 num_offsets = MIN2(num_offsets, instr->coord_components);
4753 if (num_offsets > 2)
4754 address[2] = LLVMBuildAdd(ctx->ac.builder,
4755 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4756 if (num_offsets > 1)
4757 address[1] = LLVMBuildAdd(ctx->ac.builder,
4758 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4759 address[0] = LLVMBuildAdd(ctx->ac.builder,
4760 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4761
4762 }
4763
4764 /* TODO TG4 support */
4765 if (instr->op == nir_texop_tg4) {
4766 if (instr->is_shadow)
4767 dmask = 1;
4768 else
4769 dmask = 1 << instr->component;
4770 }
4771 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4772 res_ptr, samp_ptr, address, count, dmask);
4773
4774 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4775
4776 if (instr->op == nir_texop_query_levels)
4777 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4778 else if (instr->is_shadow && instr->is_new_style_shadow &&
4779 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4780 instr->op != nir_texop_tg4)
4781 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4782 else if (instr->op == nir_texop_txs &&
4783 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4784 instr->is_array) {
4785 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4786 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4787 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4788 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4789 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4790 } else if (ctx->ac.chip_class >= GFX9 &&
4791 instr->op == nir_texop_txs &&
4792 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4793 instr->is_array) {
4794 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4795 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4796 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4797 ctx->ac.i32_1, "");
4798 } else if (instr->dest.ssa.num_components != 4)
4799 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4800
4801 write_result:
4802 if (result) {
4803 assert(instr->dest.is_ssa);
4804 result = ac_to_integer(&ctx->ac, result);
4805 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4806 }
4807 }
4808
4809
4810 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4811 {
4812 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4813 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4814
4815 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4816 _mesa_hash_table_insert(ctx->phis, instr, result);
4817 }
4818
4819 static void visit_post_phi(struct ac_nir_context *ctx,
4820 nir_phi_instr *instr,
4821 LLVMValueRef llvm_phi)
4822 {
4823 nir_foreach_phi_src(src, instr) {
4824 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4825 LLVMValueRef llvm_src = get_src(ctx, src->src);
4826
4827 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4828 }
4829 }
4830
4831 static void phi_post_pass(struct ac_nir_context *ctx)
4832 {
4833 struct hash_entry *entry;
4834 hash_table_foreach(ctx->phis, entry) {
4835 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4836 (LLVMValueRef)entry->data);
4837 }
4838 }
4839
4840
4841 static void visit_ssa_undef(struct ac_nir_context *ctx,
4842 const nir_ssa_undef_instr *instr)
4843 {
4844 unsigned num_components = instr->def.num_components;
4845 LLVMValueRef undef;
4846
4847 if (num_components == 1)
4848 undef = LLVMGetUndef(ctx->ac.i32);
4849 else {
4850 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4851 }
4852 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4853 }
4854
4855 static void visit_jump(struct ac_nir_context *ctx,
4856 const nir_jump_instr *instr)
4857 {
4858 switch (instr->type) {
4859 case nir_jump_break:
4860 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4861 LLVMClearInsertionPosition(ctx->ac.builder);
4862 break;
4863 case nir_jump_continue:
4864 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4865 LLVMClearInsertionPosition(ctx->ac.builder);
4866 break;
4867 default:
4868 fprintf(stderr, "Unknown NIR jump instr: ");
4869 nir_print_instr(&instr->instr, stderr);
4870 fprintf(stderr, "\n");
4871 abort();
4872 }
4873 }
4874
4875 static void visit_cf_list(struct ac_nir_context *ctx,
4876 struct exec_list *list);
4877
4878 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4879 {
4880 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4881 nir_foreach_instr(instr, block)
4882 {
4883 switch (instr->type) {
4884 case nir_instr_type_alu:
4885 visit_alu(ctx, nir_instr_as_alu(instr));
4886 break;
4887 case nir_instr_type_load_const:
4888 visit_load_const(ctx, nir_instr_as_load_const(instr));
4889 break;
4890 case nir_instr_type_intrinsic:
4891 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4892 break;
4893 case nir_instr_type_tex:
4894 visit_tex(ctx, nir_instr_as_tex(instr));
4895 break;
4896 case nir_instr_type_phi:
4897 visit_phi(ctx, nir_instr_as_phi(instr));
4898 break;
4899 case nir_instr_type_ssa_undef:
4900 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4901 break;
4902 case nir_instr_type_jump:
4903 visit_jump(ctx, nir_instr_as_jump(instr));
4904 break;
4905 default:
4906 fprintf(stderr, "Unknown NIR instr type: ");
4907 nir_print_instr(instr, stderr);
4908 fprintf(stderr, "\n");
4909 abort();
4910 }
4911 }
4912
4913 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4914 }
4915
4916 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4917 {
4918 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4919
4920 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4921 LLVMBasicBlockRef merge_block =
4922 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4923 LLVMBasicBlockRef if_block =
4924 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4925 LLVMBasicBlockRef else_block = merge_block;
4926 if (!exec_list_is_empty(&if_stmt->else_list))
4927 else_block = LLVMAppendBasicBlockInContext(
4928 ctx->ac.context, fn, "");
4929
4930 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4931 LLVMConstInt(ctx->ac.i32, 0, false), "");
4932 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4933
4934 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4935 visit_cf_list(ctx, &if_stmt->then_list);
4936 if (LLVMGetInsertBlock(ctx->ac.builder))
4937 LLVMBuildBr(ctx->ac.builder, merge_block);
4938
4939 if (!exec_list_is_empty(&if_stmt->else_list)) {
4940 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4941 visit_cf_list(ctx, &if_stmt->else_list);
4942 if (LLVMGetInsertBlock(ctx->ac.builder))
4943 LLVMBuildBr(ctx->ac.builder, merge_block);
4944 }
4945
4946 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4947 }
4948
4949 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4950 {
4951 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4952 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4953 LLVMBasicBlockRef break_parent = ctx->break_block;
4954
4955 ctx->continue_block =
4956 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4957 ctx->break_block =
4958 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4959
4960 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4961 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4962 visit_cf_list(ctx, &loop->body);
4963
4964 if (LLVMGetInsertBlock(ctx->ac.builder))
4965 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4966 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4967
4968 ctx->continue_block = continue_parent;
4969 ctx->break_block = break_parent;
4970 }
4971
4972 static void visit_cf_list(struct ac_nir_context *ctx,
4973 struct exec_list *list)
4974 {
4975 foreach_list_typed(nir_cf_node, node, node, list)
4976 {
4977 switch (node->type) {
4978 case nir_cf_node_block:
4979 visit_block(ctx, nir_cf_node_as_block(node));
4980 break;
4981
4982 case nir_cf_node_if:
4983 visit_if(ctx, nir_cf_node_as_if(node));
4984 break;
4985
4986 case nir_cf_node_loop:
4987 visit_loop(ctx, nir_cf_node_as_loop(node));
4988 break;
4989
4990 default:
4991 assert(0);
4992 }
4993 }
4994 }
4995
4996 static void
4997 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4998 struct nir_variable *variable)
4999 {
5000 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5001 LLVMValueRef t_offset;
5002 LLVMValueRef t_list;
5003 LLVMValueRef input;
5004 LLVMValueRef buffer_index;
5005 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5006 int idx = variable->data.location;
5007 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5008
5009 variable->data.driver_location = idx * 4;
5010
5011 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5012 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5013 ctx->abi.start_instance, "");
5014 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5015 ctx->shader_info->vs.vgpr_comp_cnt);
5016 } else
5017 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5018 ctx->abi.base_vertex, "");
5019
5020 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5021 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5022
5023 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5024
5025 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5026 buffer_index,
5027 LLVMConstInt(ctx->ac.i32, 0, false),
5028 true);
5029
5030 for (unsigned chan = 0; chan < 4; chan++) {
5031 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5032 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5033 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5034 input, llvm_chan, ""));
5035 }
5036 }
5037 }
5038
5039 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5040 unsigned attr,
5041 LLVMValueRef interp_param,
5042 LLVMValueRef prim_mask,
5043 LLVMValueRef result[4])
5044 {
5045 LLVMValueRef attr_number;
5046 unsigned chan;
5047 LLVMValueRef i, j;
5048 bool interp = interp_param != NULL;
5049
5050 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5051
5052 /* fs.constant returns the param from the middle vertex, so it's not
5053 * really useful for flat shading. It's meant to be used for custom
5054 * interpolation (but the intrinsic can't fetch from the other two
5055 * vertices).
5056 *
5057 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5058 * to do the right thing. The only reason we use fs.constant is that
5059 * fs.interp cannot be used on integers, because they can be equal
5060 * to NaN.
5061 */
5062 if (interp) {
5063 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5064 LLVMVectorType(ctx->f32, 2), "");
5065
5066 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5067 ctx->ac.i32_0, "");
5068 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5069 ctx->ac.i32_1, "");
5070 }
5071
5072 for (chan = 0; chan < 4; chan++) {
5073 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5074
5075 if (interp) {
5076 result[chan] = ac_build_fs_interp(&ctx->ac,
5077 llvm_chan,
5078 attr_number,
5079 prim_mask, i, j);
5080 } else {
5081 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5082 LLVMConstInt(ctx->ac.i32, 2, false),
5083 llvm_chan,
5084 attr_number,
5085 prim_mask);
5086 }
5087 }
5088 }
5089
5090 static void
5091 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5092 struct nir_variable *variable)
5093 {
5094 int idx = variable->data.location;
5095 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5096 LLVMValueRef interp;
5097
5098 variable->data.driver_location = idx * 4;
5099 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5100
5101 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5102 unsigned interp_type;
5103 if (variable->data.sample) {
5104 interp_type = INTERP_SAMPLE;
5105 ctx->shader_info->info.ps.force_persample = true;
5106 } else if (variable->data.centroid)
5107 interp_type = INTERP_CENTROID;
5108 else
5109 interp_type = INTERP_CENTER;
5110
5111 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5112 } else
5113 interp = NULL;
5114
5115 for (unsigned i = 0; i < attrib_count; ++i)
5116 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5117
5118 }
5119
5120 static void
5121 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5122 struct nir_shader *nir) {
5123 nir_foreach_variable(variable, &nir->inputs)
5124 handle_vs_input_decl(ctx, variable);
5125 }
5126
5127 static void
5128 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5129 struct nir_shader *nir)
5130 {
5131 if (!ctx->options->key.fs.multisample)
5132 return;
5133
5134 bool uses_center = false;
5135 bool uses_centroid = false;
5136 nir_foreach_variable(variable, &nir->inputs) {
5137 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5138 variable->data.sample)
5139 continue;
5140
5141 if (variable->data.centroid)
5142 uses_centroid = true;
5143 else
5144 uses_center = true;
5145 }
5146
5147 if (uses_center && uses_centroid) {
5148 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5149 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5150 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5151 }
5152 }
5153
5154 static void
5155 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5156 struct nir_shader *nir)
5157 {
5158 prepare_interp_optimize(ctx, nir);
5159
5160 nir_foreach_variable(variable, &nir->inputs)
5161 handle_fs_input_decl(ctx, variable);
5162
5163 unsigned index = 0;
5164
5165 if (ctx->shader_info->info.ps.uses_input_attachments ||
5166 ctx->shader_info->info.needs_multiview_view_index)
5167 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5168
5169 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5170 LLVMValueRef interp_param;
5171 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5172
5173 if (!(ctx->input_mask & (1ull << i)))
5174 continue;
5175
5176 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5177 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5178 interp_param = *inputs;
5179 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5180 inputs);
5181
5182 if (!interp_param)
5183 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5184 ++index;
5185 } else if (i == VARYING_SLOT_POS) {
5186 for(int i = 0; i < 3; ++i)
5187 inputs[i] = ctx->abi.frag_pos[i];
5188
5189 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5190 ctx->abi.frag_pos[3]);
5191 }
5192 }
5193 ctx->shader_info->fs.num_interp = index;
5194 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5195 ctx->shader_info->fs.has_pcoord = true;
5196 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5197 ctx->shader_info->fs.prim_id_input = true;
5198 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5199 ctx->shader_info->fs.layer_input = true;
5200 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5201
5202 if (ctx->shader_info->info.needs_multiview_view_index)
5203 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5204 }
5205
5206 static LLVMValueRef
5207 ac_build_alloca(struct ac_llvm_context *ac,
5208 LLVMTypeRef type,
5209 const char *name)
5210 {
5211 LLVMBuilderRef builder = ac->builder;
5212 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5213 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5214 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5215 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5216 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5217 LLVMValueRef res;
5218
5219 if (first_instr) {
5220 LLVMPositionBuilderBefore(first_builder, first_instr);
5221 } else {
5222 LLVMPositionBuilderAtEnd(first_builder, first_block);
5223 }
5224
5225 res = LLVMBuildAlloca(first_builder, type, name);
5226 LLVMBuildStore(builder, LLVMConstNull(type), res);
5227
5228 LLVMDisposeBuilder(first_builder);
5229
5230 return res;
5231 }
5232
5233 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5234 LLVMTypeRef type,
5235 const char *name)
5236 {
5237 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5238 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5239 return ptr;
5240 }
5241
5242 static void
5243 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5244 struct nir_variable *variable,
5245 struct nir_shader *shader,
5246 gl_shader_stage stage)
5247 {
5248 int idx = variable->data.location + variable->data.index;
5249 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5250 uint64_t mask_attribs;
5251
5252 variable->data.driver_location = idx * 4;
5253
5254 /* tess ctrl has it's own load/store paths for outputs */
5255 if (stage == MESA_SHADER_TESS_CTRL)
5256 return;
5257
5258 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5259 if (stage == MESA_SHADER_VERTEX ||
5260 stage == MESA_SHADER_TESS_EVAL ||
5261 stage == MESA_SHADER_GEOMETRY) {
5262 if (idx == VARYING_SLOT_CLIP_DIST0) {
5263 int length = shader->info.clip_distance_array_size +
5264 shader->info.cull_distance_array_size;
5265 if (stage == MESA_SHADER_VERTEX) {
5266 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5267 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5268 }
5269 if (stage == MESA_SHADER_TESS_EVAL) {
5270 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5271 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5272 }
5273
5274 if (length > 4)
5275 attrib_count = 2;
5276 else
5277 attrib_count = 1;
5278 mask_attribs = 1ull << idx;
5279 }
5280 }
5281
5282 ctx->output_mask |= mask_attribs;
5283 }
5284
5285 static void
5286 handle_shader_output_decl(struct ac_nir_context *ctx,
5287 struct nir_shader *nir,
5288 struct nir_variable *variable)
5289 {
5290 unsigned output_loc = variable->data.driver_location / 4;
5291 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5292
5293 /* tess ctrl has it's own load/store paths for outputs */
5294 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5295 return;
5296
5297 if (ctx->stage == MESA_SHADER_VERTEX ||
5298 ctx->stage == MESA_SHADER_TESS_EVAL ||
5299 ctx->stage == MESA_SHADER_GEOMETRY) {
5300 int idx = variable->data.location + variable->data.index;
5301 if (idx == VARYING_SLOT_CLIP_DIST0) {
5302 int length = nir->info.clip_distance_array_size +
5303 nir->info.cull_distance_array_size;
5304
5305 if (length > 4)
5306 attrib_count = 2;
5307 else
5308 attrib_count = 1;
5309 }
5310 }
5311
5312 for (unsigned i = 0; i < attrib_count; ++i) {
5313 for (unsigned chan = 0; chan < 4; chan++) {
5314 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5315 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5316 }
5317 }
5318 }
5319
5320 static LLVMTypeRef
5321 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5322 enum glsl_base_type type)
5323 {
5324 switch (type) {
5325 case GLSL_TYPE_INT:
5326 case GLSL_TYPE_UINT:
5327 case GLSL_TYPE_BOOL:
5328 case GLSL_TYPE_SUBROUTINE:
5329 return ctx->ac.i32;
5330 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5331 return ctx->f32;
5332 case GLSL_TYPE_INT64:
5333 case GLSL_TYPE_UINT64:
5334 return ctx->i64;
5335 case GLSL_TYPE_DOUBLE:
5336 return ctx->f64;
5337 default:
5338 unreachable("unknown GLSL type");
5339 }
5340 }
5341
5342 static LLVMTypeRef
5343 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5344 const struct glsl_type *type)
5345 {
5346 if (glsl_type_is_scalar(type)) {
5347 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5348 }
5349
5350 if (glsl_type_is_vector(type)) {
5351 return LLVMVectorType(
5352 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5353 glsl_get_vector_elements(type));
5354 }
5355
5356 if (glsl_type_is_matrix(type)) {
5357 return LLVMArrayType(
5358 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5359 glsl_get_matrix_columns(type));
5360 }
5361
5362 if (glsl_type_is_array(type)) {
5363 return LLVMArrayType(
5364 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5365 glsl_get_length(type));
5366 }
5367
5368 assert(glsl_type_is_struct(type));
5369
5370 LLVMTypeRef member_types[glsl_get_length(type)];
5371
5372 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5373 member_types[i] =
5374 glsl_to_llvm_type(ctx,
5375 glsl_get_struct_field(type, i));
5376 }
5377
5378 return LLVMStructTypeInContext(ctx->context, member_types,
5379 glsl_get_length(type), false);
5380 }
5381
5382 static void
5383 setup_locals(struct ac_nir_context *ctx,
5384 struct nir_function *func)
5385 {
5386 int i, j;
5387 ctx->num_locals = 0;
5388 nir_foreach_variable(variable, &func->impl->locals) {
5389 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5390 variable->data.driver_location = ctx->num_locals * 4;
5391 ctx->num_locals += attrib_count;
5392 }
5393 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5394 if (!ctx->locals)
5395 return;
5396
5397 for (i = 0; i < ctx->num_locals; i++) {
5398 for (j = 0; j < 4; j++) {
5399 ctx->locals[i * 4 + j] =
5400 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5401 }
5402 }
5403 }
5404
5405 static void
5406 setup_shared(struct ac_nir_context *ctx,
5407 struct nir_shader *nir)
5408 {
5409 nir_foreach_variable(variable, &nir->shared) {
5410 LLVMValueRef shared =
5411 LLVMAddGlobalInAddressSpace(
5412 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5413 variable->name ? variable->name : "",
5414 LOCAL_ADDR_SPACE);
5415 _mesa_hash_table_insert(ctx->vars, variable, shared);
5416 }
5417 }
5418
5419 static LLVMValueRef
5420 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5421 {
5422 v = ac_to_float(ctx, v);
5423 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5424 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5425 }
5426
5427
5428 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5429 LLVMValueRef src0, LLVMValueRef src1)
5430 {
5431 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5432 LLVMValueRef comp[2];
5433
5434 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5435 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5436 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5437 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5438 }
5439
5440 /* Initialize arguments for the shader export intrinsic */
5441 static void
5442 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5443 LLVMValueRef *values,
5444 unsigned target,
5445 struct ac_export_args *args)
5446 {
5447 /* Default is 0xf. Adjusted below depending on the format. */
5448 args->enabled_channels = 0xf;
5449
5450 /* Specify whether the EXEC mask represents the valid mask */
5451 args->valid_mask = 0;
5452
5453 /* Specify whether this is the last export */
5454 args->done = 0;
5455
5456 /* Specify the target we are exporting */
5457 args->target = target;
5458
5459 args->compr = false;
5460 args->out[0] = LLVMGetUndef(ctx->f32);
5461 args->out[1] = LLVMGetUndef(ctx->f32);
5462 args->out[2] = LLVMGetUndef(ctx->f32);
5463 args->out[3] = LLVMGetUndef(ctx->f32);
5464
5465 if (!values)
5466 return;
5467
5468 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5469 LLVMValueRef val[4];
5470 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5471 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5472 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5473 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5474
5475 switch(col_format) {
5476 case V_028714_SPI_SHADER_ZERO:
5477 args->enabled_channels = 0; /* writemask */
5478 args->target = V_008DFC_SQ_EXP_NULL;
5479 break;
5480
5481 case V_028714_SPI_SHADER_32_R:
5482 args->enabled_channels = 1;
5483 args->out[0] = values[0];
5484 break;
5485
5486 case V_028714_SPI_SHADER_32_GR:
5487 args->enabled_channels = 0x3;
5488 args->out[0] = values[0];
5489 args->out[1] = values[1];
5490 break;
5491
5492 case V_028714_SPI_SHADER_32_AR:
5493 args->enabled_channels = 0x9;
5494 args->out[0] = values[0];
5495 args->out[3] = values[3];
5496 break;
5497
5498 case V_028714_SPI_SHADER_FP16_ABGR:
5499 args->compr = 1;
5500
5501 for (unsigned chan = 0; chan < 2; chan++) {
5502 LLVMValueRef pack_args[2] = {
5503 values[2 * chan],
5504 values[2 * chan + 1]
5505 };
5506 LLVMValueRef packed;
5507
5508 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5509 args->out[chan] = packed;
5510 }
5511 break;
5512
5513 case V_028714_SPI_SHADER_UNORM16_ABGR:
5514 for (unsigned chan = 0; chan < 4; chan++) {
5515 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5516 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5517 LLVMConstReal(ctx->f32, 65535), "");
5518 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5519 LLVMConstReal(ctx->f32, 0.5), "");
5520 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5521 ctx->ac.i32, "");
5522 }
5523
5524 args->compr = 1;
5525 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5526 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5527 break;
5528
5529 case V_028714_SPI_SHADER_SNORM16_ABGR:
5530 for (unsigned chan = 0; chan < 4; chan++) {
5531 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5532 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5533 LLVMConstReal(ctx->f32, 32767), "");
5534
5535 /* If positive, add 0.5, else add -0.5. */
5536 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5537 LLVMBuildSelect(ctx->builder,
5538 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5539 val[chan], ctx->ac.f32_0, ""),
5540 LLVMConstReal(ctx->f32, 0.5),
5541 LLVMConstReal(ctx->f32, -0.5), ""), "");
5542 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5543 }
5544
5545 args->compr = 1;
5546 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5547 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5548 break;
5549
5550 case V_028714_SPI_SHADER_UINT16_ABGR: {
5551 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5552 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5553 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5554
5555 for (unsigned chan = 0; chan < 4; chan++) {
5556 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5557 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5558 }
5559
5560 args->compr = 1;
5561 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5562 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5563 break;
5564 }
5565
5566 case V_028714_SPI_SHADER_SINT16_ABGR: {
5567 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5568 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5569 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5570 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5571 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5572 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5573
5574 /* Clamp. */
5575 for (unsigned chan = 0; chan < 4; chan++) {
5576 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5577 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5578 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5579 }
5580
5581 args->compr = 1;
5582 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5583 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5584 break;
5585 }
5586
5587 default:
5588 case V_028714_SPI_SHADER_32_ABGR:
5589 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5590 break;
5591 }
5592 } else
5593 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5594
5595 for (unsigned i = 0; i < 4; ++i)
5596 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5597 }
5598
5599 static void
5600 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5601 bool export_prim_id,
5602 struct ac_vs_output_info *outinfo)
5603 {
5604 uint32_t param_count = 0;
5605 unsigned target;
5606 unsigned pos_idx, num_pos_exports = 0;
5607 struct ac_export_args args, pos_args[4] = {};
5608 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5609 int i;
5610
5611 if (ctx->options->key.has_multiview_view_index) {
5612 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5613 if(!*tmp_out) {
5614 for(unsigned i = 0; i < 4; ++i)
5615 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5616 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5617 }
5618
5619 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5620 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5621 }
5622
5623 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5624 sizeof(outinfo->vs_output_param_offset));
5625
5626 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5627 LLVMValueRef slots[8];
5628 unsigned j;
5629
5630 if (outinfo->cull_dist_mask)
5631 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5632
5633 i = VARYING_SLOT_CLIP_DIST0;
5634 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5635 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5636 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5637
5638 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5639 slots[i] = LLVMGetUndef(ctx->f32);
5640
5641 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5642 target = V_008DFC_SQ_EXP_POS + 3;
5643 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5644 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5645 &args, sizeof(args));
5646 }
5647
5648 target = V_008DFC_SQ_EXP_POS + 2;
5649 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5650 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5651 &args, sizeof(args));
5652
5653 }
5654
5655 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5656 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5657 for (unsigned j = 0; j < 4; j++)
5658 pos_values[j] = LLVMBuildLoad(ctx->builder,
5659 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5660 }
5661 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5662
5663 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5664 outinfo->writes_pointsize = true;
5665 psize_value = LLVMBuildLoad(ctx->builder,
5666 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5667 }
5668
5669 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5670 outinfo->writes_layer = true;
5671 layer_value = LLVMBuildLoad(ctx->builder,
5672 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5673 }
5674
5675 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5676 outinfo->writes_viewport_index = true;
5677 viewport_index_value = LLVMBuildLoad(ctx->builder,
5678 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5679 }
5680
5681 if (outinfo->writes_pointsize ||
5682 outinfo->writes_layer ||
5683 outinfo->writes_viewport_index) {
5684 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5685 (outinfo->writes_layer == true ? 4 : 0));
5686 pos_args[1].valid_mask = 0;
5687 pos_args[1].done = 0;
5688 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5689 pos_args[1].compr = 0;
5690 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5691 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5692 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5693 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5694
5695 if (outinfo->writes_pointsize == true)
5696 pos_args[1].out[0] = psize_value;
5697 if (outinfo->writes_layer == true)
5698 pos_args[1].out[2] = layer_value;
5699 if (outinfo->writes_viewport_index == true) {
5700 if (ctx->options->chip_class >= GFX9) {
5701 /* GFX9 has the layer in out.z[10:0] and the viewport
5702 * index in out.z[19:16].
5703 */
5704 LLVMValueRef v = viewport_index_value;
5705 v = ac_to_integer(&ctx->ac, v);
5706 v = LLVMBuildShl(ctx->builder, v,
5707 LLVMConstInt(ctx->ac.i32, 16, false),
5708 "");
5709 v = LLVMBuildOr(ctx->builder, v,
5710 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5711
5712 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5713 pos_args[1].enabled_channels |= 1 << 2;
5714 } else {
5715 pos_args[1].out[3] = viewport_index_value;
5716 pos_args[1].enabled_channels |= 1 << 3;
5717 }
5718 }
5719 }
5720 for (i = 0; i < 4; i++) {
5721 if (pos_args[i].out[0])
5722 num_pos_exports++;
5723 }
5724
5725 pos_idx = 0;
5726 for (i = 0; i < 4; i++) {
5727 if (!pos_args[i].out[0])
5728 continue;
5729
5730 /* Specify the target we are exporting */
5731 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5732 if (pos_idx == num_pos_exports)
5733 pos_args[i].done = 1;
5734 ac_build_export(&ctx->ac, &pos_args[i]);
5735 }
5736
5737 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5738 LLVMValueRef values[4];
5739 if (!(ctx->output_mask & (1ull << i)))
5740 continue;
5741
5742 for (unsigned j = 0; j < 4; j++)
5743 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5744 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5745
5746 if (i == VARYING_SLOT_LAYER) {
5747 target = V_008DFC_SQ_EXP_PARAM + param_count;
5748 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5749 param_count++;
5750 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5751 target = V_008DFC_SQ_EXP_PARAM + param_count;
5752 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5753 param_count++;
5754 } else if (i >= VARYING_SLOT_VAR0) {
5755 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5756 target = V_008DFC_SQ_EXP_PARAM + param_count;
5757 outinfo->vs_output_param_offset[i] = param_count;
5758 param_count++;
5759 } else
5760 continue;
5761
5762 si_llvm_init_export_args(ctx, values, target, &args);
5763
5764 if (target >= V_008DFC_SQ_EXP_POS &&
5765 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5766 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5767 &args, sizeof(args));
5768 } else {
5769 ac_build_export(&ctx->ac, &args);
5770 }
5771 }
5772
5773 if (export_prim_id) {
5774 LLVMValueRef values[4];
5775 target = V_008DFC_SQ_EXP_PARAM + param_count;
5776 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5777 param_count++;
5778
5779 values[0] = ctx->vs_prim_id;
5780 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5781 ctx->shader_info->vs.vgpr_comp_cnt);
5782 for (unsigned j = 1; j < 4; j++)
5783 values[j] = ctx->ac.f32_0;
5784 si_llvm_init_export_args(ctx, values, target, &args);
5785 ac_build_export(&ctx->ac, &args);
5786 outinfo->export_prim_id = true;
5787 }
5788
5789 outinfo->pos_exports = num_pos_exports;
5790 outinfo->param_exports = param_count;
5791 }
5792
5793 static void
5794 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5795 struct ac_es_output_info *outinfo)
5796 {
5797 int j;
5798 uint64_t max_output_written = 0;
5799 LLVMValueRef lds_base = NULL;
5800
5801 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5802 int param_index;
5803 int length = 4;
5804
5805 if (!(ctx->output_mask & (1ull << i)))
5806 continue;
5807
5808 if (i == VARYING_SLOT_CLIP_DIST0)
5809 length = ctx->num_output_clips + ctx->num_output_culls;
5810
5811 param_index = shader_io_get_unique_index(i);
5812
5813 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5814 }
5815
5816 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5817
5818 if (ctx->ac.chip_class >= GFX9) {
5819 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5820 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5821 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5822 LLVMConstInt(ctx->ac.i32, 24, false),
5823 LLVMConstInt(ctx->ac.i32, 4, false), false);
5824 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5825 LLVMBuildMul(ctx->ac.builder, wave_idx,
5826 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5827 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5828 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5829 }
5830
5831 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5832 LLVMValueRef dw_addr;
5833 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5834 int param_index;
5835 int length = 4;
5836
5837 if (!(ctx->output_mask & (1ull << i)))
5838 continue;
5839
5840 if (i == VARYING_SLOT_CLIP_DIST0)
5841 length = ctx->num_output_clips + ctx->num_output_culls;
5842
5843 param_index = shader_io_get_unique_index(i);
5844
5845 if (lds_base) {
5846 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5847 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5848 "");
5849 }
5850 for (j = 0; j < length; j++) {
5851 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5852 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5853
5854 if (ctx->ac.chip_class >= GFX9) {
5855 ac_lds_store(&ctx->ac, dw_addr,
5856 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5857 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5858 } else {
5859 ac_build_buffer_store_dword(&ctx->ac,
5860 ctx->esgs_ring,
5861 out_val, 1,
5862 NULL, ctx->es2gs_offset,
5863 (4 * param_index + j) * 4,
5864 1, 1, true, true);
5865 }
5866 }
5867 }
5868 }
5869
5870 static void
5871 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5872 {
5873 LLVMValueRef vertex_id = ctx->rel_auto_id;
5874 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5875 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5876 vertex_dw_stride, "");
5877
5878 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5879 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5880 int length = 4;
5881
5882 if (!(ctx->output_mask & (1ull << i)))
5883 continue;
5884
5885 if (i == VARYING_SLOT_CLIP_DIST0)
5886 length = ctx->num_output_clips + ctx->num_output_culls;
5887 int param = shader_io_get_unique_index(i);
5888 mark_tess_output(ctx, false, param);
5889 if (length > 4)
5890 mark_tess_output(ctx, false, param + 1);
5891 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5892 LLVMConstInt(ctx->ac.i32, param * 4, false),
5893 "");
5894 for (unsigned j = 0; j < length; j++) {
5895 ac_lds_store(&ctx->ac, dw_addr,
5896 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5897 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5898 }
5899 }
5900 }
5901
5902 struct ac_build_if_state
5903 {
5904 struct nir_to_llvm_context *ctx;
5905 LLVMValueRef condition;
5906 LLVMBasicBlockRef entry_block;
5907 LLVMBasicBlockRef true_block;
5908 LLVMBasicBlockRef false_block;
5909 LLVMBasicBlockRef merge_block;
5910 };
5911
5912 static LLVMBasicBlockRef
5913 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5914 {
5915 LLVMBasicBlockRef current_block;
5916 LLVMBasicBlockRef next_block;
5917 LLVMBasicBlockRef new_block;
5918
5919 /* get current basic block */
5920 current_block = LLVMGetInsertBlock(ctx->builder);
5921
5922 /* chqeck if there's another block after this one */
5923 next_block = LLVMGetNextBasicBlock(current_block);
5924 if (next_block) {
5925 /* insert the new block before the next block */
5926 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5927 }
5928 else {
5929 /* append new block after current block */
5930 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5931 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5932 }
5933 return new_block;
5934 }
5935
5936 static void
5937 ac_nir_build_if(struct ac_build_if_state *ifthen,
5938 struct nir_to_llvm_context *ctx,
5939 LLVMValueRef condition)
5940 {
5941 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5942
5943 memset(ifthen, 0, sizeof *ifthen);
5944 ifthen->ctx = ctx;
5945 ifthen->condition = condition;
5946 ifthen->entry_block = block;
5947
5948 /* create endif/merge basic block for the phi functions */
5949 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5950
5951 /* create/insert true_block before merge_block */
5952 ifthen->true_block =
5953 LLVMInsertBasicBlockInContext(ctx->context,
5954 ifthen->merge_block,
5955 "if-true-block");
5956
5957 /* successive code goes into the true block */
5958 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5959 }
5960
5961 /**
5962 * End a conditional.
5963 */
5964 static void
5965 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5966 {
5967 LLVMBuilderRef builder = ifthen->ctx->builder;
5968
5969 /* Insert branch to the merge block from current block */
5970 LLVMBuildBr(builder, ifthen->merge_block);
5971
5972 /*
5973 * Now patch in the various branch instructions.
5974 */
5975
5976 /* Insert the conditional branch instruction at the end of entry_block */
5977 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5978 if (ifthen->false_block) {
5979 /* we have an else clause */
5980 LLVMBuildCondBr(builder, ifthen->condition,
5981 ifthen->true_block, ifthen->false_block);
5982 }
5983 else {
5984 /* no else clause */
5985 LLVMBuildCondBr(builder, ifthen->condition,
5986 ifthen->true_block, ifthen->merge_block);
5987 }
5988
5989 /* Resume building code at end of the ifthen->merge_block */
5990 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5991 }
5992
5993 static void
5994 write_tess_factors(struct nir_to_llvm_context *ctx)
5995 {
5996 unsigned stride, outer_comps, inner_comps;
5997 struct ac_build_if_state if_ctx, inner_if_ctx;
5998 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5999 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6000 unsigned tess_inner_index, tess_outer_index;
6001 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6002 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6003 int i;
6004 emit_barrier(ctx);
6005
6006 switch (ctx->options->key.tcs.primitive_mode) {
6007 case GL_ISOLINES:
6008 stride = 2;
6009 outer_comps = 2;
6010 inner_comps = 0;
6011 break;
6012 case GL_TRIANGLES:
6013 stride = 4;
6014 outer_comps = 3;
6015 inner_comps = 1;
6016 break;
6017 case GL_QUADS:
6018 stride = 6;
6019 outer_comps = 4;
6020 inner_comps = 2;
6021 break;
6022 default:
6023 return;
6024 }
6025
6026 ac_nir_build_if(&if_ctx, ctx,
6027 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6028 invocation_id, ctx->ac.i32_0, ""));
6029
6030 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6031 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6032
6033 mark_tess_output(ctx, true, tess_inner_index);
6034 mark_tess_output(ctx, true, tess_outer_index);
6035 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6036 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6037 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6038 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6039 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6040
6041 for (i = 0; i < 4; i++) {
6042 inner[i] = LLVMGetUndef(ctx->ac.i32);
6043 outer[i] = LLVMGetUndef(ctx->ac.i32);
6044 }
6045
6046 // LINES reverseal
6047 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6048 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6049 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6050 LLVMConstInt(ctx->ac.i32, 1, false), "");
6051 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6052 } else {
6053 for (i = 0; i < outer_comps; i++) {
6054 outer[i] = out[i] =
6055 ac_lds_load(&ctx->ac, lds_outer);
6056 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6057 LLVMConstInt(ctx->ac.i32, 1, false), "");
6058 }
6059 for (i = 0; i < inner_comps; i++) {
6060 inner[i] = out[outer_comps+i] =
6061 ac_lds_load(&ctx->ac, lds_inner);
6062 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6063 LLVMConstInt(ctx->ac.i32, 1, false), "");
6064 }
6065 }
6066
6067 /* Convert the outputs to vectors for stores. */
6068 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6069 vec1 = NULL;
6070
6071 if (stride > 4)
6072 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6073
6074
6075 buffer = ctx->hs_ring_tess_factor;
6076 tf_base = ctx->tess_factor_offset;
6077 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6078 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6079 unsigned tf_offset = 0;
6080
6081 if (ctx->options->chip_class <= VI) {
6082 ac_nir_build_if(&inner_if_ctx, ctx,
6083 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6084 rel_patch_id, ctx->ac.i32_0, ""));
6085
6086 /* Store the dynamic HS control word. */
6087 ac_build_buffer_store_dword(&ctx->ac, buffer,
6088 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6089 1, ctx->ac.i32_0, tf_base,
6090 0, 1, 0, true, false);
6091 tf_offset += 4;
6092
6093 ac_nir_build_endif(&inner_if_ctx);
6094 }
6095
6096 /* Store the tessellation factors. */
6097 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6098 MIN2(stride, 4), byteoffset, tf_base,
6099 tf_offset, 1, 0, true, false);
6100 if (vec1)
6101 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6102 stride - 4, byteoffset, tf_base,
6103 16 + tf_offset, 1, 0, true, false);
6104
6105 //store to offchip for TES to read - only if TES reads them
6106 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6107 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6108 LLVMValueRef tf_inner_offset;
6109 unsigned param_outer, param_inner;
6110
6111 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6112 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6113 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6114
6115 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6116 util_next_power_of_two(outer_comps));
6117
6118 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6119 outer_comps, tf_outer_offset,
6120 ctx->oc_lds, 0, 1, 0, true, false);
6121 if (inner_comps) {
6122 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6123 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6124 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6125
6126 inner_vec = inner_comps == 1 ? inner[0] :
6127 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6128 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6129 inner_comps, tf_inner_offset,
6130 ctx->oc_lds, 0, 1, 0, true, false);
6131 }
6132 }
6133 ac_nir_build_endif(&if_ctx);
6134 }
6135
6136 static void
6137 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6138 {
6139 write_tess_factors(ctx);
6140 }
6141
6142 static bool
6143 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6144 LLVMValueRef *color, unsigned param, bool is_last,
6145 struct ac_export_args *args)
6146 {
6147 /* Export */
6148 si_llvm_init_export_args(ctx, color, param,
6149 args);
6150
6151 if (is_last) {
6152 args->valid_mask = 1; /* whether the EXEC mask is valid */
6153 args->done = 1; /* DONE bit */
6154 } else if (!args->enabled_channels)
6155 return false; /* unnecessary NULL export */
6156
6157 return true;
6158 }
6159
6160 static void
6161 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6162 LLVMValueRef depth, LLVMValueRef stencil,
6163 LLVMValueRef samplemask)
6164 {
6165 struct ac_export_args args;
6166
6167 args.enabled_channels = 0;
6168 args.valid_mask = 1;
6169 args.done = 1;
6170 args.target = V_008DFC_SQ_EXP_MRTZ;
6171 args.compr = false;
6172
6173 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6174 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6175 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6176 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6177
6178 if (depth) {
6179 args.out[0] = depth;
6180 args.enabled_channels |= 0x1;
6181 }
6182
6183 if (stencil) {
6184 args.out[1] = stencil;
6185 args.enabled_channels |= 0x2;
6186 }
6187
6188 if (samplemask) {
6189 args.out[2] = samplemask;
6190 args.enabled_channels |= 0x4;
6191 }
6192
6193 /* SI (except OLAND and HAINAN) has a bug that it only looks
6194 * at the X writemask component. */
6195 if (ctx->options->chip_class == SI &&
6196 ctx->options->family != CHIP_OLAND &&
6197 ctx->options->family != CHIP_HAINAN)
6198 args.enabled_channels |= 0x1;
6199
6200 ac_build_export(&ctx->ac, &args);
6201 }
6202
6203 static void
6204 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6205 {
6206 unsigned index = 0;
6207 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6208 struct ac_export_args color_args[8];
6209
6210 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6211 LLVMValueRef values[4];
6212
6213 if (!(ctx->output_mask & (1ull << i)))
6214 continue;
6215
6216 if (i == FRAG_RESULT_DEPTH) {
6217 ctx->shader_info->fs.writes_z = true;
6218 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6219 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6220 } else if (i == FRAG_RESULT_STENCIL) {
6221 ctx->shader_info->fs.writes_stencil = true;
6222 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6223 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6224 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6225 ctx->shader_info->fs.writes_sample_mask = true;
6226 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6227 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6228 } else {
6229 bool last = false;
6230 for (unsigned j = 0; j < 4; j++)
6231 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6232 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6233
6234 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6235 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6236
6237 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6238 if (ret)
6239 index++;
6240 }
6241 }
6242
6243 for (unsigned i = 0; i < index; i++)
6244 ac_build_export(&ctx->ac, &color_args[i]);
6245 if (depth || stencil || samplemask)
6246 si_export_mrt_z(ctx, depth, stencil, samplemask);
6247 else if (!index) {
6248 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6249 ac_build_export(&ctx->ac, &color_args[0]);
6250 }
6251
6252 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6253 }
6254
6255 static void
6256 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6257 {
6258 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6259 }
6260
6261 static void
6262 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6263 LLVMValueRef *addrs)
6264 {
6265 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6266
6267 switch (ctx->stage) {
6268 case MESA_SHADER_VERTEX:
6269 if (ctx->options->key.vs.as_ls)
6270 handle_ls_outputs_post(ctx);
6271 else if (ctx->options->key.vs.as_es)
6272 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6273 else
6274 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6275 &ctx->shader_info->vs.outinfo);
6276 break;
6277 case MESA_SHADER_FRAGMENT:
6278 handle_fs_outputs_post(ctx);
6279 break;
6280 case MESA_SHADER_GEOMETRY:
6281 emit_gs_epilogue(ctx);
6282 break;
6283 case MESA_SHADER_TESS_CTRL:
6284 handle_tcs_outputs_post(ctx);
6285 break;
6286 case MESA_SHADER_TESS_EVAL:
6287 if (ctx->options->key.tes.as_es)
6288 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6289 else
6290 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6291 &ctx->shader_info->tes.outinfo);
6292 break;
6293 default:
6294 break;
6295 }
6296 }
6297
6298 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6299 {
6300 LLVMPassManagerRef passmgr;
6301 /* Create the pass manager */
6302 passmgr = LLVMCreateFunctionPassManagerForModule(
6303 ctx->module);
6304
6305 /* This pass should eliminate all the load and store instructions */
6306 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6307
6308 /* Add some optimization passes */
6309 LLVMAddScalarReplAggregatesPass(passmgr);
6310 LLVMAddLICMPass(passmgr);
6311 LLVMAddAggressiveDCEPass(passmgr);
6312 LLVMAddCFGSimplificationPass(passmgr);
6313 LLVMAddInstructionCombiningPass(passmgr);
6314
6315 /* Run the pass */
6316 LLVMInitializeFunctionPassManager(passmgr);
6317 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6318 LLVMFinalizeFunctionPassManager(passmgr);
6319
6320 LLVMDisposeBuilder(ctx->builder);
6321 LLVMDisposePassManager(passmgr);
6322 }
6323
6324 static void
6325 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6326 {
6327 struct ac_vs_output_info *outinfo;
6328
6329 switch (ctx->stage) {
6330 case MESA_SHADER_FRAGMENT:
6331 case MESA_SHADER_COMPUTE:
6332 case MESA_SHADER_TESS_CTRL:
6333 case MESA_SHADER_GEOMETRY:
6334 return;
6335 case MESA_SHADER_VERTEX:
6336 if (ctx->options->key.vs.as_ls ||
6337 ctx->options->key.vs.as_es)
6338 return;
6339 outinfo = &ctx->shader_info->vs.outinfo;
6340 break;
6341 case MESA_SHADER_TESS_EVAL:
6342 if (ctx->options->key.vs.as_es)
6343 return;
6344 outinfo = &ctx->shader_info->tes.outinfo;
6345 break;
6346 default:
6347 unreachable("Unhandled shader type");
6348 }
6349
6350 ac_optimize_vs_outputs(&ctx->ac,
6351 ctx->main_function,
6352 outinfo->vs_output_param_offset,
6353 VARYING_SLOT_MAX,
6354 &outinfo->param_exports);
6355 }
6356
6357 static void
6358 ac_setup_rings(struct nir_to_llvm_context *ctx)
6359 {
6360 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6361 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6362 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6363 }
6364
6365 if (ctx->is_gs_copy_shader) {
6366 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6367 }
6368 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6369 LLVMValueRef tmp;
6370 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6371 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6372
6373 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6374
6375 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6376 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6377 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6378 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6379 }
6380
6381 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6382 ctx->stage == MESA_SHADER_TESS_EVAL) {
6383 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6384 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6385 }
6386 }
6387
6388 static unsigned
6389 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6390 const struct nir_shader *nir)
6391 {
6392 switch (nir->info.stage) {
6393 case MESA_SHADER_TESS_CTRL:
6394 return chip_class >= CIK ? 128 : 64;
6395 case MESA_SHADER_GEOMETRY:
6396 return chip_class >= GFX9 ? 128 : 64;
6397 case MESA_SHADER_COMPUTE:
6398 break;
6399 default:
6400 return 0;
6401 }
6402
6403 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6404 nir->info.cs.local_size[1] *
6405 nir->info.cs.local_size[2];
6406 return max_workgroup_size;
6407 }
6408
6409 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6410 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6411 {
6412 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6413 LLVMConstInt(ctx->ac.i32, 8, false),
6414 LLVMConstInt(ctx->ac.i32, 8, false), false);
6415 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6416 LLVMConstInt(ctx->ac.i32, 0, false), "");
6417 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6418 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6419 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6420 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6421 }
6422
6423 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6424 {
6425 for(int i = 5; i >= 0; --i) {
6426 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6427 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6428 LLVMConstInt(ctx->ac.i32, 16, false), false);
6429 }
6430
6431 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6432 LLVMConstInt(ctx->ac.i32, 16, false),
6433 LLVMConstInt(ctx->ac.i32, 8, false), false);
6434 }
6435
6436 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6437 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6438 {
6439 struct ac_nir_context ctx = {};
6440 struct nir_function *func;
6441
6442 ctx.ac = *ac;
6443 ctx.abi = abi;
6444
6445 ctx.nctx = nctx;
6446 if (nctx)
6447 nctx->nir = &ctx;
6448
6449 ctx.stage = nir->info.stage;
6450
6451 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6452
6453 nir_foreach_variable(variable, &nir->outputs)
6454 handle_shader_output_decl(&ctx, nir, variable);
6455
6456 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6457 _mesa_key_pointer_equal);
6458 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6459 _mesa_key_pointer_equal);
6460 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6461 _mesa_key_pointer_equal);
6462
6463 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6464
6465 setup_locals(&ctx, func);
6466
6467 if (nir->info.stage == MESA_SHADER_COMPUTE)
6468 setup_shared(&ctx, nir);
6469
6470 visit_cf_list(&ctx, &func->impl->body);
6471 phi_post_pass(&ctx);
6472
6473 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6474 ctx.outputs);
6475
6476 free(ctx.locals);
6477 ralloc_free(ctx.defs);
6478 ralloc_free(ctx.phis);
6479 ralloc_free(ctx.vars);
6480
6481 if (nctx)
6482 nctx->nir = NULL;
6483 }
6484
6485 static
6486 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6487 struct nir_shader *const *shaders,
6488 int shader_count,
6489 struct ac_shader_variant_info *shader_info,
6490 const struct ac_nir_compiler_options *options)
6491 {
6492 struct nir_to_llvm_context ctx = {0};
6493 unsigned i;
6494 ctx.options = options;
6495 ctx.shader_info = shader_info;
6496 ctx.context = LLVMContextCreate();
6497 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6498
6499 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6500 ctx.ac.module = ctx.module;
6501 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6502
6503 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6504 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6505 LLVMSetDataLayout(ctx.module, data_layout_str);
6506 LLVMDisposeTargetData(data_layout);
6507 LLVMDisposeMessage(data_layout_str);
6508
6509 setup_types(&ctx);
6510 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6511 ctx.ac.builder = ctx.builder;
6512
6513 memset(shader_info, 0, sizeof(*shader_info));
6514
6515 for(int i = 0; i < shader_count; ++i)
6516 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6517
6518 for (i = 0; i < AC_UD_MAX_SETS; i++)
6519 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6520 for (i = 0; i < AC_UD_MAX_UD; i++)
6521 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6522
6523 ctx.max_workgroup_size = 0;
6524 for (int i = 0; i < shader_count; ++i) {
6525 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6526 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6527 shaders[i]));
6528 }
6529
6530 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6531 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6532
6533 ctx.abi.inputs = &ctx.inputs[0];
6534 ctx.abi.emit_outputs = handle_shader_outputs_post;
6535 ctx.abi.load_ssbo = radv_load_ssbo;
6536 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6537 ctx.abi.clamp_shadow_reference = false;
6538
6539 if (shader_count >= 2)
6540 ac_init_exec_full_mask(&ctx.ac);
6541
6542 if (ctx.ac.chip_class == GFX9 &&
6543 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6544 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6545
6546 for(int i = 0; i < shader_count; ++i) {
6547 ctx.stage = shaders[i]->info.stage;
6548 ctx.output_mask = 0;
6549 ctx.tess_outputs_written = 0;
6550 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6551 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6552
6553 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6554 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6555
6556 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6557 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6558 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6559 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6560 if (shader_info->info.vs.needs_instance_id) {
6561 ctx.shader_info->vs.vgpr_comp_cnt =
6562 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6563 }
6564 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6565 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6566 }
6567
6568 if (i)
6569 emit_barrier(&ctx);
6570
6571 ac_setup_rings(&ctx);
6572
6573 LLVMBasicBlockRef merge_block;
6574 if (shader_count >= 2) {
6575 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6576 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6577 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6578
6579 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6580 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6581 LLVMConstInt(ctx.ac.i32, 8, false), false);
6582 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6583 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6584 thread_id, count, "");
6585 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6586
6587 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6588 }
6589
6590 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6591 handle_fs_inputs(&ctx, shaders[i]);
6592 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6593 handle_vs_inputs(&ctx, shaders[i]);
6594 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6595 prepare_gs_input_vgprs(&ctx);
6596
6597 nir_foreach_variable(variable, &shaders[i]->outputs)
6598 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6599
6600 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6601
6602 if (shader_count >= 2) {
6603 LLVMBuildBr(ctx.ac.builder, merge_block);
6604 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6605 }
6606
6607 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6608 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6609 shaders[i]->info.cull_distance_array_size > 4;
6610 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6611 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6612 shaders[i]->info.gs.vertices_out;
6613 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6614 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6615 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6616 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6617 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6618 }
6619 }
6620
6621 LLVMBuildRetVoid(ctx.builder);
6622
6623 ac_llvm_finalize_module(&ctx);
6624
6625 if (shader_count == 1)
6626 ac_nir_eliminate_const_vs_outputs(&ctx);
6627
6628 return ctx.module;
6629 }
6630
6631 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6632 {
6633 unsigned *retval = (unsigned *)context;
6634 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6635 char *description = LLVMGetDiagInfoDescription(di);
6636
6637 if (severity == LLVMDSError) {
6638 *retval = 1;
6639 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6640 description);
6641 }
6642
6643 LLVMDisposeMessage(description);
6644 }
6645
6646 static unsigned ac_llvm_compile(LLVMModuleRef M,
6647 struct ac_shader_binary *binary,
6648 LLVMTargetMachineRef tm)
6649 {
6650 unsigned retval = 0;
6651 char *err;
6652 LLVMContextRef llvm_ctx;
6653 LLVMMemoryBufferRef out_buffer;
6654 unsigned buffer_size;
6655 const char *buffer_data;
6656 LLVMBool mem_err;
6657
6658 /* Setup Diagnostic Handler*/
6659 llvm_ctx = LLVMGetModuleContext(M);
6660
6661 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6662 &retval);
6663
6664 /* Compile IR*/
6665 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6666 &err, &out_buffer);
6667
6668 /* Process Errors/Warnings */
6669 if (mem_err) {
6670 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6671 free(err);
6672 retval = 1;
6673 goto out;
6674 }
6675
6676 /* Extract Shader Code*/
6677 buffer_size = LLVMGetBufferSize(out_buffer);
6678 buffer_data = LLVMGetBufferStart(out_buffer);
6679
6680 ac_elf_read(buffer_data, buffer_size, binary);
6681
6682 /* Clean up */
6683 LLVMDisposeMemoryBuffer(out_buffer);
6684
6685 out:
6686 return retval;
6687 }
6688
6689 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6690 LLVMModuleRef llvm_module,
6691 struct ac_shader_binary *binary,
6692 struct ac_shader_config *config,
6693 struct ac_shader_variant_info *shader_info,
6694 gl_shader_stage stage,
6695 bool dump_shader, bool supports_spill)
6696 {
6697 if (dump_shader)
6698 ac_dump_module(llvm_module);
6699
6700 memset(binary, 0, sizeof(*binary));
6701 int v = ac_llvm_compile(llvm_module, binary, tm);
6702 if (v) {
6703 fprintf(stderr, "compile failed\n");
6704 }
6705
6706 if (dump_shader)
6707 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6708
6709 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6710
6711 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6712 LLVMDisposeModule(llvm_module);
6713 LLVMContextDispose(ctx);
6714
6715 if (stage == MESA_SHADER_FRAGMENT) {
6716 shader_info->num_input_vgprs = 0;
6717 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6718 shader_info->num_input_vgprs += 2;
6719 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6720 shader_info->num_input_vgprs += 2;
6721 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6722 shader_info->num_input_vgprs += 2;
6723 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6724 shader_info->num_input_vgprs += 3;
6725 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6726 shader_info->num_input_vgprs += 2;
6727 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6728 shader_info->num_input_vgprs += 2;
6729 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6730 shader_info->num_input_vgprs += 2;
6731 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6732 shader_info->num_input_vgprs += 1;
6733 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6734 shader_info->num_input_vgprs += 1;
6735 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6736 shader_info->num_input_vgprs += 1;
6737 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6738 shader_info->num_input_vgprs += 1;
6739 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6740 shader_info->num_input_vgprs += 1;
6741 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6742 shader_info->num_input_vgprs += 1;
6743 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6744 shader_info->num_input_vgprs += 1;
6745 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6746 shader_info->num_input_vgprs += 1;
6747 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6748 shader_info->num_input_vgprs += 1;
6749 }
6750 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6751
6752 /* +3 for scratch wave offset and VCC */
6753 config->num_sgprs = MAX2(config->num_sgprs,
6754 shader_info->num_input_sgprs + 3);
6755 }
6756
6757 static void
6758 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6759 {
6760 switch (nir->info.stage) {
6761 case MESA_SHADER_COMPUTE:
6762 for (int i = 0; i < 3; ++i)
6763 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6764 break;
6765 case MESA_SHADER_FRAGMENT:
6766 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6767 break;
6768 case MESA_SHADER_GEOMETRY:
6769 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6770 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6771 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6772 shader_info->gs.invocations = nir->info.gs.invocations;
6773 break;
6774 case MESA_SHADER_TESS_EVAL:
6775 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6776 shader_info->tes.spacing = nir->info.tess.spacing;
6777 shader_info->tes.ccw = nir->info.tess.ccw;
6778 shader_info->tes.point_mode = nir->info.tess.point_mode;
6779 shader_info->tes.as_es = options->key.tes.as_es;
6780 break;
6781 case MESA_SHADER_TESS_CTRL:
6782 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6783 break;
6784 case MESA_SHADER_VERTEX:
6785 shader_info->vs.as_es = options->key.vs.as_es;
6786 shader_info->vs.as_ls = options->key.vs.as_ls;
6787 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6788 if (options->key.vs.as_ls)
6789 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6790 break;
6791 default:
6792 break;
6793 }
6794 }
6795
6796 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6797 struct ac_shader_binary *binary,
6798 struct ac_shader_config *config,
6799 struct ac_shader_variant_info *shader_info,
6800 struct nir_shader *const *nir,
6801 int nir_count,
6802 const struct ac_nir_compiler_options *options,
6803 bool dump_shader)
6804 {
6805
6806 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6807 options);
6808
6809 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6810 for (int i = 0; i < nir_count; ++i)
6811 ac_fill_shader_info(shader_info, nir[i], options);
6812 }
6813
6814 static void
6815 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6816 {
6817 LLVMValueRef args[9];
6818 args[0] = ctx->gsvs_ring;
6819 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6820 args[3] = ctx->ac.i32_0;
6821 args[4] = ctx->ac.i32_1; /* OFFEN */
6822 args[5] = ctx->ac.i32_0; /* IDXEN */
6823 args[6] = ctx->ac.i32_1; /* GLC */
6824 args[7] = ctx->ac.i32_1; /* SLC */
6825 args[8] = ctx->ac.i32_0; /* TFE */
6826
6827 int idx = 0;
6828
6829 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6830 int length = 4;
6831 int slot = idx;
6832 int slot_inc = 1;
6833 if (!(ctx->output_mask & (1ull << i)))
6834 continue;
6835
6836 if (i == VARYING_SLOT_CLIP_DIST0) {
6837 /* unpack clip and cull from a single set of slots */
6838 length = ctx->num_output_clips + ctx->num_output_culls;
6839 if (length > 4)
6840 slot_inc = 2;
6841 }
6842
6843 for (unsigned j = 0; j < length; j++) {
6844 LLVMValueRef value;
6845 args[2] = LLVMConstInt(ctx->ac.i32,
6846 (slot * 4 + j) *
6847 ctx->gs_max_out_vertices * 16 * 4, false);
6848
6849 value = ac_build_intrinsic(&ctx->ac,
6850 "llvm.SI.buffer.load.dword.i32.i32",
6851 ctx->ac.i32, args, 9,
6852 AC_FUNC_ATTR_READONLY |
6853 AC_FUNC_ATTR_LEGACY);
6854
6855 LLVMBuildStore(ctx->builder,
6856 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6857 }
6858 idx += slot_inc;
6859 }
6860 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6861 }
6862
6863 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6864 struct nir_shader *geom_shader,
6865 struct ac_shader_binary *binary,
6866 struct ac_shader_config *config,
6867 struct ac_shader_variant_info *shader_info,
6868 const struct ac_nir_compiler_options *options,
6869 bool dump_shader)
6870 {
6871 struct nir_to_llvm_context ctx = {0};
6872 ctx.context = LLVMContextCreate();
6873 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6874 ctx.options = options;
6875 ctx.shader_info = shader_info;
6876
6877 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6878 ctx.ac.module = ctx.module;
6879
6880 ctx.is_gs_copy_shader = true;
6881 LLVMSetTarget(ctx.module, "amdgcn--");
6882 setup_types(&ctx);
6883
6884 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6885 ctx.ac.builder = ctx.builder;
6886 ctx.stage = MESA_SHADER_VERTEX;
6887
6888 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6889
6890 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6891 ac_setup_rings(&ctx);
6892
6893 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6894 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6895
6896 struct ac_nir_context nir_ctx = {};
6897 nir_ctx.ac = ctx.ac;
6898 nir_ctx.abi = &ctx.abi;
6899
6900 nir_ctx.nctx = &ctx;
6901 ctx.nir = &nir_ctx;
6902
6903 nir_foreach_variable(variable, &geom_shader->outputs) {
6904 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6905 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6906 }
6907
6908 ac_gs_copy_shader_emit(&ctx);
6909
6910 ctx.nir = NULL;
6911
6912 LLVMBuildRetVoid(ctx.builder);
6913
6914 ac_llvm_finalize_module(&ctx);
6915
6916 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6917 MESA_SHADER_VERTEX,
6918 dump_shader, options->supports_spill);
6919 }