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ac/nir: Add LS-HS input VGPR workaround.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 LLVMTypeRef i1;
138 LLVMTypeRef i8;
139 LLVMTypeRef i16;
140 LLVMTypeRef i32;
141 LLVMTypeRef i64;
142 LLVMTypeRef v2i32;
143 LLVMTypeRef v3i32;
144 LLVMTypeRef v4i32;
145 LLVMTypeRef v8i32;
146 LLVMTypeRef f64;
147 LLVMTypeRef f32;
148 LLVMTypeRef f16;
149 LLVMTypeRef v2f32;
150 LLVMTypeRef v4f32;
151 LLVMTypeRef voidt;
152
153 LLVMValueRef i1true;
154 LLVMValueRef i1false;
155 LLVMValueRef i32zero;
156 LLVMValueRef i32one;
157 LLVMValueRef f32zero;
158 LLVMValueRef f32one;
159 LLVMValueRef v4f32empty;
160
161 unsigned uniform_md_kind;
162 LLVMValueRef empty_md;
163 gl_shader_stage stage;
164
165 LLVMValueRef lds;
166 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
167
168 uint64_t input_mask;
169 uint64_t output_mask;
170 uint8_t num_output_clips;
171 uint8_t num_output_culls;
172
173 bool is_gs_copy_shader;
174 LLVMValueRef gs_next_vertex;
175 unsigned gs_max_out_vertices;
176
177 unsigned tes_primitive_mode;
178 uint64_t tess_outputs_written;
179 uint64_t tess_patch_outputs_written;
180 };
181
182 static inline struct nir_to_llvm_context *
183 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
184 {
185 struct nir_to_llvm_context *ctx = NULL;
186 return container_of(abi, ctx, abi);
187 }
188
189 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
190 const nir_deref_var *deref,
191 enum ac_descriptor_type desc_type,
192 bool image, bool write);
193
194 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
195 {
196 return (index * 4) + chan;
197 }
198
199 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
200 {
201 /* handle patch indices separate */
202 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
203 return 0;
204 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
205 return 1;
206 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
207 return 2 + (slot - VARYING_SLOT_PATCH0);
208
209 if (slot == VARYING_SLOT_POS)
210 return 0;
211 if (slot == VARYING_SLOT_PSIZ)
212 return 1;
213 if (slot == VARYING_SLOT_CLIP_DIST0)
214 return 2;
215 /* 3 is reserved for clip dist as well */
216 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
217 return 4 + (slot - VARYING_SLOT_VAR0);
218 unreachable("illegal slot in get unique index\n");
219 }
220
221 static void set_llvm_calling_convention(LLVMValueRef func,
222 gl_shader_stage stage)
223 {
224 enum radeon_llvm_calling_convention calling_conv;
225
226 switch (stage) {
227 case MESA_SHADER_VERTEX:
228 case MESA_SHADER_TESS_EVAL:
229 calling_conv = RADEON_LLVM_AMDGPU_VS;
230 break;
231 case MESA_SHADER_GEOMETRY:
232 calling_conv = RADEON_LLVM_AMDGPU_GS;
233 break;
234 case MESA_SHADER_TESS_CTRL:
235 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_FRAGMENT:
238 calling_conv = RADEON_LLVM_AMDGPU_PS;
239 break;
240 case MESA_SHADER_COMPUTE:
241 calling_conv = RADEON_LLVM_AMDGPU_CS;
242 break;
243 default:
244 unreachable("Unhandle shader type");
245 }
246
247 LLVMSetFunctionCallConv(func, calling_conv);
248 }
249
250 #define MAX_ARGS 23
251 struct arg_info {
252 LLVMTypeRef types[MAX_ARGS];
253 LLVMValueRef *assign[MAX_ARGS];
254 unsigned array_params_mask;
255 uint8_t count;
256 uint8_t user_sgpr_count;
257 uint8_t sgpr_count;
258 uint8_t num_user_sgprs_used;
259 uint8_t num_sgprs_used;
260 uint8_t num_vgprs_used;
261 };
262
263 static inline void
264 add_argument(struct arg_info *info,
265 LLVMTypeRef type, LLVMValueRef *param_ptr)
266 {
267 assert(info->count < MAX_ARGS);
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271 }
272
273 static inline void
274 add_sgpr_argument(struct arg_info *info,
275 LLVMTypeRef type, LLVMValueRef *param_ptr)
276 {
277 add_argument(info, type, param_ptr);
278 info->num_sgprs_used += ac_get_type_size(type) / 4;
279 info->sgpr_count++;
280 }
281
282 static inline void
283 add_user_sgpr_argument(struct arg_info *info,
284 LLVMTypeRef type,
285 LLVMValueRef *param_ptr)
286 {
287 add_sgpr_argument(info, type, param_ptr);
288 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
289 info->user_sgpr_count++;
290 }
291
292 static inline void
293 add_vgpr_argument(struct arg_info *info,
294 LLVMTypeRef type,
295 LLVMValueRef *param_ptr)
296 {
297 add_argument(info, type, param_ptr);
298 info->num_vgprs_used += ac_get_type_size(type) / 4;
299 }
300
301 static inline void
302 add_user_sgpr_array_argument(struct arg_info *info,
303 LLVMTypeRef type,
304 LLVMValueRef *param_ptr)
305 {
306 info->array_params_mask |= (1 << info->count);
307 add_user_sgpr_argument(info, type, param_ptr);
308 }
309
310 static void assign_arguments(LLVMValueRef main_function,
311 struct arg_info *info)
312 {
313 unsigned i;
314 for (i = 0; i < info->count; i++) {
315 if (info->assign[i])
316 *info->assign[i] = LLVMGetParam(main_function, i);
317 }
318 }
319
320 static LLVMValueRef
321 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
322 LLVMBuilderRef builder, LLVMTypeRef *return_types,
323 unsigned num_return_elems,
324 struct arg_info *args,
325 unsigned max_workgroup_size,
326 bool unsafe_math)
327 {
328 LLVMTypeRef main_function_type, ret_type;
329 LLVMBasicBlockRef main_function_body;
330
331 if (num_return_elems)
332 ret_type = LLVMStructTypeInContext(ctx, return_types,
333 num_return_elems, true);
334 else
335 ret_type = LLVMVoidTypeInContext(ctx);
336
337 /* Setup the function */
338 main_function_type =
339 LLVMFunctionType(ret_type, args->types, args->count, 0);
340 LLVMValueRef main_function =
341 LLVMAddFunction(module, "main", main_function_type);
342 main_function_body =
343 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
344 LLVMPositionBuilderAtEnd(builder, main_function_body);
345
346 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
347 for (unsigned i = 0; i < args->sgpr_count; ++i) {
348 if (args->array_params_mask & (1 << i)) {
349 LLVMValueRef P = LLVMGetParam(main_function, i);
350 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
351 ac_add_attr_dereferenceable(P, UINT64_MAX);
352 }
353 else {
354 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
355 }
356 }
357
358 if (max_workgroup_size) {
359 ac_llvm_add_target_dep_function_attr(main_function,
360 "amdgpu-max-work-group-size",
361 max_workgroup_size);
362 }
363 if (unsafe_math) {
364 /* These were copied from some LLVM test. */
365 LLVMAddTargetDependentFunctionAttr(main_function,
366 "less-precise-fpmad",
367 "true");
368 LLVMAddTargetDependentFunctionAttr(main_function,
369 "no-infs-fp-math",
370 "true");
371 LLVMAddTargetDependentFunctionAttr(main_function,
372 "no-nans-fp-math",
373 "true");
374 LLVMAddTargetDependentFunctionAttr(main_function,
375 "unsafe-fp-math",
376 "true");
377 }
378 return main_function;
379 }
380
381 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
382 {
383 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
384 CONST_ADDR_SPACE);
385 }
386
387 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = *sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 *sgpr_idx += num_sgprs;
533 }
534
535 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
536 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
537 {
538 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
539 }
540
541
542 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
543 uint32_t indirect_offset)
544 {
545 ud_info->sgpr_idx = sgpr_idx;
546 ud_info->num_sgprs = num_sgprs;
547 ud_info->indirect = true;
548 ud_info->indirect_offset = indirect_offset;
549 }
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 struct user_sgpr_info {
560 bool need_ring_offsets;
561 uint8_t sgpr_count;
562 bool indirect_all_descriptor_sets;
563 };
564
565 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
566 struct user_sgpr_info *user_sgpr_info)
567 {
568 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
569
570 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
571 if (ctx->stage == MESA_SHADER_GEOMETRY ||
572 ctx->stage == MESA_SHADER_VERTEX ||
573 ctx->stage == MESA_SHADER_TESS_CTRL ||
574 ctx->stage == MESA_SHADER_TESS_EVAL ||
575 ctx->is_gs_copy_shader)
576 user_sgpr_info->need_ring_offsets = true;
577
578 if (ctx->stage == MESA_SHADER_FRAGMENT &&
579 ctx->shader_info->info.ps.needs_sample_positions)
580 user_sgpr_info->need_ring_offsets = true;
581
582 /* 2 user sgprs will nearly always be allocated for scratch/rings */
583 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
584 user_sgpr_info->sgpr_count += 2;
585 }
586
587 switch (ctx->stage) {
588 case MESA_SHADER_COMPUTE:
589 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
590 break;
591 case MESA_SHADER_FRAGMENT:
592 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
593 break;
594 case MESA_SHADER_VERTEX:
595 if (!ctx->is_gs_copy_shader) {
596 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
597 if (ctx->shader_info->info.vs.needs_draw_id) {
598 user_sgpr_info->sgpr_count += 3;
599 } else {
600 user_sgpr_info->sgpr_count += 2;
601 }
602 }
603 if (ctx->options->key.vs.as_ls)
604 user_sgpr_info->sgpr_count++;
605 break;
606 case MESA_SHADER_TESS_CTRL:
607 user_sgpr_info->sgpr_count += 4;
608 break;
609 case MESA_SHADER_TESS_EVAL:
610 user_sgpr_info->sgpr_count += 1;
611 break;
612 case MESA_SHADER_GEOMETRY:
613 user_sgpr_info->sgpr_count += 2;
614 break;
615 default:
616 break;
617 }
618
619 if (ctx->shader_info->info.needs_push_constants)
620 user_sgpr_info->sgpr_count += 2;
621
622 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
623 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
624 user_sgpr_info->sgpr_count += 2;
625 user_sgpr_info->indirect_all_descriptor_sets = true;
626 } else {
627 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
628 }
629 }
630
631 static void
632 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
633 gl_shader_stage stage,
634 bool has_previous_stage,
635 gl_shader_stage previous_stage,
636 const struct user_sgpr_info *user_sgpr_info,
637 struct arg_info *args,
638 LLVMValueRef *desc_sets)
639 {
640 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
641 unsigned stage_mask = 1 << stage;
642 if (has_previous_stage)
643 stage_mask |= 1 << previous_stage;
644
645 /* 1 for each descriptor set */
646 if (!user_sgpr_info->indirect_all_descriptor_sets) {
647 for (unsigned i = 0; i < num_sets; ++i) {
648 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
649 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
650 }
651 }
652 } else
653 add_user_sgpr_array_argument(args, const_array(const_array(ctx->i8, 1024 * 1024), 32), desc_sets);
654
655 if (ctx->shader_info->info.needs_push_constants) {
656 /* 1 for push constants and dynamic descriptors */
657 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
658 }
659 }
660
661 static void
662 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
663 gl_shader_stage stage,
664 bool has_previous_stage,
665 gl_shader_stage previous_stage,
666 const struct user_sgpr_info *user_sgpr_info,
667 LLVMValueRef desc_sets,
668 uint8_t *user_sgpr_idx)
669 {
670 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
671 unsigned stage_mask = 1 << stage;
672 if (has_previous_stage)
673 stage_mask |= 1 << previous_stage;
674
675 if (!user_sgpr_info->indirect_all_descriptor_sets) {
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
679 } else
680 ctx->descriptor_sets[i] = NULL;
681 }
682 } else {
683 uint32_t desc_sgpr_idx = *user_sgpr_idx;
684 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
685
686 for (unsigned i = 0; i < num_sets; ++i) {
687 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
688 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
689 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
690
691 } else
692 ctx->descriptor_sets[i] = NULL;
693 }
694 ctx->shader_info->need_indirect_descriptor_sets = true;
695 }
696
697 if (ctx->shader_info->info.needs_push_constants) {
698 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
699 }
700 }
701
702 static void
703 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
704 gl_shader_stage stage,
705 bool has_previous_stage,
706 gl_shader_stage previous_stage,
707 struct arg_info *args)
708 {
709 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
710 if (ctx->shader_info->info.vs.has_vertex_buffers)
711 add_user_sgpr_argument(args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
712 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.base_vertex); // base vertex
713 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.start_instance);// start instance
714 if (ctx->shader_info->info.vs.needs_draw_id)
715 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.draw_id); // draw id
716 }
717 }
718
719 static void
720 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
721 gl_shader_stage stage,
722 bool has_previous_stage,
723 gl_shader_stage previous_stage,
724 uint8_t *user_sgpr_idx)
725 {
726 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
727 if (ctx->shader_info->info.vs.has_vertex_buffers) {
728 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
729 }
730 unsigned vs_num = 2;
731 if (ctx->shader_info->info.vs.needs_draw_id)
732 vs_num++;
733
734 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
735 }
736 }
737
738
739 static void create_function(struct nir_to_llvm_context *ctx,
740 gl_shader_stage stage,
741 bool has_previous_stage,
742 gl_shader_stage previous_stage)
743 {
744 uint8_t user_sgpr_idx;
745 struct user_sgpr_info user_sgpr_info;
746 struct arg_info args = {};
747 LLVMValueRef desc_sets;
748
749 allocate_user_sgprs(ctx, &user_sgpr_info);
750
751 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
752 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
753 }
754
755 switch (stage) {
756 case MESA_SHADER_COMPUTE:
757 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
758 if (ctx->shader_info->info.cs.grid_components_used)
759 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
760 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
761 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
762 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
763 break;
764 case MESA_SHADER_VERTEX:
765 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
766 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
767 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
769 if (ctx->options->key.vs.as_es)
770 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
771 else if (ctx->options->key.vs.as_ls)
772 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
773 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
774 if (!ctx->is_gs_copy_shader) {
775 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
776 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
777 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
778 }
779 break;
780 case MESA_SHADER_TESS_CTRL:
781 if (has_previous_stage) {
782 // First 6 system regs
783 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
784 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
785 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
786
787 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
788 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
789 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
790
791 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
792 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
793 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
794
795 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
796 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
797 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
798 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
799 if (ctx->shader_info->info.needs_multiview_view_index)
800 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
801
802 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
803 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
804 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
805 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
806 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
807 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
808 } else {
809 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
810 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
811 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
812 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
813 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
814 if (ctx->shader_info->info.needs_multiview_view_index)
815 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
816 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
817 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
818 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
819 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
820 }
821 break;
822 case MESA_SHADER_TESS_EVAL:
823 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
824 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
825 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
826 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
827 if (ctx->options->key.tes.as_es) {
828 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
829 add_sgpr_argument(&args, ctx->i32, NULL); //
830 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
831 } else {
832 add_sgpr_argument(&args, ctx->i32, NULL); //
833 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
834 }
835 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
836 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
837 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
838 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
839 break;
840 case MESA_SHADER_GEOMETRY:
841 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
842 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
843 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
844 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
845 if (ctx->shader_info->info.needs_multiview_view_index)
846 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
847 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
848 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
849 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
850 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
851 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
852 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
853 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
854 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
855 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
856 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
857 break;
858 case MESA_SHADER_FRAGMENT:
859 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
860 if (ctx->shader_info->info.ps.needs_sample_positions)
861 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
862 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
863 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
864 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
865 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
866 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
867 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
868 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
869 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
870 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
871 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
872 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
873 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
874 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
875 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
876 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
877 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
878 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
879 break;
880 default:
881 unreachable("Shader stage not implemented");
882 }
883
884 ctx->main_function = create_llvm_function(
885 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
886 ctx->max_workgroup_size,
887 ctx->options->unsafe_math);
888 set_llvm_calling_convention(ctx->main_function, stage);
889
890
891 ctx->shader_info->num_input_vgprs = 0;
892 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
893
894 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
895
896 if (ctx->stage != MESA_SHADER_FRAGMENT)
897 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
898
899 assign_arguments(ctx->main_function, &args);
900
901 user_sgpr_idx = 0;
902
903 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
904 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
905 if (ctx->options->supports_spill) {
906 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
907 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
908 NULL, 0, AC_FUNC_ATTR_READNONE);
909 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
910 const_array(ctx->v4i32, 16), "");
911 }
912 }
913
914 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
915 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
916 if (has_previous_stage)
917 user_sgpr_idx = 0;
918
919 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
920
921 switch (stage) {
922 case MESA_SHADER_COMPUTE:
923 if (ctx->shader_info->info.cs.grid_components_used) {
924 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
925 }
926 break;
927 case MESA_SHADER_VERTEX:
928 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
929 if (ctx->view_index)
930 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
931 if (ctx->options->key.vs.as_ls) {
932 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
933 }
934 if (ctx->options->key.vs.as_ls)
935 declare_tess_lds(ctx);
936 break;
937 case MESA_SHADER_TESS_CTRL:
938 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
939 if (has_previous_stage)
940 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
941 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
942 if (ctx->view_index)
943 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
944 declare_tess_lds(ctx);
945 break;
946 case MESA_SHADER_TESS_EVAL:
947 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
948 if (ctx->view_index)
949 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
950 break;
951 case MESA_SHADER_GEOMETRY:
952 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
953 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
954 if (ctx->view_index)
955 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
956 break;
957 case MESA_SHADER_FRAGMENT:
958 if (ctx->shader_info->info.ps.needs_sample_positions) {
959 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
960 }
961 break;
962 default:
963 unreachable("Shader stage not implemented");
964 }
965
966 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
967 }
968
969 static void setup_types(struct nir_to_llvm_context *ctx)
970 {
971 LLVMValueRef args[4];
972
973 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
974 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
975 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
976 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
977 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
978 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
979 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
980 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
981 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
982 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
983 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
984 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
985 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
986 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
987 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
988
989 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
990 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
991 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
992 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
993 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
994 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
995
996 args[0] = ctx->f32zero;
997 args[1] = ctx->f32zero;
998 args[2] = ctx->f32zero;
999 args[3] = ctx->f32one;
1000 ctx->v4f32empty = LLVMConstVector(args, 4);
1001
1002 ctx->uniform_md_kind =
1003 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1004 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1005
1006 args[0] = LLVMConstReal(ctx->f32, 2.5);
1007 }
1008
1009 static int get_llvm_num_components(LLVMValueRef value)
1010 {
1011 LLVMTypeRef type = LLVMTypeOf(value);
1012 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1013 ? LLVMGetVectorSize(type)
1014 : 1;
1015 return num_components;
1016 }
1017
1018 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1019 LLVMValueRef value,
1020 int index)
1021 {
1022 int count = get_llvm_num_components(value);
1023
1024 assert(index < count);
1025 if (count == 1)
1026 return value;
1027
1028 return LLVMBuildExtractElement(ac->builder, value,
1029 LLVMConstInt(ac->i32, index, false), "");
1030 }
1031
1032 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1033 LLVMValueRef value, unsigned count)
1034 {
1035 unsigned num_components = get_llvm_num_components(value);
1036 if (count == num_components)
1037 return value;
1038
1039 LLVMValueRef masks[] = {
1040 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1041 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1042
1043 if (count == 1)
1044 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1045 "");
1046
1047 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1048 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1049 }
1050
1051 static void
1052 build_store_values_extended(struct ac_llvm_context *ac,
1053 LLVMValueRef *values,
1054 unsigned value_count,
1055 unsigned value_stride,
1056 LLVMValueRef vec)
1057 {
1058 LLVMBuilderRef builder = ac->builder;
1059 unsigned i;
1060
1061 for (i = 0; i < value_count; i++) {
1062 LLVMValueRef ptr = values[i * value_stride];
1063 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1064 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1065 LLVMBuildStore(builder, value, ptr);
1066 }
1067 }
1068
1069 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1070 const nir_ssa_def *def)
1071 {
1072 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1073 if (def->num_components > 1) {
1074 type = LLVMVectorType(type, def->num_components);
1075 }
1076 return type;
1077 }
1078
1079 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1080 {
1081 assert(src.is_ssa);
1082 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1083 return (LLVMValueRef)entry->data;
1084 }
1085
1086
1087 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1088 const struct nir_block *b)
1089 {
1090 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1091 return (LLVMBasicBlockRef)entry->data;
1092 }
1093
1094 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1095 nir_alu_src src,
1096 unsigned num_components)
1097 {
1098 LLVMValueRef value = get_src(ctx, src.src);
1099 bool need_swizzle = false;
1100
1101 assert(value);
1102 LLVMTypeRef type = LLVMTypeOf(value);
1103 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1104 ? LLVMGetVectorSize(type)
1105 : 1;
1106
1107 for (unsigned i = 0; i < num_components; ++i) {
1108 assert(src.swizzle[i] < src_components);
1109 if (src.swizzle[i] != i)
1110 need_swizzle = true;
1111 }
1112
1113 if (need_swizzle || num_components != src_components) {
1114 LLVMValueRef masks[] = {
1115 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1116 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1117 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1118 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1119
1120 if (src_components > 1 && num_components == 1) {
1121 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1122 masks[0], "");
1123 } else if (src_components == 1 && num_components > 1) {
1124 LLVMValueRef values[] = {value, value, value, value};
1125 value = ac_build_gather_values(&ctx->ac, values, num_components);
1126 } else {
1127 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1128 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1129 swizzle, "");
1130 }
1131 }
1132 assert(!src.negate);
1133 assert(!src.abs);
1134 return value;
1135 }
1136
1137 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1138 LLVMIntPredicate pred, LLVMValueRef src0,
1139 LLVMValueRef src1)
1140 {
1141 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1142 return LLVMBuildSelect(ctx->builder, result,
1143 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1144 LLVMConstInt(ctx->i32, 0, false), "");
1145 }
1146
1147 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1148 LLVMRealPredicate pred, LLVMValueRef src0,
1149 LLVMValueRef src1)
1150 {
1151 LLVMValueRef result;
1152 src0 = ac_to_float(ctx, src0);
1153 src1 = ac_to_float(ctx, src1);
1154 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1155 return LLVMBuildSelect(ctx->builder, result,
1156 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1157 LLVMConstInt(ctx->i32, 0, false), "");
1158 }
1159
1160 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1161 const char *intrin,
1162 LLVMTypeRef result_type,
1163 LLVMValueRef src0)
1164 {
1165 char name[64];
1166 LLVMValueRef params[] = {
1167 ac_to_float(ctx, src0),
1168 };
1169
1170 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1171 get_elem_bits(ctx, result_type));
1172 assert(length < sizeof(name));
1173 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1174 }
1175
1176 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1177 const char *intrin,
1178 LLVMTypeRef result_type,
1179 LLVMValueRef src0, LLVMValueRef src1)
1180 {
1181 char name[64];
1182 LLVMValueRef params[] = {
1183 ac_to_float(ctx, src0),
1184 ac_to_float(ctx, src1),
1185 };
1186
1187 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1188 get_elem_bits(ctx, result_type));
1189 assert(length < sizeof(name));
1190 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1191 }
1192
1193 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1194 const char *intrin,
1195 LLVMTypeRef result_type,
1196 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1197 {
1198 char name[64];
1199 LLVMValueRef params[] = {
1200 ac_to_float(ctx, src0),
1201 ac_to_float(ctx, src1),
1202 ac_to_float(ctx, src2),
1203 };
1204
1205 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1206 get_elem_bits(ctx, result_type));
1207 assert(length < sizeof(name));
1208 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1209 }
1210
1211 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1212 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1213 {
1214 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1215 ctx->i32_0, "");
1216 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1217 }
1218
1219 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1220 LLVMValueRef src0)
1221 {
1222 LLVMValueRef params[2] = {
1223 src0,
1224
1225 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1226 * add special code to check for x=0. The reason is that
1227 * the LLVM behavior for x=0 is different from what we
1228 * need here.
1229 *
1230 * The hardware already implements the correct behavior.
1231 */
1232 LLVMConstInt(ctx->i1, 1, false),
1233 };
1234
1235 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1236 params, 2,
1237 AC_FUNC_ATTR_READNONE);
1238
1239 /* TODO: We need an intrinsic to skip this conditional. */
1240 /* Check for zero: */
1241 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1242 LLVMIntEQ, src0,
1243 ctx->i32_0, ""),
1244 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1245 }
1246
1247 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1248 LLVMValueRef src0)
1249 {
1250 return ac_build_imsb(ctx, src0, ctx->i32);
1251 }
1252
1253 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1254 LLVMValueRef src0)
1255 {
1256 return ac_build_umsb(ctx, src0, ctx->i32);
1257 }
1258
1259 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1260 LLVMIntPredicate pred,
1261 LLVMValueRef src0, LLVMValueRef src1)
1262 {
1263 return LLVMBuildSelect(ctx->builder,
1264 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1265 src0,
1266 src1, "");
1267
1268 }
1269 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1270 LLVMValueRef src0)
1271 {
1272 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1273 LLVMBuildNeg(ctx->builder, src0, ""));
1274 }
1275
1276 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1277 LLVMValueRef src0)
1278 {
1279 LLVMValueRef cmp, val;
1280
1281 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1282 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1283 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1284 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1285 return val;
1286 }
1287
1288 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 LLVMValueRef cmp, val;
1292
1293 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1294 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1295 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1296 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1297 return val;
1298 }
1299
1300 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1301 LLVMValueRef src0)
1302 {
1303 const char *intr = "llvm.floor.f32";
1304 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1305 LLVMValueRef params[] = {
1306 fsrc0,
1307 };
1308 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1309 ctx->f32, params, 1,
1310 AC_FUNC_ATTR_READNONE);
1311 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1312 }
1313
1314 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1315 const char *intrin,
1316 LLVMValueRef src0, LLVMValueRef src1)
1317 {
1318 LLVMTypeRef ret_type;
1319 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1320 LLVMValueRef res;
1321 LLVMValueRef params[] = { src0, src1 };
1322 ret_type = LLVMStructTypeInContext(ctx->context, types,
1323 2, true);
1324
1325 res = ac_build_intrinsic(ctx, intrin, ret_type,
1326 params, 2, AC_FUNC_ATTR_READNONE);
1327
1328 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1329 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1330 return res;
1331 }
1332
1333 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1337 }
1338
1339 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1340 LLVMValueRef src0)
1341 {
1342 src0 = ac_to_float(ctx, src0);
1343 return LLVMBuildSExt(ctx->builder,
1344 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1345 ctx->i32, "");
1346 }
1347
1348 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1349 LLVMValueRef src0)
1350 {
1351 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1352 }
1353
1354 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1355 LLVMValueRef src0)
1356 {
1357 return LLVMBuildSExt(ctx->builder,
1358 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1359 ctx->i32, "");
1360 }
1361
1362 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1363 LLVMValueRef src0)
1364 {
1365 LLVMValueRef result;
1366 LLVMValueRef cond = NULL;
1367
1368 src0 = ac_to_float(&ctx->ac, src0);
1369 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1370
1371 if (ctx->options->chip_class >= VI) {
1372 LLVMValueRef args[2];
1373 /* Check if the result is a denormal - and flush to 0 if so. */
1374 args[0] = result;
1375 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1376 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1377 }
1378
1379 /* need to convert back up to f32 */
1380 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1381
1382 if (ctx->options->chip_class >= VI)
1383 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1384 else {
1385 /* for SI/CIK */
1386 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1387 * so compare the result and flush to 0 if it's smaller.
1388 */
1389 LLVMValueRef temp, cond2;
1390 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1391 ctx->f32, result);
1392 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1393 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1394 temp, "");
1395 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1396 temp, ctx->f32zero, "");
1397 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1398 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1399 }
1400 return result;
1401 }
1402
1403 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0, LLVMValueRef src1)
1405 {
1406 LLVMValueRef dst64, result;
1407 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1408 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1409
1410 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1411 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1412 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1413 return result;
1414 }
1415
1416 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1417 LLVMValueRef src0, LLVMValueRef src1)
1418 {
1419 LLVMValueRef dst64, result;
1420 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1421 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1422
1423 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1424 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1425 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1426 return result;
1427 }
1428
1429 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1430 bool is_signed,
1431 const LLVMValueRef srcs[3])
1432 {
1433 LLVMValueRef result;
1434 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1435
1436 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1437 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1438 return result;
1439 }
1440
1441 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1442 LLVMValueRef src0, LLVMValueRef src1,
1443 LLVMValueRef src2, LLVMValueRef src3)
1444 {
1445 LLVMValueRef bfi_args[3], result;
1446
1447 bfi_args[0] = LLVMBuildShl(ctx->builder,
1448 LLVMBuildSub(ctx->builder,
1449 LLVMBuildShl(ctx->builder,
1450 ctx->i32_1,
1451 src3, ""),
1452 ctx->i32_1, ""),
1453 src2, "");
1454 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1455 bfi_args[2] = src0;
1456
1457 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1458
1459 /* Calculate:
1460 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1461 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1462 */
1463 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1464 LLVMBuildAnd(ctx->builder, bfi_args[0],
1465 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1466
1467 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1468 return result;
1469 }
1470
1471 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1472 LLVMValueRef src0)
1473 {
1474 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1475 int i;
1476 LLVMValueRef comp[2];
1477
1478 src0 = ac_to_float(ctx, src0);
1479 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1480 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1481 for (i = 0; i < 2; i++) {
1482 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1483 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1484 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1485 }
1486
1487 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1488 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1489
1490 return comp[0];
1491 }
1492
1493 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1494 LLVMValueRef src0)
1495 {
1496 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1497 LLVMValueRef temps[2], result, val;
1498 int i;
1499
1500 for (i = 0; i < 2; i++) {
1501 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1502 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1503 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1504 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1505 }
1506
1507 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1508 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1509 ctx->i32_0, "");
1510 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1511 ctx->i32_1, "");
1512 return result;
1513 }
1514
1515 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1516 nir_op op,
1517 LLVMValueRef src0)
1518 {
1519 unsigned mask;
1520 int idx;
1521 LLVMValueRef result;
1522
1523 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1524 mask = AC_TID_MASK_LEFT;
1525 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1526 mask = AC_TID_MASK_TOP;
1527 else
1528 mask = AC_TID_MASK_TOP_LEFT;
1529
1530 /* for DDX we want to next X pixel, DDY next Y pixel. */
1531 if (op == nir_op_fddx_fine ||
1532 op == nir_op_fddx_coarse ||
1533 op == nir_op_fddx)
1534 idx = 1;
1535 else
1536 idx = 2;
1537
1538 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1539 return result;
1540 }
1541
1542 /*
1543 * this takes an I,J coordinate pair,
1544 * and works out the X and Y derivatives.
1545 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1546 */
1547 static LLVMValueRef emit_ddxy_interp(
1548 struct ac_nir_context *ctx,
1549 LLVMValueRef interp_ij)
1550 {
1551 LLVMValueRef result[4], a;
1552 unsigned i;
1553
1554 for (i = 0; i < 2; i++) {
1555 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1556 LLVMConstInt(ctx->ac.i32, i, false), "");
1557 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1558 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1559 }
1560 return ac_build_gather_values(&ctx->ac, result, 4);
1561 }
1562
1563 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1564 {
1565 LLVMValueRef src[4], result = NULL;
1566 unsigned num_components = instr->dest.dest.ssa.num_components;
1567 unsigned src_components;
1568 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1569
1570 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1571 switch (instr->op) {
1572 case nir_op_vec2:
1573 case nir_op_vec3:
1574 case nir_op_vec4:
1575 src_components = 1;
1576 break;
1577 case nir_op_pack_half_2x16:
1578 src_components = 2;
1579 break;
1580 case nir_op_unpack_half_2x16:
1581 src_components = 1;
1582 break;
1583 default:
1584 src_components = num_components;
1585 break;
1586 }
1587 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1588 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1589
1590 switch (instr->op) {
1591 case nir_op_fmov:
1592 case nir_op_imov:
1593 result = src[0];
1594 break;
1595 case nir_op_fneg:
1596 src[0] = ac_to_float(&ctx->ac, src[0]);
1597 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1598 break;
1599 case nir_op_ineg:
1600 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1601 break;
1602 case nir_op_inot:
1603 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1604 break;
1605 case nir_op_iadd:
1606 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1607 break;
1608 case nir_op_fadd:
1609 src[0] = ac_to_float(&ctx->ac, src[0]);
1610 src[1] = ac_to_float(&ctx->ac, src[1]);
1611 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1612 break;
1613 case nir_op_fsub:
1614 src[0] = ac_to_float(&ctx->ac, src[0]);
1615 src[1] = ac_to_float(&ctx->ac, src[1]);
1616 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_isub:
1619 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_imul:
1622 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_imod:
1625 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1626 break;
1627 case nir_op_umod:
1628 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1629 break;
1630 case nir_op_fmod:
1631 src[0] = ac_to_float(&ctx->ac, src[0]);
1632 src[1] = ac_to_float(&ctx->ac, src[1]);
1633 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1634 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1635 ac_to_float_type(&ctx->ac, def_type), result);
1636 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1637 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1638 break;
1639 case nir_op_frem:
1640 src[0] = ac_to_float(&ctx->ac, src[0]);
1641 src[1] = ac_to_float(&ctx->ac, src[1]);
1642 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1643 break;
1644 case nir_op_irem:
1645 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1646 break;
1647 case nir_op_idiv:
1648 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1649 break;
1650 case nir_op_udiv:
1651 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1652 break;
1653 case nir_op_fmul:
1654 src[0] = ac_to_float(&ctx->ac, src[0]);
1655 src[1] = ac_to_float(&ctx->ac, src[1]);
1656 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1657 break;
1658 case nir_op_fdiv:
1659 src[0] = ac_to_float(&ctx->ac, src[0]);
1660 src[1] = ac_to_float(&ctx->ac, src[1]);
1661 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1662 break;
1663 case nir_op_frcp:
1664 src[0] = ac_to_float(&ctx->ac, src[0]);
1665 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1666 break;
1667 case nir_op_iand:
1668 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1669 break;
1670 case nir_op_ior:
1671 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1672 break;
1673 case nir_op_ixor:
1674 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_ishl:
1677 result = LLVMBuildShl(ctx->ac.builder, src[0],
1678 LLVMBuildZExt(ctx->ac.builder, src[1],
1679 LLVMTypeOf(src[0]), ""),
1680 "");
1681 break;
1682 case nir_op_ishr:
1683 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1684 LLVMBuildZExt(ctx->ac.builder, src[1],
1685 LLVMTypeOf(src[0]), ""),
1686 "");
1687 break;
1688 case nir_op_ushr:
1689 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1690 LLVMBuildZExt(ctx->ac.builder, src[1],
1691 LLVMTypeOf(src[0]), ""),
1692 "");
1693 break;
1694 case nir_op_ilt:
1695 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1696 break;
1697 case nir_op_ine:
1698 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1699 break;
1700 case nir_op_ieq:
1701 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1702 break;
1703 case nir_op_ige:
1704 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1705 break;
1706 case nir_op_ult:
1707 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1708 break;
1709 case nir_op_uge:
1710 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1711 break;
1712 case nir_op_feq:
1713 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1714 break;
1715 case nir_op_fne:
1716 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1717 break;
1718 case nir_op_flt:
1719 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1720 break;
1721 case nir_op_fge:
1722 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1723 break;
1724 case nir_op_fabs:
1725 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1726 ac_to_float_type(&ctx->ac, def_type), src[0]);
1727 break;
1728 case nir_op_iabs:
1729 result = emit_iabs(&ctx->ac, src[0]);
1730 break;
1731 case nir_op_imax:
1732 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1733 break;
1734 case nir_op_imin:
1735 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1736 break;
1737 case nir_op_umax:
1738 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1739 break;
1740 case nir_op_umin:
1741 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1742 break;
1743 case nir_op_isign:
1744 result = emit_isign(&ctx->ac, src[0]);
1745 break;
1746 case nir_op_fsign:
1747 src[0] = ac_to_float(&ctx->ac, src[0]);
1748 result = emit_fsign(&ctx->ac, src[0]);
1749 break;
1750 case nir_op_ffloor:
1751 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1752 ac_to_float_type(&ctx->ac, def_type), src[0]);
1753 break;
1754 case nir_op_ftrunc:
1755 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1756 ac_to_float_type(&ctx->ac, def_type), src[0]);
1757 break;
1758 case nir_op_fceil:
1759 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1760 ac_to_float_type(&ctx->ac, def_type), src[0]);
1761 break;
1762 case nir_op_fround_even:
1763 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1764 ac_to_float_type(&ctx->ac, def_type),src[0]);
1765 break;
1766 case nir_op_ffract:
1767 result = emit_ffract(&ctx->ac, src[0]);
1768 break;
1769 case nir_op_fsin:
1770 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1771 ac_to_float_type(&ctx->ac, def_type), src[0]);
1772 break;
1773 case nir_op_fcos:
1774 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1775 ac_to_float_type(&ctx->ac, def_type), src[0]);
1776 break;
1777 case nir_op_fsqrt:
1778 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1779 ac_to_float_type(&ctx->ac, def_type), src[0]);
1780 break;
1781 case nir_op_fexp2:
1782 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1783 ac_to_float_type(&ctx->ac, def_type), src[0]);
1784 break;
1785 case nir_op_flog2:
1786 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1787 ac_to_float_type(&ctx->ac, def_type), src[0]);
1788 break;
1789 case nir_op_frsq:
1790 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1791 ac_to_float_type(&ctx->ac, def_type), src[0]);
1792 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1793 break;
1794 case nir_op_fpow:
1795 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1796 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1797 break;
1798 case nir_op_fmax:
1799 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1800 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1801 if (instr->dest.dest.ssa.bit_size == 32)
1802 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1803 ac_to_float_type(&ctx->ac, def_type),
1804 result);
1805 break;
1806 case nir_op_fmin:
1807 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1808 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1809 if (instr->dest.dest.ssa.bit_size == 32)
1810 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1811 ac_to_float_type(&ctx->ac, def_type),
1812 result);
1813 break;
1814 case nir_op_ffma:
1815 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1816 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1817 break;
1818 case nir_op_ibitfield_extract:
1819 result = emit_bitfield_extract(&ctx->ac, true, src);
1820 break;
1821 case nir_op_ubitfield_extract:
1822 result = emit_bitfield_extract(&ctx->ac, false, src);
1823 break;
1824 case nir_op_bitfield_insert:
1825 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1826 break;
1827 case nir_op_bitfield_reverse:
1828 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1829 break;
1830 case nir_op_bit_count:
1831 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1832 break;
1833 case nir_op_vec2:
1834 case nir_op_vec3:
1835 case nir_op_vec4:
1836 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1837 src[i] = ac_to_integer(&ctx->ac, src[i]);
1838 result = ac_build_gather_values(&ctx->ac, src, num_components);
1839 break;
1840 case nir_op_f2i32:
1841 case nir_op_f2i64:
1842 src[0] = ac_to_float(&ctx->ac, src[0]);
1843 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1844 break;
1845 case nir_op_f2u32:
1846 case nir_op_f2u64:
1847 src[0] = ac_to_float(&ctx->ac, src[0]);
1848 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1849 break;
1850 case nir_op_i2f32:
1851 case nir_op_i2f64:
1852 src[0] = ac_to_integer(&ctx->ac, src[0]);
1853 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1854 break;
1855 case nir_op_u2f32:
1856 case nir_op_u2f64:
1857 src[0] = ac_to_integer(&ctx->ac, src[0]);
1858 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1859 break;
1860 case nir_op_f2f64:
1861 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1862 break;
1863 case nir_op_f2f32:
1864 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1865 break;
1866 case nir_op_u2u32:
1867 case nir_op_u2u64:
1868 src[0] = ac_to_integer(&ctx->ac, src[0]);
1869 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1870 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1871 else
1872 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1873 break;
1874 case nir_op_i2i32:
1875 case nir_op_i2i64:
1876 src[0] = ac_to_integer(&ctx->ac, src[0]);
1877 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1878 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1879 else
1880 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1881 break;
1882 case nir_op_bcsel:
1883 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1884 break;
1885 case nir_op_find_lsb:
1886 src[0] = ac_to_integer(&ctx->ac, src[0]);
1887 result = emit_find_lsb(&ctx->ac, src[0]);
1888 break;
1889 case nir_op_ufind_msb:
1890 src[0] = ac_to_integer(&ctx->ac, src[0]);
1891 result = emit_ufind_msb(&ctx->ac, src[0]);
1892 break;
1893 case nir_op_ifind_msb:
1894 src[0] = ac_to_integer(&ctx->ac, src[0]);
1895 result = emit_ifind_msb(&ctx->ac, src[0]);
1896 break;
1897 case nir_op_uadd_carry:
1898 src[0] = ac_to_integer(&ctx->ac, src[0]);
1899 src[1] = ac_to_integer(&ctx->ac, src[1]);
1900 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1901 break;
1902 case nir_op_usub_borrow:
1903 src[0] = ac_to_integer(&ctx->ac, src[0]);
1904 src[1] = ac_to_integer(&ctx->ac, src[1]);
1905 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1906 break;
1907 case nir_op_b2f:
1908 result = emit_b2f(&ctx->ac, src[0]);
1909 break;
1910 case nir_op_f2b:
1911 result = emit_f2b(&ctx->ac, src[0]);
1912 break;
1913 case nir_op_b2i:
1914 result = emit_b2i(&ctx->ac, src[0]);
1915 break;
1916 case nir_op_i2b:
1917 src[0] = ac_to_integer(&ctx->ac, src[0]);
1918 result = emit_i2b(&ctx->ac, src[0]);
1919 break;
1920 case nir_op_fquantize2f16:
1921 result = emit_f2f16(ctx->nctx, src[0]);
1922 break;
1923 case nir_op_umul_high:
1924 src[0] = ac_to_integer(&ctx->ac, src[0]);
1925 src[1] = ac_to_integer(&ctx->ac, src[1]);
1926 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1927 break;
1928 case nir_op_imul_high:
1929 src[0] = ac_to_integer(&ctx->ac, src[0]);
1930 src[1] = ac_to_integer(&ctx->ac, src[1]);
1931 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1932 break;
1933 case nir_op_pack_half_2x16:
1934 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1935 break;
1936 case nir_op_unpack_half_2x16:
1937 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1938 break;
1939 case nir_op_fddx:
1940 case nir_op_fddy:
1941 case nir_op_fddx_fine:
1942 case nir_op_fddy_fine:
1943 case nir_op_fddx_coarse:
1944 case nir_op_fddy_coarse:
1945 result = emit_ddxy(ctx, instr->op, src[0]);
1946 break;
1947
1948 case nir_op_unpack_64_2x32_split_x: {
1949 assert(instr->src[0].src.ssa->num_components == 1);
1950 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1951 LLVMVectorType(ctx->ac.i32, 2),
1952 "");
1953 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1954 ctx->ac.i32_0, "");
1955 break;
1956 }
1957
1958 case nir_op_unpack_64_2x32_split_y: {
1959 assert(instr->src[0].src.ssa->num_components == 1);
1960 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1961 LLVMVectorType(ctx->ac.i32, 2),
1962 "");
1963 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1964 ctx->ac.i32_1, "");
1965 break;
1966 }
1967
1968 case nir_op_pack_64_2x32_split: {
1969 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1970 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1971 src[0], ctx->ac.i32_0, "");
1972 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1973 src[1], ctx->ac.i32_1, "");
1974 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1975 break;
1976 }
1977
1978 default:
1979 fprintf(stderr, "Unknown NIR alu instr: ");
1980 nir_print_instr(&instr->instr, stderr);
1981 fprintf(stderr, "\n");
1982 abort();
1983 }
1984
1985 if (result) {
1986 assert(instr->dest.dest.is_ssa);
1987 result = ac_to_integer(&ctx->ac, result);
1988 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1989 result);
1990 }
1991 }
1992
1993 static void visit_load_const(struct ac_nir_context *ctx,
1994 const nir_load_const_instr *instr)
1995 {
1996 LLVMValueRef values[4], value = NULL;
1997 LLVMTypeRef element_type =
1998 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1999
2000 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2001 switch (instr->def.bit_size) {
2002 case 32:
2003 values[i] = LLVMConstInt(element_type,
2004 instr->value.u32[i], false);
2005 break;
2006 case 64:
2007 values[i] = LLVMConstInt(element_type,
2008 instr->value.u64[i], false);
2009 break;
2010 default:
2011 fprintf(stderr,
2012 "unsupported nir load_const bit_size: %d\n",
2013 instr->def.bit_size);
2014 abort();
2015 }
2016 }
2017 if (instr->def.num_components > 1) {
2018 value = LLVMConstVector(values, instr->def.num_components);
2019 } else
2020 value = values[0];
2021
2022 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2023 }
2024
2025 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2026 LLVMTypeRef type)
2027 {
2028 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2029 return LLVMBuildBitCast(ctx->builder, ptr,
2030 LLVMPointerType(type, addr_space), "");
2031 }
2032
2033 static LLVMValueRef
2034 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2035 {
2036 LLVMValueRef size =
2037 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2038 LLVMConstInt(ctx->ac.i32, 2, false), "");
2039
2040 /* VI only */
2041 if (ctx->ac.chip_class == VI && in_elements) {
2042 /* On VI, the descriptor contains the size in bytes,
2043 * but TXQ must return the size in elements.
2044 * The stride is always non-zero for resources using TXQ.
2045 */
2046 LLVMValueRef stride =
2047 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2048 LLVMConstInt(ctx->ac.i32, 1, false), "");
2049 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2050 LLVMConstInt(ctx->ac.i32, 16, false), "");
2051 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2052 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2053
2054 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2055 }
2056 return size;
2057 }
2058
2059 /**
2060 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2061 * intrinsic names).
2062 */
2063 static void build_int_type_name(
2064 LLVMTypeRef type,
2065 char *buf, unsigned bufsize)
2066 {
2067 assert(bufsize >= 6);
2068
2069 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2070 snprintf(buf, bufsize, "v%ui32",
2071 LLVMGetVectorSize(type));
2072 else
2073 strcpy(buf, "i32");
2074 }
2075
2076 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2077 struct ac_image_args *args,
2078 const nir_tex_instr *instr)
2079 {
2080 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2081 LLVMValueRef coord = args->addr;
2082 LLVMValueRef half_texel[2];
2083 LLVMValueRef compare_cube_wa = NULL;
2084 LLVMValueRef result;
2085 int c;
2086 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2087
2088 //TODO Rect
2089 {
2090 struct ac_image_args txq_args = { 0 };
2091
2092 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2093 txq_args.opcode = ac_image_get_resinfo;
2094 txq_args.dmask = 0xf;
2095 txq_args.addr = ctx->i32_0;
2096 txq_args.resource = args->resource;
2097 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2098
2099 for (c = 0; c < 2; c++) {
2100 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2101 LLVMConstInt(ctx->i32, c, false), "");
2102 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2103 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2104 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2105 LLVMConstReal(ctx->f32, -0.5), "");
2106 }
2107 }
2108
2109 LLVMValueRef orig_coords = args->addr;
2110
2111 for (c = 0; c < 2; c++) {
2112 LLVMValueRef tmp;
2113 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2114 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2115 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2116 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2117 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2118 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2119 }
2120
2121
2122 /*
2123 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2124 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2125 * workaround by sampling using a scaled type and converting.
2126 * This is taken from amdgpu-pro shaders.
2127 */
2128 /* NOTE this produces some ugly code compared to amdgpu-pro,
2129 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2130 * and then reads them back. -pro generates two selects,
2131 * one s_cmp for the descriptor rewriting
2132 * one v_cmp for the coordinate and result changes.
2133 */
2134 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2135 LLVMValueRef tmp, tmp2;
2136
2137 /* workaround 8/8/8/8 uint/sint cube gather bug */
2138 /* first detect it then change to a scaled read and f2i */
2139 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2140 tmp2 = tmp;
2141
2142 /* extract the DATA_FORMAT */
2143 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2144 LLVMConstInt(ctx->i32, 6, false), false);
2145
2146 /* is the DATA_FORMAT == 8_8_8_8 */
2147 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2148
2149 if (stype == GLSL_TYPE_UINT)
2150 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2151 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2152 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2153 else
2154 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2155 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2156 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2157
2158 /* replace the NUM FORMAT in the descriptor */
2159 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2160 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2161
2162 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2163
2164 /* don't modify the coordinates for this case */
2165 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2166 }
2167 args->addr = coord;
2168 result = ac_build_image_opcode(ctx, args);
2169
2170 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2171 LLVMValueRef tmp, tmp2;
2172
2173 /* if the cube workaround is in place, f2i the result. */
2174 for (c = 0; c < 4; c++) {
2175 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2176 if (stype == GLSL_TYPE_UINT)
2177 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2178 else
2179 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2180 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2181 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2182 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2183 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2184 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2185 }
2186 }
2187 return result;
2188 }
2189
2190 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2191 const nir_tex_instr *instr,
2192 bool lod_is_zero,
2193 struct ac_image_args *args)
2194 {
2195 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2196 return ac_build_buffer_load_format(&ctx->ac,
2197 args->resource,
2198 args->addr,
2199 LLVMConstInt(ctx->ac.i32, 0, false),
2200 true);
2201 }
2202
2203 args->opcode = ac_image_sample;
2204 args->compare = instr->is_shadow;
2205
2206 switch (instr->op) {
2207 case nir_texop_txf:
2208 case nir_texop_txf_ms:
2209 case nir_texop_samples_identical:
2210 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2211 args->compare = false;
2212 args->offset = false;
2213 break;
2214 case nir_texop_txb:
2215 args->bias = true;
2216 break;
2217 case nir_texop_txl:
2218 if (lod_is_zero)
2219 args->level_zero = true;
2220 else
2221 args->lod = true;
2222 break;
2223 case nir_texop_txs:
2224 case nir_texop_query_levels:
2225 args->opcode = ac_image_get_resinfo;
2226 break;
2227 case nir_texop_tex:
2228 if (ctx->stage != MESA_SHADER_FRAGMENT)
2229 args->level_zero = true;
2230 break;
2231 case nir_texop_txd:
2232 args->deriv = true;
2233 break;
2234 case nir_texop_tg4:
2235 args->opcode = ac_image_gather4;
2236 args->level_zero = true;
2237 break;
2238 case nir_texop_lod:
2239 args->opcode = ac_image_get_lod;
2240 args->compare = false;
2241 args->offset = false;
2242 break;
2243 default:
2244 break;
2245 }
2246
2247 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2248 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2249 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2250 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2251 }
2252 }
2253 return ac_build_image_opcode(&ctx->ac, args);
2254 }
2255
2256 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2257 nir_intrinsic_instr *instr)
2258 {
2259 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2260 unsigned desc_set = nir_intrinsic_desc_set(instr);
2261 unsigned binding = nir_intrinsic_binding(instr);
2262 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2263 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2264 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2265 unsigned base_offset = layout->binding[binding].offset;
2266 LLVMValueRef offset, stride;
2267
2268 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2269 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2270 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2271 layout->binding[binding].dynamic_offset_offset;
2272 desc_ptr = ctx->push_constants;
2273 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2274 stride = LLVMConstInt(ctx->i32, 16, false);
2275 } else
2276 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2277
2278 offset = LLVMConstInt(ctx->i32, base_offset, false);
2279 index = LLVMBuildMul(ctx->builder, index, stride, "");
2280 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2281
2282 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2283 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2284 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2285
2286 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2287 }
2288
2289 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2290 nir_intrinsic_instr *instr)
2291 {
2292 LLVMValueRef ptr, addr;
2293
2294 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2295 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2296
2297 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2298 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2299
2300 return LLVMBuildLoad(ctx->builder, ptr, "");
2301 }
2302
2303 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2304 const nir_intrinsic_instr *instr)
2305 {
2306 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2307
2308 return get_buffer_size(ctx, desc, false);
2309 }
2310 static void visit_store_ssbo(struct ac_nir_context *ctx,
2311 nir_intrinsic_instr *instr)
2312 {
2313 const char *store_name;
2314 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2315 LLVMTypeRef data_type = ctx->ac.f32;
2316 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2317 int components_32bit = elem_size_mult * instr->num_components;
2318 unsigned writemask = nir_intrinsic_write_mask(instr);
2319 LLVMValueRef base_data, base_offset;
2320 LLVMValueRef params[6];
2321 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2322
2323 params[1] = ctx->abi->load_ssbo(ctx->abi,
2324 get_src(ctx, instr->src[1]), true);
2325 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2326 params[4] = i1false; /* glc */
2327 params[5] = i1false; /* slc */
2328
2329 if (components_32bit > 1)
2330 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2331
2332 base_data = ac_to_float(&ctx->ac, src_data);
2333 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2334 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2335 data_type, "");
2336 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2337 while (writemask) {
2338 int start, count;
2339 LLVMValueRef data;
2340 LLVMValueRef offset;
2341 LLVMValueRef tmp;
2342 u_bit_scan_consecutive_range(&writemask, &start, &count);
2343
2344 /* Due to an LLVM limitation, split 3-element writes
2345 * into a 2-element and a 1-element write. */
2346 if (count == 3) {
2347 writemask |= 1 << (start + 2);
2348 count = 2;
2349 }
2350
2351 start *= elem_size_mult;
2352 count *= elem_size_mult;
2353
2354 if (count > 4) {
2355 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2356 count = 4;
2357 }
2358
2359 if (count == 4) {
2360 store_name = "llvm.amdgcn.buffer.store.v4f32";
2361 data = base_data;
2362 } else if (count == 2) {
2363 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2364
2365 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2366 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2367 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2368 ctx->ac.i32_0, "");
2369
2370 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2371 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2372 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2373 ctx->ac.i32_1, "");
2374 store_name = "llvm.amdgcn.buffer.store.v2f32";
2375
2376 } else {
2377 assert(count == 1);
2378 if (get_llvm_num_components(base_data) > 1)
2379 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2380 LLVMConstInt(ctx->ac.i32, start, false), "");
2381 else
2382 data = base_data;
2383 store_name = "llvm.amdgcn.buffer.store.f32";
2384 }
2385
2386 offset = base_offset;
2387 if (start != 0) {
2388 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2389 }
2390 params[0] = data;
2391 params[3] = offset;
2392 ac_build_intrinsic(&ctx->ac, store_name,
2393 ctx->ac.voidt, params, 6, 0);
2394 }
2395 }
2396
2397 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2398 const nir_intrinsic_instr *instr)
2399 {
2400 const char *name;
2401 LLVMValueRef params[6];
2402 int arg_count = 0;
2403
2404 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2405 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2406 }
2407 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2408 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2409 get_src(ctx, instr->src[0]),
2410 true);
2411 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2412 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2413 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2414
2415 switch (instr->intrinsic) {
2416 case nir_intrinsic_ssbo_atomic_add:
2417 name = "llvm.amdgcn.buffer.atomic.add";
2418 break;
2419 case nir_intrinsic_ssbo_atomic_imin:
2420 name = "llvm.amdgcn.buffer.atomic.smin";
2421 break;
2422 case nir_intrinsic_ssbo_atomic_umin:
2423 name = "llvm.amdgcn.buffer.atomic.umin";
2424 break;
2425 case nir_intrinsic_ssbo_atomic_imax:
2426 name = "llvm.amdgcn.buffer.atomic.smax";
2427 break;
2428 case nir_intrinsic_ssbo_atomic_umax:
2429 name = "llvm.amdgcn.buffer.atomic.umax";
2430 break;
2431 case nir_intrinsic_ssbo_atomic_and:
2432 name = "llvm.amdgcn.buffer.atomic.and";
2433 break;
2434 case nir_intrinsic_ssbo_atomic_or:
2435 name = "llvm.amdgcn.buffer.atomic.or";
2436 break;
2437 case nir_intrinsic_ssbo_atomic_xor:
2438 name = "llvm.amdgcn.buffer.atomic.xor";
2439 break;
2440 case nir_intrinsic_ssbo_atomic_exchange:
2441 name = "llvm.amdgcn.buffer.atomic.swap";
2442 break;
2443 case nir_intrinsic_ssbo_atomic_comp_swap:
2444 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2445 break;
2446 default:
2447 abort();
2448 }
2449
2450 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2451 }
2452
2453 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2454 const nir_intrinsic_instr *instr)
2455 {
2456 LLVMValueRef results[2];
2457 int load_components;
2458 int num_components = instr->num_components;
2459 if (instr->dest.ssa.bit_size == 64)
2460 num_components *= 2;
2461
2462 for (int i = 0; i < num_components; i += load_components) {
2463 load_components = MIN2(num_components - i, 4);
2464 const char *load_name;
2465 LLVMTypeRef data_type = ctx->ac.f32;
2466 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2467 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2468
2469 if (load_components == 3)
2470 data_type = LLVMVectorType(ctx->ac.f32, 4);
2471 else if (load_components > 1)
2472 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2473
2474 if (load_components >= 3)
2475 load_name = "llvm.amdgcn.buffer.load.v4f32";
2476 else if (load_components == 2)
2477 load_name = "llvm.amdgcn.buffer.load.v2f32";
2478 else if (load_components == 1)
2479 load_name = "llvm.amdgcn.buffer.load.f32";
2480 else
2481 unreachable("unhandled number of components");
2482
2483 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2484 LLVMValueRef params[] = {
2485 ctx->abi->load_ssbo(ctx->abi,
2486 get_src(ctx, instr->src[0]),
2487 false),
2488 LLVMConstInt(ctx->ac.i32, 0, false),
2489 offset,
2490 i1false,
2491 i1false,
2492 };
2493
2494 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2495
2496 }
2497
2498 LLVMValueRef ret = results[0];
2499 if (num_components > 4 || num_components == 3) {
2500 LLVMValueRef masks[] = {
2501 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2502 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2503 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2504 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2505 };
2506
2507 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2508 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2509 results[num_components > 4 ? 1 : 0], swizzle, "");
2510 }
2511
2512 return LLVMBuildBitCast(ctx->ac.builder, ret,
2513 get_def_type(ctx, &instr->dest.ssa), "");
2514 }
2515
2516 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2517 const nir_intrinsic_instr *instr)
2518 {
2519 LLVMValueRef results[8], ret;
2520 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2521 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2522 int num_components = instr->num_components;
2523
2524 if (ctx->abi->load_ubo)
2525 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2526
2527 if (instr->dest.ssa.bit_size == 64)
2528 num_components *= 2;
2529
2530 for (unsigned i = 0; i < num_components; ++i) {
2531 LLVMValueRef params[] = {
2532 rsrc,
2533 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2534 offset, "")
2535 };
2536 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2537 params, 2,
2538 AC_FUNC_ATTR_READNONE |
2539 AC_FUNC_ATTR_LEGACY);
2540 }
2541
2542
2543 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2544 return LLVMBuildBitCast(ctx->ac.builder, ret,
2545 get_def_type(ctx, &instr->dest.ssa), "");
2546 }
2547
2548 static void
2549 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2550 bool vs_in, unsigned *vertex_index_out,
2551 LLVMValueRef *vertex_index_ref,
2552 unsigned *const_out, LLVMValueRef *indir_out)
2553 {
2554 unsigned const_offset = 0;
2555 nir_deref *tail = &deref->deref;
2556 LLVMValueRef offset = NULL;
2557
2558 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2559 tail = tail->child;
2560 nir_deref_array *deref_array = nir_deref_as_array(tail);
2561 if (vertex_index_out)
2562 *vertex_index_out = deref_array->base_offset;
2563
2564 if (vertex_index_ref) {
2565 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2566 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2567 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2568 }
2569 *vertex_index_ref = vtx;
2570 }
2571 }
2572
2573 if (deref->var->data.compact) {
2574 assert(tail->child->deref_type == nir_deref_type_array);
2575 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2576 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2577 /* We always lower indirect dereferences for "compact" array vars. */
2578 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2579
2580 const_offset = deref_array->base_offset;
2581 goto out;
2582 }
2583
2584 while (tail->child != NULL) {
2585 const struct glsl_type *parent_type = tail->type;
2586 tail = tail->child;
2587
2588 if (tail->deref_type == nir_deref_type_array) {
2589 nir_deref_array *deref_array = nir_deref_as_array(tail);
2590 LLVMValueRef index, stride, local_offset;
2591 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2592
2593 const_offset += size * deref_array->base_offset;
2594 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2595 continue;
2596
2597 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2598 index = get_src(ctx, deref_array->indirect);
2599 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2600 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2601
2602 if (offset)
2603 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2604 else
2605 offset = local_offset;
2606 } else if (tail->deref_type == nir_deref_type_struct) {
2607 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2608
2609 for (unsigned i = 0; i < deref_struct->index; i++) {
2610 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2611 const_offset += glsl_count_attribute_slots(ft, vs_in);
2612 }
2613 } else
2614 unreachable("unsupported deref type");
2615
2616 }
2617 out:
2618 if (const_offset && offset)
2619 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2620 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2621 "");
2622
2623 *const_out = const_offset;
2624 *indir_out = offset;
2625 }
2626
2627 static LLVMValueRef
2628 lds_load(struct nir_to_llvm_context *ctx,
2629 LLVMValueRef dw_addr)
2630 {
2631 LLVMValueRef value;
2632 value = ac_build_load(&ctx->ac, ctx->lds, dw_addr);
2633 return value;
2634 }
2635
2636 static void
2637 lds_store(struct nir_to_llvm_context *ctx,
2638 LLVMValueRef dw_addr, LLVMValueRef value)
2639 {
2640 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2641 ac_build_indexed_store(&ctx->ac, ctx->lds,
2642 dw_addr, value);
2643 }
2644
2645 /* The offchip buffer layout for TCS->TES is
2646 *
2647 * - attribute 0 of patch 0 vertex 0
2648 * - attribute 0 of patch 0 vertex 1
2649 * - attribute 0 of patch 0 vertex 2
2650 * ...
2651 * - attribute 0 of patch 1 vertex 0
2652 * - attribute 0 of patch 1 vertex 1
2653 * ...
2654 * - attribute 1 of patch 0 vertex 0
2655 * - attribute 1 of patch 0 vertex 1
2656 * ...
2657 * - per patch attribute 0 of patch 0
2658 * - per patch attribute 0 of patch 1
2659 * ...
2660 *
2661 * Note that every attribute has 4 components.
2662 */
2663 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2664 LLVMValueRef vertex_index,
2665 LLVMValueRef param_index)
2666 {
2667 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2668 LLVMValueRef param_stride, constant16;
2669 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2670
2671 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2672 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2673 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2674 num_patches, "");
2675
2676 constant16 = LLVMConstInt(ctx->i32, 16, false);
2677 if (vertex_index) {
2678 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2679 vertices_per_patch, "");
2680
2681 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2682 vertex_index, "");
2683
2684 param_stride = total_vertices;
2685 } else {
2686 base_addr = rel_patch_id;
2687 param_stride = num_patches;
2688 }
2689
2690 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2691 LLVMBuildMul(ctx->builder, param_index,
2692 param_stride, ""), "");
2693
2694 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2695
2696 if (!vertex_index) {
2697 LLVMValueRef patch_data_offset =
2698 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2699
2700 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2701 patch_data_offset, "");
2702 }
2703 return base_addr;
2704 }
2705
2706 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2707 unsigned param,
2708 unsigned const_index,
2709 bool is_compact,
2710 LLVMValueRef vertex_index,
2711 LLVMValueRef indir_index)
2712 {
2713 LLVMValueRef param_index;
2714
2715 if (indir_index)
2716 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2717 indir_index, "");
2718 else {
2719 if (const_index && !is_compact)
2720 param += const_index;
2721 param_index = LLVMConstInt(ctx->i32, param, false);
2722 }
2723 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2724 }
2725
2726 static void
2727 mark_tess_output(struct nir_to_llvm_context *ctx,
2728 bool is_patch, uint32_t param)
2729
2730 {
2731 if (is_patch) {
2732 ctx->tess_patch_outputs_written |= (1ull << param);
2733 } else
2734 ctx->tess_outputs_written |= (1ull << param);
2735 }
2736
2737 static LLVMValueRef
2738 get_dw_address(struct nir_to_llvm_context *ctx,
2739 LLVMValueRef dw_addr,
2740 unsigned param,
2741 unsigned const_index,
2742 bool compact_const_index,
2743 LLVMValueRef vertex_index,
2744 LLVMValueRef stride,
2745 LLVMValueRef indir_index)
2746
2747 {
2748
2749 if (vertex_index) {
2750 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2751 LLVMBuildMul(ctx->builder,
2752 vertex_index,
2753 stride, ""), "");
2754 }
2755
2756 if (indir_index)
2757 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2758 LLVMBuildMul(ctx->builder, indir_index,
2759 LLVMConstInt(ctx->i32, 4, false), ""), "");
2760 else if (const_index && !compact_const_index)
2761 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2762 LLVMConstInt(ctx->i32, const_index, false), "");
2763
2764 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2765 LLVMConstInt(ctx->i32, param * 4, false), "");
2766
2767 if (const_index && compact_const_index)
2768 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2769 LLVMConstInt(ctx->i32, const_index, false), "");
2770 return dw_addr;
2771 }
2772
2773 static LLVMValueRef
2774 load_tcs_input(struct nir_to_llvm_context *ctx,
2775 nir_intrinsic_instr *instr)
2776 {
2777 LLVMValueRef dw_addr, stride;
2778 unsigned const_index;
2779 LLVMValueRef vertex_index;
2780 LLVMValueRef indir_index;
2781 unsigned param;
2782 LLVMValueRef value[4], result;
2783 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2784 const bool is_compact = instr->variables[0]->var->data.compact;
2785 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2786 get_deref_offset(ctx->nir, instr->variables[0],
2787 false, NULL, per_vertex ? &vertex_index : NULL,
2788 &const_index, &indir_index);
2789
2790 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2791 dw_addr = get_tcs_in_current_patch_offset(ctx);
2792 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2793 indir_index);
2794
2795 for (unsigned i = 0; i < instr->num_components; i++) {
2796 value[i] = lds_load(ctx, dw_addr);
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 ctx->i32one, "");
2799 }
2800 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2801 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2802 return result;
2803 }
2804
2805 static LLVMValueRef
2806 load_tcs_output(struct nir_to_llvm_context *ctx,
2807 nir_intrinsic_instr *instr)
2808 {
2809 LLVMValueRef dw_addr;
2810 LLVMValueRef stride = NULL;
2811 LLVMValueRef value[4], result;
2812 LLVMValueRef vertex_index = NULL;
2813 LLVMValueRef indir_index = NULL;
2814 unsigned const_index = 0;
2815 unsigned param;
2816 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2817 const bool is_compact = instr->variables[0]->var->data.compact;
2818 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2819 get_deref_offset(ctx->nir, instr->variables[0],
2820 false, NULL, per_vertex ? &vertex_index : NULL,
2821 &const_index, &indir_index);
2822
2823 if (!instr->variables[0]->var->data.patch) {
2824 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2825 dw_addr = get_tcs_out_current_patch_offset(ctx);
2826 } else {
2827 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2828 }
2829
2830 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2831 indir_index);
2832
2833 for (unsigned i = 0; i < instr->num_components; i++) {
2834 value[i] = lds_load(ctx, dw_addr);
2835 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2836 ctx->i32one, "");
2837 }
2838 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2839 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2840 return result;
2841 }
2842
2843 static void
2844 store_tcs_output(struct nir_to_llvm_context *ctx,
2845 nir_intrinsic_instr *instr,
2846 LLVMValueRef src,
2847 unsigned writemask)
2848 {
2849 LLVMValueRef dw_addr;
2850 LLVMValueRef stride = NULL;
2851 LLVMValueRef buf_addr = NULL;
2852 LLVMValueRef vertex_index = NULL;
2853 LLVMValueRef indir_index = NULL;
2854 unsigned const_index = 0;
2855 unsigned param;
2856 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2857 const bool is_compact = instr->variables[0]->var->data.compact;
2858
2859 get_deref_offset(ctx->nir, instr->variables[0],
2860 false, NULL, per_vertex ? &vertex_index : NULL,
2861 &const_index, &indir_index);
2862
2863 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2864 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2865 is_compact && const_index > 3) {
2866 const_index -= 3;
2867 param++;
2868 }
2869
2870 if (!instr->variables[0]->var->data.patch) {
2871 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2872 dw_addr = get_tcs_out_current_patch_offset(ctx);
2873 } else {
2874 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2875 }
2876
2877 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2878
2879 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2880 indir_index);
2881 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2882 vertex_index, indir_index);
2883
2884 unsigned base = is_compact ? const_index : 0;
2885 for (unsigned chan = 0; chan < 8; chan++) {
2886 bool is_tess_factor = false;
2887 if (!(writemask & (1 << chan)))
2888 continue;
2889 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2890
2891 lds_store(ctx, dw_addr, value);
2892
2893 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2894 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2895 is_tess_factor = true;
2896
2897 if (!is_tess_factor && writemask != 0xF)
2898 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2899 buf_addr, ctx->oc_lds,
2900 4 * (base + chan), 1, 0, true, false);
2901
2902 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2903 ctx->i32one, "");
2904 }
2905
2906 if (writemask == 0xF) {
2907 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2908 buf_addr, ctx->oc_lds,
2909 (base * 4), 1, 0, true, false);
2910 }
2911 }
2912
2913 static LLVMValueRef
2914 load_tes_input(struct nir_to_llvm_context *ctx,
2915 const nir_intrinsic_instr *instr)
2916 {
2917 LLVMValueRef buf_addr;
2918 LLVMValueRef result;
2919 LLVMValueRef vertex_index = NULL;
2920 LLVMValueRef indir_index = NULL;
2921 unsigned const_index = 0;
2922 unsigned param;
2923 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2924 const bool is_compact = instr->variables[0]->var->data.compact;
2925
2926 get_deref_offset(ctx->nir, instr->variables[0],
2927 false, NULL, per_vertex ? &vertex_index : NULL,
2928 &const_index, &indir_index);
2929 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2930 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2931 is_compact && const_index > 3) {
2932 const_index -= 3;
2933 param++;
2934 }
2935 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2936 is_compact, vertex_index, indir_index);
2937
2938 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2939 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2940 result = trim_vector(&ctx->ac, result, instr->num_components);
2941 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2942 return result;
2943 }
2944
2945 static LLVMValueRef
2946 load_gs_input(struct nir_to_llvm_context *ctx,
2947 nir_intrinsic_instr *instr)
2948 {
2949 LLVMValueRef indir_index, vtx_offset;
2950 unsigned const_index;
2951 LLVMValueRef args[9];
2952 unsigned param, vtx_offset_param;
2953 LLVMValueRef value[4], result;
2954 unsigned vertex_index;
2955 get_deref_offset(ctx->nir, instr->variables[0],
2956 false, &vertex_index, NULL,
2957 &const_index, &indir_index);
2958 vtx_offset_param = vertex_index;
2959 assert(vtx_offset_param < 6);
2960 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2961 LLVMConstInt(ctx->i32, 4, false), "");
2962
2963 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2964 for (unsigned i = 0; i < instr->num_components; i++) {
2965
2966 args[0] = ctx->esgs_ring;
2967 args[1] = vtx_offset;
2968 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2969 args[3] = ctx->i32zero;
2970 args[4] = ctx->i32one; /* OFFEN */
2971 args[5] = ctx->i32zero; /* IDXEN */
2972 args[6] = ctx->i32one; /* GLC */
2973 args[7] = ctx->i32zero; /* SLC */
2974 args[8] = ctx->i32zero; /* TFE */
2975
2976 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2977 ctx->i32, args, 9,
2978 AC_FUNC_ATTR_READONLY |
2979 AC_FUNC_ATTR_LEGACY);
2980 }
2981 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2982
2983 return result;
2984 }
2985
2986 static LLVMValueRef
2987 build_gep_for_deref(struct ac_nir_context *ctx,
2988 nir_deref_var *deref)
2989 {
2990 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2991 assert(entry->data);
2992 LLVMValueRef val = entry->data;
2993 nir_deref *tail = deref->deref.child;
2994 while (tail != NULL) {
2995 LLVMValueRef offset;
2996 switch (tail->deref_type) {
2997 case nir_deref_type_array: {
2998 nir_deref_array *array = nir_deref_as_array(tail);
2999 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3000 if (array->deref_array_type ==
3001 nir_deref_array_type_indirect) {
3002 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3003 get_src(ctx,
3004 array->indirect),
3005 "");
3006 }
3007 break;
3008 }
3009 case nir_deref_type_struct: {
3010 nir_deref_struct *deref_struct =
3011 nir_deref_as_struct(tail);
3012 offset = LLVMConstInt(ctx->ac.i32,
3013 deref_struct->index, 0);
3014 break;
3015 }
3016 default:
3017 unreachable("bad deref type");
3018 }
3019 val = ac_build_gep0(&ctx->ac, val, offset);
3020 tail = tail->child;
3021 }
3022 return val;
3023 }
3024
3025 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3026 nir_intrinsic_instr *instr)
3027 {
3028 LLVMValueRef values[8];
3029 int idx = instr->variables[0]->var->data.driver_location;
3030 int ve = instr->dest.ssa.num_components;
3031 LLVMValueRef indir_index;
3032 LLVMValueRef ret;
3033 unsigned const_index;
3034 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3035 instr->variables[0]->var->data.mode == nir_var_shader_in;
3036 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3037 &const_index, &indir_index);
3038
3039 if (instr->dest.ssa.bit_size == 64)
3040 ve *= 2;
3041
3042 switch (instr->variables[0]->var->data.mode) {
3043 case nir_var_shader_in:
3044 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3045 return load_tcs_input(ctx->nctx, instr);
3046 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3047 return load_tes_input(ctx->nctx, instr);
3048 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3049 return load_gs_input(ctx->nctx, instr);
3050 }
3051 for (unsigned chan = 0; chan < ve; chan++) {
3052 if (indir_index) {
3053 unsigned count = glsl_count_attribute_slots(
3054 instr->variables[0]->var->type,
3055 ctx->stage == MESA_SHADER_VERTEX);
3056 count -= chan / 4;
3057 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3058 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3059 4, false, true);
3060
3061 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3062 tmp_vec,
3063 indir_index, "");
3064 } else
3065 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3066 }
3067 break;
3068 case nir_var_local:
3069 for (unsigned chan = 0; chan < ve; chan++) {
3070 if (indir_index) {
3071 unsigned count = glsl_count_attribute_slots(
3072 instr->variables[0]->var->type, false);
3073 count -= chan / 4;
3074 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3075 &ctx->ac, ctx->locals + idx + chan, count,
3076 4, true, true);
3077
3078 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3079 tmp_vec,
3080 indir_index, "");
3081 } else {
3082 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3083 }
3084 }
3085 break;
3086 case nir_var_shared: {
3087 LLVMValueRef address = build_gep_for_deref(ctx,
3088 instr->variables[0]);
3089 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3090 return LLVMBuildBitCast(ctx->ac.builder, val,
3091 get_def_type(ctx, &instr->dest.ssa),
3092 "");
3093 }
3094 case nir_var_shader_out:
3095 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3096 return load_tcs_output(ctx->nctx, instr);
3097 for (unsigned chan = 0; chan < ve; chan++) {
3098 if (indir_index) {
3099 unsigned count = glsl_count_attribute_slots(
3100 instr->variables[0]->var->type, false);
3101 count -= chan / 4;
3102 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3103 &ctx->ac, ctx->outputs + idx + chan, count,
3104 4, true, true);
3105
3106 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3107 tmp_vec,
3108 indir_index, "");
3109 } else {
3110 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3111 ctx->outputs[idx + chan + const_index * 4],
3112 "");
3113 }
3114 }
3115 break;
3116 default:
3117 unreachable("unhandle variable mode");
3118 }
3119 ret = ac_build_gather_values(&ctx->ac, values, ve);
3120 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3121 }
3122
3123 static void
3124 visit_store_var(struct ac_nir_context *ctx,
3125 nir_intrinsic_instr *instr)
3126 {
3127 LLVMValueRef temp_ptr, value;
3128 int idx = instr->variables[0]->var->data.driver_location;
3129 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3130 int writemask = instr->const_index[0];
3131 LLVMValueRef indir_index;
3132 unsigned const_index;
3133 get_deref_offset(ctx, instr->variables[0], false,
3134 NULL, NULL, &const_index, &indir_index);
3135
3136 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3137 int old_writemask = writemask;
3138
3139 src = LLVMBuildBitCast(ctx->ac.builder, src,
3140 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3141 "");
3142
3143 writemask = 0;
3144 for (unsigned chan = 0; chan < 4; chan++) {
3145 if (old_writemask & (1 << chan))
3146 writemask |= 3u << (2 * chan);
3147 }
3148 }
3149
3150 switch (instr->variables[0]->var->data.mode) {
3151 case nir_var_shader_out:
3152
3153 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3154 store_tcs_output(ctx->nctx, instr, src, writemask);
3155 return;
3156 }
3157
3158 for (unsigned chan = 0; chan < 8; chan++) {
3159 int stride = 4;
3160 if (!(writemask & (1 << chan)))
3161 continue;
3162
3163 value = llvm_extract_elem(&ctx->ac, src, chan);
3164
3165 if (instr->variables[0]->var->data.compact)
3166 stride = 1;
3167 if (indir_index) {
3168 unsigned count = glsl_count_attribute_slots(
3169 instr->variables[0]->var->type, false);
3170 count -= chan / 4;
3171 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3172 &ctx->ac, ctx->outputs + idx + chan, count,
3173 stride, true, true);
3174
3175 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3176 value, indir_index, "");
3177 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3178 count, stride, tmp_vec);
3179
3180 } else {
3181 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3182
3183 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3184 }
3185 }
3186 break;
3187 case nir_var_local:
3188 for (unsigned chan = 0; chan < 8; chan++) {
3189 if (!(writemask & (1 << chan)))
3190 continue;
3191
3192 value = llvm_extract_elem(&ctx->ac, src, chan);
3193 if (indir_index) {
3194 unsigned count = glsl_count_attribute_slots(
3195 instr->variables[0]->var->type, false);
3196 count -= chan / 4;
3197 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3198 &ctx->ac, ctx->locals + idx + chan, count,
3199 4, true, true);
3200
3201 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3202 value, indir_index, "");
3203 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3204 count, 4, tmp_vec);
3205 } else {
3206 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3207
3208 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3209 }
3210 }
3211 break;
3212 case nir_var_shared: {
3213 int writemask = instr->const_index[0];
3214 LLVMValueRef address = build_gep_for_deref(ctx,
3215 instr->variables[0]);
3216 LLVMValueRef val = get_src(ctx, instr->src[0]);
3217 unsigned components =
3218 glsl_get_vector_elements(
3219 nir_deref_tail(&instr->variables[0]->deref)->type);
3220 if (writemask == (1 << components) - 1) {
3221 val = LLVMBuildBitCast(
3222 ctx->ac.builder, val,
3223 LLVMGetElementType(LLVMTypeOf(address)), "");
3224 LLVMBuildStore(ctx->ac.builder, val, address);
3225 } else {
3226 for (unsigned chan = 0; chan < 4; chan++) {
3227 if (!(writemask & (1 << chan)))
3228 continue;
3229 LLVMValueRef ptr =
3230 LLVMBuildStructGEP(ctx->ac.builder,
3231 address, chan, "");
3232 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3233 chan);
3234 src = LLVMBuildBitCast(
3235 ctx->ac.builder, src,
3236 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3237 LLVMBuildStore(ctx->ac.builder, src, ptr);
3238 }
3239 }
3240 break;
3241 }
3242 default:
3243 break;
3244 }
3245 }
3246
3247 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3248 {
3249 switch (dim) {
3250 case GLSL_SAMPLER_DIM_BUF:
3251 return 1;
3252 case GLSL_SAMPLER_DIM_1D:
3253 return array ? 2 : 1;
3254 case GLSL_SAMPLER_DIM_2D:
3255 return array ? 3 : 2;
3256 case GLSL_SAMPLER_DIM_MS:
3257 return array ? 4 : 3;
3258 case GLSL_SAMPLER_DIM_3D:
3259 case GLSL_SAMPLER_DIM_CUBE:
3260 return 3;
3261 case GLSL_SAMPLER_DIM_RECT:
3262 case GLSL_SAMPLER_DIM_SUBPASS:
3263 return 2;
3264 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3265 return 3;
3266 default:
3267 break;
3268 }
3269 return 0;
3270 }
3271
3272
3273
3274 /* Adjust the sample index according to FMASK.
3275 *
3276 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3277 * which is the identity mapping. Each nibble says which physical sample
3278 * should be fetched to get that sample.
3279 *
3280 * For example, 0x11111100 means there are only 2 samples stored and
3281 * the second sample covers 3/4 of the pixel. When reading samples 0
3282 * and 1, return physical sample 0 (determined by the first two 0s
3283 * in FMASK), otherwise return physical sample 1.
3284 *
3285 * The sample index should be adjusted as follows:
3286 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3287 */
3288 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3289 LLVMValueRef coord_x, LLVMValueRef coord_y,
3290 LLVMValueRef coord_z,
3291 LLVMValueRef sample_index,
3292 LLVMValueRef fmask_desc_ptr)
3293 {
3294 LLVMValueRef fmask_load_address[4];
3295 LLVMValueRef res;
3296
3297 fmask_load_address[0] = coord_x;
3298 fmask_load_address[1] = coord_y;
3299 if (coord_z) {
3300 fmask_load_address[2] = coord_z;
3301 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3302 }
3303
3304 struct ac_image_args args = {0};
3305
3306 args.opcode = ac_image_load;
3307 args.da = coord_z ? true : false;
3308 args.resource = fmask_desc_ptr;
3309 args.dmask = 0xf;
3310 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3311
3312 res = ac_build_image_opcode(ctx, &args);
3313
3314 res = ac_to_integer(ctx, res);
3315 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3316 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3317
3318 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3319 res,
3320 ctx->i32_0, "");
3321
3322 LLVMValueRef sample_index4 =
3323 LLVMBuildMul(ctx->builder, sample_index, four, "");
3324 LLVMValueRef shifted_fmask =
3325 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3326 LLVMValueRef final_sample =
3327 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3328
3329 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3330 * resource descriptor is 0 (invalid),
3331 */
3332 LLVMValueRef fmask_desc =
3333 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3334 ctx->v8i32, "");
3335
3336 LLVMValueRef fmask_word1 =
3337 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3338 ctx->i32_1, "");
3339
3340 LLVMValueRef word1_is_nonzero =
3341 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3342 fmask_word1, ctx->i32_0, "");
3343
3344 /* Replace the MSAA sample index. */
3345 sample_index =
3346 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3347 final_sample, sample_index, "");
3348 return sample_index;
3349 }
3350
3351 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3352 const nir_intrinsic_instr *instr)
3353 {
3354 const struct glsl_type *type = instr->variables[0]->var->type;
3355 if(instr->variables[0]->deref.child)
3356 type = instr->variables[0]->deref.child->type;
3357
3358 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3359 LLVMValueRef coords[4];
3360 LLVMValueRef masks[] = {
3361 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3362 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3363 };
3364 LLVMValueRef res;
3365 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3366
3367 int count;
3368 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3369 bool is_array = glsl_sampler_type_is_array(type);
3370 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3371 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3372 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3373 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3374 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3375 count = image_type_to_components_count(dim, is_array);
3376
3377 if (is_ms) {
3378 LLVMValueRef fmask_load_address[3];
3379 int chan;
3380
3381 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3382 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3383 if (is_array)
3384 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3385 else
3386 fmask_load_address[2] = NULL;
3387 if (add_frag_pos) {
3388 for (chan = 0; chan < 2; ++chan)
3389 fmask_load_address[chan] =
3390 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3391 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3392 ctx->ac.i32, ""), "");
3393 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3394 }
3395 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3396 fmask_load_address[0],
3397 fmask_load_address[1],
3398 fmask_load_address[2],
3399 sample_index,
3400 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3401 }
3402 if (count == 1 && !gfx9_1d) {
3403 if (instr->src[0].ssa->num_components)
3404 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3405 else
3406 res = src0;
3407 } else {
3408 int chan;
3409 if (is_ms)
3410 count--;
3411 for (chan = 0; chan < count; ++chan) {
3412 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3413 }
3414 if (add_frag_pos) {
3415 for (chan = 0; chan < 2; ++chan)
3416 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3417 ctx->ac.i32, ""), "");
3418 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3419 count++;
3420 }
3421
3422 if (gfx9_1d) {
3423 if (is_array) {
3424 coords[2] = coords[1];
3425 coords[1] = ctx->ac.i32_0;
3426 } else
3427 coords[1] = ctx->ac.i32_0;
3428 count++;
3429 }
3430
3431 if (is_ms) {
3432 coords[count] = sample_index;
3433 count++;
3434 }
3435
3436 if (count == 3) {
3437 coords[3] = LLVMGetUndef(ctx->ac.i32);
3438 count = 4;
3439 }
3440 res = ac_build_gather_values(&ctx->ac, coords, count);
3441 }
3442 return res;
3443 }
3444
3445 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3446 const nir_intrinsic_instr *instr)
3447 {
3448 LLVMValueRef params[7];
3449 LLVMValueRef res;
3450 char intrinsic_name[64];
3451 const nir_variable *var = instr->variables[0]->var;
3452 const struct glsl_type *type = var->type;
3453 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3454 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3455
3456 if(instr->variables[0]->deref.child)
3457 type = instr->variables[0]->deref.child->type;
3458
3459 type = glsl_without_array(type);
3460 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3461 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3462 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3463 ctx->ac.i32_0, ""); /* vindex */
3464 params[2] = ctx->ac.i32_0; /* voffset */
3465 params[3] = i1false; /* glc */
3466 params[4] = i1false; /* slc */
3467 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3468 params, 5, 0);
3469
3470 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3471 res = ac_to_integer(&ctx->ac, res);
3472 } else {
3473 bool is_da = glsl_sampler_type_is_array(type) ||
3474 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3475 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3476 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3477 LLVMValueRef da = is_da ? i1true : i1false;
3478 LLVMValueRef glc = i1false;
3479 LLVMValueRef slc = i1false;
3480
3481 params[0] = get_image_coords(ctx, instr);
3482 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3483 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3484 if (HAVE_LLVM <= 0x0309) {
3485 params[3] = i1false; /* r128 */
3486 params[4] = da;
3487 params[5] = glc;
3488 params[6] = slc;
3489 } else {
3490 LLVMValueRef lwe = i1false;
3491 params[3] = glc;
3492 params[4] = slc;
3493 params[5] = lwe;
3494 params[6] = da;
3495 }
3496
3497 ac_get_image_intr_name("llvm.amdgcn.image.load",
3498 ctx->ac.v4f32, /* vdata */
3499 LLVMTypeOf(params[0]), /* coords */
3500 LLVMTypeOf(params[1]), /* rsrc */
3501 intrinsic_name, sizeof(intrinsic_name));
3502
3503 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3504 params, 7, AC_FUNC_ATTR_READONLY);
3505 }
3506 return ac_to_integer(&ctx->ac, res);
3507 }
3508
3509 static void visit_image_store(struct ac_nir_context *ctx,
3510 nir_intrinsic_instr *instr)
3511 {
3512 LLVMValueRef params[8];
3513 char intrinsic_name[64];
3514 const nir_variable *var = instr->variables[0]->var;
3515 const struct glsl_type *type = glsl_without_array(var->type);
3516 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3517 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3518 LLVMValueRef glc = i1false;
3519 bool force_glc = ctx->ac.chip_class == SI;
3520 if (force_glc)
3521 glc = i1true;
3522
3523 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3524 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3525 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3526 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3527 ctx->ac.i32_0, ""); /* vindex */
3528 params[3] = ctx->ac.i32_0; /* voffset */
3529 params[4] = glc; /* glc */
3530 params[5] = i1false; /* slc */
3531 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3532 params, 6, 0);
3533 } else {
3534 bool is_da = glsl_sampler_type_is_array(type) ||
3535 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3536 LLVMValueRef da = is_da ? i1true : i1false;
3537 LLVMValueRef slc = i1false;
3538
3539 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3540 params[1] = get_image_coords(ctx, instr); /* coords */
3541 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3542 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3543 if (HAVE_LLVM <= 0x0309) {
3544 params[4] = i1false; /* r128 */
3545 params[5] = da;
3546 params[6] = glc;
3547 params[7] = slc;
3548 } else {
3549 LLVMValueRef lwe = i1false;
3550 params[4] = glc;
3551 params[5] = slc;
3552 params[6] = lwe;
3553 params[7] = da;
3554 }
3555
3556 ac_get_image_intr_name("llvm.amdgcn.image.store",
3557 LLVMTypeOf(params[0]), /* vdata */
3558 LLVMTypeOf(params[1]), /* coords */
3559 LLVMTypeOf(params[2]), /* rsrc */
3560 intrinsic_name, sizeof(intrinsic_name));
3561
3562 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3563 params, 8, 0);
3564 }
3565
3566 }
3567
3568 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3569 const nir_intrinsic_instr *instr)
3570 {
3571 LLVMValueRef params[7];
3572 int param_count = 0;
3573 const nir_variable *var = instr->variables[0]->var;
3574
3575 const char *atomic_name;
3576 char intrinsic_name[41];
3577 const struct glsl_type *type = glsl_without_array(var->type);
3578 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3579 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3580 MAYBE_UNUSED int length;
3581
3582 switch (instr->intrinsic) {
3583 case nir_intrinsic_image_atomic_add:
3584 atomic_name = "add";
3585 break;
3586 case nir_intrinsic_image_atomic_min:
3587 atomic_name = "smin";
3588 break;
3589 case nir_intrinsic_image_atomic_max:
3590 atomic_name = "smax";
3591 break;
3592 case nir_intrinsic_image_atomic_and:
3593 atomic_name = "and";
3594 break;
3595 case nir_intrinsic_image_atomic_or:
3596 atomic_name = "or";
3597 break;
3598 case nir_intrinsic_image_atomic_xor:
3599 atomic_name = "xor";
3600 break;
3601 case nir_intrinsic_image_atomic_exchange:
3602 atomic_name = "swap";
3603 break;
3604 case nir_intrinsic_image_atomic_comp_swap:
3605 atomic_name = "cmpswap";
3606 break;
3607 default:
3608 abort();
3609 }
3610
3611 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3612 params[param_count++] = get_src(ctx, instr->src[3]);
3613 params[param_count++] = get_src(ctx, instr->src[2]);
3614
3615 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3616 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3617 true, true);
3618 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3619 ctx->ac.i32_0, ""); /* vindex */
3620 params[param_count++] = ctx->ac.i32_0; /* voffset */
3621 params[param_count++] = i1false; /* slc */
3622
3623 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3624 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3625 } else {
3626 char coords_type[8];
3627
3628 bool da = glsl_sampler_type_is_array(type) ||
3629 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3630
3631 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3632 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3633 true, true);
3634 params[param_count++] = i1false; /* r128 */
3635 params[param_count++] = da ? i1true : i1false; /* da */
3636 params[param_count++] = i1false; /* slc */
3637
3638 build_int_type_name(LLVMTypeOf(coords),
3639 coords_type, sizeof(coords_type));
3640
3641 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3642 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3643 }
3644
3645 assert(length < sizeof(intrinsic_name));
3646 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3647 }
3648
3649 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3650 const nir_intrinsic_instr *instr)
3651 {
3652 LLVMValueRef res;
3653 const nir_variable *var = instr->variables[0]->var;
3654 const struct glsl_type *type = instr->variables[0]->var->type;
3655 bool da = glsl_sampler_type_is_array(var->type) ||
3656 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3657 if(instr->variables[0]->deref.child)
3658 type = instr->variables[0]->deref.child->type;
3659
3660 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3661 return get_buffer_size(ctx,
3662 get_sampler_desc(ctx, instr->variables[0],
3663 AC_DESC_BUFFER, true, false), true);
3664
3665 struct ac_image_args args = { 0 };
3666
3667 args.da = da;
3668 args.dmask = 0xf;
3669 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3670 args.opcode = ac_image_get_resinfo;
3671 args.addr = ctx->ac.i32_0;
3672
3673 res = ac_build_image_opcode(&ctx->ac, &args);
3674
3675 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3676
3677 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3678 glsl_sampler_type_is_array(type)) {
3679 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3680 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3681 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3682 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3683 }
3684 if (ctx->ac.chip_class >= GFX9 &&
3685 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3686 glsl_sampler_type_is_array(type)) {
3687 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3688 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3689 ctx->ac.i32_1, "");
3690
3691 }
3692 return res;
3693 }
3694
3695 #define NOOP_WAITCNT 0xf7f
3696 #define LGKM_CNT 0x07f
3697 #define VM_CNT 0xf70
3698
3699 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3700 unsigned simm16)
3701 {
3702 LLVMValueRef args[1] = {
3703 LLVMConstInt(ctx->i32, simm16, false),
3704 };
3705 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3706 ctx->voidt, args, 1, 0);
3707 }
3708
3709 static void emit_barrier(struct nir_to_llvm_context *ctx)
3710 {
3711 /* SI only (thanks to a hw bug workaround):
3712 * The real barrier instruction isn’t needed, because an entire patch
3713 * always fits into a single wave.
3714 */
3715 if (ctx->options->chip_class == SI &&
3716 ctx->stage == MESA_SHADER_TESS_CTRL) {
3717 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3718 return;
3719 }
3720 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3721 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3722 }
3723
3724 static void emit_discard_if(struct ac_nir_context *ctx,
3725 const nir_intrinsic_instr *instr)
3726 {
3727 LLVMValueRef cond;
3728
3729 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3730 get_src(ctx, instr->src[0]),
3731 ctx->ac.i32_0, "");
3732
3733 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3734 LLVMConstReal(ctx->ac.f32, -1.0f),
3735 ctx->ac.f32_0, "");
3736 ac_build_kill(&ctx->ac, cond);
3737 }
3738
3739 static LLVMValueRef
3740 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3741 {
3742 LLVMValueRef result;
3743 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3744 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3745 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3746
3747 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3748 }
3749
3750 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3751 const nir_intrinsic_instr *instr)
3752 {
3753 LLVMValueRef ptr, result;
3754 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3755 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3756
3757 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3758 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3759 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3760 ptr, src, src1,
3761 LLVMAtomicOrderingSequentiallyConsistent,
3762 LLVMAtomicOrderingSequentiallyConsistent,
3763 false);
3764 } else {
3765 LLVMAtomicRMWBinOp op;
3766 switch (instr->intrinsic) {
3767 case nir_intrinsic_var_atomic_add:
3768 op = LLVMAtomicRMWBinOpAdd;
3769 break;
3770 case nir_intrinsic_var_atomic_umin:
3771 op = LLVMAtomicRMWBinOpUMin;
3772 break;
3773 case nir_intrinsic_var_atomic_umax:
3774 op = LLVMAtomicRMWBinOpUMax;
3775 break;
3776 case nir_intrinsic_var_atomic_imin:
3777 op = LLVMAtomicRMWBinOpMin;
3778 break;
3779 case nir_intrinsic_var_atomic_imax:
3780 op = LLVMAtomicRMWBinOpMax;
3781 break;
3782 case nir_intrinsic_var_atomic_and:
3783 op = LLVMAtomicRMWBinOpAnd;
3784 break;
3785 case nir_intrinsic_var_atomic_or:
3786 op = LLVMAtomicRMWBinOpOr;
3787 break;
3788 case nir_intrinsic_var_atomic_xor:
3789 op = LLVMAtomicRMWBinOpXor;
3790 break;
3791 case nir_intrinsic_var_atomic_exchange:
3792 op = LLVMAtomicRMWBinOpXchg;
3793 break;
3794 default:
3795 return NULL;
3796 }
3797
3798 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3799 LLVMAtomicOrderingSequentiallyConsistent,
3800 false);
3801 }
3802 return result;
3803 }
3804
3805 #define INTERP_CENTER 0
3806 #define INTERP_CENTROID 1
3807 #define INTERP_SAMPLE 2
3808
3809 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3810 enum glsl_interp_mode interp, unsigned location)
3811 {
3812 switch (interp) {
3813 case INTERP_MODE_FLAT:
3814 default:
3815 return NULL;
3816 case INTERP_MODE_SMOOTH:
3817 case INTERP_MODE_NONE:
3818 if (location == INTERP_CENTER)
3819 return ctx->persp_center;
3820 else if (location == INTERP_CENTROID)
3821 return ctx->persp_centroid;
3822 else if (location == INTERP_SAMPLE)
3823 return ctx->persp_sample;
3824 break;
3825 case INTERP_MODE_NOPERSPECTIVE:
3826 if (location == INTERP_CENTER)
3827 return ctx->linear_center;
3828 else if (location == INTERP_CENTROID)
3829 return ctx->linear_centroid;
3830 else if (location == INTERP_SAMPLE)
3831 return ctx->linear_sample;
3832 break;
3833 }
3834 return NULL;
3835 }
3836
3837 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3838 LLVMValueRef sample_id)
3839 {
3840 LLVMValueRef result;
3841 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3842
3843 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3844 const_array(ctx->v2f32, 64), "");
3845
3846 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3847 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3848
3849 return result;
3850 }
3851
3852 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3853 {
3854 LLVMValueRef values[2];
3855
3856 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3857 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3858 return ac_build_gather_values(&ctx->ac, values, 2);
3859 }
3860
3861 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3862 const nir_intrinsic_instr *instr)
3863 {
3864 LLVMValueRef result[2];
3865 LLVMValueRef interp_param, attr_number;
3866 unsigned location;
3867 unsigned chan;
3868 LLVMValueRef src_c0 = NULL;
3869 LLVMValueRef src_c1 = NULL;
3870 LLVMValueRef src0 = NULL;
3871 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3872 switch (instr->intrinsic) {
3873 case nir_intrinsic_interp_var_at_centroid:
3874 location = INTERP_CENTROID;
3875 break;
3876 case nir_intrinsic_interp_var_at_sample:
3877 case nir_intrinsic_interp_var_at_offset:
3878 location = INTERP_CENTER;
3879 src0 = get_src(ctx->nir, instr->src[0]);
3880 break;
3881 default:
3882 break;
3883 }
3884
3885 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3886 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3887 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3888 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3889 LLVMValueRef sample_position;
3890 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3891
3892 /* fetch sample ID */
3893 sample_position = load_sample_position(ctx, src0);
3894
3895 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3896 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3897 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3898 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3899 }
3900 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3901 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3902
3903 if (location == INTERP_CENTER) {
3904 LLVMValueRef ij_out[2];
3905 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3906
3907 /*
3908 * take the I then J parameters, and the DDX/Y for it, and
3909 * calculate the IJ inputs for the interpolator.
3910 * temp1 = ddx * offset/sample.x + I;
3911 * interp_param.I = ddy * offset/sample.y + temp1;
3912 * temp1 = ddx * offset/sample.x + J;
3913 * interp_param.J = ddy * offset/sample.y + temp1;
3914 */
3915 for (unsigned i = 0; i < 2; i++) {
3916 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3917 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3918 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3919 ddxy_out, ix_ll, "");
3920 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3921 ddxy_out, iy_ll, "");
3922 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3923 interp_param, ix_ll, "");
3924 LLVMValueRef temp1, temp2;
3925
3926 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3927 ctx->f32, "");
3928
3929 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3930 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3931
3932 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3933 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3934
3935 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3936 temp2, ctx->i32, "");
3937 }
3938 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3939
3940 }
3941
3942 for (chan = 0; chan < 2; chan++) {
3943 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3944
3945 if (interp_param) {
3946 interp_param = LLVMBuildBitCast(ctx->builder,
3947 interp_param, LLVMVectorType(ctx->f32, 2), "");
3948 LLVMValueRef i = LLVMBuildExtractElement(
3949 ctx->builder, interp_param, ctx->i32zero, "");
3950 LLVMValueRef j = LLVMBuildExtractElement(
3951 ctx->builder, interp_param, ctx->i32one, "");
3952
3953 result[chan] = ac_build_fs_interp(&ctx->ac,
3954 llvm_chan, attr_number,
3955 ctx->prim_mask, i, j);
3956 } else {
3957 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3958 LLVMConstInt(ctx->i32, 2, false),
3959 llvm_chan, attr_number,
3960 ctx->prim_mask);
3961 }
3962 }
3963 return ac_build_gather_values(&ctx->ac, result, 2);
3964 }
3965
3966 static void
3967 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3968 const nir_intrinsic_instr *instr)
3969 {
3970 LLVMValueRef gs_next_vertex;
3971 LLVMValueRef can_emit, kill;
3972 int idx;
3973
3974 assert(instr->const_index[0] == 0);
3975 /* Write vertex attribute values to GSVS ring */
3976 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3977 ctx->gs_next_vertex,
3978 "");
3979
3980 /* If this thread has already emitted the declared maximum number of
3981 * vertices, kill it: excessive vertex emissions are not supposed to
3982 * have any effect, and GS threads have no externally observable
3983 * effects other than emitting vertices.
3984 */
3985 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3986 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3987
3988 kill = LLVMBuildSelect(ctx->builder, can_emit,
3989 LLVMConstReal(ctx->f32, 1.0f),
3990 LLVMConstReal(ctx->f32, -1.0f), "");
3991 ac_build_kill(&ctx->ac, kill);
3992
3993 /* loop num outputs */
3994 idx = 0;
3995 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3996 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3997 int length = 4;
3998 int slot = idx;
3999 int slot_inc = 1;
4000
4001 if (!(ctx->output_mask & (1ull << i)))
4002 continue;
4003
4004 if (i == VARYING_SLOT_CLIP_DIST0) {
4005 /* pack clip and cull into a single set of slots */
4006 length = ctx->num_output_clips + ctx->num_output_culls;
4007 if (length > 4)
4008 slot_inc = 2;
4009 }
4010 for (unsigned j = 0; j < length; j++) {
4011 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4012 out_ptr[j], "");
4013 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4014 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4015 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
4016
4017 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4018
4019 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4020 out_val, 1,
4021 voffset, ctx->gs2vs_offset, 0,
4022 1, 1, true, true);
4023 }
4024 idx += slot_inc;
4025 }
4026
4027 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4028 ctx->i32one, "");
4029 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4030
4031 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4032 }
4033
4034 static void
4035 visit_end_primitive(struct nir_to_llvm_context *ctx,
4036 const nir_intrinsic_instr *instr)
4037 {
4038 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4039 }
4040
4041 static LLVMValueRef
4042 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4043 const nir_intrinsic_instr *instr)
4044 {
4045 LLVMValueRef coord[4] = {
4046 ctx->tes_u,
4047 ctx->tes_v,
4048 ctx->f32zero,
4049 ctx->f32zero,
4050 };
4051
4052 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4053 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
4054 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4055
4056 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4057 return LLVMBuildBitCast(ctx->builder, result,
4058 get_def_type(ctx->nir, &instr->dest.ssa), "");
4059 }
4060
4061 static void visit_intrinsic(struct ac_nir_context *ctx,
4062 nir_intrinsic_instr *instr)
4063 {
4064 LLVMValueRef result = NULL;
4065
4066 switch (instr->intrinsic) {
4067 case nir_intrinsic_load_work_group_id: {
4068 result = ctx->nctx->workgroup_ids;
4069 break;
4070 }
4071 case nir_intrinsic_load_base_vertex: {
4072 result = ctx->abi->base_vertex;
4073 break;
4074 }
4075 case nir_intrinsic_load_vertex_id_zero_base: {
4076 result = ctx->abi->vertex_id;
4077 break;
4078 }
4079 case nir_intrinsic_load_local_invocation_id: {
4080 result = ctx->nctx->local_invocation_ids;
4081 break;
4082 }
4083 case nir_intrinsic_load_base_instance:
4084 result = ctx->abi->start_instance;
4085 break;
4086 case nir_intrinsic_load_draw_id:
4087 result = ctx->abi->draw_id;
4088 break;
4089 case nir_intrinsic_load_view_index:
4090 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4091 break;
4092 case nir_intrinsic_load_invocation_id:
4093 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4094 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4095 else
4096 result = ctx->nctx->gs_invocation_id;
4097 break;
4098 case nir_intrinsic_load_primitive_id:
4099 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4100 ctx->nctx->shader_info->gs.uses_prim_id = true;
4101 result = ctx->nctx->gs_prim_id;
4102 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4103 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4104 result = ctx->nctx->tcs_patch_id;
4105 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4106 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4107 result = ctx->nctx->tes_patch_id;
4108 } else
4109 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4110 break;
4111 case nir_intrinsic_load_sample_id:
4112 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4113 break;
4114 case nir_intrinsic_load_sample_pos:
4115 result = load_sample_pos(ctx);
4116 break;
4117 case nir_intrinsic_load_sample_mask_in:
4118 result = ctx->abi->sample_coverage;
4119 break;
4120 case nir_intrinsic_load_frag_coord: {
4121 LLVMValueRef values[4] = {
4122 ctx->abi->frag_pos[0],
4123 ctx->abi->frag_pos[1],
4124 ctx->abi->frag_pos[2],
4125 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4126 };
4127 result = ac_build_gather_values(&ctx->ac, values, 4);
4128 break;
4129 }
4130 case nir_intrinsic_load_front_face:
4131 result = ctx->abi->front_face;
4132 break;
4133 case nir_intrinsic_load_instance_id:
4134 result = ctx->abi->instance_id;
4135 break;
4136 case nir_intrinsic_load_num_work_groups:
4137 result = ctx->nctx->num_work_groups;
4138 break;
4139 case nir_intrinsic_load_local_invocation_index:
4140 result = visit_load_local_invocation_index(ctx->nctx);
4141 break;
4142 case nir_intrinsic_load_push_constant:
4143 result = visit_load_push_constant(ctx->nctx, instr);
4144 break;
4145 case nir_intrinsic_vulkan_resource_index:
4146 result = visit_vulkan_resource_index(ctx->nctx, instr);
4147 break;
4148 case nir_intrinsic_store_ssbo:
4149 visit_store_ssbo(ctx, instr);
4150 break;
4151 case nir_intrinsic_load_ssbo:
4152 result = visit_load_buffer(ctx, instr);
4153 break;
4154 case nir_intrinsic_ssbo_atomic_add:
4155 case nir_intrinsic_ssbo_atomic_imin:
4156 case nir_intrinsic_ssbo_atomic_umin:
4157 case nir_intrinsic_ssbo_atomic_imax:
4158 case nir_intrinsic_ssbo_atomic_umax:
4159 case nir_intrinsic_ssbo_atomic_and:
4160 case nir_intrinsic_ssbo_atomic_or:
4161 case nir_intrinsic_ssbo_atomic_xor:
4162 case nir_intrinsic_ssbo_atomic_exchange:
4163 case nir_intrinsic_ssbo_atomic_comp_swap:
4164 result = visit_atomic_ssbo(ctx, instr);
4165 break;
4166 case nir_intrinsic_load_ubo:
4167 result = visit_load_ubo_buffer(ctx, instr);
4168 break;
4169 case nir_intrinsic_get_buffer_size:
4170 result = visit_get_buffer_size(ctx, instr);
4171 break;
4172 case nir_intrinsic_load_var:
4173 result = visit_load_var(ctx, instr);
4174 break;
4175 case nir_intrinsic_store_var:
4176 visit_store_var(ctx, instr);
4177 break;
4178 case nir_intrinsic_image_load:
4179 result = visit_image_load(ctx, instr);
4180 break;
4181 case nir_intrinsic_image_store:
4182 visit_image_store(ctx, instr);
4183 break;
4184 case nir_intrinsic_image_atomic_add:
4185 case nir_intrinsic_image_atomic_min:
4186 case nir_intrinsic_image_atomic_max:
4187 case nir_intrinsic_image_atomic_and:
4188 case nir_intrinsic_image_atomic_or:
4189 case nir_intrinsic_image_atomic_xor:
4190 case nir_intrinsic_image_atomic_exchange:
4191 case nir_intrinsic_image_atomic_comp_swap:
4192 result = visit_image_atomic(ctx, instr);
4193 break;
4194 case nir_intrinsic_image_size:
4195 result = visit_image_size(ctx, instr);
4196 break;
4197 case nir_intrinsic_discard:
4198 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4199 LLVMVoidTypeInContext(ctx->ac.context),
4200 NULL, 0, AC_FUNC_ATTR_LEGACY);
4201 break;
4202 case nir_intrinsic_discard_if:
4203 emit_discard_if(ctx, instr);
4204 break;
4205 case nir_intrinsic_memory_barrier:
4206 emit_waitcnt(ctx->nctx, VM_CNT);
4207 break;
4208 case nir_intrinsic_barrier:
4209 emit_barrier(ctx->nctx);
4210 break;
4211 case nir_intrinsic_var_atomic_add:
4212 case nir_intrinsic_var_atomic_imin:
4213 case nir_intrinsic_var_atomic_umin:
4214 case nir_intrinsic_var_atomic_imax:
4215 case nir_intrinsic_var_atomic_umax:
4216 case nir_intrinsic_var_atomic_and:
4217 case nir_intrinsic_var_atomic_or:
4218 case nir_intrinsic_var_atomic_xor:
4219 case nir_intrinsic_var_atomic_exchange:
4220 case nir_intrinsic_var_atomic_comp_swap:
4221 result = visit_var_atomic(ctx->nctx, instr);
4222 break;
4223 case nir_intrinsic_interp_var_at_centroid:
4224 case nir_intrinsic_interp_var_at_sample:
4225 case nir_intrinsic_interp_var_at_offset:
4226 result = visit_interp(ctx->nctx, instr);
4227 break;
4228 case nir_intrinsic_emit_vertex:
4229 visit_emit_vertex(ctx->nctx, instr);
4230 break;
4231 case nir_intrinsic_end_primitive:
4232 visit_end_primitive(ctx->nctx, instr);
4233 break;
4234 case nir_intrinsic_load_tess_coord:
4235 result = visit_load_tess_coord(ctx->nctx, instr);
4236 break;
4237 case nir_intrinsic_load_patch_vertices_in:
4238 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4239 break;
4240 default:
4241 fprintf(stderr, "Unknown intrinsic: ");
4242 nir_print_instr(&instr->instr, stderr);
4243 fprintf(stderr, "\n");
4244 break;
4245 }
4246 if (result) {
4247 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4248 }
4249 }
4250
4251 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4252 LLVMValueRef buffer, bool write)
4253 {
4254 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4255
4256 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4257 ctx->shader_info->fs.writes_memory = true;
4258
4259 return buffer;
4260 }
4261
4262 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4263 unsigned descriptor_set,
4264 unsigned base_index,
4265 unsigned constant_index,
4266 LLVMValueRef index,
4267 enum ac_descriptor_type desc_type,
4268 bool image, bool write)
4269 {
4270 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4271 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4272 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4273 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4274 unsigned offset = binding->offset;
4275 unsigned stride = binding->size;
4276 unsigned type_size;
4277 LLVMBuilderRef builder = ctx->builder;
4278 LLVMTypeRef type;
4279
4280 assert(base_index < layout->binding_count);
4281
4282 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4283 ctx->shader_info->fs.writes_memory = true;
4284
4285 switch (desc_type) {
4286 case AC_DESC_IMAGE:
4287 type = ctx->v8i32;
4288 type_size = 32;
4289 break;
4290 case AC_DESC_FMASK:
4291 type = ctx->v8i32;
4292 offset += 32;
4293 type_size = 32;
4294 break;
4295 case AC_DESC_SAMPLER:
4296 type = ctx->v4i32;
4297 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4298 offset += 64;
4299
4300 type_size = 16;
4301 break;
4302 case AC_DESC_BUFFER:
4303 type = ctx->v4i32;
4304 type_size = 16;
4305 break;
4306 default:
4307 unreachable("invalid desc_type\n");
4308 }
4309
4310 offset += constant_index * stride;
4311
4312 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4313 (!index || binding->immutable_samplers_equal)) {
4314 if (binding->immutable_samplers_equal)
4315 constant_index = 0;
4316
4317 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4318
4319 LLVMValueRef constants[] = {
4320 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4321 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4322 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4323 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4324 };
4325 return ac_build_gather_values(&ctx->ac, constants, 4);
4326 }
4327
4328 assert(stride % type_size == 0);
4329
4330 if (!index)
4331 index = ctx->i32zero;
4332
4333 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4334
4335 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4336 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4337
4338 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4339 }
4340
4341 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4342 const nir_deref_var *deref,
4343 enum ac_descriptor_type desc_type,
4344 bool image, bool write)
4345 {
4346 LLVMValueRef index = NULL;
4347 unsigned constant_index = 0;
4348 const nir_deref *tail = &deref->deref;
4349
4350 while (tail->child) {
4351 const nir_deref_array *child = nir_deref_as_array(tail->child);
4352 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4353
4354 if (!array_size)
4355 array_size = 1;
4356
4357 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4358
4359 if (child->deref_array_type == nir_deref_array_type_indirect) {
4360 LLVMValueRef indirect = get_src(ctx, child->indirect);
4361
4362 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4363 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4364
4365 if (!index)
4366 index = indirect;
4367 else
4368 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4369 }
4370
4371 constant_index += child->base_offset * array_size;
4372
4373 tail = &child->deref;
4374 }
4375
4376 return ctx->abi->load_sampler_desc(ctx->abi,
4377 deref->var->data.descriptor_set,
4378 deref->var->data.binding,
4379 constant_index, index,
4380 desc_type, image, write);
4381 }
4382
4383 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4384 struct ac_image_args *args,
4385 const nir_tex_instr *instr,
4386 nir_texop op,
4387 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4388 LLVMValueRef *param, unsigned count,
4389 unsigned dmask)
4390 {
4391 unsigned is_rect = 0;
4392 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4393
4394 if (op == nir_texop_lod)
4395 da = false;
4396 /* Pad to power of two vector */
4397 while (count < util_next_power_of_two(count))
4398 param[count++] = LLVMGetUndef(ctx->i32);
4399
4400 if (count > 1)
4401 args->addr = ac_build_gather_values(ctx, param, count);
4402 else
4403 args->addr = param[0];
4404
4405 args->resource = res_ptr;
4406 args->sampler = samp_ptr;
4407
4408 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4409 args->addr = param[0];
4410 return;
4411 }
4412
4413 args->dmask = dmask;
4414 args->unorm = is_rect;
4415 args->da = da;
4416 }
4417
4418 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4419 *
4420 * SI-CI:
4421 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4422 * filtering manually. The driver sets img7 to a mask clearing
4423 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4424 * s_and_b32 samp0, samp0, img7
4425 *
4426 * VI:
4427 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4428 */
4429 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4430 LLVMValueRef res, LLVMValueRef samp)
4431 {
4432 LLVMBuilderRef builder = ctx->ac.builder;
4433 LLVMValueRef img7, samp0;
4434
4435 if (ctx->ac.chip_class >= VI)
4436 return samp;
4437
4438 img7 = LLVMBuildExtractElement(builder, res,
4439 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4440 samp0 = LLVMBuildExtractElement(builder, samp,
4441 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4442 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4443 return LLVMBuildInsertElement(builder, samp, samp0,
4444 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4445 }
4446
4447 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4448 nir_tex_instr *instr,
4449 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4450 LLVMValueRef *fmask_ptr)
4451 {
4452 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4453 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4454 else
4455 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4456 if (samp_ptr) {
4457 if (instr->sampler)
4458 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4459 else
4460 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4461 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4462 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4463 }
4464 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4465 instr->op == nir_texop_samples_identical))
4466 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4467 }
4468
4469 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4470 LLVMValueRef coord)
4471 {
4472 coord = ac_to_float(ctx, coord);
4473 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4474 coord = ac_to_integer(ctx, coord);
4475 return coord;
4476 }
4477
4478 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4479 {
4480 LLVMValueRef result = NULL;
4481 struct ac_image_args args = { 0 };
4482 unsigned dmask = 0xf;
4483 LLVMValueRef address[16];
4484 LLVMValueRef coords[5];
4485 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4486 LLVMValueRef bias = NULL, offsets = NULL;
4487 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4488 LLVMValueRef ddx = NULL, ddy = NULL;
4489 LLVMValueRef derivs[6];
4490 unsigned chan, count = 0;
4491 unsigned const_src = 0, num_deriv_comp = 0;
4492 bool lod_is_zero = false;
4493
4494 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4495
4496 for (unsigned i = 0; i < instr->num_srcs; i++) {
4497 switch (instr->src[i].src_type) {
4498 case nir_tex_src_coord:
4499 coord = get_src(ctx, instr->src[i].src);
4500 break;
4501 case nir_tex_src_projector:
4502 break;
4503 case nir_tex_src_comparator:
4504 comparator = get_src(ctx, instr->src[i].src);
4505 break;
4506 case nir_tex_src_offset:
4507 offsets = get_src(ctx, instr->src[i].src);
4508 const_src = i;
4509 break;
4510 case nir_tex_src_bias:
4511 bias = get_src(ctx, instr->src[i].src);
4512 break;
4513 case nir_tex_src_lod: {
4514 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4515
4516 if (val && val->i32[0] == 0)
4517 lod_is_zero = true;
4518 lod = get_src(ctx, instr->src[i].src);
4519 break;
4520 }
4521 case nir_tex_src_ms_index:
4522 sample_index = get_src(ctx, instr->src[i].src);
4523 break;
4524 case nir_tex_src_ms_mcs:
4525 break;
4526 case nir_tex_src_ddx:
4527 ddx = get_src(ctx, instr->src[i].src);
4528 num_deriv_comp = instr->src[i].src.ssa->num_components;
4529 break;
4530 case nir_tex_src_ddy:
4531 ddy = get_src(ctx, instr->src[i].src);
4532 break;
4533 case nir_tex_src_texture_offset:
4534 case nir_tex_src_sampler_offset:
4535 case nir_tex_src_plane:
4536 default:
4537 break;
4538 }
4539 }
4540
4541 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4542 result = get_buffer_size(ctx, res_ptr, true);
4543 goto write_result;
4544 }
4545
4546 if (instr->op == nir_texop_texture_samples) {
4547 LLVMValueRef res, samples, is_msaa;
4548 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4549 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4550 LLVMConstInt(ctx->ac.i32, 3, false), "");
4551 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4552 LLVMConstInt(ctx->ac.i32, 28, false), "");
4553 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4554 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4555 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4556 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4557
4558 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4559 LLVMConstInt(ctx->ac.i32, 16, false), "");
4560 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4561 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4562 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4563 samples, "");
4564 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4565 ctx->ac.i32_1, "");
4566 result = samples;
4567 goto write_result;
4568 }
4569
4570 if (coord)
4571 for (chan = 0; chan < instr->coord_components; chan++)
4572 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4573
4574 if (offsets && instr->op != nir_texop_txf) {
4575 LLVMValueRef offset[3], pack;
4576 for (chan = 0; chan < 3; ++chan)
4577 offset[chan] = ctx->ac.i32_0;
4578
4579 args.offset = true;
4580 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4581 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4582 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4583 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4584 if (chan)
4585 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4586 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4587 }
4588 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4589 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4590 address[count++] = pack;
4591
4592 }
4593 /* pack LOD bias value */
4594 if (instr->op == nir_texop_txb && bias) {
4595 address[count++] = bias;
4596 }
4597
4598 /* Pack depth comparison value */
4599 if (instr->is_shadow && comparator) {
4600 LLVMValueRef z = ac_to_float(&ctx->ac,
4601 llvm_extract_elem(&ctx->ac, comparator, 0));
4602
4603 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4604 * so the depth comparison value isn't clamped for Z16 and
4605 * Z24 anymore. Do it manually here.
4606 *
4607 * It's unnecessary if the original texture format was
4608 * Z32_FLOAT, but we don't know that here.
4609 */
4610 if (ctx->ac.chip_class == VI)
4611 z = ac_build_clamp(&ctx->ac, z);
4612
4613 address[count++] = z;
4614 }
4615
4616 /* pack derivatives */
4617 if (ddx || ddy) {
4618 int num_src_deriv_channels, num_dest_deriv_channels;
4619 switch (instr->sampler_dim) {
4620 case GLSL_SAMPLER_DIM_3D:
4621 case GLSL_SAMPLER_DIM_CUBE:
4622 num_deriv_comp = 3;
4623 num_src_deriv_channels = 3;
4624 num_dest_deriv_channels = 3;
4625 break;
4626 case GLSL_SAMPLER_DIM_2D:
4627 default:
4628 num_src_deriv_channels = 2;
4629 num_dest_deriv_channels = 2;
4630 num_deriv_comp = 2;
4631 break;
4632 case GLSL_SAMPLER_DIM_1D:
4633 num_src_deriv_channels = 1;
4634 if (ctx->ac.chip_class >= GFX9) {
4635 num_dest_deriv_channels = 2;
4636 num_deriv_comp = 2;
4637 } else {
4638 num_dest_deriv_channels = 1;
4639 num_deriv_comp = 1;
4640 }
4641 break;
4642 }
4643
4644 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4645 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4646 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4647 }
4648 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4649 derivs[i] = ctx->ac.f32_0;
4650 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4651 }
4652 }
4653
4654 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4655 for (chan = 0; chan < instr->coord_components; chan++)
4656 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4657 if (instr->coord_components == 3)
4658 coords[3] = LLVMGetUndef(ctx->ac.f32);
4659 ac_prepare_cube_coords(&ctx->ac,
4660 instr->op == nir_texop_txd, instr->is_array,
4661 instr->op == nir_texop_lod, coords, derivs);
4662 if (num_deriv_comp)
4663 num_deriv_comp--;
4664 }
4665
4666 if (ddx || ddy) {
4667 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4668 address[count++] = derivs[i];
4669 }
4670
4671 /* Pack texture coordinates */
4672 if (coord) {
4673 address[count++] = coords[0];
4674 if (instr->coord_components > 1) {
4675 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4676 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4677 }
4678 address[count++] = coords[1];
4679 }
4680 if (instr->coord_components > 2) {
4681 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4682 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4683 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4684 instr->op != nir_texop_txf) {
4685 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4686 }
4687 address[count++] = coords[2];
4688 }
4689
4690 if (ctx->ac.chip_class >= GFX9) {
4691 LLVMValueRef filler;
4692 if (instr->op == nir_texop_txf)
4693 filler = ctx->ac.i32_0;
4694 else
4695 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4696
4697 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4698 if (instr->is_array) {
4699 address[count] = address[count - 1];
4700 address[count - 1] = filler;
4701 count++;
4702 } else
4703 address[count++] = filler;
4704 }
4705 }
4706 }
4707
4708 /* Pack LOD */
4709 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4710 instr->op == nir_texop_txf)) {
4711 address[count++] = lod;
4712 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4713 address[count++] = sample_index;
4714 } else if(instr->op == nir_texop_txs) {
4715 count = 0;
4716 if (lod)
4717 address[count++] = lod;
4718 else
4719 address[count++] = ctx->ac.i32_0;
4720 }
4721
4722 for (chan = 0; chan < count; chan++) {
4723 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4724 address[chan], ctx->ac.i32, "");
4725 }
4726
4727 if (instr->op == nir_texop_samples_identical) {
4728 LLVMValueRef txf_address[4];
4729 struct ac_image_args txf_args = { 0 };
4730 unsigned txf_count = count;
4731 memcpy(txf_address, address, sizeof(txf_address));
4732
4733 if (!instr->is_array)
4734 txf_address[2] = ctx->ac.i32_0;
4735 txf_address[3] = ctx->ac.i32_0;
4736
4737 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4738 fmask_ptr, NULL,
4739 txf_address, txf_count, 0xf);
4740
4741 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4742
4743 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4744 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4745 goto write_result;
4746 }
4747
4748 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4749 instr->op != nir_texop_txs) {
4750 unsigned sample_chan = instr->is_array ? 3 : 2;
4751 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4752 address[0],
4753 address[1],
4754 instr->is_array ? address[2] : NULL,
4755 address[sample_chan],
4756 fmask_ptr);
4757 }
4758
4759 if (offsets && instr->op == nir_texop_txf) {
4760 nir_const_value *const_offset =
4761 nir_src_as_const_value(instr->src[const_src].src);
4762 int num_offsets = instr->src[const_src].src.ssa->num_components;
4763 assert(const_offset);
4764 num_offsets = MIN2(num_offsets, instr->coord_components);
4765 if (num_offsets > 2)
4766 address[2] = LLVMBuildAdd(ctx->ac.builder,
4767 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4768 if (num_offsets > 1)
4769 address[1] = LLVMBuildAdd(ctx->ac.builder,
4770 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4771 address[0] = LLVMBuildAdd(ctx->ac.builder,
4772 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4773
4774 }
4775
4776 /* TODO TG4 support */
4777 if (instr->op == nir_texop_tg4) {
4778 if (instr->is_shadow)
4779 dmask = 1;
4780 else
4781 dmask = 1 << instr->component;
4782 }
4783 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4784 res_ptr, samp_ptr, address, count, dmask);
4785
4786 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4787
4788 if (instr->op == nir_texop_query_levels)
4789 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4790 else if (instr->is_shadow && instr->is_new_style_shadow &&
4791 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4792 instr->op != nir_texop_tg4)
4793 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4794 else if (instr->op == nir_texop_txs &&
4795 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4796 instr->is_array) {
4797 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4798 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4799 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4800 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4801 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4802 } else if (ctx->ac.chip_class >= GFX9 &&
4803 instr->op == nir_texop_txs &&
4804 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4805 instr->is_array) {
4806 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4807 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4808 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4809 ctx->ac.i32_1, "");
4810 } else if (instr->dest.ssa.num_components != 4)
4811 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4812
4813 write_result:
4814 if (result) {
4815 assert(instr->dest.is_ssa);
4816 result = ac_to_integer(&ctx->ac, result);
4817 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4818 }
4819 }
4820
4821
4822 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4823 {
4824 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4825 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4826
4827 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4828 _mesa_hash_table_insert(ctx->phis, instr, result);
4829 }
4830
4831 static void visit_post_phi(struct ac_nir_context *ctx,
4832 nir_phi_instr *instr,
4833 LLVMValueRef llvm_phi)
4834 {
4835 nir_foreach_phi_src(src, instr) {
4836 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4837 LLVMValueRef llvm_src = get_src(ctx, src->src);
4838
4839 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4840 }
4841 }
4842
4843 static void phi_post_pass(struct ac_nir_context *ctx)
4844 {
4845 struct hash_entry *entry;
4846 hash_table_foreach(ctx->phis, entry) {
4847 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4848 (LLVMValueRef)entry->data);
4849 }
4850 }
4851
4852
4853 static void visit_ssa_undef(struct ac_nir_context *ctx,
4854 const nir_ssa_undef_instr *instr)
4855 {
4856 unsigned num_components = instr->def.num_components;
4857 LLVMValueRef undef;
4858
4859 if (num_components == 1)
4860 undef = LLVMGetUndef(ctx->ac.i32);
4861 else {
4862 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4863 }
4864 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4865 }
4866
4867 static void visit_jump(struct ac_nir_context *ctx,
4868 const nir_jump_instr *instr)
4869 {
4870 switch (instr->type) {
4871 case nir_jump_break:
4872 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4873 LLVMClearInsertionPosition(ctx->ac.builder);
4874 break;
4875 case nir_jump_continue:
4876 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4877 LLVMClearInsertionPosition(ctx->ac.builder);
4878 break;
4879 default:
4880 fprintf(stderr, "Unknown NIR jump instr: ");
4881 nir_print_instr(&instr->instr, stderr);
4882 fprintf(stderr, "\n");
4883 abort();
4884 }
4885 }
4886
4887 static void visit_cf_list(struct ac_nir_context *ctx,
4888 struct exec_list *list);
4889
4890 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4891 {
4892 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4893 nir_foreach_instr(instr, block)
4894 {
4895 switch (instr->type) {
4896 case nir_instr_type_alu:
4897 visit_alu(ctx, nir_instr_as_alu(instr));
4898 break;
4899 case nir_instr_type_load_const:
4900 visit_load_const(ctx, nir_instr_as_load_const(instr));
4901 break;
4902 case nir_instr_type_intrinsic:
4903 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4904 break;
4905 case nir_instr_type_tex:
4906 visit_tex(ctx, nir_instr_as_tex(instr));
4907 break;
4908 case nir_instr_type_phi:
4909 visit_phi(ctx, nir_instr_as_phi(instr));
4910 break;
4911 case nir_instr_type_ssa_undef:
4912 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4913 break;
4914 case nir_instr_type_jump:
4915 visit_jump(ctx, nir_instr_as_jump(instr));
4916 break;
4917 default:
4918 fprintf(stderr, "Unknown NIR instr type: ");
4919 nir_print_instr(instr, stderr);
4920 fprintf(stderr, "\n");
4921 abort();
4922 }
4923 }
4924
4925 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4926 }
4927
4928 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4929 {
4930 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4931
4932 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4933 LLVMBasicBlockRef merge_block =
4934 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4935 LLVMBasicBlockRef if_block =
4936 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4937 LLVMBasicBlockRef else_block = merge_block;
4938 if (!exec_list_is_empty(&if_stmt->else_list))
4939 else_block = LLVMAppendBasicBlockInContext(
4940 ctx->ac.context, fn, "");
4941
4942 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4943 LLVMConstInt(ctx->ac.i32, 0, false), "");
4944 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4945
4946 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4947 visit_cf_list(ctx, &if_stmt->then_list);
4948 if (LLVMGetInsertBlock(ctx->ac.builder))
4949 LLVMBuildBr(ctx->ac.builder, merge_block);
4950
4951 if (!exec_list_is_empty(&if_stmt->else_list)) {
4952 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4953 visit_cf_list(ctx, &if_stmt->else_list);
4954 if (LLVMGetInsertBlock(ctx->ac.builder))
4955 LLVMBuildBr(ctx->ac.builder, merge_block);
4956 }
4957
4958 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4959 }
4960
4961 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4962 {
4963 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4964 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4965 LLVMBasicBlockRef break_parent = ctx->break_block;
4966
4967 ctx->continue_block =
4968 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4969 ctx->break_block =
4970 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4971
4972 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4973 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4974 visit_cf_list(ctx, &loop->body);
4975
4976 if (LLVMGetInsertBlock(ctx->ac.builder))
4977 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4978 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4979
4980 ctx->continue_block = continue_parent;
4981 ctx->break_block = break_parent;
4982 }
4983
4984 static void visit_cf_list(struct ac_nir_context *ctx,
4985 struct exec_list *list)
4986 {
4987 foreach_list_typed(nir_cf_node, node, node, list)
4988 {
4989 switch (node->type) {
4990 case nir_cf_node_block:
4991 visit_block(ctx, nir_cf_node_as_block(node));
4992 break;
4993
4994 case nir_cf_node_if:
4995 visit_if(ctx, nir_cf_node_as_if(node));
4996 break;
4997
4998 case nir_cf_node_loop:
4999 visit_loop(ctx, nir_cf_node_as_loop(node));
5000 break;
5001
5002 default:
5003 assert(0);
5004 }
5005 }
5006 }
5007
5008 static void
5009 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5010 struct nir_variable *variable)
5011 {
5012 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5013 LLVMValueRef t_offset;
5014 LLVMValueRef t_list;
5015 LLVMValueRef input;
5016 LLVMValueRef buffer_index;
5017 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5018 int idx = variable->data.location;
5019 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5020
5021 variable->data.driver_location = idx * 4;
5022
5023 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5024 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5025 ctx->abi.start_instance, "");
5026 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5027 ctx->shader_info->vs.vgpr_comp_cnt);
5028 } else
5029 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5030 ctx->abi.base_vertex, "");
5031
5032 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5033 t_offset = LLVMConstInt(ctx->i32, index + i, false);
5034
5035 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5036
5037 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5038 buffer_index,
5039 LLVMConstInt(ctx->i32, 0, false),
5040 true);
5041
5042 for (unsigned chan = 0; chan < 4; chan++) {
5043 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5044 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5045 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5046 input, llvm_chan, ""));
5047 }
5048 }
5049 }
5050
5051 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5052 unsigned attr,
5053 LLVMValueRef interp_param,
5054 LLVMValueRef prim_mask,
5055 LLVMValueRef result[4])
5056 {
5057 LLVMValueRef attr_number;
5058 unsigned chan;
5059 LLVMValueRef i, j;
5060 bool interp = interp_param != NULL;
5061
5062 attr_number = LLVMConstInt(ctx->i32, attr, false);
5063
5064 /* fs.constant returns the param from the middle vertex, so it's not
5065 * really useful for flat shading. It's meant to be used for custom
5066 * interpolation (but the intrinsic can't fetch from the other two
5067 * vertices).
5068 *
5069 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5070 * to do the right thing. The only reason we use fs.constant is that
5071 * fs.interp cannot be used on integers, because they can be equal
5072 * to NaN.
5073 */
5074 if (interp) {
5075 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5076 LLVMVectorType(ctx->f32, 2), "");
5077
5078 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5079 ctx->i32zero, "");
5080 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5081 ctx->i32one, "");
5082 }
5083
5084 for (chan = 0; chan < 4; chan++) {
5085 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5086
5087 if (interp) {
5088 result[chan] = ac_build_fs_interp(&ctx->ac,
5089 llvm_chan,
5090 attr_number,
5091 prim_mask, i, j);
5092 } else {
5093 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5094 LLVMConstInt(ctx->i32, 2, false),
5095 llvm_chan,
5096 attr_number,
5097 prim_mask);
5098 }
5099 }
5100 }
5101
5102 static void
5103 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5104 struct nir_variable *variable)
5105 {
5106 int idx = variable->data.location;
5107 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5108 LLVMValueRef interp;
5109
5110 variable->data.driver_location = idx * 4;
5111 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5112
5113 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5114 unsigned interp_type;
5115 if (variable->data.sample) {
5116 interp_type = INTERP_SAMPLE;
5117 ctx->shader_info->info.ps.force_persample = true;
5118 } else if (variable->data.centroid)
5119 interp_type = INTERP_CENTROID;
5120 else
5121 interp_type = INTERP_CENTER;
5122
5123 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5124 } else
5125 interp = NULL;
5126
5127 for (unsigned i = 0; i < attrib_count; ++i)
5128 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5129
5130 }
5131
5132 static void
5133 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5134 struct nir_shader *nir) {
5135 nir_foreach_variable(variable, &nir->inputs)
5136 handle_vs_input_decl(ctx, variable);
5137 }
5138
5139 static void
5140 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5141 struct nir_shader *nir)
5142 {
5143 if (!ctx->options->key.fs.multisample)
5144 return;
5145
5146 bool uses_center = false;
5147 bool uses_centroid = false;
5148 nir_foreach_variable(variable, &nir->inputs) {
5149 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5150 variable->data.sample)
5151 continue;
5152
5153 if (variable->data.centroid)
5154 uses_centroid = true;
5155 else
5156 uses_center = true;
5157 }
5158
5159 if (uses_center && uses_centroid) {
5160 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5161 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5162 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5163 }
5164 }
5165
5166 static void
5167 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5168 struct nir_shader *nir)
5169 {
5170 prepare_interp_optimize(ctx, nir);
5171
5172 nir_foreach_variable(variable, &nir->inputs)
5173 handle_fs_input_decl(ctx, variable);
5174
5175 unsigned index = 0;
5176
5177 if (ctx->shader_info->info.ps.uses_input_attachments ||
5178 ctx->shader_info->info.needs_multiview_view_index)
5179 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5180
5181 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5182 LLVMValueRef interp_param;
5183 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5184
5185 if (!(ctx->input_mask & (1ull << i)))
5186 continue;
5187
5188 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5189 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5190 interp_param = *inputs;
5191 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5192 inputs);
5193
5194 if (!interp_param)
5195 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5196 ++index;
5197 } else if (i == VARYING_SLOT_POS) {
5198 for(int i = 0; i < 3; ++i)
5199 inputs[i] = ctx->abi.frag_pos[i];
5200
5201 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5202 ctx->abi.frag_pos[3]);
5203 }
5204 }
5205 ctx->shader_info->fs.num_interp = index;
5206 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5207 ctx->shader_info->fs.has_pcoord = true;
5208 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5209 ctx->shader_info->fs.prim_id_input = true;
5210 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5211 ctx->shader_info->fs.layer_input = true;
5212 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5213
5214 if (ctx->shader_info->info.needs_multiview_view_index)
5215 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5216 }
5217
5218 static LLVMValueRef
5219 ac_build_alloca(struct ac_llvm_context *ac,
5220 LLVMTypeRef type,
5221 const char *name)
5222 {
5223 LLVMBuilderRef builder = ac->builder;
5224 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5225 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5226 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5227 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5228 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5229 LLVMValueRef res;
5230
5231 if (first_instr) {
5232 LLVMPositionBuilderBefore(first_builder, first_instr);
5233 } else {
5234 LLVMPositionBuilderAtEnd(first_builder, first_block);
5235 }
5236
5237 res = LLVMBuildAlloca(first_builder, type, name);
5238 LLVMBuildStore(builder, LLVMConstNull(type), res);
5239
5240 LLVMDisposeBuilder(first_builder);
5241
5242 return res;
5243 }
5244
5245 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5246 LLVMTypeRef type,
5247 const char *name)
5248 {
5249 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5250 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5251 return ptr;
5252 }
5253
5254 static void
5255 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5256 struct nir_variable *variable,
5257 struct nir_shader *shader,
5258 gl_shader_stage stage)
5259 {
5260 int idx = variable->data.location + variable->data.index;
5261 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5262 uint64_t mask_attribs;
5263
5264 variable->data.driver_location = idx * 4;
5265
5266 /* tess ctrl has it's own load/store paths for outputs */
5267 if (stage == MESA_SHADER_TESS_CTRL)
5268 return;
5269
5270 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5271 if (stage == MESA_SHADER_VERTEX ||
5272 stage == MESA_SHADER_TESS_EVAL ||
5273 stage == MESA_SHADER_GEOMETRY) {
5274 if (idx == VARYING_SLOT_CLIP_DIST0) {
5275 int length = shader->info.clip_distance_array_size +
5276 shader->info.cull_distance_array_size;
5277 if (stage == MESA_SHADER_VERTEX) {
5278 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5279 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5280 }
5281 if (stage == MESA_SHADER_TESS_EVAL) {
5282 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5283 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5284 }
5285
5286 if (length > 4)
5287 attrib_count = 2;
5288 else
5289 attrib_count = 1;
5290 mask_attribs = 1ull << idx;
5291 }
5292 }
5293
5294 ctx->output_mask |= mask_attribs;
5295 }
5296
5297 static void
5298 handle_shader_output_decl(struct ac_nir_context *ctx,
5299 struct nir_shader *nir,
5300 struct nir_variable *variable)
5301 {
5302 unsigned output_loc = variable->data.driver_location / 4;
5303 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5304
5305 /* tess ctrl has it's own load/store paths for outputs */
5306 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5307 return;
5308
5309 if (ctx->stage == MESA_SHADER_VERTEX ||
5310 ctx->stage == MESA_SHADER_TESS_EVAL ||
5311 ctx->stage == MESA_SHADER_GEOMETRY) {
5312 int idx = variable->data.location + variable->data.index;
5313 if (idx == VARYING_SLOT_CLIP_DIST0) {
5314 int length = nir->info.clip_distance_array_size +
5315 nir->info.cull_distance_array_size;
5316
5317 if (length > 4)
5318 attrib_count = 2;
5319 else
5320 attrib_count = 1;
5321 }
5322 }
5323
5324 for (unsigned i = 0; i < attrib_count; ++i) {
5325 for (unsigned chan = 0; chan < 4; chan++) {
5326 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5327 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5328 }
5329 }
5330 }
5331
5332 static LLVMTypeRef
5333 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5334 enum glsl_base_type type)
5335 {
5336 switch (type) {
5337 case GLSL_TYPE_INT:
5338 case GLSL_TYPE_UINT:
5339 case GLSL_TYPE_BOOL:
5340 case GLSL_TYPE_SUBROUTINE:
5341 return ctx->i32;
5342 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5343 return ctx->f32;
5344 case GLSL_TYPE_INT64:
5345 case GLSL_TYPE_UINT64:
5346 return ctx->i64;
5347 case GLSL_TYPE_DOUBLE:
5348 return ctx->f64;
5349 default:
5350 unreachable("unknown GLSL type");
5351 }
5352 }
5353
5354 static LLVMTypeRef
5355 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5356 const struct glsl_type *type)
5357 {
5358 if (glsl_type_is_scalar(type)) {
5359 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5360 }
5361
5362 if (glsl_type_is_vector(type)) {
5363 return LLVMVectorType(
5364 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5365 glsl_get_vector_elements(type));
5366 }
5367
5368 if (glsl_type_is_matrix(type)) {
5369 return LLVMArrayType(
5370 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5371 glsl_get_matrix_columns(type));
5372 }
5373
5374 if (glsl_type_is_array(type)) {
5375 return LLVMArrayType(
5376 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5377 glsl_get_length(type));
5378 }
5379
5380 assert(glsl_type_is_struct(type));
5381
5382 LLVMTypeRef member_types[glsl_get_length(type)];
5383
5384 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5385 member_types[i] =
5386 glsl_to_llvm_type(ctx,
5387 glsl_get_struct_field(type, i));
5388 }
5389
5390 return LLVMStructTypeInContext(ctx->context, member_types,
5391 glsl_get_length(type), false);
5392 }
5393
5394 static void
5395 setup_locals(struct ac_nir_context *ctx,
5396 struct nir_function *func)
5397 {
5398 int i, j;
5399 ctx->num_locals = 0;
5400 nir_foreach_variable(variable, &func->impl->locals) {
5401 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5402 variable->data.driver_location = ctx->num_locals * 4;
5403 ctx->num_locals += attrib_count;
5404 }
5405 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5406 if (!ctx->locals)
5407 return;
5408
5409 for (i = 0; i < ctx->num_locals; i++) {
5410 for (j = 0; j < 4; j++) {
5411 ctx->locals[i * 4 + j] =
5412 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5413 }
5414 }
5415 }
5416
5417 static void
5418 setup_shared(struct ac_nir_context *ctx,
5419 struct nir_shader *nir)
5420 {
5421 nir_foreach_variable(variable, &nir->shared) {
5422 LLVMValueRef shared =
5423 LLVMAddGlobalInAddressSpace(
5424 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5425 variable->name ? variable->name : "",
5426 LOCAL_ADDR_SPACE);
5427 _mesa_hash_table_insert(ctx->vars, variable, shared);
5428 }
5429 }
5430
5431 static LLVMValueRef
5432 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5433 {
5434 v = ac_to_float(ctx, v);
5435 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5436 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5437 }
5438
5439
5440 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5441 LLVMValueRef src0, LLVMValueRef src1)
5442 {
5443 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5444 LLVMValueRef comp[2];
5445
5446 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5447 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5448 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5449 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5450 }
5451
5452 /* Initialize arguments for the shader export intrinsic */
5453 static void
5454 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5455 LLVMValueRef *values,
5456 unsigned target,
5457 struct ac_export_args *args)
5458 {
5459 /* Default is 0xf. Adjusted below depending on the format. */
5460 args->enabled_channels = 0xf;
5461
5462 /* Specify whether the EXEC mask represents the valid mask */
5463 args->valid_mask = 0;
5464
5465 /* Specify whether this is the last export */
5466 args->done = 0;
5467
5468 /* Specify the target we are exporting */
5469 args->target = target;
5470
5471 args->compr = false;
5472 args->out[0] = LLVMGetUndef(ctx->f32);
5473 args->out[1] = LLVMGetUndef(ctx->f32);
5474 args->out[2] = LLVMGetUndef(ctx->f32);
5475 args->out[3] = LLVMGetUndef(ctx->f32);
5476
5477 if (!values)
5478 return;
5479
5480 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5481 LLVMValueRef val[4];
5482 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5483 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5484 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5485 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5486
5487 switch(col_format) {
5488 case V_028714_SPI_SHADER_ZERO:
5489 args->enabled_channels = 0; /* writemask */
5490 args->target = V_008DFC_SQ_EXP_NULL;
5491 break;
5492
5493 case V_028714_SPI_SHADER_32_R:
5494 args->enabled_channels = 1;
5495 args->out[0] = values[0];
5496 break;
5497
5498 case V_028714_SPI_SHADER_32_GR:
5499 args->enabled_channels = 0x3;
5500 args->out[0] = values[0];
5501 args->out[1] = values[1];
5502 break;
5503
5504 case V_028714_SPI_SHADER_32_AR:
5505 args->enabled_channels = 0x9;
5506 args->out[0] = values[0];
5507 args->out[3] = values[3];
5508 break;
5509
5510 case V_028714_SPI_SHADER_FP16_ABGR:
5511 args->compr = 1;
5512
5513 for (unsigned chan = 0; chan < 2; chan++) {
5514 LLVMValueRef pack_args[2] = {
5515 values[2 * chan],
5516 values[2 * chan + 1]
5517 };
5518 LLVMValueRef packed;
5519
5520 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5521 args->out[chan] = packed;
5522 }
5523 break;
5524
5525 case V_028714_SPI_SHADER_UNORM16_ABGR:
5526 for (unsigned chan = 0; chan < 4; chan++) {
5527 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5528 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5529 LLVMConstReal(ctx->f32, 65535), "");
5530 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5531 LLVMConstReal(ctx->f32, 0.5), "");
5532 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5533 ctx->i32, "");
5534 }
5535
5536 args->compr = 1;
5537 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5538 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5539 break;
5540
5541 case V_028714_SPI_SHADER_SNORM16_ABGR:
5542 for (unsigned chan = 0; chan < 4; chan++) {
5543 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5544 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5545 LLVMConstReal(ctx->f32, 32767), "");
5546
5547 /* If positive, add 0.5, else add -0.5. */
5548 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5549 LLVMBuildSelect(ctx->builder,
5550 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5551 val[chan], ctx->f32zero, ""),
5552 LLVMConstReal(ctx->f32, 0.5),
5553 LLVMConstReal(ctx->f32, -0.5), ""), "");
5554 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5555 }
5556
5557 args->compr = 1;
5558 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5559 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5560 break;
5561
5562 case V_028714_SPI_SHADER_UINT16_ABGR: {
5563 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5564 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5565 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5566
5567 for (unsigned chan = 0; chan < 4; chan++) {
5568 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5569 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5570 }
5571
5572 args->compr = 1;
5573 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5574 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5575 break;
5576 }
5577
5578 case V_028714_SPI_SHADER_SINT16_ABGR: {
5579 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5580 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5581 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5582 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5583 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5584 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5585
5586 /* Clamp. */
5587 for (unsigned chan = 0; chan < 4; chan++) {
5588 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5589 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5590 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5591 }
5592
5593 args->compr = 1;
5594 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5595 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5596 break;
5597 }
5598
5599 default:
5600 case V_028714_SPI_SHADER_32_ABGR:
5601 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5602 break;
5603 }
5604 } else
5605 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5606
5607 for (unsigned i = 0; i < 4; ++i)
5608 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5609 }
5610
5611 static void
5612 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5613 bool export_prim_id,
5614 struct ac_vs_output_info *outinfo)
5615 {
5616 uint32_t param_count = 0;
5617 unsigned target;
5618 unsigned pos_idx, num_pos_exports = 0;
5619 struct ac_export_args args, pos_args[4] = {};
5620 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5621 int i;
5622
5623 if (ctx->options->key.has_multiview_view_index) {
5624 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5625 if(!*tmp_out) {
5626 for(unsigned i = 0; i < 4; ++i)
5627 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5628 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5629 }
5630
5631 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5632 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5633 }
5634
5635 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5636 sizeof(outinfo->vs_output_param_offset));
5637
5638 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5639 LLVMValueRef slots[8];
5640 unsigned j;
5641
5642 if (outinfo->cull_dist_mask)
5643 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5644
5645 i = VARYING_SLOT_CLIP_DIST0;
5646 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5647 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5648 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5649
5650 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5651 slots[i] = LLVMGetUndef(ctx->f32);
5652
5653 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5654 target = V_008DFC_SQ_EXP_POS + 3;
5655 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5656 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5657 &args, sizeof(args));
5658 }
5659
5660 target = V_008DFC_SQ_EXP_POS + 2;
5661 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5662 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5663 &args, sizeof(args));
5664
5665 }
5666
5667 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5668 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5669 for (unsigned j = 0; j < 4; j++)
5670 pos_values[j] = LLVMBuildLoad(ctx->builder,
5671 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5672 }
5673 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5674
5675 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5676 outinfo->writes_pointsize = true;
5677 psize_value = LLVMBuildLoad(ctx->builder,
5678 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5679 }
5680
5681 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5682 outinfo->writes_layer = true;
5683 layer_value = LLVMBuildLoad(ctx->builder,
5684 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5685 }
5686
5687 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5688 outinfo->writes_viewport_index = true;
5689 viewport_index_value = LLVMBuildLoad(ctx->builder,
5690 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5691 }
5692
5693 if (outinfo->writes_pointsize ||
5694 outinfo->writes_layer ||
5695 outinfo->writes_viewport_index) {
5696 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5697 (outinfo->writes_layer == true ? 4 : 0));
5698 pos_args[1].valid_mask = 0;
5699 pos_args[1].done = 0;
5700 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5701 pos_args[1].compr = 0;
5702 pos_args[1].out[0] = ctx->f32zero; /* X */
5703 pos_args[1].out[1] = ctx->f32zero; /* Y */
5704 pos_args[1].out[2] = ctx->f32zero; /* Z */
5705 pos_args[1].out[3] = ctx->f32zero; /* W */
5706
5707 if (outinfo->writes_pointsize == true)
5708 pos_args[1].out[0] = psize_value;
5709 if (outinfo->writes_layer == true)
5710 pos_args[1].out[2] = layer_value;
5711 if (outinfo->writes_viewport_index == true) {
5712 if (ctx->options->chip_class >= GFX9) {
5713 /* GFX9 has the layer in out.z[10:0] and the viewport
5714 * index in out.z[19:16].
5715 */
5716 LLVMValueRef v = viewport_index_value;
5717 v = ac_to_integer(&ctx->ac, v);
5718 v = LLVMBuildShl(ctx->builder, v,
5719 LLVMConstInt(ctx->i32, 16, false),
5720 "");
5721 v = LLVMBuildOr(ctx->builder, v,
5722 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5723
5724 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5725 pos_args[1].enabled_channels |= 1 << 2;
5726 } else {
5727 pos_args[1].out[3] = viewport_index_value;
5728 pos_args[1].enabled_channels |= 1 << 3;
5729 }
5730 }
5731 }
5732 for (i = 0; i < 4; i++) {
5733 if (pos_args[i].out[0])
5734 num_pos_exports++;
5735 }
5736
5737 pos_idx = 0;
5738 for (i = 0; i < 4; i++) {
5739 if (!pos_args[i].out[0])
5740 continue;
5741
5742 /* Specify the target we are exporting */
5743 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5744 if (pos_idx == num_pos_exports)
5745 pos_args[i].done = 1;
5746 ac_build_export(&ctx->ac, &pos_args[i]);
5747 }
5748
5749 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5750 LLVMValueRef values[4];
5751 if (!(ctx->output_mask & (1ull << i)))
5752 continue;
5753
5754 for (unsigned j = 0; j < 4; j++)
5755 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5756 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5757
5758 if (i == VARYING_SLOT_LAYER) {
5759 target = V_008DFC_SQ_EXP_PARAM + param_count;
5760 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5761 param_count++;
5762 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5763 target = V_008DFC_SQ_EXP_PARAM + param_count;
5764 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5765 param_count++;
5766 } else if (i >= VARYING_SLOT_VAR0) {
5767 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5768 target = V_008DFC_SQ_EXP_PARAM + param_count;
5769 outinfo->vs_output_param_offset[i] = param_count;
5770 param_count++;
5771 } else
5772 continue;
5773
5774 si_llvm_init_export_args(ctx, values, target, &args);
5775
5776 if (target >= V_008DFC_SQ_EXP_POS &&
5777 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5778 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5779 &args, sizeof(args));
5780 } else {
5781 ac_build_export(&ctx->ac, &args);
5782 }
5783 }
5784
5785 if (export_prim_id) {
5786 LLVMValueRef values[4];
5787 target = V_008DFC_SQ_EXP_PARAM + param_count;
5788 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5789 param_count++;
5790
5791 values[0] = ctx->vs_prim_id;
5792 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5793 ctx->shader_info->vs.vgpr_comp_cnt);
5794 for (unsigned j = 1; j < 4; j++)
5795 values[j] = ctx->f32zero;
5796 si_llvm_init_export_args(ctx, values, target, &args);
5797 ac_build_export(&ctx->ac, &args);
5798 outinfo->export_prim_id = true;
5799 }
5800
5801 outinfo->pos_exports = num_pos_exports;
5802 outinfo->param_exports = param_count;
5803 }
5804
5805 static void
5806 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5807 struct ac_es_output_info *outinfo)
5808 {
5809 int j;
5810 uint64_t max_output_written = 0;
5811 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5812 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5813 int param_index;
5814 int length = 4;
5815
5816 if (!(ctx->output_mask & (1ull << i)))
5817 continue;
5818
5819 if (i == VARYING_SLOT_CLIP_DIST0)
5820 length = ctx->num_output_clips + ctx->num_output_culls;
5821
5822 param_index = shader_io_get_unique_index(i);
5823
5824 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5825
5826 for (j = 0; j < length; j++) {
5827 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5828 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5829
5830 ac_build_buffer_store_dword(&ctx->ac,
5831 ctx->esgs_ring,
5832 out_val, 1,
5833 NULL, ctx->es2gs_offset,
5834 (4 * param_index + j) * 4,
5835 1, 1, true, true);
5836 }
5837 }
5838 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5839 }
5840
5841 static void
5842 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5843 {
5844 LLVMValueRef vertex_id = ctx->rel_auto_id;
5845 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5846 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5847 vertex_dw_stride, "");
5848
5849 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5850 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5851 int length = 4;
5852
5853 if (!(ctx->output_mask & (1ull << i)))
5854 continue;
5855
5856 if (i == VARYING_SLOT_CLIP_DIST0)
5857 length = ctx->num_output_clips + ctx->num_output_culls;
5858 int param = shader_io_get_unique_index(i);
5859 mark_tess_output(ctx, false, param);
5860 if (length > 4)
5861 mark_tess_output(ctx, false, param + 1);
5862 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5863 LLVMConstInt(ctx->i32, param * 4, false),
5864 "");
5865 for (unsigned j = 0; j < length; j++) {
5866 lds_store(ctx, dw_addr,
5867 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5868 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5869 }
5870 }
5871 }
5872
5873 struct ac_build_if_state
5874 {
5875 struct nir_to_llvm_context *ctx;
5876 LLVMValueRef condition;
5877 LLVMBasicBlockRef entry_block;
5878 LLVMBasicBlockRef true_block;
5879 LLVMBasicBlockRef false_block;
5880 LLVMBasicBlockRef merge_block;
5881 };
5882
5883 static LLVMBasicBlockRef
5884 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5885 {
5886 LLVMBasicBlockRef current_block;
5887 LLVMBasicBlockRef next_block;
5888 LLVMBasicBlockRef new_block;
5889
5890 /* get current basic block */
5891 current_block = LLVMGetInsertBlock(ctx->builder);
5892
5893 /* chqeck if there's another block after this one */
5894 next_block = LLVMGetNextBasicBlock(current_block);
5895 if (next_block) {
5896 /* insert the new block before the next block */
5897 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5898 }
5899 else {
5900 /* append new block after current block */
5901 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5902 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5903 }
5904 return new_block;
5905 }
5906
5907 static void
5908 ac_nir_build_if(struct ac_build_if_state *ifthen,
5909 struct nir_to_llvm_context *ctx,
5910 LLVMValueRef condition)
5911 {
5912 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5913
5914 memset(ifthen, 0, sizeof *ifthen);
5915 ifthen->ctx = ctx;
5916 ifthen->condition = condition;
5917 ifthen->entry_block = block;
5918
5919 /* create endif/merge basic block for the phi functions */
5920 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5921
5922 /* create/insert true_block before merge_block */
5923 ifthen->true_block =
5924 LLVMInsertBasicBlockInContext(ctx->context,
5925 ifthen->merge_block,
5926 "if-true-block");
5927
5928 /* successive code goes into the true block */
5929 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5930 }
5931
5932 /**
5933 * End a conditional.
5934 */
5935 static void
5936 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5937 {
5938 LLVMBuilderRef builder = ifthen->ctx->builder;
5939
5940 /* Insert branch to the merge block from current block */
5941 LLVMBuildBr(builder, ifthen->merge_block);
5942
5943 /*
5944 * Now patch in the various branch instructions.
5945 */
5946
5947 /* Insert the conditional branch instruction at the end of entry_block */
5948 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5949 if (ifthen->false_block) {
5950 /* we have an else clause */
5951 LLVMBuildCondBr(builder, ifthen->condition,
5952 ifthen->true_block, ifthen->false_block);
5953 }
5954 else {
5955 /* no else clause */
5956 LLVMBuildCondBr(builder, ifthen->condition,
5957 ifthen->true_block, ifthen->merge_block);
5958 }
5959
5960 /* Resume building code at end of the ifthen->merge_block */
5961 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5962 }
5963
5964 static void
5965 write_tess_factors(struct nir_to_llvm_context *ctx)
5966 {
5967 unsigned stride, outer_comps, inner_comps;
5968 struct ac_build_if_state if_ctx, inner_if_ctx;
5969 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5970 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5971 unsigned tess_inner_index, tess_outer_index;
5972 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5973 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5974 int i;
5975 emit_barrier(ctx);
5976
5977 switch (ctx->options->key.tcs.primitive_mode) {
5978 case GL_ISOLINES:
5979 stride = 2;
5980 outer_comps = 2;
5981 inner_comps = 0;
5982 break;
5983 case GL_TRIANGLES:
5984 stride = 4;
5985 outer_comps = 3;
5986 inner_comps = 1;
5987 break;
5988 case GL_QUADS:
5989 stride = 6;
5990 outer_comps = 4;
5991 inner_comps = 2;
5992 break;
5993 default:
5994 return;
5995 }
5996
5997 ac_nir_build_if(&if_ctx, ctx,
5998 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5999 invocation_id, ctx->i32zero, ""));
6000
6001 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6002 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6003
6004 mark_tess_output(ctx, true, tess_inner_index);
6005 mark_tess_output(ctx, true, tess_outer_index);
6006 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6007 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6008 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
6009 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6010 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
6011
6012 for (i = 0; i < 4; i++) {
6013 inner[i] = LLVMGetUndef(ctx->i32);
6014 outer[i] = LLVMGetUndef(ctx->i32);
6015 }
6016
6017 // LINES reverseal
6018 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6019 outer[0] = out[1] = lds_load(ctx, lds_outer);
6020 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6021 LLVMConstInt(ctx->i32, 1, false), "");
6022 outer[1] = out[0] = lds_load(ctx, lds_outer);
6023 } else {
6024 for (i = 0; i < outer_comps; i++) {
6025 outer[i] = out[i] =
6026 lds_load(ctx, lds_outer);
6027 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6028 LLVMConstInt(ctx->i32, 1, false), "");
6029 }
6030 for (i = 0; i < inner_comps; i++) {
6031 inner[i] = out[outer_comps+i] =
6032 lds_load(ctx, lds_inner);
6033 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6034 LLVMConstInt(ctx->i32, 1, false), "");
6035 }
6036 }
6037
6038 /* Convert the outputs to vectors for stores. */
6039 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6040 vec1 = NULL;
6041
6042 if (stride > 4)
6043 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6044
6045
6046 buffer = ctx->hs_ring_tess_factor;
6047 tf_base = ctx->tess_factor_offset;
6048 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6049 LLVMConstInt(ctx->i32, 4 * stride, false), "");
6050 unsigned tf_offset = 0;
6051
6052 if (ctx->options->chip_class <= VI) {
6053 ac_nir_build_if(&inner_if_ctx, ctx,
6054 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6055 rel_patch_id, ctx->i32zero, ""));
6056
6057 /* Store the dynamic HS control word. */
6058 ac_build_buffer_store_dword(&ctx->ac, buffer,
6059 LLVMConstInt(ctx->i32, 0x80000000, false),
6060 1, ctx->i32zero, tf_base,
6061 0, 1, 0, true, false);
6062 tf_offset += 4;
6063
6064 ac_nir_build_endif(&inner_if_ctx);
6065 }
6066
6067 /* Store the tessellation factors. */
6068 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6069 MIN2(stride, 4), byteoffset, tf_base,
6070 tf_offset, 1, 0, true, false);
6071 if (vec1)
6072 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6073 stride - 4, byteoffset, tf_base,
6074 16 + tf_offset, 1, 0, true, false);
6075
6076 //TODO store to offchip for TES to read - only if TES reads them
6077 if (1) {
6078 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6079 LLVMValueRef tf_inner_offset;
6080 unsigned param_outer, param_inner;
6081
6082 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6083 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6084 LLVMConstInt(ctx->i32, param_outer, 0));
6085
6086 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6087 util_next_power_of_two(outer_comps));
6088
6089 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6090 outer_comps, tf_outer_offset,
6091 ctx->oc_lds, 0, 1, 0, true, false);
6092 if (inner_comps) {
6093 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6094 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6095 LLVMConstInt(ctx->i32, param_inner, 0));
6096
6097 inner_vec = inner_comps == 1 ? inner[0] :
6098 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6099 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6100 inner_comps, tf_inner_offset,
6101 ctx->oc_lds, 0, 1, 0, true, false);
6102 }
6103 }
6104 ac_nir_build_endif(&if_ctx);
6105 }
6106
6107 static void
6108 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6109 {
6110 write_tess_factors(ctx);
6111 }
6112
6113 static bool
6114 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6115 LLVMValueRef *color, unsigned param, bool is_last,
6116 struct ac_export_args *args)
6117 {
6118 /* Export */
6119 si_llvm_init_export_args(ctx, color, param,
6120 args);
6121
6122 if (is_last) {
6123 args->valid_mask = 1; /* whether the EXEC mask is valid */
6124 args->done = 1; /* DONE bit */
6125 } else if (!args->enabled_channels)
6126 return false; /* unnecessary NULL export */
6127
6128 return true;
6129 }
6130
6131 static void
6132 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6133 LLVMValueRef depth, LLVMValueRef stencil,
6134 LLVMValueRef samplemask)
6135 {
6136 struct ac_export_args args;
6137
6138 args.enabled_channels = 0;
6139 args.valid_mask = 1;
6140 args.done = 1;
6141 args.target = V_008DFC_SQ_EXP_MRTZ;
6142 args.compr = false;
6143
6144 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6145 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6146 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6147 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6148
6149 if (depth) {
6150 args.out[0] = depth;
6151 args.enabled_channels |= 0x1;
6152 }
6153
6154 if (stencil) {
6155 args.out[1] = stencil;
6156 args.enabled_channels |= 0x2;
6157 }
6158
6159 if (samplemask) {
6160 args.out[2] = samplemask;
6161 args.enabled_channels |= 0x4;
6162 }
6163
6164 /* SI (except OLAND and HAINAN) has a bug that it only looks
6165 * at the X writemask component. */
6166 if (ctx->options->chip_class == SI &&
6167 ctx->options->family != CHIP_OLAND &&
6168 ctx->options->family != CHIP_HAINAN)
6169 args.enabled_channels |= 0x1;
6170
6171 ac_build_export(&ctx->ac, &args);
6172 }
6173
6174 static void
6175 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6176 {
6177 unsigned index = 0;
6178 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6179 struct ac_export_args color_args[8];
6180
6181 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6182 LLVMValueRef values[4];
6183
6184 if (!(ctx->output_mask & (1ull << i)))
6185 continue;
6186
6187 if (i == FRAG_RESULT_DEPTH) {
6188 ctx->shader_info->fs.writes_z = true;
6189 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6190 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6191 } else if (i == FRAG_RESULT_STENCIL) {
6192 ctx->shader_info->fs.writes_stencil = true;
6193 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6194 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6195 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6196 ctx->shader_info->fs.writes_sample_mask = true;
6197 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6198 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6199 } else {
6200 bool last = false;
6201 for (unsigned j = 0; j < 4; j++)
6202 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6203 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6204
6205 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6206 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6207
6208 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6209 if (ret)
6210 index++;
6211 }
6212 }
6213
6214 for (unsigned i = 0; i < index; i++)
6215 ac_build_export(&ctx->ac, &color_args[i]);
6216 if (depth || stencil || samplemask)
6217 si_export_mrt_z(ctx, depth, stencil, samplemask);
6218 else if (!index) {
6219 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6220 ac_build_export(&ctx->ac, &color_args[0]);
6221 }
6222
6223 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6224 }
6225
6226 static void
6227 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6228 {
6229 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6230 }
6231
6232 static void
6233 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6234 LLVMValueRef *addrs)
6235 {
6236 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6237
6238 switch (ctx->stage) {
6239 case MESA_SHADER_VERTEX:
6240 if (ctx->options->key.vs.as_ls)
6241 handle_ls_outputs_post(ctx);
6242 else if (ctx->options->key.vs.as_es)
6243 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6244 else
6245 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6246 &ctx->shader_info->vs.outinfo);
6247 break;
6248 case MESA_SHADER_FRAGMENT:
6249 handle_fs_outputs_post(ctx);
6250 break;
6251 case MESA_SHADER_GEOMETRY:
6252 emit_gs_epilogue(ctx);
6253 break;
6254 case MESA_SHADER_TESS_CTRL:
6255 handle_tcs_outputs_post(ctx);
6256 break;
6257 case MESA_SHADER_TESS_EVAL:
6258 if (ctx->options->key.tes.as_es)
6259 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6260 else
6261 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6262 &ctx->shader_info->tes.outinfo);
6263 break;
6264 default:
6265 break;
6266 }
6267 }
6268
6269 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6270 {
6271 LLVMPassManagerRef passmgr;
6272 /* Create the pass manager */
6273 passmgr = LLVMCreateFunctionPassManagerForModule(
6274 ctx->module);
6275
6276 /* This pass should eliminate all the load and store instructions */
6277 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6278
6279 /* Add some optimization passes */
6280 LLVMAddScalarReplAggregatesPass(passmgr);
6281 LLVMAddLICMPass(passmgr);
6282 LLVMAddAggressiveDCEPass(passmgr);
6283 LLVMAddCFGSimplificationPass(passmgr);
6284 LLVMAddInstructionCombiningPass(passmgr);
6285
6286 /* Run the pass */
6287 LLVMInitializeFunctionPassManager(passmgr);
6288 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6289 LLVMFinalizeFunctionPassManager(passmgr);
6290
6291 LLVMDisposeBuilder(ctx->builder);
6292 LLVMDisposePassManager(passmgr);
6293 }
6294
6295 static void
6296 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6297 {
6298 struct ac_vs_output_info *outinfo;
6299
6300 switch (ctx->stage) {
6301 case MESA_SHADER_FRAGMENT:
6302 case MESA_SHADER_COMPUTE:
6303 case MESA_SHADER_TESS_CTRL:
6304 case MESA_SHADER_GEOMETRY:
6305 return;
6306 case MESA_SHADER_VERTEX:
6307 if (ctx->options->key.vs.as_ls ||
6308 ctx->options->key.vs.as_es)
6309 return;
6310 outinfo = &ctx->shader_info->vs.outinfo;
6311 break;
6312 case MESA_SHADER_TESS_EVAL:
6313 if (ctx->options->key.vs.as_es)
6314 return;
6315 outinfo = &ctx->shader_info->tes.outinfo;
6316 break;
6317 default:
6318 unreachable("Unhandled shader type");
6319 }
6320
6321 ac_optimize_vs_outputs(&ctx->ac,
6322 ctx->main_function,
6323 outinfo->vs_output_param_offset,
6324 VARYING_SLOT_MAX,
6325 &outinfo->param_exports);
6326 }
6327
6328 static void
6329 ac_setup_rings(struct nir_to_llvm_context *ctx)
6330 {
6331 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6332 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6333 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6334 }
6335
6336 if (ctx->is_gs_copy_shader) {
6337 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6338 }
6339 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6340 LLVMValueRef tmp;
6341 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6342 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6343
6344 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6345
6346 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6347 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6348 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6349 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6350 }
6351
6352 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6353 ctx->stage == MESA_SHADER_TESS_EVAL) {
6354 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6355 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6356 }
6357 }
6358
6359 static unsigned
6360 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6361 const struct nir_shader *nir)
6362 {
6363 switch (nir->stage) {
6364 case MESA_SHADER_TESS_CTRL:
6365 return chip_class >= CIK ? 128 : 64;
6366 case MESA_SHADER_GEOMETRY:
6367 return 64;
6368 case MESA_SHADER_COMPUTE:
6369 break;
6370 default:
6371 return 0;
6372 }
6373
6374 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6375 nir->info.cs.local_size[1] *
6376 nir->info.cs.local_size[2];
6377 return max_workgroup_size;
6378 }
6379
6380 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6381 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6382 {
6383 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6384 LLVMConstInt(ctx->ac.i32, 8, false),
6385 LLVMConstInt(ctx->ac.i32, 8, false), false);
6386 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6387 LLVMConstInt(ctx->ac.i32, 0, false), "");
6388 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6389 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6390 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6391 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6392 }
6393
6394 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6395 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6396 {
6397 struct ac_nir_context ctx = {};
6398 struct nir_function *func;
6399
6400 ctx.ac = *ac;
6401 ctx.abi = abi;
6402
6403 ctx.nctx = nctx;
6404 if (nctx)
6405 nctx->nir = &ctx;
6406
6407 ctx.stage = nir->stage;
6408
6409 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6410
6411 nir_foreach_variable(variable, &nir->outputs)
6412 handle_shader_output_decl(&ctx, nir, variable);
6413
6414 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6415 _mesa_key_pointer_equal);
6416 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6417 _mesa_key_pointer_equal);
6418 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6419 _mesa_key_pointer_equal);
6420
6421 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6422
6423 setup_locals(&ctx, func);
6424
6425 if (nir->stage == MESA_SHADER_COMPUTE)
6426 setup_shared(&ctx, nir);
6427
6428 visit_cf_list(&ctx, &func->impl->body);
6429 phi_post_pass(&ctx);
6430
6431 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6432 ctx.outputs);
6433
6434 free(ctx.locals);
6435 ralloc_free(ctx.defs);
6436 ralloc_free(ctx.phis);
6437 ralloc_free(ctx.vars);
6438
6439 if (nctx)
6440 nctx->nir = NULL;
6441 }
6442
6443 static
6444 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6445 struct nir_shader *const *shaders,
6446 int shader_count,
6447 struct ac_shader_variant_info *shader_info,
6448 const struct ac_nir_compiler_options *options)
6449 {
6450 struct nir_to_llvm_context ctx = {0};
6451 unsigned i;
6452 ctx.options = options;
6453 ctx.shader_info = shader_info;
6454 ctx.context = LLVMContextCreate();
6455 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6456
6457 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6458 ctx.ac.module = ctx.module;
6459 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6460
6461 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6462 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6463 LLVMSetDataLayout(ctx.module, data_layout_str);
6464 LLVMDisposeTargetData(data_layout);
6465 LLVMDisposeMessage(data_layout_str);
6466
6467 setup_types(&ctx);
6468 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6469 ctx.ac.builder = ctx.builder;
6470
6471 memset(shader_info, 0, sizeof(*shader_info));
6472
6473 for(int i = 0; i < shader_count; ++i)
6474 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6475
6476 for (i = 0; i < AC_UD_MAX_SETS; i++)
6477 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6478 for (i = 0; i < AC_UD_MAX_UD; i++)
6479 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6480
6481 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, shaders[0]);
6482
6483 create_function(&ctx, shaders[shader_count - 1]->stage, shader_count >= 2,
6484 shader_count >= 2 ? shaders[shader_count - 2]->stage : MESA_SHADER_VERTEX);
6485
6486 ctx.abi.inputs = &ctx.inputs[0];
6487 ctx.abi.emit_outputs = handle_shader_outputs_post;
6488 ctx.abi.load_ssbo = radv_load_ssbo;
6489 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6490
6491 if (ctx.ac.chip_class == GFX9 &&
6492 shaders[shader_count - 1]->stage == MESA_SHADER_TESS_CTRL)
6493 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6494
6495 for(int i = 0; i < shader_count; ++i) {
6496 ctx.stage = shaders[i]->stage;
6497 ctx.output_mask = 0;
6498 ctx.tess_outputs_written = 0;
6499 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6500 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6501
6502 if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
6503 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6504
6505 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6506 } else if (shaders[i]->stage == MESA_SHADER_TESS_EVAL) {
6507 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6508 } else if (shaders[i]->stage == MESA_SHADER_VERTEX) {
6509 if (shader_info->info.vs.needs_instance_id) {
6510 ctx.shader_info->vs.vgpr_comp_cnt =
6511 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6512 }
6513 } else if (shaders[i]->stage == MESA_SHADER_FRAGMENT) {
6514 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6515 }
6516
6517 if (i)
6518 emit_barrier(&ctx);
6519
6520 ac_setup_rings(&ctx);
6521
6522 LLVMBasicBlockRef merge_block;
6523 if (shader_count >= 2) {
6524 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6525 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6526 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6527
6528 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6529 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6530 LLVMConstInt(ctx.ac.i32, 8, false), false);
6531 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6532 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6533 thread_id, count, "");
6534 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6535
6536 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6537 }
6538
6539 if (shaders[i]->stage == MESA_SHADER_FRAGMENT)
6540 handle_fs_inputs(&ctx, shaders[i]);
6541 else if(shaders[i]->stage == MESA_SHADER_VERTEX)
6542 handle_vs_inputs(&ctx, shaders[i]);
6543
6544 nir_foreach_variable(variable, &shaders[i]->outputs)
6545 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->stage);
6546
6547 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6548
6549 if (shader_count >= 2) {
6550 LLVMBuildBr(ctx.ac.builder, merge_block);
6551 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6552 }
6553
6554 if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
6555 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6556 shaders[i]->info.cull_distance_array_size > 4;
6557 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6558 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6559 shaders[i]->info.gs.vertices_out;
6560 } else if (shaders[i]->stage == MESA_SHADER_TESS_CTRL) {
6561 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6562 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6563 } else if (shaders[i]->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6564 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6565 }
6566 }
6567
6568 LLVMBuildRetVoid(ctx.builder);
6569
6570 ac_llvm_finalize_module(&ctx);
6571
6572 if (shader_count == 1)
6573 ac_nir_eliminate_const_vs_outputs(&ctx);
6574
6575 return ctx.module;
6576 }
6577
6578 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6579 {
6580 unsigned *retval = (unsigned *)context;
6581 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6582 char *description = LLVMGetDiagInfoDescription(di);
6583
6584 if (severity == LLVMDSError) {
6585 *retval = 1;
6586 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6587 description);
6588 }
6589
6590 LLVMDisposeMessage(description);
6591 }
6592
6593 static unsigned ac_llvm_compile(LLVMModuleRef M,
6594 struct ac_shader_binary *binary,
6595 LLVMTargetMachineRef tm)
6596 {
6597 unsigned retval = 0;
6598 char *err;
6599 LLVMContextRef llvm_ctx;
6600 LLVMMemoryBufferRef out_buffer;
6601 unsigned buffer_size;
6602 const char *buffer_data;
6603 LLVMBool mem_err;
6604
6605 /* Setup Diagnostic Handler*/
6606 llvm_ctx = LLVMGetModuleContext(M);
6607
6608 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6609 &retval);
6610
6611 /* Compile IR*/
6612 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6613 &err, &out_buffer);
6614
6615 /* Process Errors/Warnings */
6616 if (mem_err) {
6617 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6618 free(err);
6619 retval = 1;
6620 goto out;
6621 }
6622
6623 /* Extract Shader Code*/
6624 buffer_size = LLVMGetBufferSize(out_buffer);
6625 buffer_data = LLVMGetBufferStart(out_buffer);
6626
6627 ac_elf_read(buffer_data, buffer_size, binary);
6628
6629 /* Clean up */
6630 LLVMDisposeMemoryBuffer(out_buffer);
6631
6632 out:
6633 return retval;
6634 }
6635
6636 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6637 LLVMModuleRef llvm_module,
6638 struct ac_shader_binary *binary,
6639 struct ac_shader_config *config,
6640 struct ac_shader_variant_info *shader_info,
6641 gl_shader_stage stage,
6642 bool dump_shader, bool supports_spill)
6643 {
6644 if (dump_shader)
6645 ac_dump_module(llvm_module);
6646
6647 memset(binary, 0, sizeof(*binary));
6648 int v = ac_llvm_compile(llvm_module, binary, tm);
6649 if (v) {
6650 fprintf(stderr, "compile failed\n");
6651 }
6652
6653 if (dump_shader)
6654 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6655
6656 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6657
6658 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6659 LLVMDisposeModule(llvm_module);
6660 LLVMContextDispose(ctx);
6661
6662 if (stage == MESA_SHADER_FRAGMENT) {
6663 shader_info->num_input_vgprs = 0;
6664 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6665 shader_info->num_input_vgprs += 2;
6666 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6667 shader_info->num_input_vgprs += 2;
6668 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6669 shader_info->num_input_vgprs += 2;
6670 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6671 shader_info->num_input_vgprs += 3;
6672 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6673 shader_info->num_input_vgprs += 2;
6674 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6675 shader_info->num_input_vgprs += 2;
6676 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6677 shader_info->num_input_vgprs += 2;
6678 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6679 shader_info->num_input_vgprs += 1;
6680 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6681 shader_info->num_input_vgprs += 1;
6682 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6683 shader_info->num_input_vgprs += 1;
6684 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6685 shader_info->num_input_vgprs += 1;
6686 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6687 shader_info->num_input_vgprs += 1;
6688 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6689 shader_info->num_input_vgprs += 1;
6690 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6691 shader_info->num_input_vgprs += 1;
6692 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6693 shader_info->num_input_vgprs += 1;
6694 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6695 shader_info->num_input_vgprs += 1;
6696 }
6697 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6698
6699 /* +3 for scratch wave offset and VCC */
6700 config->num_sgprs = MAX2(config->num_sgprs,
6701 shader_info->num_input_sgprs + 3);
6702 }
6703
6704 static void
6705 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6706 {
6707 switch (nir->stage) {
6708 case MESA_SHADER_COMPUTE:
6709 for (int i = 0; i < 3; ++i)
6710 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6711 break;
6712 case MESA_SHADER_FRAGMENT:
6713 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6714 break;
6715 case MESA_SHADER_GEOMETRY:
6716 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6717 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6718 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6719 shader_info->gs.invocations = nir->info.gs.invocations;
6720 break;
6721 case MESA_SHADER_TESS_EVAL:
6722 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6723 shader_info->tes.spacing = nir->info.tess.spacing;
6724 shader_info->tes.ccw = nir->info.tess.ccw;
6725 shader_info->tes.point_mode = nir->info.tess.point_mode;
6726 shader_info->tes.as_es = options->key.tes.as_es;
6727 break;
6728 case MESA_SHADER_TESS_CTRL:
6729 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6730 break;
6731 case MESA_SHADER_VERTEX:
6732 shader_info->vs.as_es = options->key.vs.as_es;
6733 shader_info->vs.as_ls = options->key.vs.as_ls;
6734 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6735 if (options->key.vs.as_ls)
6736 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6737 break;
6738 default:
6739 break;
6740 }
6741 }
6742
6743 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6744 struct ac_shader_binary *binary,
6745 struct ac_shader_config *config,
6746 struct ac_shader_variant_info *shader_info,
6747 struct nir_shader *const *nir,
6748 int nir_count,
6749 const struct ac_nir_compiler_options *options,
6750 bool dump_shader)
6751 {
6752
6753 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6754 options);
6755
6756 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->stage, dump_shader, options->supports_spill);
6757 for (int i = 0; i < nir_count; ++i)
6758 ac_fill_shader_info(shader_info, nir[i], options);
6759 }
6760
6761 static void
6762 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6763 {
6764 LLVMValueRef args[9];
6765 args[0] = ctx->gsvs_ring;
6766 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6767 args[3] = ctx->i32zero;
6768 args[4] = ctx->i32one; /* OFFEN */
6769 args[5] = ctx->i32zero; /* IDXEN */
6770 args[6] = ctx->i32one; /* GLC */
6771 args[7] = ctx->i32one; /* SLC */
6772 args[8] = ctx->i32zero; /* TFE */
6773
6774 int idx = 0;
6775
6776 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6777 int length = 4;
6778 int slot = idx;
6779 int slot_inc = 1;
6780 if (!(ctx->output_mask & (1ull << i)))
6781 continue;
6782
6783 if (i == VARYING_SLOT_CLIP_DIST0) {
6784 /* unpack clip and cull from a single set of slots */
6785 length = ctx->num_output_clips + ctx->num_output_culls;
6786 if (length > 4)
6787 slot_inc = 2;
6788 }
6789
6790 for (unsigned j = 0; j < length; j++) {
6791 LLVMValueRef value;
6792 args[2] = LLVMConstInt(ctx->i32,
6793 (slot * 4 + j) *
6794 ctx->gs_max_out_vertices * 16 * 4, false);
6795
6796 value = ac_build_intrinsic(&ctx->ac,
6797 "llvm.SI.buffer.load.dword.i32.i32",
6798 ctx->i32, args, 9,
6799 AC_FUNC_ATTR_READONLY |
6800 AC_FUNC_ATTR_LEGACY);
6801
6802 LLVMBuildStore(ctx->builder,
6803 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6804 }
6805 idx += slot_inc;
6806 }
6807 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6808 }
6809
6810 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6811 struct nir_shader *geom_shader,
6812 struct ac_shader_binary *binary,
6813 struct ac_shader_config *config,
6814 struct ac_shader_variant_info *shader_info,
6815 const struct ac_nir_compiler_options *options,
6816 bool dump_shader)
6817 {
6818 struct nir_to_llvm_context ctx = {0};
6819 ctx.context = LLVMContextCreate();
6820 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6821 ctx.options = options;
6822 ctx.shader_info = shader_info;
6823
6824 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6825 ctx.ac.module = ctx.module;
6826
6827 ctx.is_gs_copy_shader = true;
6828 LLVMSetTarget(ctx.module, "amdgcn--");
6829 setup_types(&ctx);
6830
6831 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6832 ctx.ac.builder = ctx.builder;
6833 ctx.stage = MESA_SHADER_VERTEX;
6834
6835 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6836
6837 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6838 ac_setup_rings(&ctx);
6839
6840 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6841 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6842
6843 struct ac_nir_context nir_ctx = {};
6844 nir_ctx.ac = ctx.ac;
6845 nir_ctx.abi = &ctx.abi;
6846
6847 nir_ctx.nctx = &ctx;
6848 ctx.nir = &nir_ctx;
6849
6850 nir_foreach_variable(variable, &geom_shader->outputs) {
6851 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6852 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6853 }
6854
6855 ac_gs_copy_shader_emit(&ctx);
6856
6857 ctx.nir = NULL;
6858
6859 LLVMBuildRetVoid(ctx.builder);
6860
6861 ac_llvm_finalize_module(&ctx);
6862
6863 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6864 MESA_SHADER_VERTEX,
6865 dump_shader, options->supports_spill);
6866 }