projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
amd/common: bump the number of available user SGPRS to 32 on GFX9
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.loads_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
604 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
605
606 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
607 user_sgpr_info->sgpr_count += 2;
608 user_sgpr_info->indirect_all_descriptor_sets = true;
609 } else {
610 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
611 }
612 }
613
614 static void
615 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 const struct user_sgpr_info *user_sgpr_info,
620 struct arg_info *args,
621 LLVMValueRef *desc_sets)
622 {
623 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
624 unsigned num_sets = ctx->options->layout ?
625 ctx->options->layout->num_sets : 0;
626 unsigned stage_mask = 1 << stage;
627
628 if (has_previous_stage)
629 stage_mask |= 1 << previous_stage;
630
631 /* 1 for each descriptor set */
632 if (!user_sgpr_info->indirect_all_descriptor_sets) {
633 for (unsigned i = 0; i < num_sets; ++i) {
634 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
635 add_array_arg(args, type,
636 &ctx->descriptor_sets[i]);
637 }
638 }
639 } else {
640 add_array_arg(args, const_array(type, 32), desc_sets);
641 }
642
643 if (ctx->shader_info->info.loads_push_constants) {
644 /* 1 for push constants and dynamic descriptors */
645 add_array_arg(args, type, &ctx->push_constants);
646 }
647 }
648
649 static void
650 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
651 gl_shader_stage stage,
652 bool has_previous_stage,
653 gl_shader_stage previous_stage,
654 struct arg_info *args)
655 {
656 if (!ctx->is_gs_copy_shader &&
657 (stage == MESA_SHADER_VERTEX ||
658 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
659 if (ctx->shader_info->info.vs.has_vertex_buffers) {
660 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
661 &ctx->vertex_buffers);
662 }
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
665 if (ctx->shader_info->info.vs.needs_draw_id) {
666 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
667 }
668 }
669 }
670
671 static void
672 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
675 if (!ctx->is_gs_copy_shader) {
676 if (ctx->options->key.vs.as_ls) {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 } else {
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
682 }
683 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
684 }
685 }
686
687 static void
688 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
689 {
690 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
691 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
692 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
693 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
694 }
695
696 static void
697 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
698 bool has_previous_stage, gl_shader_stage previous_stage,
699 const struct user_sgpr_info *user_sgpr_info,
700 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
701 {
702 unsigned num_sets = ctx->options->layout ?
703 ctx->options->layout->num_sets : 0;
704 unsigned stage_mask = 1 << stage;
705
706 if (has_previous_stage)
707 stage_mask |= 1 << previous_stage;
708
709 if (!user_sgpr_info->indirect_all_descriptor_sets) {
710 for (unsigned i = 0; i < num_sets; ++i) {
711 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
712 set_loc_desc(ctx, i, user_sgpr_idx, 0);
713 } else
714 ctx->descriptor_sets[i] = NULL;
715 }
716 } else {
717 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
718 user_sgpr_idx, 2);
719
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
722 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
723 ctx->descriptor_sets[i] =
724 ac_build_load_to_sgpr(&ctx->ac,
725 desc_sets,
726 LLVMConstInt(ctx->ac.i32, i, false));
727
728 } else
729 ctx->descriptor_sets[i] = NULL;
730 }
731 ctx->shader_info->need_indirect_descriptor_sets = true;
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
736 }
737 }
738
739 static void
740 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
741 gl_shader_stage stage, bool has_previous_stage,
742 gl_shader_stage previous_stage,
743 uint8_t *user_sgpr_idx)
744 {
745 if (!ctx->is_gs_copy_shader &&
746 (stage == MESA_SHADER_VERTEX ||
747 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
748 if (ctx->shader_info->info.vs.has_vertex_buffers) {
749 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
750 user_sgpr_idx, 2);
751 }
752
753 unsigned vs_num = 2;
754 if (ctx->shader_info->info.vs.needs_draw_id)
755 vs_num++;
756
757 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
758 user_sgpr_idx, vs_num);
759 }
760 }
761
762 static void create_function(struct nir_to_llvm_context *ctx,
763 gl_shader_stage stage,
764 bool has_previous_stage,
765 gl_shader_stage previous_stage)
766 {
767 uint8_t user_sgpr_idx;
768 struct user_sgpr_info user_sgpr_info;
769 struct arg_info args = {};
770 LLVMValueRef desc_sets;
771
772 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
773
774 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
775 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
776 &ctx->ring_offsets);
777 }
778
779 switch (stage) {
780 case MESA_SHADER_COMPUTE:
781 declare_global_input_sgprs(ctx, stage, has_previous_stage,
782 previous_stage, &user_sgpr_info,
783 &args, &desc_sets);
784
785 if (ctx->shader_info->info.cs.uses_grid_size) {
786 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
787 &ctx->num_work_groups);
788 }
789
790 for (int i = 0; i < 3; i++) {
791 ctx->workgroup_ids[i] = NULL;
792 if (ctx->shader_info->info.cs.uses_block_id[i]) {
793 add_arg(&args, ARG_SGPR, ctx->ac.i32,
794 &ctx->workgroup_ids[i]);
795 }
796 }
797
798 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
799 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
800 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
801 &ctx->local_invocation_ids);
802 break;
803 case MESA_SHADER_VERTEX:
804 declare_global_input_sgprs(ctx, stage, has_previous_stage,
805 previous_stage, &user_sgpr_info,
806 &args, &desc_sets);
807 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
808 previous_stage, &args);
809
810 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
812 if (ctx->options->key.vs.as_es)
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->es2gs_offset);
815 else if (ctx->options->key.vs.as_ls)
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->ls_out_layout);
818
819 declare_vs_input_vgprs(ctx, &args);
820 break;
821 case MESA_SHADER_TESS_CTRL:
822 if (has_previous_stage) {
823 // First 6 system regs
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->merged_wave_info);
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tess_factor_offset);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
831 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
832 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
833
834 declare_global_input_sgprs(ctx, stage,
835 has_previous_stage,
836 previous_stage,
837 &user_sgpr_info, &args,
838 &desc_sets);
839 declare_vs_specific_input_sgprs(ctx, stage,
840 has_previous_stage,
841 previous_stage, &args);
842
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->ls_out_layout);
845
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_offchip_layout);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_offsets);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_out_layout);
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_in_layout);
854 if (ctx->shader_info->info.needs_multiview_view_index)
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->view_index);
857
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_patch_id);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_rel_ids);
862
863 declare_vs_input_vgprs(ctx, &args);
864 } else {
865 declare_global_input_sgprs(ctx, stage,
866 has_previous_stage,
867 previous_stage,
868 &user_sgpr_info, &args,
869 &desc_sets);
870
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_offchip_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_offsets);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_out_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_in_layout);
879 if (ctx->shader_info->info.needs_multiview_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->view_index);
882
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->tess_factor_offset);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_patch_id);
888 add_arg(&args, ARG_VGPR, ctx->ac.i32,
889 &ctx->abi.tcs_rel_ids);
890 }
891 break;
892 case MESA_SHADER_TESS_EVAL:
893 declare_global_input_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, &user_sgpr_info,
895 &args, &desc_sets);
896
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
898 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
900
901 if (ctx->options->key.tes.as_es) {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->es2gs_offset);
906 } else {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
909 }
910 declare_tes_input_vgprs(ctx, &args);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 if (has_previous_stage) {
914 // First 6 system regs
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->gs2vs_offset);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->merged_wave_info);
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
920
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
924
925 declare_global_input_sgprs(ctx, stage,
926 has_previous_stage,
927 previous_stage,
928 &user_sgpr_info, &args,
929 &desc_sets);
930
931 if (previous_stage == MESA_SHADER_TESS_EVAL) {
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->tcs_offchip_layout);
934 } else {
935 declare_vs_specific_input_sgprs(ctx, stage,
936 has_previous_stage,
937 previous_stage,
938 &args);
939 }
940
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_ring_stride);
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->gsvs_num_entries);
945 if (ctx->shader_info->info.needs_multiview_view_index)
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->view_index);
948
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[0]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[2]);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_prim_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.gs_invocation_id);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32,
958 &ctx->gs_vtx_offset[4]);
959
960 if (previous_stage == MESA_SHADER_VERTEX) {
961 declare_vs_input_vgprs(ctx, &args);
962 } else {
963 declare_tes_input_vgprs(ctx, &args);
964 }
965 } else {
966 declare_global_input_sgprs(ctx, stage,
967 has_previous_stage,
968 previous_stage,
969 &user_sgpr_info, &args,
970 &desc_sets);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_ring_stride);
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->gsvs_num_entries);
976 if (ctx->shader_info->info.needs_multiview_view_index)
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->view_index);
979
980 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[0]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[1]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->abi.gs_prim_id);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[2]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[3]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[4]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->gs_vtx_offset[5]);
996 add_arg(&args, ARG_VGPR, ctx->ac.i32,
997 &ctx->abi.gs_invocation_id);
998 }
999 break;
1000 case MESA_SHADER_FRAGMENT:
1001 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1002 previous_stage, &user_sgpr_info,
1003 &args, &desc_sets);
1004
1005 if (ctx->shader_info->info.ps.needs_sample_positions)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->sample_pos_offset);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1016 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1026 break;
1027 default:
1028 unreachable("Shader stage not implemented");
1029 }
1030
1031 ctx->main_function = create_llvm_function(
1032 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1033 ctx->max_workgroup_size,
1034 ctx->options->unsafe_math);
1035 set_llvm_calling_convention(ctx->main_function, stage);
1036
1037
1038 ctx->shader_info->num_input_vgprs = 0;
1039 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1040
1041 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1042
1043 if (ctx->stage != MESA_SHADER_FRAGMENT)
1044 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1045
1046 assign_arguments(ctx->main_function, &args);
1047
1048 user_sgpr_idx = 0;
1049
1050 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1051 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1052 &user_sgpr_idx, 2);
1053 if (ctx->options->supports_spill) {
1054 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1055 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1056 NULL, 0, AC_FUNC_ATTR_READNONE);
1057 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1058 const_array(ctx->ac.v4i32, 16), "");
1059 }
1060 }
1061
1062 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1063 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1064 if (has_previous_stage)
1065 user_sgpr_idx = 0;
1066
1067 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1068 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1069
1070 switch (stage) {
1071 case MESA_SHADER_COMPUTE:
1072 if (ctx->shader_info->info.cs.uses_grid_size) {
1073 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1074 &user_sgpr_idx, 3);
1075 }
1076 break;
1077 case MESA_SHADER_VERTEX:
1078 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1079 previous_stage, &user_sgpr_idx);
1080 if (ctx->view_index)
1081 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1082 if (ctx->options->key.vs.as_ls) {
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 }
1086 if (ctx->options->key.vs.as_ls)
1087 ac_declare_lds_as_pointer(&ctx->ac);
1088 break;
1089 case MESA_SHADER_TESS_CTRL:
1090 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1091 previous_stage, &user_sgpr_idx);
1092 if (has_previous_stage)
1093 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1094 &user_sgpr_idx, 1);
1095 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 ac_declare_lds_as_pointer(&ctx->ac);
1099 break;
1100 case MESA_SHADER_TESS_EVAL:
1101 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1102 if (ctx->view_index)
1103 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1104 break;
1105 case MESA_SHADER_GEOMETRY:
1106 if (has_previous_stage) {
1107 if (previous_stage == MESA_SHADER_VERTEX)
1108 set_vs_specific_input_locs(ctx, stage,
1109 has_previous_stage,
1110 previous_stage,
1111 &user_sgpr_idx);
1112 else
1113 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1114 &user_sgpr_idx, 1);
1115 }
1116 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1117 &user_sgpr_idx, 2);
1118 if (ctx->view_index)
1119 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1120 if (has_previous_stage)
1121 ac_declare_lds_as_pointer(&ctx->ac);
1122 break;
1123 case MESA_SHADER_FRAGMENT:
1124 if (ctx->shader_info->info.ps.needs_sample_positions) {
1125 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1126 &user_sgpr_idx, 1);
1127 }
1128 break;
1129 default:
1130 unreachable("Shader stage not implemented");
1131 }
1132
1133 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1134 }
1135
1136 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1137 LLVMValueRef value, unsigned count)
1138 {
1139 unsigned num_components = ac_get_llvm_num_components(value);
1140 if (count == num_components)
1141 return value;
1142
1143 LLVMValueRef masks[] = {
1144 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1145 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1146
1147 if (count == 1)
1148 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1149 "");
1150
1151 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1152 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1153 }
1154
1155 static void
1156 build_store_values_extended(struct ac_llvm_context *ac,
1157 LLVMValueRef *values,
1158 unsigned value_count,
1159 unsigned value_stride,
1160 LLVMValueRef vec)
1161 {
1162 LLVMBuilderRef builder = ac->builder;
1163 unsigned i;
1164
1165 for (i = 0; i < value_count; i++) {
1166 LLVMValueRef ptr = values[i * value_stride];
1167 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1168 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1169 LLVMBuildStore(builder, value, ptr);
1170 }
1171 }
1172
1173 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1174 const nir_ssa_def *def)
1175 {
1176 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1177 if (def->num_components > 1) {
1178 type = LLVMVectorType(type, def->num_components);
1179 }
1180 return type;
1181 }
1182
1183 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1184 {
1185 assert(src.is_ssa);
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1187 return (LLVMValueRef)entry->data;
1188 }
1189
1190
1191 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1192 const struct nir_block *b)
1193 {
1194 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1195 return (LLVMBasicBlockRef)entry->data;
1196 }
1197
1198 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1199 nir_alu_src src,
1200 unsigned num_components)
1201 {
1202 LLVMValueRef value = get_src(ctx, src.src);
1203 bool need_swizzle = false;
1204
1205 assert(value);
1206 LLVMTypeRef type = LLVMTypeOf(value);
1207 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1208 ? LLVMGetVectorSize(type)
1209 : 1;
1210
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1321 }
1322
1323 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1324 LLVMIntPredicate pred,
1325 LLVMValueRef src0, LLVMValueRef src1)
1326 {
1327 return LLVMBuildSelect(ctx->builder,
1328 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1329 src0,
1330 src1, "");
1331
1332 }
1333 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1337 LLVMBuildNeg(ctx->builder, src0, ""));
1338 }
1339
1340 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0)
1342 {
1343 LLVMValueRef cmp, val;
1344
1345 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1346 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1347 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1348 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1349 return val;
1350 }
1351
1352 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1353 LLVMValueRef src0)
1354 {
1355 LLVMValueRef cmp, val;
1356
1357 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1359 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1360 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1361 return val;
1362 }
1363
1364 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0)
1366 {
1367 const char *intr = "llvm.floor.f32";
1368 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1369 LLVMValueRef params[] = {
1370 fsrc0,
1371 };
1372 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1373 ctx->f32, params, 1,
1374 AC_FUNC_ATTR_READNONE);
1375 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1376 }
1377
1378 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1379 const char *intrin,
1380 LLVMValueRef src0, LLVMValueRef src1)
1381 {
1382 LLVMTypeRef ret_type;
1383 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1384 LLVMValueRef res;
1385 LLVMValueRef params[] = { src0, src1 };
1386 ret_type = LLVMStructTypeInContext(ctx->context, types,
1387 2, true);
1388
1389 res = ac_build_intrinsic(ctx, intrin, ret_type,
1390 params, 2, AC_FUNC_ATTR_READNONE);
1391
1392 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1393 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1394 return res;
1395 }
1396
1397 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0)
1399 {
1400 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1401 }
1402
1403 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 src0 = ac_to_float(ctx, src0);
1407 return LLVMBuildSExt(ctx->builder,
1408 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1409 ctx->i32, "");
1410 }
1411
1412 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1416 }
1417
1418 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1419 LLVMValueRef src0)
1420 {
1421 return LLVMBuildSExt(ctx->builder,
1422 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1423 ctx->i32, "");
1424 }
1425
1426 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef result;
1430 LLVMValueRef cond = NULL;
1431
1432 src0 = ac_to_float(&ctx->ac, src0);
1433 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1434
1435 if (ctx->options->chip_class >= VI) {
1436 LLVMValueRef args[2];
1437 /* Check if the result is a denormal - and flush to 0 if so. */
1438 args[0] = result;
1439 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1440 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1441 }
1442
1443 /* need to convert back up to f32 */
1444 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1445
1446 if (ctx->options->chip_class >= VI)
1447 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1448 else {
1449 /* for SI/CIK */
1450 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1451 * so compare the result and flush to 0 if it's smaller.
1452 */
1453 LLVMValueRef temp, cond2;
1454 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1455 ctx->ac.f32, result);
1456 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1457 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1458 temp, "");
1459 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1460 temp, ctx->ac.f32_0, "");
1461 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1462 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1463 }
1464 return result;
1465 }
1466
1467 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1468 LLVMValueRef src0, LLVMValueRef src1)
1469 {
1470 LLVMValueRef dst64, result;
1471 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1472 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1473
1474 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1475 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1476 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1477 return result;
1478 }
1479
1480 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1481 LLVMValueRef src0, LLVMValueRef src1)
1482 {
1483 LLVMValueRef dst64, result;
1484 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1485 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1486
1487 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1488 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1489 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1490 return result;
1491 }
1492
1493 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1494 bool is_signed,
1495 const LLVMValueRef srcs[3])
1496 {
1497 LLVMValueRef result;
1498 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1499
1500 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1501 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1502 return result;
1503 }
1504
1505 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1506 LLVMValueRef src0, LLVMValueRef src1,
1507 LLVMValueRef src2, LLVMValueRef src3)
1508 {
1509 LLVMValueRef bfi_args[3], result;
1510
1511 bfi_args[0] = LLVMBuildShl(ctx->builder,
1512 LLVMBuildSub(ctx->builder,
1513 LLVMBuildShl(ctx->builder,
1514 ctx->i32_1,
1515 src3, ""),
1516 ctx->i32_1, ""),
1517 src2, "");
1518 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1519 bfi_args[2] = src0;
1520
1521 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1522
1523 /* Calculate:
1524 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1525 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1526 */
1527 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1528 LLVMBuildAnd(ctx->builder, bfi_args[0],
1529 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1530
1531 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1536 LLVMValueRef src0)
1537 {
1538 LLVMValueRef comp[2];
1539
1540 src0 = ac_to_float(ctx, src0);
1541 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1542 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1543
1544 return ac_build_cvt_pkrtz_f16(ctx, comp);
1545 }
1546
1547 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0)
1549 {
1550 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1551 LLVMValueRef temps[2], result, val;
1552 int i;
1553
1554 for (i = 0; i < 2; i++) {
1555 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1556 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1557 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1558 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1559 }
1560
1561 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1562 ctx->i32_0, "");
1563 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1564 ctx->i32_1, "");
1565 return result;
1566 }
1567
1568 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1569 nir_op op,
1570 LLVMValueRef src0)
1571 {
1572 unsigned mask;
1573 int idx;
1574 LLVMValueRef result;
1575
1576 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1577 mask = AC_TID_MASK_LEFT;
1578 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1579 mask = AC_TID_MASK_TOP;
1580 else
1581 mask = AC_TID_MASK_TOP_LEFT;
1582
1583 /* for DDX we want to next X pixel, DDY next Y pixel. */
1584 if (op == nir_op_fddx_fine ||
1585 op == nir_op_fddx_coarse ||
1586 op == nir_op_fddx)
1587 idx = 1;
1588 else
1589 idx = 2;
1590
1591 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1592 return result;
1593 }
1594
1595 /*
1596 * this takes an I,J coordinate pair,
1597 * and works out the X and Y derivatives.
1598 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1599 */
1600 static LLVMValueRef emit_ddxy_interp(
1601 struct ac_nir_context *ctx,
1602 LLVMValueRef interp_ij)
1603 {
1604 LLVMValueRef result[4], a;
1605 unsigned i;
1606
1607 for (i = 0; i < 2; i++) {
1608 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1609 LLVMConstInt(ctx->ac.i32, i, false), "");
1610 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1611 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1612 }
1613 return ac_build_gather_values(&ctx->ac, result, 4);
1614 }
1615
1616 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1617 {
1618 LLVMValueRef src[4], result = NULL;
1619 unsigned num_components = instr->dest.dest.ssa.num_components;
1620 unsigned src_components;
1621 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1622
1623 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1624 switch (instr->op) {
1625 case nir_op_vec2:
1626 case nir_op_vec3:
1627 case nir_op_vec4:
1628 src_components = 1;
1629 break;
1630 case nir_op_pack_half_2x16:
1631 src_components = 2;
1632 break;
1633 case nir_op_unpack_half_2x16:
1634 src_components = 1;
1635 break;
1636 default:
1637 src_components = num_components;
1638 break;
1639 }
1640 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1641 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1642
1643 switch (instr->op) {
1644 case nir_op_fmov:
1645 case nir_op_imov:
1646 result = src[0];
1647 break;
1648 case nir_op_fneg:
1649 src[0] = ac_to_float(&ctx->ac, src[0]);
1650 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1651 break;
1652 case nir_op_ineg:
1653 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1654 break;
1655 case nir_op_inot:
1656 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1657 break;
1658 case nir_op_iadd:
1659 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1660 break;
1661 case nir_op_fadd:
1662 src[0] = ac_to_float(&ctx->ac, src[0]);
1663 src[1] = ac_to_float(&ctx->ac, src[1]);
1664 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1665 break;
1666 case nir_op_fsub:
1667 src[0] = ac_to_float(&ctx->ac, src[0]);
1668 src[1] = ac_to_float(&ctx->ac, src[1]);
1669 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_isub:
1672 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_imul:
1675 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_imod:
1678 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1679 break;
1680 case nir_op_umod:
1681 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1682 break;
1683 case nir_op_fmod:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 src[1] = ac_to_float(&ctx->ac, src[1]);
1686 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1687 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1688 ac_to_float_type(&ctx->ac, def_type), result);
1689 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1690 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1691 break;
1692 case nir_op_frem:
1693 src[0] = ac_to_float(&ctx->ac, src[0]);
1694 src[1] = ac_to_float(&ctx->ac, src[1]);
1695 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_irem:
1698 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_idiv:
1701 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_udiv:
1704 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_fmul:
1707 src[0] = ac_to_float(&ctx->ac, src[0]);
1708 src[1] = ac_to_float(&ctx->ac, src[1]);
1709 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_fdiv:
1712 src[0] = ac_to_float(&ctx->ac, src[0]);
1713 src[1] = ac_to_float(&ctx->ac, src[1]);
1714 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1715 break;
1716 case nir_op_frcp:
1717 src[0] = ac_to_float(&ctx->ac, src[0]);
1718 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1719 break;
1720 case nir_op_iand:
1721 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1722 break;
1723 case nir_op_ior:
1724 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_ixor:
1727 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_ishl:
1730 result = LLVMBuildShl(ctx->ac.builder, src[0],
1731 LLVMBuildZExt(ctx->ac.builder, src[1],
1732 LLVMTypeOf(src[0]), ""),
1733 "");
1734 break;
1735 case nir_op_ishr:
1736 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1737 LLVMBuildZExt(ctx->ac.builder, src[1],
1738 LLVMTypeOf(src[0]), ""),
1739 "");
1740 break;
1741 case nir_op_ushr:
1742 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1743 LLVMBuildZExt(ctx->ac.builder, src[1],
1744 LLVMTypeOf(src[0]), ""),
1745 "");
1746 break;
1747 case nir_op_ilt:
1748 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1749 break;
1750 case nir_op_ine:
1751 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1752 break;
1753 case nir_op_ieq:
1754 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1755 break;
1756 case nir_op_ige:
1757 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1758 break;
1759 case nir_op_ult:
1760 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1761 break;
1762 case nir_op_uge:
1763 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1764 break;
1765 case nir_op_feq:
1766 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1767 break;
1768 case nir_op_fne:
1769 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1770 break;
1771 case nir_op_flt:
1772 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1773 break;
1774 case nir_op_fge:
1775 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1776 break;
1777 case nir_op_fabs:
1778 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1779 ac_to_float_type(&ctx->ac, def_type), src[0]);
1780 break;
1781 case nir_op_iabs:
1782 result = emit_iabs(&ctx->ac, src[0]);
1783 break;
1784 case nir_op_imax:
1785 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1786 break;
1787 case nir_op_imin:
1788 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1789 break;
1790 case nir_op_umax:
1791 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1792 break;
1793 case nir_op_umin:
1794 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1795 break;
1796 case nir_op_isign:
1797 result = emit_isign(&ctx->ac, src[0]);
1798 break;
1799 case nir_op_fsign:
1800 src[0] = ac_to_float(&ctx->ac, src[0]);
1801 result = emit_fsign(&ctx->ac, src[0]);
1802 break;
1803 case nir_op_ffloor:
1804 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1805 ac_to_float_type(&ctx->ac, def_type), src[0]);
1806 break;
1807 case nir_op_ftrunc:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1809 ac_to_float_type(&ctx->ac, def_type), src[0]);
1810 break;
1811 case nir_op_fceil:
1812 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1813 ac_to_float_type(&ctx->ac, def_type), src[0]);
1814 break;
1815 case nir_op_fround_even:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1817 ac_to_float_type(&ctx->ac, def_type),src[0]);
1818 break;
1819 case nir_op_ffract:
1820 result = emit_ffract(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_fsin:
1823 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1824 ac_to_float_type(&ctx->ac, def_type), src[0]);
1825 break;
1826 case nir_op_fcos:
1827 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1828 ac_to_float_type(&ctx->ac, def_type), src[0]);
1829 break;
1830 case nir_op_fsqrt:
1831 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1832 ac_to_float_type(&ctx->ac, def_type), src[0]);
1833 break;
1834 case nir_op_fexp2:
1835 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1836 ac_to_float_type(&ctx->ac, def_type), src[0]);
1837 break;
1838 case nir_op_flog2:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_frsq:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1846 break;
1847 case nir_op_fpow:
1848 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1849 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1850 break;
1851 case nir_op_fmax:
1852 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1853 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1854 if (instr->dest.dest.ssa.bit_size == 32)
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1856 ac_to_float_type(&ctx->ac, def_type),
1857 result);
1858 break;
1859 case nir_op_fmin:
1860 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1861 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1862 if (instr->dest.dest.ssa.bit_size == 32)
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1864 ac_to_float_type(&ctx->ac, def_type),
1865 result);
1866 break;
1867 case nir_op_ffma:
1868 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1869 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1870 break;
1871 case nir_op_ibitfield_extract:
1872 result = emit_bitfield_extract(&ctx->ac, true, src);
1873 break;
1874 case nir_op_ubitfield_extract:
1875 result = emit_bitfield_extract(&ctx->ac, false, src);
1876 break;
1877 case nir_op_bitfield_insert:
1878 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1879 break;
1880 case nir_op_bitfield_reverse:
1881 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1882 break;
1883 case nir_op_bit_count:
1884 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1885 break;
1886 case nir_op_vec2:
1887 case nir_op_vec3:
1888 case nir_op_vec4:
1889 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1890 src[i] = ac_to_integer(&ctx->ac, src[i]);
1891 result = ac_build_gather_values(&ctx->ac, src, num_components);
1892 break;
1893 case nir_op_f2i32:
1894 case nir_op_f2i64:
1895 src[0] = ac_to_float(&ctx->ac, src[0]);
1896 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1897 break;
1898 case nir_op_f2u32:
1899 case nir_op_f2u64:
1900 src[0] = ac_to_float(&ctx->ac, src[0]);
1901 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1902 break;
1903 case nir_op_i2f32:
1904 case nir_op_i2f64:
1905 src[0] = ac_to_integer(&ctx->ac, src[0]);
1906 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1907 break;
1908 case nir_op_u2f32:
1909 case nir_op_u2f64:
1910 src[0] = ac_to_integer(&ctx->ac, src[0]);
1911 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1912 break;
1913 case nir_op_f2f64:
1914 src[0] = ac_to_float(&ctx->ac, src[0]);
1915 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1916 break;
1917 case nir_op_f2f32:
1918 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1919 break;
1920 case nir_op_u2u32:
1921 case nir_op_u2u64:
1922 src[0] = ac_to_integer(&ctx->ac, src[0]);
1923 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1924 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1925 else
1926 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1927 break;
1928 case nir_op_i2i32:
1929 case nir_op_i2i64:
1930 src[0] = ac_to_integer(&ctx->ac, src[0]);
1931 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1932 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1933 else
1934 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1935 break;
1936 case nir_op_bcsel:
1937 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1938 break;
1939 case nir_op_find_lsb:
1940 src[0] = ac_to_integer(&ctx->ac, src[0]);
1941 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1942 break;
1943 case nir_op_ufind_msb:
1944 src[0] = ac_to_integer(&ctx->ac, src[0]);
1945 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1946 break;
1947 case nir_op_ifind_msb:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1950 break;
1951 case nir_op_uadd_carry:
1952 src[0] = ac_to_integer(&ctx->ac, src[0]);
1953 src[1] = ac_to_integer(&ctx->ac, src[1]);
1954 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1955 break;
1956 case nir_op_usub_borrow:
1957 src[0] = ac_to_integer(&ctx->ac, src[0]);
1958 src[1] = ac_to_integer(&ctx->ac, src[1]);
1959 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1960 break;
1961 case nir_op_b2f:
1962 result = emit_b2f(&ctx->ac, src[0]);
1963 break;
1964 case nir_op_f2b:
1965 result = emit_f2b(&ctx->ac, src[0]);
1966 break;
1967 case nir_op_b2i:
1968 result = emit_b2i(&ctx->ac, src[0]);
1969 break;
1970 case nir_op_i2b:
1971 src[0] = ac_to_integer(&ctx->ac, src[0]);
1972 result = emit_i2b(&ctx->ac, src[0]);
1973 break;
1974 case nir_op_fquantize2f16:
1975 result = emit_f2f16(ctx->nctx, src[0]);
1976 break;
1977 case nir_op_umul_high:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 src[1] = ac_to_integer(&ctx->ac, src[1]);
1980 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1981 break;
1982 case nir_op_imul_high:
1983 src[0] = ac_to_integer(&ctx->ac, src[0]);
1984 src[1] = ac_to_integer(&ctx->ac, src[1]);
1985 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1986 break;
1987 case nir_op_pack_half_2x16:
1988 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_unpack_half_2x16:
1991 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1992 break;
1993 case nir_op_fddx:
1994 case nir_op_fddy:
1995 case nir_op_fddx_fine:
1996 case nir_op_fddy_fine:
1997 case nir_op_fddx_coarse:
1998 case nir_op_fddy_coarse:
1999 result = emit_ddxy(ctx, instr->op, src[0]);
2000 break;
2001
2002 case nir_op_unpack_64_2x32_split_x: {
2003 assert(instr->src[0].src.ssa->num_components == 1);
2004 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2005 ctx->ac.v2i32,
2006 "");
2007 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2008 ctx->ac.i32_0, "");
2009 break;
2010 }
2011
2012 case nir_op_unpack_64_2x32_split_y: {
2013 assert(instr->src[0].src.ssa->num_components == 1);
2014 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2015 ctx->ac.v2i32,
2016 "");
2017 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2018 ctx->ac.i32_1, "");
2019 break;
2020 }
2021
2022 case nir_op_pack_64_2x32_split: {
2023 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2024 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2025 src[0], ctx->ac.i32_0, "");
2026 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2027 src[1], ctx->ac.i32_1, "");
2028 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2029 break;
2030 }
2031
2032 default:
2033 fprintf(stderr, "Unknown NIR alu instr: ");
2034 nir_print_instr(&instr->instr, stderr);
2035 fprintf(stderr, "\n");
2036 abort();
2037 }
2038
2039 if (result) {
2040 assert(instr->dest.dest.is_ssa);
2041 result = ac_to_integer(&ctx->ac, result);
2042 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2043 result);
2044 }
2045 }
2046
2047 static void visit_load_const(struct ac_nir_context *ctx,
2048 const nir_load_const_instr *instr)
2049 {
2050 LLVMValueRef values[4], value = NULL;
2051 LLVMTypeRef element_type =
2052 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2053
2054 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2055 switch (instr->def.bit_size) {
2056 case 32:
2057 values[i] = LLVMConstInt(element_type,
2058 instr->value.u32[i], false);
2059 break;
2060 case 64:
2061 values[i] = LLVMConstInt(element_type,
2062 instr->value.u64[i], false);
2063 break;
2064 default:
2065 fprintf(stderr,
2066 "unsupported nir load_const bit_size: %d\n",
2067 instr->def.bit_size);
2068 abort();
2069 }
2070 }
2071 if (instr->def.num_components > 1) {
2072 value = LLVMConstVector(values, instr->def.num_components);
2073 } else
2074 value = values[0];
2075
2076 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2077 }
2078
2079 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2080 LLVMTypeRef type)
2081 {
2082 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2083 return LLVMBuildBitCast(ctx->builder, ptr,
2084 LLVMPointerType(type, addr_space), "");
2085 }
2086
2087 static LLVMValueRef
2088 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2089 {
2090 LLVMValueRef size =
2091 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2092 LLVMConstInt(ctx->ac.i32, 2, false), "");
2093
2094 /* VI only */
2095 if (ctx->ac.chip_class == VI && in_elements) {
2096 /* On VI, the descriptor contains the size in bytes,
2097 * but TXQ must return the size in elements.
2098 * The stride is always non-zero for resources using TXQ.
2099 */
2100 LLVMValueRef stride =
2101 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2102 ctx->ac.i32_1, "");
2103 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2104 LLVMConstInt(ctx->ac.i32, 16, false), "");
2105 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2106 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2107
2108 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2109 }
2110 return size;
2111 }
2112
2113 /**
2114 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2115 * intrinsic names).
2116 */
2117 static void build_int_type_name(
2118 LLVMTypeRef type,
2119 char *buf, unsigned bufsize)
2120 {
2121 assert(bufsize >= 6);
2122
2123 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2124 snprintf(buf, bufsize, "v%ui32",
2125 LLVMGetVectorSize(type));
2126 else
2127 strcpy(buf, "i32");
2128 }
2129
2130 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2131 struct ac_image_args *args,
2132 const nir_tex_instr *instr)
2133 {
2134 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2135 LLVMValueRef coord = args->addr;
2136 LLVMValueRef half_texel[2];
2137 LLVMValueRef compare_cube_wa = NULL;
2138 LLVMValueRef result;
2139 int c;
2140 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2141
2142 //TODO Rect
2143 {
2144 struct ac_image_args txq_args = { 0 };
2145
2146 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2147 txq_args.opcode = ac_image_get_resinfo;
2148 txq_args.dmask = 0xf;
2149 txq_args.addr = ctx->i32_0;
2150 txq_args.resource = args->resource;
2151 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2152
2153 for (c = 0; c < 2; c++) {
2154 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2155 LLVMConstInt(ctx->i32, c, false), "");
2156 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2157 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2158 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2159 LLVMConstReal(ctx->f32, -0.5), "");
2160 }
2161 }
2162
2163 LLVMValueRef orig_coords = args->addr;
2164
2165 for (c = 0; c < 2; c++) {
2166 LLVMValueRef tmp;
2167 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2168 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2169 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2170 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2171 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2172 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2173 }
2174
2175
2176 /*
2177 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2178 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2179 * workaround by sampling using a scaled type and converting.
2180 * This is taken from amdgpu-pro shaders.
2181 */
2182 /* NOTE this produces some ugly code compared to amdgpu-pro,
2183 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2184 * and then reads them back. -pro generates two selects,
2185 * one s_cmp for the descriptor rewriting
2186 * one v_cmp for the coordinate and result changes.
2187 */
2188 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2189 LLVMValueRef tmp, tmp2;
2190
2191 /* workaround 8/8/8/8 uint/sint cube gather bug */
2192 /* first detect it then change to a scaled read and f2i */
2193 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2194 tmp2 = tmp;
2195
2196 /* extract the DATA_FORMAT */
2197 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2198 LLVMConstInt(ctx->i32, 6, false), false);
2199
2200 /* is the DATA_FORMAT == 8_8_8_8 */
2201 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2202
2203 if (stype == GLSL_TYPE_UINT)
2204 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2205 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2206 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2207 else
2208 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2209 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2210 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2211
2212 /* replace the NUM FORMAT in the descriptor */
2213 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2214 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2215
2216 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2217
2218 /* don't modify the coordinates for this case */
2219 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2220 }
2221 args->addr = coord;
2222 result = ac_build_image_opcode(ctx, args);
2223
2224 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2225 LLVMValueRef tmp, tmp2;
2226
2227 /* if the cube workaround is in place, f2i the result. */
2228 for (c = 0; c < 4; c++) {
2229 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2230 if (stype == GLSL_TYPE_UINT)
2231 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2232 else
2233 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2234 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2235 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2236 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2237 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2238 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2239 }
2240 }
2241 return result;
2242 }
2243
2244 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2245 const nir_tex_instr *instr,
2246 bool lod_is_zero,
2247 struct ac_image_args *args)
2248 {
2249 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2250 return ac_build_buffer_load_format(&ctx->ac,
2251 args->resource,
2252 args->addr,
2253 ctx->ac.i32_0,
2254 true);
2255 }
2256
2257 args->opcode = ac_image_sample;
2258 args->compare = instr->is_shadow;
2259
2260 switch (instr->op) {
2261 case nir_texop_txf:
2262 case nir_texop_txf_ms:
2263 case nir_texop_samples_identical:
2264 args->opcode = lod_is_zero ||
2265 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2266 ac_image_load : ac_image_load_mip;
2267 args->compare = false;
2268 args->offset = false;
2269 break;
2270 case nir_texop_txb:
2271 args->bias = true;
2272 break;
2273 case nir_texop_txl:
2274 if (lod_is_zero)
2275 args->level_zero = true;
2276 else
2277 args->lod = true;
2278 break;
2279 case nir_texop_txs:
2280 case nir_texop_query_levels:
2281 args->opcode = ac_image_get_resinfo;
2282 break;
2283 case nir_texop_tex:
2284 if (ctx->stage != MESA_SHADER_FRAGMENT)
2285 args->level_zero = true;
2286 break;
2287 case nir_texop_txd:
2288 args->deriv = true;
2289 break;
2290 case nir_texop_tg4:
2291 args->opcode = ac_image_gather4;
2292 args->level_zero = true;
2293 break;
2294 case nir_texop_lod:
2295 args->opcode = ac_image_get_lod;
2296 args->compare = false;
2297 args->offset = false;
2298 break;
2299 default:
2300 break;
2301 }
2302
2303 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2304 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2305 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2306 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2307 }
2308 }
2309 return ac_build_image_opcode(&ctx->ac, args);
2310 }
2311
2312 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2313 nir_intrinsic_instr *instr)
2314 {
2315 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2316 unsigned desc_set = nir_intrinsic_desc_set(instr);
2317 unsigned binding = nir_intrinsic_binding(instr);
2318 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2319 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2320 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2321 unsigned base_offset = layout->binding[binding].offset;
2322 LLVMValueRef offset, stride;
2323
2324 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2325 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2326 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2327 layout->binding[binding].dynamic_offset_offset;
2328 desc_ptr = ctx->push_constants;
2329 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2330 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2331 } else
2332 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2333
2334 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2335 index = LLVMBuildMul(ctx->builder, index, stride, "");
2336 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2337
2338 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2339 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2340 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2341
2342 return desc_ptr;
2343 }
2344
2345 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2346 nir_intrinsic_instr *instr)
2347 {
2348 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2349 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2350
2351 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2352 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2353 return result;
2354 }
2355
2356 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2357 nir_intrinsic_instr *instr)
2358 {
2359 LLVMValueRef ptr, addr;
2360
2361 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2362 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2363
2364 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2365 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2366
2367 return LLVMBuildLoad(ctx->builder, ptr, "");
2368 }
2369
2370 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2371 const nir_intrinsic_instr *instr)
2372 {
2373 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2374
2375 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2376 }
2377 static void visit_store_ssbo(struct ac_nir_context *ctx,
2378 nir_intrinsic_instr *instr)
2379 {
2380 const char *store_name;
2381 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2382 LLVMTypeRef data_type = ctx->ac.f32;
2383 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2384 int components_32bit = elem_size_mult * instr->num_components;
2385 unsigned writemask = nir_intrinsic_write_mask(instr);
2386 LLVMValueRef base_data, base_offset;
2387 LLVMValueRef params[6];
2388
2389 params[1] = ctx->abi->load_ssbo(ctx->abi,
2390 get_src(ctx, instr->src[1]), true);
2391 params[2] = ctx->ac.i32_0; /* vindex */
2392 params[4] = ctx->ac.i1false; /* glc */
2393 params[5] = ctx->ac.i1false; /* slc */
2394
2395 if (components_32bit > 1)
2396 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2397
2398 base_data = ac_to_float(&ctx->ac, src_data);
2399 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2400 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2401 data_type, "");
2402 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2403 while (writemask) {
2404 int start, count;
2405 LLVMValueRef data;
2406 LLVMValueRef offset;
2407 LLVMValueRef tmp;
2408 u_bit_scan_consecutive_range(&writemask, &start, &count);
2409
2410 /* Due to an LLVM limitation, split 3-element writes
2411 * into a 2-element and a 1-element write. */
2412 if (count == 3) {
2413 writemask |= 1 << (start + 2);
2414 count = 2;
2415 }
2416
2417 start *= elem_size_mult;
2418 count *= elem_size_mult;
2419
2420 if (count > 4) {
2421 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2422 count = 4;
2423 }
2424
2425 if (count == 4) {
2426 store_name = "llvm.amdgcn.buffer.store.v4f32";
2427 data = base_data;
2428 } else if (count == 2) {
2429 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2430 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2431 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2432 ctx->ac.i32_0, "");
2433
2434 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2435 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2436 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2437 ctx->ac.i32_1, "");
2438 store_name = "llvm.amdgcn.buffer.store.v2f32";
2439
2440 } else {
2441 assert(count == 1);
2442 if (ac_get_llvm_num_components(base_data) > 1)
2443 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2444 LLVMConstInt(ctx->ac.i32, start, false), "");
2445 else
2446 data = base_data;
2447 store_name = "llvm.amdgcn.buffer.store.f32";
2448 }
2449
2450 offset = base_offset;
2451 if (start != 0) {
2452 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2453 }
2454 params[0] = data;
2455 params[3] = offset;
2456 ac_build_intrinsic(&ctx->ac, store_name,
2457 ctx->ac.voidt, params, 6, 0);
2458 }
2459 }
2460
2461 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2462 const nir_intrinsic_instr *instr)
2463 {
2464 const char *name;
2465 LLVMValueRef params[6];
2466 int arg_count = 0;
2467
2468 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2469 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2470 }
2471 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2472 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2473 get_src(ctx, instr->src[0]),
2474 true);
2475 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2476 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2477 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2478
2479 switch (instr->intrinsic) {
2480 case nir_intrinsic_ssbo_atomic_add:
2481 name = "llvm.amdgcn.buffer.atomic.add";
2482 break;
2483 case nir_intrinsic_ssbo_atomic_imin:
2484 name = "llvm.amdgcn.buffer.atomic.smin";
2485 break;
2486 case nir_intrinsic_ssbo_atomic_umin:
2487 name = "llvm.amdgcn.buffer.atomic.umin";
2488 break;
2489 case nir_intrinsic_ssbo_atomic_imax:
2490 name = "llvm.amdgcn.buffer.atomic.smax";
2491 break;
2492 case nir_intrinsic_ssbo_atomic_umax:
2493 name = "llvm.amdgcn.buffer.atomic.umax";
2494 break;
2495 case nir_intrinsic_ssbo_atomic_and:
2496 name = "llvm.amdgcn.buffer.atomic.and";
2497 break;
2498 case nir_intrinsic_ssbo_atomic_or:
2499 name = "llvm.amdgcn.buffer.atomic.or";
2500 break;
2501 case nir_intrinsic_ssbo_atomic_xor:
2502 name = "llvm.amdgcn.buffer.atomic.xor";
2503 break;
2504 case nir_intrinsic_ssbo_atomic_exchange:
2505 name = "llvm.amdgcn.buffer.atomic.swap";
2506 break;
2507 case nir_intrinsic_ssbo_atomic_comp_swap:
2508 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2509 break;
2510 default:
2511 abort();
2512 }
2513
2514 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2515 }
2516
2517 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2518 const nir_intrinsic_instr *instr)
2519 {
2520 LLVMValueRef results[2];
2521 int load_components;
2522 int num_components = instr->num_components;
2523 if (instr->dest.ssa.bit_size == 64)
2524 num_components *= 2;
2525
2526 for (int i = 0; i < num_components; i += load_components) {
2527 load_components = MIN2(num_components - i, 4);
2528 const char *load_name;
2529 LLVMTypeRef data_type = ctx->ac.f32;
2530 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2531 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2532
2533 if (load_components == 3)
2534 data_type = LLVMVectorType(ctx->ac.f32, 4);
2535 else if (load_components > 1)
2536 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2537
2538 if (load_components >= 3)
2539 load_name = "llvm.amdgcn.buffer.load.v4f32";
2540 else if (load_components == 2)
2541 load_name = "llvm.amdgcn.buffer.load.v2f32";
2542 else if (load_components == 1)
2543 load_name = "llvm.amdgcn.buffer.load.f32";
2544 else
2545 unreachable("unhandled number of components");
2546
2547 LLVMValueRef params[] = {
2548 ctx->abi->load_ssbo(ctx->abi,
2549 get_src(ctx, instr->src[0]),
2550 false),
2551 ctx->ac.i32_0,
2552 offset,
2553 ctx->ac.i1false,
2554 ctx->ac.i1false,
2555 };
2556
2557 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2558
2559 }
2560
2561 assume(results[0]);
2562 LLVMValueRef ret = results[0];
2563 if (num_components > 4 || num_components == 3) {
2564 LLVMValueRef masks[] = {
2565 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2566 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2567 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2568 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2569 };
2570
2571 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2572 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2573 results[num_components > 4 ? 1 : 0], swizzle, "");
2574 }
2575
2576 return LLVMBuildBitCast(ctx->ac.builder, ret,
2577 get_def_type(ctx, &instr->dest.ssa), "");
2578 }
2579
2580 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2581 const nir_intrinsic_instr *instr)
2582 {
2583 LLVMValueRef results[8], ret;
2584 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2585 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2586 int num_components = instr->num_components;
2587
2588 if (ctx->abi->load_ubo)
2589 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2590
2591 if (instr->dest.ssa.bit_size == 64)
2592 num_components *= 2;
2593
2594 for (unsigned i = 0; i < num_components; ++i) {
2595 LLVMValueRef params[] = {
2596 rsrc,
2597 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2598 offset, "")
2599 };
2600 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2601 params, 2,
2602 AC_FUNC_ATTR_READNONE |
2603 AC_FUNC_ATTR_LEGACY);
2604 }
2605
2606
2607 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2608 return LLVMBuildBitCast(ctx->ac.builder, ret,
2609 get_def_type(ctx, &instr->dest.ssa), "");
2610 }
2611
2612 static void
2613 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2614 bool vs_in, unsigned *vertex_index_out,
2615 LLVMValueRef *vertex_index_ref,
2616 unsigned *const_out, LLVMValueRef *indir_out)
2617 {
2618 unsigned const_offset = 0;
2619 nir_deref *tail = &deref->deref;
2620 LLVMValueRef offset = NULL;
2621
2622 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2623 tail = tail->child;
2624 nir_deref_array *deref_array = nir_deref_as_array(tail);
2625 if (vertex_index_out)
2626 *vertex_index_out = deref_array->base_offset;
2627
2628 if (vertex_index_ref) {
2629 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2630 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2631 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2632 }
2633 *vertex_index_ref = vtx;
2634 }
2635 }
2636
2637 if (deref->var->data.compact) {
2638 assert(tail->child->deref_type == nir_deref_type_array);
2639 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2640 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2641 /* We always lower indirect dereferences for "compact" array vars. */
2642 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2643
2644 const_offset = deref_array->base_offset;
2645 goto out;
2646 }
2647
2648 while (tail->child != NULL) {
2649 const struct glsl_type *parent_type = tail->type;
2650 tail = tail->child;
2651
2652 if (tail->deref_type == nir_deref_type_array) {
2653 nir_deref_array *deref_array = nir_deref_as_array(tail);
2654 LLVMValueRef index, stride, local_offset;
2655 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2656
2657 const_offset += size * deref_array->base_offset;
2658 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2659 continue;
2660
2661 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2662 index = get_src(ctx, deref_array->indirect);
2663 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2664 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2665
2666 if (offset)
2667 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2668 else
2669 offset = local_offset;
2670 } else if (tail->deref_type == nir_deref_type_struct) {
2671 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2672
2673 for (unsigned i = 0; i < deref_struct->index; i++) {
2674 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2675 const_offset += glsl_count_attribute_slots(ft, vs_in);
2676 }
2677 } else
2678 unreachable("unsupported deref type");
2679
2680 }
2681 out:
2682 if (const_offset && offset)
2683 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2684 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2685 "");
2686
2687 *const_out = const_offset;
2688 *indir_out = offset;
2689 }
2690
2691
2692 /* The offchip buffer layout for TCS->TES is
2693 *
2694 * - attribute 0 of patch 0 vertex 0
2695 * - attribute 0 of patch 0 vertex 1
2696 * - attribute 0 of patch 0 vertex 2
2697 * ...
2698 * - attribute 0 of patch 1 vertex 0
2699 * - attribute 0 of patch 1 vertex 1
2700 * ...
2701 * - attribute 1 of patch 0 vertex 0
2702 * - attribute 1 of patch 0 vertex 1
2703 * ...
2704 * - per patch attribute 0 of patch 0
2705 * - per patch attribute 0 of patch 1
2706 * ...
2707 *
2708 * Note that every attribute has 4 components.
2709 */
2710 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2711 LLVMValueRef vertex_index,
2712 LLVMValueRef param_index)
2713 {
2714 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2715 LLVMValueRef param_stride, constant16;
2716 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2717
2718 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2719 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2720 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2721 num_patches, "");
2722
2723 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2724 if (vertex_index) {
2725 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2726 vertices_per_patch, "");
2727
2728 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2729 vertex_index, "");
2730
2731 param_stride = total_vertices;
2732 } else {
2733 base_addr = rel_patch_id;
2734 param_stride = num_patches;
2735 }
2736
2737 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2738 LLVMBuildMul(ctx->builder, param_index,
2739 param_stride, ""), "");
2740
2741 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2742
2743 if (!vertex_index) {
2744 LLVMValueRef patch_data_offset =
2745 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2746
2747 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2748 patch_data_offset, "");
2749 }
2750 return base_addr;
2751 }
2752
2753 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2754 unsigned param,
2755 unsigned const_index,
2756 bool is_compact,
2757 LLVMValueRef vertex_index,
2758 LLVMValueRef indir_index)
2759 {
2760 LLVMValueRef param_index;
2761
2762 if (indir_index)
2763 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2764 indir_index, "");
2765 else {
2766 if (const_index && !is_compact)
2767 param += const_index;
2768 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2769 }
2770 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2771 }
2772
2773 static void
2774 mark_tess_output(struct nir_to_llvm_context *ctx,
2775 bool is_patch, uint32_t param)
2776
2777 {
2778 if (is_patch) {
2779 ctx->tess_patch_outputs_written |= (1ull << param);
2780 } else
2781 ctx->tess_outputs_written |= (1ull << param);
2782 }
2783
2784 static LLVMValueRef
2785 get_dw_address(struct nir_to_llvm_context *ctx,
2786 LLVMValueRef dw_addr,
2787 unsigned param,
2788 unsigned const_index,
2789 bool compact_const_index,
2790 LLVMValueRef vertex_index,
2791 LLVMValueRef stride,
2792 LLVMValueRef indir_index)
2793
2794 {
2795
2796 if (vertex_index) {
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 LLVMBuildMul(ctx->builder,
2799 vertex_index,
2800 stride, ""), "");
2801 }
2802
2803 if (indir_index)
2804 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2805 LLVMBuildMul(ctx->builder, indir_index,
2806 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2807 else if (const_index && !compact_const_index)
2808 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2809 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2810
2811 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2812 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2813
2814 if (const_index && compact_const_index)
2815 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2816 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2817 return dw_addr;
2818 }
2819
2820 static LLVMValueRef
2821 load_tcs_input(struct ac_shader_abi *abi,
2822 LLVMValueRef vertex_index,
2823 LLVMValueRef indir_index,
2824 unsigned const_index,
2825 unsigned location,
2826 unsigned driver_location,
2827 unsigned component,
2828 unsigned num_components,
2829 bool is_patch,
2830 bool is_compact)
2831 {
2832 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2833 LLVMValueRef dw_addr, stride;
2834 LLVMValueRef value[4], result;
2835 unsigned param = shader_io_get_unique_index(location);
2836
2837 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2838 dw_addr = get_tcs_in_current_patch_offset(ctx);
2839 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2840 indir_index);
2841
2842 for (unsigned i = 0; i < num_components + component; i++) {
2843 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2844 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2845 ctx->ac.i32_1, "");
2846 }
2847 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2848 return result;
2849 }
2850
2851 static LLVMValueRef
2852 load_tcs_output(struct nir_to_llvm_context *ctx,
2853 nir_intrinsic_instr *instr)
2854 {
2855 LLVMValueRef dw_addr;
2856 LLVMValueRef stride = NULL;
2857 LLVMValueRef value[4], result;
2858 LLVMValueRef vertex_index = NULL;
2859 LLVMValueRef indir_index = NULL;
2860 unsigned const_index = 0;
2861 unsigned param;
2862 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2863 const bool is_compact = instr->variables[0]->var->data.compact;
2864 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2865 get_deref_offset(ctx->nir, instr->variables[0],
2866 false, NULL, per_vertex ? &vertex_index : NULL,
2867 &const_index, &indir_index);
2868
2869 if (!instr->variables[0]->var->data.patch) {
2870 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2871 dw_addr = get_tcs_out_current_patch_offset(ctx);
2872 } else {
2873 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2874 }
2875
2876 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2877 indir_index);
2878
2879 unsigned comp = instr->variables[0]->var->data.location_frac;
2880 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2881 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2882 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2883 ctx->ac.i32_1, "");
2884 }
2885 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2886 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2887 return result;
2888 }
2889
2890 static void
2891 store_tcs_output(struct ac_shader_abi *abi,
2892 LLVMValueRef vertex_index,
2893 LLVMValueRef param_index,
2894 unsigned const_index,
2895 unsigned location,
2896 unsigned driver_location,
2897 LLVMValueRef src,
2898 unsigned component,
2899 bool is_patch,
2900 bool is_compact,
2901 unsigned writemask)
2902 {
2903 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2904 LLVMValueRef dw_addr;
2905 LLVMValueRef stride = NULL;
2906 LLVMValueRef buf_addr = NULL;
2907 unsigned param;
2908 bool store_lds = true;
2909
2910 if (is_patch) {
2911 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2912 store_lds = false;
2913 } else {
2914 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2915 store_lds = false;
2916 }
2917
2918 param = shader_io_get_unique_index(location);
2919 if (location == VARYING_SLOT_CLIP_DIST0 &&
2920 is_compact && const_index > 3) {
2921 const_index -= 3;
2922 param++;
2923 }
2924
2925 if (!is_patch) {
2926 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2927 dw_addr = get_tcs_out_current_patch_offset(ctx);
2928 } else {
2929 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2930 }
2931
2932 mark_tess_output(ctx, is_patch, param);
2933
2934 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2935 param_index);
2936 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2937 vertex_index, param_index);
2938
2939 bool is_tess_factor = false;
2940 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2941 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2942 is_tess_factor = true;
2943
2944 unsigned base = is_compact ? const_index : 0;
2945 for (unsigned chan = 0; chan < 8; chan++) {
2946 if (!(writemask & (1 << chan)))
2947 continue;
2948 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2949
2950 if (store_lds || is_tess_factor)
2951 ac_lds_store(&ctx->ac, dw_addr, value);
2952
2953 if (!is_tess_factor && writemask != 0xF)
2954 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2955 buf_addr, ctx->oc_lds,
2956 4 * (base + chan), 1, 0, true, false);
2957
2958 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2959 ctx->ac.i32_1, "");
2960 }
2961
2962 if (writemask == 0xF) {
2963 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2964 buf_addr, ctx->oc_lds,
2965 (base * 4), 1, 0, true, false);
2966 }
2967 }
2968
2969 static LLVMValueRef
2970 load_tes_input(struct ac_shader_abi *abi,
2971 LLVMValueRef vertex_index,
2972 LLVMValueRef param_index,
2973 unsigned const_index,
2974 unsigned location,
2975 unsigned driver_location,
2976 unsigned component,
2977 unsigned num_components,
2978 bool is_patch,
2979 bool is_compact)
2980 {
2981 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2982 LLVMValueRef buf_addr;
2983 LLVMValueRef result;
2984 unsigned param = shader_io_get_unique_index(location);
2985
2986 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2987 const_index -= 3;
2988 param++;
2989 }
2990
2991 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2992 is_compact, vertex_index, param_index);
2993
2994 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2995 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2996
2997 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2998 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2999 result = trim_vector(&ctx->ac, result, num_components);
3000 return result;
3001 }
3002
3003 static LLVMValueRef
3004 load_gs_input(struct ac_shader_abi *abi,
3005 unsigned location,
3006 unsigned driver_location,
3007 unsigned component,
3008 unsigned num_components,
3009 unsigned vertex_index,
3010 unsigned const_index,
3011 LLVMTypeRef type)
3012 {
3013 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3014 LLVMValueRef vtx_offset;
3015 LLVMValueRef args[9];
3016 unsigned param, vtx_offset_param;
3017 LLVMValueRef value[4], result;
3018
3019 vtx_offset_param = vertex_index;
3020 assert(vtx_offset_param < 6);
3021 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3022 LLVMConstInt(ctx->ac.i32, 4, false), "");
3023
3024 param = shader_io_get_unique_index(location);
3025
3026 for (unsigned i = component; i < num_components + component; i++) {
3027 if (ctx->ac.chip_class >= GFX9) {
3028 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3029 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3030 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3031 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3032 } else {
3033 args[0] = ctx->esgs_ring;
3034 args[1] = vtx_offset;
3035 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3036 args[3] = ctx->ac.i32_0;
3037 args[4] = ctx->ac.i32_1; /* OFFEN */
3038 args[5] = ctx->ac.i32_0; /* IDXEN */
3039 args[6] = ctx->ac.i32_1; /* GLC */
3040 args[7] = ctx->ac.i32_0; /* SLC */
3041 args[8] = ctx->ac.i32_0; /* TFE */
3042
3043 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3044 ctx->ac.i32, args, 9,
3045 AC_FUNC_ATTR_READONLY |
3046 AC_FUNC_ATTR_LEGACY);
3047 }
3048 }
3049 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3050
3051 return result;
3052 }
3053
3054 static LLVMValueRef
3055 build_gep_for_deref(struct ac_nir_context *ctx,
3056 nir_deref_var *deref)
3057 {
3058 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3059 assert(entry->data);
3060 LLVMValueRef val = entry->data;
3061 nir_deref *tail = deref->deref.child;
3062 while (tail != NULL) {
3063 LLVMValueRef offset;
3064 switch (tail->deref_type) {
3065 case nir_deref_type_array: {
3066 nir_deref_array *array = nir_deref_as_array(tail);
3067 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3068 if (array->deref_array_type ==
3069 nir_deref_array_type_indirect) {
3070 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3071 get_src(ctx,
3072 array->indirect),
3073 "");
3074 }
3075 break;
3076 }
3077 case nir_deref_type_struct: {
3078 nir_deref_struct *deref_struct =
3079 nir_deref_as_struct(tail);
3080 offset = LLVMConstInt(ctx->ac.i32,
3081 deref_struct->index, 0);
3082 break;
3083 }
3084 default:
3085 unreachable("bad deref type");
3086 }
3087 val = ac_build_gep0(&ctx->ac, val, offset);
3088 tail = tail->child;
3089 }
3090 return val;
3091 }
3092
3093 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3094 nir_intrinsic_instr *instr)
3095 {
3096 LLVMValueRef values[8];
3097 int idx = instr->variables[0]->var->data.driver_location;
3098 int ve = instr->dest.ssa.num_components;
3099 unsigned comp = instr->variables[0]->var->data.location_frac;
3100 LLVMValueRef indir_index;
3101 LLVMValueRef ret;
3102 unsigned const_index;
3103 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3104 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3105 instr->variables[0]->var->data.mode == nir_var_shader_in;
3106 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3107 &const_index, &indir_index);
3108
3109 if (instr->dest.ssa.bit_size == 64)
3110 ve *= 2;
3111
3112 switch (instr->variables[0]->var->data.mode) {
3113 case nir_var_shader_in:
3114 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3115 ctx->stage == MESA_SHADER_TESS_EVAL) {
3116 LLVMValueRef result;
3117 LLVMValueRef vertex_index = NULL;
3118 LLVMValueRef indir_index = NULL;
3119 unsigned const_index = 0;
3120 unsigned location = instr->variables[0]->var->data.location;
3121 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3122 const bool is_patch = instr->variables[0]->var->data.patch;
3123 const bool is_compact = instr->variables[0]->var->data.compact;
3124
3125 get_deref_offset(ctx, instr->variables[0],
3126 false, NULL, is_patch ? NULL : &vertex_index,
3127 &const_index, &indir_index);
3128
3129 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3130 const_index, location, driver_location,
3131 instr->variables[0]->var->data.location_frac,
3132 instr->num_components,
3133 is_patch, is_compact);
3134 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3135 }
3136
3137 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3138 LLVMValueRef indir_index;
3139 unsigned const_index, vertex_index;
3140 get_deref_offset(ctx, instr->variables[0],
3141 false, &vertex_index, NULL,
3142 &const_index, &indir_index);
3143 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3144 instr->variables[0]->var->data.driver_location,
3145 instr->variables[0]->var->data.location_frac, ve,
3146 vertex_index, const_index,
3147 nir2llvmtype(ctx, instr->variables[0]->var->type));
3148 }
3149
3150 for (unsigned chan = comp; chan < ve + comp; chan++) {
3151 if (indir_index) {
3152 unsigned count = glsl_count_attribute_slots(
3153 instr->variables[0]->var->type,
3154 ctx->stage == MESA_SHADER_VERTEX);
3155 count -= chan / 4;
3156 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3157 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3158 stride, false, true);
3159
3160 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3161 tmp_vec,
3162 indir_index, "");
3163 } else
3164 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3165 }
3166 break;
3167 case nir_var_local:
3168 for (unsigned chan = 0; chan < ve; chan++) {
3169 if (indir_index) {
3170 unsigned count = glsl_count_attribute_slots(
3171 instr->variables[0]->var->type, false);
3172 count -= chan / 4;
3173 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3174 &ctx->ac, ctx->locals + idx + chan, count,
3175 stride, true, true);
3176
3177 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3178 tmp_vec,
3179 indir_index, "");
3180 } else {
3181 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3182 }
3183 }
3184 break;
3185 case nir_var_shared: {
3186 LLVMValueRef address = build_gep_for_deref(ctx,
3187 instr->variables[0]);
3188 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3189 return LLVMBuildBitCast(ctx->ac.builder, val,
3190 get_def_type(ctx, &instr->dest.ssa),
3191 "");
3192 }
3193 case nir_var_shader_out:
3194 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3195 return load_tcs_output(ctx->nctx, instr);
3196
3197 for (unsigned chan = comp; chan < ve + comp; chan++) {
3198 if (indir_index) {
3199 unsigned count = glsl_count_attribute_slots(
3200 instr->variables[0]->var->type, false);
3201 count -= chan / 4;
3202 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3203 &ctx->ac, ctx->outputs + idx + chan, count,
3204 stride, true, true);
3205
3206 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3207 tmp_vec,
3208 indir_index, "");
3209 } else {
3210 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3211 ctx->outputs[idx + chan + const_index * stride],
3212 "");
3213 }
3214 }
3215 break;
3216 default:
3217 unreachable("unhandle variable mode");
3218 }
3219 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3220 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3221 }
3222
3223 static void
3224 visit_store_var(struct ac_nir_context *ctx,
3225 nir_intrinsic_instr *instr)
3226 {
3227 LLVMValueRef temp_ptr, value;
3228 int idx = instr->variables[0]->var->data.driver_location;
3229 unsigned comp = instr->variables[0]->var->data.location_frac;
3230 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3231 int writemask = instr->const_index[0] << comp;
3232 LLVMValueRef indir_index;
3233 unsigned const_index;
3234 get_deref_offset(ctx, instr->variables[0], false,
3235 NULL, NULL, &const_index, &indir_index);
3236
3237 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3238 int old_writemask = writemask;
3239
3240 src = LLVMBuildBitCast(ctx->ac.builder, src,
3241 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3242 "");
3243
3244 writemask = 0;
3245 for (unsigned chan = 0; chan < 4; chan++) {
3246 if (old_writemask & (1 << chan))
3247 writemask |= 3u << (2 * chan);
3248 }
3249 }
3250
3251 switch (instr->variables[0]->var->data.mode) {
3252 case nir_var_shader_out:
3253
3254 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3255 LLVMValueRef vertex_index = NULL;
3256 LLVMValueRef indir_index = NULL;
3257 unsigned const_index = 0;
3258 const unsigned location = instr->variables[0]->var->data.location;
3259 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3260 const unsigned comp = instr->variables[0]->var->data.location_frac;
3261 const bool is_patch = instr->variables[0]->var->data.patch;
3262 const bool is_compact = instr->variables[0]->var->data.compact;
3263
3264 get_deref_offset(ctx, instr->variables[0],
3265 false, NULL, is_patch ? NULL : &vertex_index,
3266 &const_index, &indir_index);
3267
3268 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3269 const_index, location, driver_location,
3270 src, comp, is_patch, is_compact, writemask);
3271 return;
3272 }
3273
3274 for (unsigned chan = 0; chan < 8; chan++) {
3275 int stride = 4;
3276 if (!(writemask & (1 << chan)))
3277 continue;
3278
3279 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3280
3281 if (instr->variables[0]->var->data.compact)
3282 stride = 1;
3283 if (indir_index) {
3284 unsigned count = glsl_count_attribute_slots(
3285 instr->variables[0]->var->type, false);
3286 count -= chan / 4;
3287 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3288 &ctx->ac, ctx->outputs + idx + chan, count,
3289 stride, true, true);
3290
3291 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3292 value, indir_index, "");
3293 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3294 count, stride, tmp_vec);
3295
3296 } else {
3297 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3298
3299 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3300 }
3301 }
3302 break;
3303 case nir_var_local:
3304 for (unsigned chan = 0; chan < 8; chan++) {
3305 if (!(writemask & (1 << chan)))
3306 continue;
3307
3308 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3309 if (indir_index) {
3310 unsigned count = glsl_count_attribute_slots(
3311 instr->variables[0]->var->type, false);
3312 count -= chan / 4;
3313 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3314 &ctx->ac, ctx->locals + idx + chan, count,
3315 4, true, true);
3316
3317 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3318 value, indir_index, "");
3319 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3320 count, 4, tmp_vec);
3321 } else {
3322 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3323
3324 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3325 }
3326 }
3327 break;
3328 case nir_var_shared: {
3329 int writemask = instr->const_index[0];
3330 LLVMValueRef address = build_gep_for_deref(ctx,
3331 instr->variables[0]);
3332 LLVMValueRef val = get_src(ctx, instr->src[0]);
3333 unsigned components =
3334 glsl_get_vector_elements(
3335 nir_deref_tail(&instr->variables[0]->deref)->type);
3336 if (writemask == (1 << components) - 1) {
3337 val = LLVMBuildBitCast(
3338 ctx->ac.builder, val,
3339 LLVMGetElementType(LLVMTypeOf(address)), "");
3340 LLVMBuildStore(ctx->ac.builder, val, address);
3341 } else {
3342 for (unsigned chan = 0; chan < 4; chan++) {
3343 if (!(writemask & (1 << chan)))
3344 continue;
3345 LLVMValueRef ptr =
3346 LLVMBuildStructGEP(ctx->ac.builder,
3347 address, chan, "");
3348 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3349 chan);
3350 src = LLVMBuildBitCast(
3351 ctx->ac.builder, src,
3352 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3353 LLVMBuildStore(ctx->ac.builder, src, ptr);
3354 }
3355 }
3356 break;
3357 }
3358 default:
3359 break;
3360 }
3361 }
3362
3363 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3364 {
3365 switch (dim) {
3366 case GLSL_SAMPLER_DIM_BUF:
3367 return 1;
3368 case GLSL_SAMPLER_DIM_1D:
3369 return array ? 2 : 1;
3370 case GLSL_SAMPLER_DIM_2D:
3371 return array ? 3 : 2;
3372 case GLSL_SAMPLER_DIM_MS:
3373 return array ? 4 : 3;
3374 case GLSL_SAMPLER_DIM_3D:
3375 case GLSL_SAMPLER_DIM_CUBE:
3376 return 3;
3377 case GLSL_SAMPLER_DIM_RECT:
3378 case GLSL_SAMPLER_DIM_SUBPASS:
3379 return 2;
3380 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3381 return 3;
3382 default:
3383 break;
3384 }
3385 return 0;
3386 }
3387
3388
3389
3390 /* Adjust the sample index according to FMASK.
3391 *
3392 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3393 * which is the identity mapping. Each nibble says which physical sample
3394 * should be fetched to get that sample.
3395 *
3396 * For example, 0x11111100 means there are only 2 samples stored and
3397 * the second sample covers 3/4 of the pixel. When reading samples 0
3398 * and 1, return physical sample 0 (determined by the first two 0s
3399 * in FMASK), otherwise return physical sample 1.
3400 *
3401 * The sample index should be adjusted as follows:
3402 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3403 */
3404 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3405 LLVMValueRef coord_x, LLVMValueRef coord_y,
3406 LLVMValueRef coord_z,
3407 LLVMValueRef sample_index,
3408 LLVMValueRef fmask_desc_ptr)
3409 {
3410 LLVMValueRef fmask_load_address[4];
3411 LLVMValueRef res;
3412
3413 fmask_load_address[0] = coord_x;
3414 fmask_load_address[1] = coord_y;
3415 if (coord_z) {
3416 fmask_load_address[2] = coord_z;
3417 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3418 }
3419
3420 struct ac_image_args args = {0};
3421
3422 args.opcode = ac_image_load;
3423 args.da = coord_z ? true : false;
3424 args.resource = fmask_desc_ptr;
3425 args.dmask = 0xf;
3426 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3427
3428 res = ac_build_image_opcode(ctx, &args);
3429
3430 res = ac_to_integer(ctx, res);
3431 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3432 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3433
3434 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3435 res,
3436 ctx->i32_0, "");
3437
3438 LLVMValueRef sample_index4 =
3439 LLVMBuildMul(ctx->builder, sample_index, four, "");
3440 LLVMValueRef shifted_fmask =
3441 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3442 LLVMValueRef final_sample =
3443 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3444
3445 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3446 * resource descriptor is 0 (invalid),
3447 */
3448 LLVMValueRef fmask_desc =
3449 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3450 ctx->v8i32, "");
3451
3452 LLVMValueRef fmask_word1 =
3453 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3454 ctx->i32_1, "");
3455
3456 LLVMValueRef word1_is_nonzero =
3457 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3458 fmask_word1, ctx->i32_0, "");
3459
3460 /* Replace the MSAA sample index. */
3461 sample_index =
3462 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3463 final_sample, sample_index, "");
3464 return sample_index;
3465 }
3466
3467 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3468 const nir_intrinsic_instr *instr)
3469 {
3470 const struct glsl_type *type = instr->variables[0]->var->type;
3471 if(instr->variables[0]->deref.child)
3472 type = instr->variables[0]->deref.child->type;
3473
3474 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3475 LLVMValueRef coords[4];
3476 LLVMValueRef masks[] = {
3477 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3478 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3479 };
3480 LLVMValueRef res;
3481 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3482
3483 int count;
3484 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3485 bool is_array = glsl_sampler_type_is_array(type);
3486 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3487 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3488 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3489 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3490 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3491 count = image_type_to_components_count(dim, is_array);
3492
3493 if (is_ms) {
3494 LLVMValueRef fmask_load_address[3];
3495 int chan;
3496
3497 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3498 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3499 if (is_array)
3500 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3501 else
3502 fmask_load_address[2] = NULL;
3503 if (add_frag_pos) {
3504 for (chan = 0; chan < 2; ++chan)
3505 fmask_load_address[chan] =
3506 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3507 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3508 ctx->ac.i32, ""), "");
3509 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3510 }
3511 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3512 fmask_load_address[0],
3513 fmask_load_address[1],
3514 fmask_load_address[2],
3515 sample_index,
3516 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3517 }
3518 if (count == 1 && !gfx9_1d) {
3519 if (instr->src[0].ssa->num_components)
3520 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3521 else
3522 res = src0;
3523 } else {
3524 int chan;
3525 if (is_ms)
3526 count--;
3527 for (chan = 0; chan < count; ++chan) {
3528 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3529 }
3530 if (add_frag_pos) {
3531 for (chan = 0; chan < 2; ++chan)
3532 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3533 ctx->ac.i32, ""), "");
3534 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3535 count++;
3536 }
3537
3538 if (gfx9_1d) {
3539 if (is_array) {
3540 coords[2] = coords[1];
3541 coords[1] = ctx->ac.i32_0;
3542 } else
3543 coords[1] = ctx->ac.i32_0;
3544 count++;
3545 }
3546
3547 if (is_ms) {
3548 coords[count] = sample_index;
3549 count++;
3550 }
3551
3552 if (count == 3) {
3553 coords[3] = LLVMGetUndef(ctx->ac.i32);
3554 count = 4;
3555 }
3556 res = ac_build_gather_values(&ctx->ac, coords, count);
3557 }
3558 return res;
3559 }
3560
3561 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3562 const nir_intrinsic_instr *instr)
3563 {
3564 LLVMValueRef params[7];
3565 LLVMValueRef res;
3566 char intrinsic_name[64];
3567 const nir_variable *var = instr->variables[0]->var;
3568 const struct glsl_type *type = var->type;
3569
3570 if(instr->variables[0]->deref.child)
3571 type = instr->variables[0]->deref.child->type;
3572
3573 type = glsl_without_array(type);
3574 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3575 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3576 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3577 ctx->ac.i32_0, ""); /* vindex */
3578 params[2] = ctx->ac.i32_0; /* voffset */
3579 params[3] = ctx->ac.i1false; /* glc */
3580 params[4] = ctx->ac.i1false; /* slc */
3581 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3582 params, 5, 0);
3583
3584 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3585 res = ac_to_integer(&ctx->ac, res);
3586 } else {
3587 bool is_da = glsl_sampler_type_is_array(type) ||
3588 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3589 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3590 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3591 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3592 LLVMValueRef glc = ctx->ac.i1false;
3593 LLVMValueRef slc = ctx->ac.i1false;
3594
3595 params[0] = get_image_coords(ctx, instr);
3596 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3597 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3598 if (HAVE_LLVM <= 0x0309) {
3599 params[3] = ctx->ac.i1false; /* r128 */
3600 params[4] = da;
3601 params[5] = glc;
3602 params[6] = slc;
3603 } else {
3604 LLVMValueRef lwe = ctx->ac.i1false;
3605 params[3] = glc;
3606 params[4] = slc;
3607 params[5] = lwe;
3608 params[6] = da;
3609 }
3610
3611 ac_get_image_intr_name("llvm.amdgcn.image.load",
3612 ctx->ac.v4f32, /* vdata */
3613 LLVMTypeOf(params[0]), /* coords */
3614 LLVMTypeOf(params[1]), /* rsrc */
3615 intrinsic_name, sizeof(intrinsic_name));
3616
3617 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3618 params, 7, AC_FUNC_ATTR_READONLY);
3619 }
3620 return ac_to_integer(&ctx->ac, res);
3621 }
3622
3623 static void visit_image_store(struct ac_nir_context *ctx,
3624 nir_intrinsic_instr *instr)
3625 {
3626 LLVMValueRef params[8];
3627 char intrinsic_name[64];
3628 const nir_variable *var = instr->variables[0]->var;
3629 const struct glsl_type *type = glsl_without_array(var->type);
3630 LLVMValueRef glc = ctx->ac.i1false;
3631 bool force_glc = ctx->ac.chip_class == SI;
3632 if (force_glc)
3633 glc = ctx->ac.i1true;
3634
3635 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3636 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3637 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3638 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3639 ctx->ac.i32_0, ""); /* vindex */
3640 params[3] = ctx->ac.i32_0; /* voffset */
3641 params[4] = glc; /* glc */
3642 params[5] = ctx->ac.i1false; /* slc */
3643 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3644 params, 6, 0);
3645 } else {
3646 bool is_da = glsl_sampler_type_is_array(type) ||
3647 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3648 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3649 LLVMValueRef slc = ctx->ac.i1false;
3650
3651 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3652 params[1] = get_image_coords(ctx, instr); /* coords */
3653 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3654 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3655 if (HAVE_LLVM <= 0x0309) {
3656 params[4] = ctx->ac.i1false; /* r128 */
3657 params[5] = da;
3658 params[6] = glc;
3659 params[7] = slc;
3660 } else {
3661 LLVMValueRef lwe = ctx->ac.i1false;
3662 params[4] = glc;
3663 params[5] = slc;
3664 params[6] = lwe;
3665 params[7] = da;
3666 }
3667
3668 ac_get_image_intr_name("llvm.amdgcn.image.store",
3669 LLVMTypeOf(params[0]), /* vdata */
3670 LLVMTypeOf(params[1]), /* coords */
3671 LLVMTypeOf(params[2]), /* rsrc */
3672 intrinsic_name, sizeof(intrinsic_name));
3673
3674 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3675 params, 8, 0);
3676 }
3677
3678 }
3679
3680 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3681 const nir_intrinsic_instr *instr)
3682 {
3683 LLVMValueRef params[7];
3684 int param_count = 0;
3685 const nir_variable *var = instr->variables[0]->var;
3686
3687 const char *atomic_name;
3688 char intrinsic_name[41];
3689 const struct glsl_type *type = glsl_without_array(var->type);
3690 MAYBE_UNUSED int length;
3691
3692 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3693
3694 switch (instr->intrinsic) {
3695 case nir_intrinsic_image_atomic_add:
3696 atomic_name = "add";
3697 break;
3698 case nir_intrinsic_image_atomic_min:
3699 atomic_name = is_unsigned ? "umin" : "smin";
3700 break;
3701 case nir_intrinsic_image_atomic_max:
3702 atomic_name = is_unsigned ? "umax" : "smax";
3703 break;
3704 case nir_intrinsic_image_atomic_and:
3705 atomic_name = "and";
3706 break;
3707 case nir_intrinsic_image_atomic_or:
3708 atomic_name = "or";
3709 break;
3710 case nir_intrinsic_image_atomic_xor:
3711 atomic_name = "xor";
3712 break;
3713 case nir_intrinsic_image_atomic_exchange:
3714 atomic_name = "swap";
3715 break;
3716 case nir_intrinsic_image_atomic_comp_swap:
3717 atomic_name = "cmpswap";
3718 break;
3719 default:
3720 abort();
3721 }
3722
3723 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3724 params[param_count++] = get_src(ctx, instr->src[3]);
3725 params[param_count++] = get_src(ctx, instr->src[2]);
3726
3727 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3728 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3729 NULL, true, true);
3730 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3731 ctx->ac.i32_0, ""); /* vindex */
3732 params[param_count++] = ctx->ac.i32_0; /* voffset */
3733 params[param_count++] = ctx->ac.i1false; /* slc */
3734
3735 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3736 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3737 } else {
3738 char coords_type[8];
3739
3740 bool da = glsl_sampler_type_is_array(type) ||
3741 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3742
3743 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3744 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3745 NULL, true, true);
3746 params[param_count++] = ctx->ac.i1false; /* r128 */
3747 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3748 params[param_count++] = ctx->ac.i1false; /* slc */
3749
3750 build_int_type_name(LLVMTypeOf(coords),
3751 coords_type, sizeof(coords_type));
3752
3753 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3754 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3755 }
3756
3757 assert(length < sizeof(intrinsic_name));
3758 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3759 }
3760
3761 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3762 const nir_intrinsic_instr *instr)
3763 {
3764 LLVMValueRef res;
3765 const nir_variable *var = instr->variables[0]->var;
3766 const struct glsl_type *type = instr->variables[0]->var->type;
3767 bool da = glsl_sampler_type_is_array(var->type) ||
3768 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3769 if(instr->variables[0]->deref.child)
3770 type = instr->variables[0]->deref.child->type;
3771
3772 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3773 return get_buffer_size(ctx,
3774 get_sampler_desc(ctx, instr->variables[0],
3775 AC_DESC_BUFFER, NULL, true, false), true);
3776
3777 struct ac_image_args args = { 0 };
3778
3779 args.da = da;
3780 args.dmask = 0xf;
3781 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3782 args.opcode = ac_image_get_resinfo;
3783 args.addr = ctx->ac.i32_0;
3784
3785 res = ac_build_image_opcode(&ctx->ac, &args);
3786
3787 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3788
3789 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3790 glsl_sampler_type_is_array(type)) {
3791 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3792 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3793 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3794 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3795 }
3796 if (ctx->ac.chip_class >= GFX9 &&
3797 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3798 glsl_sampler_type_is_array(type)) {
3799 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3800 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3801 ctx->ac.i32_1, "");
3802
3803 }
3804 return res;
3805 }
3806
3807 #define NOOP_WAITCNT 0xf7f
3808 #define LGKM_CNT 0x07f
3809 #define VM_CNT 0xf70
3810
3811 static void emit_membar(struct nir_to_llvm_context *ctx,
3812 const nir_intrinsic_instr *instr)
3813 {
3814 unsigned waitcnt = NOOP_WAITCNT;
3815
3816 switch (instr->intrinsic) {
3817 case nir_intrinsic_memory_barrier:
3818 case nir_intrinsic_group_memory_barrier:
3819 waitcnt &= VM_CNT & LGKM_CNT;
3820 break;
3821 case nir_intrinsic_memory_barrier_atomic_counter:
3822 case nir_intrinsic_memory_barrier_buffer:
3823 case nir_intrinsic_memory_barrier_image:
3824 waitcnt &= VM_CNT;
3825 break;
3826 case nir_intrinsic_memory_barrier_shared:
3827 waitcnt &= LGKM_CNT;
3828 break;
3829 default:
3830 break;
3831 }
3832 if (waitcnt != NOOP_WAITCNT)
3833 ac_build_waitcnt(&ctx->ac, waitcnt);
3834 }
3835
3836 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3837 {
3838 /* SI only (thanks to a hw bug workaround):
3839 * The real barrier instruction isn’t needed, because an entire patch
3840 * always fits into a single wave.
3841 */
3842 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3843 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3844 return;
3845 }
3846 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3847 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3848 }
3849
3850 static void emit_discard_if(struct ac_nir_context *ctx,
3851 const nir_intrinsic_instr *instr)
3852 {
3853 LLVMValueRef cond;
3854
3855 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3856 get_src(ctx, instr->src[0]),
3857 ctx->ac.i32_0, "");
3858 ac_build_kill_if_false(&ctx->ac, cond);
3859 }
3860
3861 static LLVMValueRef
3862 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3863 {
3864 LLVMValueRef result;
3865 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3866 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3867 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3868
3869 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3870 }
3871
3872 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3873 const nir_intrinsic_instr *instr)
3874 {
3875 LLVMValueRef ptr, result;
3876 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3877 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3878
3879 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3880 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3881 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3882 ptr, src, src1,
3883 LLVMAtomicOrderingSequentiallyConsistent,
3884 LLVMAtomicOrderingSequentiallyConsistent,
3885 false);
3886 } else {
3887 LLVMAtomicRMWBinOp op;
3888 switch (instr->intrinsic) {
3889 case nir_intrinsic_var_atomic_add:
3890 op = LLVMAtomicRMWBinOpAdd;
3891 break;
3892 case nir_intrinsic_var_atomic_umin:
3893 op = LLVMAtomicRMWBinOpUMin;
3894 break;
3895 case nir_intrinsic_var_atomic_umax:
3896 op = LLVMAtomicRMWBinOpUMax;
3897 break;
3898 case nir_intrinsic_var_atomic_imin:
3899 op = LLVMAtomicRMWBinOpMin;
3900 break;
3901 case nir_intrinsic_var_atomic_imax:
3902 op = LLVMAtomicRMWBinOpMax;
3903 break;
3904 case nir_intrinsic_var_atomic_and:
3905 op = LLVMAtomicRMWBinOpAnd;
3906 break;
3907 case nir_intrinsic_var_atomic_or:
3908 op = LLVMAtomicRMWBinOpOr;
3909 break;
3910 case nir_intrinsic_var_atomic_xor:
3911 op = LLVMAtomicRMWBinOpXor;
3912 break;
3913 case nir_intrinsic_var_atomic_exchange:
3914 op = LLVMAtomicRMWBinOpXchg;
3915 break;
3916 default:
3917 return NULL;
3918 }
3919
3920 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3921 LLVMAtomicOrderingSequentiallyConsistent,
3922 false);
3923 }
3924 return result;
3925 }
3926
3927 #define INTERP_CENTER 0
3928 #define INTERP_CENTROID 1
3929 #define INTERP_SAMPLE 2
3930
3931 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3932 enum glsl_interp_mode interp, unsigned location)
3933 {
3934 switch (interp) {
3935 case INTERP_MODE_FLAT:
3936 default:
3937 return NULL;
3938 case INTERP_MODE_SMOOTH:
3939 case INTERP_MODE_NONE:
3940 if (location == INTERP_CENTER)
3941 return ctx->persp_center;
3942 else if (location == INTERP_CENTROID)
3943 return ctx->persp_centroid;
3944 else if (location == INTERP_SAMPLE)
3945 return ctx->persp_sample;
3946 break;
3947 case INTERP_MODE_NOPERSPECTIVE:
3948 if (location == INTERP_CENTER)
3949 return ctx->linear_center;
3950 else if (location == INTERP_CENTROID)
3951 return ctx->linear_centroid;
3952 else if (location == INTERP_SAMPLE)
3953 return ctx->linear_sample;
3954 break;
3955 }
3956 return NULL;
3957 }
3958
3959 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3960 LLVMValueRef sample_id)
3961 {
3962 LLVMValueRef result;
3963 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3964
3965 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3966 const_array(ctx->ac.v2f32, 64), "");
3967
3968 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3969 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3970
3971 return result;
3972 }
3973
3974 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3975 {
3976 LLVMValueRef values[2];
3977
3978 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3979 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3980 return ac_build_gather_values(&ctx->ac, values, 2);
3981 }
3982
3983 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3984 const nir_intrinsic_instr *instr)
3985 {
3986 LLVMValueRef result[4];
3987 LLVMValueRef interp_param, attr_number;
3988 unsigned location;
3989 unsigned chan;
3990 LLVMValueRef src_c0 = NULL;
3991 LLVMValueRef src_c1 = NULL;
3992 LLVMValueRef src0 = NULL;
3993 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3994 switch (instr->intrinsic) {
3995 case nir_intrinsic_interp_var_at_centroid:
3996 location = INTERP_CENTROID;
3997 break;
3998 case nir_intrinsic_interp_var_at_sample:
3999 case nir_intrinsic_interp_var_at_offset:
4000 location = INTERP_CENTER;
4001 src0 = get_src(ctx->nir, instr->src[0]);
4002 break;
4003 default:
4004 break;
4005 }
4006
4007 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4008 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4009 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4010 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4011 LLVMValueRef sample_position;
4012 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4013
4014 /* fetch sample ID */
4015 sample_position = load_sample_position(ctx, src0);
4016
4017 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4018 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4019 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4020 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4021 }
4022 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4023 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4024
4025 if (location == INTERP_CENTER) {
4026 LLVMValueRef ij_out[2];
4027 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4028
4029 /*
4030 * take the I then J parameters, and the DDX/Y for it, and
4031 * calculate the IJ inputs for the interpolator.
4032 * temp1 = ddx * offset/sample.x + I;
4033 * interp_param.I = ddy * offset/sample.y + temp1;
4034 * temp1 = ddx * offset/sample.x + J;
4035 * interp_param.J = ddy * offset/sample.y + temp1;
4036 */
4037 for (unsigned i = 0; i < 2; i++) {
4038 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4039 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4040 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4041 ddxy_out, ix_ll, "");
4042 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4043 ddxy_out, iy_ll, "");
4044 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4045 interp_param, ix_ll, "");
4046 LLVMValueRef temp1, temp2;
4047
4048 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4049 ctx->ac.f32, "");
4050
4051 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4052 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4053
4054 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4055 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4056
4057 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4058 temp2, ctx->ac.i32, "");
4059 }
4060 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4061
4062 }
4063
4064 for (chan = 0; chan < 4; chan++) {
4065 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4066
4067 if (interp_param) {
4068 interp_param = LLVMBuildBitCast(ctx->builder,
4069 interp_param, ctx->ac.v2f32, "");
4070 LLVMValueRef i = LLVMBuildExtractElement(
4071 ctx->builder, interp_param, ctx->ac.i32_0, "");
4072 LLVMValueRef j = LLVMBuildExtractElement(
4073 ctx->builder, interp_param, ctx->ac.i32_1, "");
4074
4075 result[chan] = ac_build_fs_interp(&ctx->ac,
4076 llvm_chan, attr_number,
4077 ctx->prim_mask, i, j);
4078 } else {
4079 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4080 LLVMConstInt(ctx->ac.i32, 2, false),
4081 llvm_chan, attr_number,
4082 ctx->prim_mask);
4083 }
4084 }
4085 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4086 instr->variables[0]->var->data.location_frac);
4087 }
4088
4089 static void
4090 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4091 {
4092 LLVMValueRef gs_next_vertex;
4093 LLVMValueRef can_emit;
4094 int idx;
4095 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4096
4097 /* Write vertex attribute values to GSVS ring */
4098 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4099 ctx->gs_next_vertex,
4100 "");
4101
4102 /* If this thread has already emitted the declared maximum number of
4103 * vertices, kill it: excessive vertex emissions are not supposed to
4104 * have any effect, and GS threads have no externally observable
4105 * effects other than emitting vertices.
4106 */
4107 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4108 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4109 ac_build_kill_if_false(&ctx->ac, can_emit);
4110
4111 /* loop num outputs */
4112 idx = 0;
4113 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4114 LLVMValueRef *out_ptr = &addrs[i * 4];
4115 int length = 4;
4116 int slot = idx;
4117 int slot_inc = 1;
4118
4119 if (!(ctx->output_mask & (1ull << i)))
4120 continue;
4121
4122 if (i == VARYING_SLOT_CLIP_DIST0) {
4123 /* pack clip and cull into a single set of slots */
4124 length = ctx->num_output_clips + ctx->num_output_culls;
4125 if (length > 4)
4126 slot_inc = 2;
4127 }
4128 for (unsigned j = 0; j < length; j++) {
4129 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4130 out_ptr[j], "");
4131 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4132 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4133 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4134
4135 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4136
4137 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4138 out_val, 1,
4139 voffset, ctx->gs2vs_offset, 0,
4140 1, 1, true, true);
4141 }
4142 idx += slot_inc;
4143 }
4144
4145 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4146 ctx->ac.i32_1, "");
4147 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4148
4149 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4150 }
4151
4152 static void
4153 visit_end_primitive(struct nir_to_llvm_context *ctx,
4154 const nir_intrinsic_instr *instr)
4155 {
4156 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4157 }
4158
4159 static LLVMValueRef
4160 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4161 unsigned num_components)
4162 {
4163 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4164
4165 LLVMValueRef coord[4] = {
4166 ctx->tes_u,
4167 ctx->tes_v,
4168 ctx->ac.f32_0,
4169 ctx->ac.f32_0,
4170 };
4171
4172 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4173 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4174 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4175
4176 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4177 return LLVMBuildBitCast(ctx->builder, result, type, "");
4178 }
4179
4180 static void visit_intrinsic(struct ac_nir_context *ctx,
4181 nir_intrinsic_instr *instr)
4182 {
4183 LLVMValueRef result = NULL;
4184
4185 switch (instr->intrinsic) {
4186 case nir_intrinsic_load_work_group_id: {
4187 LLVMValueRef values[3];
4188
4189 for (int i = 0; i < 3; i++) {
4190 values[i] = ctx->nctx->workgroup_ids[i] ?
4191 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4192 }
4193
4194 result = ac_build_gather_values(&ctx->ac, values, 3);
4195 break;
4196 }
4197 case nir_intrinsic_load_base_vertex: {
4198 result = ctx->abi->base_vertex;
4199 break;
4200 }
4201 case nir_intrinsic_load_vertex_id_zero_base: {
4202 result = ctx->abi->vertex_id;
4203 break;
4204 }
4205 case nir_intrinsic_load_local_invocation_id: {
4206 result = ctx->nctx->local_invocation_ids;
4207 break;
4208 }
4209 case nir_intrinsic_load_base_instance:
4210 result = ctx->abi->start_instance;
4211 break;
4212 case nir_intrinsic_load_draw_id:
4213 result = ctx->abi->draw_id;
4214 break;
4215 case nir_intrinsic_load_view_index:
4216 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4217 break;
4218 case nir_intrinsic_load_invocation_id:
4219 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4220 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4221 else
4222 result = ctx->abi->gs_invocation_id;
4223 break;
4224 case nir_intrinsic_load_primitive_id:
4225 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4226 result = ctx->abi->gs_prim_id;
4227 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4228 result = ctx->abi->tcs_patch_id;
4229 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4230 result = ctx->abi->tes_patch_id;
4231 } else
4232 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4233 break;
4234 case nir_intrinsic_load_sample_id:
4235 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4236 break;
4237 case nir_intrinsic_load_sample_pos:
4238 result = load_sample_pos(ctx);
4239 break;
4240 case nir_intrinsic_load_sample_mask_in:
4241 result = ctx->abi->sample_coverage;
4242 break;
4243 case nir_intrinsic_load_frag_coord: {
4244 LLVMValueRef values[4] = {
4245 ctx->abi->frag_pos[0],
4246 ctx->abi->frag_pos[1],
4247 ctx->abi->frag_pos[2],
4248 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4249 };
4250 result = ac_build_gather_values(&ctx->ac, values, 4);
4251 break;
4252 }
4253 case nir_intrinsic_load_front_face:
4254 result = ctx->abi->front_face;
4255 break;
4256 case nir_intrinsic_load_instance_id:
4257 result = ctx->abi->instance_id;
4258 break;
4259 case nir_intrinsic_load_num_work_groups:
4260 result = ctx->nctx->num_work_groups;
4261 break;
4262 case nir_intrinsic_load_local_invocation_index:
4263 result = visit_load_local_invocation_index(ctx->nctx);
4264 break;
4265 case nir_intrinsic_load_push_constant:
4266 result = visit_load_push_constant(ctx->nctx, instr);
4267 break;
4268 case nir_intrinsic_vulkan_resource_index:
4269 result = visit_vulkan_resource_index(ctx->nctx, instr);
4270 break;
4271 case nir_intrinsic_vulkan_resource_reindex:
4272 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4273 break;
4274 case nir_intrinsic_store_ssbo:
4275 visit_store_ssbo(ctx, instr);
4276 break;
4277 case nir_intrinsic_load_ssbo:
4278 result = visit_load_buffer(ctx, instr);
4279 break;
4280 case nir_intrinsic_ssbo_atomic_add:
4281 case nir_intrinsic_ssbo_atomic_imin:
4282 case nir_intrinsic_ssbo_atomic_umin:
4283 case nir_intrinsic_ssbo_atomic_imax:
4284 case nir_intrinsic_ssbo_atomic_umax:
4285 case nir_intrinsic_ssbo_atomic_and:
4286 case nir_intrinsic_ssbo_atomic_or:
4287 case nir_intrinsic_ssbo_atomic_xor:
4288 case nir_intrinsic_ssbo_atomic_exchange:
4289 case nir_intrinsic_ssbo_atomic_comp_swap:
4290 result = visit_atomic_ssbo(ctx, instr);
4291 break;
4292 case nir_intrinsic_load_ubo:
4293 result = visit_load_ubo_buffer(ctx, instr);
4294 break;
4295 case nir_intrinsic_get_buffer_size:
4296 result = visit_get_buffer_size(ctx, instr);
4297 break;
4298 case nir_intrinsic_load_var:
4299 result = visit_load_var(ctx, instr);
4300 break;
4301 case nir_intrinsic_store_var:
4302 visit_store_var(ctx, instr);
4303 break;
4304 case nir_intrinsic_image_load:
4305 result = visit_image_load(ctx, instr);
4306 break;
4307 case nir_intrinsic_image_store:
4308 visit_image_store(ctx, instr);
4309 break;
4310 case nir_intrinsic_image_atomic_add:
4311 case nir_intrinsic_image_atomic_min:
4312 case nir_intrinsic_image_atomic_max:
4313 case nir_intrinsic_image_atomic_and:
4314 case nir_intrinsic_image_atomic_or:
4315 case nir_intrinsic_image_atomic_xor:
4316 case nir_intrinsic_image_atomic_exchange:
4317 case nir_intrinsic_image_atomic_comp_swap:
4318 result = visit_image_atomic(ctx, instr);
4319 break;
4320 case nir_intrinsic_image_size:
4321 result = visit_image_size(ctx, instr);
4322 break;
4323 case nir_intrinsic_discard:
4324 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4325 LLVMVoidTypeInContext(ctx->ac.context),
4326 NULL, 0, AC_FUNC_ATTR_LEGACY);
4327 break;
4328 case nir_intrinsic_discard_if:
4329 emit_discard_if(ctx, instr);
4330 break;
4331 case nir_intrinsic_memory_barrier:
4332 case nir_intrinsic_group_memory_barrier:
4333 case nir_intrinsic_memory_barrier_atomic_counter:
4334 case nir_intrinsic_memory_barrier_buffer:
4335 case nir_intrinsic_memory_barrier_image:
4336 case nir_intrinsic_memory_barrier_shared:
4337 emit_membar(ctx->nctx, instr);
4338 break;
4339 case nir_intrinsic_barrier:
4340 emit_barrier(&ctx->ac, ctx->stage);
4341 break;
4342 case nir_intrinsic_var_atomic_add:
4343 case nir_intrinsic_var_atomic_imin:
4344 case nir_intrinsic_var_atomic_umin:
4345 case nir_intrinsic_var_atomic_imax:
4346 case nir_intrinsic_var_atomic_umax:
4347 case nir_intrinsic_var_atomic_and:
4348 case nir_intrinsic_var_atomic_or:
4349 case nir_intrinsic_var_atomic_xor:
4350 case nir_intrinsic_var_atomic_exchange:
4351 case nir_intrinsic_var_atomic_comp_swap:
4352 result = visit_var_atomic(ctx->nctx, instr);
4353 break;
4354 case nir_intrinsic_interp_var_at_centroid:
4355 case nir_intrinsic_interp_var_at_sample:
4356 case nir_intrinsic_interp_var_at_offset:
4357 result = visit_interp(ctx->nctx, instr);
4358 break;
4359 case nir_intrinsic_emit_vertex:
4360 assert(instr->const_index[0] == 0);
4361 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4362 break;
4363 case nir_intrinsic_end_primitive:
4364 visit_end_primitive(ctx->nctx, instr);
4365 break;
4366 case nir_intrinsic_load_tess_coord: {
4367 LLVMTypeRef type = ctx->nctx ?
4368 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4369 NULL;
4370 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4371 break;
4372 }
4373 case nir_intrinsic_load_tess_level_outer:
4374 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4375 break;
4376 case nir_intrinsic_load_tess_level_inner:
4377 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4378 break;
4379 case nir_intrinsic_load_patch_vertices_in:
4380 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4381 break;
4382 default:
4383 fprintf(stderr, "Unknown intrinsic: ");
4384 nir_print_instr(&instr->instr, stderr);
4385 fprintf(stderr, "\n");
4386 break;
4387 }
4388 if (result) {
4389 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4390 }
4391 }
4392
4393 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4394 LLVMValueRef buffer_ptr, bool write)
4395 {
4396 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4397
4398 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4399 ctx->shader_info->fs.writes_memory = true;
4400
4401 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4402 }
4403
4404 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4405 {
4406 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4407
4408 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4409 }
4410
4411 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4412 unsigned descriptor_set,
4413 unsigned base_index,
4414 unsigned constant_index,
4415 LLVMValueRef index,
4416 enum ac_descriptor_type desc_type,
4417 bool image, bool write)
4418 {
4419 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4420 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4421 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4422 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4423 unsigned offset = binding->offset;
4424 unsigned stride = binding->size;
4425 unsigned type_size;
4426 LLVMBuilderRef builder = ctx->builder;
4427 LLVMTypeRef type;
4428
4429 assert(base_index < layout->binding_count);
4430
4431 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4432 ctx->shader_info->fs.writes_memory = true;
4433
4434 switch (desc_type) {
4435 case AC_DESC_IMAGE:
4436 type = ctx->ac.v8i32;
4437 type_size = 32;
4438 break;
4439 case AC_DESC_FMASK:
4440 type = ctx->ac.v8i32;
4441 offset += 32;
4442 type_size = 32;
4443 break;
4444 case AC_DESC_SAMPLER:
4445 type = ctx->ac.v4i32;
4446 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4447 offset += 64;
4448
4449 type_size = 16;
4450 break;
4451 case AC_DESC_BUFFER:
4452 type = ctx->ac.v4i32;
4453 type_size = 16;
4454 break;
4455 default:
4456 unreachable("invalid desc_type\n");
4457 }
4458
4459 offset += constant_index * stride;
4460
4461 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4462 (!index || binding->immutable_samplers_equal)) {
4463 if (binding->immutable_samplers_equal)
4464 constant_index = 0;
4465
4466 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4467
4468 LLVMValueRef constants[] = {
4469 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4470 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4471 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4472 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4473 };
4474 return ac_build_gather_values(&ctx->ac, constants, 4);
4475 }
4476
4477 assert(stride % type_size == 0);
4478
4479 if (!index)
4480 index = ctx->ac.i32_0;
4481
4482 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4483
4484 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4485 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4486
4487 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4488 }
4489
4490 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4491 const nir_deref_var *deref,
4492 enum ac_descriptor_type desc_type,
4493 const nir_tex_instr *tex_instr,
4494 bool image, bool write)
4495 {
4496 LLVMValueRef index = NULL;
4497 unsigned constant_index = 0;
4498 unsigned descriptor_set;
4499 unsigned base_index;
4500
4501 if (!deref) {
4502 assert(tex_instr && !image);
4503 descriptor_set = 0;
4504 base_index = tex_instr->sampler_index;
4505 } else {
4506 const nir_deref *tail = &deref->deref;
4507 while (tail->child) {
4508 const nir_deref_array *child = nir_deref_as_array(tail->child);
4509 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4510
4511 if (!array_size)
4512 array_size = 1;
4513
4514 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4515
4516 if (child->deref_array_type == nir_deref_array_type_indirect) {
4517 LLVMValueRef indirect = get_src(ctx, child->indirect);
4518
4519 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4520 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4521
4522 if (!index)
4523 index = indirect;
4524 else
4525 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4526 }
4527
4528 constant_index += child->base_offset * array_size;
4529
4530 tail = &child->deref;
4531 }
4532 descriptor_set = deref->var->data.descriptor_set;
4533 base_index = deref->var->data.binding;
4534 }
4535
4536 return ctx->abi->load_sampler_desc(ctx->abi,
4537 descriptor_set,
4538 base_index,
4539 constant_index, index,
4540 desc_type, image, write);
4541 }
4542
4543 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4544 struct ac_image_args *args,
4545 const nir_tex_instr *instr,
4546 nir_texop op,
4547 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4548 LLVMValueRef *param, unsigned count,
4549 unsigned dmask)
4550 {
4551 unsigned is_rect = 0;
4552 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4553
4554 if (op == nir_texop_lod)
4555 da = false;
4556 /* Pad to power of two vector */
4557 while (count < util_next_power_of_two(count))
4558 param[count++] = LLVMGetUndef(ctx->i32);
4559
4560 if (count > 1)
4561 args->addr = ac_build_gather_values(ctx, param, count);
4562 else
4563 args->addr = param[0];
4564
4565 args->resource = res_ptr;
4566 args->sampler = samp_ptr;
4567
4568 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4569 args->addr = param[0];
4570 return;
4571 }
4572
4573 args->dmask = dmask;
4574 args->unorm = is_rect;
4575 args->da = da;
4576 }
4577
4578 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4579 *
4580 * SI-CI:
4581 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4582 * filtering manually. The driver sets img7 to a mask clearing
4583 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4584 * s_and_b32 samp0, samp0, img7
4585 *
4586 * VI:
4587 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4588 */
4589 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4590 LLVMValueRef res, LLVMValueRef samp)
4591 {
4592 LLVMBuilderRef builder = ctx->ac.builder;
4593 LLVMValueRef img7, samp0;
4594
4595 if (ctx->ac.chip_class >= VI)
4596 return samp;
4597
4598 img7 = LLVMBuildExtractElement(builder, res,
4599 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4600 samp0 = LLVMBuildExtractElement(builder, samp,
4601 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4602 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4603 return LLVMBuildInsertElement(builder, samp, samp0,
4604 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4605 }
4606
4607 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4608 nir_tex_instr *instr,
4609 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4610 LLVMValueRef *fmask_ptr)
4611 {
4612 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4613 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4614 else
4615 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4616 if (samp_ptr) {
4617 if (instr->sampler)
4618 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4619 else
4620 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4621 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4622 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4623 }
4624 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4625 instr->op == nir_texop_samples_identical))
4626 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4627 }
4628
4629 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4630 LLVMValueRef coord)
4631 {
4632 coord = ac_to_float(ctx, coord);
4633 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4634 coord = ac_to_integer(ctx, coord);
4635 return coord;
4636 }
4637
4638 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4639 {
4640 LLVMValueRef result = NULL;
4641 struct ac_image_args args = { 0 };
4642 unsigned dmask = 0xf;
4643 LLVMValueRef address[16];
4644 LLVMValueRef coords[5];
4645 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4646 LLVMValueRef bias = NULL, offsets = NULL;
4647 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4648 LLVMValueRef ddx = NULL, ddy = NULL;
4649 LLVMValueRef derivs[6];
4650 unsigned chan, count = 0;
4651 unsigned const_src = 0, num_deriv_comp = 0;
4652 bool lod_is_zero = false;
4653
4654 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4655
4656 for (unsigned i = 0; i < instr->num_srcs; i++) {
4657 switch (instr->src[i].src_type) {
4658 case nir_tex_src_coord:
4659 coord = get_src(ctx, instr->src[i].src);
4660 break;
4661 case nir_tex_src_projector:
4662 break;
4663 case nir_tex_src_comparator:
4664 comparator = get_src(ctx, instr->src[i].src);
4665 break;
4666 case nir_tex_src_offset:
4667 offsets = get_src(ctx, instr->src[i].src);
4668 const_src = i;
4669 break;
4670 case nir_tex_src_bias:
4671 bias = get_src(ctx, instr->src[i].src);
4672 break;
4673 case nir_tex_src_lod: {
4674 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4675
4676 if (val && val->i32[0] == 0)
4677 lod_is_zero = true;
4678 lod = get_src(ctx, instr->src[i].src);
4679 break;
4680 }
4681 case nir_tex_src_ms_index:
4682 sample_index = get_src(ctx, instr->src[i].src);
4683 break;
4684 case nir_tex_src_ms_mcs:
4685 break;
4686 case nir_tex_src_ddx:
4687 ddx = get_src(ctx, instr->src[i].src);
4688 num_deriv_comp = instr->src[i].src.ssa->num_components;
4689 break;
4690 case nir_tex_src_ddy:
4691 ddy = get_src(ctx, instr->src[i].src);
4692 break;
4693 case nir_tex_src_texture_offset:
4694 case nir_tex_src_sampler_offset:
4695 case nir_tex_src_plane:
4696 default:
4697 break;
4698 }
4699 }
4700
4701 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4702 result = get_buffer_size(ctx, res_ptr, true);
4703 goto write_result;
4704 }
4705
4706 if (instr->op == nir_texop_texture_samples) {
4707 LLVMValueRef res, samples, is_msaa;
4708 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4709 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4710 LLVMConstInt(ctx->ac.i32, 3, false), "");
4711 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4712 LLVMConstInt(ctx->ac.i32, 28, false), "");
4713 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4714 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4715 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4716 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4717
4718 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4719 LLVMConstInt(ctx->ac.i32, 16, false), "");
4720 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4721 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4722 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4723 samples, "");
4724 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4725 ctx->ac.i32_1, "");
4726 result = samples;
4727 goto write_result;
4728 }
4729
4730 if (coord)
4731 for (chan = 0; chan < instr->coord_components; chan++)
4732 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4733
4734 if (offsets && instr->op != nir_texop_txf) {
4735 LLVMValueRef offset[3], pack;
4736 for (chan = 0; chan < 3; ++chan)
4737 offset[chan] = ctx->ac.i32_0;
4738
4739 args.offset = true;
4740 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4741 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4742 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4743 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4744 if (chan)
4745 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4746 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4747 }
4748 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4749 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4750 address[count++] = pack;
4751
4752 }
4753 /* pack LOD bias value */
4754 if (instr->op == nir_texop_txb && bias) {
4755 address[count++] = bias;
4756 }
4757
4758 /* Pack depth comparison value */
4759 if (instr->is_shadow && comparator) {
4760 LLVMValueRef z = ac_to_float(&ctx->ac,
4761 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4762
4763 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4764 * so the depth comparison value isn't clamped for Z16 and
4765 * Z24 anymore. Do it manually here.
4766 *
4767 * It's unnecessary if the original texture format was
4768 * Z32_FLOAT, but we don't know that here.
4769 */
4770 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4771 z = ac_build_clamp(&ctx->ac, z);
4772
4773 address[count++] = z;
4774 }
4775
4776 /* pack derivatives */
4777 if (ddx || ddy) {
4778 int num_src_deriv_channels, num_dest_deriv_channels;
4779 switch (instr->sampler_dim) {
4780 case GLSL_SAMPLER_DIM_3D:
4781 case GLSL_SAMPLER_DIM_CUBE:
4782 num_deriv_comp = 3;
4783 num_src_deriv_channels = 3;
4784 num_dest_deriv_channels = 3;
4785 break;
4786 case GLSL_SAMPLER_DIM_2D:
4787 default:
4788 num_src_deriv_channels = 2;
4789 num_dest_deriv_channels = 2;
4790 num_deriv_comp = 2;
4791 break;
4792 case GLSL_SAMPLER_DIM_1D:
4793 num_src_deriv_channels = 1;
4794 if (ctx->ac.chip_class >= GFX9) {
4795 num_dest_deriv_channels = 2;
4796 num_deriv_comp = 2;
4797 } else {
4798 num_dest_deriv_channels = 1;
4799 num_deriv_comp = 1;
4800 }
4801 break;
4802 }
4803
4804 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4805 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4806 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4807 }
4808 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4809 derivs[i] = ctx->ac.f32_0;
4810 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4811 }
4812 }
4813
4814 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4815 for (chan = 0; chan < instr->coord_components; chan++)
4816 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4817 if (instr->coord_components == 3)
4818 coords[3] = LLVMGetUndef(ctx->ac.f32);
4819 ac_prepare_cube_coords(&ctx->ac,
4820 instr->op == nir_texop_txd, instr->is_array,
4821 instr->op == nir_texop_lod, coords, derivs);
4822 if (num_deriv_comp)
4823 num_deriv_comp--;
4824 }
4825
4826 if (ddx || ddy) {
4827 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4828 address[count++] = derivs[i];
4829 }
4830
4831 /* Pack texture coordinates */
4832 if (coord) {
4833 address[count++] = coords[0];
4834 if (instr->coord_components > 1) {
4835 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4836 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4837 }
4838 address[count++] = coords[1];
4839 }
4840 if (instr->coord_components > 2) {
4841 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4842 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4843 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4844 instr->op != nir_texop_txf) {
4845 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4846 }
4847 address[count++] = coords[2];
4848 }
4849
4850 if (ctx->ac.chip_class >= GFX9) {
4851 LLVMValueRef filler;
4852 if (instr->op == nir_texop_txf)
4853 filler = ctx->ac.i32_0;
4854 else
4855 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4856
4857 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4858 /* No nir_texop_lod, because it does not take a slice
4859 * even with array textures. */
4860 if (instr->is_array && instr->op != nir_texop_lod ) {
4861 address[count] = address[count - 1];
4862 address[count - 1] = filler;
4863 count++;
4864 } else
4865 address[count++] = filler;
4866 }
4867 }
4868 }
4869
4870 /* Pack LOD */
4871 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4872 instr->op == nir_texop_txf)) {
4873 address[count++] = lod;
4874 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4875 address[count++] = sample_index;
4876 } else if(instr->op == nir_texop_txs) {
4877 count = 0;
4878 if (lod)
4879 address[count++] = lod;
4880 else
4881 address[count++] = ctx->ac.i32_0;
4882 }
4883
4884 for (chan = 0; chan < count; chan++) {
4885 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4886 address[chan], ctx->ac.i32, "");
4887 }
4888
4889 if (instr->op == nir_texop_samples_identical) {
4890 LLVMValueRef txf_address[4];
4891 struct ac_image_args txf_args = { 0 };
4892 unsigned txf_count = count;
4893 memcpy(txf_address, address, sizeof(txf_address));
4894
4895 if (!instr->is_array)
4896 txf_address[2] = ctx->ac.i32_0;
4897 txf_address[3] = ctx->ac.i32_0;
4898
4899 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4900 fmask_ptr, NULL,
4901 txf_address, txf_count, 0xf);
4902
4903 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4904
4905 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4906 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4907 goto write_result;
4908 }
4909
4910 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4911 instr->op != nir_texop_txs) {
4912 unsigned sample_chan = instr->is_array ? 3 : 2;
4913 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4914 address[0],
4915 address[1],
4916 instr->is_array ? address[2] : NULL,
4917 address[sample_chan],
4918 fmask_ptr);
4919 }
4920
4921 if (offsets && instr->op == nir_texop_txf) {
4922 nir_const_value *const_offset =
4923 nir_src_as_const_value(instr->src[const_src].src);
4924 int num_offsets = instr->src[const_src].src.ssa->num_components;
4925 assert(const_offset);
4926 num_offsets = MIN2(num_offsets, instr->coord_components);
4927 if (num_offsets > 2)
4928 address[2] = LLVMBuildAdd(ctx->ac.builder,
4929 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4930 if (num_offsets > 1)
4931 address[1] = LLVMBuildAdd(ctx->ac.builder,
4932 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4933 address[0] = LLVMBuildAdd(ctx->ac.builder,
4934 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4935
4936 }
4937
4938 /* TODO TG4 support */
4939 if (instr->op == nir_texop_tg4) {
4940 if (instr->is_shadow)
4941 dmask = 1;
4942 else
4943 dmask = 1 << instr->component;
4944 }
4945 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4946 res_ptr, samp_ptr, address, count, dmask);
4947
4948 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4949
4950 if (instr->op == nir_texop_query_levels)
4951 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4952 else if (instr->is_shadow && instr->is_new_style_shadow &&
4953 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4954 instr->op != nir_texop_tg4)
4955 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4956 else if (instr->op == nir_texop_txs &&
4957 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4958 instr->is_array) {
4959 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4960 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4961 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4962 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4963 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4964 } else if (ctx->ac.chip_class >= GFX9 &&
4965 instr->op == nir_texop_txs &&
4966 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4967 instr->is_array) {
4968 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4969 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4970 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4971 ctx->ac.i32_1, "");
4972 } else if (instr->dest.ssa.num_components != 4)
4973 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4974
4975 write_result:
4976 if (result) {
4977 assert(instr->dest.is_ssa);
4978 result = ac_to_integer(&ctx->ac, result);
4979 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4980 }
4981 }
4982
4983
4984 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4985 {
4986 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4987 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4988
4989 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4990 _mesa_hash_table_insert(ctx->phis, instr, result);
4991 }
4992
4993 static void visit_post_phi(struct ac_nir_context *ctx,
4994 nir_phi_instr *instr,
4995 LLVMValueRef llvm_phi)
4996 {
4997 nir_foreach_phi_src(src, instr) {
4998 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4999 LLVMValueRef llvm_src = get_src(ctx, src->src);
5000
5001 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5002 }
5003 }
5004
5005 static void phi_post_pass(struct ac_nir_context *ctx)
5006 {
5007 struct hash_entry *entry;
5008 hash_table_foreach(ctx->phis, entry) {
5009 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5010 (LLVMValueRef)entry->data);
5011 }
5012 }
5013
5014
5015 static void visit_ssa_undef(struct ac_nir_context *ctx,
5016 const nir_ssa_undef_instr *instr)
5017 {
5018 unsigned num_components = instr->def.num_components;
5019 LLVMValueRef undef;
5020
5021 if (num_components == 1)
5022 undef = LLVMGetUndef(ctx->ac.i32);
5023 else {
5024 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5025 }
5026 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5027 }
5028
5029 static void visit_jump(struct ac_nir_context *ctx,
5030 const nir_jump_instr *instr)
5031 {
5032 switch (instr->type) {
5033 case nir_jump_break:
5034 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5035 LLVMClearInsertionPosition(ctx->ac.builder);
5036 break;
5037 case nir_jump_continue:
5038 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5039 LLVMClearInsertionPosition(ctx->ac.builder);
5040 break;
5041 default:
5042 fprintf(stderr, "Unknown NIR jump instr: ");
5043 nir_print_instr(&instr->instr, stderr);
5044 fprintf(stderr, "\n");
5045 abort();
5046 }
5047 }
5048
5049 static void visit_cf_list(struct ac_nir_context *ctx,
5050 struct exec_list *list);
5051
5052 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5053 {
5054 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5055 nir_foreach_instr(instr, block)
5056 {
5057 switch (instr->type) {
5058 case nir_instr_type_alu:
5059 visit_alu(ctx, nir_instr_as_alu(instr));
5060 break;
5061 case nir_instr_type_load_const:
5062 visit_load_const(ctx, nir_instr_as_load_const(instr));
5063 break;
5064 case nir_instr_type_intrinsic:
5065 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5066 break;
5067 case nir_instr_type_tex:
5068 visit_tex(ctx, nir_instr_as_tex(instr));
5069 break;
5070 case nir_instr_type_phi:
5071 visit_phi(ctx, nir_instr_as_phi(instr));
5072 break;
5073 case nir_instr_type_ssa_undef:
5074 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5075 break;
5076 case nir_instr_type_jump:
5077 visit_jump(ctx, nir_instr_as_jump(instr));
5078 break;
5079 default:
5080 fprintf(stderr, "Unknown NIR instr type: ");
5081 nir_print_instr(instr, stderr);
5082 fprintf(stderr, "\n");
5083 abort();
5084 }
5085 }
5086
5087 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5088 }
5089
5090 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5091 {
5092 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5093
5094 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5095 LLVMBasicBlockRef merge_block =
5096 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5097 LLVMBasicBlockRef if_block =
5098 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5099 LLVMBasicBlockRef else_block = merge_block;
5100 if (!exec_list_is_empty(&if_stmt->else_list))
5101 else_block = LLVMAppendBasicBlockInContext(
5102 ctx->ac.context, fn, "");
5103
5104 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5105 ctx->ac.i32_0, "");
5106 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5107
5108 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5109 visit_cf_list(ctx, &if_stmt->then_list);
5110 if (LLVMGetInsertBlock(ctx->ac.builder))
5111 LLVMBuildBr(ctx->ac.builder, merge_block);
5112
5113 if (!exec_list_is_empty(&if_stmt->else_list)) {
5114 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5115 visit_cf_list(ctx, &if_stmt->else_list);
5116 if (LLVMGetInsertBlock(ctx->ac.builder))
5117 LLVMBuildBr(ctx->ac.builder, merge_block);
5118 }
5119
5120 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5121 }
5122
5123 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5124 {
5125 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5126 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5127 LLVMBasicBlockRef break_parent = ctx->break_block;
5128
5129 ctx->continue_block =
5130 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5131 ctx->break_block =
5132 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5133
5134 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5135 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5136 visit_cf_list(ctx, &loop->body);
5137
5138 if (LLVMGetInsertBlock(ctx->ac.builder))
5139 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5140 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5141
5142 ctx->continue_block = continue_parent;
5143 ctx->break_block = break_parent;
5144 }
5145
5146 static void visit_cf_list(struct ac_nir_context *ctx,
5147 struct exec_list *list)
5148 {
5149 foreach_list_typed(nir_cf_node, node, node, list)
5150 {
5151 switch (node->type) {
5152 case nir_cf_node_block:
5153 visit_block(ctx, nir_cf_node_as_block(node));
5154 break;
5155
5156 case nir_cf_node_if:
5157 visit_if(ctx, nir_cf_node_as_if(node));
5158 break;
5159
5160 case nir_cf_node_loop:
5161 visit_loop(ctx, nir_cf_node_as_loop(node));
5162 break;
5163
5164 default:
5165 assert(0);
5166 }
5167 }
5168 }
5169
5170 static void
5171 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5172 struct nir_variable *variable)
5173 {
5174 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5175 LLVMValueRef t_offset;
5176 LLVMValueRef t_list;
5177 LLVMValueRef input;
5178 LLVMValueRef buffer_index;
5179 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5180 int idx = variable->data.location;
5181 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5182
5183 variable->data.driver_location = idx * 4;
5184
5185 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5186 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5187 ctx->abi.start_instance, "");
5188 if (ctx->options->key.vs.as_ls) {
5189 ctx->shader_info->vs.vgpr_comp_cnt =
5190 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5191 } else {
5192 ctx->shader_info->vs.vgpr_comp_cnt =
5193 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5194 }
5195 } else
5196 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5197 ctx->abi.base_vertex, "");
5198
5199 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5200 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5201
5202 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5203
5204 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5205 buffer_index,
5206 ctx->ac.i32_0,
5207 true);
5208
5209 for (unsigned chan = 0; chan < 4; chan++) {
5210 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5211 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5212 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5213 input, llvm_chan, ""));
5214 }
5215 }
5216 }
5217
5218 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5219 unsigned attr,
5220 LLVMValueRef interp_param,
5221 LLVMValueRef prim_mask,
5222 LLVMValueRef result[4])
5223 {
5224 LLVMValueRef attr_number;
5225 unsigned chan;
5226 LLVMValueRef i, j;
5227 bool interp = interp_param != NULL;
5228
5229 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5230
5231 /* fs.constant returns the param from the middle vertex, so it's not
5232 * really useful for flat shading. It's meant to be used for custom
5233 * interpolation (but the intrinsic can't fetch from the other two
5234 * vertices).
5235 *
5236 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5237 * to do the right thing. The only reason we use fs.constant is that
5238 * fs.interp cannot be used on integers, because they can be equal
5239 * to NaN.
5240 */
5241 if (interp) {
5242 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5243 ctx->ac.v2f32, "");
5244
5245 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5246 ctx->ac.i32_0, "");
5247 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5248 ctx->ac.i32_1, "");
5249 }
5250
5251 for (chan = 0; chan < 4; chan++) {
5252 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5253
5254 if (interp) {
5255 result[chan] = ac_build_fs_interp(&ctx->ac,
5256 llvm_chan,
5257 attr_number,
5258 prim_mask, i, j);
5259 } else {
5260 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5261 LLVMConstInt(ctx->ac.i32, 2, false),
5262 llvm_chan,
5263 attr_number,
5264 prim_mask);
5265 }
5266 }
5267 }
5268
5269 static void
5270 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5271 struct nir_variable *variable)
5272 {
5273 int idx = variable->data.location;
5274 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5275 LLVMValueRef interp;
5276
5277 variable->data.driver_location = idx * 4;
5278 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5279
5280 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5281 unsigned interp_type;
5282 if (variable->data.sample) {
5283 interp_type = INTERP_SAMPLE;
5284 ctx->shader_info->info.ps.force_persample = true;
5285 } else if (variable->data.centroid)
5286 interp_type = INTERP_CENTROID;
5287 else
5288 interp_type = INTERP_CENTER;
5289
5290 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5291 } else
5292 interp = NULL;
5293
5294 for (unsigned i = 0; i < attrib_count; ++i)
5295 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5296
5297 }
5298
5299 static void
5300 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5301 struct nir_shader *nir) {
5302 nir_foreach_variable(variable, &nir->inputs)
5303 handle_vs_input_decl(ctx, variable);
5304 }
5305
5306 static void
5307 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5308 struct nir_shader *nir)
5309 {
5310 if (!ctx->options->key.fs.multisample)
5311 return;
5312
5313 bool uses_center = false;
5314 bool uses_centroid = false;
5315 nir_foreach_variable(variable, &nir->inputs) {
5316 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5317 variable->data.sample)
5318 continue;
5319
5320 if (variable->data.centroid)
5321 uses_centroid = true;
5322 else
5323 uses_center = true;
5324 }
5325
5326 if (uses_center && uses_centroid) {
5327 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5328 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5329 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5330 }
5331 }
5332
5333 static void
5334 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5335 struct nir_shader *nir)
5336 {
5337 prepare_interp_optimize(ctx, nir);
5338
5339 nir_foreach_variable(variable, &nir->inputs)
5340 handle_fs_input_decl(ctx, variable);
5341
5342 unsigned index = 0;
5343
5344 if (ctx->shader_info->info.ps.uses_input_attachments ||
5345 ctx->shader_info->info.needs_multiview_view_index)
5346 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5347
5348 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5349 LLVMValueRef interp_param;
5350 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5351
5352 if (!(ctx->input_mask & (1ull << i)))
5353 continue;
5354
5355 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5356 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5357 interp_param = *inputs;
5358 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5359 inputs);
5360
5361 if (!interp_param)
5362 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5363 ++index;
5364 } else if (i == VARYING_SLOT_POS) {
5365 for(int i = 0; i < 3; ++i)
5366 inputs[i] = ctx->abi.frag_pos[i];
5367
5368 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5369 ctx->abi.frag_pos[3]);
5370 }
5371 }
5372 ctx->shader_info->fs.num_interp = index;
5373 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5374 ctx->shader_info->fs.has_pcoord = true;
5375 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5376 ctx->shader_info->fs.prim_id_input = true;
5377 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5378 ctx->shader_info->fs.layer_input = true;
5379 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5380
5381 if (ctx->shader_info->info.needs_multiview_view_index)
5382 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5383 }
5384
5385 static LLVMValueRef
5386 ac_build_alloca(struct ac_llvm_context *ac,
5387 LLVMTypeRef type,
5388 const char *name)
5389 {
5390 LLVMBuilderRef builder = ac->builder;
5391 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5392 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5393 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5394 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5395 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5396 LLVMValueRef res;
5397
5398 if (first_instr) {
5399 LLVMPositionBuilderBefore(first_builder, first_instr);
5400 } else {
5401 LLVMPositionBuilderAtEnd(first_builder, first_block);
5402 }
5403
5404 res = LLVMBuildAlloca(first_builder, type, name);
5405 LLVMBuildStore(builder, LLVMConstNull(type), res);
5406
5407 LLVMDisposeBuilder(first_builder);
5408
5409 return res;
5410 }
5411
5412 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5413 LLVMTypeRef type,
5414 const char *name)
5415 {
5416 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5417 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5418 return ptr;
5419 }
5420
5421 static void
5422 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5423 struct nir_variable *variable,
5424 struct nir_shader *shader,
5425 gl_shader_stage stage)
5426 {
5427 int idx = variable->data.location + variable->data.index;
5428 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5429 uint64_t mask_attribs;
5430
5431 variable->data.driver_location = idx * 4;
5432
5433 /* tess ctrl has it's own load/store paths for outputs */
5434 if (stage == MESA_SHADER_TESS_CTRL)
5435 return;
5436
5437 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5438 if (stage == MESA_SHADER_VERTEX ||
5439 stage == MESA_SHADER_TESS_EVAL ||
5440 stage == MESA_SHADER_GEOMETRY) {
5441 if (idx == VARYING_SLOT_CLIP_DIST0) {
5442 int length = shader->info.clip_distance_array_size +
5443 shader->info.cull_distance_array_size;
5444 if (stage == MESA_SHADER_VERTEX) {
5445 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5446 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5447 }
5448 if (stage == MESA_SHADER_TESS_EVAL) {
5449 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5450 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5451 }
5452
5453 if (length > 4)
5454 attrib_count = 2;
5455 else
5456 attrib_count = 1;
5457 mask_attribs = 1ull << idx;
5458 }
5459 }
5460
5461 ctx->output_mask |= mask_attribs;
5462 }
5463
5464 static void
5465 handle_shader_output_decl(struct ac_nir_context *ctx,
5466 struct nir_shader *nir,
5467 struct nir_variable *variable)
5468 {
5469 unsigned output_loc = variable->data.driver_location / 4;
5470 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5471
5472 /* tess ctrl has it's own load/store paths for outputs */
5473 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5474 return;
5475
5476 if (ctx->stage == MESA_SHADER_VERTEX ||
5477 ctx->stage == MESA_SHADER_TESS_EVAL ||
5478 ctx->stage == MESA_SHADER_GEOMETRY) {
5479 int idx = variable->data.location + variable->data.index;
5480 if (idx == VARYING_SLOT_CLIP_DIST0) {
5481 int length = nir->info.clip_distance_array_size +
5482 nir->info.cull_distance_array_size;
5483
5484 if (length > 4)
5485 attrib_count = 2;
5486 else
5487 attrib_count = 1;
5488 }
5489 }
5490
5491 for (unsigned i = 0; i < attrib_count; ++i) {
5492 for (unsigned chan = 0; chan < 4; chan++) {
5493 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5494 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5495 }
5496 }
5497 }
5498
5499 static LLVMTypeRef
5500 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5501 enum glsl_base_type type)
5502 {
5503 switch (type) {
5504 case GLSL_TYPE_INT:
5505 case GLSL_TYPE_UINT:
5506 case GLSL_TYPE_BOOL:
5507 case GLSL_TYPE_SUBROUTINE:
5508 return ctx->ac.i32;
5509 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5510 return ctx->ac.f32;
5511 case GLSL_TYPE_INT64:
5512 case GLSL_TYPE_UINT64:
5513 return ctx->ac.i64;
5514 case GLSL_TYPE_DOUBLE:
5515 return ctx->ac.f64;
5516 default:
5517 unreachable("unknown GLSL type");
5518 }
5519 }
5520
5521 static LLVMTypeRef
5522 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5523 const struct glsl_type *type)
5524 {
5525 if (glsl_type_is_scalar(type)) {
5526 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5527 }
5528
5529 if (glsl_type_is_vector(type)) {
5530 return LLVMVectorType(
5531 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5532 glsl_get_vector_elements(type));
5533 }
5534
5535 if (glsl_type_is_matrix(type)) {
5536 return LLVMArrayType(
5537 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5538 glsl_get_matrix_columns(type));
5539 }
5540
5541 if (glsl_type_is_array(type)) {
5542 return LLVMArrayType(
5543 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5544 glsl_get_length(type));
5545 }
5546
5547 assert(glsl_type_is_struct(type));
5548
5549 LLVMTypeRef member_types[glsl_get_length(type)];
5550
5551 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5552 member_types[i] =
5553 glsl_to_llvm_type(ctx,
5554 glsl_get_struct_field(type, i));
5555 }
5556
5557 return LLVMStructTypeInContext(ctx->context, member_types,
5558 glsl_get_length(type), false);
5559 }
5560
5561 static void
5562 setup_locals(struct ac_nir_context *ctx,
5563 struct nir_function *func)
5564 {
5565 int i, j;
5566 ctx->num_locals = 0;
5567 nir_foreach_variable(variable, &func->impl->locals) {
5568 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5569 variable->data.driver_location = ctx->num_locals * 4;
5570 ctx->num_locals += attrib_count;
5571 }
5572 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5573 if (!ctx->locals)
5574 return;
5575
5576 for (i = 0; i < ctx->num_locals; i++) {
5577 for (j = 0; j < 4; j++) {
5578 ctx->locals[i * 4 + j] =
5579 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5580 }
5581 }
5582 }
5583
5584 static void
5585 setup_shared(struct ac_nir_context *ctx,
5586 struct nir_shader *nir)
5587 {
5588 nir_foreach_variable(variable, &nir->shared) {
5589 LLVMValueRef shared =
5590 LLVMAddGlobalInAddressSpace(
5591 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5592 variable->name ? variable->name : "",
5593 LOCAL_ADDR_SPACE);
5594 _mesa_hash_table_insert(ctx->vars, variable, shared);
5595 }
5596 }
5597
5598 static LLVMValueRef
5599 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5600 {
5601 v = ac_to_float(ctx, v);
5602 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5603 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5604 }
5605
5606
5607 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5608 LLVMValueRef src0, LLVMValueRef src1)
5609 {
5610 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5611 LLVMValueRef comp[2];
5612
5613 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5614 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5615 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5616 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5617 }
5618
5619 /* Initialize arguments for the shader export intrinsic */
5620 static void
5621 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5622 LLVMValueRef *values,
5623 unsigned target,
5624 struct ac_export_args *args)
5625 {
5626 /* Default is 0xf. Adjusted below depending on the format. */
5627 args->enabled_channels = 0xf;
5628
5629 /* Specify whether the EXEC mask represents the valid mask */
5630 args->valid_mask = 0;
5631
5632 /* Specify whether this is the last export */
5633 args->done = 0;
5634
5635 /* Specify the target we are exporting */
5636 args->target = target;
5637
5638 args->compr = false;
5639 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5640 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5641 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5642 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5643
5644 if (!values)
5645 return;
5646
5647 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5648 LLVMValueRef val[4];
5649 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5650 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5651 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5652 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5653
5654 switch(col_format) {
5655 case V_028714_SPI_SHADER_ZERO:
5656 args->enabled_channels = 0; /* writemask */
5657 args->target = V_008DFC_SQ_EXP_NULL;
5658 break;
5659
5660 case V_028714_SPI_SHADER_32_R:
5661 args->enabled_channels = 1;
5662 args->out[0] = values[0];
5663 break;
5664
5665 case V_028714_SPI_SHADER_32_GR:
5666 args->enabled_channels = 0x3;
5667 args->out[0] = values[0];
5668 args->out[1] = values[1];
5669 break;
5670
5671 case V_028714_SPI_SHADER_32_AR:
5672 args->enabled_channels = 0x9;
5673 args->out[0] = values[0];
5674 args->out[3] = values[3];
5675 break;
5676
5677 case V_028714_SPI_SHADER_FP16_ABGR:
5678 args->compr = 1;
5679
5680 for (unsigned chan = 0; chan < 2; chan++) {
5681 LLVMValueRef pack_args[2] = {
5682 values[2 * chan],
5683 values[2 * chan + 1]
5684 };
5685 LLVMValueRef packed;
5686
5687 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5688 args->out[chan] = packed;
5689 }
5690 break;
5691
5692 case V_028714_SPI_SHADER_UNORM16_ABGR:
5693 for (unsigned chan = 0; chan < 4; chan++) {
5694 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5695 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5696 LLVMConstReal(ctx->ac.f32, 65535), "");
5697 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5698 LLVMConstReal(ctx->ac.f32, 0.5), "");
5699 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5700 ctx->ac.i32, "");
5701 }
5702
5703 args->compr = 1;
5704 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5705 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5706 break;
5707
5708 case V_028714_SPI_SHADER_SNORM16_ABGR:
5709 for (unsigned chan = 0; chan < 4; chan++) {
5710 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5711 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5712 LLVMConstReal(ctx->ac.f32, 32767), "");
5713
5714 /* If positive, add 0.5, else add -0.5. */
5715 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5716 LLVMBuildSelect(ctx->builder,
5717 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5718 val[chan], ctx->ac.f32_0, ""),
5719 LLVMConstReal(ctx->ac.f32, 0.5),
5720 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5721 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5722 }
5723
5724 args->compr = 1;
5725 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5726 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5727 break;
5728
5729 case V_028714_SPI_SHADER_UINT16_ABGR: {
5730 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5731 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5732 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5733
5734 for (unsigned chan = 0; chan < 4; chan++) {
5735 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5736 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5737 }
5738
5739 args->compr = 1;
5740 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5741 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5742 break;
5743 }
5744
5745 case V_028714_SPI_SHADER_SINT16_ABGR: {
5746 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5747 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5748 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5749 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5750 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5751 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5752
5753 /* Clamp. */
5754 for (unsigned chan = 0; chan < 4; chan++) {
5755 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5756 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5757 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5758 }
5759
5760 args->compr = 1;
5761 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5762 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5763 break;
5764 }
5765
5766 default:
5767 case V_028714_SPI_SHADER_32_ABGR:
5768 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5769 break;
5770 }
5771 } else
5772 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5773
5774 for (unsigned i = 0; i < 4; ++i)
5775 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5776 }
5777
5778 static void
5779 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5780 bool export_prim_id,
5781 struct ac_vs_output_info *outinfo)
5782 {
5783 uint32_t param_count = 0;
5784 unsigned target;
5785 unsigned pos_idx, num_pos_exports = 0;
5786 struct ac_export_args args, pos_args[4] = {};
5787 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5788 int i;
5789
5790 if (ctx->options->key.has_multiview_view_index) {
5791 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5792 if(!*tmp_out) {
5793 for(unsigned i = 0; i < 4; ++i)
5794 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5795 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5796 }
5797
5798 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5799 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5800 }
5801
5802 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5803 sizeof(outinfo->vs_output_param_offset));
5804
5805 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5806 LLVMValueRef slots[8];
5807 unsigned j;
5808
5809 if (outinfo->cull_dist_mask)
5810 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5811
5812 i = VARYING_SLOT_CLIP_DIST0;
5813 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5814 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5815 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5816
5817 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5818 slots[i] = LLVMGetUndef(ctx->ac.f32);
5819
5820 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5821 target = V_008DFC_SQ_EXP_POS + 3;
5822 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5823 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5824 &args, sizeof(args));
5825 }
5826
5827 target = V_008DFC_SQ_EXP_POS + 2;
5828 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5829 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5830 &args, sizeof(args));
5831
5832 }
5833
5834 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5835 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5836 for (unsigned j = 0; j < 4; j++)
5837 pos_values[j] = LLVMBuildLoad(ctx->builder,
5838 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5839 }
5840 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5841
5842 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5843 outinfo->writes_pointsize = true;
5844 psize_value = LLVMBuildLoad(ctx->builder,
5845 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5846 }
5847
5848 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5849 outinfo->writes_layer = true;
5850 layer_value = LLVMBuildLoad(ctx->builder,
5851 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5852 }
5853
5854 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5855 outinfo->writes_viewport_index = true;
5856 viewport_index_value = LLVMBuildLoad(ctx->builder,
5857 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5858 }
5859
5860 if (outinfo->writes_pointsize ||
5861 outinfo->writes_layer ||
5862 outinfo->writes_viewport_index) {
5863 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5864 (outinfo->writes_layer == true ? 4 : 0));
5865 pos_args[1].valid_mask = 0;
5866 pos_args[1].done = 0;
5867 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5868 pos_args[1].compr = 0;
5869 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5870 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5871 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5872 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5873
5874 if (outinfo->writes_pointsize == true)
5875 pos_args[1].out[0] = psize_value;
5876 if (outinfo->writes_layer == true)
5877 pos_args[1].out[2] = layer_value;
5878 if (outinfo->writes_viewport_index == true) {
5879 if (ctx->options->chip_class >= GFX9) {
5880 /* GFX9 has the layer in out.z[10:0] and the viewport
5881 * index in out.z[19:16].
5882 */
5883 LLVMValueRef v = viewport_index_value;
5884 v = ac_to_integer(&ctx->ac, v);
5885 v = LLVMBuildShl(ctx->builder, v,
5886 LLVMConstInt(ctx->ac.i32, 16, false),
5887 "");
5888 v = LLVMBuildOr(ctx->builder, v,
5889 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5890
5891 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5892 pos_args[1].enabled_channels |= 1 << 2;
5893 } else {
5894 pos_args[1].out[3] = viewport_index_value;
5895 pos_args[1].enabled_channels |= 1 << 3;
5896 }
5897 }
5898 }
5899 for (i = 0; i < 4; i++) {
5900 if (pos_args[i].out[0])
5901 num_pos_exports++;
5902 }
5903
5904 pos_idx = 0;
5905 for (i = 0; i < 4; i++) {
5906 if (!pos_args[i].out[0])
5907 continue;
5908
5909 /* Specify the target we are exporting */
5910 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5911 if (pos_idx == num_pos_exports)
5912 pos_args[i].done = 1;
5913 ac_build_export(&ctx->ac, &pos_args[i]);
5914 }
5915
5916 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5917 LLVMValueRef values[4];
5918 if (!(ctx->output_mask & (1ull << i)))
5919 continue;
5920
5921 for (unsigned j = 0; j < 4; j++)
5922 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5923 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5924
5925 if (i == VARYING_SLOT_LAYER) {
5926 target = V_008DFC_SQ_EXP_PARAM + param_count;
5927 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5928 param_count++;
5929 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5930 target = V_008DFC_SQ_EXP_PARAM + param_count;
5931 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5932 param_count++;
5933 } else if (i >= VARYING_SLOT_VAR0) {
5934 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5935 target = V_008DFC_SQ_EXP_PARAM + param_count;
5936 outinfo->vs_output_param_offset[i] = param_count;
5937 param_count++;
5938 } else
5939 continue;
5940
5941 si_llvm_init_export_args(ctx, values, target, &args);
5942
5943 if (target >= V_008DFC_SQ_EXP_POS &&
5944 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5945 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5946 &args, sizeof(args));
5947 } else {
5948 ac_build_export(&ctx->ac, &args);
5949 }
5950 }
5951
5952 if (export_prim_id) {
5953 LLVMValueRef values[4];
5954 target = V_008DFC_SQ_EXP_PARAM + param_count;
5955 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5956 param_count++;
5957
5958 values[0] = ctx->vs_prim_id;
5959 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5960 ctx->shader_info->vs.vgpr_comp_cnt);
5961 for (unsigned j = 1; j < 4; j++)
5962 values[j] = ctx->ac.f32_0;
5963 si_llvm_init_export_args(ctx, values, target, &args);
5964 ac_build_export(&ctx->ac, &args);
5965 outinfo->export_prim_id = true;
5966 }
5967
5968 outinfo->pos_exports = num_pos_exports;
5969 outinfo->param_exports = param_count;
5970 }
5971
5972 static void
5973 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5974 struct ac_es_output_info *outinfo)
5975 {
5976 int j;
5977 uint64_t max_output_written = 0;
5978 LLVMValueRef lds_base = NULL;
5979
5980 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5981 int param_index;
5982 int length = 4;
5983
5984 if (!(ctx->output_mask & (1ull << i)))
5985 continue;
5986
5987 if (i == VARYING_SLOT_CLIP_DIST0)
5988 length = ctx->num_output_clips + ctx->num_output_culls;
5989
5990 param_index = shader_io_get_unique_index(i);
5991
5992 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5993 }
5994
5995 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5996
5997 if (ctx->ac.chip_class >= GFX9) {
5998 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5999 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6000 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6001 LLVMConstInt(ctx->ac.i32, 24, false),
6002 LLVMConstInt(ctx->ac.i32, 4, false), false);
6003 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6004 LLVMBuildMul(ctx->ac.builder, wave_idx,
6005 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6006 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6007 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6008 }
6009
6010 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6011 LLVMValueRef dw_addr;
6012 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6013 int param_index;
6014 int length = 4;
6015
6016 if (!(ctx->output_mask & (1ull << i)))
6017 continue;
6018
6019 if (i == VARYING_SLOT_CLIP_DIST0)
6020 length = ctx->num_output_clips + ctx->num_output_culls;
6021
6022 param_index = shader_io_get_unique_index(i);
6023
6024 if (lds_base) {
6025 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6026 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6027 "");
6028 }
6029 for (j = 0; j < length; j++) {
6030 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6031 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6032
6033 if (ctx->ac.chip_class >= GFX9) {
6034 ac_lds_store(&ctx->ac, dw_addr,
6035 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6036 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6037 } else {
6038 ac_build_buffer_store_dword(&ctx->ac,
6039 ctx->esgs_ring,
6040 out_val, 1,
6041 NULL, ctx->es2gs_offset,
6042 (4 * param_index + j) * 4,
6043 1, 1, true, true);
6044 }
6045 }
6046 }
6047 }
6048
6049 static void
6050 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6051 {
6052 LLVMValueRef vertex_id = ctx->rel_auto_id;
6053 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6054 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6055 vertex_dw_stride, "");
6056
6057 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6058 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6059 int length = 4;
6060
6061 if (!(ctx->output_mask & (1ull << i)))
6062 continue;
6063
6064 if (i == VARYING_SLOT_CLIP_DIST0)
6065 length = ctx->num_output_clips + ctx->num_output_culls;
6066 int param = shader_io_get_unique_index(i);
6067 mark_tess_output(ctx, false, param);
6068 if (length > 4)
6069 mark_tess_output(ctx, false, param + 1);
6070 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6071 LLVMConstInt(ctx->ac.i32, param * 4, false),
6072 "");
6073 for (unsigned j = 0; j < length; j++) {
6074 ac_lds_store(&ctx->ac, dw_addr,
6075 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6076 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6077 }
6078 }
6079 }
6080
6081 struct ac_build_if_state
6082 {
6083 struct nir_to_llvm_context *ctx;
6084 LLVMValueRef condition;
6085 LLVMBasicBlockRef entry_block;
6086 LLVMBasicBlockRef true_block;
6087 LLVMBasicBlockRef false_block;
6088 LLVMBasicBlockRef merge_block;
6089 };
6090
6091 static LLVMBasicBlockRef
6092 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6093 {
6094 LLVMBasicBlockRef current_block;
6095 LLVMBasicBlockRef next_block;
6096 LLVMBasicBlockRef new_block;
6097
6098 /* get current basic block */
6099 current_block = LLVMGetInsertBlock(ctx->builder);
6100
6101 /* chqeck if there's another block after this one */
6102 next_block = LLVMGetNextBasicBlock(current_block);
6103 if (next_block) {
6104 /* insert the new block before the next block */
6105 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6106 }
6107 else {
6108 /* append new block after current block */
6109 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6110 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6111 }
6112 return new_block;
6113 }
6114
6115 static void
6116 ac_nir_build_if(struct ac_build_if_state *ifthen,
6117 struct nir_to_llvm_context *ctx,
6118 LLVMValueRef condition)
6119 {
6120 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6121
6122 memset(ifthen, 0, sizeof *ifthen);
6123 ifthen->ctx = ctx;
6124 ifthen->condition = condition;
6125 ifthen->entry_block = block;
6126
6127 /* create endif/merge basic block for the phi functions */
6128 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6129
6130 /* create/insert true_block before merge_block */
6131 ifthen->true_block =
6132 LLVMInsertBasicBlockInContext(ctx->context,
6133 ifthen->merge_block,
6134 "if-true-block");
6135
6136 /* successive code goes into the true block */
6137 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6138 }
6139
6140 /**
6141 * End a conditional.
6142 */
6143 static void
6144 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6145 {
6146 LLVMBuilderRef builder = ifthen->ctx->builder;
6147
6148 /* Insert branch to the merge block from current block */
6149 LLVMBuildBr(builder, ifthen->merge_block);
6150
6151 /*
6152 * Now patch in the various branch instructions.
6153 */
6154
6155 /* Insert the conditional branch instruction at the end of entry_block */
6156 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6157 if (ifthen->false_block) {
6158 /* we have an else clause */
6159 LLVMBuildCondBr(builder, ifthen->condition,
6160 ifthen->true_block, ifthen->false_block);
6161 }
6162 else {
6163 /* no else clause */
6164 LLVMBuildCondBr(builder, ifthen->condition,
6165 ifthen->true_block, ifthen->merge_block);
6166 }
6167
6168 /* Resume building code at end of the ifthen->merge_block */
6169 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6170 }
6171
6172 static void
6173 write_tess_factors(struct nir_to_llvm_context *ctx)
6174 {
6175 unsigned stride, outer_comps, inner_comps;
6176 struct ac_build_if_state if_ctx, inner_if_ctx;
6177 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6178 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6179 unsigned tess_inner_index, tess_outer_index;
6180 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6181 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6182 int i;
6183 emit_barrier(&ctx->ac, ctx->stage);
6184
6185 switch (ctx->options->key.tcs.primitive_mode) {
6186 case GL_ISOLINES:
6187 stride = 2;
6188 outer_comps = 2;
6189 inner_comps = 0;
6190 break;
6191 case GL_TRIANGLES:
6192 stride = 4;
6193 outer_comps = 3;
6194 inner_comps = 1;
6195 break;
6196 case GL_QUADS:
6197 stride = 6;
6198 outer_comps = 4;
6199 inner_comps = 2;
6200 break;
6201 default:
6202 return;
6203 }
6204
6205 ac_nir_build_if(&if_ctx, ctx,
6206 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6207 invocation_id, ctx->ac.i32_0, ""));
6208
6209 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6210 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6211
6212 mark_tess_output(ctx, true, tess_inner_index);
6213 mark_tess_output(ctx, true, tess_outer_index);
6214 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6215 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6216 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6217 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6218 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6219
6220 for (i = 0; i < 4; i++) {
6221 inner[i] = LLVMGetUndef(ctx->ac.i32);
6222 outer[i] = LLVMGetUndef(ctx->ac.i32);
6223 }
6224
6225 // LINES reverseal
6226 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6227 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6228 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6229 ctx->ac.i32_1, "");
6230 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6231 } else {
6232 for (i = 0; i < outer_comps; i++) {
6233 outer[i] = out[i] =
6234 ac_lds_load(&ctx->ac, lds_outer);
6235 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6236 ctx->ac.i32_1, "");
6237 }
6238 for (i = 0; i < inner_comps; i++) {
6239 inner[i] = out[outer_comps+i] =
6240 ac_lds_load(&ctx->ac, lds_inner);
6241 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6242 ctx->ac.i32_1, "");
6243 }
6244 }
6245
6246 /* Convert the outputs to vectors for stores. */
6247 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6248 vec1 = NULL;
6249
6250 if (stride > 4)
6251 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6252
6253
6254 buffer = ctx->hs_ring_tess_factor;
6255 tf_base = ctx->tess_factor_offset;
6256 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6257 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6258 unsigned tf_offset = 0;
6259
6260 if (ctx->options->chip_class <= VI) {
6261 ac_nir_build_if(&inner_if_ctx, ctx,
6262 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6263 rel_patch_id, ctx->ac.i32_0, ""));
6264
6265 /* Store the dynamic HS control word. */
6266 ac_build_buffer_store_dword(&ctx->ac, buffer,
6267 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6268 1, ctx->ac.i32_0, tf_base,
6269 0, 1, 0, true, false);
6270 tf_offset += 4;
6271
6272 ac_nir_build_endif(&inner_if_ctx);
6273 }
6274
6275 /* Store the tessellation factors. */
6276 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6277 MIN2(stride, 4), byteoffset, tf_base,
6278 tf_offset, 1, 0, true, false);
6279 if (vec1)
6280 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6281 stride - 4, byteoffset, tf_base,
6282 16 + tf_offset, 1, 0, true, false);
6283
6284 //store to offchip for TES to read - only if TES reads them
6285 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6286 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6287 LLVMValueRef tf_inner_offset;
6288 unsigned param_outer, param_inner;
6289
6290 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6291 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6292 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6293
6294 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6295 util_next_power_of_two(outer_comps));
6296
6297 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6298 outer_comps, tf_outer_offset,
6299 ctx->oc_lds, 0, 1, 0, true, false);
6300 if (inner_comps) {
6301 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6302 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6303 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6304
6305 inner_vec = inner_comps == 1 ? inner[0] :
6306 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6307 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6308 inner_comps, tf_inner_offset,
6309 ctx->oc_lds, 0, 1, 0, true, false);
6310 }
6311 }
6312 ac_nir_build_endif(&if_ctx);
6313 }
6314
6315 static void
6316 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6317 {
6318 write_tess_factors(ctx);
6319 }
6320
6321 static bool
6322 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6323 LLVMValueRef *color, unsigned param, bool is_last,
6324 struct ac_export_args *args)
6325 {
6326 /* Export */
6327 si_llvm_init_export_args(ctx, color, param,
6328 args);
6329
6330 if (is_last) {
6331 args->valid_mask = 1; /* whether the EXEC mask is valid */
6332 args->done = 1; /* DONE bit */
6333 } else if (!args->enabled_channels)
6334 return false; /* unnecessary NULL export */
6335
6336 return true;
6337 }
6338
6339 static void
6340 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6341 LLVMValueRef depth, LLVMValueRef stencil,
6342 LLVMValueRef samplemask)
6343 {
6344 struct ac_export_args args;
6345
6346 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6347
6348 ac_build_export(&ctx->ac, &args);
6349 }
6350
6351 static void
6352 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6353 {
6354 unsigned index = 0;
6355 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6356 struct ac_export_args color_args[8];
6357
6358 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6359 LLVMValueRef values[4];
6360
6361 if (!(ctx->output_mask & (1ull << i)))
6362 continue;
6363
6364 if (i == FRAG_RESULT_DEPTH) {
6365 ctx->shader_info->fs.writes_z = true;
6366 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6367 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6368 } else if (i == FRAG_RESULT_STENCIL) {
6369 ctx->shader_info->fs.writes_stencil = true;
6370 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6371 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6372 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6373 ctx->shader_info->fs.writes_sample_mask = true;
6374 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6375 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6376 } else {
6377 bool last = false;
6378 for (unsigned j = 0; j < 4; j++)
6379 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6380 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6381
6382 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6383 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6384
6385 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6386 if (ret)
6387 index++;
6388 }
6389 }
6390
6391 for (unsigned i = 0; i < index; i++)
6392 ac_build_export(&ctx->ac, &color_args[i]);
6393 if (depth || stencil || samplemask)
6394 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6395 else if (!index) {
6396 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6397 ac_build_export(&ctx->ac, &color_args[0]);
6398 }
6399
6400 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6401 }
6402
6403 static void
6404 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6405 {
6406 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6407 }
6408
6409 static void
6410 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6411 LLVMValueRef *addrs)
6412 {
6413 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6414
6415 switch (ctx->stage) {
6416 case MESA_SHADER_VERTEX:
6417 if (ctx->options->key.vs.as_ls)
6418 handle_ls_outputs_post(ctx);
6419 else if (ctx->options->key.vs.as_es)
6420 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6421 else
6422 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6423 &ctx->shader_info->vs.outinfo);
6424 break;
6425 case MESA_SHADER_FRAGMENT:
6426 handle_fs_outputs_post(ctx);
6427 break;
6428 case MESA_SHADER_GEOMETRY:
6429 emit_gs_epilogue(ctx);
6430 break;
6431 case MESA_SHADER_TESS_CTRL:
6432 handle_tcs_outputs_post(ctx);
6433 break;
6434 case MESA_SHADER_TESS_EVAL:
6435 if (ctx->options->key.tes.as_es)
6436 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6437 else
6438 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6439 &ctx->shader_info->tes.outinfo);
6440 break;
6441 default:
6442 break;
6443 }
6444 }
6445
6446 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6447 {
6448 LLVMPassManagerRef passmgr;
6449 /* Create the pass manager */
6450 passmgr = LLVMCreateFunctionPassManagerForModule(
6451 ctx->module);
6452
6453 /* This pass should eliminate all the load and store instructions */
6454 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6455
6456 /* Add some optimization passes */
6457 LLVMAddScalarReplAggregatesPass(passmgr);
6458 LLVMAddLICMPass(passmgr);
6459 LLVMAddAggressiveDCEPass(passmgr);
6460 LLVMAddCFGSimplificationPass(passmgr);
6461 LLVMAddInstructionCombiningPass(passmgr);
6462
6463 /* Run the pass */
6464 LLVMInitializeFunctionPassManager(passmgr);
6465 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6466 LLVMFinalizeFunctionPassManager(passmgr);
6467
6468 LLVMDisposeBuilder(ctx->builder);
6469 LLVMDisposePassManager(passmgr);
6470 }
6471
6472 static void
6473 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6474 {
6475 struct ac_vs_output_info *outinfo;
6476
6477 switch (ctx->stage) {
6478 case MESA_SHADER_FRAGMENT:
6479 case MESA_SHADER_COMPUTE:
6480 case MESA_SHADER_TESS_CTRL:
6481 case MESA_SHADER_GEOMETRY:
6482 return;
6483 case MESA_SHADER_VERTEX:
6484 if (ctx->options->key.vs.as_ls ||
6485 ctx->options->key.vs.as_es)
6486 return;
6487 outinfo = &ctx->shader_info->vs.outinfo;
6488 break;
6489 case MESA_SHADER_TESS_EVAL:
6490 if (ctx->options->key.vs.as_es)
6491 return;
6492 outinfo = &ctx->shader_info->tes.outinfo;
6493 break;
6494 default:
6495 unreachable("Unhandled shader type");
6496 }
6497
6498 ac_optimize_vs_outputs(&ctx->ac,
6499 ctx->main_function,
6500 outinfo->vs_output_param_offset,
6501 VARYING_SLOT_MAX,
6502 &outinfo->param_exports);
6503 }
6504
6505 static void
6506 ac_setup_rings(struct nir_to_llvm_context *ctx)
6507 {
6508 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6509 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6510 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6511 }
6512
6513 if (ctx->is_gs_copy_shader) {
6514 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6515 }
6516 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6517 LLVMValueRef tmp;
6518 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6519 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6520
6521 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6522
6523 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6524 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6525 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6526 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6527 }
6528
6529 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6530 ctx->stage == MESA_SHADER_TESS_EVAL) {
6531 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6532 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6533 }
6534 }
6535
6536 static unsigned
6537 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6538 const struct nir_shader *nir)
6539 {
6540 switch (nir->info.stage) {
6541 case MESA_SHADER_TESS_CTRL:
6542 return chip_class >= CIK ? 128 : 64;
6543 case MESA_SHADER_GEOMETRY:
6544 return chip_class >= GFX9 ? 128 : 64;
6545 case MESA_SHADER_COMPUTE:
6546 break;
6547 default:
6548 return 0;
6549 }
6550
6551 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6552 nir->info.cs.local_size[1] *
6553 nir->info.cs.local_size[2];
6554 return max_workgroup_size;
6555 }
6556
6557 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6558 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6559 {
6560 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6561 LLVMConstInt(ctx->ac.i32, 8, false),
6562 LLVMConstInt(ctx->ac.i32, 8, false), false);
6563 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6564 ctx->ac.i32_0, "");
6565 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6566 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6567 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6568 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6569 }
6570
6571 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6572 {
6573 for(int i = 5; i >= 0; --i) {
6574 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6575 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6576 LLVMConstInt(ctx->ac.i32, 16, false), false);
6577 }
6578
6579 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6580 LLVMConstInt(ctx->ac.i32, 16, false),
6581 LLVMConstInt(ctx->ac.i32, 8, false), false);
6582 }
6583
6584 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6585 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6586 {
6587 struct ac_nir_context ctx = {};
6588 struct nir_function *func;
6589
6590 ctx.ac = *ac;
6591 ctx.abi = abi;
6592
6593 ctx.nctx = nctx;
6594 if (nctx)
6595 nctx->nir = &ctx;
6596
6597 ctx.stage = nir->info.stage;
6598
6599 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6600
6601 nir_foreach_variable(variable, &nir->outputs)
6602 handle_shader_output_decl(&ctx, nir, variable);
6603
6604 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6605 _mesa_key_pointer_equal);
6606 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6607 _mesa_key_pointer_equal);
6608 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6609 _mesa_key_pointer_equal);
6610
6611 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6612
6613 setup_locals(&ctx, func);
6614
6615 if (nir->info.stage == MESA_SHADER_COMPUTE)
6616 setup_shared(&ctx, nir);
6617
6618 visit_cf_list(&ctx, &func->impl->body);
6619 phi_post_pass(&ctx);
6620
6621 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6622 ctx.outputs);
6623
6624 free(ctx.locals);
6625 ralloc_free(ctx.defs);
6626 ralloc_free(ctx.phis);
6627 ralloc_free(ctx.vars);
6628
6629 if (nctx)
6630 nctx->nir = NULL;
6631 }
6632
6633 static
6634 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6635 struct nir_shader *const *shaders,
6636 int shader_count,
6637 struct ac_shader_variant_info *shader_info,
6638 const struct ac_nir_compiler_options *options)
6639 {
6640 struct nir_to_llvm_context ctx = {0};
6641 unsigned i;
6642 ctx.options = options;
6643 ctx.shader_info = shader_info;
6644 ctx.context = LLVMContextCreate();
6645 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6646
6647 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6648 options->family);
6649 ctx.ac.module = ctx.module;
6650 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6651
6652 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6653 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6654 LLVMSetDataLayout(ctx.module, data_layout_str);
6655 LLVMDisposeTargetData(data_layout);
6656 LLVMDisposeMessage(data_layout_str);
6657
6658 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6659 ctx.ac.builder = ctx.builder;
6660
6661 memset(shader_info, 0, sizeof(*shader_info));
6662
6663 for(int i = 0; i < shader_count; ++i)
6664 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6665
6666 for (i = 0; i < AC_UD_MAX_SETS; i++)
6667 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6668 for (i = 0; i < AC_UD_MAX_UD; i++)
6669 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6670
6671 ctx.max_workgroup_size = 0;
6672 for (int i = 0; i < shader_count; ++i) {
6673 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6674 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6675 shaders[i]));
6676 }
6677
6678 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6679 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6680
6681 ctx.abi.inputs = &ctx.inputs[0];
6682 ctx.abi.emit_outputs = handle_shader_outputs_post;
6683 ctx.abi.emit_vertex = visit_emit_vertex;
6684 ctx.abi.load_ubo = radv_load_ubo;
6685 ctx.abi.load_ssbo = radv_load_ssbo;
6686 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6687 ctx.abi.clamp_shadow_reference = false;
6688
6689 if (shader_count >= 2)
6690 ac_init_exec_full_mask(&ctx.ac);
6691
6692 if (ctx.ac.chip_class == GFX9 &&
6693 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6694 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6695
6696 for(int i = 0; i < shader_count; ++i) {
6697 ctx.stage = shaders[i]->info.stage;
6698 ctx.output_mask = 0;
6699 ctx.tess_outputs_written = 0;
6700 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6701 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6702
6703 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6704 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6705 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6706 ctx.abi.load_inputs = load_gs_input;
6707 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6708 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6709 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6710 ctx.abi.load_tess_inputs = load_tcs_input;
6711 ctx.abi.store_tcs_outputs = store_tcs_output;
6712 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6713 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6714 ctx.abi.load_tess_inputs = load_tes_input;
6715 ctx.abi.load_tess_coord = load_tess_coord;
6716 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6717 if (shader_info->info.vs.needs_instance_id) {
6718 if (ctx.ac.chip_class == GFX9 &&
6719 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) {
6720 ctx.shader_info->vs.vgpr_comp_cnt =
6721 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6722 } else {
6723 ctx.shader_info->vs.vgpr_comp_cnt =
6724 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6725 }
6726 }
6727 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6728 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6729 }
6730
6731 if (i)
6732 emit_barrier(&ctx.ac, ctx.stage);
6733
6734 ac_setup_rings(&ctx);
6735
6736 LLVMBasicBlockRef merge_block;
6737 if (shader_count >= 2) {
6738 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6739 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6740 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6741
6742 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6743 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6744 LLVMConstInt(ctx.ac.i32, 8, false), false);
6745 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6746 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6747 thread_id, count, "");
6748 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6749
6750 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6751 }
6752
6753 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6754 handle_fs_inputs(&ctx, shaders[i]);
6755 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6756 handle_vs_inputs(&ctx, shaders[i]);
6757 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6758 prepare_gs_input_vgprs(&ctx);
6759
6760 nir_foreach_variable(variable, &shaders[i]->outputs)
6761 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6762
6763 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6764
6765 if (shader_count >= 2) {
6766 LLVMBuildBr(ctx.ac.builder, merge_block);
6767 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6768 }
6769
6770 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6771 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6772 shaders[i]->info.cull_distance_array_size > 4;
6773 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6774 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6775 shaders[i]->info.gs.vertices_out;
6776 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6777 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6778 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6779 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6780 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6781 }
6782 }
6783
6784 LLVMBuildRetVoid(ctx.builder);
6785
6786 ac_llvm_finalize_module(&ctx);
6787
6788 if (shader_count == 1)
6789 ac_nir_eliminate_const_vs_outputs(&ctx);
6790
6791 return ctx.module;
6792 }
6793
6794 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6795 {
6796 unsigned *retval = (unsigned *)context;
6797 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6798 char *description = LLVMGetDiagInfoDescription(di);
6799
6800 if (severity == LLVMDSError) {
6801 *retval = 1;
6802 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6803 description);
6804 }
6805
6806 LLVMDisposeMessage(description);
6807 }
6808
6809 static unsigned ac_llvm_compile(LLVMModuleRef M,
6810 struct ac_shader_binary *binary,
6811 LLVMTargetMachineRef tm)
6812 {
6813 unsigned retval = 0;
6814 char *err;
6815 LLVMContextRef llvm_ctx;
6816 LLVMMemoryBufferRef out_buffer;
6817 unsigned buffer_size;
6818 const char *buffer_data;
6819 LLVMBool mem_err;
6820
6821 /* Setup Diagnostic Handler*/
6822 llvm_ctx = LLVMGetModuleContext(M);
6823
6824 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6825 &retval);
6826
6827 /* Compile IR*/
6828 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6829 &err, &out_buffer);
6830
6831 /* Process Errors/Warnings */
6832 if (mem_err) {
6833 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6834 free(err);
6835 retval = 1;
6836 goto out;
6837 }
6838
6839 /* Extract Shader Code*/
6840 buffer_size = LLVMGetBufferSize(out_buffer);
6841 buffer_data = LLVMGetBufferStart(out_buffer);
6842
6843 ac_elf_read(buffer_data, buffer_size, binary);
6844
6845 /* Clean up */
6846 LLVMDisposeMemoryBuffer(out_buffer);
6847
6848 out:
6849 return retval;
6850 }
6851
6852 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6853 LLVMModuleRef llvm_module,
6854 struct ac_shader_binary *binary,
6855 struct ac_shader_config *config,
6856 struct ac_shader_variant_info *shader_info,
6857 gl_shader_stage stage,
6858 bool dump_shader, bool supports_spill)
6859 {
6860 if (dump_shader)
6861 ac_dump_module(llvm_module);
6862
6863 memset(binary, 0, sizeof(*binary));
6864 int v = ac_llvm_compile(llvm_module, binary, tm);
6865 if (v) {
6866 fprintf(stderr, "compile failed\n");
6867 }
6868
6869 if (dump_shader)
6870 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6871
6872 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6873
6874 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6875 LLVMDisposeModule(llvm_module);
6876 LLVMContextDispose(ctx);
6877
6878 if (stage == MESA_SHADER_FRAGMENT) {
6879 shader_info->num_input_vgprs = 0;
6880 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6881 shader_info->num_input_vgprs += 2;
6882 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6883 shader_info->num_input_vgprs += 2;
6884 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6885 shader_info->num_input_vgprs += 2;
6886 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6887 shader_info->num_input_vgprs += 3;
6888 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6889 shader_info->num_input_vgprs += 2;
6890 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6891 shader_info->num_input_vgprs += 2;
6892 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6893 shader_info->num_input_vgprs += 2;
6894 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6895 shader_info->num_input_vgprs += 1;
6896 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6897 shader_info->num_input_vgprs += 1;
6898 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6899 shader_info->num_input_vgprs += 1;
6900 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6901 shader_info->num_input_vgprs += 1;
6902 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6903 shader_info->num_input_vgprs += 1;
6904 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6905 shader_info->num_input_vgprs += 1;
6906 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6907 shader_info->num_input_vgprs += 1;
6908 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6909 shader_info->num_input_vgprs += 1;
6910 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6911 shader_info->num_input_vgprs += 1;
6912 }
6913 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6914
6915 /* +3 for scratch wave offset and VCC */
6916 config->num_sgprs = MAX2(config->num_sgprs,
6917 shader_info->num_input_sgprs + 3);
6918
6919 /* Enable 64-bit and 16-bit denormals, because there is no performance
6920 * cost.
6921 *
6922 * If denormals are enabled, all floating-point output modifiers are
6923 * ignored.
6924 *
6925 * Don't enable denormals for 32-bit floats, because:
6926 * - Floating-point output modifiers would be ignored by the hw.
6927 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6928 * have to stop using those.
6929 * - SI & CI would be very slow.
6930 */
6931 config->float_mode |= V_00B028_FP_64_DENORMS;
6932 }
6933
6934 static void
6935 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6936 {
6937 switch (nir->info.stage) {
6938 case MESA_SHADER_COMPUTE:
6939 for (int i = 0; i < 3; ++i)
6940 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6941 break;
6942 case MESA_SHADER_FRAGMENT:
6943 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6944 break;
6945 case MESA_SHADER_GEOMETRY:
6946 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6947 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6948 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6949 shader_info->gs.invocations = nir->info.gs.invocations;
6950 break;
6951 case MESA_SHADER_TESS_EVAL:
6952 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6953 shader_info->tes.spacing = nir->info.tess.spacing;
6954 shader_info->tes.ccw = nir->info.tess.ccw;
6955 shader_info->tes.point_mode = nir->info.tess.point_mode;
6956 shader_info->tes.as_es = options->key.tes.as_es;
6957 break;
6958 case MESA_SHADER_TESS_CTRL:
6959 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6960 break;
6961 case MESA_SHADER_VERTEX:
6962 shader_info->vs.as_es = options->key.vs.as_es;
6963 shader_info->vs.as_ls = options->key.vs.as_ls;
6964 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6965 if (options->key.vs.as_ls)
6966 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6967 break;
6968 default:
6969 break;
6970 }
6971 }
6972
6973 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6974 struct ac_shader_binary *binary,
6975 struct ac_shader_config *config,
6976 struct ac_shader_variant_info *shader_info,
6977 struct nir_shader *const *nir,
6978 int nir_count,
6979 const struct ac_nir_compiler_options *options,
6980 bool dump_shader)
6981 {
6982
6983 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6984 options);
6985
6986 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6987 for (int i = 0; i < nir_count; ++i)
6988 ac_fill_shader_info(shader_info, nir[i], options);
6989
6990 /* Determine the ES type (VS or TES) for the GS on GFX9. */
6991 if (options->chip_class == GFX9) {
6992 if (nir_count == 2 &&
6993 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
6994 shader_info->gs.es_type = nir[0]->info.stage;
6995 }
6996 }
6997 }
6998
6999 static void
7000 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7001 {
7002 LLVMValueRef args[9];
7003 args[0] = ctx->gsvs_ring;
7004 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7005 args[3] = ctx->ac.i32_0;
7006 args[4] = ctx->ac.i32_1; /* OFFEN */
7007 args[5] = ctx->ac.i32_0; /* IDXEN */
7008 args[6] = ctx->ac.i32_1; /* GLC */
7009 args[7] = ctx->ac.i32_1; /* SLC */
7010 args[8] = ctx->ac.i32_0; /* TFE */
7011
7012 int idx = 0;
7013
7014 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7015 int length = 4;
7016 int slot = idx;
7017 int slot_inc = 1;
7018 if (!(ctx->output_mask & (1ull << i)))
7019 continue;
7020
7021 if (i == VARYING_SLOT_CLIP_DIST0) {
7022 /* unpack clip and cull from a single set of slots */
7023 length = ctx->num_output_clips + ctx->num_output_culls;
7024 if (length > 4)
7025 slot_inc = 2;
7026 }
7027
7028 for (unsigned j = 0; j < length; j++) {
7029 LLVMValueRef value;
7030 args[2] = LLVMConstInt(ctx->ac.i32,
7031 (slot * 4 + j) *
7032 ctx->gs_max_out_vertices * 16 * 4, false);
7033
7034 value = ac_build_intrinsic(&ctx->ac,
7035 "llvm.SI.buffer.load.dword.i32.i32",
7036 ctx->ac.i32, args, 9,
7037 AC_FUNC_ATTR_READONLY |
7038 AC_FUNC_ATTR_LEGACY);
7039
7040 LLVMBuildStore(ctx->builder,
7041 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7042 }
7043 idx += slot_inc;
7044 }
7045 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7046 }
7047
7048 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7049 struct nir_shader *geom_shader,
7050 struct ac_shader_binary *binary,
7051 struct ac_shader_config *config,
7052 struct ac_shader_variant_info *shader_info,
7053 const struct ac_nir_compiler_options *options,
7054 bool dump_shader)
7055 {
7056 struct nir_to_llvm_context ctx = {0};
7057 ctx.context = LLVMContextCreate();
7058 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7059 ctx.options = options;
7060 ctx.shader_info = shader_info;
7061
7062 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7063 options->family);
7064 ctx.ac.module = ctx.module;
7065
7066 ctx.is_gs_copy_shader = true;
7067 LLVMSetTarget(ctx.module, "amdgcn--");
7068
7069 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7070 ctx.ac.builder = ctx.builder;
7071 ctx.stage = MESA_SHADER_VERTEX;
7072
7073 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7074
7075 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7076 ac_setup_rings(&ctx);
7077
7078 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7079 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7080
7081 struct ac_nir_context nir_ctx = {};
7082 nir_ctx.ac = ctx.ac;
7083 nir_ctx.abi = &ctx.abi;
7084
7085 nir_ctx.nctx = &ctx;
7086 ctx.nir = &nir_ctx;
7087
7088 nir_foreach_variable(variable, &geom_shader->outputs) {
7089 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7090 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7091 }
7092
7093 ac_gs_copy_shader_emit(&ctx);
7094
7095 ctx.nir = NULL;
7096
7097 LLVMBuildRetVoid(ctx.builder);
7098
7099 ac_llvm_finalize_module(&ctx);
7100
7101 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7102 MESA_SHADER_VERTEX,
7103 dump_shader, options->supports_spill);
7104 }