projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
amd/common: correctly detect if we need ring buffers
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.needs_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
604 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
605 user_sgpr_info->sgpr_count += 2;
606 user_sgpr_info->indirect_all_descriptor_sets = true;
607 } else {
608 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
609 }
610 }
611
612 static void
613 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
614 gl_shader_stage stage,
615 bool has_previous_stage,
616 gl_shader_stage previous_stage,
617 const struct user_sgpr_info *user_sgpr_info,
618 struct arg_info *args,
619 LLVMValueRef *desc_sets)
620 {
621 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
622 unsigned num_sets = ctx->options->layout ?
623 ctx->options->layout->num_sets : 0;
624 unsigned stage_mask = 1 << stage;
625
626 if (has_previous_stage)
627 stage_mask |= 1 << previous_stage;
628
629 /* 1 for each descriptor set */
630 if (!user_sgpr_info->indirect_all_descriptor_sets) {
631 for (unsigned i = 0; i < num_sets; ++i) {
632 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
633 add_array_arg(args, type,
634 &ctx->descriptor_sets[i]);
635 }
636 }
637 } else {
638 add_array_arg(args, const_array(type, 32), desc_sets);
639 }
640
641 if (ctx->shader_info->info.needs_push_constants) {
642 /* 1 for push constants and dynamic descriptors */
643 add_array_arg(args, type, &ctx->push_constants);
644 }
645 }
646
647 static void
648 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
649 gl_shader_stage stage,
650 bool has_previous_stage,
651 gl_shader_stage previous_stage,
652 struct arg_info *args)
653 {
654 if (!ctx->is_gs_copy_shader &&
655 (stage == MESA_SHADER_VERTEX ||
656 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
657 if (ctx->shader_info->info.vs.has_vertex_buffers) {
658 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
659 &ctx->vertex_buffers);
660 }
661 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
663 if (ctx->shader_info->info.vs.needs_draw_id) {
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
665 }
666 }
667 }
668
669 static void
670 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
671 {
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
673 if (!ctx->is_gs_copy_shader) {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
677 }
678 }
679
680 static void
681 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
682 {
683 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
684 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
685 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
686 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
687 }
688
689 static void
690 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
691 bool has_previous_stage, gl_shader_stage previous_stage,
692 const struct user_sgpr_info *user_sgpr_info,
693 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
694 {
695 unsigned num_sets = ctx->options->layout ?
696 ctx->options->layout->num_sets : 0;
697 unsigned stage_mask = 1 << stage;
698
699 if (has_previous_stage)
700 stage_mask |= 1 << previous_stage;
701
702 if (!user_sgpr_info->indirect_all_descriptor_sets) {
703 for (unsigned i = 0; i < num_sets; ++i) {
704 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
705 set_loc_desc(ctx, i, user_sgpr_idx, 0);
706 } else
707 ctx->descriptor_sets[i] = NULL;
708 }
709 } else {
710 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
711 user_sgpr_idx, 2);
712
713 for (unsigned i = 0; i < num_sets; ++i) {
714 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
715 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
716 ctx->descriptor_sets[i] =
717 ac_build_load_to_sgpr(&ctx->ac,
718 desc_sets,
719 LLVMConstInt(ctx->ac.i32, i, false));
720
721 } else
722 ctx->descriptor_sets[i] = NULL;
723 }
724 ctx->shader_info->need_indirect_descriptor_sets = true;
725 }
726
727 if (ctx->shader_info->info.needs_push_constants) {
728 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
729 }
730 }
731
732 static void
733 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
734 gl_shader_stage stage, bool has_previous_stage,
735 gl_shader_stage previous_stage,
736 uint8_t *user_sgpr_idx)
737 {
738 if (!ctx->is_gs_copy_shader &&
739 (stage == MESA_SHADER_VERTEX ||
740 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
741 if (ctx->shader_info->info.vs.has_vertex_buffers) {
742 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
743 user_sgpr_idx, 2);
744 }
745
746 unsigned vs_num = 2;
747 if (ctx->shader_info->info.vs.needs_draw_id)
748 vs_num++;
749
750 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
751 user_sgpr_idx, vs_num);
752 }
753 }
754
755 static void create_function(struct nir_to_llvm_context *ctx,
756 gl_shader_stage stage,
757 bool has_previous_stage,
758 gl_shader_stage previous_stage)
759 {
760 uint8_t user_sgpr_idx;
761 struct user_sgpr_info user_sgpr_info;
762 struct arg_info args = {};
763 LLVMValueRef desc_sets;
764
765 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
766
767 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
768 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
769 &ctx->ring_offsets);
770 }
771
772 switch (stage) {
773 case MESA_SHADER_COMPUTE:
774 declare_global_input_sgprs(ctx, stage, has_previous_stage,
775 previous_stage, &user_sgpr_info,
776 &args, &desc_sets);
777
778 if (ctx->shader_info->info.cs.uses_grid_size) {
779 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
780 &ctx->num_work_groups);
781 }
782
783 for (int i = 0; i < 3; i++) {
784 ctx->workgroup_ids[i] = NULL;
785 if (ctx->shader_info->info.cs.uses_block_id[i]) {
786 add_arg(&args, ARG_SGPR, ctx->ac.i32,
787 &ctx->workgroup_ids[i]);
788 }
789 }
790
791 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
792 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
793 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
794 &ctx->local_invocation_ids);
795 break;
796 case MESA_SHADER_VERTEX:
797 declare_global_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &user_sgpr_info,
799 &args, &desc_sets);
800 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
801 previous_stage, &args);
802
803 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
804 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
805 if (ctx->options->key.vs.as_es)
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->es2gs_offset);
808 else if (ctx->options->key.vs.as_ls)
809 add_arg(&args, ARG_SGPR, ctx->ac.i32,
810 &ctx->ls_out_layout);
811
812 declare_vs_input_vgprs(ctx, &args);
813 break;
814 case MESA_SHADER_TESS_CTRL:
815 if (has_previous_stage) {
816 // First 6 system regs
817 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->merged_wave_info);
820 add_arg(&args, ARG_SGPR, ctx->ac.i32,
821 &ctx->tess_factor_offset);
822
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
825 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
826
827 declare_global_input_sgprs(ctx, stage,
828 has_previous_stage,
829 previous_stage,
830 &user_sgpr_info, &args,
831 &desc_sets);
832 declare_vs_specific_input_sgprs(ctx, stage,
833 has_previous_stage,
834 previous_stage, &args);
835
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->ls_out_layout);
838
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_offchip_layout);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_offsets);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_out_layout);
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->tcs_in_layout);
847 if (ctx->shader_info->info.needs_multiview_view_index)
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->view_index);
850
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_patch_id);
853 add_arg(&args, ARG_VGPR, ctx->ac.i32,
854 &ctx->abi.tcs_rel_ids);
855
856 declare_vs_input_vgprs(ctx, &args);
857 } else {
858 declare_global_input_sgprs(ctx, stage,
859 has_previous_stage,
860 previous_stage,
861 &user_sgpr_info, &args,
862 &desc_sets);
863
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_offchip_layout);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_offsets);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_out_layout);
870 add_arg(&args, ARG_SGPR, ctx->ac.i32,
871 &ctx->tcs_in_layout);
872 if (ctx->shader_info->info.needs_multiview_view_index)
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->view_index);
875
876 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tess_factor_offset);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_patch_id);
881 add_arg(&args, ARG_VGPR, ctx->ac.i32,
882 &ctx->abi.tcs_rel_ids);
883 }
884 break;
885 case MESA_SHADER_TESS_EVAL:
886 declare_global_input_sgprs(ctx, stage, has_previous_stage,
887 previous_stage, &user_sgpr_info,
888 &args, &desc_sets);
889
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
891 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
892 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
893
894 if (ctx->options->key.tes.as_es) {
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32,
898 &ctx->es2gs_offset);
899 } else {
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
902 }
903 declare_tes_input_vgprs(ctx, &args);
904 break;
905 case MESA_SHADER_GEOMETRY:
906 if (has_previous_stage) {
907 // First 6 system regs
908 add_arg(&args, ARG_SGPR, ctx->ac.i32,
909 &ctx->gs2vs_offset);
910 add_arg(&args, ARG_SGPR, ctx->ac.i32,
911 &ctx->merged_wave_info);
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
913
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
917
918 declare_global_input_sgprs(ctx, stage,
919 has_previous_stage,
920 previous_stage,
921 &user_sgpr_info, &args,
922 &desc_sets);
923
924 if (previous_stage == MESA_SHADER_TESS_EVAL) {
925 add_arg(&args, ARG_SGPR, ctx->ac.i32,
926 &ctx->tcs_offchip_layout);
927 } else {
928 declare_vs_specific_input_sgprs(ctx, stage,
929 has_previous_stage,
930 previous_stage,
931 &args);
932 }
933
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->gsvs_ring_stride);
936 add_arg(&args, ARG_SGPR, ctx->ac.i32,
937 &ctx->gsvs_num_entries);
938 if (ctx->shader_info->info.needs_multiview_view_index)
939 add_arg(&args, ARG_SGPR, ctx->ac.i32,
940 &ctx->view_index);
941
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[0]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->gs_vtx_offset[2]);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->abi.gs_prim_id);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->abi.gs_invocation_id);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->gs_vtx_offset[4]);
952
953 if (previous_stage == MESA_SHADER_VERTEX) {
954 declare_vs_input_vgprs(ctx, &args);
955 } else {
956 declare_tes_input_vgprs(ctx, &args);
957 }
958 } else {
959 declare_global_input_sgprs(ctx, stage,
960 has_previous_stage,
961 previous_stage,
962 &user_sgpr_info, &args,
963 &desc_sets);
964
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->gsvs_ring_stride);
967 add_arg(&args, ARG_SGPR, ctx->ac.i32,
968 &ctx->gsvs_num_entries);
969 if (ctx->shader_info->info.needs_multiview_view_index)
970 add_arg(&args, ARG_SGPR, ctx->ac.i32,
971 &ctx->view_index);
972
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
974 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[0]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->gs_vtx_offset[1]);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->abi.gs_prim_id);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[2]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[3]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[4]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->gs_vtx_offset[5]);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->abi.gs_invocation_id);
991 }
992 break;
993 case MESA_SHADER_FRAGMENT:
994 declare_global_input_sgprs(ctx, stage, has_previous_stage,
995 previous_stage, &user_sgpr_info,
996 &args, &desc_sets);
997
998 if (ctx->shader_info->info.ps.needs_sample_positions)
999 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1000 &ctx->sample_pos_offset);
1001
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1019 break;
1020 default:
1021 unreachable("Shader stage not implemented");
1022 }
1023
1024 ctx->main_function = create_llvm_function(
1025 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1026 ctx->max_workgroup_size,
1027 ctx->options->unsafe_math);
1028 set_llvm_calling_convention(ctx->main_function, stage);
1029
1030
1031 ctx->shader_info->num_input_vgprs = 0;
1032 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1033
1034 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1035
1036 if (ctx->stage != MESA_SHADER_FRAGMENT)
1037 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1038
1039 assign_arguments(ctx->main_function, &args);
1040
1041 user_sgpr_idx = 0;
1042
1043 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1044 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1045 &user_sgpr_idx, 2);
1046 if (ctx->options->supports_spill) {
1047 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1048 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1049 NULL, 0, AC_FUNC_ATTR_READNONE);
1050 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1051 const_array(ctx->ac.v4i32, 16), "");
1052 }
1053 }
1054
1055 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1056 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1057 if (has_previous_stage)
1058 user_sgpr_idx = 0;
1059
1060 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1061 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1062
1063 switch (stage) {
1064 case MESA_SHADER_COMPUTE:
1065 if (ctx->shader_info->info.cs.uses_grid_size) {
1066 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1067 &user_sgpr_idx, 3);
1068 }
1069 break;
1070 case MESA_SHADER_VERTEX:
1071 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1072 previous_stage, &user_sgpr_idx);
1073 if (ctx->view_index)
1074 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1075 if (ctx->options->key.vs.as_ls) {
1076 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1077 &user_sgpr_idx, 1);
1078 }
1079 if (ctx->options->key.vs.as_ls)
1080 ac_declare_lds_as_pointer(&ctx->ac);
1081 break;
1082 case MESA_SHADER_TESS_CTRL:
1083 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1084 previous_stage, &user_sgpr_idx);
1085 if (has_previous_stage)
1086 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1087 &user_sgpr_idx, 1);
1088 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1089 if (ctx->view_index)
1090 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1091 ac_declare_lds_as_pointer(&ctx->ac);
1092 break;
1093 case MESA_SHADER_TESS_EVAL:
1094 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1095 if (ctx->view_index)
1096 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1097 break;
1098 case MESA_SHADER_GEOMETRY:
1099 if (has_previous_stage) {
1100 if (previous_stage == MESA_SHADER_VERTEX)
1101 set_vs_specific_input_locs(ctx, stage,
1102 has_previous_stage,
1103 previous_stage,
1104 &user_sgpr_idx);
1105 else
1106 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1107 &user_sgpr_idx, 1);
1108 }
1109 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1110 &user_sgpr_idx, 2);
1111 if (ctx->view_index)
1112 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1113 if (has_previous_stage)
1114 ac_declare_lds_as_pointer(&ctx->ac);
1115 break;
1116 case MESA_SHADER_FRAGMENT:
1117 if (ctx->shader_info->info.ps.needs_sample_positions) {
1118 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1119 &user_sgpr_idx, 1);
1120 }
1121 break;
1122 default:
1123 unreachable("Shader stage not implemented");
1124 }
1125
1126 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1127 }
1128
1129 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1130 LLVMValueRef value, unsigned count)
1131 {
1132 unsigned num_components = ac_get_llvm_num_components(value);
1133 if (count == num_components)
1134 return value;
1135
1136 LLVMValueRef masks[] = {
1137 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1138 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1139
1140 if (count == 1)
1141 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1142 "");
1143
1144 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1145 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1146 }
1147
1148 static void
1149 build_store_values_extended(struct ac_llvm_context *ac,
1150 LLVMValueRef *values,
1151 unsigned value_count,
1152 unsigned value_stride,
1153 LLVMValueRef vec)
1154 {
1155 LLVMBuilderRef builder = ac->builder;
1156 unsigned i;
1157
1158 for (i = 0; i < value_count; i++) {
1159 LLVMValueRef ptr = values[i * value_stride];
1160 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1161 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1162 LLVMBuildStore(builder, value, ptr);
1163 }
1164 }
1165
1166 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1167 const nir_ssa_def *def)
1168 {
1169 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1170 if (def->num_components > 1) {
1171 type = LLVMVectorType(type, def->num_components);
1172 }
1173 return type;
1174 }
1175
1176 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1177 {
1178 assert(src.is_ssa);
1179 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1180 return (LLVMValueRef)entry->data;
1181 }
1182
1183
1184 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1185 const struct nir_block *b)
1186 {
1187 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1188 return (LLVMBasicBlockRef)entry->data;
1189 }
1190
1191 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1192 nir_alu_src src,
1193 unsigned num_components)
1194 {
1195 LLVMValueRef value = get_src(ctx, src.src);
1196 bool need_swizzle = false;
1197
1198 assert(value);
1199 LLVMTypeRef type = LLVMTypeOf(value);
1200 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1201 ? LLVMGetVectorSize(type)
1202 : 1;
1203
1204 for (unsigned i = 0; i < num_components; ++i) {
1205 assert(src.swizzle[i] < src_components);
1206 if (src.swizzle[i] != i)
1207 need_swizzle = true;
1208 }
1209
1210 if (need_swizzle || num_components != src_components) {
1211 LLVMValueRef masks[] = {
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1214 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1215 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1216
1217 if (src_components > 1 && num_components == 1) {
1218 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1219 masks[0], "");
1220 } else if (src_components == 1 && num_components > 1) {
1221 LLVMValueRef values[] = {value, value, value, value};
1222 value = ac_build_gather_values(&ctx->ac, values, num_components);
1223 } else {
1224 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1225 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1226 swizzle, "");
1227 }
1228 }
1229 assert(!src.negate);
1230 assert(!src.abs);
1231 return value;
1232 }
1233
1234 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1235 LLVMIntPredicate pred, LLVMValueRef src0,
1236 LLVMValueRef src1)
1237 {
1238 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1239 return LLVMBuildSelect(ctx->builder, result,
1240 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1241 ctx->i32_0, "");
1242 }
1243
1244 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1245 LLVMRealPredicate pred, LLVMValueRef src0,
1246 LLVMValueRef src1)
1247 {
1248 LLVMValueRef result;
1249 src0 = ac_to_float(ctx, src0);
1250 src1 = ac_to_float(ctx, src1);
1251 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1252 return LLVMBuildSelect(ctx->builder, result,
1253 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1254 ctx->i32_0, "");
1255 }
1256
1257 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1258 const char *intrin,
1259 LLVMTypeRef result_type,
1260 LLVMValueRef src0)
1261 {
1262 char name[64];
1263 LLVMValueRef params[] = {
1264 ac_to_float(ctx, src0),
1265 };
1266
1267 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1268 get_elem_bits(ctx, result_type));
1269 assert(length < sizeof(name));
1270 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1271 }
1272
1273 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1274 const char *intrin,
1275 LLVMTypeRef result_type,
1276 LLVMValueRef src0, LLVMValueRef src1)
1277 {
1278 char name[64];
1279 LLVMValueRef params[] = {
1280 ac_to_float(ctx, src0),
1281 ac_to_float(ctx, src1),
1282 };
1283
1284 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1285 get_elem_bits(ctx, result_type));
1286 assert(length < sizeof(name));
1287 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1288 }
1289
1290 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1291 const char *intrin,
1292 LLVMTypeRef result_type,
1293 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1294 {
1295 char name[64];
1296 LLVMValueRef params[] = {
1297 ac_to_float(ctx, src0),
1298 ac_to_float(ctx, src1),
1299 ac_to_float(ctx, src2),
1300 };
1301
1302 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1303 get_elem_bits(ctx, result_type));
1304 assert(length < sizeof(name));
1305 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1306 }
1307
1308 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1310 {
1311 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1312 ctx->i32_0, "");
1313 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1314 }
1315
1316 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1317 LLVMIntPredicate pred,
1318 LLVMValueRef src0, LLVMValueRef src1)
1319 {
1320 return LLVMBuildSelect(ctx->builder,
1321 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1322 src0,
1323 src1, "");
1324
1325 }
1326 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1327 LLVMValueRef src0)
1328 {
1329 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1330 LLVMBuildNeg(ctx->builder, src0, ""));
1331 }
1332
1333 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 LLVMValueRef cmp, val;
1337
1338 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1339 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1340 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1341 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1342 return val;
1343 }
1344
1345 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1346 LLVMValueRef src0)
1347 {
1348 LLVMValueRef cmp, val;
1349
1350 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1351 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1352 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1353 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1354 return val;
1355 }
1356
1357 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1358 LLVMValueRef src0)
1359 {
1360 const char *intr = "llvm.floor.f32";
1361 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1362 LLVMValueRef params[] = {
1363 fsrc0,
1364 };
1365 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1366 ctx->f32, params, 1,
1367 AC_FUNC_ATTR_READNONE);
1368 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1369 }
1370
1371 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1372 const char *intrin,
1373 LLVMValueRef src0, LLVMValueRef src1)
1374 {
1375 LLVMTypeRef ret_type;
1376 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1377 LLVMValueRef res;
1378 LLVMValueRef params[] = { src0, src1 };
1379 ret_type = LLVMStructTypeInContext(ctx->context, types,
1380 2, true);
1381
1382 res = ac_build_intrinsic(ctx, intrin, ret_type,
1383 params, 2, AC_FUNC_ATTR_READNONE);
1384
1385 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1386 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1387 return res;
1388 }
1389
1390 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1391 LLVMValueRef src0)
1392 {
1393 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1394 }
1395
1396 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1397 LLVMValueRef src0)
1398 {
1399 src0 = ac_to_float(ctx, src0);
1400 return LLVMBuildSExt(ctx->builder,
1401 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1402 ctx->i32, "");
1403 }
1404
1405 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1406 LLVMValueRef src0)
1407 {
1408 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1409 }
1410
1411 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1412 LLVMValueRef src0)
1413 {
1414 return LLVMBuildSExt(ctx->builder,
1415 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1416 ctx->i32, "");
1417 }
1418
1419 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 LLVMValueRef result;
1423 LLVMValueRef cond = NULL;
1424
1425 src0 = ac_to_float(&ctx->ac, src0);
1426 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1427
1428 if (ctx->options->chip_class >= VI) {
1429 LLVMValueRef args[2];
1430 /* Check if the result is a denormal - and flush to 0 if so. */
1431 args[0] = result;
1432 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1433 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1434 }
1435
1436 /* need to convert back up to f32 */
1437 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1438
1439 if (ctx->options->chip_class >= VI)
1440 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1441 else {
1442 /* for SI/CIK */
1443 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1444 * so compare the result and flush to 0 if it's smaller.
1445 */
1446 LLVMValueRef temp, cond2;
1447 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1448 ctx->ac.f32, result);
1449 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1450 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1451 temp, "");
1452 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1453 temp, ctx->ac.f32_0, "");
1454 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1455 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1456 }
1457 return result;
1458 }
1459
1460 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1461 LLVMValueRef src0, LLVMValueRef src1)
1462 {
1463 LLVMValueRef dst64, result;
1464 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1465 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1466
1467 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1468 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1469 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1470 return result;
1471 }
1472
1473 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1474 LLVMValueRef src0, LLVMValueRef src1)
1475 {
1476 LLVMValueRef dst64, result;
1477 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1478 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1479
1480 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1481 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1482 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1483 return result;
1484 }
1485
1486 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1487 bool is_signed,
1488 const LLVMValueRef srcs[3])
1489 {
1490 LLVMValueRef result;
1491 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1492
1493 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1494 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1495 return result;
1496 }
1497
1498 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1499 LLVMValueRef src0, LLVMValueRef src1,
1500 LLVMValueRef src2, LLVMValueRef src3)
1501 {
1502 LLVMValueRef bfi_args[3], result;
1503
1504 bfi_args[0] = LLVMBuildShl(ctx->builder,
1505 LLVMBuildSub(ctx->builder,
1506 LLVMBuildShl(ctx->builder,
1507 ctx->i32_1,
1508 src3, ""),
1509 ctx->i32_1, ""),
1510 src2, "");
1511 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1512 bfi_args[2] = src0;
1513
1514 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1515
1516 /* Calculate:
1517 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1518 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1519 */
1520 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1521 LLVMBuildAnd(ctx->builder, bfi_args[0],
1522 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1523
1524 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1525 return result;
1526 }
1527
1528 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1529 LLVMValueRef src0)
1530 {
1531 LLVMValueRef comp[2];
1532
1533 src0 = ac_to_float(ctx, src0);
1534 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1535 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1536
1537 return ac_build_cvt_pkrtz_f16(ctx, comp);
1538 }
1539
1540 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1541 LLVMValueRef src0)
1542 {
1543 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1544 LLVMValueRef temps[2], result, val;
1545 int i;
1546
1547 for (i = 0; i < 2; i++) {
1548 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1549 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1550 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1551 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1552 }
1553
1554 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1555 ctx->i32_0, "");
1556 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1557 ctx->i32_1, "");
1558 return result;
1559 }
1560
1561 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1562 nir_op op,
1563 LLVMValueRef src0)
1564 {
1565 unsigned mask;
1566 int idx;
1567 LLVMValueRef result;
1568
1569 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1570 mask = AC_TID_MASK_LEFT;
1571 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1572 mask = AC_TID_MASK_TOP;
1573 else
1574 mask = AC_TID_MASK_TOP_LEFT;
1575
1576 /* for DDX we want to next X pixel, DDY next Y pixel. */
1577 if (op == nir_op_fddx_fine ||
1578 op == nir_op_fddx_coarse ||
1579 op == nir_op_fddx)
1580 idx = 1;
1581 else
1582 idx = 2;
1583
1584 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1585 return result;
1586 }
1587
1588 /*
1589 * this takes an I,J coordinate pair,
1590 * and works out the X and Y derivatives.
1591 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1592 */
1593 static LLVMValueRef emit_ddxy_interp(
1594 struct ac_nir_context *ctx,
1595 LLVMValueRef interp_ij)
1596 {
1597 LLVMValueRef result[4], a;
1598 unsigned i;
1599
1600 for (i = 0; i < 2; i++) {
1601 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1602 LLVMConstInt(ctx->ac.i32, i, false), "");
1603 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1604 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1605 }
1606 return ac_build_gather_values(&ctx->ac, result, 4);
1607 }
1608
1609 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1610 {
1611 LLVMValueRef src[4], result = NULL;
1612 unsigned num_components = instr->dest.dest.ssa.num_components;
1613 unsigned src_components;
1614 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1615
1616 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1617 switch (instr->op) {
1618 case nir_op_vec2:
1619 case nir_op_vec3:
1620 case nir_op_vec4:
1621 src_components = 1;
1622 break;
1623 case nir_op_pack_half_2x16:
1624 src_components = 2;
1625 break;
1626 case nir_op_unpack_half_2x16:
1627 src_components = 1;
1628 break;
1629 default:
1630 src_components = num_components;
1631 break;
1632 }
1633 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1634 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1635
1636 switch (instr->op) {
1637 case nir_op_fmov:
1638 case nir_op_imov:
1639 result = src[0];
1640 break;
1641 case nir_op_fneg:
1642 src[0] = ac_to_float(&ctx->ac, src[0]);
1643 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1644 break;
1645 case nir_op_ineg:
1646 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1647 break;
1648 case nir_op_inot:
1649 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1650 break;
1651 case nir_op_iadd:
1652 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1653 break;
1654 case nir_op_fadd:
1655 src[0] = ac_to_float(&ctx->ac, src[0]);
1656 src[1] = ac_to_float(&ctx->ac, src[1]);
1657 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1658 break;
1659 case nir_op_fsub:
1660 src[0] = ac_to_float(&ctx->ac, src[0]);
1661 src[1] = ac_to_float(&ctx->ac, src[1]);
1662 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1663 break;
1664 case nir_op_isub:
1665 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1666 break;
1667 case nir_op_imul:
1668 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1669 break;
1670 case nir_op_imod:
1671 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1672 break;
1673 case nir_op_umod:
1674 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_fmod:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 src[1] = ac_to_float(&ctx->ac, src[1]);
1679 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1680 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1681 ac_to_float_type(&ctx->ac, def_type), result);
1682 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1683 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1684 break;
1685 case nir_op_frem:
1686 src[0] = ac_to_float(&ctx->ac, src[0]);
1687 src[1] = ac_to_float(&ctx->ac, src[1]);
1688 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_irem:
1691 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_idiv:
1694 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_udiv:
1697 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fmul:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1703 break;
1704 case nir_op_fdiv:
1705 src[0] = ac_to_float(&ctx->ac, src[0]);
1706 src[1] = ac_to_float(&ctx->ac, src[1]);
1707 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1708 break;
1709 case nir_op_frcp:
1710 src[0] = ac_to_float(&ctx->ac, src[0]);
1711 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1712 break;
1713 case nir_op_iand:
1714 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_ior:
1717 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_ixor:
1720 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_ishl:
1723 result = LLVMBuildShl(ctx->ac.builder, src[0],
1724 LLVMBuildZExt(ctx->ac.builder, src[1],
1725 LLVMTypeOf(src[0]), ""),
1726 "");
1727 break;
1728 case nir_op_ishr:
1729 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1730 LLVMBuildZExt(ctx->ac.builder, src[1],
1731 LLVMTypeOf(src[0]), ""),
1732 "");
1733 break;
1734 case nir_op_ushr:
1735 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1736 LLVMBuildZExt(ctx->ac.builder, src[1],
1737 LLVMTypeOf(src[0]), ""),
1738 "");
1739 break;
1740 case nir_op_ilt:
1741 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1742 break;
1743 case nir_op_ine:
1744 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1745 break;
1746 case nir_op_ieq:
1747 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1748 break;
1749 case nir_op_ige:
1750 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1751 break;
1752 case nir_op_ult:
1753 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1754 break;
1755 case nir_op_uge:
1756 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1757 break;
1758 case nir_op_feq:
1759 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1760 break;
1761 case nir_op_fne:
1762 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1763 break;
1764 case nir_op_flt:
1765 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1766 break;
1767 case nir_op_fge:
1768 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1769 break;
1770 case nir_op_fabs:
1771 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1772 ac_to_float_type(&ctx->ac, def_type), src[0]);
1773 break;
1774 case nir_op_iabs:
1775 result = emit_iabs(&ctx->ac, src[0]);
1776 break;
1777 case nir_op_imax:
1778 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1779 break;
1780 case nir_op_imin:
1781 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1782 break;
1783 case nir_op_umax:
1784 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1785 break;
1786 case nir_op_umin:
1787 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1788 break;
1789 case nir_op_isign:
1790 result = emit_isign(&ctx->ac, src[0]);
1791 break;
1792 case nir_op_fsign:
1793 src[0] = ac_to_float(&ctx->ac, src[0]);
1794 result = emit_fsign(&ctx->ac, src[0]);
1795 break;
1796 case nir_op_ffloor:
1797 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1798 ac_to_float_type(&ctx->ac, def_type), src[0]);
1799 break;
1800 case nir_op_ftrunc:
1801 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1802 ac_to_float_type(&ctx->ac, def_type), src[0]);
1803 break;
1804 case nir_op_fceil:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_fround_even:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1810 ac_to_float_type(&ctx->ac, def_type),src[0]);
1811 break;
1812 case nir_op_ffract:
1813 result = emit_ffract(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fsin:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1817 ac_to_float_type(&ctx->ac, def_type), src[0]);
1818 break;
1819 case nir_op_fcos:
1820 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1821 ac_to_float_type(&ctx->ac, def_type), src[0]);
1822 break;
1823 case nir_op_fsqrt:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fexp2:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_flog2:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1833 ac_to_float_type(&ctx->ac, def_type), src[0]);
1834 break;
1835 case nir_op_frsq:
1836 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1837 ac_to_float_type(&ctx->ac, def_type), src[0]);
1838 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1839 break;
1840 case nir_op_fpow:
1841 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1842 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1843 break;
1844 case nir_op_fmax:
1845 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1846 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1847 if (instr->dest.dest.ssa.bit_size == 32)
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1849 ac_to_float_type(&ctx->ac, def_type),
1850 result);
1851 break;
1852 case nir_op_fmin:
1853 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1854 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1855 if (instr->dest.dest.ssa.bit_size == 32)
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1857 ac_to_float_type(&ctx->ac, def_type),
1858 result);
1859 break;
1860 case nir_op_ffma:
1861 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1862 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1863 break;
1864 case nir_op_ibitfield_extract:
1865 result = emit_bitfield_extract(&ctx->ac, true, src);
1866 break;
1867 case nir_op_ubitfield_extract:
1868 result = emit_bitfield_extract(&ctx->ac, false, src);
1869 break;
1870 case nir_op_bitfield_insert:
1871 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1872 break;
1873 case nir_op_bitfield_reverse:
1874 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1875 break;
1876 case nir_op_bit_count:
1877 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1878 break;
1879 case nir_op_vec2:
1880 case nir_op_vec3:
1881 case nir_op_vec4:
1882 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1883 src[i] = ac_to_integer(&ctx->ac, src[i]);
1884 result = ac_build_gather_values(&ctx->ac, src, num_components);
1885 break;
1886 case nir_op_f2i32:
1887 case nir_op_f2i64:
1888 src[0] = ac_to_float(&ctx->ac, src[0]);
1889 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1890 break;
1891 case nir_op_f2u32:
1892 case nir_op_f2u64:
1893 src[0] = ac_to_float(&ctx->ac, src[0]);
1894 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1895 break;
1896 case nir_op_i2f32:
1897 case nir_op_i2f64:
1898 src[0] = ac_to_integer(&ctx->ac, src[0]);
1899 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1900 break;
1901 case nir_op_u2f32:
1902 case nir_op_u2f64:
1903 src[0] = ac_to_integer(&ctx->ac, src[0]);
1904 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1905 break;
1906 case nir_op_f2f64:
1907 src[0] = ac_to_float(&ctx->ac, src[0]);
1908 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1909 break;
1910 case nir_op_f2f32:
1911 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1912 break;
1913 case nir_op_u2u32:
1914 case nir_op_u2u64:
1915 src[0] = ac_to_integer(&ctx->ac, src[0]);
1916 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1917 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1918 else
1919 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1920 break;
1921 case nir_op_i2i32:
1922 case nir_op_i2i64:
1923 src[0] = ac_to_integer(&ctx->ac, src[0]);
1924 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1925 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1926 else
1927 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1928 break;
1929 case nir_op_bcsel:
1930 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1931 break;
1932 case nir_op_find_lsb:
1933 src[0] = ac_to_integer(&ctx->ac, src[0]);
1934 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1935 break;
1936 case nir_op_ufind_msb:
1937 src[0] = ac_to_integer(&ctx->ac, src[0]);
1938 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1939 break;
1940 case nir_op_ifind_msb:
1941 src[0] = ac_to_integer(&ctx->ac, src[0]);
1942 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1943 break;
1944 case nir_op_uadd_carry:
1945 src[0] = ac_to_integer(&ctx->ac, src[0]);
1946 src[1] = ac_to_integer(&ctx->ac, src[1]);
1947 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1948 break;
1949 case nir_op_usub_borrow:
1950 src[0] = ac_to_integer(&ctx->ac, src[0]);
1951 src[1] = ac_to_integer(&ctx->ac, src[1]);
1952 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1953 break;
1954 case nir_op_b2f:
1955 result = emit_b2f(&ctx->ac, src[0]);
1956 break;
1957 case nir_op_f2b:
1958 result = emit_f2b(&ctx->ac, src[0]);
1959 break;
1960 case nir_op_b2i:
1961 result = emit_b2i(&ctx->ac, src[0]);
1962 break;
1963 case nir_op_i2b:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 result = emit_i2b(&ctx->ac, src[0]);
1966 break;
1967 case nir_op_fquantize2f16:
1968 result = emit_f2f16(ctx->nctx, src[0]);
1969 break;
1970 case nir_op_umul_high:
1971 src[0] = ac_to_integer(&ctx->ac, src[0]);
1972 src[1] = ac_to_integer(&ctx->ac, src[1]);
1973 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1974 break;
1975 case nir_op_imul_high:
1976 src[0] = ac_to_integer(&ctx->ac, src[0]);
1977 src[1] = ac_to_integer(&ctx->ac, src[1]);
1978 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1979 break;
1980 case nir_op_pack_half_2x16:
1981 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_unpack_half_2x16:
1984 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1985 break;
1986 case nir_op_fddx:
1987 case nir_op_fddy:
1988 case nir_op_fddx_fine:
1989 case nir_op_fddy_fine:
1990 case nir_op_fddx_coarse:
1991 case nir_op_fddy_coarse:
1992 result = emit_ddxy(ctx, instr->op, src[0]);
1993 break;
1994
1995 case nir_op_unpack_64_2x32_split_x: {
1996 assert(instr->src[0].src.ssa->num_components == 1);
1997 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1998 ctx->ac.v2i32,
1999 "");
2000 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2001 ctx->ac.i32_0, "");
2002 break;
2003 }
2004
2005 case nir_op_unpack_64_2x32_split_y: {
2006 assert(instr->src[0].src.ssa->num_components == 1);
2007 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2008 ctx->ac.v2i32,
2009 "");
2010 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2011 ctx->ac.i32_1, "");
2012 break;
2013 }
2014
2015 case nir_op_pack_64_2x32_split: {
2016 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2017 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2018 src[0], ctx->ac.i32_0, "");
2019 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2020 src[1], ctx->ac.i32_1, "");
2021 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2022 break;
2023 }
2024
2025 default:
2026 fprintf(stderr, "Unknown NIR alu instr: ");
2027 nir_print_instr(&instr->instr, stderr);
2028 fprintf(stderr, "\n");
2029 abort();
2030 }
2031
2032 if (result) {
2033 assert(instr->dest.dest.is_ssa);
2034 result = ac_to_integer(&ctx->ac, result);
2035 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2036 result);
2037 }
2038 }
2039
2040 static void visit_load_const(struct ac_nir_context *ctx,
2041 const nir_load_const_instr *instr)
2042 {
2043 LLVMValueRef values[4], value = NULL;
2044 LLVMTypeRef element_type =
2045 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2046
2047 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2048 switch (instr->def.bit_size) {
2049 case 32:
2050 values[i] = LLVMConstInt(element_type,
2051 instr->value.u32[i], false);
2052 break;
2053 case 64:
2054 values[i] = LLVMConstInt(element_type,
2055 instr->value.u64[i], false);
2056 break;
2057 default:
2058 fprintf(stderr,
2059 "unsupported nir load_const bit_size: %d\n",
2060 instr->def.bit_size);
2061 abort();
2062 }
2063 }
2064 if (instr->def.num_components > 1) {
2065 value = LLVMConstVector(values, instr->def.num_components);
2066 } else
2067 value = values[0];
2068
2069 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2070 }
2071
2072 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2073 LLVMTypeRef type)
2074 {
2075 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2076 return LLVMBuildBitCast(ctx->builder, ptr,
2077 LLVMPointerType(type, addr_space), "");
2078 }
2079
2080 static LLVMValueRef
2081 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2082 {
2083 LLVMValueRef size =
2084 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2085 LLVMConstInt(ctx->ac.i32, 2, false), "");
2086
2087 /* VI only */
2088 if (ctx->ac.chip_class == VI && in_elements) {
2089 /* On VI, the descriptor contains the size in bytes,
2090 * but TXQ must return the size in elements.
2091 * The stride is always non-zero for resources using TXQ.
2092 */
2093 LLVMValueRef stride =
2094 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2095 ctx->ac.i32_1, "");
2096 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2097 LLVMConstInt(ctx->ac.i32, 16, false), "");
2098 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2099 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2100
2101 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2102 }
2103 return size;
2104 }
2105
2106 /**
2107 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2108 * intrinsic names).
2109 */
2110 static void build_int_type_name(
2111 LLVMTypeRef type,
2112 char *buf, unsigned bufsize)
2113 {
2114 assert(bufsize >= 6);
2115
2116 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2117 snprintf(buf, bufsize, "v%ui32",
2118 LLVMGetVectorSize(type));
2119 else
2120 strcpy(buf, "i32");
2121 }
2122
2123 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2124 struct ac_image_args *args,
2125 const nir_tex_instr *instr)
2126 {
2127 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2128 LLVMValueRef coord = args->addr;
2129 LLVMValueRef half_texel[2];
2130 LLVMValueRef compare_cube_wa = NULL;
2131 LLVMValueRef result;
2132 int c;
2133 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2134
2135 //TODO Rect
2136 {
2137 struct ac_image_args txq_args = { 0 };
2138
2139 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2140 txq_args.opcode = ac_image_get_resinfo;
2141 txq_args.dmask = 0xf;
2142 txq_args.addr = ctx->i32_0;
2143 txq_args.resource = args->resource;
2144 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2145
2146 for (c = 0; c < 2; c++) {
2147 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2148 LLVMConstInt(ctx->i32, c, false), "");
2149 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2150 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2151 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2152 LLVMConstReal(ctx->f32, -0.5), "");
2153 }
2154 }
2155
2156 LLVMValueRef orig_coords = args->addr;
2157
2158 for (c = 0; c < 2; c++) {
2159 LLVMValueRef tmp;
2160 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2161 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2162 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2163 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2164 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2165 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2166 }
2167
2168
2169 /*
2170 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2171 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2172 * workaround by sampling using a scaled type and converting.
2173 * This is taken from amdgpu-pro shaders.
2174 */
2175 /* NOTE this produces some ugly code compared to amdgpu-pro,
2176 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2177 * and then reads them back. -pro generates two selects,
2178 * one s_cmp for the descriptor rewriting
2179 * one v_cmp for the coordinate and result changes.
2180 */
2181 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2182 LLVMValueRef tmp, tmp2;
2183
2184 /* workaround 8/8/8/8 uint/sint cube gather bug */
2185 /* first detect it then change to a scaled read and f2i */
2186 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2187 tmp2 = tmp;
2188
2189 /* extract the DATA_FORMAT */
2190 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2191 LLVMConstInt(ctx->i32, 6, false), false);
2192
2193 /* is the DATA_FORMAT == 8_8_8_8 */
2194 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2195
2196 if (stype == GLSL_TYPE_UINT)
2197 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2198 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2199 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2200 else
2201 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2202 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2203 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2204
2205 /* replace the NUM FORMAT in the descriptor */
2206 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2207 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2208
2209 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2210
2211 /* don't modify the coordinates for this case */
2212 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2213 }
2214 args->addr = coord;
2215 result = ac_build_image_opcode(ctx, args);
2216
2217 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2218 LLVMValueRef tmp, tmp2;
2219
2220 /* if the cube workaround is in place, f2i the result. */
2221 for (c = 0; c < 4; c++) {
2222 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2223 if (stype == GLSL_TYPE_UINT)
2224 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2225 else
2226 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2227 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2228 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2229 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2230 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2231 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2232 }
2233 }
2234 return result;
2235 }
2236
2237 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2238 const nir_tex_instr *instr,
2239 bool lod_is_zero,
2240 struct ac_image_args *args)
2241 {
2242 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2243 return ac_build_buffer_load_format(&ctx->ac,
2244 args->resource,
2245 args->addr,
2246 ctx->ac.i32_0,
2247 true);
2248 }
2249
2250 args->opcode = ac_image_sample;
2251 args->compare = instr->is_shadow;
2252
2253 switch (instr->op) {
2254 case nir_texop_txf:
2255 case nir_texop_txf_ms:
2256 case nir_texop_samples_identical:
2257 args->opcode = lod_is_zero ||
2258 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2259 ac_image_load : ac_image_load_mip;
2260 args->compare = false;
2261 args->offset = false;
2262 break;
2263 case nir_texop_txb:
2264 args->bias = true;
2265 break;
2266 case nir_texop_txl:
2267 if (lod_is_zero)
2268 args->level_zero = true;
2269 else
2270 args->lod = true;
2271 break;
2272 case nir_texop_txs:
2273 case nir_texop_query_levels:
2274 args->opcode = ac_image_get_resinfo;
2275 break;
2276 case nir_texop_tex:
2277 if (ctx->stage != MESA_SHADER_FRAGMENT)
2278 args->level_zero = true;
2279 break;
2280 case nir_texop_txd:
2281 args->deriv = true;
2282 break;
2283 case nir_texop_tg4:
2284 args->opcode = ac_image_gather4;
2285 args->level_zero = true;
2286 break;
2287 case nir_texop_lod:
2288 args->opcode = ac_image_get_lod;
2289 args->compare = false;
2290 args->offset = false;
2291 break;
2292 default:
2293 break;
2294 }
2295
2296 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2297 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2298 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2299 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2300 }
2301 }
2302 return ac_build_image_opcode(&ctx->ac, args);
2303 }
2304
2305 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2306 nir_intrinsic_instr *instr)
2307 {
2308 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2309 unsigned desc_set = nir_intrinsic_desc_set(instr);
2310 unsigned binding = nir_intrinsic_binding(instr);
2311 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2312 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2313 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2314 unsigned base_offset = layout->binding[binding].offset;
2315 LLVMValueRef offset, stride;
2316
2317 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2318 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2319 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2320 layout->binding[binding].dynamic_offset_offset;
2321 desc_ptr = ctx->push_constants;
2322 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2323 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2324 } else
2325 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2326
2327 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2328 index = LLVMBuildMul(ctx->builder, index, stride, "");
2329 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2330
2331 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2332 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2333 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2334
2335 return desc_ptr;
2336 }
2337
2338 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2339 nir_intrinsic_instr *instr)
2340 {
2341 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2342 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2343
2344 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2345 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2346 return result;
2347 }
2348
2349 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2350 nir_intrinsic_instr *instr)
2351 {
2352 LLVMValueRef ptr, addr;
2353
2354 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2355 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2356
2357 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2358 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2359
2360 return LLVMBuildLoad(ctx->builder, ptr, "");
2361 }
2362
2363 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2364 const nir_intrinsic_instr *instr)
2365 {
2366 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2367
2368 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2369 }
2370 static void visit_store_ssbo(struct ac_nir_context *ctx,
2371 nir_intrinsic_instr *instr)
2372 {
2373 const char *store_name;
2374 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2375 LLVMTypeRef data_type = ctx->ac.f32;
2376 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2377 int components_32bit = elem_size_mult * instr->num_components;
2378 unsigned writemask = nir_intrinsic_write_mask(instr);
2379 LLVMValueRef base_data, base_offset;
2380 LLVMValueRef params[6];
2381
2382 params[1] = ctx->abi->load_ssbo(ctx->abi,
2383 get_src(ctx, instr->src[1]), true);
2384 params[2] = ctx->ac.i32_0; /* vindex */
2385 params[4] = ctx->ac.i1false; /* glc */
2386 params[5] = ctx->ac.i1false; /* slc */
2387
2388 if (components_32bit > 1)
2389 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2390
2391 base_data = ac_to_float(&ctx->ac, src_data);
2392 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2393 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2394 data_type, "");
2395 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2396 while (writemask) {
2397 int start, count;
2398 LLVMValueRef data;
2399 LLVMValueRef offset;
2400 LLVMValueRef tmp;
2401 u_bit_scan_consecutive_range(&writemask, &start, &count);
2402
2403 /* Due to an LLVM limitation, split 3-element writes
2404 * into a 2-element and a 1-element write. */
2405 if (count == 3) {
2406 writemask |= 1 << (start + 2);
2407 count = 2;
2408 }
2409
2410 start *= elem_size_mult;
2411 count *= elem_size_mult;
2412
2413 if (count > 4) {
2414 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2415 count = 4;
2416 }
2417
2418 if (count == 4) {
2419 store_name = "llvm.amdgcn.buffer.store.v4f32";
2420 data = base_data;
2421 } else if (count == 2) {
2422 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2423 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2424 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2425 ctx->ac.i32_0, "");
2426
2427 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2428 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2429 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2430 ctx->ac.i32_1, "");
2431 store_name = "llvm.amdgcn.buffer.store.v2f32";
2432
2433 } else {
2434 assert(count == 1);
2435 if (ac_get_llvm_num_components(base_data) > 1)
2436 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2437 LLVMConstInt(ctx->ac.i32, start, false), "");
2438 else
2439 data = base_data;
2440 store_name = "llvm.amdgcn.buffer.store.f32";
2441 }
2442
2443 offset = base_offset;
2444 if (start != 0) {
2445 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2446 }
2447 params[0] = data;
2448 params[3] = offset;
2449 ac_build_intrinsic(&ctx->ac, store_name,
2450 ctx->ac.voidt, params, 6, 0);
2451 }
2452 }
2453
2454 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2455 const nir_intrinsic_instr *instr)
2456 {
2457 const char *name;
2458 LLVMValueRef params[6];
2459 int arg_count = 0;
2460
2461 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2462 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2463 }
2464 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2465 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2466 get_src(ctx, instr->src[0]),
2467 true);
2468 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2469 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2470 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2471
2472 switch (instr->intrinsic) {
2473 case nir_intrinsic_ssbo_atomic_add:
2474 name = "llvm.amdgcn.buffer.atomic.add";
2475 break;
2476 case nir_intrinsic_ssbo_atomic_imin:
2477 name = "llvm.amdgcn.buffer.atomic.smin";
2478 break;
2479 case nir_intrinsic_ssbo_atomic_umin:
2480 name = "llvm.amdgcn.buffer.atomic.umin";
2481 break;
2482 case nir_intrinsic_ssbo_atomic_imax:
2483 name = "llvm.amdgcn.buffer.atomic.smax";
2484 break;
2485 case nir_intrinsic_ssbo_atomic_umax:
2486 name = "llvm.amdgcn.buffer.atomic.umax";
2487 break;
2488 case nir_intrinsic_ssbo_atomic_and:
2489 name = "llvm.amdgcn.buffer.atomic.and";
2490 break;
2491 case nir_intrinsic_ssbo_atomic_or:
2492 name = "llvm.amdgcn.buffer.atomic.or";
2493 break;
2494 case nir_intrinsic_ssbo_atomic_xor:
2495 name = "llvm.amdgcn.buffer.atomic.xor";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_exchange:
2498 name = "llvm.amdgcn.buffer.atomic.swap";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_comp_swap:
2501 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2502 break;
2503 default:
2504 abort();
2505 }
2506
2507 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2508 }
2509
2510 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2511 const nir_intrinsic_instr *instr)
2512 {
2513 LLVMValueRef results[2];
2514 int load_components;
2515 int num_components = instr->num_components;
2516 if (instr->dest.ssa.bit_size == 64)
2517 num_components *= 2;
2518
2519 for (int i = 0; i < num_components; i += load_components) {
2520 load_components = MIN2(num_components - i, 4);
2521 const char *load_name;
2522 LLVMTypeRef data_type = ctx->ac.f32;
2523 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2524 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2525
2526 if (load_components == 3)
2527 data_type = LLVMVectorType(ctx->ac.f32, 4);
2528 else if (load_components > 1)
2529 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2530
2531 if (load_components >= 3)
2532 load_name = "llvm.amdgcn.buffer.load.v4f32";
2533 else if (load_components == 2)
2534 load_name = "llvm.amdgcn.buffer.load.v2f32";
2535 else if (load_components == 1)
2536 load_name = "llvm.amdgcn.buffer.load.f32";
2537 else
2538 unreachable("unhandled number of components");
2539
2540 LLVMValueRef params[] = {
2541 ctx->abi->load_ssbo(ctx->abi,
2542 get_src(ctx, instr->src[0]),
2543 false),
2544 ctx->ac.i32_0,
2545 offset,
2546 ctx->ac.i1false,
2547 ctx->ac.i1false,
2548 };
2549
2550 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2551
2552 }
2553
2554 assume(results[0]);
2555 LLVMValueRef ret = results[0];
2556 if (num_components > 4 || num_components == 3) {
2557 LLVMValueRef masks[] = {
2558 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2559 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2560 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2561 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2562 };
2563
2564 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2565 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2566 results[num_components > 4 ? 1 : 0], swizzle, "");
2567 }
2568
2569 return LLVMBuildBitCast(ctx->ac.builder, ret,
2570 get_def_type(ctx, &instr->dest.ssa), "");
2571 }
2572
2573 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2574 const nir_intrinsic_instr *instr)
2575 {
2576 LLVMValueRef results[8], ret;
2577 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2578 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2579 int num_components = instr->num_components;
2580
2581 if (ctx->abi->load_ubo)
2582 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2583
2584 if (instr->dest.ssa.bit_size == 64)
2585 num_components *= 2;
2586
2587 for (unsigned i = 0; i < num_components; ++i) {
2588 LLVMValueRef params[] = {
2589 rsrc,
2590 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2591 offset, "")
2592 };
2593 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2594 params, 2,
2595 AC_FUNC_ATTR_READNONE |
2596 AC_FUNC_ATTR_LEGACY);
2597 }
2598
2599
2600 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2601 return LLVMBuildBitCast(ctx->ac.builder, ret,
2602 get_def_type(ctx, &instr->dest.ssa), "");
2603 }
2604
2605 static void
2606 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2607 bool vs_in, unsigned *vertex_index_out,
2608 LLVMValueRef *vertex_index_ref,
2609 unsigned *const_out, LLVMValueRef *indir_out)
2610 {
2611 unsigned const_offset = 0;
2612 nir_deref *tail = &deref->deref;
2613 LLVMValueRef offset = NULL;
2614
2615 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2616 tail = tail->child;
2617 nir_deref_array *deref_array = nir_deref_as_array(tail);
2618 if (vertex_index_out)
2619 *vertex_index_out = deref_array->base_offset;
2620
2621 if (vertex_index_ref) {
2622 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2623 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2624 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2625 }
2626 *vertex_index_ref = vtx;
2627 }
2628 }
2629
2630 if (deref->var->data.compact) {
2631 assert(tail->child->deref_type == nir_deref_type_array);
2632 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2633 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2634 /* We always lower indirect dereferences for "compact" array vars. */
2635 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2636
2637 const_offset = deref_array->base_offset;
2638 goto out;
2639 }
2640
2641 while (tail->child != NULL) {
2642 const struct glsl_type *parent_type = tail->type;
2643 tail = tail->child;
2644
2645 if (tail->deref_type == nir_deref_type_array) {
2646 nir_deref_array *deref_array = nir_deref_as_array(tail);
2647 LLVMValueRef index, stride, local_offset;
2648 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2649
2650 const_offset += size * deref_array->base_offset;
2651 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2652 continue;
2653
2654 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2655 index = get_src(ctx, deref_array->indirect);
2656 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2657 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2658
2659 if (offset)
2660 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2661 else
2662 offset = local_offset;
2663 } else if (tail->deref_type == nir_deref_type_struct) {
2664 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2665
2666 for (unsigned i = 0; i < deref_struct->index; i++) {
2667 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2668 const_offset += glsl_count_attribute_slots(ft, vs_in);
2669 }
2670 } else
2671 unreachable("unsupported deref type");
2672
2673 }
2674 out:
2675 if (const_offset && offset)
2676 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2677 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2678 "");
2679
2680 *const_out = const_offset;
2681 *indir_out = offset;
2682 }
2683
2684
2685 /* The offchip buffer layout for TCS->TES is
2686 *
2687 * - attribute 0 of patch 0 vertex 0
2688 * - attribute 0 of patch 0 vertex 1
2689 * - attribute 0 of patch 0 vertex 2
2690 * ...
2691 * - attribute 0 of patch 1 vertex 0
2692 * - attribute 0 of patch 1 vertex 1
2693 * ...
2694 * - attribute 1 of patch 0 vertex 0
2695 * - attribute 1 of patch 0 vertex 1
2696 * ...
2697 * - per patch attribute 0 of patch 0
2698 * - per patch attribute 0 of patch 1
2699 * ...
2700 *
2701 * Note that every attribute has 4 components.
2702 */
2703 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2704 LLVMValueRef vertex_index,
2705 LLVMValueRef param_index)
2706 {
2707 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2708 LLVMValueRef param_stride, constant16;
2709 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2710
2711 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2712 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2713 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2714 num_patches, "");
2715
2716 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2717 if (vertex_index) {
2718 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2719 vertices_per_patch, "");
2720
2721 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2722 vertex_index, "");
2723
2724 param_stride = total_vertices;
2725 } else {
2726 base_addr = rel_patch_id;
2727 param_stride = num_patches;
2728 }
2729
2730 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2731 LLVMBuildMul(ctx->builder, param_index,
2732 param_stride, ""), "");
2733
2734 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2735
2736 if (!vertex_index) {
2737 LLVMValueRef patch_data_offset =
2738 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2739
2740 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2741 patch_data_offset, "");
2742 }
2743 return base_addr;
2744 }
2745
2746 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2747 unsigned param,
2748 unsigned const_index,
2749 bool is_compact,
2750 LLVMValueRef vertex_index,
2751 LLVMValueRef indir_index)
2752 {
2753 LLVMValueRef param_index;
2754
2755 if (indir_index)
2756 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2757 indir_index, "");
2758 else {
2759 if (const_index && !is_compact)
2760 param += const_index;
2761 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2762 }
2763 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2764 }
2765
2766 static void
2767 mark_tess_output(struct nir_to_llvm_context *ctx,
2768 bool is_patch, uint32_t param)
2769
2770 {
2771 if (is_patch) {
2772 ctx->tess_patch_outputs_written |= (1ull << param);
2773 } else
2774 ctx->tess_outputs_written |= (1ull << param);
2775 }
2776
2777 static LLVMValueRef
2778 get_dw_address(struct nir_to_llvm_context *ctx,
2779 LLVMValueRef dw_addr,
2780 unsigned param,
2781 unsigned const_index,
2782 bool compact_const_index,
2783 LLVMValueRef vertex_index,
2784 LLVMValueRef stride,
2785 LLVMValueRef indir_index)
2786
2787 {
2788
2789 if (vertex_index) {
2790 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2791 LLVMBuildMul(ctx->builder,
2792 vertex_index,
2793 stride, ""), "");
2794 }
2795
2796 if (indir_index)
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 LLVMBuildMul(ctx->builder, indir_index,
2799 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2800 else if (const_index && !compact_const_index)
2801 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2802 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2803
2804 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2805 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2806
2807 if (const_index && compact_const_index)
2808 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2809 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2810 return dw_addr;
2811 }
2812
2813 static LLVMValueRef
2814 load_tcs_input(struct ac_shader_abi *abi,
2815 LLVMValueRef vertex_index,
2816 LLVMValueRef indir_index,
2817 unsigned const_index,
2818 unsigned location,
2819 unsigned driver_location,
2820 unsigned component,
2821 unsigned num_components,
2822 bool is_patch,
2823 bool is_compact)
2824 {
2825 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2826 LLVMValueRef dw_addr, stride;
2827 LLVMValueRef value[4], result;
2828 unsigned param = shader_io_get_unique_index(location);
2829
2830 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2831 dw_addr = get_tcs_in_current_patch_offset(ctx);
2832 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2833 indir_index);
2834
2835 for (unsigned i = 0; i < num_components + component; i++) {
2836 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2837 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2838 ctx->ac.i32_1, "");
2839 }
2840 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2841 return result;
2842 }
2843
2844 static LLVMValueRef
2845 load_tcs_output(struct nir_to_llvm_context *ctx,
2846 nir_intrinsic_instr *instr)
2847 {
2848 LLVMValueRef dw_addr;
2849 LLVMValueRef stride = NULL;
2850 LLVMValueRef value[4], result;
2851 LLVMValueRef vertex_index = NULL;
2852 LLVMValueRef indir_index = NULL;
2853 unsigned const_index = 0;
2854 unsigned param;
2855 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2856 const bool is_compact = instr->variables[0]->var->data.compact;
2857 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2858 get_deref_offset(ctx->nir, instr->variables[0],
2859 false, NULL, per_vertex ? &vertex_index : NULL,
2860 &const_index, &indir_index);
2861
2862 if (!instr->variables[0]->var->data.patch) {
2863 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2864 dw_addr = get_tcs_out_current_patch_offset(ctx);
2865 } else {
2866 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2867 }
2868
2869 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2870 indir_index);
2871
2872 unsigned comp = instr->variables[0]->var->data.location_frac;
2873 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2874 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2875 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2876 ctx->ac.i32_1, "");
2877 }
2878 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2879 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2880 return result;
2881 }
2882
2883 static void
2884 store_tcs_output(struct ac_shader_abi *abi,
2885 LLVMValueRef vertex_index,
2886 LLVMValueRef param_index,
2887 unsigned const_index,
2888 unsigned location,
2889 unsigned driver_location,
2890 LLVMValueRef src,
2891 unsigned component,
2892 bool is_patch,
2893 bool is_compact,
2894 unsigned writemask)
2895 {
2896 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2897 LLVMValueRef dw_addr;
2898 LLVMValueRef stride = NULL;
2899 LLVMValueRef buf_addr = NULL;
2900 unsigned param;
2901 bool store_lds = true;
2902
2903 if (is_patch) {
2904 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2905 store_lds = false;
2906 } else {
2907 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2908 store_lds = false;
2909 }
2910
2911 param = shader_io_get_unique_index(location);
2912 if (location == VARYING_SLOT_CLIP_DIST0 &&
2913 is_compact && const_index > 3) {
2914 const_index -= 3;
2915 param++;
2916 }
2917
2918 if (!is_patch) {
2919 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2920 dw_addr = get_tcs_out_current_patch_offset(ctx);
2921 } else {
2922 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2923 }
2924
2925 mark_tess_output(ctx, is_patch, param);
2926
2927 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2928 param_index);
2929 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2930 vertex_index, param_index);
2931
2932 bool is_tess_factor = false;
2933 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2934 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2935 is_tess_factor = true;
2936
2937 unsigned base = is_compact ? const_index : 0;
2938 for (unsigned chan = 0; chan < 8; chan++) {
2939 if (!(writemask & (1 << chan)))
2940 continue;
2941 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2942
2943 if (store_lds || is_tess_factor)
2944 ac_lds_store(&ctx->ac, dw_addr, value);
2945
2946 if (!is_tess_factor && writemask != 0xF)
2947 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2948 buf_addr, ctx->oc_lds,
2949 4 * (base + chan), 1, 0, true, false);
2950
2951 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2952 ctx->ac.i32_1, "");
2953 }
2954
2955 if (writemask == 0xF) {
2956 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2957 buf_addr, ctx->oc_lds,
2958 (base * 4), 1, 0, true, false);
2959 }
2960 }
2961
2962 static LLVMValueRef
2963 load_tes_input(struct ac_shader_abi *abi,
2964 LLVMValueRef vertex_index,
2965 LLVMValueRef param_index,
2966 unsigned const_index,
2967 unsigned location,
2968 unsigned driver_location,
2969 unsigned component,
2970 unsigned num_components,
2971 bool is_patch,
2972 bool is_compact)
2973 {
2974 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2975 LLVMValueRef buf_addr;
2976 LLVMValueRef result;
2977 unsigned param = shader_io_get_unique_index(location);
2978
2979 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2980 const_index -= 3;
2981 param++;
2982 }
2983
2984 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2985 is_compact, vertex_index, param_index);
2986
2987 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2988 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2989
2990 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2991 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2992 result = trim_vector(&ctx->ac, result, num_components);
2993 return result;
2994 }
2995
2996 static LLVMValueRef
2997 load_gs_input(struct ac_shader_abi *abi,
2998 unsigned location,
2999 unsigned driver_location,
3000 unsigned component,
3001 unsigned num_components,
3002 unsigned vertex_index,
3003 unsigned const_index,
3004 LLVMTypeRef type)
3005 {
3006 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3007 LLVMValueRef vtx_offset;
3008 LLVMValueRef args[9];
3009 unsigned param, vtx_offset_param;
3010 LLVMValueRef value[4], result;
3011
3012 vtx_offset_param = vertex_index;
3013 assert(vtx_offset_param < 6);
3014 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3015 LLVMConstInt(ctx->ac.i32, 4, false), "");
3016
3017 param = shader_io_get_unique_index(location);
3018
3019 for (unsigned i = component; i < num_components + component; i++) {
3020 if (ctx->ac.chip_class >= GFX9) {
3021 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3022 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3023 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3024 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3025 } else {
3026 args[0] = ctx->esgs_ring;
3027 args[1] = vtx_offset;
3028 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3029 args[3] = ctx->ac.i32_0;
3030 args[4] = ctx->ac.i32_1; /* OFFEN */
3031 args[5] = ctx->ac.i32_0; /* IDXEN */
3032 args[6] = ctx->ac.i32_1; /* GLC */
3033 args[7] = ctx->ac.i32_0; /* SLC */
3034 args[8] = ctx->ac.i32_0; /* TFE */
3035
3036 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3037 ctx->ac.i32, args, 9,
3038 AC_FUNC_ATTR_READONLY |
3039 AC_FUNC_ATTR_LEGACY);
3040 }
3041 }
3042 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3043
3044 return result;
3045 }
3046
3047 static LLVMValueRef
3048 build_gep_for_deref(struct ac_nir_context *ctx,
3049 nir_deref_var *deref)
3050 {
3051 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3052 assert(entry->data);
3053 LLVMValueRef val = entry->data;
3054 nir_deref *tail = deref->deref.child;
3055 while (tail != NULL) {
3056 LLVMValueRef offset;
3057 switch (tail->deref_type) {
3058 case nir_deref_type_array: {
3059 nir_deref_array *array = nir_deref_as_array(tail);
3060 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3061 if (array->deref_array_type ==
3062 nir_deref_array_type_indirect) {
3063 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3064 get_src(ctx,
3065 array->indirect),
3066 "");
3067 }
3068 break;
3069 }
3070 case nir_deref_type_struct: {
3071 nir_deref_struct *deref_struct =
3072 nir_deref_as_struct(tail);
3073 offset = LLVMConstInt(ctx->ac.i32,
3074 deref_struct->index, 0);
3075 break;
3076 }
3077 default:
3078 unreachable("bad deref type");
3079 }
3080 val = ac_build_gep0(&ctx->ac, val, offset);
3081 tail = tail->child;
3082 }
3083 return val;
3084 }
3085
3086 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3087 nir_intrinsic_instr *instr)
3088 {
3089 LLVMValueRef values[8];
3090 int idx = instr->variables[0]->var->data.driver_location;
3091 int ve = instr->dest.ssa.num_components;
3092 unsigned comp = instr->variables[0]->var->data.location_frac;
3093 LLVMValueRef indir_index;
3094 LLVMValueRef ret;
3095 unsigned const_index;
3096 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3097 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3098 instr->variables[0]->var->data.mode == nir_var_shader_in;
3099 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3100 &const_index, &indir_index);
3101
3102 if (instr->dest.ssa.bit_size == 64)
3103 ve *= 2;
3104
3105 switch (instr->variables[0]->var->data.mode) {
3106 case nir_var_shader_in:
3107 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3108 ctx->stage == MESA_SHADER_TESS_EVAL) {
3109 LLVMValueRef result;
3110 LLVMValueRef vertex_index = NULL;
3111 LLVMValueRef indir_index = NULL;
3112 unsigned const_index = 0;
3113 unsigned location = instr->variables[0]->var->data.location;
3114 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3115 const bool is_patch = instr->variables[0]->var->data.patch;
3116 const bool is_compact = instr->variables[0]->var->data.compact;
3117
3118 get_deref_offset(ctx, instr->variables[0],
3119 false, NULL, is_patch ? NULL : &vertex_index,
3120 &const_index, &indir_index);
3121
3122 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3123 const_index, location, driver_location,
3124 instr->variables[0]->var->data.location_frac,
3125 instr->num_components,
3126 is_patch, is_compact);
3127 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3128 }
3129
3130 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3131 LLVMValueRef indir_index;
3132 unsigned const_index, vertex_index;
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, &vertex_index, NULL,
3135 &const_index, &indir_index);
3136 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3137 instr->variables[0]->var->data.driver_location,
3138 instr->variables[0]->var->data.location_frac, ve,
3139 vertex_index, const_index,
3140 nir2llvmtype(ctx, instr->variables[0]->var->type));
3141 }
3142
3143 for (unsigned chan = comp; chan < ve + comp; chan++) {
3144 if (indir_index) {
3145 unsigned count = glsl_count_attribute_slots(
3146 instr->variables[0]->var->type,
3147 ctx->stage == MESA_SHADER_VERTEX);
3148 count -= chan / 4;
3149 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3150 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3151 stride, false, true);
3152
3153 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3154 tmp_vec,
3155 indir_index, "");
3156 } else
3157 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3158 }
3159 break;
3160 case nir_var_local:
3161 for (unsigned chan = 0; chan < ve; chan++) {
3162 if (indir_index) {
3163 unsigned count = glsl_count_attribute_slots(
3164 instr->variables[0]->var->type, false);
3165 count -= chan / 4;
3166 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3167 &ctx->ac, ctx->locals + idx + chan, count,
3168 stride, true, true);
3169
3170 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3171 tmp_vec,
3172 indir_index, "");
3173 } else {
3174 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3175 }
3176 }
3177 break;
3178 case nir_var_shared: {
3179 LLVMValueRef address = build_gep_for_deref(ctx,
3180 instr->variables[0]);
3181 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3182 return LLVMBuildBitCast(ctx->ac.builder, val,
3183 get_def_type(ctx, &instr->dest.ssa),
3184 "");
3185 }
3186 case nir_var_shader_out:
3187 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3188 return load_tcs_output(ctx->nctx, instr);
3189
3190 for (unsigned chan = comp; chan < ve + comp; chan++) {
3191 if (indir_index) {
3192 unsigned count = glsl_count_attribute_slots(
3193 instr->variables[0]->var->type, false);
3194 count -= chan / 4;
3195 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3196 &ctx->ac, ctx->outputs + idx + chan, count,
3197 stride, true, true);
3198
3199 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3200 tmp_vec,
3201 indir_index, "");
3202 } else {
3203 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3204 ctx->outputs[idx + chan + const_index * stride],
3205 "");
3206 }
3207 }
3208 break;
3209 default:
3210 unreachable("unhandle variable mode");
3211 }
3212 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3213 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3214 }
3215
3216 static void
3217 visit_store_var(struct ac_nir_context *ctx,
3218 nir_intrinsic_instr *instr)
3219 {
3220 LLVMValueRef temp_ptr, value;
3221 int idx = instr->variables[0]->var->data.driver_location;
3222 unsigned comp = instr->variables[0]->var->data.location_frac;
3223 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3224 int writemask = instr->const_index[0] << comp;
3225 LLVMValueRef indir_index;
3226 unsigned const_index;
3227 get_deref_offset(ctx, instr->variables[0], false,
3228 NULL, NULL, &const_index, &indir_index);
3229
3230 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3231 int old_writemask = writemask;
3232
3233 src = LLVMBuildBitCast(ctx->ac.builder, src,
3234 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3235 "");
3236
3237 writemask = 0;
3238 for (unsigned chan = 0; chan < 4; chan++) {
3239 if (old_writemask & (1 << chan))
3240 writemask |= 3u << (2 * chan);
3241 }
3242 }
3243
3244 switch (instr->variables[0]->var->data.mode) {
3245 case nir_var_shader_out:
3246
3247 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3248 LLVMValueRef vertex_index = NULL;
3249 LLVMValueRef indir_index = NULL;
3250 unsigned const_index = 0;
3251 const unsigned location = instr->variables[0]->var->data.location;
3252 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3253 const unsigned comp = instr->variables[0]->var->data.location_frac;
3254 const bool is_patch = instr->variables[0]->var->data.patch;
3255 const bool is_compact = instr->variables[0]->var->data.compact;
3256
3257 get_deref_offset(ctx, instr->variables[0],
3258 false, NULL, is_patch ? NULL : &vertex_index,
3259 &const_index, &indir_index);
3260
3261 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3262 const_index, location, driver_location,
3263 src, comp, is_patch, is_compact, writemask);
3264 return;
3265 }
3266
3267 for (unsigned chan = 0; chan < 8; chan++) {
3268 int stride = 4;
3269 if (!(writemask & (1 << chan)))
3270 continue;
3271
3272 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3273
3274 if (instr->variables[0]->var->data.compact)
3275 stride = 1;
3276 if (indir_index) {
3277 unsigned count = glsl_count_attribute_slots(
3278 instr->variables[0]->var->type, false);
3279 count -= chan / 4;
3280 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3281 &ctx->ac, ctx->outputs + idx + chan, count,
3282 stride, true, true);
3283
3284 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3285 value, indir_index, "");
3286 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3287 count, stride, tmp_vec);
3288
3289 } else {
3290 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3291
3292 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3293 }
3294 }
3295 break;
3296 case nir_var_local:
3297 for (unsigned chan = 0; chan < 8; chan++) {
3298 if (!(writemask & (1 << chan)))
3299 continue;
3300
3301 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3302 if (indir_index) {
3303 unsigned count = glsl_count_attribute_slots(
3304 instr->variables[0]->var->type, false);
3305 count -= chan / 4;
3306 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3307 &ctx->ac, ctx->locals + idx + chan, count,
3308 4, true, true);
3309
3310 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3311 value, indir_index, "");
3312 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3313 count, 4, tmp_vec);
3314 } else {
3315 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3316
3317 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3318 }
3319 }
3320 break;
3321 case nir_var_shared: {
3322 int writemask = instr->const_index[0];
3323 LLVMValueRef address = build_gep_for_deref(ctx,
3324 instr->variables[0]);
3325 LLVMValueRef val = get_src(ctx, instr->src[0]);
3326 unsigned components =
3327 glsl_get_vector_elements(
3328 nir_deref_tail(&instr->variables[0]->deref)->type);
3329 if (writemask == (1 << components) - 1) {
3330 val = LLVMBuildBitCast(
3331 ctx->ac.builder, val,
3332 LLVMGetElementType(LLVMTypeOf(address)), "");
3333 LLVMBuildStore(ctx->ac.builder, val, address);
3334 } else {
3335 for (unsigned chan = 0; chan < 4; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338 LLVMValueRef ptr =
3339 LLVMBuildStructGEP(ctx->ac.builder,
3340 address, chan, "");
3341 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3342 chan);
3343 src = LLVMBuildBitCast(
3344 ctx->ac.builder, src,
3345 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3346 LLVMBuildStore(ctx->ac.builder, src, ptr);
3347 }
3348 }
3349 break;
3350 }
3351 default:
3352 break;
3353 }
3354 }
3355
3356 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3357 {
3358 switch (dim) {
3359 case GLSL_SAMPLER_DIM_BUF:
3360 return 1;
3361 case GLSL_SAMPLER_DIM_1D:
3362 return array ? 2 : 1;
3363 case GLSL_SAMPLER_DIM_2D:
3364 return array ? 3 : 2;
3365 case GLSL_SAMPLER_DIM_MS:
3366 return array ? 4 : 3;
3367 case GLSL_SAMPLER_DIM_3D:
3368 case GLSL_SAMPLER_DIM_CUBE:
3369 return 3;
3370 case GLSL_SAMPLER_DIM_RECT:
3371 case GLSL_SAMPLER_DIM_SUBPASS:
3372 return 2;
3373 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3374 return 3;
3375 default:
3376 break;
3377 }
3378 return 0;
3379 }
3380
3381
3382
3383 /* Adjust the sample index according to FMASK.
3384 *
3385 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3386 * which is the identity mapping. Each nibble says which physical sample
3387 * should be fetched to get that sample.
3388 *
3389 * For example, 0x11111100 means there are only 2 samples stored and
3390 * the second sample covers 3/4 of the pixel. When reading samples 0
3391 * and 1, return physical sample 0 (determined by the first two 0s
3392 * in FMASK), otherwise return physical sample 1.
3393 *
3394 * The sample index should be adjusted as follows:
3395 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3396 */
3397 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3398 LLVMValueRef coord_x, LLVMValueRef coord_y,
3399 LLVMValueRef coord_z,
3400 LLVMValueRef sample_index,
3401 LLVMValueRef fmask_desc_ptr)
3402 {
3403 LLVMValueRef fmask_load_address[4];
3404 LLVMValueRef res;
3405
3406 fmask_load_address[0] = coord_x;
3407 fmask_load_address[1] = coord_y;
3408 if (coord_z) {
3409 fmask_load_address[2] = coord_z;
3410 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3411 }
3412
3413 struct ac_image_args args = {0};
3414
3415 args.opcode = ac_image_load;
3416 args.da = coord_z ? true : false;
3417 args.resource = fmask_desc_ptr;
3418 args.dmask = 0xf;
3419 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3420
3421 res = ac_build_image_opcode(ctx, &args);
3422
3423 res = ac_to_integer(ctx, res);
3424 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3425 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3426
3427 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3428 res,
3429 ctx->i32_0, "");
3430
3431 LLVMValueRef sample_index4 =
3432 LLVMBuildMul(ctx->builder, sample_index, four, "");
3433 LLVMValueRef shifted_fmask =
3434 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3435 LLVMValueRef final_sample =
3436 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3437
3438 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3439 * resource descriptor is 0 (invalid),
3440 */
3441 LLVMValueRef fmask_desc =
3442 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3443 ctx->v8i32, "");
3444
3445 LLVMValueRef fmask_word1 =
3446 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3447 ctx->i32_1, "");
3448
3449 LLVMValueRef word1_is_nonzero =
3450 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3451 fmask_word1, ctx->i32_0, "");
3452
3453 /* Replace the MSAA sample index. */
3454 sample_index =
3455 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3456 final_sample, sample_index, "");
3457 return sample_index;
3458 }
3459
3460 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3461 const nir_intrinsic_instr *instr)
3462 {
3463 const struct glsl_type *type = instr->variables[0]->var->type;
3464 if(instr->variables[0]->deref.child)
3465 type = instr->variables[0]->deref.child->type;
3466
3467 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3468 LLVMValueRef coords[4];
3469 LLVMValueRef masks[] = {
3470 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3471 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3472 };
3473 LLVMValueRef res;
3474 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3475
3476 int count;
3477 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3478 bool is_array = glsl_sampler_type_is_array(type);
3479 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3480 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3481 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3482 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3483 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3484 count = image_type_to_components_count(dim, is_array);
3485
3486 if (is_ms) {
3487 LLVMValueRef fmask_load_address[3];
3488 int chan;
3489
3490 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3491 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3492 if (is_array)
3493 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3494 else
3495 fmask_load_address[2] = NULL;
3496 if (add_frag_pos) {
3497 for (chan = 0; chan < 2; ++chan)
3498 fmask_load_address[chan] =
3499 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3500 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3501 ctx->ac.i32, ""), "");
3502 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3503 }
3504 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3505 fmask_load_address[0],
3506 fmask_load_address[1],
3507 fmask_load_address[2],
3508 sample_index,
3509 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3510 }
3511 if (count == 1 && !gfx9_1d) {
3512 if (instr->src[0].ssa->num_components)
3513 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3514 else
3515 res = src0;
3516 } else {
3517 int chan;
3518 if (is_ms)
3519 count--;
3520 for (chan = 0; chan < count; ++chan) {
3521 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3522 }
3523 if (add_frag_pos) {
3524 for (chan = 0; chan < 2; ++chan)
3525 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3526 ctx->ac.i32, ""), "");
3527 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3528 count++;
3529 }
3530
3531 if (gfx9_1d) {
3532 if (is_array) {
3533 coords[2] = coords[1];
3534 coords[1] = ctx->ac.i32_0;
3535 } else
3536 coords[1] = ctx->ac.i32_0;
3537 count++;
3538 }
3539
3540 if (is_ms) {
3541 coords[count] = sample_index;
3542 count++;
3543 }
3544
3545 if (count == 3) {
3546 coords[3] = LLVMGetUndef(ctx->ac.i32);
3547 count = 4;
3548 }
3549 res = ac_build_gather_values(&ctx->ac, coords, count);
3550 }
3551 return res;
3552 }
3553
3554 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3555 const nir_intrinsic_instr *instr)
3556 {
3557 LLVMValueRef params[7];
3558 LLVMValueRef res;
3559 char intrinsic_name[64];
3560 const nir_variable *var = instr->variables[0]->var;
3561 const struct glsl_type *type = var->type;
3562
3563 if(instr->variables[0]->deref.child)
3564 type = instr->variables[0]->deref.child->type;
3565
3566 type = glsl_without_array(type);
3567 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3568 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3569 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3570 ctx->ac.i32_0, ""); /* vindex */
3571 params[2] = ctx->ac.i32_0; /* voffset */
3572 params[3] = ctx->ac.i1false; /* glc */
3573 params[4] = ctx->ac.i1false; /* slc */
3574 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3575 params, 5, 0);
3576
3577 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3578 res = ac_to_integer(&ctx->ac, res);
3579 } else {
3580 bool is_da = glsl_sampler_type_is_array(type) ||
3581 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3582 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3583 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3584 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3585 LLVMValueRef glc = ctx->ac.i1false;
3586 LLVMValueRef slc = ctx->ac.i1false;
3587
3588 params[0] = get_image_coords(ctx, instr);
3589 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3590 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3591 if (HAVE_LLVM <= 0x0309) {
3592 params[3] = ctx->ac.i1false; /* r128 */
3593 params[4] = da;
3594 params[5] = glc;
3595 params[6] = slc;
3596 } else {
3597 LLVMValueRef lwe = ctx->ac.i1false;
3598 params[3] = glc;
3599 params[4] = slc;
3600 params[5] = lwe;
3601 params[6] = da;
3602 }
3603
3604 ac_get_image_intr_name("llvm.amdgcn.image.load",
3605 ctx->ac.v4f32, /* vdata */
3606 LLVMTypeOf(params[0]), /* coords */
3607 LLVMTypeOf(params[1]), /* rsrc */
3608 intrinsic_name, sizeof(intrinsic_name));
3609
3610 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3611 params, 7, AC_FUNC_ATTR_READONLY);
3612 }
3613 return ac_to_integer(&ctx->ac, res);
3614 }
3615
3616 static void visit_image_store(struct ac_nir_context *ctx,
3617 nir_intrinsic_instr *instr)
3618 {
3619 LLVMValueRef params[8];
3620 char intrinsic_name[64];
3621 const nir_variable *var = instr->variables[0]->var;
3622 const struct glsl_type *type = glsl_without_array(var->type);
3623 LLVMValueRef glc = ctx->ac.i1false;
3624 bool force_glc = ctx->ac.chip_class == SI;
3625 if (force_glc)
3626 glc = ctx->ac.i1true;
3627
3628 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3629 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3630 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3631 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3632 ctx->ac.i32_0, ""); /* vindex */
3633 params[3] = ctx->ac.i32_0; /* voffset */
3634 params[4] = glc; /* glc */
3635 params[5] = ctx->ac.i1false; /* slc */
3636 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3637 params, 6, 0);
3638 } else {
3639 bool is_da = glsl_sampler_type_is_array(type) ||
3640 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3641 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3642 LLVMValueRef slc = ctx->ac.i1false;
3643
3644 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3645 params[1] = get_image_coords(ctx, instr); /* coords */
3646 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3647 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3648 if (HAVE_LLVM <= 0x0309) {
3649 params[4] = ctx->ac.i1false; /* r128 */
3650 params[5] = da;
3651 params[6] = glc;
3652 params[7] = slc;
3653 } else {
3654 LLVMValueRef lwe = ctx->ac.i1false;
3655 params[4] = glc;
3656 params[5] = slc;
3657 params[6] = lwe;
3658 params[7] = da;
3659 }
3660
3661 ac_get_image_intr_name("llvm.amdgcn.image.store",
3662 LLVMTypeOf(params[0]), /* vdata */
3663 LLVMTypeOf(params[1]), /* coords */
3664 LLVMTypeOf(params[2]), /* rsrc */
3665 intrinsic_name, sizeof(intrinsic_name));
3666
3667 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3668 params, 8, 0);
3669 }
3670
3671 }
3672
3673 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3674 const nir_intrinsic_instr *instr)
3675 {
3676 LLVMValueRef params[7];
3677 int param_count = 0;
3678 const nir_variable *var = instr->variables[0]->var;
3679
3680 const char *atomic_name;
3681 char intrinsic_name[41];
3682 const struct glsl_type *type = glsl_without_array(var->type);
3683 MAYBE_UNUSED int length;
3684
3685 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3686
3687 switch (instr->intrinsic) {
3688 case nir_intrinsic_image_atomic_add:
3689 atomic_name = "add";
3690 break;
3691 case nir_intrinsic_image_atomic_min:
3692 atomic_name = is_unsigned ? "umin" : "smin";
3693 break;
3694 case nir_intrinsic_image_atomic_max:
3695 atomic_name = is_unsigned ? "umax" : "smax";
3696 break;
3697 case nir_intrinsic_image_atomic_and:
3698 atomic_name = "and";
3699 break;
3700 case nir_intrinsic_image_atomic_or:
3701 atomic_name = "or";
3702 break;
3703 case nir_intrinsic_image_atomic_xor:
3704 atomic_name = "xor";
3705 break;
3706 case nir_intrinsic_image_atomic_exchange:
3707 atomic_name = "swap";
3708 break;
3709 case nir_intrinsic_image_atomic_comp_swap:
3710 atomic_name = "cmpswap";
3711 break;
3712 default:
3713 abort();
3714 }
3715
3716 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3717 params[param_count++] = get_src(ctx, instr->src[3]);
3718 params[param_count++] = get_src(ctx, instr->src[2]);
3719
3720 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3721 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3722 NULL, true, true);
3723 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3724 ctx->ac.i32_0, ""); /* vindex */
3725 params[param_count++] = ctx->ac.i32_0; /* voffset */
3726 params[param_count++] = ctx->ac.i1false; /* slc */
3727
3728 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3729 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3730 } else {
3731 char coords_type[8];
3732
3733 bool da = glsl_sampler_type_is_array(type) ||
3734 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3735
3736 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3737 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3738 NULL, true, true);
3739 params[param_count++] = ctx->ac.i1false; /* r128 */
3740 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3741 params[param_count++] = ctx->ac.i1false; /* slc */
3742
3743 build_int_type_name(LLVMTypeOf(coords),
3744 coords_type, sizeof(coords_type));
3745
3746 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3747 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3748 }
3749
3750 assert(length < sizeof(intrinsic_name));
3751 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3752 }
3753
3754 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3755 const nir_intrinsic_instr *instr)
3756 {
3757 LLVMValueRef res;
3758 const nir_variable *var = instr->variables[0]->var;
3759 const struct glsl_type *type = instr->variables[0]->var->type;
3760 bool da = glsl_sampler_type_is_array(var->type) ||
3761 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3762 if(instr->variables[0]->deref.child)
3763 type = instr->variables[0]->deref.child->type;
3764
3765 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3766 return get_buffer_size(ctx,
3767 get_sampler_desc(ctx, instr->variables[0],
3768 AC_DESC_BUFFER, NULL, true, false), true);
3769
3770 struct ac_image_args args = { 0 };
3771
3772 args.da = da;
3773 args.dmask = 0xf;
3774 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3775 args.opcode = ac_image_get_resinfo;
3776 args.addr = ctx->ac.i32_0;
3777
3778 res = ac_build_image_opcode(&ctx->ac, &args);
3779
3780 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3781
3782 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3783 glsl_sampler_type_is_array(type)) {
3784 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3785 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3786 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3787 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3788 }
3789 if (ctx->ac.chip_class >= GFX9 &&
3790 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3791 glsl_sampler_type_is_array(type)) {
3792 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3793 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3794 ctx->ac.i32_1, "");
3795
3796 }
3797 return res;
3798 }
3799
3800 #define NOOP_WAITCNT 0xf7f
3801 #define LGKM_CNT 0x07f
3802 #define VM_CNT 0xf70
3803
3804 static void emit_membar(struct nir_to_llvm_context *ctx,
3805 const nir_intrinsic_instr *instr)
3806 {
3807 unsigned waitcnt = NOOP_WAITCNT;
3808
3809 switch (instr->intrinsic) {
3810 case nir_intrinsic_memory_barrier:
3811 case nir_intrinsic_group_memory_barrier:
3812 waitcnt &= VM_CNT & LGKM_CNT;
3813 break;
3814 case nir_intrinsic_memory_barrier_atomic_counter:
3815 case nir_intrinsic_memory_barrier_buffer:
3816 case nir_intrinsic_memory_barrier_image:
3817 waitcnt &= VM_CNT;
3818 break;
3819 case nir_intrinsic_memory_barrier_shared:
3820 waitcnt &= LGKM_CNT;
3821 break;
3822 default:
3823 break;
3824 }
3825 if (waitcnt != NOOP_WAITCNT)
3826 ac_build_waitcnt(&ctx->ac, waitcnt);
3827 }
3828
3829 static void emit_barrier(struct nir_to_llvm_context *ctx)
3830 {
3831 /* SI only (thanks to a hw bug workaround):
3832 * The real barrier instruction isn’t needed, because an entire patch
3833 * always fits into a single wave.
3834 */
3835 if (ctx->options->chip_class == SI &&
3836 ctx->stage == MESA_SHADER_TESS_CTRL) {
3837 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3838 return;
3839 }
3840 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3841 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3842 }
3843
3844 static void emit_discard_if(struct ac_nir_context *ctx,
3845 const nir_intrinsic_instr *instr)
3846 {
3847 LLVMValueRef cond;
3848
3849 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3850 get_src(ctx, instr->src[0]),
3851 ctx->ac.i32_0, "");
3852 ac_build_kill_if_false(&ctx->ac, cond);
3853 }
3854
3855 static LLVMValueRef
3856 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3857 {
3858 LLVMValueRef result;
3859 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3860 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3861 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3862
3863 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3864 }
3865
3866 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3867 const nir_intrinsic_instr *instr)
3868 {
3869 LLVMValueRef ptr, result;
3870 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3871 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3872
3873 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3874 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3875 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3876 ptr, src, src1,
3877 LLVMAtomicOrderingSequentiallyConsistent,
3878 LLVMAtomicOrderingSequentiallyConsistent,
3879 false);
3880 } else {
3881 LLVMAtomicRMWBinOp op;
3882 switch (instr->intrinsic) {
3883 case nir_intrinsic_var_atomic_add:
3884 op = LLVMAtomicRMWBinOpAdd;
3885 break;
3886 case nir_intrinsic_var_atomic_umin:
3887 op = LLVMAtomicRMWBinOpUMin;
3888 break;
3889 case nir_intrinsic_var_atomic_umax:
3890 op = LLVMAtomicRMWBinOpUMax;
3891 break;
3892 case nir_intrinsic_var_atomic_imin:
3893 op = LLVMAtomicRMWBinOpMin;
3894 break;
3895 case nir_intrinsic_var_atomic_imax:
3896 op = LLVMAtomicRMWBinOpMax;
3897 break;
3898 case nir_intrinsic_var_atomic_and:
3899 op = LLVMAtomicRMWBinOpAnd;
3900 break;
3901 case nir_intrinsic_var_atomic_or:
3902 op = LLVMAtomicRMWBinOpOr;
3903 break;
3904 case nir_intrinsic_var_atomic_xor:
3905 op = LLVMAtomicRMWBinOpXor;
3906 break;
3907 case nir_intrinsic_var_atomic_exchange:
3908 op = LLVMAtomicRMWBinOpXchg;
3909 break;
3910 default:
3911 return NULL;
3912 }
3913
3914 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3915 LLVMAtomicOrderingSequentiallyConsistent,
3916 false);
3917 }
3918 return result;
3919 }
3920
3921 #define INTERP_CENTER 0
3922 #define INTERP_CENTROID 1
3923 #define INTERP_SAMPLE 2
3924
3925 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3926 enum glsl_interp_mode interp, unsigned location)
3927 {
3928 switch (interp) {
3929 case INTERP_MODE_FLAT:
3930 default:
3931 return NULL;
3932 case INTERP_MODE_SMOOTH:
3933 case INTERP_MODE_NONE:
3934 if (location == INTERP_CENTER)
3935 return ctx->persp_center;
3936 else if (location == INTERP_CENTROID)
3937 return ctx->persp_centroid;
3938 else if (location == INTERP_SAMPLE)
3939 return ctx->persp_sample;
3940 break;
3941 case INTERP_MODE_NOPERSPECTIVE:
3942 if (location == INTERP_CENTER)
3943 return ctx->linear_center;
3944 else if (location == INTERP_CENTROID)
3945 return ctx->linear_centroid;
3946 else if (location == INTERP_SAMPLE)
3947 return ctx->linear_sample;
3948 break;
3949 }
3950 return NULL;
3951 }
3952
3953 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3954 LLVMValueRef sample_id)
3955 {
3956 LLVMValueRef result;
3957 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3958
3959 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3960 const_array(ctx->ac.v2f32, 64), "");
3961
3962 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3963 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3964
3965 return result;
3966 }
3967
3968 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3969 {
3970 LLVMValueRef values[2];
3971
3972 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3973 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3974 return ac_build_gather_values(&ctx->ac, values, 2);
3975 }
3976
3977 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3978 const nir_intrinsic_instr *instr)
3979 {
3980 LLVMValueRef result[4];
3981 LLVMValueRef interp_param, attr_number;
3982 unsigned location;
3983 unsigned chan;
3984 LLVMValueRef src_c0 = NULL;
3985 LLVMValueRef src_c1 = NULL;
3986 LLVMValueRef src0 = NULL;
3987 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3988 switch (instr->intrinsic) {
3989 case nir_intrinsic_interp_var_at_centroid:
3990 location = INTERP_CENTROID;
3991 break;
3992 case nir_intrinsic_interp_var_at_sample:
3993 case nir_intrinsic_interp_var_at_offset:
3994 location = INTERP_CENTER;
3995 src0 = get_src(ctx->nir, instr->src[0]);
3996 break;
3997 default:
3998 break;
3999 }
4000
4001 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4002 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4003 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4004 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4005 LLVMValueRef sample_position;
4006 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4007
4008 /* fetch sample ID */
4009 sample_position = load_sample_position(ctx, src0);
4010
4011 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4012 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4013 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4014 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4015 }
4016 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4017 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4018
4019 if (location == INTERP_CENTER) {
4020 LLVMValueRef ij_out[2];
4021 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4022
4023 /*
4024 * take the I then J parameters, and the DDX/Y for it, and
4025 * calculate the IJ inputs for the interpolator.
4026 * temp1 = ddx * offset/sample.x + I;
4027 * interp_param.I = ddy * offset/sample.y + temp1;
4028 * temp1 = ddx * offset/sample.x + J;
4029 * interp_param.J = ddy * offset/sample.y + temp1;
4030 */
4031 for (unsigned i = 0; i < 2; i++) {
4032 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4033 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4034 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4035 ddxy_out, ix_ll, "");
4036 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4037 ddxy_out, iy_ll, "");
4038 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4039 interp_param, ix_ll, "");
4040 LLVMValueRef temp1, temp2;
4041
4042 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4043 ctx->ac.f32, "");
4044
4045 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4046 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4047
4048 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4049 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4050
4051 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4052 temp2, ctx->ac.i32, "");
4053 }
4054 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4055
4056 }
4057
4058 for (chan = 0; chan < 4; chan++) {
4059 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4060
4061 if (interp_param) {
4062 interp_param = LLVMBuildBitCast(ctx->builder,
4063 interp_param, ctx->ac.v2f32, "");
4064 LLVMValueRef i = LLVMBuildExtractElement(
4065 ctx->builder, interp_param, ctx->ac.i32_0, "");
4066 LLVMValueRef j = LLVMBuildExtractElement(
4067 ctx->builder, interp_param, ctx->ac.i32_1, "");
4068
4069 result[chan] = ac_build_fs_interp(&ctx->ac,
4070 llvm_chan, attr_number,
4071 ctx->prim_mask, i, j);
4072 } else {
4073 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4074 LLVMConstInt(ctx->ac.i32, 2, false),
4075 llvm_chan, attr_number,
4076 ctx->prim_mask);
4077 }
4078 }
4079 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4080 instr->variables[0]->var->data.location_frac);
4081 }
4082
4083 static void
4084 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4085 {
4086 LLVMValueRef gs_next_vertex;
4087 LLVMValueRef can_emit;
4088 int idx;
4089 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4090
4091 /* Write vertex attribute values to GSVS ring */
4092 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4093 ctx->gs_next_vertex,
4094 "");
4095
4096 /* If this thread has already emitted the declared maximum number of
4097 * vertices, kill it: excessive vertex emissions are not supposed to
4098 * have any effect, and GS threads have no externally observable
4099 * effects other than emitting vertices.
4100 */
4101 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4102 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4103 ac_build_kill_if_false(&ctx->ac, can_emit);
4104
4105 /* loop num outputs */
4106 idx = 0;
4107 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4108 LLVMValueRef *out_ptr = &addrs[i * 4];
4109 int length = 4;
4110 int slot = idx;
4111 int slot_inc = 1;
4112
4113 if (!(ctx->output_mask & (1ull << i)))
4114 continue;
4115
4116 if (i == VARYING_SLOT_CLIP_DIST0) {
4117 /* pack clip and cull into a single set of slots */
4118 length = ctx->num_output_clips + ctx->num_output_culls;
4119 if (length > 4)
4120 slot_inc = 2;
4121 }
4122 for (unsigned j = 0; j < length; j++) {
4123 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4124 out_ptr[j], "");
4125 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4126 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4127 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4128
4129 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4130
4131 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4132 out_val, 1,
4133 voffset, ctx->gs2vs_offset, 0,
4134 1, 1, true, true);
4135 }
4136 idx += slot_inc;
4137 }
4138
4139 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4140 ctx->ac.i32_1, "");
4141 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4142
4143 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4144 }
4145
4146 static void
4147 visit_end_primitive(struct nir_to_llvm_context *ctx,
4148 const nir_intrinsic_instr *instr)
4149 {
4150 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4151 }
4152
4153 static LLVMValueRef
4154 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4155 unsigned num_components)
4156 {
4157 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4158
4159 LLVMValueRef coord[4] = {
4160 ctx->tes_u,
4161 ctx->tes_v,
4162 ctx->ac.f32_0,
4163 ctx->ac.f32_0,
4164 };
4165
4166 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4167 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4168 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4169
4170 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4171 return LLVMBuildBitCast(ctx->builder, result, type, "");
4172 }
4173
4174 static void visit_intrinsic(struct ac_nir_context *ctx,
4175 nir_intrinsic_instr *instr)
4176 {
4177 LLVMValueRef result = NULL;
4178
4179 switch (instr->intrinsic) {
4180 case nir_intrinsic_load_work_group_id: {
4181 LLVMValueRef values[3];
4182
4183 for (int i = 0; i < 3; i++) {
4184 values[i] = ctx->nctx->workgroup_ids[i] ?
4185 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4186 }
4187
4188 result = ac_build_gather_values(&ctx->ac, values, 3);
4189 break;
4190 }
4191 case nir_intrinsic_load_base_vertex: {
4192 result = ctx->abi->base_vertex;
4193 break;
4194 }
4195 case nir_intrinsic_load_vertex_id_zero_base: {
4196 result = ctx->abi->vertex_id;
4197 break;
4198 }
4199 case nir_intrinsic_load_local_invocation_id: {
4200 result = ctx->nctx->local_invocation_ids;
4201 break;
4202 }
4203 case nir_intrinsic_load_base_instance:
4204 result = ctx->abi->start_instance;
4205 break;
4206 case nir_intrinsic_load_draw_id:
4207 result = ctx->abi->draw_id;
4208 break;
4209 case nir_intrinsic_load_view_index:
4210 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4211 break;
4212 case nir_intrinsic_load_invocation_id:
4213 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4214 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4215 else
4216 result = ctx->abi->gs_invocation_id;
4217 break;
4218 case nir_intrinsic_load_primitive_id:
4219 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4220 result = ctx->abi->gs_prim_id;
4221 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4222 result = ctx->abi->tcs_patch_id;
4223 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4224 result = ctx->abi->tes_patch_id;
4225 } else
4226 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4227 break;
4228 case nir_intrinsic_load_sample_id:
4229 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4230 break;
4231 case nir_intrinsic_load_sample_pos:
4232 result = load_sample_pos(ctx);
4233 break;
4234 case nir_intrinsic_load_sample_mask_in:
4235 result = ctx->abi->sample_coverage;
4236 break;
4237 case nir_intrinsic_load_frag_coord: {
4238 LLVMValueRef values[4] = {
4239 ctx->abi->frag_pos[0],
4240 ctx->abi->frag_pos[1],
4241 ctx->abi->frag_pos[2],
4242 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4243 };
4244 result = ac_build_gather_values(&ctx->ac, values, 4);
4245 break;
4246 }
4247 case nir_intrinsic_load_front_face:
4248 result = ctx->abi->front_face;
4249 break;
4250 case nir_intrinsic_load_instance_id:
4251 result = ctx->abi->instance_id;
4252 break;
4253 case nir_intrinsic_load_num_work_groups:
4254 result = ctx->nctx->num_work_groups;
4255 break;
4256 case nir_intrinsic_load_local_invocation_index:
4257 result = visit_load_local_invocation_index(ctx->nctx);
4258 break;
4259 case nir_intrinsic_load_push_constant:
4260 result = visit_load_push_constant(ctx->nctx, instr);
4261 break;
4262 case nir_intrinsic_vulkan_resource_index:
4263 result = visit_vulkan_resource_index(ctx->nctx, instr);
4264 break;
4265 case nir_intrinsic_vulkan_resource_reindex:
4266 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4267 break;
4268 case nir_intrinsic_store_ssbo:
4269 visit_store_ssbo(ctx, instr);
4270 break;
4271 case nir_intrinsic_load_ssbo:
4272 result = visit_load_buffer(ctx, instr);
4273 break;
4274 case nir_intrinsic_ssbo_atomic_add:
4275 case nir_intrinsic_ssbo_atomic_imin:
4276 case nir_intrinsic_ssbo_atomic_umin:
4277 case nir_intrinsic_ssbo_atomic_imax:
4278 case nir_intrinsic_ssbo_atomic_umax:
4279 case nir_intrinsic_ssbo_atomic_and:
4280 case nir_intrinsic_ssbo_atomic_or:
4281 case nir_intrinsic_ssbo_atomic_xor:
4282 case nir_intrinsic_ssbo_atomic_exchange:
4283 case nir_intrinsic_ssbo_atomic_comp_swap:
4284 result = visit_atomic_ssbo(ctx, instr);
4285 break;
4286 case nir_intrinsic_load_ubo:
4287 result = visit_load_ubo_buffer(ctx, instr);
4288 break;
4289 case nir_intrinsic_get_buffer_size:
4290 result = visit_get_buffer_size(ctx, instr);
4291 break;
4292 case nir_intrinsic_load_var:
4293 result = visit_load_var(ctx, instr);
4294 break;
4295 case nir_intrinsic_store_var:
4296 visit_store_var(ctx, instr);
4297 break;
4298 case nir_intrinsic_image_load:
4299 result = visit_image_load(ctx, instr);
4300 break;
4301 case nir_intrinsic_image_store:
4302 visit_image_store(ctx, instr);
4303 break;
4304 case nir_intrinsic_image_atomic_add:
4305 case nir_intrinsic_image_atomic_min:
4306 case nir_intrinsic_image_atomic_max:
4307 case nir_intrinsic_image_atomic_and:
4308 case nir_intrinsic_image_atomic_or:
4309 case nir_intrinsic_image_atomic_xor:
4310 case nir_intrinsic_image_atomic_exchange:
4311 case nir_intrinsic_image_atomic_comp_swap:
4312 result = visit_image_atomic(ctx, instr);
4313 break;
4314 case nir_intrinsic_image_size:
4315 result = visit_image_size(ctx, instr);
4316 break;
4317 case nir_intrinsic_discard:
4318 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4319 LLVMVoidTypeInContext(ctx->ac.context),
4320 NULL, 0, AC_FUNC_ATTR_LEGACY);
4321 break;
4322 case nir_intrinsic_discard_if:
4323 emit_discard_if(ctx, instr);
4324 break;
4325 case nir_intrinsic_memory_barrier:
4326 case nir_intrinsic_group_memory_barrier:
4327 case nir_intrinsic_memory_barrier_atomic_counter:
4328 case nir_intrinsic_memory_barrier_buffer:
4329 case nir_intrinsic_memory_barrier_image:
4330 case nir_intrinsic_memory_barrier_shared:
4331 emit_membar(ctx->nctx, instr);
4332 break;
4333 case nir_intrinsic_barrier:
4334 emit_barrier(ctx->nctx);
4335 break;
4336 case nir_intrinsic_var_atomic_add:
4337 case nir_intrinsic_var_atomic_imin:
4338 case nir_intrinsic_var_atomic_umin:
4339 case nir_intrinsic_var_atomic_imax:
4340 case nir_intrinsic_var_atomic_umax:
4341 case nir_intrinsic_var_atomic_and:
4342 case nir_intrinsic_var_atomic_or:
4343 case nir_intrinsic_var_atomic_xor:
4344 case nir_intrinsic_var_atomic_exchange:
4345 case nir_intrinsic_var_atomic_comp_swap:
4346 result = visit_var_atomic(ctx->nctx, instr);
4347 break;
4348 case nir_intrinsic_interp_var_at_centroid:
4349 case nir_intrinsic_interp_var_at_sample:
4350 case nir_intrinsic_interp_var_at_offset:
4351 result = visit_interp(ctx->nctx, instr);
4352 break;
4353 case nir_intrinsic_emit_vertex:
4354 assert(instr->const_index[0] == 0);
4355 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4356 break;
4357 case nir_intrinsic_end_primitive:
4358 visit_end_primitive(ctx->nctx, instr);
4359 break;
4360 case nir_intrinsic_load_tess_coord: {
4361 LLVMTypeRef type = ctx->nctx ?
4362 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4363 NULL;
4364 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4365 break;
4366 }
4367 case nir_intrinsic_load_patch_vertices_in:
4368 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4369 break;
4370 default:
4371 fprintf(stderr, "Unknown intrinsic: ");
4372 nir_print_instr(&instr->instr, stderr);
4373 fprintf(stderr, "\n");
4374 break;
4375 }
4376 if (result) {
4377 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4378 }
4379 }
4380
4381 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4382 LLVMValueRef buffer_ptr, bool write)
4383 {
4384 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4385
4386 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4387 ctx->shader_info->fs.writes_memory = true;
4388
4389 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4390 }
4391
4392 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4393 {
4394 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4395
4396 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4397 }
4398
4399 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4400 unsigned descriptor_set,
4401 unsigned base_index,
4402 unsigned constant_index,
4403 LLVMValueRef index,
4404 enum ac_descriptor_type desc_type,
4405 bool image, bool write)
4406 {
4407 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4408 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4409 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4410 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4411 unsigned offset = binding->offset;
4412 unsigned stride = binding->size;
4413 unsigned type_size;
4414 LLVMBuilderRef builder = ctx->builder;
4415 LLVMTypeRef type;
4416
4417 assert(base_index < layout->binding_count);
4418
4419 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4420 ctx->shader_info->fs.writes_memory = true;
4421
4422 switch (desc_type) {
4423 case AC_DESC_IMAGE:
4424 type = ctx->ac.v8i32;
4425 type_size = 32;
4426 break;
4427 case AC_DESC_FMASK:
4428 type = ctx->ac.v8i32;
4429 offset += 32;
4430 type_size = 32;
4431 break;
4432 case AC_DESC_SAMPLER:
4433 type = ctx->ac.v4i32;
4434 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4435 offset += 64;
4436
4437 type_size = 16;
4438 break;
4439 case AC_DESC_BUFFER:
4440 type = ctx->ac.v4i32;
4441 type_size = 16;
4442 break;
4443 default:
4444 unreachable("invalid desc_type\n");
4445 }
4446
4447 offset += constant_index * stride;
4448
4449 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4450 (!index || binding->immutable_samplers_equal)) {
4451 if (binding->immutable_samplers_equal)
4452 constant_index = 0;
4453
4454 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4455
4456 LLVMValueRef constants[] = {
4457 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4458 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4459 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4460 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4461 };
4462 return ac_build_gather_values(&ctx->ac, constants, 4);
4463 }
4464
4465 assert(stride % type_size == 0);
4466
4467 if (!index)
4468 index = ctx->ac.i32_0;
4469
4470 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4471
4472 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4473 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4474
4475 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4476 }
4477
4478 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4479 const nir_deref_var *deref,
4480 enum ac_descriptor_type desc_type,
4481 const nir_tex_instr *tex_instr,
4482 bool image, bool write)
4483 {
4484 LLVMValueRef index = NULL;
4485 unsigned constant_index = 0;
4486 unsigned descriptor_set;
4487 unsigned base_index;
4488
4489 if (!deref) {
4490 assert(tex_instr && !image);
4491 descriptor_set = 0;
4492 base_index = tex_instr->sampler_index;
4493 } else {
4494 const nir_deref *tail = &deref->deref;
4495 while (tail->child) {
4496 const nir_deref_array *child = nir_deref_as_array(tail->child);
4497 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4498
4499 if (!array_size)
4500 array_size = 1;
4501
4502 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4503
4504 if (child->deref_array_type == nir_deref_array_type_indirect) {
4505 LLVMValueRef indirect = get_src(ctx, child->indirect);
4506
4507 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4508 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4509
4510 if (!index)
4511 index = indirect;
4512 else
4513 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4514 }
4515
4516 constant_index += child->base_offset * array_size;
4517
4518 tail = &child->deref;
4519 }
4520 descriptor_set = deref->var->data.descriptor_set;
4521 base_index = deref->var->data.binding;
4522 }
4523
4524 return ctx->abi->load_sampler_desc(ctx->abi,
4525 descriptor_set,
4526 base_index,
4527 constant_index, index,
4528 desc_type, image, write);
4529 }
4530
4531 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4532 struct ac_image_args *args,
4533 const nir_tex_instr *instr,
4534 nir_texop op,
4535 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4536 LLVMValueRef *param, unsigned count,
4537 unsigned dmask)
4538 {
4539 unsigned is_rect = 0;
4540 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4541
4542 if (op == nir_texop_lod)
4543 da = false;
4544 /* Pad to power of two vector */
4545 while (count < util_next_power_of_two(count))
4546 param[count++] = LLVMGetUndef(ctx->i32);
4547
4548 if (count > 1)
4549 args->addr = ac_build_gather_values(ctx, param, count);
4550 else
4551 args->addr = param[0];
4552
4553 args->resource = res_ptr;
4554 args->sampler = samp_ptr;
4555
4556 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4557 args->addr = param[0];
4558 return;
4559 }
4560
4561 args->dmask = dmask;
4562 args->unorm = is_rect;
4563 args->da = da;
4564 }
4565
4566 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4567 *
4568 * SI-CI:
4569 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4570 * filtering manually. The driver sets img7 to a mask clearing
4571 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4572 * s_and_b32 samp0, samp0, img7
4573 *
4574 * VI:
4575 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4576 */
4577 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4578 LLVMValueRef res, LLVMValueRef samp)
4579 {
4580 LLVMBuilderRef builder = ctx->ac.builder;
4581 LLVMValueRef img7, samp0;
4582
4583 if (ctx->ac.chip_class >= VI)
4584 return samp;
4585
4586 img7 = LLVMBuildExtractElement(builder, res,
4587 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4588 samp0 = LLVMBuildExtractElement(builder, samp,
4589 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4590 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4591 return LLVMBuildInsertElement(builder, samp, samp0,
4592 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4593 }
4594
4595 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4596 nir_tex_instr *instr,
4597 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4598 LLVMValueRef *fmask_ptr)
4599 {
4600 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4601 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4602 else
4603 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4604 if (samp_ptr) {
4605 if (instr->sampler)
4606 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4607 else
4608 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4609 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4610 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4611 }
4612 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4613 instr->op == nir_texop_samples_identical))
4614 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4615 }
4616
4617 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4618 LLVMValueRef coord)
4619 {
4620 coord = ac_to_float(ctx, coord);
4621 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4622 coord = ac_to_integer(ctx, coord);
4623 return coord;
4624 }
4625
4626 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4627 {
4628 LLVMValueRef result = NULL;
4629 struct ac_image_args args = { 0 };
4630 unsigned dmask = 0xf;
4631 LLVMValueRef address[16];
4632 LLVMValueRef coords[5];
4633 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4634 LLVMValueRef bias = NULL, offsets = NULL;
4635 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4636 LLVMValueRef ddx = NULL, ddy = NULL;
4637 LLVMValueRef derivs[6];
4638 unsigned chan, count = 0;
4639 unsigned const_src = 0, num_deriv_comp = 0;
4640 bool lod_is_zero = false;
4641
4642 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4643
4644 for (unsigned i = 0; i < instr->num_srcs; i++) {
4645 switch (instr->src[i].src_type) {
4646 case nir_tex_src_coord:
4647 coord = get_src(ctx, instr->src[i].src);
4648 break;
4649 case nir_tex_src_projector:
4650 break;
4651 case nir_tex_src_comparator:
4652 comparator = get_src(ctx, instr->src[i].src);
4653 break;
4654 case nir_tex_src_offset:
4655 offsets = get_src(ctx, instr->src[i].src);
4656 const_src = i;
4657 break;
4658 case nir_tex_src_bias:
4659 bias = get_src(ctx, instr->src[i].src);
4660 break;
4661 case nir_tex_src_lod: {
4662 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4663
4664 if (val && val->i32[0] == 0)
4665 lod_is_zero = true;
4666 lod = get_src(ctx, instr->src[i].src);
4667 break;
4668 }
4669 case nir_tex_src_ms_index:
4670 sample_index = get_src(ctx, instr->src[i].src);
4671 break;
4672 case nir_tex_src_ms_mcs:
4673 break;
4674 case nir_tex_src_ddx:
4675 ddx = get_src(ctx, instr->src[i].src);
4676 num_deriv_comp = instr->src[i].src.ssa->num_components;
4677 break;
4678 case nir_tex_src_ddy:
4679 ddy = get_src(ctx, instr->src[i].src);
4680 break;
4681 case nir_tex_src_texture_offset:
4682 case nir_tex_src_sampler_offset:
4683 case nir_tex_src_plane:
4684 default:
4685 break;
4686 }
4687 }
4688
4689 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4690 result = get_buffer_size(ctx, res_ptr, true);
4691 goto write_result;
4692 }
4693
4694 if (instr->op == nir_texop_texture_samples) {
4695 LLVMValueRef res, samples, is_msaa;
4696 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4697 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4698 LLVMConstInt(ctx->ac.i32, 3, false), "");
4699 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4700 LLVMConstInt(ctx->ac.i32, 28, false), "");
4701 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4702 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4703 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4704 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4705
4706 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4707 LLVMConstInt(ctx->ac.i32, 16, false), "");
4708 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4709 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4710 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4711 samples, "");
4712 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4713 ctx->ac.i32_1, "");
4714 result = samples;
4715 goto write_result;
4716 }
4717
4718 if (coord)
4719 for (chan = 0; chan < instr->coord_components; chan++)
4720 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4721
4722 if (offsets && instr->op != nir_texop_txf) {
4723 LLVMValueRef offset[3], pack;
4724 for (chan = 0; chan < 3; ++chan)
4725 offset[chan] = ctx->ac.i32_0;
4726
4727 args.offset = true;
4728 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4729 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4730 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4731 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4732 if (chan)
4733 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4734 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4735 }
4736 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4737 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4738 address[count++] = pack;
4739
4740 }
4741 /* pack LOD bias value */
4742 if (instr->op == nir_texop_txb && bias) {
4743 address[count++] = bias;
4744 }
4745
4746 /* Pack depth comparison value */
4747 if (instr->is_shadow && comparator) {
4748 LLVMValueRef z = ac_to_float(&ctx->ac,
4749 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4750
4751 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4752 * so the depth comparison value isn't clamped for Z16 and
4753 * Z24 anymore. Do it manually here.
4754 *
4755 * It's unnecessary if the original texture format was
4756 * Z32_FLOAT, but we don't know that here.
4757 */
4758 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4759 z = ac_build_clamp(&ctx->ac, z);
4760
4761 address[count++] = z;
4762 }
4763
4764 /* pack derivatives */
4765 if (ddx || ddy) {
4766 int num_src_deriv_channels, num_dest_deriv_channels;
4767 switch (instr->sampler_dim) {
4768 case GLSL_SAMPLER_DIM_3D:
4769 case GLSL_SAMPLER_DIM_CUBE:
4770 num_deriv_comp = 3;
4771 num_src_deriv_channels = 3;
4772 num_dest_deriv_channels = 3;
4773 break;
4774 case GLSL_SAMPLER_DIM_2D:
4775 default:
4776 num_src_deriv_channels = 2;
4777 num_dest_deriv_channels = 2;
4778 num_deriv_comp = 2;
4779 break;
4780 case GLSL_SAMPLER_DIM_1D:
4781 num_src_deriv_channels = 1;
4782 if (ctx->ac.chip_class >= GFX9) {
4783 num_dest_deriv_channels = 2;
4784 num_deriv_comp = 2;
4785 } else {
4786 num_dest_deriv_channels = 1;
4787 num_deriv_comp = 1;
4788 }
4789 break;
4790 }
4791
4792 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4793 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4794 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4795 }
4796 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4797 derivs[i] = ctx->ac.f32_0;
4798 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4799 }
4800 }
4801
4802 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4803 for (chan = 0; chan < instr->coord_components; chan++)
4804 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4805 if (instr->coord_components == 3)
4806 coords[3] = LLVMGetUndef(ctx->ac.f32);
4807 ac_prepare_cube_coords(&ctx->ac,
4808 instr->op == nir_texop_txd, instr->is_array,
4809 instr->op == nir_texop_lod, coords, derivs);
4810 if (num_deriv_comp)
4811 num_deriv_comp--;
4812 }
4813
4814 if (ddx || ddy) {
4815 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4816 address[count++] = derivs[i];
4817 }
4818
4819 /* Pack texture coordinates */
4820 if (coord) {
4821 address[count++] = coords[0];
4822 if (instr->coord_components > 1) {
4823 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4824 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4825 }
4826 address[count++] = coords[1];
4827 }
4828 if (instr->coord_components > 2) {
4829 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4830 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4831 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4832 instr->op != nir_texop_txf) {
4833 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4834 }
4835 address[count++] = coords[2];
4836 }
4837
4838 if (ctx->ac.chip_class >= GFX9) {
4839 LLVMValueRef filler;
4840 if (instr->op == nir_texop_txf)
4841 filler = ctx->ac.i32_0;
4842 else
4843 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4844
4845 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4846 /* No nir_texop_lod, because it does not take a slice
4847 * even with array textures. */
4848 if (instr->is_array && instr->op != nir_texop_lod ) {
4849 address[count] = address[count - 1];
4850 address[count - 1] = filler;
4851 count++;
4852 } else
4853 address[count++] = filler;
4854 }
4855 }
4856 }
4857
4858 /* Pack LOD */
4859 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4860 instr->op == nir_texop_txf)) {
4861 address[count++] = lod;
4862 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4863 address[count++] = sample_index;
4864 } else if(instr->op == nir_texop_txs) {
4865 count = 0;
4866 if (lod)
4867 address[count++] = lod;
4868 else
4869 address[count++] = ctx->ac.i32_0;
4870 }
4871
4872 for (chan = 0; chan < count; chan++) {
4873 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4874 address[chan], ctx->ac.i32, "");
4875 }
4876
4877 if (instr->op == nir_texop_samples_identical) {
4878 LLVMValueRef txf_address[4];
4879 struct ac_image_args txf_args = { 0 };
4880 unsigned txf_count = count;
4881 memcpy(txf_address, address, sizeof(txf_address));
4882
4883 if (!instr->is_array)
4884 txf_address[2] = ctx->ac.i32_0;
4885 txf_address[3] = ctx->ac.i32_0;
4886
4887 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4888 fmask_ptr, NULL,
4889 txf_address, txf_count, 0xf);
4890
4891 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4892
4893 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4894 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4895 goto write_result;
4896 }
4897
4898 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4899 instr->op != nir_texop_txs) {
4900 unsigned sample_chan = instr->is_array ? 3 : 2;
4901 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4902 address[0],
4903 address[1],
4904 instr->is_array ? address[2] : NULL,
4905 address[sample_chan],
4906 fmask_ptr);
4907 }
4908
4909 if (offsets && instr->op == nir_texop_txf) {
4910 nir_const_value *const_offset =
4911 nir_src_as_const_value(instr->src[const_src].src);
4912 int num_offsets = instr->src[const_src].src.ssa->num_components;
4913 assert(const_offset);
4914 num_offsets = MIN2(num_offsets, instr->coord_components);
4915 if (num_offsets > 2)
4916 address[2] = LLVMBuildAdd(ctx->ac.builder,
4917 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4918 if (num_offsets > 1)
4919 address[1] = LLVMBuildAdd(ctx->ac.builder,
4920 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4921 address[0] = LLVMBuildAdd(ctx->ac.builder,
4922 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4923
4924 }
4925
4926 /* TODO TG4 support */
4927 if (instr->op == nir_texop_tg4) {
4928 if (instr->is_shadow)
4929 dmask = 1;
4930 else
4931 dmask = 1 << instr->component;
4932 }
4933 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4934 res_ptr, samp_ptr, address, count, dmask);
4935
4936 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4937
4938 if (instr->op == nir_texop_query_levels)
4939 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4940 else if (instr->is_shadow && instr->is_new_style_shadow &&
4941 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4942 instr->op != nir_texop_tg4)
4943 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4944 else if (instr->op == nir_texop_txs &&
4945 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4946 instr->is_array) {
4947 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4948 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4949 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4950 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4951 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4952 } else if (ctx->ac.chip_class >= GFX9 &&
4953 instr->op == nir_texop_txs &&
4954 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4955 instr->is_array) {
4956 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4957 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4958 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4959 ctx->ac.i32_1, "");
4960 } else if (instr->dest.ssa.num_components != 4)
4961 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4962
4963 write_result:
4964 if (result) {
4965 assert(instr->dest.is_ssa);
4966 result = ac_to_integer(&ctx->ac, result);
4967 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4968 }
4969 }
4970
4971
4972 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4973 {
4974 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4975 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4976
4977 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4978 _mesa_hash_table_insert(ctx->phis, instr, result);
4979 }
4980
4981 static void visit_post_phi(struct ac_nir_context *ctx,
4982 nir_phi_instr *instr,
4983 LLVMValueRef llvm_phi)
4984 {
4985 nir_foreach_phi_src(src, instr) {
4986 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4987 LLVMValueRef llvm_src = get_src(ctx, src->src);
4988
4989 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4990 }
4991 }
4992
4993 static void phi_post_pass(struct ac_nir_context *ctx)
4994 {
4995 struct hash_entry *entry;
4996 hash_table_foreach(ctx->phis, entry) {
4997 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4998 (LLVMValueRef)entry->data);
4999 }
5000 }
5001
5002
5003 static void visit_ssa_undef(struct ac_nir_context *ctx,
5004 const nir_ssa_undef_instr *instr)
5005 {
5006 unsigned num_components = instr->def.num_components;
5007 LLVMValueRef undef;
5008
5009 if (num_components == 1)
5010 undef = LLVMGetUndef(ctx->ac.i32);
5011 else {
5012 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5013 }
5014 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5015 }
5016
5017 static void visit_jump(struct ac_nir_context *ctx,
5018 const nir_jump_instr *instr)
5019 {
5020 switch (instr->type) {
5021 case nir_jump_break:
5022 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5023 LLVMClearInsertionPosition(ctx->ac.builder);
5024 break;
5025 case nir_jump_continue:
5026 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5027 LLVMClearInsertionPosition(ctx->ac.builder);
5028 break;
5029 default:
5030 fprintf(stderr, "Unknown NIR jump instr: ");
5031 nir_print_instr(&instr->instr, stderr);
5032 fprintf(stderr, "\n");
5033 abort();
5034 }
5035 }
5036
5037 static void visit_cf_list(struct ac_nir_context *ctx,
5038 struct exec_list *list);
5039
5040 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5041 {
5042 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5043 nir_foreach_instr(instr, block)
5044 {
5045 switch (instr->type) {
5046 case nir_instr_type_alu:
5047 visit_alu(ctx, nir_instr_as_alu(instr));
5048 break;
5049 case nir_instr_type_load_const:
5050 visit_load_const(ctx, nir_instr_as_load_const(instr));
5051 break;
5052 case nir_instr_type_intrinsic:
5053 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5054 break;
5055 case nir_instr_type_tex:
5056 visit_tex(ctx, nir_instr_as_tex(instr));
5057 break;
5058 case nir_instr_type_phi:
5059 visit_phi(ctx, nir_instr_as_phi(instr));
5060 break;
5061 case nir_instr_type_ssa_undef:
5062 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5063 break;
5064 case nir_instr_type_jump:
5065 visit_jump(ctx, nir_instr_as_jump(instr));
5066 break;
5067 default:
5068 fprintf(stderr, "Unknown NIR instr type: ");
5069 nir_print_instr(instr, stderr);
5070 fprintf(stderr, "\n");
5071 abort();
5072 }
5073 }
5074
5075 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5076 }
5077
5078 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5079 {
5080 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5081
5082 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5083 LLVMBasicBlockRef merge_block =
5084 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5085 LLVMBasicBlockRef if_block =
5086 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5087 LLVMBasicBlockRef else_block = merge_block;
5088 if (!exec_list_is_empty(&if_stmt->else_list))
5089 else_block = LLVMAppendBasicBlockInContext(
5090 ctx->ac.context, fn, "");
5091
5092 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5093 ctx->ac.i32_0, "");
5094 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5095
5096 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5097 visit_cf_list(ctx, &if_stmt->then_list);
5098 if (LLVMGetInsertBlock(ctx->ac.builder))
5099 LLVMBuildBr(ctx->ac.builder, merge_block);
5100
5101 if (!exec_list_is_empty(&if_stmt->else_list)) {
5102 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5103 visit_cf_list(ctx, &if_stmt->else_list);
5104 if (LLVMGetInsertBlock(ctx->ac.builder))
5105 LLVMBuildBr(ctx->ac.builder, merge_block);
5106 }
5107
5108 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5109 }
5110
5111 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5112 {
5113 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5114 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5115 LLVMBasicBlockRef break_parent = ctx->break_block;
5116
5117 ctx->continue_block =
5118 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5119 ctx->break_block =
5120 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5121
5122 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5123 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5124 visit_cf_list(ctx, &loop->body);
5125
5126 if (LLVMGetInsertBlock(ctx->ac.builder))
5127 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5128 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5129
5130 ctx->continue_block = continue_parent;
5131 ctx->break_block = break_parent;
5132 }
5133
5134 static void visit_cf_list(struct ac_nir_context *ctx,
5135 struct exec_list *list)
5136 {
5137 foreach_list_typed(nir_cf_node, node, node, list)
5138 {
5139 switch (node->type) {
5140 case nir_cf_node_block:
5141 visit_block(ctx, nir_cf_node_as_block(node));
5142 break;
5143
5144 case nir_cf_node_if:
5145 visit_if(ctx, nir_cf_node_as_if(node));
5146 break;
5147
5148 case nir_cf_node_loop:
5149 visit_loop(ctx, nir_cf_node_as_loop(node));
5150 break;
5151
5152 default:
5153 assert(0);
5154 }
5155 }
5156 }
5157
5158 static void
5159 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5160 struct nir_variable *variable)
5161 {
5162 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5163 LLVMValueRef t_offset;
5164 LLVMValueRef t_list;
5165 LLVMValueRef input;
5166 LLVMValueRef buffer_index;
5167 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5168 int idx = variable->data.location;
5169 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5170
5171 variable->data.driver_location = idx * 4;
5172
5173 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5174 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5175 ctx->abi.start_instance, "");
5176 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5177 ctx->shader_info->vs.vgpr_comp_cnt);
5178 } else
5179 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5180 ctx->abi.base_vertex, "");
5181
5182 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5183 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5184
5185 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5186
5187 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5188 buffer_index,
5189 ctx->ac.i32_0,
5190 true);
5191
5192 for (unsigned chan = 0; chan < 4; chan++) {
5193 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5194 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5195 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5196 input, llvm_chan, ""));
5197 }
5198 }
5199 }
5200
5201 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5202 unsigned attr,
5203 LLVMValueRef interp_param,
5204 LLVMValueRef prim_mask,
5205 LLVMValueRef result[4])
5206 {
5207 LLVMValueRef attr_number;
5208 unsigned chan;
5209 LLVMValueRef i, j;
5210 bool interp = interp_param != NULL;
5211
5212 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5213
5214 /* fs.constant returns the param from the middle vertex, so it's not
5215 * really useful for flat shading. It's meant to be used for custom
5216 * interpolation (but the intrinsic can't fetch from the other two
5217 * vertices).
5218 *
5219 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5220 * to do the right thing. The only reason we use fs.constant is that
5221 * fs.interp cannot be used on integers, because they can be equal
5222 * to NaN.
5223 */
5224 if (interp) {
5225 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5226 ctx->ac.v2f32, "");
5227
5228 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5229 ctx->ac.i32_0, "");
5230 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5231 ctx->ac.i32_1, "");
5232 }
5233
5234 for (chan = 0; chan < 4; chan++) {
5235 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5236
5237 if (interp) {
5238 result[chan] = ac_build_fs_interp(&ctx->ac,
5239 llvm_chan,
5240 attr_number,
5241 prim_mask, i, j);
5242 } else {
5243 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5244 LLVMConstInt(ctx->ac.i32, 2, false),
5245 llvm_chan,
5246 attr_number,
5247 prim_mask);
5248 }
5249 }
5250 }
5251
5252 static void
5253 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5254 struct nir_variable *variable)
5255 {
5256 int idx = variable->data.location;
5257 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5258 LLVMValueRef interp;
5259
5260 variable->data.driver_location = idx * 4;
5261 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5262
5263 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5264 unsigned interp_type;
5265 if (variable->data.sample) {
5266 interp_type = INTERP_SAMPLE;
5267 ctx->shader_info->info.ps.force_persample = true;
5268 } else if (variable->data.centroid)
5269 interp_type = INTERP_CENTROID;
5270 else
5271 interp_type = INTERP_CENTER;
5272
5273 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5274 } else
5275 interp = NULL;
5276
5277 for (unsigned i = 0; i < attrib_count; ++i)
5278 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5279
5280 }
5281
5282 static void
5283 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5284 struct nir_shader *nir) {
5285 nir_foreach_variable(variable, &nir->inputs)
5286 handle_vs_input_decl(ctx, variable);
5287 }
5288
5289 static void
5290 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5291 struct nir_shader *nir)
5292 {
5293 if (!ctx->options->key.fs.multisample)
5294 return;
5295
5296 bool uses_center = false;
5297 bool uses_centroid = false;
5298 nir_foreach_variable(variable, &nir->inputs) {
5299 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5300 variable->data.sample)
5301 continue;
5302
5303 if (variable->data.centroid)
5304 uses_centroid = true;
5305 else
5306 uses_center = true;
5307 }
5308
5309 if (uses_center && uses_centroid) {
5310 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5311 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5312 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5313 }
5314 }
5315
5316 static void
5317 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5318 struct nir_shader *nir)
5319 {
5320 prepare_interp_optimize(ctx, nir);
5321
5322 nir_foreach_variable(variable, &nir->inputs)
5323 handle_fs_input_decl(ctx, variable);
5324
5325 unsigned index = 0;
5326
5327 if (ctx->shader_info->info.ps.uses_input_attachments ||
5328 ctx->shader_info->info.needs_multiview_view_index)
5329 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5330
5331 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5332 LLVMValueRef interp_param;
5333 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5334
5335 if (!(ctx->input_mask & (1ull << i)))
5336 continue;
5337
5338 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5339 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5340 interp_param = *inputs;
5341 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5342 inputs);
5343
5344 if (!interp_param)
5345 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5346 ++index;
5347 } else if (i == VARYING_SLOT_POS) {
5348 for(int i = 0; i < 3; ++i)
5349 inputs[i] = ctx->abi.frag_pos[i];
5350
5351 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5352 ctx->abi.frag_pos[3]);
5353 }
5354 }
5355 ctx->shader_info->fs.num_interp = index;
5356 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5357 ctx->shader_info->fs.has_pcoord = true;
5358 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5359 ctx->shader_info->fs.prim_id_input = true;
5360 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5361 ctx->shader_info->fs.layer_input = true;
5362 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5363
5364 if (ctx->shader_info->info.needs_multiview_view_index)
5365 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5366 }
5367
5368 static LLVMValueRef
5369 ac_build_alloca(struct ac_llvm_context *ac,
5370 LLVMTypeRef type,
5371 const char *name)
5372 {
5373 LLVMBuilderRef builder = ac->builder;
5374 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5375 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5376 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5377 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5378 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5379 LLVMValueRef res;
5380
5381 if (first_instr) {
5382 LLVMPositionBuilderBefore(first_builder, first_instr);
5383 } else {
5384 LLVMPositionBuilderAtEnd(first_builder, first_block);
5385 }
5386
5387 res = LLVMBuildAlloca(first_builder, type, name);
5388 LLVMBuildStore(builder, LLVMConstNull(type), res);
5389
5390 LLVMDisposeBuilder(first_builder);
5391
5392 return res;
5393 }
5394
5395 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5396 LLVMTypeRef type,
5397 const char *name)
5398 {
5399 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5400 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5401 return ptr;
5402 }
5403
5404 static void
5405 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5406 struct nir_variable *variable,
5407 struct nir_shader *shader,
5408 gl_shader_stage stage)
5409 {
5410 int idx = variable->data.location + variable->data.index;
5411 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5412 uint64_t mask_attribs;
5413
5414 variable->data.driver_location = idx * 4;
5415
5416 /* tess ctrl has it's own load/store paths for outputs */
5417 if (stage == MESA_SHADER_TESS_CTRL)
5418 return;
5419
5420 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5421 if (stage == MESA_SHADER_VERTEX ||
5422 stage == MESA_SHADER_TESS_EVAL ||
5423 stage == MESA_SHADER_GEOMETRY) {
5424 if (idx == VARYING_SLOT_CLIP_DIST0) {
5425 int length = shader->info.clip_distance_array_size +
5426 shader->info.cull_distance_array_size;
5427 if (stage == MESA_SHADER_VERTEX) {
5428 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5429 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5430 }
5431 if (stage == MESA_SHADER_TESS_EVAL) {
5432 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5433 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5434 }
5435
5436 if (length > 4)
5437 attrib_count = 2;
5438 else
5439 attrib_count = 1;
5440 mask_attribs = 1ull << idx;
5441 }
5442 }
5443
5444 ctx->output_mask |= mask_attribs;
5445 }
5446
5447 static void
5448 handle_shader_output_decl(struct ac_nir_context *ctx,
5449 struct nir_shader *nir,
5450 struct nir_variable *variable)
5451 {
5452 unsigned output_loc = variable->data.driver_location / 4;
5453 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5454
5455 /* tess ctrl has it's own load/store paths for outputs */
5456 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5457 return;
5458
5459 if (ctx->stage == MESA_SHADER_VERTEX ||
5460 ctx->stage == MESA_SHADER_TESS_EVAL ||
5461 ctx->stage == MESA_SHADER_GEOMETRY) {
5462 int idx = variable->data.location + variable->data.index;
5463 if (idx == VARYING_SLOT_CLIP_DIST0) {
5464 int length = nir->info.clip_distance_array_size +
5465 nir->info.cull_distance_array_size;
5466
5467 if (length > 4)
5468 attrib_count = 2;
5469 else
5470 attrib_count = 1;
5471 }
5472 }
5473
5474 for (unsigned i = 0; i < attrib_count; ++i) {
5475 for (unsigned chan = 0; chan < 4; chan++) {
5476 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5477 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5478 }
5479 }
5480 }
5481
5482 static LLVMTypeRef
5483 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5484 enum glsl_base_type type)
5485 {
5486 switch (type) {
5487 case GLSL_TYPE_INT:
5488 case GLSL_TYPE_UINT:
5489 case GLSL_TYPE_BOOL:
5490 case GLSL_TYPE_SUBROUTINE:
5491 return ctx->ac.i32;
5492 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5493 return ctx->ac.f32;
5494 case GLSL_TYPE_INT64:
5495 case GLSL_TYPE_UINT64:
5496 return ctx->ac.i64;
5497 case GLSL_TYPE_DOUBLE:
5498 return ctx->ac.f64;
5499 default:
5500 unreachable("unknown GLSL type");
5501 }
5502 }
5503
5504 static LLVMTypeRef
5505 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5506 const struct glsl_type *type)
5507 {
5508 if (glsl_type_is_scalar(type)) {
5509 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5510 }
5511
5512 if (glsl_type_is_vector(type)) {
5513 return LLVMVectorType(
5514 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5515 glsl_get_vector_elements(type));
5516 }
5517
5518 if (glsl_type_is_matrix(type)) {
5519 return LLVMArrayType(
5520 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5521 glsl_get_matrix_columns(type));
5522 }
5523
5524 if (glsl_type_is_array(type)) {
5525 return LLVMArrayType(
5526 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5527 glsl_get_length(type));
5528 }
5529
5530 assert(glsl_type_is_struct(type));
5531
5532 LLVMTypeRef member_types[glsl_get_length(type)];
5533
5534 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5535 member_types[i] =
5536 glsl_to_llvm_type(ctx,
5537 glsl_get_struct_field(type, i));
5538 }
5539
5540 return LLVMStructTypeInContext(ctx->context, member_types,
5541 glsl_get_length(type), false);
5542 }
5543
5544 static void
5545 setup_locals(struct ac_nir_context *ctx,
5546 struct nir_function *func)
5547 {
5548 int i, j;
5549 ctx->num_locals = 0;
5550 nir_foreach_variable(variable, &func->impl->locals) {
5551 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5552 variable->data.driver_location = ctx->num_locals * 4;
5553 ctx->num_locals += attrib_count;
5554 }
5555 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5556 if (!ctx->locals)
5557 return;
5558
5559 for (i = 0; i < ctx->num_locals; i++) {
5560 for (j = 0; j < 4; j++) {
5561 ctx->locals[i * 4 + j] =
5562 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5563 }
5564 }
5565 }
5566
5567 static void
5568 setup_shared(struct ac_nir_context *ctx,
5569 struct nir_shader *nir)
5570 {
5571 nir_foreach_variable(variable, &nir->shared) {
5572 LLVMValueRef shared =
5573 LLVMAddGlobalInAddressSpace(
5574 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5575 variable->name ? variable->name : "",
5576 LOCAL_ADDR_SPACE);
5577 _mesa_hash_table_insert(ctx->vars, variable, shared);
5578 }
5579 }
5580
5581 static LLVMValueRef
5582 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5583 {
5584 v = ac_to_float(ctx, v);
5585 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5586 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5587 }
5588
5589
5590 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5591 LLVMValueRef src0, LLVMValueRef src1)
5592 {
5593 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5594 LLVMValueRef comp[2];
5595
5596 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5597 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5598 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5599 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5600 }
5601
5602 /* Initialize arguments for the shader export intrinsic */
5603 static void
5604 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5605 LLVMValueRef *values,
5606 unsigned target,
5607 struct ac_export_args *args)
5608 {
5609 /* Default is 0xf. Adjusted below depending on the format. */
5610 args->enabled_channels = 0xf;
5611
5612 /* Specify whether the EXEC mask represents the valid mask */
5613 args->valid_mask = 0;
5614
5615 /* Specify whether this is the last export */
5616 args->done = 0;
5617
5618 /* Specify the target we are exporting */
5619 args->target = target;
5620
5621 args->compr = false;
5622 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5623 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5624 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5625 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5626
5627 if (!values)
5628 return;
5629
5630 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5631 LLVMValueRef val[4];
5632 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5633 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5634 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5635 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5636
5637 switch(col_format) {
5638 case V_028714_SPI_SHADER_ZERO:
5639 args->enabled_channels = 0; /* writemask */
5640 args->target = V_008DFC_SQ_EXP_NULL;
5641 break;
5642
5643 case V_028714_SPI_SHADER_32_R:
5644 args->enabled_channels = 1;
5645 args->out[0] = values[0];
5646 break;
5647
5648 case V_028714_SPI_SHADER_32_GR:
5649 args->enabled_channels = 0x3;
5650 args->out[0] = values[0];
5651 args->out[1] = values[1];
5652 break;
5653
5654 case V_028714_SPI_SHADER_32_AR:
5655 args->enabled_channels = 0x9;
5656 args->out[0] = values[0];
5657 args->out[3] = values[3];
5658 break;
5659
5660 case V_028714_SPI_SHADER_FP16_ABGR:
5661 args->compr = 1;
5662
5663 for (unsigned chan = 0; chan < 2; chan++) {
5664 LLVMValueRef pack_args[2] = {
5665 values[2 * chan],
5666 values[2 * chan + 1]
5667 };
5668 LLVMValueRef packed;
5669
5670 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5671 args->out[chan] = packed;
5672 }
5673 break;
5674
5675 case V_028714_SPI_SHADER_UNORM16_ABGR:
5676 for (unsigned chan = 0; chan < 4; chan++) {
5677 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5678 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5679 LLVMConstReal(ctx->ac.f32, 65535), "");
5680 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5681 LLVMConstReal(ctx->ac.f32, 0.5), "");
5682 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5683 ctx->ac.i32, "");
5684 }
5685
5686 args->compr = 1;
5687 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5688 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5689 break;
5690
5691 case V_028714_SPI_SHADER_SNORM16_ABGR:
5692 for (unsigned chan = 0; chan < 4; chan++) {
5693 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5694 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5695 LLVMConstReal(ctx->ac.f32, 32767), "");
5696
5697 /* If positive, add 0.5, else add -0.5. */
5698 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5699 LLVMBuildSelect(ctx->builder,
5700 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5701 val[chan], ctx->ac.f32_0, ""),
5702 LLVMConstReal(ctx->ac.f32, 0.5),
5703 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5704 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5705 }
5706
5707 args->compr = 1;
5708 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5709 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5710 break;
5711
5712 case V_028714_SPI_SHADER_UINT16_ABGR: {
5713 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5714 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5715 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5716
5717 for (unsigned chan = 0; chan < 4; chan++) {
5718 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5719 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5720 }
5721
5722 args->compr = 1;
5723 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5724 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5725 break;
5726 }
5727
5728 case V_028714_SPI_SHADER_SINT16_ABGR: {
5729 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5730 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5731 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5732 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5733 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5734 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5735
5736 /* Clamp. */
5737 for (unsigned chan = 0; chan < 4; chan++) {
5738 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5739 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5740 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5741 }
5742
5743 args->compr = 1;
5744 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5745 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5746 break;
5747 }
5748
5749 default:
5750 case V_028714_SPI_SHADER_32_ABGR:
5751 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5752 break;
5753 }
5754 } else
5755 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5756
5757 for (unsigned i = 0; i < 4; ++i)
5758 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5759 }
5760
5761 static void
5762 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5763 bool export_prim_id,
5764 struct ac_vs_output_info *outinfo)
5765 {
5766 uint32_t param_count = 0;
5767 unsigned target;
5768 unsigned pos_idx, num_pos_exports = 0;
5769 struct ac_export_args args, pos_args[4] = {};
5770 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5771 int i;
5772
5773 if (ctx->options->key.has_multiview_view_index) {
5774 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5775 if(!*tmp_out) {
5776 for(unsigned i = 0; i < 4; ++i)
5777 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5778 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5779 }
5780
5781 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5782 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5783 }
5784
5785 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5786 sizeof(outinfo->vs_output_param_offset));
5787
5788 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5789 LLVMValueRef slots[8];
5790 unsigned j;
5791
5792 if (outinfo->cull_dist_mask)
5793 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5794
5795 i = VARYING_SLOT_CLIP_DIST0;
5796 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5797 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5798 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5799
5800 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5801 slots[i] = LLVMGetUndef(ctx->ac.f32);
5802
5803 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5804 target = V_008DFC_SQ_EXP_POS + 3;
5805 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5806 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5807 &args, sizeof(args));
5808 }
5809
5810 target = V_008DFC_SQ_EXP_POS + 2;
5811 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5812 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5813 &args, sizeof(args));
5814
5815 }
5816
5817 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5818 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5819 for (unsigned j = 0; j < 4; j++)
5820 pos_values[j] = LLVMBuildLoad(ctx->builder,
5821 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5822 }
5823 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5824
5825 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5826 outinfo->writes_pointsize = true;
5827 psize_value = LLVMBuildLoad(ctx->builder,
5828 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5829 }
5830
5831 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5832 outinfo->writes_layer = true;
5833 layer_value = LLVMBuildLoad(ctx->builder,
5834 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5835 }
5836
5837 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5838 outinfo->writes_viewport_index = true;
5839 viewport_index_value = LLVMBuildLoad(ctx->builder,
5840 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5841 }
5842
5843 if (outinfo->writes_pointsize ||
5844 outinfo->writes_layer ||
5845 outinfo->writes_viewport_index) {
5846 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5847 (outinfo->writes_layer == true ? 4 : 0));
5848 pos_args[1].valid_mask = 0;
5849 pos_args[1].done = 0;
5850 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5851 pos_args[1].compr = 0;
5852 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5853 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5854 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5855 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5856
5857 if (outinfo->writes_pointsize == true)
5858 pos_args[1].out[0] = psize_value;
5859 if (outinfo->writes_layer == true)
5860 pos_args[1].out[2] = layer_value;
5861 if (outinfo->writes_viewport_index == true) {
5862 if (ctx->options->chip_class >= GFX9) {
5863 /* GFX9 has the layer in out.z[10:0] and the viewport
5864 * index in out.z[19:16].
5865 */
5866 LLVMValueRef v = viewport_index_value;
5867 v = ac_to_integer(&ctx->ac, v);
5868 v = LLVMBuildShl(ctx->builder, v,
5869 LLVMConstInt(ctx->ac.i32, 16, false),
5870 "");
5871 v = LLVMBuildOr(ctx->builder, v,
5872 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5873
5874 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5875 pos_args[1].enabled_channels |= 1 << 2;
5876 } else {
5877 pos_args[1].out[3] = viewport_index_value;
5878 pos_args[1].enabled_channels |= 1 << 3;
5879 }
5880 }
5881 }
5882 for (i = 0; i < 4; i++) {
5883 if (pos_args[i].out[0])
5884 num_pos_exports++;
5885 }
5886
5887 pos_idx = 0;
5888 for (i = 0; i < 4; i++) {
5889 if (!pos_args[i].out[0])
5890 continue;
5891
5892 /* Specify the target we are exporting */
5893 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5894 if (pos_idx == num_pos_exports)
5895 pos_args[i].done = 1;
5896 ac_build_export(&ctx->ac, &pos_args[i]);
5897 }
5898
5899 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5900 LLVMValueRef values[4];
5901 if (!(ctx->output_mask & (1ull << i)))
5902 continue;
5903
5904 for (unsigned j = 0; j < 4; j++)
5905 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5906 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5907
5908 if (i == VARYING_SLOT_LAYER) {
5909 target = V_008DFC_SQ_EXP_PARAM + param_count;
5910 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5911 param_count++;
5912 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5913 target = V_008DFC_SQ_EXP_PARAM + param_count;
5914 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5915 param_count++;
5916 } else if (i >= VARYING_SLOT_VAR0) {
5917 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5918 target = V_008DFC_SQ_EXP_PARAM + param_count;
5919 outinfo->vs_output_param_offset[i] = param_count;
5920 param_count++;
5921 } else
5922 continue;
5923
5924 si_llvm_init_export_args(ctx, values, target, &args);
5925
5926 if (target >= V_008DFC_SQ_EXP_POS &&
5927 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5928 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5929 &args, sizeof(args));
5930 } else {
5931 ac_build_export(&ctx->ac, &args);
5932 }
5933 }
5934
5935 if (export_prim_id) {
5936 LLVMValueRef values[4];
5937 target = V_008DFC_SQ_EXP_PARAM + param_count;
5938 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5939 param_count++;
5940
5941 values[0] = ctx->vs_prim_id;
5942 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5943 ctx->shader_info->vs.vgpr_comp_cnt);
5944 for (unsigned j = 1; j < 4; j++)
5945 values[j] = ctx->ac.f32_0;
5946 si_llvm_init_export_args(ctx, values, target, &args);
5947 ac_build_export(&ctx->ac, &args);
5948 outinfo->export_prim_id = true;
5949 }
5950
5951 outinfo->pos_exports = num_pos_exports;
5952 outinfo->param_exports = param_count;
5953 }
5954
5955 static void
5956 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5957 struct ac_es_output_info *outinfo)
5958 {
5959 int j;
5960 uint64_t max_output_written = 0;
5961 LLVMValueRef lds_base = NULL;
5962
5963 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5964 int param_index;
5965 int length = 4;
5966
5967 if (!(ctx->output_mask & (1ull << i)))
5968 continue;
5969
5970 if (i == VARYING_SLOT_CLIP_DIST0)
5971 length = ctx->num_output_clips + ctx->num_output_culls;
5972
5973 param_index = shader_io_get_unique_index(i);
5974
5975 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5976 }
5977
5978 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5979
5980 if (ctx->ac.chip_class >= GFX9) {
5981 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5982 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5983 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5984 LLVMConstInt(ctx->ac.i32, 24, false),
5985 LLVMConstInt(ctx->ac.i32, 4, false), false);
5986 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5987 LLVMBuildMul(ctx->ac.builder, wave_idx,
5988 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5989 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5990 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5991 }
5992
5993 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5994 LLVMValueRef dw_addr;
5995 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5996 int param_index;
5997 int length = 4;
5998
5999 if (!(ctx->output_mask & (1ull << i)))
6000 continue;
6001
6002 if (i == VARYING_SLOT_CLIP_DIST0)
6003 length = ctx->num_output_clips + ctx->num_output_culls;
6004
6005 param_index = shader_io_get_unique_index(i);
6006
6007 if (lds_base) {
6008 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6009 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6010 "");
6011 }
6012 for (j = 0; j < length; j++) {
6013 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6014 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6015
6016 if (ctx->ac.chip_class >= GFX9) {
6017 ac_lds_store(&ctx->ac, dw_addr,
6018 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6019 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6020 } else {
6021 ac_build_buffer_store_dword(&ctx->ac,
6022 ctx->esgs_ring,
6023 out_val, 1,
6024 NULL, ctx->es2gs_offset,
6025 (4 * param_index + j) * 4,
6026 1, 1, true, true);
6027 }
6028 }
6029 }
6030 }
6031
6032 static void
6033 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6034 {
6035 LLVMValueRef vertex_id = ctx->rel_auto_id;
6036 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6037 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6038 vertex_dw_stride, "");
6039
6040 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6041 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6042 int length = 4;
6043
6044 if (!(ctx->output_mask & (1ull << i)))
6045 continue;
6046
6047 if (i == VARYING_SLOT_CLIP_DIST0)
6048 length = ctx->num_output_clips + ctx->num_output_culls;
6049 int param = shader_io_get_unique_index(i);
6050 mark_tess_output(ctx, false, param);
6051 if (length > 4)
6052 mark_tess_output(ctx, false, param + 1);
6053 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6054 LLVMConstInt(ctx->ac.i32, param * 4, false),
6055 "");
6056 for (unsigned j = 0; j < length; j++) {
6057 ac_lds_store(&ctx->ac, dw_addr,
6058 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6059 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6060 }
6061 }
6062 }
6063
6064 struct ac_build_if_state
6065 {
6066 struct nir_to_llvm_context *ctx;
6067 LLVMValueRef condition;
6068 LLVMBasicBlockRef entry_block;
6069 LLVMBasicBlockRef true_block;
6070 LLVMBasicBlockRef false_block;
6071 LLVMBasicBlockRef merge_block;
6072 };
6073
6074 static LLVMBasicBlockRef
6075 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6076 {
6077 LLVMBasicBlockRef current_block;
6078 LLVMBasicBlockRef next_block;
6079 LLVMBasicBlockRef new_block;
6080
6081 /* get current basic block */
6082 current_block = LLVMGetInsertBlock(ctx->builder);
6083
6084 /* chqeck if there's another block after this one */
6085 next_block = LLVMGetNextBasicBlock(current_block);
6086 if (next_block) {
6087 /* insert the new block before the next block */
6088 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6089 }
6090 else {
6091 /* append new block after current block */
6092 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6093 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6094 }
6095 return new_block;
6096 }
6097
6098 static void
6099 ac_nir_build_if(struct ac_build_if_state *ifthen,
6100 struct nir_to_llvm_context *ctx,
6101 LLVMValueRef condition)
6102 {
6103 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6104
6105 memset(ifthen, 0, sizeof *ifthen);
6106 ifthen->ctx = ctx;
6107 ifthen->condition = condition;
6108 ifthen->entry_block = block;
6109
6110 /* create endif/merge basic block for the phi functions */
6111 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6112
6113 /* create/insert true_block before merge_block */
6114 ifthen->true_block =
6115 LLVMInsertBasicBlockInContext(ctx->context,
6116 ifthen->merge_block,
6117 "if-true-block");
6118
6119 /* successive code goes into the true block */
6120 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6121 }
6122
6123 /**
6124 * End a conditional.
6125 */
6126 static void
6127 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6128 {
6129 LLVMBuilderRef builder = ifthen->ctx->builder;
6130
6131 /* Insert branch to the merge block from current block */
6132 LLVMBuildBr(builder, ifthen->merge_block);
6133
6134 /*
6135 * Now patch in the various branch instructions.
6136 */
6137
6138 /* Insert the conditional branch instruction at the end of entry_block */
6139 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6140 if (ifthen->false_block) {
6141 /* we have an else clause */
6142 LLVMBuildCondBr(builder, ifthen->condition,
6143 ifthen->true_block, ifthen->false_block);
6144 }
6145 else {
6146 /* no else clause */
6147 LLVMBuildCondBr(builder, ifthen->condition,
6148 ifthen->true_block, ifthen->merge_block);
6149 }
6150
6151 /* Resume building code at end of the ifthen->merge_block */
6152 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6153 }
6154
6155 static void
6156 write_tess_factors(struct nir_to_llvm_context *ctx)
6157 {
6158 unsigned stride, outer_comps, inner_comps;
6159 struct ac_build_if_state if_ctx, inner_if_ctx;
6160 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6161 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6162 unsigned tess_inner_index, tess_outer_index;
6163 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6164 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6165 int i;
6166 emit_barrier(ctx);
6167
6168 switch (ctx->options->key.tcs.primitive_mode) {
6169 case GL_ISOLINES:
6170 stride = 2;
6171 outer_comps = 2;
6172 inner_comps = 0;
6173 break;
6174 case GL_TRIANGLES:
6175 stride = 4;
6176 outer_comps = 3;
6177 inner_comps = 1;
6178 break;
6179 case GL_QUADS:
6180 stride = 6;
6181 outer_comps = 4;
6182 inner_comps = 2;
6183 break;
6184 default:
6185 return;
6186 }
6187
6188 ac_nir_build_if(&if_ctx, ctx,
6189 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6190 invocation_id, ctx->ac.i32_0, ""));
6191
6192 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6193 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6194
6195 mark_tess_output(ctx, true, tess_inner_index);
6196 mark_tess_output(ctx, true, tess_outer_index);
6197 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6198 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6199 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6200 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6201 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6202
6203 for (i = 0; i < 4; i++) {
6204 inner[i] = LLVMGetUndef(ctx->ac.i32);
6205 outer[i] = LLVMGetUndef(ctx->ac.i32);
6206 }
6207
6208 // LINES reverseal
6209 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6210 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6211 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6212 ctx->ac.i32_1, "");
6213 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6214 } else {
6215 for (i = 0; i < outer_comps; i++) {
6216 outer[i] = out[i] =
6217 ac_lds_load(&ctx->ac, lds_outer);
6218 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6219 ctx->ac.i32_1, "");
6220 }
6221 for (i = 0; i < inner_comps; i++) {
6222 inner[i] = out[outer_comps+i] =
6223 ac_lds_load(&ctx->ac, lds_inner);
6224 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6225 ctx->ac.i32_1, "");
6226 }
6227 }
6228
6229 /* Convert the outputs to vectors for stores. */
6230 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6231 vec1 = NULL;
6232
6233 if (stride > 4)
6234 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6235
6236
6237 buffer = ctx->hs_ring_tess_factor;
6238 tf_base = ctx->tess_factor_offset;
6239 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6240 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6241 unsigned tf_offset = 0;
6242
6243 if (ctx->options->chip_class <= VI) {
6244 ac_nir_build_if(&inner_if_ctx, ctx,
6245 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6246 rel_patch_id, ctx->ac.i32_0, ""));
6247
6248 /* Store the dynamic HS control word. */
6249 ac_build_buffer_store_dword(&ctx->ac, buffer,
6250 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6251 1, ctx->ac.i32_0, tf_base,
6252 0, 1, 0, true, false);
6253 tf_offset += 4;
6254
6255 ac_nir_build_endif(&inner_if_ctx);
6256 }
6257
6258 /* Store the tessellation factors. */
6259 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6260 MIN2(stride, 4), byteoffset, tf_base,
6261 tf_offset, 1, 0, true, false);
6262 if (vec1)
6263 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6264 stride - 4, byteoffset, tf_base,
6265 16 + tf_offset, 1, 0, true, false);
6266
6267 //store to offchip for TES to read - only if TES reads them
6268 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6269 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6270 LLVMValueRef tf_inner_offset;
6271 unsigned param_outer, param_inner;
6272
6273 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6274 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6275 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6276
6277 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6278 util_next_power_of_two(outer_comps));
6279
6280 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6281 outer_comps, tf_outer_offset,
6282 ctx->oc_lds, 0, 1, 0, true, false);
6283 if (inner_comps) {
6284 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6285 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6286 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6287
6288 inner_vec = inner_comps == 1 ? inner[0] :
6289 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6290 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6291 inner_comps, tf_inner_offset,
6292 ctx->oc_lds, 0, 1, 0, true, false);
6293 }
6294 }
6295 ac_nir_build_endif(&if_ctx);
6296 }
6297
6298 static void
6299 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6300 {
6301 write_tess_factors(ctx);
6302 }
6303
6304 static bool
6305 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6306 LLVMValueRef *color, unsigned param, bool is_last,
6307 struct ac_export_args *args)
6308 {
6309 /* Export */
6310 si_llvm_init_export_args(ctx, color, param,
6311 args);
6312
6313 if (is_last) {
6314 args->valid_mask = 1; /* whether the EXEC mask is valid */
6315 args->done = 1; /* DONE bit */
6316 } else if (!args->enabled_channels)
6317 return false; /* unnecessary NULL export */
6318
6319 return true;
6320 }
6321
6322 static void
6323 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6324 LLVMValueRef depth, LLVMValueRef stencil,
6325 LLVMValueRef samplemask)
6326 {
6327 struct ac_export_args args;
6328
6329 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6330
6331 ac_build_export(&ctx->ac, &args);
6332 }
6333
6334 static void
6335 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6336 {
6337 unsigned index = 0;
6338 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6339 struct ac_export_args color_args[8];
6340
6341 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6342 LLVMValueRef values[4];
6343
6344 if (!(ctx->output_mask & (1ull << i)))
6345 continue;
6346
6347 if (i == FRAG_RESULT_DEPTH) {
6348 ctx->shader_info->fs.writes_z = true;
6349 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6350 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6351 } else if (i == FRAG_RESULT_STENCIL) {
6352 ctx->shader_info->fs.writes_stencil = true;
6353 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6354 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6355 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6356 ctx->shader_info->fs.writes_sample_mask = true;
6357 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6358 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6359 } else {
6360 bool last = false;
6361 for (unsigned j = 0; j < 4; j++)
6362 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6363 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6364
6365 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6366 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6367
6368 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6369 if (ret)
6370 index++;
6371 }
6372 }
6373
6374 for (unsigned i = 0; i < index; i++)
6375 ac_build_export(&ctx->ac, &color_args[i]);
6376 if (depth || stencil || samplemask)
6377 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6378 else if (!index) {
6379 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6380 ac_build_export(&ctx->ac, &color_args[0]);
6381 }
6382
6383 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6384 }
6385
6386 static void
6387 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6388 {
6389 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6390 }
6391
6392 static void
6393 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6394 LLVMValueRef *addrs)
6395 {
6396 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6397
6398 switch (ctx->stage) {
6399 case MESA_SHADER_VERTEX:
6400 if (ctx->options->key.vs.as_ls)
6401 handle_ls_outputs_post(ctx);
6402 else if (ctx->options->key.vs.as_es)
6403 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6404 else
6405 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6406 &ctx->shader_info->vs.outinfo);
6407 break;
6408 case MESA_SHADER_FRAGMENT:
6409 handle_fs_outputs_post(ctx);
6410 break;
6411 case MESA_SHADER_GEOMETRY:
6412 emit_gs_epilogue(ctx);
6413 break;
6414 case MESA_SHADER_TESS_CTRL:
6415 handle_tcs_outputs_post(ctx);
6416 break;
6417 case MESA_SHADER_TESS_EVAL:
6418 if (ctx->options->key.tes.as_es)
6419 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6420 else
6421 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6422 &ctx->shader_info->tes.outinfo);
6423 break;
6424 default:
6425 break;
6426 }
6427 }
6428
6429 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6430 {
6431 LLVMPassManagerRef passmgr;
6432 /* Create the pass manager */
6433 passmgr = LLVMCreateFunctionPassManagerForModule(
6434 ctx->module);
6435
6436 /* This pass should eliminate all the load and store instructions */
6437 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6438
6439 /* Add some optimization passes */
6440 LLVMAddScalarReplAggregatesPass(passmgr);
6441 LLVMAddLICMPass(passmgr);
6442 LLVMAddAggressiveDCEPass(passmgr);
6443 LLVMAddCFGSimplificationPass(passmgr);
6444 LLVMAddInstructionCombiningPass(passmgr);
6445
6446 /* Run the pass */
6447 LLVMInitializeFunctionPassManager(passmgr);
6448 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6449 LLVMFinalizeFunctionPassManager(passmgr);
6450
6451 LLVMDisposeBuilder(ctx->builder);
6452 LLVMDisposePassManager(passmgr);
6453 }
6454
6455 static void
6456 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6457 {
6458 struct ac_vs_output_info *outinfo;
6459
6460 switch (ctx->stage) {
6461 case MESA_SHADER_FRAGMENT:
6462 case MESA_SHADER_COMPUTE:
6463 case MESA_SHADER_TESS_CTRL:
6464 case MESA_SHADER_GEOMETRY:
6465 return;
6466 case MESA_SHADER_VERTEX:
6467 if (ctx->options->key.vs.as_ls ||
6468 ctx->options->key.vs.as_es)
6469 return;
6470 outinfo = &ctx->shader_info->vs.outinfo;
6471 break;
6472 case MESA_SHADER_TESS_EVAL:
6473 if (ctx->options->key.vs.as_es)
6474 return;
6475 outinfo = &ctx->shader_info->tes.outinfo;
6476 break;
6477 default:
6478 unreachable("Unhandled shader type");
6479 }
6480
6481 ac_optimize_vs_outputs(&ctx->ac,
6482 ctx->main_function,
6483 outinfo->vs_output_param_offset,
6484 VARYING_SLOT_MAX,
6485 &outinfo->param_exports);
6486 }
6487
6488 static void
6489 ac_setup_rings(struct nir_to_llvm_context *ctx)
6490 {
6491 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6492 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6493 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6494 }
6495
6496 if (ctx->is_gs_copy_shader) {
6497 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6498 }
6499 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6500 LLVMValueRef tmp;
6501 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6502 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6503
6504 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6505
6506 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6507 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6508 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6509 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6510 }
6511
6512 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6513 ctx->stage == MESA_SHADER_TESS_EVAL) {
6514 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6515 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6516 }
6517 }
6518
6519 static unsigned
6520 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6521 const struct nir_shader *nir)
6522 {
6523 switch (nir->info.stage) {
6524 case MESA_SHADER_TESS_CTRL:
6525 return chip_class >= CIK ? 128 : 64;
6526 case MESA_SHADER_GEOMETRY:
6527 return chip_class >= GFX9 ? 128 : 64;
6528 case MESA_SHADER_COMPUTE:
6529 break;
6530 default:
6531 return 0;
6532 }
6533
6534 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6535 nir->info.cs.local_size[1] *
6536 nir->info.cs.local_size[2];
6537 return max_workgroup_size;
6538 }
6539
6540 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6541 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6542 {
6543 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6544 LLVMConstInt(ctx->ac.i32, 8, false),
6545 LLVMConstInt(ctx->ac.i32, 8, false), false);
6546 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6547 ctx->ac.i32_0, "");
6548 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6549 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6550 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6551 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6552 }
6553
6554 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6555 {
6556 for(int i = 5; i >= 0; --i) {
6557 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6558 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6559 LLVMConstInt(ctx->ac.i32, 16, false), false);
6560 }
6561
6562 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6563 LLVMConstInt(ctx->ac.i32, 16, false),
6564 LLVMConstInt(ctx->ac.i32, 8, false), false);
6565 }
6566
6567 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6568 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6569 {
6570 struct ac_nir_context ctx = {};
6571 struct nir_function *func;
6572
6573 ctx.ac = *ac;
6574 ctx.abi = abi;
6575
6576 ctx.nctx = nctx;
6577 if (nctx)
6578 nctx->nir = &ctx;
6579
6580 ctx.stage = nir->info.stage;
6581
6582 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6583
6584 nir_foreach_variable(variable, &nir->outputs)
6585 handle_shader_output_decl(&ctx, nir, variable);
6586
6587 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6588 _mesa_key_pointer_equal);
6589 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6590 _mesa_key_pointer_equal);
6591 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6592 _mesa_key_pointer_equal);
6593
6594 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6595
6596 setup_locals(&ctx, func);
6597
6598 if (nir->info.stage == MESA_SHADER_COMPUTE)
6599 setup_shared(&ctx, nir);
6600
6601 visit_cf_list(&ctx, &func->impl->body);
6602 phi_post_pass(&ctx);
6603
6604 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6605 ctx.outputs);
6606
6607 free(ctx.locals);
6608 ralloc_free(ctx.defs);
6609 ralloc_free(ctx.phis);
6610 ralloc_free(ctx.vars);
6611
6612 if (nctx)
6613 nctx->nir = NULL;
6614 }
6615
6616 static
6617 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6618 struct nir_shader *const *shaders,
6619 int shader_count,
6620 struct ac_shader_variant_info *shader_info,
6621 const struct ac_nir_compiler_options *options)
6622 {
6623 struct nir_to_llvm_context ctx = {0};
6624 unsigned i;
6625 ctx.options = options;
6626 ctx.shader_info = shader_info;
6627 ctx.context = LLVMContextCreate();
6628 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6629
6630 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6631 options->family);
6632 ctx.ac.module = ctx.module;
6633 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6634
6635 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6636 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6637 LLVMSetDataLayout(ctx.module, data_layout_str);
6638 LLVMDisposeTargetData(data_layout);
6639 LLVMDisposeMessage(data_layout_str);
6640
6641 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6642 ctx.ac.builder = ctx.builder;
6643
6644 memset(shader_info, 0, sizeof(*shader_info));
6645
6646 for(int i = 0; i < shader_count; ++i)
6647 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6648
6649 for (i = 0; i < AC_UD_MAX_SETS; i++)
6650 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6651 for (i = 0; i < AC_UD_MAX_UD; i++)
6652 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6653
6654 ctx.max_workgroup_size = 0;
6655 for (int i = 0; i < shader_count; ++i) {
6656 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6657 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6658 shaders[i]));
6659 }
6660
6661 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6662 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6663
6664 ctx.abi.inputs = &ctx.inputs[0];
6665 ctx.abi.emit_outputs = handle_shader_outputs_post;
6666 ctx.abi.emit_vertex = visit_emit_vertex;
6667 ctx.abi.load_ubo = radv_load_ubo;
6668 ctx.abi.load_ssbo = radv_load_ssbo;
6669 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6670 ctx.abi.clamp_shadow_reference = false;
6671
6672 if (shader_count >= 2)
6673 ac_init_exec_full_mask(&ctx.ac);
6674
6675 if (ctx.ac.chip_class == GFX9 &&
6676 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6677 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6678
6679 for(int i = 0; i < shader_count; ++i) {
6680 ctx.stage = shaders[i]->info.stage;
6681 ctx.output_mask = 0;
6682 ctx.tess_outputs_written = 0;
6683 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6684 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6685
6686 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6687 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6688 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6689 ctx.abi.load_inputs = load_gs_input;
6690 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6691 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6692 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6693 ctx.abi.load_tess_inputs = load_tcs_input;
6694 ctx.abi.store_tcs_outputs = store_tcs_output;
6695 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6696 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6697 ctx.abi.load_tess_inputs = load_tes_input;
6698 ctx.abi.load_tess_coord = load_tess_coord;
6699 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6700 if (shader_info->info.vs.needs_instance_id) {
6701 ctx.shader_info->vs.vgpr_comp_cnt =
6702 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6703 }
6704 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6705 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6706 }
6707
6708 if (i)
6709 emit_barrier(&ctx);
6710
6711 ac_setup_rings(&ctx);
6712
6713 LLVMBasicBlockRef merge_block;
6714 if (shader_count >= 2) {
6715 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6716 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6717 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6718
6719 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6720 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6721 LLVMConstInt(ctx.ac.i32, 8, false), false);
6722 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6723 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6724 thread_id, count, "");
6725 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6726
6727 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6728 }
6729
6730 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6731 handle_fs_inputs(&ctx, shaders[i]);
6732 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6733 handle_vs_inputs(&ctx, shaders[i]);
6734 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6735 prepare_gs_input_vgprs(&ctx);
6736
6737 nir_foreach_variable(variable, &shaders[i]->outputs)
6738 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6739
6740 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6741
6742 if (shader_count >= 2) {
6743 LLVMBuildBr(ctx.ac.builder, merge_block);
6744 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6745 }
6746
6747 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6748 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6749 shaders[i]->info.cull_distance_array_size > 4;
6750 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6751 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6752 shaders[i]->info.gs.vertices_out;
6753 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6754 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6755 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6756 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6757 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6758 }
6759 }
6760
6761 LLVMBuildRetVoid(ctx.builder);
6762
6763 ac_llvm_finalize_module(&ctx);
6764
6765 if (shader_count == 1)
6766 ac_nir_eliminate_const_vs_outputs(&ctx);
6767
6768 return ctx.module;
6769 }
6770
6771 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6772 {
6773 unsigned *retval = (unsigned *)context;
6774 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6775 char *description = LLVMGetDiagInfoDescription(di);
6776
6777 if (severity == LLVMDSError) {
6778 *retval = 1;
6779 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6780 description);
6781 }
6782
6783 LLVMDisposeMessage(description);
6784 }
6785
6786 static unsigned ac_llvm_compile(LLVMModuleRef M,
6787 struct ac_shader_binary *binary,
6788 LLVMTargetMachineRef tm)
6789 {
6790 unsigned retval = 0;
6791 char *err;
6792 LLVMContextRef llvm_ctx;
6793 LLVMMemoryBufferRef out_buffer;
6794 unsigned buffer_size;
6795 const char *buffer_data;
6796 LLVMBool mem_err;
6797
6798 /* Setup Diagnostic Handler*/
6799 llvm_ctx = LLVMGetModuleContext(M);
6800
6801 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6802 &retval);
6803
6804 /* Compile IR*/
6805 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6806 &err, &out_buffer);
6807
6808 /* Process Errors/Warnings */
6809 if (mem_err) {
6810 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6811 free(err);
6812 retval = 1;
6813 goto out;
6814 }
6815
6816 /* Extract Shader Code*/
6817 buffer_size = LLVMGetBufferSize(out_buffer);
6818 buffer_data = LLVMGetBufferStart(out_buffer);
6819
6820 ac_elf_read(buffer_data, buffer_size, binary);
6821
6822 /* Clean up */
6823 LLVMDisposeMemoryBuffer(out_buffer);
6824
6825 out:
6826 return retval;
6827 }
6828
6829 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6830 LLVMModuleRef llvm_module,
6831 struct ac_shader_binary *binary,
6832 struct ac_shader_config *config,
6833 struct ac_shader_variant_info *shader_info,
6834 gl_shader_stage stage,
6835 bool dump_shader, bool supports_spill)
6836 {
6837 if (dump_shader)
6838 ac_dump_module(llvm_module);
6839
6840 memset(binary, 0, sizeof(*binary));
6841 int v = ac_llvm_compile(llvm_module, binary, tm);
6842 if (v) {
6843 fprintf(stderr, "compile failed\n");
6844 }
6845
6846 if (dump_shader)
6847 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6848
6849 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6850
6851 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6852 LLVMDisposeModule(llvm_module);
6853 LLVMContextDispose(ctx);
6854
6855 if (stage == MESA_SHADER_FRAGMENT) {
6856 shader_info->num_input_vgprs = 0;
6857 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 2;
6859 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 2;
6861 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 2;
6863 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 3;
6865 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 2;
6867 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 2;
6869 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 2;
6871 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 1;
6873 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 1;
6875 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 1;
6877 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6878 shader_info->num_input_vgprs += 1;
6879 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6880 shader_info->num_input_vgprs += 1;
6881 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6882 shader_info->num_input_vgprs += 1;
6883 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6884 shader_info->num_input_vgprs += 1;
6885 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6886 shader_info->num_input_vgprs += 1;
6887 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6888 shader_info->num_input_vgprs += 1;
6889 }
6890 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6891
6892 /* +3 for scratch wave offset and VCC */
6893 config->num_sgprs = MAX2(config->num_sgprs,
6894 shader_info->num_input_sgprs + 3);
6895 }
6896
6897 static void
6898 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6899 {
6900 switch (nir->info.stage) {
6901 case MESA_SHADER_COMPUTE:
6902 for (int i = 0; i < 3; ++i)
6903 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6904 break;
6905 case MESA_SHADER_FRAGMENT:
6906 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6907 break;
6908 case MESA_SHADER_GEOMETRY:
6909 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6910 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6911 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6912 shader_info->gs.invocations = nir->info.gs.invocations;
6913 break;
6914 case MESA_SHADER_TESS_EVAL:
6915 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6916 shader_info->tes.spacing = nir->info.tess.spacing;
6917 shader_info->tes.ccw = nir->info.tess.ccw;
6918 shader_info->tes.point_mode = nir->info.tess.point_mode;
6919 shader_info->tes.as_es = options->key.tes.as_es;
6920 break;
6921 case MESA_SHADER_TESS_CTRL:
6922 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6923 break;
6924 case MESA_SHADER_VERTEX:
6925 shader_info->vs.as_es = options->key.vs.as_es;
6926 shader_info->vs.as_ls = options->key.vs.as_ls;
6927 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6928 if (options->key.vs.as_ls)
6929 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6930 break;
6931 default:
6932 break;
6933 }
6934 }
6935
6936 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6937 struct ac_shader_binary *binary,
6938 struct ac_shader_config *config,
6939 struct ac_shader_variant_info *shader_info,
6940 struct nir_shader *const *nir,
6941 int nir_count,
6942 const struct ac_nir_compiler_options *options,
6943 bool dump_shader)
6944 {
6945
6946 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6947 options);
6948
6949 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6950 for (int i = 0; i < nir_count; ++i)
6951 ac_fill_shader_info(shader_info, nir[i], options);
6952 }
6953
6954 static void
6955 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6956 {
6957 LLVMValueRef args[9];
6958 args[0] = ctx->gsvs_ring;
6959 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6960 args[3] = ctx->ac.i32_0;
6961 args[4] = ctx->ac.i32_1; /* OFFEN */
6962 args[5] = ctx->ac.i32_0; /* IDXEN */
6963 args[6] = ctx->ac.i32_1; /* GLC */
6964 args[7] = ctx->ac.i32_1; /* SLC */
6965 args[8] = ctx->ac.i32_0; /* TFE */
6966
6967 int idx = 0;
6968
6969 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6970 int length = 4;
6971 int slot = idx;
6972 int slot_inc = 1;
6973 if (!(ctx->output_mask & (1ull << i)))
6974 continue;
6975
6976 if (i == VARYING_SLOT_CLIP_DIST0) {
6977 /* unpack clip and cull from a single set of slots */
6978 length = ctx->num_output_clips + ctx->num_output_culls;
6979 if (length > 4)
6980 slot_inc = 2;
6981 }
6982
6983 for (unsigned j = 0; j < length; j++) {
6984 LLVMValueRef value;
6985 args[2] = LLVMConstInt(ctx->ac.i32,
6986 (slot * 4 + j) *
6987 ctx->gs_max_out_vertices * 16 * 4, false);
6988
6989 value = ac_build_intrinsic(&ctx->ac,
6990 "llvm.SI.buffer.load.dword.i32.i32",
6991 ctx->ac.i32, args, 9,
6992 AC_FUNC_ATTR_READONLY |
6993 AC_FUNC_ATTR_LEGACY);
6994
6995 LLVMBuildStore(ctx->builder,
6996 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6997 }
6998 idx += slot_inc;
6999 }
7000 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7001 }
7002
7003 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7004 struct nir_shader *geom_shader,
7005 struct ac_shader_binary *binary,
7006 struct ac_shader_config *config,
7007 struct ac_shader_variant_info *shader_info,
7008 const struct ac_nir_compiler_options *options,
7009 bool dump_shader)
7010 {
7011 struct nir_to_llvm_context ctx = {0};
7012 ctx.context = LLVMContextCreate();
7013 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7014 ctx.options = options;
7015 ctx.shader_info = shader_info;
7016
7017 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7018 options->family);
7019 ctx.ac.module = ctx.module;
7020
7021 ctx.is_gs_copy_shader = true;
7022 LLVMSetTarget(ctx.module, "amdgcn--");
7023
7024 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7025 ctx.ac.builder = ctx.builder;
7026 ctx.stage = MESA_SHADER_VERTEX;
7027
7028 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7029
7030 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7031 ac_setup_rings(&ctx);
7032
7033 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7034 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7035
7036 struct ac_nir_context nir_ctx = {};
7037 nir_ctx.ac = ctx.ac;
7038 nir_ctx.abi = &ctx.abi;
7039
7040 nir_ctx.nctx = &ctx;
7041 ctx.nir = &nir_ctx;
7042
7043 nir_foreach_variable(variable, &geom_shader->outputs) {
7044 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7045 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7046 }
7047
7048 ac_gs_copy_shader_emit(&ctx);
7049
7050 ctx.nir = NULL;
7051
7052 LLVMBuildRetVoid(ctx.builder);
7053
7054 ac_llvm_finalize_module(&ctx);
7055
7056 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7057 MESA_SHADER_VERTEX,
7058 dump_shader, options->supports_spill);
7059 }