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ac: rework load_tcs_{inputs,outputs}
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "no-signed-zeros-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
547 gl_shader_stage stage,
548 struct user_sgpr_info *user_sgpr_info)
549 {
550 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
551
552 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
553 if (stage == MESA_SHADER_GEOMETRY ||
554 stage == MESA_SHADER_VERTEX ||
555 stage == MESA_SHADER_TESS_CTRL ||
556 stage == MESA_SHADER_TESS_EVAL ||
557 ctx->is_gs_copy_shader)
558 user_sgpr_info->need_ring_offsets = true;
559
560 if (stage == MESA_SHADER_FRAGMENT &&
561 ctx->shader_info->info.ps.needs_sample_positions)
562 user_sgpr_info->need_ring_offsets = true;
563
564 /* 2 user sgprs will nearly always be allocated for scratch/rings */
565 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
566 user_sgpr_info->sgpr_count += 2;
567 }
568
569 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
570 switch (stage) {
571 case MESA_SHADER_COMPUTE:
572 if (ctx->shader_info->info.cs.uses_grid_size)
573 user_sgpr_info->sgpr_count += 3;
574 break;
575 case MESA_SHADER_FRAGMENT:
576 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
577 break;
578 case MESA_SHADER_VERTEX:
579 if (!ctx->is_gs_copy_shader) {
580 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
581 if (ctx->shader_info->info.vs.needs_draw_id) {
582 user_sgpr_info->sgpr_count += 3;
583 } else {
584 user_sgpr_info->sgpr_count += 2;
585 }
586 }
587 if (ctx->options->key.vs.as_ls)
588 user_sgpr_info->sgpr_count++;
589 break;
590 case MESA_SHADER_TESS_CTRL:
591 user_sgpr_info->sgpr_count += 4;
592 break;
593 case MESA_SHADER_TESS_EVAL:
594 user_sgpr_info->sgpr_count += 1;
595 break;
596 case MESA_SHADER_GEOMETRY:
597 user_sgpr_info->sgpr_count += 2;
598 break;
599 default:
600 break;
601 }
602
603 if (ctx->shader_info->info.loads_push_constants)
604 user_sgpr_info->sgpr_count += 2;
605
606 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
607 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
608
609 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
610 user_sgpr_info->sgpr_count += 2;
611 user_sgpr_info->indirect_all_descriptor_sets = true;
612 } else {
613 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
614 }
615 }
616
617 static void
618 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
619 gl_shader_stage stage,
620 bool has_previous_stage,
621 gl_shader_stage previous_stage,
622 const struct user_sgpr_info *user_sgpr_info,
623 struct arg_info *args,
624 LLVMValueRef *desc_sets)
625 {
626 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
627 unsigned num_sets = ctx->options->layout ?
628 ctx->options->layout->num_sets : 0;
629 unsigned stage_mask = 1 << stage;
630
631 if (has_previous_stage)
632 stage_mask |= 1 << previous_stage;
633
634 /* 1 for each descriptor set */
635 if (!user_sgpr_info->indirect_all_descriptor_sets) {
636 for (unsigned i = 0; i < num_sets; ++i) {
637 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
638 add_array_arg(args, type,
639 &ctx->descriptor_sets[i]);
640 }
641 }
642 } else {
643 add_array_arg(args, const_array(type, 32), desc_sets);
644 }
645
646 if (ctx->shader_info->info.loads_push_constants) {
647 /* 1 for push constants and dynamic descriptors */
648 add_array_arg(args, type, &ctx->push_constants);
649 }
650 }
651
652 static void
653 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
654 gl_shader_stage stage,
655 bool has_previous_stage,
656 gl_shader_stage previous_stage,
657 struct arg_info *args)
658 {
659 if (!ctx->is_gs_copy_shader &&
660 (stage == MESA_SHADER_VERTEX ||
661 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
662 if (ctx->shader_info->info.vs.has_vertex_buffers) {
663 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
664 &ctx->vertex_buffers);
665 }
666 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
667 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
668 if (ctx->shader_info->info.vs.needs_draw_id) {
669 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
670 }
671 }
672 }
673
674 static void
675 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
678 if (!ctx->is_gs_copy_shader) {
679 if (ctx->options->key.vs.as_ls) {
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
682 } else {
683 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
684 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
685 }
686 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
687 }
688 }
689
690 static void
691 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
692 {
693 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
694 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
695 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
696 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
697 }
698
699 static void
700 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
701 bool has_previous_stage, gl_shader_stage previous_stage,
702 const struct user_sgpr_info *user_sgpr_info,
703 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
704 {
705 unsigned num_sets = ctx->options->layout ?
706 ctx->options->layout->num_sets : 0;
707 unsigned stage_mask = 1 << stage;
708
709 if (has_previous_stage)
710 stage_mask |= 1 << previous_stage;
711
712 if (!user_sgpr_info->indirect_all_descriptor_sets) {
713 for (unsigned i = 0; i < num_sets; ++i) {
714 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
715 set_loc_desc(ctx, i, user_sgpr_idx, 0);
716 } else
717 ctx->descriptor_sets[i] = NULL;
718 }
719 } else {
720 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
721 user_sgpr_idx, 2);
722
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
725 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
726 ctx->descriptor_sets[i] =
727 ac_build_load_to_sgpr(&ctx->ac,
728 desc_sets,
729 LLVMConstInt(ctx->ac.i32, i, false));
730
731 } else
732 ctx->descriptor_sets[i] = NULL;
733 }
734 ctx->shader_info->need_indirect_descriptor_sets = true;
735 }
736
737 if (ctx->shader_info->info.loads_push_constants) {
738 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
739 }
740 }
741
742 static void
743 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
744 gl_shader_stage stage, bool has_previous_stage,
745 gl_shader_stage previous_stage,
746 uint8_t *user_sgpr_idx)
747 {
748 if (!ctx->is_gs_copy_shader &&
749 (stage == MESA_SHADER_VERTEX ||
750 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
751 if (ctx->shader_info->info.vs.has_vertex_buffers) {
752 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
753 user_sgpr_idx, 2);
754 }
755
756 unsigned vs_num = 2;
757 if (ctx->shader_info->info.vs.needs_draw_id)
758 vs_num++;
759
760 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
761 user_sgpr_idx, vs_num);
762 }
763 }
764
765 static void create_function(struct nir_to_llvm_context *ctx,
766 gl_shader_stage stage,
767 bool has_previous_stage,
768 gl_shader_stage previous_stage)
769 {
770 uint8_t user_sgpr_idx;
771 struct user_sgpr_info user_sgpr_info;
772 struct arg_info args = {};
773 LLVMValueRef desc_sets;
774
775 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
776
777 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
778 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
779 &ctx->ring_offsets);
780 }
781
782 switch (stage) {
783 case MESA_SHADER_COMPUTE:
784 declare_global_input_sgprs(ctx, stage, has_previous_stage,
785 previous_stage, &user_sgpr_info,
786 &args, &desc_sets);
787
788 if (ctx->shader_info->info.cs.uses_grid_size) {
789 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
790 &ctx->num_work_groups);
791 }
792
793 for (int i = 0; i < 3; i++) {
794 ctx->workgroup_ids[i] = NULL;
795 if (ctx->shader_info->info.cs.uses_block_id[i]) {
796 add_arg(&args, ARG_SGPR, ctx->ac.i32,
797 &ctx->workgroup_ids[i]);
798 }
799 }
800
801 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
802 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
803 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
804 &ctx->local_invocation_ids);
805 break;
806 case MESA_SHADER_VERTEX:
807 declare_global_input_sgprs(ctx, stage, has_previous_stage,
808 previous_stage, &user_sgpr_info,
809 &args, &desc_sets);
810 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
811 previous_stage, &args);
812
813 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
814 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
815 if (ctx->options->key.vs.as_es)
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->es2gs_offset);
818 else if (ctx->options->key.vs.as_ls)
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->ls_out_layout);
821
822 declare_vs_input_vgprs(ctx, &args);
823 break;
824 case MESA_SHADER_TESS_CTRL:
825 if (has_previous_stage) {
826 // First 6 system regs
827 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
828 add_arg(&args, ARG_SGPR, ctx->ac.i32,
829 &ctx->merged_wave_info);
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->tess_factor_offset);
832
833 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
834 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
835 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
836
837 declare_global_input_sgprs(ctx, stage,
838 has_previous_stage,
839 previous_stage,
840 &user_sgpr_info, &args,
841 &desc_sets);
842 declare_vs_specific_input_sgprs(ctx, stage,
843 has_previous_stage,
844 previous_stage, &args);
845
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->ls_out_layout);
848
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->tcs_offchip_layout);
851 add_arg(&args, ARG_SGPR, ctx->ac.i32,
852 &ctx->tcs_out_offsets);
853 add_arg(&args, ARG_SGPR, ctx->ac.i32,
854 &ctx->tcs_out_layout);
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->tcs_in_layout);
857 if (ctx->shader_info->info.needs_multiview_view_index)
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->view_index);
860
861 add_arg(&args, ARG_VGPR, ctx->ac.i32,
862 &ctx->abi.tcs_patch_id);
863 add_arg(&args, ARG_VGPR, ctx->ac.i32,
864 &ctx->abi.tcs_rel_ids);
865
866 declare_vs_input_vgprs(ctx, &args);
867 } else {
868 declare_global_input_sgprs(ctx, stage,
869 has_previous_stage,
870 previous_stage,
871 &user_sgpr_info, &args,
872 &desc_sets);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->tcs_offchip_layout);
876 add_arg(&args, ARG_SGPR, ctx->ac.i32,
877 &ctx->tcs_out_offsets);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tcs_out_layout);
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->tcs_in_layout);
882 if (ctx->shader_info->info.needs_multiview_view_index)
883 add_arg(&args, ARG_SGPR, ctx->ac.i32,
884 &ctx->view_index);
885
886 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
887 add_arg(&args, ARG_SGPR, ctx->ac.i32,
888 &ctx->tess_factor_offset);
889 add_arg(&args, ARG_VGPR, ctx->ac.i32,
890 &ctx->abi.tcs_patch_id);
891 add_arg(&args, ARG_VGPR, ctx->ac.i32,
892 &ctx->abi.tcs_rel_ids);
893 }
894 break;
895 case MESA_SHADER_TESS_EVAL:
896 declare_global_input_sgprs(ctx, stage, has_previous_stage,
897 previous_stage, &user_sgpr_info,
898 &args, &desc_sets);
899
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
901 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
903
904 if (ctx->options->key.tes.as_es) {
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
906 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->es2gs_offset);
909 } else {
910 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912 }
913 declare_tes_input_vgprs(ctx, &args);
914 break;
915 case MESA_SHADER_GEOMETRY:
916 if (has_previous_stage) {
917 // First 6 system regs
918 add_arg(&args, ARG_SGPR, ctx->ac.i32,
919 &ctx->gs2vs_offset);
920 add_arg(&args, ARG_SGPR, ctx->ac.i32,
921 &ctx->merged_wave_info);
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
923
924 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
925 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
926 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
927
928 declare_global_input_sgprs(ctx, stage,
929 has_previous_stage,
930 previous_stage,
931 &user_sgpr_info, &args,
932 &desc_sets);
933
934 if (previous_stage == MESA_SHADER_TESS_EVAL) {
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->tcs_offchip_layout);
937 } else {
938 declare_vs_specific_input_sgprs(ctx, stage,
939 has_previous_stage,
940 previous_stage,
941 &args);
942 }
943
944 add_arg(&args, ARG_SGPR, ctx->ac.i32,
945 &ctx->gsvs_ring_stride);
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->gsvs_num_entries);
948 if (ctx->shader_info->info.needs_multiview_view_index)
949 add_arg(&args, ARG_SGPR, ctx->ac.i32,
950 &ctx->view_index);
951
952 add_arg(&args, ARG_VGPR, ctx->ac.i32,
953 &ctx->gs_vtx_offset[0]);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32,
955 &ctx->gs_vtx_offset[2]);
956 add_arg(&args, ARG_VGPR, ctx->ac.i32,
957 &ctx->abi.gs_prim_id);
958 add_arg(&args, ARG_VGPR, ctx->ac.i32,
959 &ctx->abi.gs_invocation_id);
960 add_arg(&args, ARG_VGPR, ctx->ac.i32,
961 &ctx->gs_vtx_offset[4]);
962
963 if (previous_stage == MESA_SHADER_VERTEX) {
964 declare_vs_input_vgprs(ctx, &args);
965 } else {
966 declare_tes_input_vgprs(ctx, &args);
967 }
968 } else {
969 declare_global_input_sgprs(ctx, stage,
970 has_previous_stage,
971 previous_stage,
972 &user_sgpr_info, &args,
973 &desc_sets);
974
975 add_arg(&args, ARG_SGPR, ctx->ac.i32,
976 &ctx->gsvs_ring_stride);
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->gsvs_num_entries);
979 if (ctx->shader_info->info.needs_multiview_view_index)
980 add_arg(&args, ARG_SGPR, ctx->ac.i32,
981 &ctx->view_index);
982
983 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
984 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[0]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->gs_vtx_offset[1]);
989 add_arg(&args, ARG_VGPR, ctx->ac.i32,
990 &ctx->abi.gs_prim_id);
991 add_arg(&args, ARG_VGPR, ctx->ac.i32,
992 &ctx->gs_vtx_offset[2]);
993 add_arg(&args, ARG_VGPR, ctx->ac.i32,
994 &ctx->gs_vtx_offset[3]);
995 add_arg(&args, ARG_VGPR, ctx->ac.i32,
996 &ctx->gs_vtx_offset[4]);
997 add_arg(&args, ARG_VGPR, ctx->ac.i32,
998 &ctx->gs_vtx_offset[5]);
999 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1000 &ctx->abi.gs_invocation_id);
1001 }
1002 break;
1003 case MESA_SHADER_FRAGMENT:
1004 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1005 previous_stage, &user_sgpr_info,
1006 &args, &desc_sets);
1007
1008 if (ctx->shader_info->info.ps.needs_sample_positions)
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1010 &ctx->sample_pos_offset);
1011
1012 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1016 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1017 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1018 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1019 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1021 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1022 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1023 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1024 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1026 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1027 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1028 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1029 break;
1030 default:
1031 unreachable("Shader stage not implemented");
1032 }
1033
1034 ctx->main_function = create_llvm_function(
1035 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1036 ctx->max_workgroup_size,
1037 ctx->options->unsafe_math);
1038 set_llvm_calling_convention(ctx->main_function, stage);
1039
1040
1041 ctx->shader_info->num_input_vgprs = 0;
1042 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1043
1044 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1045
1046 if (ctx->stage != MESA_SHADER_FRAGMENT)
1047 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1048
1049 assign_arguments(ctx->main_function, &args);
1050
1051 user_sgpr_idx = 0;
1052
1053 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1054 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1055 &user_sgpr_idx, 2);
1056 if (ctx->options->supports_spill) {
1057 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1058 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1059 NULL, 0, AC_FUNC_ATTR_READNONE);
1060 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1061 const_array(ctx->ac.v4i32, 16), "");
1062 }
1063 }
1064
1065 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1066 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1067 if (has_previous_stage)
1068 user_sgpr_idx = 0;
1069
1070 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1071 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1072
1073 switch (stage) {
1074 case MESA_SHADER_COMPUTE:
1075 if (ctx->shader_info->info.cs.uses_grid_size) {
1076 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1077 &user_sgpr_idx, 3);
1078 }
1079 break;
1080 case MESA_SHADER_VERTEX:
1081 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1082 previous_stage, &user_sgpr_idx);
1083 if (ctx->view_index)
1084 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1085 if (ctx->options->key.vs.as_ls) {
1086 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1087 &user_sgpr_idx, 1);
1088 }
1089 if (ctx->options->key.vs.as_ls)
1090 ac_declare_lds_as_pointer(&ctx->ac);
1091 break;
1092 case MESA_SHADER_TESS_CTRL:
1093 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1094 previous_stage, &user_sgpr_idx);
1095 if (has_previous_stage)
1096 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1097 &user_sgpr_idx, 1);
1098 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1099 if (ctx->view_index)
1100 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1101 ac_declare_lds_as_pointer(&ctx->ac);
1102 break;
1103 case MESA_SHADER_TESS_EVAL:
1104 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1105 if (ctx->view_index)
1106 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1107 break;
1108 case MESA_SHADER_GEOMETRY:
1109 if (has_previous_stage) {
1110 if (previous_stage == MESA_SHADER_VERTEX)
1111 set_vs_specific_input_locs(ctx, stage,
1112 has_previous_stage,
1113 previous_stage,
1114 &user_sgpr_idx);
1115 else
1116 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1117 &user_sgpr_idx, 1);
1118 }
1119 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1120 &user_sgpr_idx, 2);
1121 if (ctx->view_index)
1122 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1123 if (has_previous_stage)
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 break;
1126 case MESA_SHADER_FRAGMENT:
1127 if (ctx->shader_info->info.ps.needs_sample_positions) {
1128 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1129 &user_sgpr_idx, 1);
1130 }
1131 break;
1132 default:
1133 unreachable("Shader stage not implemented");
1134 }
1135
1136 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1137 }
1138
1139 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1140 LLVMValueRef value, unsigned count)
1141 {
1142 unsigned num_components = ac_get_llvm_num_components(value);
1143 if (count == num_components)
1144 return value;
1145
1146 LLVMValueRef masks[] = {
1147 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1148 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1149
1150 if (count == 1)
1151 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1152 "");
1153
1154 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1155 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1156 }
1157
1158 static void
1159 build_store_values_extended(struct ac_llvm_context *ac,
1160 LLVMValueRef *values,
1161 unsigned value_count,
1162 unsigned value_stride,
1163 LLVMValueRef vec)
1164 {
1165 LLVMBuilderRef builder = ac->builder;
1166 unsigned i;
1167
1168 for (i = 0; i < value_count; i++) {
1169 LLVMValueRef ptr = values[i * value_stride];
1170 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1171 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1172 LLVMBuildStore(builder, value, ptr);
1173 }
1174 }
1175
1176 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1177 const nir_ssa_def *def)
1178 {
1179 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1180 if (def->num_components > 1) {
1181 type = LLVMVectorType(type, def->num_components);
1182 }
1183 return type;
1184 }
1185
1186 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1187 {
1188 assert(src.is_ssa);
1189 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1190 return (LLVMValueRef)entry->data;
1191 }
1192
1193
1194 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1195 const struct nir_block *b)
1196 {
1197 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1198 return (LLVMBasicBlockRef)entry->data;
1199 }
1200
1201 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1202 nir_alu_src src,
1203 unsigned num_components)
1204 {
1205 LLVMValueRef value = get_src(ctx, src.src);
1206 bool need_swizzle = false;
1207
1208 assert(value);
1209 LLVMTypeRef type = LLVMTypeOf(value);
1210 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1211 ? LLVMGetVectorSize(type)
1212 : 1;
1213
1214 for (unsigned i = 0; i < num_components; ++i) {
1215 assert(src.swizzle[i] < src_components);
1216 if (src.swizzle[i] != i)
1217 need_swizzle = true;
1218 }
1219
1220 if (need_swizzle || num_components != src_components) {
1221 LLVMValueRef masks[] = {
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1223 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1224 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1225 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1226
1227 if (src_components > 1 && num_components == 1) {
1228 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1229 masks[0], "");
1230 } else if (src_components == 1 && num_components > 1) {
1231 LLVMValueRef values[] = {value, value, value, value};
1232 value = ac_build_gather_values(&ctx->ac, values, num_components);
1233 } else {
1234 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1235 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1236 swizzle, "");
1237 }
1238 }
1239 assert(!src.negate);
1240 assert(!src.abs);
1241 return value;
1242 }
1243
1244 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1245 LLVMIntPredicate pred, LLVMValueRef src0,
1246 LLVMValueRef src1)
1247 {
1248 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1249 return LLVMBuildSelect(ctx->builder, result,
1250 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1251 ctx->i32_0, "");
1252 }
1253
1254 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1255 LLVMRealPredicate pred, LLVMValueRef src0,
1256 LLVMValueRef src1)
1257 {
1258 LLVMValueRef result;
1259 src0 = ac_to_float(ctx, src0);
1260 src1 = ac_to_float(ctx, src1);
1261 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1262 return LLVMBuildSelect(ctx->builder, result,
1263 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1264 ctx->i32_0, "");
1265 }
1266
1267 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1268 const char *intrin,
1269 LLVMTypeRef result_type,
1270 LLVMValueRef src0)
1271 {
1272 char name[64];
1273 LLVMValueRef params[] = {
1274 ac_to_float(ctx, src0),
1275 };
1276
1277 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1278 get_elem_bits(ctx, result_type));
1279 assert(length < sizeof(name));
1280 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1281 }
1282
1283 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1284 const char *intrin,
1285 LLVMTypeRef result_type,
1286 LLVMValueRef src0, LLVMValueRef src1)
1287 {
1288 char name[64];
1289 LLVMValueRef params[] = {
1290 ac_to_float(ctx, src0),
1291 ac_to_float(ctx, src1),
1292 };
1293
1294 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1295 get_elem_bits(ctx, result_type));
1296 assert(length < sizeof(name));
1297 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1298 }
1299
1300 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1301 const char *intrin,
1302 LLVMTypeRef result_type,
1303 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1304 {
1305 char name[64];
1306 LLVMValueRef params[] = {
1307 ac_to_float(ctx, src0),
1308 ac_to_float(ctx, src1),
1309 ac_to_float(ctx, src2),
1310 };
1311
1312 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1313 get_elem_bits(ctx, result_type));
1314 assert(length < sizeof(name));
1315 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1316 }
1317
1318 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1319 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1320 {
1321 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1322 ctx->i32_0, "");
1323 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1324 }
1325
1326 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1327 LLVMIntPredicate pred,
1328 LLVMValueRef src0, LLVMValueRef src1)
1329 {
1330 return LLVMBuildSelect(ctx->builder,
1331 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1332 src0,
1333 src1, "");
1334
1335 }
1336 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1337 LLVMValueRef src0)
1338 {
1339 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1340 LLVMBuildNeg(ctx->builder, src0, ""));
1341 }
1342
1343 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0,
1345 unsigned bitsize)
1346 {
1347 LLVMValueRef cmp, val, zero, one;
1348 LLVMTypeRef type;
1349
1350 if (bitsize == 32) {
1351 type = ctx->f32;
1352 zero = ctx->f32_0;
1353 one = ctx->f32_1;
1354 } else {
1355 type = ctx->f64;
1356 zero = ctx->f64_0;
1357 one = ctx->f64_1;
1358 }
1359
1360 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1361 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1362 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1363 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1364 return val;
1365 }
1366
1367 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1368 LLVMValueRef src0, unsigned bitsize)
1369 {
1370 LLVMValueRef cmp, val, zero, one;
1371 LLVMTypeRef type;
1372
1373 if (bitsize == 32) {
1374 type = ctx->i32;
1375 zero = ctx->i32_0;
1376 one = ctx->i32_1;
1377 } else {
1378 type = ctx->i64;
1379 zero = ctx->i64_0;
1380 one = ctx->i64_1;
1381 }
1382
1383 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1384 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1385 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1386 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1387 return val;
1388 }
1389
1390 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1391 LLVMValueRef src0)
1392 {
1393 const char *intr = "llvm.floor.f32";
1394 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1395 LLVMValueRef params[] = {
1396 fsrc0,
1397 };
1398 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1399 ctx->f32, params, 1,
1400 AC_FUNC_ATTR_READNONE);
1401 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1402 }
1403
1404 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1405 const char *intrin,
1406 LLVMValueRef src0, LLVMValueRef src1)
1407 {
1408 LLVMTypeRef ret_type;
1409 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1410 LLVMValueRef res;
1411 LLVMValueRef params[] = { src0, src1 };
1412 ret_type = LLVMStructTypeInContext(ctx->context, types,
1413 2, true);
1414
1415 res = ac_build_intrinsic(ctx, intrin, ret_type,
1416 params, 2, AC_FUNC_ATTR_READNONE);
1417
1418 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1419 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1420 return res;
1421 }
1422
1423 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1424 LLVMValueRef src0)
1425 {
1426 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1427 }
1428
1429 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1430 LLVMValueRef src0)
1431 {
1432 src0 = ac_to_float(ctx, src0);
1433 return LLVMBuildSExt(ctx->builder,
1434 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1435 ctx->i32, "");
1436 }
1437
1438 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1439 LLVMValueRef src0,
1440 unsigned bitsize)
1441 {
1442 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1443
1444 if (bitsize == 32)
1445 return result;
1446
1447 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1448 }
1449
1450 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1451 LLVMValueRef src0)
1452 {
1453 return LLVMBuildSExt(ctx->builder,
1454 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1455 ctx->i32, "");
1456 }
1457
1458 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1459 LLVMValueRef src0)
1460 {
1461 LLVMValueRef result;
1462 LLVMValueRef cond = NULL;
1463
1464 src0 = ac_to_float(&ctx->ac, src0);
1465 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1466
1467 if (ctx->options->chip_class >= VI) {
1468 LLVMValueRef args[2];
1469 /* Check if the result is a denormal - and flush to 0 if so. */
1470 args[0] = result;
1471 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1472 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1473 }
1474
1475 /* need to convert back up to f32 */
1476 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1477
1478 if (ctx->options->chip_class >= VI)
1479 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1480 else {
1481 /* for SI/CIK */
1482 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1483 * so compare the result and flush to 0 if it's smaller.
1484 */
1485 LLVMValueRef temp, cond2;
1486 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1487 ctx->ac.f32, result);
1488 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1489 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1490 temp, "");
1491 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1492 temp, ctx->ac.f32_0, "");
1493 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1494 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1495 }
1496 return result;
1497 }
1498
1499 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1500 LLVMValueRef src0, LLVMValueRef src1)
1501 {
1502 LLVMValueRef dst64, result;
1503 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1504 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1505
1506 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1507 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1508 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1509 return result;
1510 }
1511
1512 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1513 LLVMValueRef src0, LLVMValueRef src1)
1514 {
1515 LLVMValueRef dst64, result;
1516 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1517 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1518
1519 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1520 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1521 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1522 return result;
1523 }
1524
1525 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1526 bool is_signed,
1527 const LLVMValueRef srcs[3])
1528 {
1529 LLVMValueRef result;
1530 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1531
1532 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1533 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1534 return result;
1535 }
1536
1537 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1538 LLVMValueRef src0, LLVMValueRef src1,
1539 LLVMValueRef src2, LLVMValueRef src3)
1540 {
1541 LLVMValueRef bfi_args[3], result;
1542
1543 bfi_args[0] = LLVMBuildShl(ctx->builder,
1544 LLVMBuildSub(ctx->builder,
1545 LLVMBuildShl(ctx->builder,
1546 ctx->i32_1,
1547 src3, ""),
1548 ctx->i32_1, ""),
1549 src2, "");
1550 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1551 bfi_args[2] = src0;
1552
1553 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1554
1555 /* Calculate:
1556 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1557 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1558 */
1559 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1560 LLVMBuildAnd(ctx->builder, bfi_args[0],
1561 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1562
1563 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1564 return result;
1565 }
1566
1567 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1568 LLVMValueRef src0)
1569 {
1570 LLVMValueRef comp[2];
1571
1572 src0 = ac_to_float(ctx, src0);
1573 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1574 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1575
1576 return ac_build_cvt_pkrtz_f16(ctx, comp);
1577 }
1578
1579 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1580 LLVMValueRef src0)
1581 {
1582 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1583 LLVMValueRef temps[2], result, val;
1584 int i;
1585
1586 for (i = 0; i < 2; i++) {
1587 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1588 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1589 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1590 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1591 }
1592
1593 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1594 ctx->i32_0, "");
1595 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1596 ctx->i32_1, "");
1597 return result;
1598 }
1599
1600 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1601 nir_op op,
1602 LLVMValueRef src0)
1603 {
1604 unsigned mask;
1605 int idx;
1606 LLVMValueRef result;
1607
1608 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1609 mask = AC_TID_MASK_LEFT;
1610 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1611 mask = AC_TID_MASK_TOP;
1612 else
1613 mask = AC_TID_MASK_TOP_LEFT;
1614
1615 /* for DDX we want to next X pixel, DDY next Y pixel. */
1616 if (op == nir_op_fddx_fine ||
1617 op == nir_op_fddx_coarse ||
1618 op == nir_op_fddx)
1619 idx = 1;
1620 else
1621 idx = 2;
1622
1623 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1624 return result;
1625 }
1626
1627 /*
1628 * this takes an I,J coordinate pair,
1629 * and works out the X and Y derivatives.
1630 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1631 */
1632 static LLVMValueRef emit_ddxy_interp(
1633 struct ac_nir_context *ctx,
1634 LLVMValueRef interp_ij)
1635 {
1636 LLVMValueRef result[4], a;
1637 unsigned i;
1638
1639 for (i = 0; i < 2; i++) {
1640 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1641 LLVMConstInt(ctx->ac.i32, i, false), "");
1642 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1643 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1644 }
1645 return ac_build_gather_values(&ctx->ac, result, 4);
1646 }
1647
1648 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1649 {
1650 LLVMValueRef src[4], result = NULL;
1651 unsigned num_components = instr->dest.dest.ssa.num_components;
1652 unsigned src_components;
1653 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1654
1655 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1656 switch (instr->op) {
1657 case nir_op_vec2:
1658 case nir_op_vec3:
1659 case nir_op_vec4:
1660 src_components = 1;
1661 break;
1662 case nir_op_pack_half_2x16:
1663 src_components = 2;
1664 break;
1665 case nir_op_unpack_half_2x16:
1666 src_components = 1;
1667 break;
1668 default:
1669 src_components = num_components;
1670 break;
1671 }
1672 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1673 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1674
1675 switch (instr->op) {
1676 case nir_op_fmov:
1677 case nir_op_imov:
1678 result = src[0];
1679 break;
1680 case nir_op_fneg:
1681 src[0] = ac_to_float(&ctx->ac, src[0]);
1682 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1683 break;
1684 case nir_op_ineg:
1685 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_inot:
1688 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1689 break;
1690 case nir_op_iadd:
1691 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_fadd:
1694 src[0] = ac_to_float(&ctx->ac, src[0]);
1695 src[1] = ac_to_float(&ctx->ac, src[1]);
1696 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1697 break;
1698 case nir_op_fsub:
1699 src[0] = ac_to_float(&ctx->ac, src[0]);
1700 src[1] = ac_to_float(&ctx->ac, src[1]);
1701 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_isub:
1704 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_imul:
1707 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_imod:
1710 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_umod:
1713 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1714 break;
1715 case nir_op_fmod:
1716 src[0] = ac_to_float(&ctx->ac, src[0]);
1717 src[1] = ac_to_float(&ctx->ac, src[1]);
1718 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1719 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1720 ac_to_float_type(&ctx->ac, def_type), result);
1721 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1722 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1723 break;
1724 case nir_op_frem:
1725 src[0] = ac_to_float(&ctx->ac, src[0]);
1726 src[1] = ac_to_float(&ctx->ac, src[1]);
1727 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_irem:
1730 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_idiv:
1733 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_udiv:
1736 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1737 break;
1738 case nir_op_fmul:
1739 src[0] = ac_to_float(&ctx->ac, src[0]);
1740 src[1] = ac_to_float(&ctx->ac, src[1]);
1741 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1742 break;
1743 case nir_op_fdiv:
1744 src[0] = ac_to_float(&ctx->ac, src[0]);
1745 src[1] = ac_to_float(&ctx->ac, src[1]);
1746 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1747 break;
1748 case nir_op_frcp:
1749 src[0] = ac_to_float(&ctx->ac, src[0]);
1750 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1751 src[0]);
1752 break;
1753 case nir_op_iand:
1754 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1755 break;
1756 case nir_op_ior:
1757 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1758 break;
1759 case nir_op_ixor:
1760 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1761 break;
1762 case nir_op_ishl:
1763 result = LLVMBuildShl(ctx->ac.builder, src[0],
1764 LLVMBuildZExt(ctx->ac.builder, src[1],
1765 LLVMTypeOf(src[0]), ""),
1766 "");
1767 break;
1768 case nir_op_ishr:
1769 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1770 LLVMBuildZExt(ctx->ac.builder, src[1],
1771 LLVMTypeOf(src[0]), ""),
1772 "");
1773 break;
1774 case nir_op_ushr:
1775 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1776 LLVMBuildZExt(ctx->ac.builder, src[1],
1777 LLVMTypeOf(src[0]), ""),
1778 "");
1779 break;
1780 case nir_op_ilt:
1781 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1782 break;
1783 case nir_op_ine:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1785 break;
1786 case nir_op_ieq:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1788 break;
1789 case nir_op_ige:
1790 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1791 break;
1792 case nir_op_ult:
1793 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1794 break;
1795 case nir_op_uge:
1796 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1797 break;
1798 case nir_op_feq:
1799 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1800 break;
1801 case nir_op_fne:
1802 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1803 break;
1804 case nir_op_flt:
1805 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1806 break;
1807 case nir_op_fge:
1808 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1809 break;
1810 case nir_op_fabs:
1811 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1812 ac_to_float_type(&ctx->ac, def_type), src[0]);
1813 break;
1814 case nir_op_iabs:
1815 result = emit_iabs(&ctx->ac, src[0]);
1816 break;
1817 case nir_op_imax:
1818 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1819 break;
1820 case nir_op_imin:
1821 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1822 break;
1823 case nir_op_umax:
1824 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1825 break;
1826 case nir_op_umin:
1827 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1828 break;
1829 case nir_op_isign:
1830 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1831 break;
1832 case nir_op_fsign:
1833 src[0] = ac_to_float(&ctx->ac, src[0]);
1834 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1835 break;
1836 case nir_op_ffloor:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_ftrunc:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 break;
1844 case nir_op_fceil:
1845 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1846 ac_to_float_type(&ctx->ac, def_type), src[0]);
1847 break;
1848 case nir_op_fround_even:
1849 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1850 ac_to_float_type(&ctx->ac, def_type),src[0]);
1851 break;
1852 case nir_op_ffract:
1853 result = emit_ffract(&ctx->ac, src[0]);
1854 break;
1855 case nir_op_fsin:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 break;
1859 case nir_op_fcos:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_fsqrt:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_fexp2:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 break;
1871 case nir_op_flog2:
1872 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1873 ac_to_float_type(&ctx->ac, def_type), src[0]);
1874 break;
1875 case nir_op_frsq:
1876 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1877 ac_to_float_type(&ctx->ac, def_type), src[0]);
1878 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1879 result);
1880 break;
1881 case nir_op_fpow:
1882 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1883 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1884 break;
1885 case nir_op_fmax:
1886 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1887 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1888 if (instr->dest.dest.ssa.bit_size == 32)
1889 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1890 ac_to_float_type(&ctx->ac, def_type),
1891 result);
1892 break;
1893 case nir_op_fmin:
1894 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1895 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1896 if (instr->dest.dest.ssa.bit_size == 32)
1897 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1898 ac_to_float_type(&ctx->ac, def_type),
1899 result);
1900 break;
1901 case nir_op_ffma:
1902 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1903 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1904 break;
1905 case nir_op_ibitfield_extract:
1906 result = emit_bitfield_extract(&ctx->ac, true, src);
1907 break;
1908 case nir_op_ubitfield_extract:
1909 result = emit_bitfield_extract(&ctx->ac, false, src);
1910 break;
1911 case nir_op_bitfield_insert:
1912 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1913 break;
1914 case nir_op_bitfield_reverse:
1915 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1916 break;
1917 case nir_op_bit_count:
1918 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1919 break;
1920 case nir_op_vec2:
1921 case nir_op_vec3:
1922 case nir_op_vec4:
1923 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1924 src[i] = ac_to_integer(&ctx->ac, src[i]);
1925 result = ac_build_gather_values(&ctx->ac, src, num_components);
1926 break;
1927 case nir_op_f2i32:
1928 case nir_op_f2i64:
1929 src[0] = ac_to_float(&ctx->ac, src[0]);
1930 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1931 break;
1932 case nir_op_f2u32:
1933 case nir_op_f2u64:
1934 src[0] = ac_to_float(&ctx->ac, src[0]);
1935 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1936 break;
1937 case nir_op_i2f32:
1938 case nir_op_i2f64:
1939 src[0] = ac_to_integer(&ctx->ac, src[0]);
1940 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1941 break;
1942 case nir_op_u2f32:
1943 case nir_op_u2f64:
1944 src[0] = ac_to_integer(&ctx->ac, src[0]);
1945 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1946 break;
1947 case nir_op_f2f64:
1948 src[0] = ac_to_float(&ctx->ac, src[0]);
1949 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1950 break;
1951 case nir_op_f2f32:
1952 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_u2u32:
1955 case nir_op_u2u64:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1958 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1959 else
1960 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1961 break;
1962 case nir_op_i2i32:
1963 case nir_op_i2i64:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1966 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1967 else
1968 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1969 break;
1970 case nir_op_bcsel:
1971 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1972 break;
1973 case nir_op_find_lsb:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1976 break;
1977 case nir_op_ufind_msb:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1980 break;
1981 case nir_op_ifind_msb:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1984 break;
1985 case nir_op_uadd_carry:
1986 src[0] = ac_to_integer(&ctx->ac, src[0]);
1987 src[1] = ac_to_integer(&ctx->ac, src[1]);
1988 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1989 break;
1990 case nir_op_usub_borrow:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 src[1] = ac_to_integer(&ctx->ac, src[1]);
1993 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1994 break;
1995 case nir_op_b2f:
1996 result = emit_b2f(&ctx->ac, src[0]);
1997 break;
1998 case nir_op_f2b:
1999 result = emit_f2b(&ctx->ac, src[0]);
2000 break;
2001 case nir_op_b2i:
2002 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2003 break;
2004 case nir_op_i2b:
2005 src[0] = ac_to_integer(&ctx->ac, src[0]);
2006 result = emit_i2b(&ctx->ac, src[0]);
2007 break;
2008 case nir_op_fquantize2f16:
2009 result = emit_f2f16(ctx->nctx, src[0]);
2010 break;
2011 case nir_op_umul_high:
2012 src[0] = ac_to_integer(&ctx->ac, src[0]);
2013 src[1] = ac_to_integer(&ctx->ac, src[1]);
2014 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2015 break;
2016 case nir_op_imul_high:
2017 src[0] = ac_to_integer(&ctx->ac, src[0]);
2018 src[1] = ac_to_integer(&ctx->ac, src[1]);
2019 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2020 break;
2021 case nir_op_pack_half_2x16:
2022 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_unpack_half_2x16:
2025 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2026 break;
2027 case nir_op_fddx:
2028 case nir_op_fddy:
2029 case nir_op_fddx_fine:
2030 case nir_op_fddy_fine:
2031 case nir_op_fddx_coarse:
2032 case nir_op_fddy_coarse:
2033 result = emit_ddxy(ctx, instr->op, src[0]);
2034 break;
2035
2036 case nir_op_unpack_64_2x32_split_x: {
2037 assert(instr->src[0].src.ssa->num_components == 1);
2038 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2039 ctx->ac.v2i32,
2040 "");
2041 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2042 ctx->ac.i32_0, "");
2043 break;
2044 }
2045
2046 case nir_op_unpack_64_2x32_split_y: {
2047 assert(instr->src[0].src.ssa->num_components == 1);
2048 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2049 ctx->ac.v2i32,
2050 "");
2051 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2052 ctx->ac.i32_1, "");
2053 break;
2054 }
2055
2056 case nir_op_pack_64_2x32_split: {
2057 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2058 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2059 src[0], ctx->ac.i32_0, "");
2060 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2061 src[1], ctx->ac.i32_1, "");
2062 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2063 break;
2064 }
2065
2066 default:
2067 fprintf(stderr, "Unknown NIR alu instr: ");
2068 nir_print_instr(&instr->instr, stderr);
2069 fprintf(stderr, "\n");
2070 abort();
2071 }
2072
2073 if (result) {
2074 assert(instr->dest.dest.is_ssa);
2075 result = ac_to_integer(&ctx->ac, result);
2076 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2077 result);
2078 }
2079 }
2080
2081 static void visit_load_const(struct ac_nir_context *ctx,
2082 const nir_load_const_instr *instr)
2083 {
2084 LLVMValueRef values[4], value = NULL;
2085 LLVMTypeRef element_type =
2086 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2087
2088 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2089 switch (instr->def.bit_size) {
2090 case 32:
2091 values[i] = LLVMConstInt(element_type,
2092 instr->value.u32[i], false);
2093 break;
2094 case 64:
2095 values[i] = LLVMConstInt(element_type,
2096 instr->value.u64[i], false);
2097 break;
2098 default:
2099 fprintf(stderr,
2100 "unsupported nir load_const bit_size: %d\n",
2101 instr->def.bit_size);
2102 abort();
2103 }
2104 }
2105 if (instr->def.num_components > 1) {
2106 value = LLVMConstVector(values, instr->def.num_components);
2107 } else
2108 value = values[0];
2109
2110 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2111 }
2112
2113 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2114 LLVMTypeRef type)
2115 {
2116 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2117 return LLVMBuildBitCast(ctx->builder, ptr,
2118 LLVMPointerType(type, addr_space), "");
2119 }
2120
2121 static LLVMValueRef
2122 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2123 {
2124 LLVMValueRef size =
2125 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2126 LLVMConstInt(ctx->ac.i32, 2, false), "");
2127
2128 /* VI only */
2129 if (ctx->ac.chip_class == VI && in_elements) {
2130 /* On VI, the descriptor contains the size in bytes,
2131 * but TXQ must return the size in elements.
2132 * The stride is always non-zero for resources using TXQ.
2133 */
2134 LLVMValueRef stride =
2135 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2136 ctx->ac.i32_1, "");
2137 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2138 LLVMConstInt(ctx->ac.i32, 16, false), "");
2139 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2140 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2141
2142 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2143 }
2144 return size;
2145 }
2146
2147 /**
2148 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2149 * intrinsic names).
2150 */
2151 static void build_int_type_name(
2152 LLVMTypeRef type,
2153 char *buf, unsigned bufsize)
2154 {
2155 assert(bufsize >= 6);
2156
2157 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2158 snprintf(buf, bufsize, "v%ui32",
2159 LLVMGetVectorSize(type));
2160 else
2161 strcpy(buf, "i32");
2162 }
2163
2164 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2165 struct ac_image_args *args,
2166 const nir_tex_instr *instr)
2167 {
2168 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2169 LLVMValueRef coord = args->addr;
2170 LLVMValueRef half_texel[2];
2171 LLVMValueRef compare_cube_wa = NULL;
2172 LLVMValueRef result;
2173 int c;
2174 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2175
2176 //TODO Rect
2177 {
2178 struct ac_image_args txq_args = { 0 };
2179
2180 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2181 txq_args.opcode = ac_image_get_resinfo;
2182 txq_args.dmask = 0xf;
2183 txq_args.addr = ctx->i32_0;
2184 txq_args.resource = args->resource;
2185 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2186
2187 for (c = 0; c < 2; c++) {
2188 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2189 LLVMConstInt(ctx->i32, c, false), "");
2190 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2191 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2192 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2193 LLVMConstReal(ctx->f32, -0.5), "");
2194 }
2195 }
2196
2197 LLVMValueRef orig_coords = args->addr;
2198
2199 for (c = 0; c < 2; c++) {
2200 LLVMValueRef tmp;
2201 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2202 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2203 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2204 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2205 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2206 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2207 }
2208
2209
2210 /*
2211 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2212 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2213 * workaround by sampling using a scaled type and converting.
2214 * This is taken from amdgpu-pro shaders.
2215 */
2216 /* NOTE this produces some ugly code compared to amdgpu-pro,
2217 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2218 * and then reads them back. -pro generates two selects,
2219 * one s_cmp for the descriptor rewriting
2220 * one v_cmp for the coordinate and result changes.
2221 */
2222 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2223 LLVMValueRef tmp, tmp2;
2224
2225 /* workaround 8/8/8/8 uint/sint cube gather bug */
2226 /* first detect it then change to a scaled read and f2i */
2227 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2228 tmp2 = tmp;
2229
2230 /* extract the DATA_FORMAT */
2231 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2232 LLVMConstInt(ctx->i32, 6, false), false);
2233
2234 /* is the DATA_FORMAT == 8_8_8_8 */
2235 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2236
2237 if (stype == GLSL_TYPE_UINT)
2238 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2239 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2240 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2241 else
2242 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2243 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2244 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2245
2246 /* replace the NUM FORMAT in the descriptor */
2247 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2248 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2249
2250 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2251
2252 /* don't modify the coordinates for this case */
2253 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2254 }
2255 args->addr = coord;
2256 result = ac_build_image_opcode(ctx, args);
2257
2258 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2259 LLVMValueRef tmp, tmp2;
2260
2261 /* if the cube workaround is in place, f2i the result. */
2262 for (c = 0; c < 4; c++) {
2263 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2264 if (stype == GLSL_TYPE_UINT)
2265 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2266 else
2267 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2268 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2269 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2270 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2271 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2272 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2273 }
2274 }
2275 return result;
2276 }
2277
2278 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2279 const nir_tex_instr *instr,
2280 bool lod_is_zero,
2281 struct ac_image_args *args)
2282 {
2283 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2284 return ac_build_buffer_load_format(&ctx->ac,
2285 args->resource,
2286 args->addr,
2287 ctx->ac.i32_0,
2288 true);
2289 }
2290
2291 args->opcode = ac_image_sample;
2292 args->compare = instr->is_shadow;
2293
2294 switch (instr->op) {
2295 case nir_texop_txf:
2296 case nir_texop_txf_ms:
2297 case nir_texop_samples_identical:
2298 args->opcode = lod_is_zero ||
2299 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2300 ac_image_load : ac_image_load_mip;
2301 args->compare = false;
2302 args->offset = false;
2303 break;
2304 case nir_texop_txb:
2305 args->bias = true;
2306 break;
2307 case nir_texop_txl:
2308 if (lod_is_zero)
2309 args->level_zero = true;
2310 else
2311 args->lod = true;
2312 break;
2313 case nir_texop_txs:
2314 case nir_texop_query_levels:
2315 args->opcode = ac_image_get_resinfo;
2316 break;
2317 case nir_texop_tex:
2318 if (ctx->stage != MESA_SHADER_FRAGMENT)
2319 args->level_zero = true;
2320 break;
2321 case nir_texop_txd:
2322 args->deriv = true;
2323 break;
2324 case nir_texop_tg4:
2325 args->opcode = ac_image_gather4;
2326 args->level_zero = true;
2327 break;
2328 case nir_texop_lod:
2329 args->opcode = ac_image_get_lod;
2330 args->compare = false;
2331 args->offset = false;
2332 break;
2333 default:
2334 break;
2335 }
2336
2337 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2338 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2339 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2340 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2341 }
2342 }
2343 return ac_build_image_opcode(&ctx->ac, args);
2344 }
2345
2346 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2347 nir_intrinsic_instr *instr)
2348 {
2349 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2350 unsigned desc_set = nir_intrinsic_desc_set(instr);
2351 unsigned binding = nir_intrinsic_binding(instr);
2352 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2353 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2354 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2355 unsigned base_offset = layout->binding[binding].offset;
2356 LLVMValueRef offset, stride;
2357
2358 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2359 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2360 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2361 layout->binding[binding].dynamic_offset_offset;
2362 desc_ptr = ctx->push_constants;
2363 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2364 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2365 } else
2366 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2367
2368 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2369 index = LLVMBuildMul(ctx->builder, index, stride, "");
2370 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2371
2372 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2373 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2374 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2375
2376 return desc_ptr;
2377 }
2378
2379 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2380 nir_intrinsic_instr *instr)
2381 {
2382 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2383 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2384
2385 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2386 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2387 return result;
2388 }
2389
2390 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2391 nir_intrinsic_instr *instr)
2392 {
2393 LLVMValueRef ptr, addr;
2394
2395 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2396 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2397
2398 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2399 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2400
2401 return LLVMBuildLoad(ctx->builder, ptr, "");
2402 }
2403
2404 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2405 const nir_intrinsic_instr *instr)
2406 {
2407 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2408
2409 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2410 }
2411 static void visit_store_ssbo(struct ac_nir_context *ctx,
2412 nir_intrinsic_instr *instr)
2413 {
2414 const char *store_name;
2415 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2416 LLVMTypeRef data_type = ctx->ac.f32;
2417 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2418 int components_32bit = elem_size_mult * instr->num_components;
2419 unsigned writemask = nir_intrinsic_write_mask(instr);
2420 LLVMValueRef base_data, base_offset;
2421 LLVMValueRef params[6];
2422
2423 params[1] = ctx->abi->load_ssbo(ctx->abi,
2424 get_src(ctx, instr->src[1]), true);
2425 params[2] = ctx->ac.i32_0; /* vindex */
2426 params[4] = ctx->ac.i1false; /* glc */
2427 params[5] = ctx->ac.i1false; /* slc */
2428
2429 if (components_32bit > 1)
2430 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2431
2432 base_data = ac_to_float(&ctx->ac, src_data);
2433 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2434 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2435 data_type, "");
2436 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2437 while (writemask) {
2438 int start, count;
2439 LLVMValueRef data;
2440 LLVMValueRef offset;
2441 LLVMValueRef tmp;
2442 u_bit_scan_consecutive_range(&writemask, &start, &count);
2443
2444 /* Due to an LLVM limitation, split 3-element writes
2445 * into a 2-element and a 1-element write. */
2446 if (count == 3) {
2447 writemask |= 1 << (start + 2);
2448 count = 2;
2449 }
2450
2451 start *= elem_size_mult;
2452 count *= elem_size_mult;
2453
2454 if (count > 4) {
2455 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2456 count = 4;
2457 }
2458
2459 if (count == 4) {
2460 store_name = "llvm.amdgcn.buffer.store.v4f32";
2461 data = base_data;
2462 } else if (count == 2) {
2463 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2464 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2465 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2466 ctx->ac.i32_0, "");
2467
2468 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2469 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2470 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2471 ctx->ac.i32_1, "");
2472 store_name = "llvm.amdgcn.buffer.store.v2f32";
2473
2474 } else {
2475 assert(count == 1);
2476 if (ac_get_llvm_num_components(base_data) > 1)
2477 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2478 LLVMConstInt(ctx->ac.i32, start, false), "");
2479 else
2480 data = base_data;
2481 store_name = "llvm.amdgcn.buffer.store.f32";
2482 }
2483
2484 offset = base_offset;
2485 if (start != 0) {
2486 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2487 }
2488 params[0] = data;
2489 params[3] = offset;
2490 ac_build_intrinsic(&ctx->ac, store_name,
2491 ctx->ac.voidt, params, 6, 0);
2492 }
2493 }
2494
2495 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2496 const nir_intrinsic_instr *instr)
2497 {
2498 const char *name;
2499 LLVMValueRef params[6];
2500 int arg_count = 0;
2501
2502 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2503 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2504 }
2505 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2506 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2507 get_src(ctx, instr->src[0]),
2508 true);
2509 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2510 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2511 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2512
2513 switch (instr->intrinsic) {
2514 case nir_intrinsic_ssbo_atomic_add:
2515 name = "llvm.amdgcn.buffer.atomic.add";
2516 break;
2517 case nir_intrinsic_ssbo_atomic_imin:
2518 name = "llvm.amdgcn.buffer.atomic.smin";
2519 break;
2520 case nir_intrinsic_ssbo_atomic_umin:
2521 name = "llvm.amdgcn.buffer.atomic.umin";
2522 break;
2523 case nir_intrinsic_ssbo_atomic_imax:
2524 name = "llvm.amdgcn.buffer.atomic.smax";
2525 break;
2526 case nir_intrinsic_ssbo_atomic_umax:
2527 name = "llvm.amdgcn.buffer.atomic.umax";
2528 break;
2529 case nir_intrinsic_ssbo_atomic_and:
2530 name = "llvm.amdgcn.buffer.atomic.and";
2531 break;
2532 case nir_intrinsic_ssbo_atomic_or:
2533 name = "llvm.amdgcn.buffer.atomic.or";
2534 break;
2535 case nir_intrinsic_ssbo_atomic_xor:
2536 name = "llvm.amdgcn.buffer.atomic.xor";
2537 break;
2538 case nir_intrinsic_ssbo_atomic_exchange:
2539 name = "llvm.amdgcn.buffer.atomic.swap";
2540 break;
2541 case nir_intrinsic_ssbo_atomic_comp_swap:
2542 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2543 break;
2544 default:
2545 abort();
2546 }
2547
2548 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2549 }
2550
2551 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2552 const nir_intrinsic_instr *instr)
2553 {
2554 LLVMValueRef results[2];
2555 int load_components;
2556 int num_components = instr->num_components;
2557 if (instr->dest.ssa.bit_size == 64)
2558 num_components *= 2;
2559
2560 for (int i = 0; i < num_components; i += load_components) {
2561 load_components = MIN2(num_components - i, 4);
2562 const char *load_name;
2563 LLVMTypeRef data_type = ctx->ac.f32;
2564 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2565 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2566
2567 if (load_components == 3)
2568 data_type = LLVMVectorType(ctx->ac.f32, 4);
2569 else if (load_components > 1)
2570 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2571
2572 if (load_components >= 3)
2573 load_name = "llvm.amdgcn.buffer.load.v4f32";
2574 else if (load_components == 2)
2575 load_name = "llvm.amdgcn.buffer.load.v2f32";
2576 else if (load_components == 1)
2577 load_name = "llvm.amdgcn.buffer.load.f32";
2578 else
2579 unreachable("unhandled number of components");
2580
2581 LLVMValueRef params[] = {
2582 ctx->abi->load_ssbo(ctx->abi,
2583 get_src(ctx, instr->src[0]),
2584 false),
2585 ctx->ac.i32_0,
2586 offset,
2587 ctx->ac.i1false,
2588 ctx->ac.i1false,
2589 };
2590
2591 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2592
2593 }
2594
2595 assume(results[0]);
2596 LLVMValueRef ret = results[0];
2597 if (num_components > 4 || num_components == 3) {
2598 LLVMValueRef masks[] = {
2599 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2600 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2601 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2602 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2603 };
2604
2605 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2606 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2607 results[num_components > 4 ? 1 : 0], swizzle, "");
2608 }
2609
2610 return LLVMBuildBitCast(ctx->ac.builder, ret,
2611 get_def_type(ctx, &instr->dest.ssa), "");
2612 }
2613
2614 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2615 const nir_intrinsic_instr *instr)
2616 {
2617 LLVMValueRef ret;
2618 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2619 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2620 int num_components = instr->num_components;
2621
2622 if (ctx->abi->load_ubo)
2623 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2624
2625 if (instr->dest.ssa.bit_size == 64)
2626 num_components *= 2;
2627
2628 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2629 NULL, 0, false, false, true, true);
2630 ret = trim_vector(&ctx->ac, ret, num_components);
2631 return LLVMBuildBitCast(ctx->ac.builder, ret,
2632 get_def_type(ctx, &instr->dest.ssa), "");
2633 }
2634
2635 static void
2636 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2637 bool vs_in, unsigned *vertex_index_out,
2638 LLVMValueRef *vertex_index_ref,
2639 unsigned *const_out, LLVMValueRef *indir_out)
2640 {
2641 unsigned const_offset = 0;
2642 nir_deref *tail = &deref->deref;
2643 LLVMValueRef offset = NULL;
2644
2645 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2646 tail = tail->child;
2647 nir_deref_array *deref_array = nir_deref_as_array(tail);
2648 if (vertex_index_out)
2649 *vertex_index_out = deref_array->base_offset;
2650
2651 if (vertex_index_ref) {
2652 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2653 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2654 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2655 }
2656 *vertex_index_ref = vtx;
2657 }
2658 }
2659
2660 if (deref->var->data.compact) {
2661 assert(tail->child->deref_type == nir_deref_type_array);
2662 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2663 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2664 /* We always lower indirect dereferences for "compact" array vars. */
2665 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2666
2667 const_offset = deref_array->base_offset;
2668 goto out;
2669 }
2670
2671 while (tail->child != NULL) {
2672 const struct glsl_type *parent_type = tail->type;
2673 tail = tail->child;
2674
2675 if (tail->deref_type == nir_deref_type_array) {
2676 nir_deref_array *deref_array = nir_deref_as_array(tail);
2677 LLVMValueRef index, stride, local_offset;
2678 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2679
2680 const_offset += size * deref_array->base_offset;
2681 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2682 continue;
2683
2684 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2685 index = get_src(ctx, deref_array->indirect);
2686 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2687 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2688
2689 if (offset)
2690 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2691 else
2692 offset = local_offset;
2693 } else if (tail->deref_type == nir_deref_type_struct) {
2694 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2695
2696 for (unsigned i = 0; i < deref_struct->index; i++) {
2697 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2698 const_offset += glsl_count_attribute_slots(ft, vs_in);
2699 }
2700 } else
2701 unreachable("unsupported deref type");
2702
2703 }
2704 out:
2705 if (const_offset && offset)
2706 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2707 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2708 "");
2709
2710 *const_out = const_offset;
2711 *indir_out = offset;
2712 }
2713
2714
2715 /* The offchip buffer layout for TCS->TES is
2716 *
2717 * - attribute 0 of patch 0 vertex 0
2718 * - attribute 0 of patch 0 vertex 1
2719 * - attribute 0 of patch 0 vertex 2
2720 * ...
2721 * - attribute 0 of patch 1 vertex 0
2722 * - attribute 0 of patch 1 vertex 1
2723 * ...
2724 * - attribute 1 of patch 0 vertex 0
2725 * - attribute 1 of patch 0 vertex 1
2726 * ...
2727 * - per patch attribute 0 of patch 0
2728 * - per patch attribute 0 of patch 1
2729 * ...
2730 *
2731 * Note that every attribute has 4 components.
2732 */
2733 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2734 LLVMValueRef vertex_index,
2735 LLVMValueRef param_index)
2736 {
2737 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2738 LLVMValueRef param_stride, constant16;
2739 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2740
2741 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2742 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2743 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2744 num_patches, "");
2745
2746 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2747 if (vertex_index) {
2748 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2749 vertices_per_patch, "");
2750
2751 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2752 vertex_index, "");
2753
2754 param_stride = total_vertices;
2755 } else {
2756 base_addr = rel_patch_id;
2757 param_stride = num_patches;
2758 }
2759
2760 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2761 LLVMBuildMul(ctx->builder, param_index,
2762 param_stride, ""), "");
2763
2764 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2765
2766 if (!vertex_index) {
2767 LLVMValueRef patch_data_offset =
2768 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2769
2770 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2771 patch_data_offset, "");
2772 }
2773 return base_addr;
2774 }
2775
2776 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2777 unsigned param,
2778 unsigned const_index,
2779 bool is_compact,
2780 LLVMValueRef vertex_index,
2781 LLVMValueRef indir_index)
2782 {
2783 LLVMValueRef param_index;
2784
2785 if (indir_index)
2786 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2787 indir_index, "");
2788 else {
2789 if (const_index && !is_compact)
2790 param += const_index;
2791 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2792 }
2793 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2794 }
2795
2796 static void
2797 mark_tess_output(struct nir_to_llvm_context *ctx,
2798 bool is_patch, uint32_t param)
2799
2800 {
2801 if (is_patch) {
2802 ctx->tess_patch_outputs_written |= (1ull << param);
2803 } else
2804 ctx->tess_outputs_written |= (1ull << param);
2805 }
2806
2807 static LLVMValueRef
2808 get_dw_address(struct nir_to_llvm_context *ctx,
2809 LLVMValueRef dw_addr,
2810 unsigned param,
2811 unsigned const_index,
2812 bool compact_const_index,
2813 LLVMValueRef vertex_index,
2814 LLVMValueRef stride,
2815 LLVMValueRef indir_index)
2816
2817 {
2818
2819 if (vertex_index) {
2820 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2821 LLVMBuildMul(ctx->builder,
2822 vertex_index,
2823 stride, ""), "");
2824 }
2825
2826 if (indir_index)
2827 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2828 LLVMBuildMul(ctx->builder, indir_index,
2829 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2830 else if (const_index && !compact_const_index)
2831 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2832 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2833
2834 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2835 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2836
2837 if (const_index && compact_const_index)
2838 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2839 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2840 return dw_addr;
2841 }
2842
2843 static LLVMValueRef
2844 load_tcs_varyings(struct ac_shader_abi *abi,
2845 LLVMValueRef vertex_index,
2846 LLVMValueRef indir_index,
2847 unsigned const_index,
2848 unsigned location,
2849 unsigned driver_location,
2850 unsigned component,
2851 unsigned num_components,
2852 bool is_patch,
2853 bool is_compact,
2854 bool load_input)
2855 {
2856 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2857 LLVMValueRef dw_addr, stride;
2858 LLVMValueRef value[4], result;
2859 unsigned param = shader_io_get_unique_index(location);
2860
2861 if (load_input) {
2862 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2863 dw_addr = get_tcs_in_current_patch_offset(ctx);
2864 } else {
2865 if (!is_patch) {
2866 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2867 dw_addr = get_tcs_out_current_patch_offset(ctx);
2868 } else {
2869 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2870 stride = NULL;
2871 }
2872 }
2873
2874 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2875 indir_index);
2876
2877 for (unsigned i = 0; i < num_components + component; i++) {
2878 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2879 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2880 ctx->ac.i32_1, "");
2881 }
2882 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2883 return result;
2884 }
2885
2886 static void
2887 store_tcs_output(struct ac_shader_abi *abi,
2888 LLVMValueRef vertex_index,
2889 LLVMValueRef param_index,
2890 unsigned const_index,
2891 unsigned location,
2892 unsigned driver_location,
2893 LLVMValueRef src,
2894 unsigned component,
2895 bool is_patch,
2896 bool is_compact,
2897 unsigned writemask)
2898 {
2899 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2900 LLVMValueRef dw_addr;
2901 LLVMValueRef stride = NULL;
2902 LLVMValueRef buf_addr = NULL;
2903 unsigned param;
2904 bool store_lds = true;
2905
2906 if (is_patch) {
2907 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2908 store_lds = false;
2909 } else {
2910 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2911 store_lds = false;
2912 }
2913
2914 param = shader_io_get_unique_index(location);
2915 if (location == VARYING_SLOT_CLIP_DIST0 &&
2916 is_compact && const_index > 3) {
2917 const_index -= 3;
2918 param++;
2919 }
2920
2921 if (!is_patch) {
2922 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2923 dw_addr = get_tcs_out_current_patch_offset(ctx);
2924 } else {
2925 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2926 }
2927
2928 mark_tess_output(ctx, is_patch, param);
2929
2930 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2931 param_index);
2932 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2933 vertex_index, param_index);
2934
2935 bool is_tess_factor = false;
2936 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2937 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2938 is_tess_factor = true;
2939
2940 unsigned base = is_compact ? const_index : 0;
2941 for (unsigned chan = 0; chan < 8; chan++) {
2942 if (!(writemask & (1 << chan)))
2943 continue;
2944 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2945
2946 if (store_lds || is_tess_factor)
2947 ac_lds_store(&ctx->ac, dw_addr, value);
2948
2949 if (!is_tess_factor && writemask != 0xF)
2950 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2951 buf_addr, ctx->oc_lds,
2952 4 * (base + chan), 1, 0, true, false);
2953
2954 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2955 ctx->ac.i32_1, "");
2956 }
2957
2958 if (writemask == 0xF) {
2959 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2960 buf_addr, ctx->oc_lds,
2961 (base * 4), 1, 0, true, false);
2962 }
2963 }
2964
2965 static LLVMValueRef
2966 load_tes_input(struct ac_shader_abi *abi,
2967 LLVMValueRef vertex_index,
2968 LLVMValueRef param_index,
2969 unsigned const_index,
2970 unsigned location,
2971 unsigned driver_location,
2972 unsigned component,
2973 unsigned num_components,
2974 bool is_patch,
2975 bool is_compact,
2976 bool load_input)
2977 {
2978 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2979 LLVMValueRef buf_addr;
2980 LLVMValueRef result;
2981 unsigned param = shader_io_get_unique_index(location);
2982
2983 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2984 const_index -= 3;
2985 param++;
2986 }
2987
2988 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2989 is_compact, vertex_index, param_index);
2990
2991 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2992 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2993
2994 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2995 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2996 result = trim_vector(&ctx->ac, result, num_components);
2997 return result;
2998 }
2999
3000 static LLVMValueRef
3001 load_gs_input(struct ac_shader_abi *abi,
3002 unsigned location,
3003 unsigned driver_location,
3004 unsigned component,
3005 unsigned num_components,
3006 unsigned vertex_index,
3007 unsigned const_index,
3008 LLVMTypeRef type)
3009 {
3010 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3011 LLVMValueRef vtx_offset;
3012 LLVMValueRef args[9];
3013 unsigned param, vtx_offset_param;
3014 LLVMValueRef value[4], result;
3015
3016 vtx_offset_param = vertex_index;
3017 assert(vtx_offset_param < 6);
3018 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3019 LLVMConstInt(ctx->ac.i32, 4, false), "");
3020
3021 param = shader_io_get_unique_index(location);
3022
3023 for (unsigned i = component; i < num_components + component; i++) {
3024 if (ctx->ac.chip_class >= GFX9) {
3025 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3026 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3027 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3028 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3029 } else {
3030 args[0] = ctx->esgs_ring;
3031 args[1] = vtx_offset;
3032 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3033 args[3] = ctx->ac.i32_0;
3034 args[4] = ctx->ac.i32_1; /* OFFEN */
3035 args[5] = ctx->ac.i32_0; /* IDXEN */
3036 args[6] = ctx->ac.i32_1; /* GLC */
3037 args[7] = ctx->ac.i32_0; /* SLC */
3038 args[8] = ctx->ac.i32_0; /* TFE */
3039
3040 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3041 ctx->ac.i32, args, 9,
3042 AC_FUNC_ATTR_READONLY |
3043 AC_FUNC_ATTR_LEGACY);
3044 }
3045 }
3046 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3047
3048 return result;
3049 }
3050
3051 static LLVMValueRef
3052 build_gep_for_deref(struct ac_nir_context *ctx,
3053 nir_deref_var *deref)
3054 {
3055 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3056 assert(entry->data);
3057 LLVMValueRef val = entry->data;
3058 nir_deref *tail = deref->deref.child;
3059 while (tail != NULL) {
3060 LLVMValueRef offset;
3061 switch (tail->deref_type) {
3062 case nir_deref_type_array: {
3063 nir_deref_array *array = nir_deref_as_array(tail);
3064 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3065 if (array->deref_array_type ==
3066 nir_deref_array_type_indirect) {
3067 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3068 get_src(ctx,
3069 array->indirect),
3070 "");
3071 }
3072 break;
3073 }
3074 case nir_deref_type_struct: {
3075 nir_deref_struct *deref_struct =
3076 nir_deref_as_struct(tail);
3077 offset = LLVMConstInt(ctx->ac.i32,
3078 deref_struct->index, 0);
3079 break;
3080 }
3081 default:
3082 unreachable("bad deref type");
3083 }
3084 val = ac_build_gep0(&ctx->ac, val, offset);
3085 tail = tail->child;
3086 }
3087 return val;
3088 }
3089
3090 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3091 nir_intrinsic_instr *instr,
3092 bool load_inputs)
3093 {
3094 LLVMValueRef result;
3095 LLVMValueRef vertex_index = NULL;
3096 LLVMValueRef indir_index = NULL;
3097 unsigned const_index = 0;
3098 unsigned location = instr->variables[0]->var->data.location;
3099 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3100 const bool is_patch = instr->variables[0]->var->data.patch;
3101 const bool is_compact = instr->variables[0]->var->data.compact;
3102
3103 get_deref_offset(ctx, instr->variables[0],
3104 false, NULL, is_patch ? NULL : &vertex_index,
3105 &const_index, &indir_index);
3106
3107 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3108 const_index, location, driver_location,
3109 instr->variables[0]->var->data.location_frac,
3110 instr->num_components,
3111 is_patch, is_compact, load_inputs);
3112 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3113 }
3114
3115 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3116 nir_intrinsic_instr *instr)
3117 {
3118 LLVMValueRef values[8];
3119 int idx = instr->variables[0]->var->data.driver_location;
3120 int ve = instr->dest.ssa.num_components;
3121 unsigned comp = instr->variables[0]->var->data.location_frac;
3122 LLVMValueRef indir_index;
3123 LLVMValueRef ret;
3124 unsigned const_index;
3125 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3126 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3127 instr->variables[0]->var->data.mode == nir_var_shader_in;
3128 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3129 &const_index, &indir_index);
3130
3131 if (instr->dest.ssa.bit_size == 64)
3132 ve *= 2;
3133
3134 switch (instr->variables[0]->var->data.mode) {
3135 case nir_var_shader_in:
3136 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3137 ctx->stage == MESA_SHADER_TESS_EVAL) {
3138 return load_tess_varyings(ctx, instr, true);
3139 }
3140
3141 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3142 LLVMValueRef indir_index;
3143 unsigned const_index, vertex_index;
3144 get_deref_offset(ctx, instr->variables[0],
3145 false, &vertex_index, NULL,
3146 &const_index, &indir_index);
3147 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3148 instr->variables[0]->var->data.driver_location,
3149 instr->variables[0]->var->data.location_frac, ve,
3150 vertex_index, const_index,
3151 nir2llvmtype(ctx, instr->variables[0]->var->type));
3152 }
3153
3154 for (unsigned chan = comp; chan < ve + comp; chan++) {
3155 if (indir_index) {
3156 unsigned count = glsl_count_attribute_slots(
3157 instr->variables[0]->var->type,
3158 ctx->stage == MESA_SHADER_VERTEX);
3159 count -= chan / 4;
3160 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3161 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3162 stride, false, true);
3163
3164 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3165 tmp_vec,
3166 indir_index, "");
3167 } else
3168 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3169 }
3170 break;
3171 case nir_var_local:
3172 for (unsigned chan = 0; chan < ve; chan++) {
3173 if (indir_index) {
3174 unsigned count = glsl_count_attribute_slots(
3175 instr->variables[0]->var->type, false);
3176 count -= chan / 4;
3177 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3178 &ctx->ac, ctx->locals + idx + chan, count,
3179 stride, true, true);
3180
3181 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3182 tmp_vec,
3183 indir_index, "");
3184 } else {
3185 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3186 }
3187 }
3188 break;
3189 case nir_var_shared: {
3190 LLVMValueRef address = build_gep_for_deref(ctx,
3191 instr->variables[0]);
3192 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3193 return LLVMBuildBitCast(ctx->ac.builder, val,
3194 get_def_type(ctx, &instr->dest.ssa),
3195 "");
3196 }
3197 case nir_var_shader_out:
3198 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3199 return load_tess_varyings(ctx, instr, false);
3200 }
3201
3202 for (unsigned chan = comp; chan < ve + comp; chan++) {
3203 if (indir_index) {
3204 unsigned count = glsl_count_attribute_slots(
3205 instr->variables[0]->var->type, false);
3206 count -= chan / 4;
3207 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3208 &ctx->ac, ctx->outputs + idx + chan, count,
3209 stride, true, true);
3210
3211 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3212 tmp_vec,
3213 indir_index, "");
3214 } else {
3215 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3216 ctx->outputs[idx + chan + const_index * stride],
3217 "");
3218 }
3219 }
3220 break;
3221 default:
3222 unreachable("unhandle variable mode");
3223 }
3224 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3225 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3226 }
3227
3228 static void
3229 visit_store_var(struct ac_nir_context *ctx,
3230 nir_intrinsic_instr *instr)
3231 {
3232 LLVMValueRef temp_ptr, value;
3233 int idx = instr->variables[0]->var->data.driver_location;
3234 unsigned comp = instr->variables[0]->var->data.location_frac;
3235 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3236 int writemask = instr->const_index[0] << comp;
3237 LLVMValueRef indir_index;
3238 unsigned const_index;
3239 get_deref_offset(ctx, instr->variables[0], false,
3240 NULL, NULL, &const_index, &indir_index);
3241
3242 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3243 int old_writemask = writemask;
3244
3245 src = LLVMBuildBitCast(ctx->ac.builder, src,
3246 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3247 "");
3248
3249 writemask = 0;
3250 for (unsigned chan = 0; chan < 4; chan++) {
3251 if (old_writemask & (1 << chan))
3252 writemask |= 3u << (2 * chan);
3253 }
3254 }
3255
3256 switch (instr->variables[0]->var->data.mode) {
3257 case nir_var_shader_out:
3258
3259 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3260 LLVMValueRef vertex_index = NULL;
3261 LLVMValueRef indir_index = NULL;
3262 unsigned const_index = 0;
3263 const unsigned location = instr->variables[0]->var->data.location;
3264 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3265 const unsigned comp = instr->variables[0]->var->data.location_frac;
3266 const bool is_patch = instr->variables[0]->var->data.patch;
3267 const bool is_compact = instr->variables[0]->var->data.compact;
3268
3269 get_deref_offset(ctx, instr->variables[0],
3270 false, NULL, is_patch ? NULL : &vertex_index,
3271 &const_index, &indir_index);
3272
3273 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3274 const_index, location, driver_location,
3275 src, comp, is_patch, is_compact, writemask);
3276 return;
3277 }
3278
3279 for (unsigned chan = 0; chan < 8; chan++) {
3280 int stride = 4;
3281 if (!(writemask & (1 << chan)))
3282 continue;
3283
3284 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3285
3286 if (instr->variables[0]->var->data.compact)
3287 stride = 1;
3288 if (indir_index) {
3289 unsigned count = glsl_count_attribute_slots(
3290 instr->variables[0]->var->type, false);
3291 count -= chan / 4;
3292 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3293 &ctx->ac, ctx->outputs + idx + chan, count,
3294 stride, true, true);
3295
3296 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3297 value, indir_index, "");
3298 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3299 count, stride, tmp_vec);
3300
3301 } else {
3302 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3303
3304 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3305 }
3306 }
3307 break;
3308 case nir_var_local:
3309 for (unsigned chan = 0; chan < 8; chan++) {
3310 if (!(writemask & (1 << chan)))
3311 continue;
3312
3313 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->locals + idx + chan, count,
3320 4, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3325 count, 4, tmp_vec);
3326 } else {
3327 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3328
3329 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3330 }
3331 }
3332 break;
3333 case nir_var_shared: {
3334 int writemask = instr->const_index[0];
3335 LLVMValueRef address = build_gep_for_deref(ctx,
3336 instr->variables[0]);
3337 LLVMValueRef val = get_src(ctx, instr->src[0]);
3338 unsigned components =
3339 glsl_get_vector_elements(
3340 nir_deref_tail(&instr->variables[0]->deref)->type);
3341 if (writemask == (1 << components) - 1) {
3342 val = LLVMBuildBitCast(
3343 ctx->ac.builder, val,
3344 LLVMGetElementType(LLVMTypeOf(address)), "");
3345 LLVMBuildStore(ctx->ac.builder, val, address);
3346 } else {
3347 for (unsigned chan = 0; chan < 4; chan++) {
3348 if (!(writemask & (1 << chan)))
3349 continue;
3350 LLVMValueRef ptr =
3351 LLVMBuildStructGEP(ctx->ac.builder,
3352 address, chan, "");
3353 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3354 chan);
3355 src = LLVMBuildBitCast(
3356 ctx->ac.builder, src,
3357 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3358 LLVMBuildStore(ctx->ac.builder, src, ptr);
3359 }
3360 }
3361 break;
3362 }
3363 default:
3364 break;
3365 }
3366 }
3367
3368 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3369 {
3370 switch (dim) {
3371 case GLSL_SAMPLER_DIM_BUF:
3372 return 1;
3373 case GLSL_SAMPLER_DIM_1D:
3374 return array ? 2 : 1;
3375 case GLSL_SAMPLER_DIM_2D:
3376 return array ? 3 : 2;
3377 case GLSL_SAMPLER_DIM_MS:
3378 return array ? 4 : 3;
3379 case GLSL_SAMPLER_DIM_3D:
3380 case GLSL_SAMPLER_DIM_CUBE:
3381 return 3;
3382 case GLSL_SAMPLER_DIM_RECT:
3383 case GLSL_SAMPLER_DIM_SUBPASS:
3384 return 2;
3385 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3386 return 3;
3387 default:
3388 break;
3389 }
3390 return 0;
3391 }
3392
3393
3394
3395 /* Adjust the sample index according to FMASK.
3396 *
3397 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3398 * which is the identity mapping. Each nibble says which physical sample
3399 * should be fetched to get that sample.
3400 *
3401 * For example, 0x11111100 means there are only 2 samples stored and
3402 * the second sample covers 3/4 of the pixel. When reading samples 0
3403 * and 1, return physical sample 0 (determined by the first two 0s
3404 * in FMASK), otherwise return physical sample 1.
3405 *
3406 * The sample index should be adjusted as follows:
3407 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3408 */
3409 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3410 LLVMValueRef coord_x, LLVMValueRef coord_y,
3411 LLVMValueRef coord_z,
3412 LLVMValueRef sample_index,
3413 LLVMValueRef fmask_desc_ptr)
3414 {
3415 LLVMValueRef fmask_load_address[4];
3416 LLVMValueRef res;
3417
3418 fmask_load_address[0] = coord_x;
3419 fmask_load_address[1] = coord_y;
3420 if (coord_z) {
3421 fmask_load_address[2] = coord_z;
3422 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3423 }
3424
3425 struct ac_image_args args = {0};
3426
3427 args.opcode = ac_image_load;
3428 args.da = coord_z ? true : false;
3429 args.resource = fmask_desc_ptr;
3430 args.dmask = 0xf;
3431 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3432
3433 res = ac_build_image_opcode(ctx, &args);
3434
3435 res = ac_to_integer(ctx, res);
3436 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3437 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3438
3439 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3440 res,
3441 ctx->i32_0, "");
3442
3443 LLVMValueRef sample_index4 =
3444 LLVMBuildMul(ctx->builder, sample_index, four, "");
3445 LLVMValueRef shifted_fmask =
3446 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3447 LLVMValueRef final_sample =
3448 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3449
3450 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3451 * resource descriptor is 0 (invalid),
3452 */
3453 LLVMValueRef fmask_desc =
3454 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3455 ctx->v8i32, "");
3456
3457 LLVMValueRef fmask_word1 =
3458 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3459 ctx->i32_1, "");
3460
3461 LLVMValueRef word1_is_nonzero =
3462 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3463 fmask_word1, ctx->i32_0, "");
3464
3465 /* Replace the MSAA sample index. */
3466 sample_index =
3467 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3468 final_sample, sample_index, "");
3469 return sample_index;
3470 }
3471
3472 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3473 const nir_intrinsic_instr *instr)
3474 {
3475 const struct glsl_type *type = instr->variables[0]->var->type;
3476 if(instr->variables[0]->deref.child)
3477 type = instr->variables[0]->deref.child->type;
3478
3479 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3480 LLVMValueRef coords[4];
3481 LLVMValueRef masks[] = {
3482 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3483 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3484 };
3485 LLVMValueRef res;
3486 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3487
3488 int count;
3489 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3490 bool is_array = glsl_sampler_type_is_array(type);
3491 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3492 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3493 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3494 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3495 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3496 count = image_type_to_components_count(dim, is_array);
3497
3498 if (is_ms) {
3499 LLVMValueRef fmask_load_address[3];
3500 int chan;
3501
3502 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3503 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3504 if (is_array)
3505 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3506 else
3507 fmask_load_address[2] = NULL;
3508 if (add_frag_pos) {
3509 for (chan = 0; chan < 2; ++chan)
3510 fmask_load_address[chan] =
3511 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3512 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3513 ctx->ac.i32, ""), "");
3514 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3515 }
3516 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3517 fmask_load_address[0],
3518 fmask_load_address[1],
3519 fmask_load_address[2],
3520 sample_index,
3521 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3522 }
3523 if (count == 1 && !gfx9_1d) {
3524 if (instr->src[0].ssa->num_components)
3525 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3526 else
3527 res = src0;
3528 } else {
3529 int chan;
3530 if (is_ms)
3531 count--;
3532 for (chan = 0; chan < count; ++chan) {
3533 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3534 }
3535 if (add_frag_pos) {
3536 for (chan = 0; chan < 2; ++chan)
3537 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3538 ctx->ac.i32, ""), "");
3539 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3540 count++;
3541 }
3542
3543 if (gfx9_1d) {
3544 if (is_array) {
3545 coords[2] = coords[1];
3546 coords[1] = ctx->ac.i32_0;
3547 } else
3548 coords[1] = ctx->ac.i32_0;
3549 count++;
3550 }
3551
3552 if (is_ms) {
3553 coords[count] = sample_index;
3554 count++;
3555 }
3556
3557 if (count == 3) {
3558 coords[3] = LLVMGetUndef(ctx->ac.i32);
3559 count = 4;
3560 }
3561 res = ac_build_gather_values(&ctx->ac, coords, count);
3562 }
3563 return res;
3564 }
3565
3566 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3567 const nir_intrinsic_instr *instr)
3568 {
3569 LLVMValueRef params[7];
3570 LLVMValueRef res;
3571 char intrinsic_name[64];
3572 const nir_variable *var = instr->variables[0]->var;
3573 const struct glsl_type *type = var->type;
3574
3575 if(instr->variables[0]->deref.child)
3576 type = instr->variables[0]->deref.child->type;
3577
3578 type = glsl_without_array(type);
3579 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3580 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3581 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3582 ctx->ac.i32_0, ""); /* vindex */
3583 params[2] = ctx->ac.i32_0; /* voffset */
3584 params[3] = ctx->ac.i1false; /* glc */
3585 params[4] = ctx->ac.i1false; /* slc */
3586 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3587 params, 5, 0);
3588
3589 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3590 res = ac_to_integer(&ctx->ac, res);
3591 } else {
3592 bool is_da = glsl_sampler_type_is_array(type) ||
3593 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3594 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3595 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3596 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3597 LLVMValueRef glc = ctx->ac.i1false;
3598 LLVMValueRef slc = ctx->ac.i1false;
3599
3600 params[0] = get_image_coords(ctx, instr);
3601 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3602 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3603 if (HAVE_LLVM <= 0x0309) {
3604 params[3] = ctx->ac.i1false; /* r128 */
3605 params[4] = da;
3606 params[5] = glc;
3607 params[6] = slc;
3608 } else {
3609 LLVMValueRef lwe = ctx->ac.i1false;
3610 params[3] = glc;
3611 params[4] = slc;
3612 params[5] = lwe;
3613 params[6] = da;
3614 }
3615
3616 ac_get_image_intr_name("llvm.amdgcn.image.load",
3617 ctx->ac.v4f32, /* vdata */
3618 LLVMTypeOf(params[0]), /* coords */
3619 LLVMTypeOf(params[1]), /* rsrc */
3620 intrinsic_name, sizeof(intrinsic_name));
3621
3622 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3623 params, 7, AC_FUNC_ATTR_READONLY);
3624 }
3625 return ac_to_integer(&ctx->ac, res);
3626 }
3627
3628 static void visit_image_store(struct ac_nir_context *ctx,
3629 nir_intrinsic_instr *instr)
3630 {
3631 LLVMValueRef params[8];
3632 char intrinsic_name[64];
3633 const nir_variable *var = instr->variables[0]->var;
3634 const struct glsl_type *type = glsl_without_array(var->type);
3635 LLVMValueRef glc = ctx->ac.i1false;
3636 bool force_glc = ctx->ac.chip_class == SI;
3637 if (force_glc)
3638 glc = ctx->ac.i1true;
3639
3640 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3641 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3642 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3643 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3644 ctx->ac.i32_0, ""); /* vindex */
3645 params[3] = ctx->ac.i32_0; /* voffset */
3646 params[4] = glc; /* glc */
3647 params[5] = ctx->ac.i1false; /* slc */
3648 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3649 params, 6, 0);
3650 } else {
3651 bool is_da = glsl_sampler_type_is_array(type) ||
3652 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3653 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3654 LLVMValueRef slc = ctx->ac.i1false;
3655
3656 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3657 params[1] = get_image_coords(ctx, instr); /* coords */
3658 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3659 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3660 if (HAVE_LLVM <= 0x0309) {
3661 params[4] = ctx->ac.i1false; /* r128 */
3662 params[5] = da;
3663 params[6] = glc;
3664 params[7] = slc;
3665 } else {
3666 LLVMValueRef lwe = ctx->ac.i1false;
3667 params[4] = glc;
3668 params[5] = slc;
3669 params[6] = lwe;
3670 params[7] = da;
3671 }
3672
3673 ac_get_image_intr_name("llvm.amdgcn.image.store",
3674 LLVMTypeOf(params[0]), /* vdata */
3675 LLVMTypeOf(params[1]), /* coords */
3676 LLVMTypeOf(params[2]), /* rsrc */
3677 intrinsic_name, sizeof(intrinsic_name));
3678
3679 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3680 params, 8, 0);
3681 }
3682
3683 }
3684
3685 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3686 const nir_intrinsic_instr *instr)
3687 {
3688 LLVMValueRef params[7];
3689 int param_count = 0;
3690 const nir_variable *var = instr->variables[0]->var;
3691
3692 const char *atomic_name;
3693 char intrinsic_name[41];
3694 const struct glsl_type *type = glsl_without_array(var->type);
3695 MAYBE_UNUSED int length;
3696
3697 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3698
3699 switch (instr->intrinsic) {
3700 case nir_intrinsic_image_atomic_add:
3701 atomic_name = "add";
3702 break;
3703 case nir_intrinsic_image_atomic_min:
3704 atomic_name = is_unsigned ? "umin" : "smin";
3705 break;
3706 case nir_intrinsic_image_atomic_max:
3707 atomic_name = is_unsigned ? "umax" : "smax";
3708 break;
3709 case nir_intrinsic_image_atomic_and:
3710 atomic_name = "and";
3711 break;
3712 case nir_intrinsic_image_atomic_or:
3713 atomic_name = "or";
3714 break;
3715 case nir_intrinsic_image_atomic_xor:
3716 atomic_name = "xor";
3717 break;
3718 case nir_intrinsic_image_atomic_exchange:
3719 atomic_name = "swap";
3720 break;
3721 case nir_intrinsic_image_atomic_comp_swap:
3722 atomic_name = "cmpswap";
3723 break;
3724 default:
3725 abort();
3726 }
3727
3728 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3729 params[param_count++] = get_src(ctx, instr->src[3]);
3730 params[param_count++] = get_src(ctx, instr->src[2]);
3731
3732 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3733 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3734 NULL, true, true);
3735 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3736 ctx->ac.i32_0, ""); /* vindex */
3737 params[param_count++] = ctx->ac.i32_0; /* voffset */
3738 params[param_count++] = ctx->ac.i1false; /* slc */
3739
3740 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3741 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3742 } else {
3743 char coords_type[8];
3744
3745 bool da = glsl_sampler_type_is_array(type) ||
3746 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3747
3748 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3749 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3750 NULL, true, true);
3751 params[param_count++] = ctx->ac.i1false; /* r128 */
3752 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3753 params[param_count++] = ctx->ac.i1false; /* slc */
3754
3755 build_int_type_name(LLVMTypeOf(coords),
3756 coords_type, sizeof(coords_type));
3757
3758 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3759 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3760 }
3761
3762 assert(length < sizeof(intrinsic_name));
3763 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3764 }
3765
3766 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3767 const nir_intrinsic_instr *instr)
3768 {
3769 LLVMValueRef res;
3770 const nir_variable *var = instr->variables[0]->var;
3771 const struct glsl_type *type = instr->variables[0]->var->type;
3772 bool da = glsl_sampler_type_is_array(var->type) ||
3773 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3774 if(instr->variables[0]->deref.child)
3775 type = instr->variables[0]->deref.child->type;
3776
3777 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3778 return get_buffer_size(ctx,
3779 get_sampler_desc(ctx, instr->variables[0],
3780 AC_DESC_BUFFER, NULL, true, false), true);
3781
3782 struct ac_image_args args = { 0 };
3783
3784 args.da = da;
3785 args.dmask = 0xf;
3786 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3787 args.opcode = ac_image_get_resinfo;
3788 args.addr = ctx->ac.i32_0;
3789
3790 res = ac_build_image_opcode(&ctx->ac, &args);
3791
3792 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3793
3794 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3795 glsl_sampler_type_is_array(type)) {
3796 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3797 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3798 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3799 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3800 }
3801 if (ctx->ac.chip_class >= GFX9 &&
3802 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3803 glsl_sampler_type_is_array(type)) {
3804 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3805 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3806 ctx->ac.i32_1, "");
3807
3808 }
3809 return res;
3810 }
3811
3812 #define NOOP_WAITCNT 0xf7f
3813 #define LGKM_CNT 0x07f
3814 #define VM_CNT 0xf70
3815
3816 static void emit_membar(struct nir_to_llvm_context *ctx,
3817 const nir_intrinsic_instr *instr)
3818 {
3819 unsigned waitcnt = NOOP_WAITCNT;
3820
3821 switch (instr->intrinsic) {
3822 case nir_intrinsic_memory_barrier:
3823 case nir_intrinsic_group_memory_barrier:
3824 waitcnt &= VM_CNT & LGKM_CNT;
3825 break;
3826 case nir_intrinsic_memory_barrier_atomic_counter:
3827 case nir_intrinsic_memory_barrier_buffer:
3828 case nir_intrinsic_memory_barrier_image:
3829 waitcnt &= VM_CNT;
3830 break;
3831 case nir_intrinsic_memory_barrier_shared:
3832 waitcnt &= LGKM_CNT;
3833 break;
3834 default:
3835 break;
3836 }
3837 if (waitcnt != NOOP_WAITCNT)
3838 ac_build_waitcnt(&ctx->ac, waitcnt);
3839 }
3840
3841 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3842 {
3843 /* SI only (thanks to a hw bug workaround):
3844 * The real barrier instruction isn’t needed, because an entire patch
3845 * always fits into a single wave.
3846 */
3847 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3848 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3849 return;
3850 }
3851 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3852 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3853 }
3854
3855 static void emit_discard(struct ac_nir_context *ctx,
3856 const nir_intrinsic_instr *instr)
3857 {
3858 LLVMValueRef cond;
3859
3860 if (instr->intrinsic == nir_intrinsic_discard_if) {
3861 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3862 get_src(ctx, instr->src[0]),
3863 ctx->ac.i32_0, "");
3864 } else {
3865 assert(instr->intrinsic == nir_intrinsic_discard);
3866 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3867 }
3868
3869 ac_build_kill_if_false(&ctx->ac, cond);
3870 }
3871
3872 static LLVMValueRef
3873 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3874 {
3875 LLVMValueRef result;
3876 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3877 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3878 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3879
3880 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3881 }
3882
3883 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3884 const nir_intrinsic_instr *instr)
3885 {
3886 LLVMValueRef ptr, result;
3887 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3888 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3889
3890 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3891 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3892 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3893 ptr, src, src1,
3894 LLVMAtomicOrderingSequentiallyConsistent,
3895 LLVMAtomicOrderingSequentiallyConsistent,
3896 false);
3897 } else {
3898 LLVMAtomicRMWBinOp op;
3899 switch (instr->intrinsic) {
3900 case nir_intrinsic_var_atomic_add:
3901 op = LLVMAtomicRMWBinOpAdd;
3902 break;
3903 case nir_intrinsic_var_atomic_umin:
3904 op = LLVMAtomicRMWBinOpUMin;
3905 break;
3906 case nir_intrinsic_var_atomic_umax:
3907 op = LLVMAtomicRMWBinOpUMax;
3908 break;
3909 case nir_intrinsic_var_atomic_imin:
3910 op = LLVMAtomicRMWBinOpMin;
3911 break;
3912 case nir_intrinsic_var_atomic_imax:
3913 op = LLVMAtomicRMWBinOpMax;
3914 break;
3915 case nir_intrinsic_var_atomic_and:
3916 op = LLVMAtomicRMWBinOpAnd;
3917 break;
3918 case nir_intrinsic_var_atomic_or:
3919 op = LLVMAtomicRMWBinOpOr;
3920 break;
3921 case nir_intrinsic_var_atomic_xor:
3922 op = LLVMAtomicRMWBinOpXor;
3923 break;
3924 case nir_intrinsic_var_atomic_exchange:
3925 op = LLVMAtomicRMWBinOpXchg;
3926 break;
3927 default:
3928 return NULL;
3929 }
3930
3931 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3932 LLVMAtomicOrderingSequentiallyConsistent,
3933 false);
3934 }
3935 return result;
3936 }
3937
3938 #define INTERP_CENTER 0
3939 #define INTERP_CENTROID 1
3940 #define INTERP_SAMPLE 2
3941
3942 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3943 enum glsl_interp_mode interp, unsigned location)
3944 {
3945 switch (interp) {
3946 case INTERP_MODE_FLAT:
3947 default:
3948 return NULL;
3949 case INTERP_MODE_SMOOTH:
3950 case INTERP_MODE_NONE:
3951 if (location == INTERP_CENTER)
3952 return ctx->persp_center;
3953 else if (location == INTERP_CENTROID)
3954 return ctx->persp_centroid;
3955 else if (location == INTERP_SAMPLE)
3956 return ctx->persp_sample;
3957 break;
3958 case INTERP_MODE_NOPERSPECTIVE:
3959 if (location == INTERP_CENTER)
3960 return ctx->linear_center;
3961 else if (location == INTERP_CENTROID)
3962 return ctx->linear_centroid;
3963 else if (location == INTERP_SAMPLE)
3964 return ctx->linear_sample;
3965 break;
3966 }
3967 return NULL;
3968 }
3969
3970 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3971 LLVMValueRef sample_id)
3972 {
3973 LLVMValueRef result;
3974 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3975
3976 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3977 const_array(ctx->ac.v2f32, 64), "");
3978
3979 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3980 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3981
3982 return result;
3983 }
3984
3985 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3986 {
3987 LLVMValueRef values[2];
3988
3989 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3990 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3991 return ac_build_gather_values(&ctx->ac, values, 2);
3992 }
3993
3994 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3995 const nir_intrinsic_instr *instr)
3996 {
3997 LLVMValueRef result[4];
3998 LLVMValueRef interp_param, attr_number;
3999 unsigned location;
4000 unsigned chan;
4001 LLVMValueRef src_c0 = NULL;
4002 LLVMValueRef src_c1 = NULL;
4003 LLVMValueRef src0 = NULL;
4004 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4005 switch (instr->intrinsic) {
4006 case nir_intrinsic_interp_var_at_centroid:
4007 location = INTERP_CENTROID;
4008 break;
4009 case nir_intrinsic_interp_var_at_sample:
4010 case nir_intrinsic_interp_var_at_offset:
4011 location = INTERP_CENTER;
4012 src0 = get_src(ctx->nir, instr->src[0]);
4013 break;
4014 default:
4015 break;
4016 }
4017
4018 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4019 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4020 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4021 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4022 LLVMValueRef sample_position;
4023 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4024
4025 /* fetch sample ID */
4026 sample_position = load_sample_position(ctx, src0);
4027
4028 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4029 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4030 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4031 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4032 }
4033 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4034 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4035
4036 if (location == INTERP_CENTER) {
4037 LLVMValueRef ij_out[2];
4038 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4039
4040 /*
4041 * take the I then J parameters, and the DDX/Y for it, and
4042 * calculate the IJ inputs for the interpolator.
4043 * temp1 = ddx * offset/sample.x + I;
4044 * interp_param.I = ddy * offset/sample.y + temp1;
4045 * temp1 = ddx * offset/sample.x + J;
4046 * interp_param.J = ddy * offset/sample.y + temp1;
4047 */
4048 for (unsigned i = 0; i < 2; i++) {
4049 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4050 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4051 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4052 ddxy_out, ix_ll, "");
4053 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4054 ddxy_out, iy_ll, "");
4055 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4056 interp_param, ix_ll, "");
4057 LLVMValueRef temp1, temp2;
4058
4059 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4060 ctx->ac.f32, "");
4061
4062 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4063 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4064
4065 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4066 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4067
4068 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4069 temp2, ctx->ac.i32, "");
4070 }
4071 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4072
4073 }
4074
4075 for (chan = 0; chan < 4; chan++) {
4076 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4077
4078 if (interp_param) {
4079 interp_param = LLVMBuildBitCast(ctx->builder,
4080 interp_param, ctx->ac.v2f32, "");
4081 LLVMValueRef i = LLVMBuildExtractElement(
4082 ctx->builder, interp_param, ctx->ac.i32_0, "");
4083 LLVMValueRef j = LLVMBuildExtractElement(
4084 ctx->builder, interp_param, ctx->ac.i32_1, "");
4085
4086 result[chan] = ac_build_fs_interp(&ctx->ac,
4087 llvm_chan, attr_number,
4088 ctx->prim_mask, i, j);
4089 } else {
4090 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4091 LLVMConstInt(ctx->ac.i32, 2, false),
4092 llvm_chan, attr_number,
4093 ctx->prim_mask);
4094 }
4095 }
4096 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4097 instr->variables[0]->var->data.location_frac);
4098 }
4099
4100 static void
4101 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4102 {
4103 LLVMValueRef gs_next_vertex;
4104 LLVMValueRef can_emit;
4105 int idx;
4106 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4107
4108 /* Write vertex attribute values to GSVS ring */
4109 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4110 ctx->gs_next_vertex,
4111 "");
4112
4113 /* If this thread has already emitted the declared maximum number of
4114 * vertices, kill it: excessive vertex emissions are not supposed to
4115 * have any effect, and GS threads have no externally observable
4116 * effects other than emitting vertices.
4117 */
4118 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4119 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4120 ac_build_kill_if_false(&ctx->ac, can_emit);
4121
4122 /* loop num outputs */
4123 idx = 0;
4124 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4125 LLVMValueRef *out_ptr = &addrs[i * 4];
4126 int length = 4;
4127 int slot = idx;
4128 int slot_inc = 1;
4129
4130 if (!(ctx->output_mask & (1ull << i)))
4131 continue;
4132
4133 if (i == VARYING_SLOT_CLIP_DIST0) {
4134 /* pack clip and cull into a single set of slots */
4135 length = ctx->num_output_clips + ctx->num_output_culls;
4136 if (length > 4)
4137 slot_inc = 2;
4138 }
4139 for (unsigned j = 0; j < length; j++) {
4140 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4141 out_ptr[j], "");
4142 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4143 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4144 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4145
4146 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4147
4148 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4149 out_val, 1,
4150 voffset, ctx->gs2vs_offset, 0,
4151 1, 1, true, true);
4152 }
4153 idx += slot_inc;
4154 }
4155
4156 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4157 ctx->ac.i32_1, "");
4158 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4159
4160 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4161 }
4162
4163 static void
4164 visit_end_primitive(struct nir_to_llvm_context *ctx,
4165 const nir_intrinsic_instr *instr)
4166 {
4167 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4168 }
4169
4170 static LLVMValueRef
4171 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4172 unsigned num_components)
4173 {
4174 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4175
4176 LLVMValueRef coord[4] = {
4177 ctx->tes_u,
4178 ctx->tes_v,
4179 ctx->ac.f32_0,
4180 ctx->ac.f32_0,
4181 };
4182
4183 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4184 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4185 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4186
4187 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4188 return LLVMBuildBitCast(ctx->builder, result, type, "");
4189 }
4190
4191 static LLVMValueRef
4192 load_patch_vertices_in(struct ac_shader_abi *abi)
4193 {
4194 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4195 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4196 }
4197
4198 static void visit_intrinsic(struct ac_nir_context *ctx,
4199 nir_intrinsic_instr *instr)
4200 {
4201 LLVMValueRef result = NULL;
4202
4203 switch (instr->intrinsic) {
4204 case nir_intrinsic_load_work_group_id: {
4205 LLVMValueRef values[3];
4206
4207 for (int i = 0; i < 3; i++) {
4208 values[i] = ctx->nctx->workgroup_ids[i] ?
4209 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4210 }
4211
4212 result = ac_build_gather_values(&ctx->ac, values, 3);
4213 break;
4214 }
4215 case nir_intrinsic_load_base_vertex: {
4216 result = ctx->abi->base_vertex;
4217 break;
4218 }
4219 case nir_intrinsic_load_vertex_id_zero_base: {
4220 result = ctx->abi->vertex_id;
4221 break;
4222 }
4223 case nir_intrinsic_load_local_invocation_id: {
4224 result = ctx->nctx->local_invocation_ids;
4225 break;
4226 }
4227 case nir_intrinsic_load_base_instance:
4228 result = ctx->abi->start_instance;
4229 break;
4230 case nir_intrinsic_load_draw_id:
4231 result = ctx->abi->draw_id;
4232 break;
4233 case nir_intrinsic_load_view_index:
4234 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4235 break;
4236 case nir_intrinsic_load_invocation_id:
4237 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4238 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4239 else
4240 result = ctx->abi->gs_invocation_id;
4241 break;
4242 case nir_intrinsic_load_primitive_id:
4243 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4244 result = ctx->abi->gs_prim_id;
4245 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4246 result = ctx->abi->tcs_patch_id;
4247 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4248 result = ctx->abi->tes_patch_id;
4249 } else
4250 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4251 break;
4252 case nir_intrinsic_load_sample_id:
4253 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4254 break;
4255 case nir_intrinsic_load_sample_pos:
4256 result = load_sample_pos(ctx);
4257 break;
4258 case nir_intrinsic_load_sample_mask_in:
4259 result = ctx->abi->sample_coverage;
4260 break;
4261 case nir_intrinsic_load_frag_coord: {
4262 LLVMValueRef values[4] = {
4263 ctx->abi->frag_pos[0],
4264 ctx->abi->frag_pos[1],
4265 ctx->abi->frag_pos[2],
4266 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4267 };
4268 result = ac_build_gather_values(&ctx->ac, values, 4);
4269 break;
4270 }
4271 case nir_intrinsic_load_front_face:
4272 result = ctx->abi->front_face;
4273 break;
4274 case nir_intrinsic_load_instance_id:
4275 result = ctx->abi->instance_id;
4276 break;
4277 case nir_intrinsic_load_num_work_groups:
4278 result = ctx->nctx->num_work_groups;
4279 break;
4280 case nir_intrinsic_load_local_invocation_index:
4281 result = visit_load_local_invocation_index(ctx->nctx);
4282 break;
4283 case nir_intrinsic_load_push_constant:
4284 result = visit_load_push_constant(ctx->nctx, instr);
4285 break;
4286 case nir_intrinsic_vulkan_resource_index:
4287 result = visit_vulkan_resource_index(ctx->nctx, instr);
4288 break;
4289 case nir_intrinsic_vulkan_resource_reindex:
4290 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4291 break;
4292 case nir_intrinsic_store_ssbo:
4293 visit_store_ssbo(ctx, instr);
4294 break;
4295 case nir_intrinsic_load_ssbo:
4296 result = visit_load_buffer(ctx, instr);
4297 break;
4298 case nir_intrinsic_ssbo_atomic_add:
4299 case nir_intrinsic_ssbo_atomic_imin:
4300 case nir_intrinsic_ssbo_atomic_umin:
4301 case nir_intrinsic_ssbo_atomic_imax:
4302 case nir_intrinsic_ssbo_atomic_umax:
4303 case nir_intrinsic_ssbo_atomic_and:
4304 case nir_intrinsic_ssbo_atomic_or:
4305 case nir_intrinsic_ssbo_atomic_xor:
4306 case nir_intrinsic_ssbo_atomic_exchange:
4307 case nir_intrinsic_ssbo_atomic_comp_swap:
4308 result = visit_atomic_ssbo(ctx, instr);
4309 break;
4310 case nir_intrinsic_load_ubo:
4311 result = visit_load_ubo_buffer(ctx, instr);
4312 break;
4313 case nir_intrinsic_get_buffer_size:
4314 result = visit_get_buffer_size(ctx, instr);
4315 break;
4316 case nir_intrinsic_load_var:
4317 result = visit_load_var(ctx, instr);
4318 break;
4319 case nir_intrinsic_store_var:
4320 visit_store_var(ctx, instr);
4321 break;
4322 case nir_intrinsic_image_load:
4323 result = visit_image_load(ctx, instr);
4324 break;
4325 case nir_intrinsic_image_store:
4326 visit_image_store(ctx, instr);
4327 break;
4328 case nir_intrinsic_image_atomic_add:
4329 case nir_intrinsic_image_atomic_min:
4330 case nir_intrinsic_image_atomic_max:
4331 case nir_intrinsic_image_atomic_and:
4332 case nir_intrinsic_image_atomic_or:
4333 case nir_intrinsic_image_atomic_xor:
4334 case nir_intrinsic_image_atomic_exchange:
4335 case nir_intrinsic_image_atomic_comp_swap:
4336 result = visit_image_atomic(ctx, instr);
4337 break;
4338 case nir_intrinsic_image_size:
4339 result = visit_image_size(ctx, instr);
4340 break;
4341 case nir_intrinsic_discard:
4342 case nir_intrinsic_discard_if:
4343 emit_discard(ctx, instr);
4344 break;
4345 case nir_intrinsic_memory_barrier:
4346 case nir_intrinsic_group_memory_barrier:
4347 case nir_intrinsic_memory_barrier_atomic_counter:
4348 case nir_intrinsic_memory_barrier_buffer:
4349 case nir_intrinsic_memory_barrier_image:
4350 case nir_intrinsic_memory_barrier_shared:
4351 emit_membar(ctx->nctx, instr);
4352 break;
4353 case nir_intrinsic_barrier:
4354 emit_barrier(&ctx->ac, ctx->stage);
4355 break;
4356 case nir_intrinsic_var_atomic_add:
4357 case nir_intrinsic_var_atomic_imin:
4358 case nir_intrinsic_var_atomic_umin:
4359 case nir_intrinsic_var_atomic_imax:
4360 case nir_intrinsic_var_atomic_umax:
4361 case nir_intrinsic_var_atomic_and:
4362 case nir_intrinsic_var_atomic_or:
4363 case nir_intrinsic_var_atomic_xor:
4364 case nir_intrinsic_var_atomic_exchange:
4365 case nir_intrinsic_var_atomic_comp_swap:
4366 result = visit_var_atomic(ctx->nctx, instr);
4367 break;
4368 case nir_intrinsic_interp_var_at_centroid:
4369 case nir_intrinsic_interp_var_at_sample:
4370 case nir_intrinsic_interp_var_at_offset:
4371 result = visit_interp(ctx->nctx, instr);
4372 break;
4373 case nir_intrinsic_emit_vertex:
4374 assert(instr->const_index[0] == 0);
4375 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4376 break;
4377 case nir_intrinsic_end_primitive:
4378 visit_end_primitive(ctx->nctx, instr);
4379 break;
4380 case nir_intrinsic_load_tess_coord: {
4381 LLVMTypeRef type = ctx->nctx ?
4382 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4383 NULL;
4384 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4385 break;
4386 }
4387 case nir_intrinsic_load_tess_level_outer:
4388 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4389 break;
4390 case nir_intrinsic_load_tess_level_inner:
4391 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4392 break;
4393 case nir_intrinsic_load_patch_vertices_in:
4394 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4395 break;
4396 default:
4397 fprintf(stderr, "Unknown intrinsic: ");
4398 nir_print_instr(&instr->instr, stderr);
4399 fprintf(stderr, "\n");
4400 break;
4401 }
4402 if (result) {
4403 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4404 }
4405 }
4406
4407 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4408 LLVMValueRef buffer_ptr, bool write)
4409 {
4410 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4411
4412 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4413 ctx->shader_info->fs.writes_memory = true;
4414
4415 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4416 }
4417
4418 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4419 {
4420 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4421
4422 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4423 }
4424
4425 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4426 unsigned descriptor_set,
4427 unsigned base_index,
4428 unsigned constant_index,
4429 LLVMValueRef index,
4430 enum ac_descriptor_type desc_type,
4431 bool image, bool write)
4432 {
4433 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4434 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4435 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4436 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4437 unsigned offset = binding->offset;
4438 unsigned stride = binding->size;
4439 unsigned type_size;
4440 LLVMBuilderRef builder = ctx->builder;
4441 LLVMTypeRef type;
4442
4443 assert(base_index < layout->binding_count);
4444
4445 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4446 ctx->shader_info->fs.writes_memory = true;
4447
4448 switch (desc_type) {
4449 case AC_DESC_IMAGE:
4450 type = ctx->ac.v8i32;
4451 type_size = 32;
4452 break;
4453 case AC_DESC_FMASK:
4454 type = ctx->ac.v8i32;
4455 offset += 32;
4456 type_size = 32;
4457 break;
4458 case AC_DESC_SAMPLER:
4459 type = ctx->ac.v4i32;
4460 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4461 offset += 64;
4462
4463 type_size = 16;
4464 break;
4465 case AC_DESC_BUFFER:
4466 type = ctx->ac.v4i32;
4467 type_size = 16;
4468 break;
4469 default:
4470 unreachable("invalid desc_type\n");
4471 }
4472
4473 offset += constant_index * stride;
4474
4475 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4476 (!index || binding->immutable_samplers_equal)) {
4477 if (binding->immutable_samplers_equal)
4478 constant_index = 0;
4479
4480 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4481
4482 LLVMValueRef constants[] = {
4483 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4484 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4485 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4486 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4487 };
4488 return ac_build_gather_values(&ctx->ac, constants, 4);
4489 }
4490
4491 assert(stride % type_size == 0);
4492
4493 if (!index)
4494 index = ctx->ac.i32_0;
4495
4496 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4497
4498 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4499 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4500
4501 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4502 }
4503
4504 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4505 const nir_deref_var *deref,
4506 enum ac_descriptor_type desc_type,
4507 const nir_tex_instr *tex_instr,
4508 bool image, bool write)
4509 {
4510 LLVMValueRef index = NULL;
4511 unsigned constant_index = 0;
4512 unsigned descriptor_set;
4513 unsigned base_index;
4514
4515 if (!deref) {
4516 assert(tex_instr && !image);
4517 descriptor_set = 0;
4518 base_index = tex_instr->sampler_index;
4519 } else {
4520 const nir_deref *tail = &deref->deref;
4521 while (tail->child) {
4522 const nir_deref_array *child = nir_deref_as_array(tail->child);
4523 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4524
4525 if (!array_size)
4526 array_size = 1;
4527
4528 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4529
4530 if (child->deref_array_type == nir_deref_array_type_indirect) {
4531 LLVMValueRef indirect = get_src(ctx, child->indirect);
4532
4533 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4534 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4535
4536 if (!index)
4537 index = indirect;
4538 else
4539 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4540 }
4541
4542 constant_index += child->base_offset * array_size;
4543
4544 tail = &child->deref;
4545 }
4546 descriptor_set = deref->var->data.descriptor_set;
4547 base_index = deref->var->data.binding;
4548 }
4549
4550 return ctx->abi->load_sampler_desc(ctx->abi,
4551 descriptor_set,
4552 base_index,
4553 constant_index, index,
4554 desc_type, image, write);
4555 }
4556
4557 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4558 struct ac_image_args *args,
4559 const nir_tex_instr *instr,
4560 nir_texop op,
4561 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4562 LLVMValueRef *param, unsigned count,
4563 unsigned dmask)
4564 {
4565 unsigned is_rect = 0;
4566 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4567
4568 if (op == nir_texop_lod)
4569 da = false;
4570 /* Pad to power of two vector */
4571 while (count < util_next_power_of_two(count))
4572 param[count++] = LLVMGetUndef(ctx->i32);
4573
4574 if (count > 1)
4575 args->addr = ac_build_gather_values(ctx, param, count);
4576 else
4577 args->addr = param[0];
4578
4579 args->resource = res_ptr;
4580 args->sampler = samp_ptr;
4581
4582 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4583 args->addr = param[0];
4584 return;
4585 }
4586
4587 args->dmask = dmask;
4588 args->unorm = is_rect;
4589 args->da = da;
4590 }
4591
4592 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4593 *
4594 * SI-CI:
4595 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4596 * filtering manually. The driver sets img7 to a mask clearing
4597 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4598 * s_and_b32 samp0, samp0, img7
4599 *
4600 * VI:
4601 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4602 */
4603 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4604 LLVMValueRef res, LLVMValueRef samp)
4605 {
4606 LLVMBuilderRef builder = ctx->ac.builder;
4607 LLVMValueRef img7, samp0;
4608
4609 if (ctx->ac.chip_class >= VI)
4610 return samp;
4611
4612 img7 = LLVMBuildExtractElement(builder, res,
4613 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4614 samp0 = LLVMBuildExtractElement(builder, samp,
4615 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4616 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4617 return LLVMBuildInsertElement(builder, samp, samp0,
4618 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4619 }
4620
4621 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4622 nir_tex_instr *instr,
4623 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4624 LLVMValueRef *fmask_ptr)
4625 {
4626 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4627 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4628 else
4629 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4630 if (samp_ptr) {
4631 if (instr->sampler)
4632 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4633 else
4634 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4635 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4636 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4637 }
4638 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4639 instr->op == nir_texop_samples_identical))
4640 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4641 }
4642
4643 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4644 LLVMValueRef coord)
4645 {
4646 coord = ac_to_float(ctx, coord);
4647 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4648 coord = ac_to_integer(ctx, coord);
4649 return coord;
4650 }
4651
4652 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4653 {
4654 LLVMValueRef result = NULL;
4655 struct ac_image_args args = { 0 };
4656 unsigned dmask = 0xf;
4657 LLVMValueRef address[16];
4658 LLVMValueRef coords[5];
4659 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4660 LLVMValueRef bias = NULL, offsets = NULL;
4661 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4662 LLVMValueRef ddx = NULL, ddy = NULL;
4663 LLVMValueRef derivs[6];
4664 unsigned chan, count = 0;
4665 unsigned const_src = 0, num_deriv_comp = 0;
4666 bool lod_is_zero = false;
4667
4668 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4669
4670 for (unsigned i = 0; i < instr->num_srcs; i++) {
4671 switch (instr->src[i].src_type) {
4672 case nir_tex_src_coord:
4673 coord = get_src(ctx, instr->src[i].src);
4674 break;
4675 case nir_tex_src_projector:
4676 break;
4677 case nir_tex_src_comparator:
4678 comparator = get_src(ctx, instr->src[i].src);
4679 break;
4680 case nir_tex_src_offset:
4681 offsets = get_src(ctx, instr->src[i].src);
4682 const_src = i;
4683 break;
4684 case nir_tex_src_bias:
4685 bias = get_src(ctx, instr->src[i].src);
4686 break;
4687 case nir_tex_src_lod: {
4688 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4689
4690 if (val && val->i32[0] == 0)
4691 lod_is_zero = true;
4692 lod = get_src(ctx, instr->src[i].src);
4693 break;
4694 }
4695 case nir_tex_src_ms_index:
4696 sample_index = get_src(ctx, instr->src[i].src);
4697 break;
4698 case nir_tex_src_ms_mcs:
4699 break;
4700 case nir_tex_src_ddx:
4701 ddx = get_src(ctx, instr->src[i].src);
4702 num_deriv_comp = instr->src[i].src.ssa->num_components;
4703 break;
4704 case nir_tex_src_ddy:
4705 ddy = get_src(ctx, instr->src[i].src);
4706 break;
4707 case nir_tex_src_texture_offset:
4708 case nir_tex_src_sampler_offset:
4709 case nir_tex_src_plane:
4710 default:
4711 break;
4712 }
4713 }
4714
4715 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4716 result = get_buffer_size(ctx, res_ptr, true);
4717 goto write_result;
4718 }
4719
4720 if (instr->op == nir_texop_texture_samples) {
4721 LLVMValueRef res, samples, is_msaa;
4722 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4723 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4724 LLVMConstInt(ctx->ac.i32, 3, false), "");
4725 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4726 LLVMConstInt(ctx->ac.i32, 28, false), "");
4727 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4728 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4729 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4730 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4731
4732 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4733 LLVMConstInt(ctx->ac.i32, 16, false), "");
4734 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4735 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4736 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4737 samples, "");
4738 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4739 ctx->ac.i32_1, "");
4740 result = samples;
4741 goto write_result;
4742 }
4743
4744 if (coord)
4745 for (chan = 0; chan < instr->coord_components; chan++)
4746 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4747
4748 if (offsets && instr->op != nir_texop_txf) {
4749 LLVMValueRef offset[3], pack;
4750 for (chan = 0; chan < 3; ++chan)
4751 offset[chan] = ctx->ac.i32_0;
4752
4753 args.offset = true;
4754 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4755 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4756 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4757 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4758 if (chan)
4759 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4760 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4761 }
4762 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4763 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4764 address[count++] = pack;
4765
4766 }
4767 /* pack LOD bias value */
4768 if (instr->op == nir_texop_txb && bias) {
4769 address[count++] = bias;
4770 }
4771
4772 /* Pack depth comparison value */
4773 if (instr->is_shadow && comparator) {
4774 LLVMValueRef z = ac_to_float(&ctx->ac,
4775 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4776
4777 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4778 * so the depth comparison value isn't clamped for Z16 and
4779 * Z24 anymore. Do it manually here.
4780 *
4781 * It's unnecessary if the original texture format was
4782 * Z32_FLOAT, but we don't know that here.
4783 */
4784 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4785 z = ac_build_clamp(&ctx->ac, z);
4786
4787 address[count++] = z;
4788 }
4789
4790 /* pack derivatives */
4791 if (ddx || ddy) {
4792 int num_src_deriv_channels, num_dest_deriv_channels;
4793 switch (instr->sampler_dim) {
4794 case GLSL_SAMPLER_DIM_3D:
4795 case GLSL_SAMPLER_DIM_CUBE:
4796 num_deriv_comp = 3;
4797 num_src_deriv_channels = 3;
4798 num_dest_deriv_channels = 3;
4799 break;
4800 case GLSL_SAMPLER_DIM_2D:
4801 default:
4802 num_src_deriv_channels = 2;
4803 num_dest_deriv_channels = 2;
4804 num_deriv_comp = 2;
4805 break;
4806 case GLSL_SAMPLER_DIM_1D:
4807 num_src_deriv_channels = 1;
4808 if (ctx->ac.chip_class >= GFX9) {
4809 num_dest_deriv_channels = 2;
4810 num_deriv_comp = 2;
4811 } else {
4812 num_dest_deriv_channels = 1;
4813 num_deriv_comp = 1;
4814 }
4815 break;
4816 }
4817
4818 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4819 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4820 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4821 }
4822 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4823 derivs[i] = ctx->ac.f32_0;
4824 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4825 }
4826 }
4827
4828 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4829 for (chan = 0; chan < instr->coord_components; chan++)
4830 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4831 if (instr->coord_components == 3)
4832 coords[3] = LLVMGetUndef(ctx->ac.f32);
4833 ac_prepare_cube_coords(&ctx->ac,
4834 instr->op == nir_texop_txd, instr->is_array,
4835 instr->op == nir_texop_lod, coords, derivs);
4836 if (num_deriv_comp)
4837 num_deriv_comp--;
4838 }
4839
4840 if (ddx || ddy) {
4841 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4842 address[count++] = derivs[i];
4843 }
4844
4845 /* Pack texture coordinates */
4846 if (coord) {
4847 address[count++] = coords[0];
4848 if (instr->coord_components > 1) {
4849 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4850 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4851 }
4852 address[count++] = coords[1];
4853 }
4854 if (instr->coord_components > 2) {
4855 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4856 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4857 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4858 instr->op != nir_texop_txf) {
4859 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4860 }
4861 address[count++] = coords[2];
4862 }
4863
4864 if (ctx->ac.chip_class >= GFX9) {
4865 LLVMValueRef filler;
4866 if (instr->op == nir_texop_txf)
4867 filler = ctx->ac.i32_0;
4868 else
4869 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4870
4871 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4872 /* No nir_texop_lod, because it does not take a slice
4873 * even with array textures. */
4874 if (instr->is_array && instr->op != nir_texop_lod ) {
4875 address[count] = address[count - 1];
4876 address[count - 1] = filler;
4877 count++;
4878 } else
4879 address[count++] = filler;
4880 }
4881 }
4882 }
4883
4884 /* Pack LOD */
4885 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4886 instr->op == nir_texop_txf)) {
4887 address[count++] = lod;
4888 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4889 address[count++] = sample_index;
4890 } else if(instr->op == nir_texop_txs) {
4891 count = 0;
4892 if (lod)
4893 address[count++] = lod;
4894 else
4895 address[count++] = ctx->ac.i32_0;
4896 }
4897
4898 for (chan = 0; chan < count; chan++) {
4899 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4900 address[chan], ctx->ac.i32, "");
4901 }
4902
4903 if (instr->op == nir_texop_samples_identical) {
4904 LLVMValueRef txf_address[4];
4905 struct ac_image_args txf_args = { 0 };
4906 unsigned txf_count = count;
4907 memcpy(txf_address, address, sizeof(txf_address));
4908
4909 if (!instr->is_array)
4910 txf_address[2] = ctx->ac.i32_0;
4911 txf_address[3] = ctx->ac.i32_0;
4912
4913 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4914 fmask_ptr, NULL,
4915 txf_address, txf_count, 0xf);
4916
4917 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4918
4919 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4920 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4921 goto write_result;
4922 }
4923
4924 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4925 instr->op != nir_texop_txs) {
4926 unsigned sample_chan = instr->is_array ? 3 : 2;
4927 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4928 address[0],
4929 address[1],
4930 instr->is_array ? address[2] : NULL,
4931 address[sample_chan],
4932 fmask_ptr);
4933 }
4934
4935 if (offsets && instr->op == nir_texop_txf) {
4936 nir_const_value *const_offset =
4937 nir_src_as_const_value(instr->src[const_src].src);
4938 int num_offsets = instr->src[const_src].src.ssa->num_components;
4939 assert(const_offset);
4940 num_offsets = MIN2(num_offsets, instr->coord_components);
4941 if (num_offsets > 2)
4942 address[2] = LLVMBuildAdd(ctx->ac.builder,
4943 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4944 if (num_offsets > 1)
4945 address[1] = LLVMBuildAdd(ctx->ac.builder,
4946 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4947 address[0] = LLVMBuildAdd(ctx->ac.builder,
4948 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4949
4950 }
4951
4952 /* TODO TG4 support */
4953 if (instr->op == nir_texop_tg4) {
4954 if (instr->is_shadow)
4955 dmask = 1;
4956 else
4957 dmask = 1 << instr->component;
4958 }
4959 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4960 res_ptr, samp_ptr, address, count, dmask);
4961
4962 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4963
4964 if (instr->op == nir_texop_query_levels)
4965 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4966 else if (instr->is_shadow && instr->is_new_style_shadow &&
4967 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4968 instr->op != nir_texop_tg4)
4969 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4970 else if (instr->op == nir_texop_txs &&
4971 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4972 instr->is_array) {
4973 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4974 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4975 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4976 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4977 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4978 } else if (ctx->ac.chip_class >= GFX9 &&
4979 instr->op == nir_texop_txs &&
4980 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4981 instr->is_array) {
4982 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4983 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4984 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4985 ctx->ac.i32_1, "");
4986 } else if (instr->dest.ssa.num_components != 4)
4987 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4988
4989 write_result:
4990 if (result) {
4991 assert(instr->dest.is_ssa);
4992 result = ac_to_integer(&ctx->ac, result);
4993 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4994 }
4995 }
4996
4997
4998 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4999 {
5000 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5001 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5002
5003 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5004 _mesa_hash_table_insert(ctx->phis, instr, result);
5005 }
5006
5007 static void visit_post_phi(struct ac_nir_context *ctx,
5008 nir_phi_instr *instr,
5009 LLVMValueRef llvm_phi)
5010 {
5011 nir_foreach_phi_src(src, instr) {
5012 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5013 LLVMValueRef llvm_src = get_src(ctx, src->src);
5014
5015 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5016 }
5017 }
5018
5019 static void phi_post_pass(struct ac_nir_context *ctx)
5020 {
5021 struct hash_entry *entry;
5022 hash_table_foreach(ctx->phis, entry) {
5023 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5024 (LLVMValueRef)entry->data);
5025 }
5026 }
5027
5028
5029 static void visit_ssa_undef(struct ac_nir_context *ctx,
5030 const nir_ssa_undef_instr *instr)
5031 {
5032 unsigned num_components = instr->def.num_components;
5033 LLVMValueRef undef;
5034
5035 if (num_components == 1)
5036 undef = LLVMGetUndef(ctx->ac.i32);
5037 else {
5038 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5039 }
5040 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5041 }
5042
5043 static void visit_jump(struct ac_nir_context *ctx,
5044 const nir_jump_instr *instr)
5045 {
5046 switch (instr->type) {
5047 case nir_jump_break:
5048 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5049 LLVMClearInsertionPosition(ctx->ac.builder);
5050 break;
5051 case nir_jump_continue:
5052 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5053 LLVMClearInsertionPosition(ctx->ac.builder);
5054 break;
5055 default:
5056 fprintf(stderr, "Unknown NIR jump instr: ");
5057 nir_print_instr(&instr->instr, stderr);
5058 fprintf(stderr, "\n");
5059 abort();
5060 }
5061 }
5062
5063 static void visit_cf_list(struct ac_nir_context *ctx,
5064 struct exec_list *list);
5065
5066 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5067 {
5068 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5069 nir_foreach_instr(instr, block)
5070 {
5071 switch (instr->type) {
5072 case nir_instr_type_alu:
5073 visit_alu(ctx, nir_instr_as_alu(instr));
5074 break;
5075 case nir_instr_type_load_const:
5076 visit_load_const(ctx, nir_instr_as_load_const(instr));
5077 break;
5078 case nir_instr_type_intrinsic:
5079 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5080 break;
5081 case nir_instr_type_tex:
5082 visit_tex(ctx, nir_instr_as_tex(instr));
5083 break;
5084 case nir_instr_type_phi:
5085 visit_phi(ctx, nir_instr_as_phi(instr));
5086 break;
5087 case nir_instr_type_ssa_undef:
5088 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5089 break;
5090 case nir_instr_type_jump:
5091 visit_jump(ctx, nir_instr_as_jump(instr));
5092 break;
5093 default:
5094 fprintf(stderr, "Unknown NIR instr type: ");
5095 nir_print_instr(instr, stderr);
5096 fprintf(stderr, "\n");
5097 abort();
5098 }
5099 }
5100
5101 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5102 }
5103
5104 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5105 {
5106 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5107
5108 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5109 LLVMBasicBlockRef merge_block =
5110 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5111 LLVMBasicBlockRef if_block =
5112 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5113 LLVMBasicBlockRef else_block = merge_block;
5114 if (!exec_list_is_empty(&if_stmt->else_list))
5115 else_block = LLVMAppendBasicBlockInContext(
5116 ctx->ac.context, fn, "");
5117
5118 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5119 ctx->ac.i32_0, "");
5120 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5121
5122 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5123 visit_cf_list(ctx, &if_stmt->then_list);
5124 if (LLVMGetInsertBlock(ctx->ac.builder))
5125 LLVMBuildBr(ctx->ac.builder, merge_block);
5126
5127 if (!exec_list_is_empty(&if_stmt->else_list)) {
5128 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5129 visit_cf_list(ctx, &if_stmt->else_list);
5130 if (LLVMGetInsertBlock(ctx->ac.builder))
5131 LLVMBuildBr(ctx->ac.builder, merge_block);
5132 }
5133
5134 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5135 }
5136
5137 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5138 {
5139 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5140 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5141 LLVMBasicBlockRef break_parent = ctx->break_block;
5142
5143 ctx->continue_block =
5144 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5145 ctx->break_block =
5146 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5147
5148 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5149 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5150 visit_cf_list(ctx, &loop->body);
5151
5152 if (LLVMGetInsertBlock(ctx->ac.builder))
5153 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5154 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5155
5156 ctx->continue_block = continue_parent;
5157 ctx->break_block = break_parent;
5158 }
5159
5160 static void visit_cf_list(struct ac_nir_context *ctx,
5161 struct exec_list *list)
5162 {
5163 foreach_list_typed(nir_cf_node, node, node, list)
5164 {
5165 switch (node->type) {
5166 case nir_cf_node_block:
5167 visit_block(ctx, nir_cf_node_as_block(node));
5168 break;
5169
5170 case nir_cf_node_if:
5171 visit_if(ctx, nir_cf_node_as_if(node));
5172 break;
5173
5174 case nir_cf_node_loop:
5175 visit_loop(ctx, nir_cf_node_as_loop(node));
5176 break;
5177
5178 default:
5179 assert(0);
5180 }
5181 }
5182 }
5183
5184 static void
5185 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5186 struct nir_variable *variable)
5187 {
5188 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5189 LLVMValueRef t_offset;
5190 LLVMValueRef t_list;
5191 LLVMValueRef input;
5192 LLVMValueRef buffer_index;
5193 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5194 int idx = variable->data.location;
5195 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5196
5197 variable->data.driver_location = idx * 4;
5198
5199 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5200 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5201 ctx->abi.start_instance, "");
5202 if (ctx->options->key.vs.as_ls) {
5203 ctx->shader_info->vs.vgpr_comp_cnt =
5204 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5205 } else {
5206 ctx->shader_info->vs.vgpr_comp_cnt =
5207 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5208 }
5209 } else
5210 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5211 ctx->abi.base_vertex, "");
5212
5213 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5214 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5215
5216 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5217
5218 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5219 buffer_index,
5220 ctx->ac.i32_0,
5221 true);
5222
5223 for (unsigned chan = 0; chan < 4; chan++) {
5224 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5225 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5226 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5227 input, llvm_chan, ""));
5228 }
5229 }
5230 }
5231
5232 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5233 unsigned attr,
5234 LLVMValueRef interp_param,
5235 LLVMValueRef prim_mask,
5236 LLVMValueRef result[4])
5237 {
5238 LLVMValueRef attr_number;
5239 unsigned chan;
5240 LLVMValueRef i, j;
5241 bool interp = interp_param != NULL;
5242
5243 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5244
5245 /* fs.constant returns the param from the middle vertex, so it's not
5246 * really useful for flat shading. It's meant to be used for custom
5247 * interpolation (but the intrinsic can't fetch from the other two
5248 * vertices).
5249 *
5250 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5251 * to do the right thing. The only reason we use fs.constant is that
5252 * fs.interp cannot be used on integers, because they can be equal
5253 * to NaN.
5254 */
5255 if (interp) {
5256 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5257 ctx->ac.v2f32, "");
5258
5259 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5260 ctx->ac.i32_0, "");
5261 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5262 ctx->ac.i32_1, "");
5263 }
5264
5265 for (chan = 0; chan < 4; chan++) {
5266 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5267
5268 if (interp) {
5269 result[chan] = ac_build_fs_interp(&ctx->ac,
5270 llvm_chan,
5271 attr_number,
5272 prim_mask, i, j);
5273 } else {
5274 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5275 LLVMConstInt(ctx->ac.i32, 2, false),
5276 llvm_chan,
5277 attr_number,
5278 prim_mask);
5279 }
5280 }
5281 }
5282
5283 static void
5284 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5285 struct nir_variable *variable)
5286 {
5287 int idx = variable->data.location;
5288 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5289 LLVMValueRef interp;
5290
5291 variable->data.driver_location = idx * 4;
5292 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5293
5294 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5295 unsigned interp_type;
5296 if (variable->data.sample) {
5297 interp_type = INTERP_SAMPLE;
5298 ctx->shader_info->info.ps.force_persample = true;
5299 } else if (variable->data.centroid)
5300 interp_type = INTERP_CENTROID;
5301 else
5302 interp_type = INTERP_CENTER;
5303
5304 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5305 } else
5306 interp = NULL;
5307
5308 for (unsigned i = 0; i < attrib_count; ++i)
5309 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5310
5311 }
5312
5313 static void
5314 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5315 struct nir_shader *nir) {
5316 nir_foreach_variable(variable, &nir->inputs)
5317 handle_vs_input_decl(ctx, variable);
5318 }
5319
5320 static void
5321 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5322 struct nir_shader *nir)
5323 {
5324 if (!ctx->options->key.fs.multisample)
5325 return;
5326
5327 bool uses_center = false;
5328 bool uses_centroid = false;
5329 nir_foreach_variable(variable, &nir->inputs) {
5330 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5331 variable->data.sample)
5332 continue;
5333
5334 if (variable->data.centroid)
5335 uses_centroid = true;
5336 else
5337 uses_center = true;
5338 }
5339
5340 if (uses_center && uses_centroid) {
5341 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5342 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5343 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5344 }
5345 }
5346
5347 static void
5348 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5349 struct nir_shader *nir)
5350 {
5351 prepare_interp_optimize(ctx, nir);
5352
5353 nir_foreach_variable(variable, &nir->inputs)
5354 handle_fs_input_decl(ctx, variable);
5355
5356 unsigned index = 0;
5357
5358 if (ctx->shader_info->info.ps.uses_input_attachments ||
5359 ctx->shader_info->info.needs_multiview_view_index)
5360 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5361
5362 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5363 LLVMValueRef interp_param;
5364 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5365
5366 if (!(ctx->input_mask & (1ull << i)))
5367 continue;
5368
5369 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5370 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5371 interp_param = *inputs;
5372 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5373 inputs);
5374
5375 if (!interp_param)
5376 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5377 ++index;
5378 } else if (i == VARYING_SLOT_POS) {
5379 for(int i = 0; i < 3; ++i)
5380 inputs[i] = ctx->abi.frag_pos[i];
5381
5382 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5383 ctx->abi.frag_pos[3]);
5384 }
5385 }
5386 ctx->shader_info->fs.num_interp = index;
5387 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5388 ctx->shader_info->fs.has_pcoord = true;
5389 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5390 ctx->shader_info->fs.prim_id_input = true;
5391 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5392 ctx->shader_info->fs.layer_input = true;
5393 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5394
5395 if (ctx->shader_info->info.needs_multiview_view_index)
5396 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5397 }
5398
5399 static LLVMValueRef
5400 ac_build_alloca(struct ac_llvm_context *ac,
5401 LLVMTypeRef type,
5402 const char *name)
5403 {
5404 LLVMBuilderRef builder = ac->builder;
5405 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5406 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5407 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5408 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5409 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5410 LLVMValueRef res;
5411
5412 if (first_instr) {
5413 LLVMPositionBuilderBefore(first_builder, first_instr);
5414 } else {
5415 LLVMPositionBuilderAtEnd(first_builder, first_block);
5416 }
5417
5418 res = LLVMBuildAlloca(first_builder, type, name);
5419 LLVMBuildStore(builder, LLVMConstNull(type), res);
5420
5421 LLVMDisposeBuilder(first_builder);
5422
5423 return res;
5424 }
5425
5426 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5427 LLVMTypeRef type,
5428 const char *name)
5429 {
5430 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5431 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5432 return ptr;
5433 }
5434
5435 static void
5436 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5437 struct nir_variable *variable,
5438 struct nir_shader *shader,
5439 gl_shader_stage stage)
5440 {
5441 int idx = variable->data.location + variable->data.index;
5442 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5443 uint64_t mask_attribs;
5444
5445 variable->data.driver_location = idx * 4;
5446
5447 /* tess ctrl has it's own load/store paths for outputs */
5448 if (stage == MESA_SHADER_TESS_CTRL)
5449 return;
5450
5451 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5452 if (stage == MESA_SHADER_VERTEX ||
5453 stage == MESA_SHADER_TESS_EVAL ||
5454 stage == MESA_SHADER_GEOMETRY) {
5455 if (idx == VARYING_SLOT_CLIP_DIST0) {
5456 int length = shader->info.clip_distance_array_size +
5457 shader->info.cull_distance_array_size;
5458 if (stage == MESA_SHADER_VERTEX) {
5459 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5460 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5461 }
5462 if (stage == MESA_SHADER_TESS_EVAL) {
5463 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5464 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5465 }
5466
5467 if (length > 4)
5468 attrib_count = 2;
5469 else
5470 attrib_count = 1;
5471 mask_attribs = 1ull << idx;
5472 }
5473 }
5474
5475 ctx->output_mask |= mask_attribs;
5476 }
5477
5478 static void
5479 handle_shader_output_decl(struct ac_nir_context *ctx,
5480 struct nir_shader *nir,
5481 struct nir_variable *variable)
5482 {
5483 unsigned output_loc = variable->data.driver_location / 4;
5484 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5485
5486 /* tess ctrl has it's own load/store paths for outputs */
5487 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5488 return;
5489
5490 if (ctx->stage == MESA_SHADER_VERTEX ||
5491 ctx->stage == MESA_SHADER_TESS_EVAL ||
5492 ctx->stage == MESA_SHADER_GEOMETRY) {
5493 int idx = variable->data.location + variable->data.index;
5494 if (idx == VARYING_SLOT_CLIP_DIST0) {
5495 int length = nir->info.clip_distance_array_size +
5496 nir->info.cull_distance_array_size;
5497
5498 if (length > 4)
5499 attrib_count = 2;
5500 else
5501 attrib_count = 1;
5502 }
5503 }
5504
5505 for (unsigned i = 0; i < attrib_count; ++i) {
5506 for (unsigned chan = 0; chan < 4; chan++) {
5507 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5508 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5509 }
5510 }
5511 }
5512
5513 static LLVMTypeRef
5514 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5515 enum glsl_base_type type)
5516 {
5517 switch (type) {
5518 case GLSL_TYPE_INT:
5519 case GLSL_TYPE_UINT:
5520 case GLSL_TYPE_BOOL:
5521 case GLSL_TYPE_SUBROUTINE:
5522 return ctx->ac.i32;
5523 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5524 return ctx->ac.f32;
5525 case GLSL_TYPE_INT64:
5526 case GLSL_TYPE_UINT64:
5527 return ctx->ac.i64;
5528 case GLSL_TYPE_DOUBLE:
5529 return ctx->ac.f64;
5530 default:
5531 unreachable("unknown GLSL type");
5532 }
5533 }
5534
5535 static LLVMTypeRef
5536 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5537 const struct glsl_type *type)
5538 {
5539 if (glsl_type_is_scalar(type)) {
5540 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5541 }
5542
5543 if (glsl_type_is_vector(type)) {
5544 return LLVMVectorType(
5545 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5546 glsl_get_vector_elements(type));
5547 }
5548
5549 if (glsl_type_is_matrix(type)) {
5550 return LLVMArrayType(
5551 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5552 glsl_get_matrix_columns(type));
5553 }
5554
5555 if (glsl_type_is_array(type)) {
5556 return LLVMArrayType(
5557 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5558 glsl_get_length(type));
5559 }
5560
5561 assert(glsl_type_is_struct(type));
5562
5563 LLVMTypeRef member_types[glsl_get_length(type)];
5564
5565 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5566 member_types[i] =
5567 glsl_to_llvm_type(ctx,
5568 glsl_get_struct_field(type, i));
5569 }
5570
5571 return LLVMStructTypeInContext(ctx->context, member_types,
5572 glsl_get_length(type), false);
5573 }
5574
5575 static void
5576 setup_locals(struct ac_nir_context *ctx,
5577 struct nir_function *func)
5578 {
5579 int i, j;
5580 ctx->num_locals = 0;
5581 nir_foreach_variable(variable, &func->impl->locals) {
5582 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5583 variable->data.driver_location = ctx->num_locals * 4;
5584 variable->data.location_frac = 0;
5585 ctx->num_locals += attrib_count;
5586 }
5587 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5588 if (!ctx->locals)
5589 return;
5590
5591 for (i = 0; i < ctx->num_locals; i++) {
5592 for (j = 0; j < 4; j++) {
5593 ctx->locals[i * 4 + j] =
5594 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5595 }
5596 }
5597 }
5598
5599 static void
5600 setup_shared(struct ac_nir_context *ctx,
5601 struct nir_shader *nir)
5602 {
5603 nir_foreach_variable(variable, &nir->shared) {
5604 LLVMValueRef shared =
5605 LLVMAddGlobalInAddressSpace(
5606 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5607 variable->name ? variable->name : "",
5608 LOCAL_ADDR_SPACE);
5609 _mesa_hash_table_insert(ctx->vars, variable, shared);
5610 }
5611 }
5612
5613 static LLVMValueRef
5614 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5615 {
5616 v = ac_to_float(ctx, v);
5617 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5618 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5619 }
5620
5621
5622 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5623 LLVMValueRef src0, LLVMValueRef src1)
5624 {
5625 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5626 LLVMValueRef comp[2];
5627
5628 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5629 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5630 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5631 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5632 }
5633
5634 /* Initialize arguments for the shader export intrinsic */
5635 static void
5636 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5637 LLVMValueRef *values,
5638 unsigned target,
5639 struct ac_export_args *args)
5640 {
5641 /* Default is 0xf. Adjusted below depending on the format. */
5642 args->enabled_channels = 0xf;
5643
5644 /* Specify whether the EXEC mask represents the valid mask */
5645 args->valid_mask = 0;
5646
5647 /* Specify whether this is the last export */
5648 args->done = 0;
5649
5650 /* Specify the target we are exporting */
5651 args->target = target;
5652
5653 args->compr = false;
5654 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5655 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5656 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5657 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5658
5659 if (!values)
5660 return;
5661
5662 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5663 LLVMValueRef val[4];
5664 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5665 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5666 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5667 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5668
5669 switch(col_format) {
5670 case V_028714_SPI_SHADER_ZERO:
5671 args->enabled_channels = 0; /* writemask */
5672 args->target = V_008DFC_SQ_EXP_NULL;
5673 break;
5674
5675 case V_028714_SPI_SHADER_32_R:
5676 args->enabled_channels = 1;
5677 args->out[0] = values[0];
5678 break;
5679
5680 case V_028714_SPI_SHADER_32_GR:
5681 args->enabled_channels = 0x3;
5682 args->out[0] = values[0];
5683 args->out[1] = values[1];
5684 break;
5685
5686 case V_028714_SPI_SHADER_32_AR:
5687 args->enabled_channels = 0x9;
5688 args->out[0] = values[0];
5689 args->out[3] = values[3];
5690 break;
5691
5692 case V_028714_SPI_SHADER_FP16_ABGR:
5693 args->compr = 1;
5694
5695 for (unsigned chan = 0; chan < 2; chan++) {
5696 LLVMValueRef pack_args[2] = {
5697 values[2 * chan],
5698 values[2 * chan + 1]
5699 };
5700 LLVMValueRef packed;
5701
5702 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5703 args->out[chan] = packed;
5704 }
5705 break;
5706
5707 case V_028714_SPI_SHADER_UNORM16_ABGR:
5708 for (unsigned chan = 0; chan < 4; chan++) {
5709 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5710 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5711 LLVMConstReal(ctx->ac.f32, 65535), "");
5712 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5713 LLVMConstReal(ctx->ac.f32, 0.5), "");
5714 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5715 ctx->ac.i32, "");
5716 }
5717
5718 args->compr = 1;
5719 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5720 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5721 break;
5722
5723 case V_028714_SPI_SHADER_SNORM16_ABGR:
5724 for (unsigned chan = 0; chan < 4; chan++) {
5725 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5726 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5727 LLVMConstReal(ctx->ac.f32, 32767), "");
5728
5729 /* If positive, add 0.5, else add -0.5. */
5730 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5731 LLVMBuildSelect(ctx->builder,
5732 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5733 val[chan], ctx->ac.f32_0, ""),
5734 LLVMConstReal(ctx->ac.f32, 0.5),
5735 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5736 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5737 }
5738
5739 args->compr = 1;
5740 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5741 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5742 break;
5743
5744 case V_028714_SPI_SHADER_UINT16_ABGR: {
5745 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5746 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5747 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5748
5749 for (unsigned chan = 0; chan < 4; chan++) {
5750 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5751 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5752 }
5753
5754 args->compr = 1;
5755 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5756 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5757 break;
5758 }
5759
5760 case V_028714_SPI_SHADER_SINT16_ABGR: {
5761 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5762 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5763 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5764 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5765 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5766 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5767
5768 /* Clamp. */
5769 for (unsigned chan = 0; chan < 4; chan++) {
5770 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5771 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5772 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5773 }
5774
5775 args->compr = 1;
5776 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5777 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5778 break;
5779 }
5780
5781 default:
5782 case V_028714_SPI_SHADER_32_ABGR:
5783 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5784 break;
5785 }
5786 } else
5787 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5788
5789 for (unsigned i = 0; i < 4; ++i)
5790 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5791 }
5792
5793 static void
5794 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5795 bool export_prim_id,
5796 struct ac_vs_output_info *outinfo)
5797 {
5798 uint32_t param_count = 0;
5799 unsigned target;
5800 unsigned pos_idx, num_pos_exports = 0;
5801 struct ac_export_args args, pos_args[4] = {};
5802 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5803 int i;
5804
5805 if (ctx->options->key.has_multiview_view_index) {
5806 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5807 if(!*tmp_out) {
5808 for(unsigned i = 0; i < 4; ++i)
5809 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5810 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5811 }
5812
5813 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5814 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5815 }
5816
5817 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5818 sizeof(outinfo->vs_output_param_offset));
5819
5820 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5821 LLVMValueRef slots[8];
5822 unsigned j;
5823
5824 if (outinfo->cull_dist_mask)
5825 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5826
5827 i = VARYING_SLOT_CLIP_DIST0;
5828 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5829 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5830 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5831
5832 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5833 slots[i] = LLVMGetUndef(ctx->ac.f32);
5834
5835 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5836 target = V_008DFC_SQ_EXP_POS + 3;
5837 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5838 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5839 &args, sizeof(args));
5840 }
5841
5842 target = V_008DFC_SQ_EXP_POS + 2;
5843 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5844 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5845 &args, sizeof(args));
5846
5847 }
5848
5849 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5850 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5851 for (unsigned j = 0; j < 4; j++)
5852 pos_values[j] = LLVMBuildLoad(ctx->builder,
5853 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5854 }
5855 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5856
5857 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5858 outinfo->writes_pointsize = true;
5859 psize_value = LLVMBuildLoad(ctx->builder,
5860 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5861 }
5862
5863 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5864 outinfo->writes_layer = true;
5865 layer_value = LLVMBuildLoad(ctx->builder,
5866 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5867 }
5868
5869 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5870 outinfo->writes_viewport_index = true;
5871 viewport_index_value = LLVMBuildLoad(ctx->builder,
5872 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5873 }
5874
5875 if (outinfo->writes_pointsize ||
5876 outinfo->writes_layer ||
5877 outinfo->writes_viewport_index) {
5878 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5879 (outinfo->writes_layer == true ? 4 : 0));
5880 pos_args[1].valid_mask = 0;
5881 pos_args[1].done = 0;
5882 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5883 pos_args[1].compr = 0;
5884 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5885 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5886 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5887 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5888
5889 if (outinfo->writes_pointsize == true)
5890 pos_args[1].out[0] = psize_value;
5891 if (outinfo->writes_layer == true)
5892 pos_args[1].out[2] = layer_value;
5893 if (outinfo->writes_viewport_index == true) {
5894 if (ctx->options->chip_class >= GFX9) {
5895 /* GFX9 has the layer in out.z[10:0] and the viewport
5896 * index in out.z[19:16].
5897 */
5898 LLVMValueRef v = viewport_index_value;
5899 v = ac_to_integer(&ctx->ac, v);
5900 v = LLVMBuildShl(ctx->builder, v,
5901 LLVMConstInt(ctx->ac.i32, 16, false),
5902 "");
5903 v = LLVMBuildOr(ctx->builder, v,
5904 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5905
5906 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5907 pos_args[1].enabled_channels |= 1 << 2;
5908 } else {
5909 pos_args[1].out[3] = viewport_index_value;
5910 pos_args[1].enabled_channels |= 1 << 3;
5911 }
5912 }
5913 }
5914 for (i = 0; i < 4; i++) {
5915 if (pos_args[i].out[0])
5916 num_pos_exports++;
5917 }
5918
5919 pos_idx = 0;
5920 for (i = 0; i < 4; i++) {
5921 if (!pos_args[i].out[0])
5922 continue;
5923
5924 /* Specify the target we are exporting */
5925 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5926 if (pos_idx == num_pos_exports)
5927 pos_args[i].done = 1;
5928 ac_build_export(&ctx->ac, &pos_args[i]);
5929 }
5930
5931 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5932 LLVMValueRef values[4];
5933 if (!(ctx->output_mask & (1ull << i)))
5934 continue;
5935
5936 for (unsigned j = 0; j < 4; j++)
5937 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5938 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5939
5940 if (i == VARYING_SLOT_LAYER) {
5941 target = V_008DFC_SQ_EXP_PARAM + param_count;
5942 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5943 param_count++;
5944 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5945 target = V_008DFC_SQ_EXP_PARAM + param_count;
5946 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5947 param_count++;
5948 } else if (i >= VARYING_SLOT_VAR0) {
5949 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5950 target = V_008DFC_SQ_EXP_PARAM + param_count;
5951 outinfo->vs_output_param_offset[i] = param_count;
5952 param_count++;
5953 } else
5954 continue;
5955
5956 si_llvm_init_export_args(ctx, values, target, &args);
5957
5958 if (target >= V_008DFC_SQ_EXP_POS &&
5959 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5960 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5961 &args, sizeof(args));
5962 } else {
5963 ac_build_export(&ctx->ac, &args);
5964 }
5965 }
5966
5967 if (export_prim_id) {
5968 LLVMValueRef values[4];
5969 target = V_008DFC_SQ_EXP_PARAM + param_count;
5970 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5971 param_count++;
5972
5973 values[0] = ctx->vs_prim_id;
5974 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5975 ctx->shader_info->vs.vgpr_comp_cnt);
5976 for (unsigned j = 1; j < 4; j++)
5977 values[j] = ctx->ac.f32_0;
5978 si_llvm_init_export_args(ctx, values, target, &args);
5979 ac_build_export(&ctx->ac, &args);
5980 outinfo->export_prim_id = true;
5981 }
5982
5983 outinfo->pos_exports = num_pos_exports;
5984 outinfo->param_exports = param_count;
5985 }
5986
5987 static void
5988 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5989 struct ac_es_output_info *outinfo)
5990 {
5991 int j;
5992 uint64_t max_output_written = 0;
5993 LLVMValueRef lds_base = NULL;
5994
5995 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5996 int param_index;
5997 int length = 4;
5998
5999 if (!(ctx->output_mask & (1ull << i)))
6000 continue;
6001
6002 if (i == VARYING_SLOT_CLIP_DIST0)
6003 length = ctx->num_output_clips + ctx->num_output_culls;
6004
6005 param_index = shader_io_get_unique_index(i);
6006
6007 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6008 }
6009
6010 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6011
6012 if (ctx->ac.chip_class >= GFX9) {
6013 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6014 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6015 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6016 LLVMConstInt(ctx->ac.i32, 24, false),
6017 LLVMConstInt(ctx->ac.i32, 4, false), false);
6018 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6019 LLVMBuildMul(ctx->ac.builder, wave_idx,
6020 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6021 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6022 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6023 }
6024
6025 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6026 LLVMValueRef dw_addr;
6027 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6028 int param_index;
6029 int length = 4;
6030
6031 if (!(ctx->output_mask & (1ull << i)))
6032 continue;
6033
6034 if (i == VARYING_SLOT_CLIP_DIST0)
6035 length = ctx->num_output_clips + ctx->num_output_culls;
6036
6037 param_index = shader_io_get_unique_index(i);
6038
6039 if (lds_base) {
6040 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6041 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6042 "");
6043 }
6044 for (j = 0; j < length; j++) {
6045 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6046 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6047
6048 if (ctx->ac.chip_class >= GFX9) {
6049 ac_lds_store(&ctx->ac, dw_addr,
6050 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6051 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6052 } else {
6053 ac_build_buffer_store_dword(&ctx->ac,
6054 ctx->esgs_ring,
6055 out_val, 1,
6056 NULL, ctx->es2gs_offset,
6057 (4 * param_index + j) * 4,
6058 1, 1, true, true);
6059 }
6060 }
6061 }
6062 }
6063
6064 static void
6065 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6066 {
6067 LLVMValueRef vertex_id = ctx->rel_auto_id;
6068 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6069 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6070 vertex_dw_stride, "");
6071
6072 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6073 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6074 int length = 4;
6075
6076 if (!(ctx->output_mask & (1ull << i)))
6077 continue;
6078
6079 if (i == VARYING_SLOT_CLIP_DIST0)
6080 length = ctx->num_output_clips + ctx->num_output_culls;
6081 int param = shader_io_get_unique_index(i);
6082 mark_tess_output(ctx, false, param);
6083 if (length > 4)
6084 mark_tess_output(ctx, false, param + 1);
6085 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6086 LLVMConstInt(ctx->ac.i32, param * 4, false),
6087 "");
6088 for (unsigned j = 0; j < length; j++) {
6089 ac_lds_store(&ctx->ac, dw_addr,
6090 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6091 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6092 }
6093 }
6094 }
6095
6096 struct ac_build_if_state
6097 {
6098 struct nir_to_llvm_context *ctx;
6099 LLVMValueRef condition;
6100 LLVMBasicBlockRef entry_block;
6101 LLVMBasicBlockRef true_block;
6102 LLVMBasicBlockRef false_block;
6103 LLVMBasicBlockRef merge_block;
6104 };
6105
6106 static LLVMBasicBlockRef
6107 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6108 {
6109 LLVMBasicBlockRef current_block;
6110 LLVMBasicBlockRef next_block;
6111 LLVMBasicBlockRef new_block;
6112
6113 /* get current basic block */
6114 current_block = LLVMGetInsertBlock(ctx->builder);
6115
6116 /* chqeck if there's another block after this one */
6117 next_block = LLVMGetNextBasicBlock(current_block);
6118 if (next_block) {
6119 /* insert the new block before the next block */
6120 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6121 }
6122 else {
6123 /* append new block after current block */
6124 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6125 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6126 }
6127 return new_block;
6128 }
6129
6130 static void
6131 ac_nir_build_if(struct ac_build_if_state *ifthen,
6132 struct nir_to_llvm_context *ctx,
6133 LLVMValueRef condition)
6134 {
6135 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6136
6137 memset(ifthen, 0, sizeof *ifthen);
6138 ifthen->ctx = ctx;
6139 ifthen->condition = condition;
6140 ifthen->entry_block = block;
6141
6142 /* create endif/merge basic block for the phi functions */
6143 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6144
6145 /* create/insert true_block before merge_block */
6146 ifthen->true_block =
6147 LLVMInsertBasicBlockInContext(ctx->context,
6148 ifthen->merge_block,
6149 "if-true-block");
6150
6151 /* successive code goes into the true block */
6152 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6153 }
6154
6155 /**
6156 * End a conditional.
6157 */
6158 static void
6159 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6160 {
6161 LLVMBuilderRef builder = ifthen->ctx->builder;
6162
6163 /* Insert branch to the merge block from current block */
6164 LLVMBuildBr(builder, ifthen->merge_block);
6165
6166 /*
6167 * Now patch in the various branch instructions.
6168 */
6169
6170 /* Insert the conditional branch instruction at the end of entry_block */
6171 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6172 if (ifthen->false_block) {
6173 /* we have an else clause */
6174 LLVMBuildCondBr(builder, ifthen->condition,
6175 ifthen->true_block, ifthen->false_block);
6176 }
6177 else {
6178 /* no else clause */
6179 LLVMBuildCondBr(builder, ifthen->condition,
6180 ifthen->true_block, ifthen->merge_block);
6181 }
6182
6183 /* Resume building code at end of the ifthen->merge_block */
6184 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6185 }
6186
6187 static void
6188 write_tess_factors(struct nir_to_llvm_context *ctx)
6189 {
6190 unsigned stride, outer_comps, inner_comps;
6191 struct ac_build_if_state if_ctx, inner_if_ctx;
6192 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6193 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6194 unsigned tess_inner_index, tess_outer_index;
6195 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6196 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6197 int i;
6198 emit_barrier(&ctx->ac, ctx->stage);
6199
6200 switch (ctx->options->key.tcs.primitive_mode) {
6201 case GL_ISOLINES:
6202 stride = 2;
6203 outer_comps = 2;
6204 inner_comps = 0;
6205 break;
6206 case GL_TRIANGLES:
6207 stride = 4;
6208 outer_comps = 3;
6209 inner_comps = 1;
6210 break;
6211 case GL_QUADS:
6212 stride = 6;
6213 outer_comps = 4;
6214 inner_comps = 2;
6215 break;
6216 default:
6217 return;
6218 }
6219
6220 ac_nir_build_if(&if_ctx, ctx,
6221 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6222 invocation_id, ctx->ac.i32_0, ""));
6223
6224 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6225 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6226
6227 mark_tess_output(ctx, true, tess_inner_index);
6228 mark_tess_output(ctx, true, tess_outer_index);
6229 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6230 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6231 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6232 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6233 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6234
6235 for (i = 0; i < 4; i++) {
6236 inner[i] = LLVMGetUndef(ctx->ac.i32);
6237 outer[i] = LLVMGetUndef(ctx->ac.i32);
6238 }
6239
6240 // LINES reverseal
6241 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6242 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6243 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6244 ctx->ac.i32_1, "");
6245 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6246 } else {
6247 for (i = 0; i < outer_comps; i++) {
6248 outer[i] = out[i] =
6249 ac_lds_load(&ctx->ac, lds_outer);
6250 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6251 ctx->ac.i32_1, "");
6252 }
6253 for (i = 0; i < inner_comps; i++) {
6254 inner[i] = out[outer_comps+i] =
6255 ac_lds_load(&ctx->ac, lds_inner);
6256 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6257 ctx->ac.i32_1, "");
6258 }
6259 }
6260
6261 /* Convert the outputs to vectors for stores. */
6262 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6263 vec1 = NULL;
6264
6265 if (stride > 4)
6266 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6267
6268
6269 buffer = ctx->hs_ring_tess_factor;
6270 tf_base = ctx->tess_factor_offset;
6271 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6272 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6273 unsigned tf_offset = 0;
6274
6275 if (ctx->options->chip_class <= VI) {
6276 ac_nir_build_if(&inner_if_ctx, ctx,
6277 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6278 rel_patch_id, ctx->ac.i32_0, ""));
6279
6280 /* Store the dynamic HS control word. */
6281 ac_build_buffer_store_dword(&ctx->ac, buffer,
6282 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6283 1, ctx->ac.i32_0, tf_base,
6284 0, 1, 0, true, false);
6285 tf_offset += 4;
6286
6287 ac_nir_build_endif(&inner_if_ctx);
6288 }
6289
6290 /* Store the tessellation factors. */
6291 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6292 MIN2(stride, 4), byteoffset, tf_base,
6293 tf_offset, 1, 0, true, false);
6294 if (vec1)
6295 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6296 stride - 4, byteoffset, tf_base,
6297 16 + tf_offset, 1, 0, true, false);
6298
6299 //store to offchip for TES to read - only if TES reads them
6300 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6301 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6302 LLVMValueRef tf_inner_offset;
6303 unsigned param_outer, param_inner;
6304
6305 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6306 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6307 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6308
6309 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6310 util_next_power_of_two(outer_comps));
6311
6312 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6313 outer_comps, tf_outer_offset,
6314 ctx->oc_lds, 0, 1, 0, true, false);
6315 if (inner_comps) {
6316 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6317 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6318 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6319
6320 inner_vec = inner_comps == 1 ? inner[0] :
6321 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6322 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6323 inner_comps, tf_inner_offset,
6324 ctx->oc_lds, 0, 1, 0, true, false);
6325 }
6326 }
6327 ac_nir_build_endif(&if_ctx);
6328 }
6329
6330 static void
6331 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6332 {
6333 write_tess_factors(ctx);
6334 }
6335
6336 static bool
6337 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6338 LLVMValueRef *color, unsigned param, bool is_last,
6339 struct ac_export_args *args)
6340 {
6341 /* Export */
6342 si_llvm_init_export_args(ctx, color, param,
6343 args);
6344
6345 if (is_last) {
6346 args->valid_mask = 1; /* whether the EXEC mask is valid */
6347 args->done = 1; /* DONE bit */
6348 } else if (!args->enabled_channels)
6349 return false; /* unnecessary NULL export */
6350
6351 return true;
6352 }
6353
6354 static void
6355 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6356 LLVMValueRef depth, LLVMValueRef stencil,
6357 LLVMValueRef samplemask)
6358 {
6359 struct ac_export_args args;
6360
6361 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6362
6363 ac_build_export(&ctx->ac, &args);
6364 }
6365
6366 static void
6367 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6368 {
6369 unsigned index = 0;
6370 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6371 struct ac_export_args color_args[8];
6372
6373 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6374 LLVMValueRef values[4];
6375
6376 if (!(ctx->output_mask & (1ull << i)))
6377 continue;
6378
6379 if (i == FRAG_RESULT_DEPTH) {
6380 ctx->shader_info->fs.writes_z = true;
6381 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6382 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6383 } else if (i == FRAG_RESULT_STENCIL) {
6384 ctx->shader_info->fs.writes_stencil = true;
6385 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6386 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6387 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6388 ctx->shader_info->fs.writes_sample_mask = true;
6389 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6390 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6391 } else {
6392 bool last = false;
6393 for (unsigned j = 0; j < 4; j++)
6394 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6395 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6396
6397 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6398 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6399
6400 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6401 if (ret)
6402 index++;
6403 }
6404 }
6405
6406 for (unsigned i = 0; i < index; i++)
6407 ac_build_export(&ctx->ac, &color_args[i]);
6408 if (depth || stencil || samplemask)
6409 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6410 else if (!index) {
6411 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6412 ac_build_export(&ctx->ac, &color_args[0]);
6413 }
6414 }
6415
6416 static void
6417 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6418 {
6419 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6420 }
6421
6422 static void
6423 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6424 LLVMValueRef *addrs)
6425 {
6426 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6427
6428 switch (ctx->stage) {
6429 case MESA_SHADER_VERTEX:
6430 if (ctx->options->key.vs.as_ls)
6431 handle_ls_outputs_post(ctx);
6432 else if (ctx->options->key.vs.as_es)
6433 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6434 else
6435 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6436 &ctx->shader_info->vs.outinfo);
6437 break;
6438 case MESA_SHADER_FRAGMENT:
6439 handle_fs_outputs_post(ctx);
6440 break;
6441 case MESA_SHADER_GEOMETRY:
6442 emit_gs_epilogue(ctx);
6443 break;
6444 case MESA_SHADER_TESS_CTRL:
6445 handle_tcs_outputs_post(ctx);
6446 break;
6447 case MESA_SHADER_TESS_EVAL:
6448 if (ctx->options->key.tes.as_es)
6449 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6450 else
6451 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6452 &ctx->shader_info->tes.outinfo);
6453 break;
6454 default:
6455 break;
6456 }
6457 }
6458
6459 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6460 {
6461 LLVMPassManagerRef passmgr;
6462 /* Create the pass manager */
6463 passmgr = LLVMCreateFunctionPassManagerForModule(
6464 ctx->module);
6465
6466 /* This pass should eliminate all the load and store instructions */
6467 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6468
6469 /* Add some optimization passes */
6470 LLVMAddScalarReplAggregatesPass(passmgr);
6471 LLVMAddLICMPass(passmgr);
6472 LLVMAddAggressiveDCEPass(passmgr);
6473 LLVMAddCFGSimplificationPass(passmgr);
6474 LLVMAddInstructionCombiningPass(passmgr);
6475
6476 /* Run the pass */
6477 LLVMInitializeFunctionPassManager(passmgr);
6478 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6479 LLVMFinalizeFunctionPassManager(passmgr);
6480
6481 LLVMDisposeBuilder(ctx->builder);
6482 LLVMDisposePassManager(passmgr);
6483 }
6484
6485 static void
6486 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6487 {
6488 struct ac_vs_output_info *outinfo;
6489
6490 switch (ctx->stage) {
6491 case MESA_SHADER_FRAGMENT:
6492 case MESA_SHADER_COMPUTE:
6493 case MESA_SHADER_TESS_CTRL:
6494 case MESA_SHADER_GEOMETRY:
6495 return;
6496 case MESA_SHADER_VERTEX:
6497 if (ctx->options->key.vs.as_ls ||
6498 ctx->options->key.vs.as_es)
6499 return;
6500 outinfo = &ctx->shader_info->vs.outinfo;
6501 break;
6502 case MESA_SHADER_TESS_EVAL:
6503 if (ctx->options->key.vs.as_es)
6504 return;
6505 outinfo = &ctx->shader_info->tes.outinfo;
6506 break;
6507 default:
6508 unreachable("Unhandled shader type");
6509 }
6510
6511 ac_optimize_vs_outputs(&ctx->ac,
6512 ctx->main_function,
6513 outinfo->vs_output_param_offset,
6514 VARYING_SLOT_MAX,
6515 &outinfo->param_exports);
6516 }
6517
6518 static void
6519 ac_setup_rings(struct nir_to_llvm_context *ctx)
6520 {
6521 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6522 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6523 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6524 }
6525
6526 if (ctx->is_gs_copy_shader) {
6527 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6528 }
6529 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6530 LLVMValueRef tmp;
6531 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6532 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6533
6534 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6535
6536 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6537 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6538 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6539 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6540 }
6541
6542 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6543 ctx->stage == MESA_SHADER_TESS_EVAL) {
6544 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6545 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6546 }
6547 }
6548
6549 static unsigned
6550 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6551 const struct nir_shader *nir)
6552 {
6553 switch (nir->info.stage) {
6554 case MESA_SHADER_TESS_CTRL:
6555 return chip_class >= CIK ? 128 : 64;
6556 case MESA_SHADER_GEOMETRY:
6557 return chip_class >= GFX9 ? 128 : 64;
6558 case MESA_SHADER_COMPUTE:
6559 break;
6560 default:
6561 return 0;
6562 }
6563
6564 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6565 nir->info.cs.local_size[1] *
6566 nir->info.cs.local_size[2];
6567 return max_workgroup_size;
6568 }
6569
6570 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6571 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6572 {
6573 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6574 LLVMConstInt(ctx->ac.i32, 8, false),
6575 LLVMConstInt(ctx->ac.i32, 8, false), false);
6576 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6577 ctx->ac.i32_0, "");
6578 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6579 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6580 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6581 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6582 }
6583
6584 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6585 {
6586 for(int i = 5; i >= 0; --i) {
6587 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6588 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6589 LLVMConstInt(ctx->ac.i32, 16, false), false);
6590 }
6591
6592 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6593 LLVMConstInt(ctx->ac.i32, 16, false),
6594 LLVMConstInt(ctx->ac.i32, 8, false), false);
6595 }
6596
6597 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6598 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6599 {
6600 struct ac_nir_context ctx = {};
6601 struct nir_function *func;
6602
6603 ctx.ac = *ac;
6604 ctx.abi = abi;
6605
6606 ctx.nctx = nctx;
6607 if (nctx)
6608 nctx->nir = &ctx;
6609
6610 ctx.stage = nir->info.stage;
6611
6612 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6613
6614 nir_foreach_variable(variable, &nir->outputs)
6615 handle_shader_output_decl(&ctx, nir, variable);
6616
6617 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6618 _mesa_key_pointer_equal);
6619 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6620 _mesa_key_pointer_equal);
6621 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6622 _mesa_key_pointer_equal);
6623
6624 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6625
6626 setup_locals(&ctx, func);
6627
6628 if (nir->info.stage == MESA_SHADER_COMPUTE)
6629 setup_shared(&ctx, nir);
6630
6631 visit_cf_list(&ctx, &func->impl->body);
6632 phi_post_pass(&ctx);
6633
6634 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6635 ctx.outputs);
6636
6637 free(ctx.locals);
6638 ralloc_free(ctx.defs);
6639 ralloc_free(ctx.phis);
6640 ralloc_free(ctx.vars);
6641
6642 if (nctx)
6643 nctx->nir = NULL;
6644 }
6645
6646 static
6647 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6648 struct nir_shader *const *shaders,
6649 int shader_count,
6650 struct ac_shader_variant_info *shader_info,
6651 const struct ac_nir_compiler_options *options)
6652 {
6653 struct nir_to_llvm_context ctx = {0};
6654 unsigned i;
6655 ctx.options = options;
6656 ctx.shader_info = shader_info;
6657 ctx.context = LLVMContextCreate();
6658 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6659
6660 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6661 options->family);
6662 ctx.ac.module = ctx.module;
6663 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6664
6665 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6666 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6667 LLVMSetDataLayout(ctx.module, data_layout_str);
6668 LLVMDisposeTargetData(data_layout);
6669 LLVMDisposeMessage(data_layout_str);
6670
6671 enum ac_float_mode float_mode =
6672 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6673 AC_FLOAT_MODE_DEFAULT;
6674
6675 ctx.builder = ac_create_builder(ctx.context, float_mode);
6676 ctx.ac.builder = ctx.builder;
6677
6678 memset(shader_info, 0, sizeof(*shader_info));
6679
6680 for(int i = 0; i < shader_count; ++i)
6681 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6682
6683 for (i = 0; i < AC_UD_MAX_SETS; i++)
6684 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6685 for (i = 0; i < AC_UD_MAX_UD; i++)
6686 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6687
6688 ctx.max_workgroup_size = 0;
6689 for (int i = 0; i < shader_count; ++i) {
6690 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6691 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6692 shaders[i]));
6693 }
6694
6695 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6696 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6697
6698 ctx.abi.inputs = &ctx.inputs[0];
6699 ctx.abi.emit_outputs = handle_shader_outputs_post;
6700 ctx.abi.emit_vertex = visit_emit_vertex;
6701 ctx.abi.load_ubo = radv_load_ubo;
6702 ctx.abi.load_ssbo = radv_load_ssbo;
6703 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6704 ctx.abi.clamp_shadow_reference = false;
6705
6706 if (shader_count >= 2)
6707 ac_init_exec_full_mask(&ctx.ac);
6708
6709 if (ctx.ac.chip_class == GFX9 &&
6710 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6711 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6712
6713 for(int i = 0; i < shader_count; ++i) {
6714 ctx.stage = shaders[i]->info.stage;
6715 ctx.output_mask = 0;
6716 ctx.tess_outputs_written = 0;
6717 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6718 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6719
6720 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6721 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6722 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6723 ctx.abi.load_inputs = load_gs_input;
6724 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6725 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6726 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6727 ctx.abi.load_tess_varyings = load_tcs_varyings;
6728 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6729 ctx.abi.store_tcs_outputs = store_tcs_output;
6730 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6731 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6732 ctx.abi.load_tess_varyings = load_tes_input;
6733 ctx.abi.load_tess_coord = load_tess_coord;
6734 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6735 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6736 if (shader_info->info.vs.needs_instance_id) {
6737 if (ctx.options->key.vs.as_ls) {
6738 ctx.shader_info->vs.vgpr_comp_cnt =
6739 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6740 } else {
6741 ctx.shader_info->vs.vgpr_comp_cnt =
6742 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6743 }
6744 }
6745 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6746 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6747 }
6748
6749 if (i)
6750 emit_barrier(&ctx.ac, ctx.stage);
6751
6752 ac_setup_rings(&ctx);
6753
6754 LLVMBasicBlockRef merge_block;
6755 if (shader_count >= 2) {
6756 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6757 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6758 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6759
6760 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6761 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6762 LLVMConstInt(ctx.ac.i32, 8, false), false);
6763 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6764 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6765 thread_id, count, "");
6766 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6767
6768 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6769 }
6770
6771 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6772 handle_fs_inputs(&ctx, shaders[i]);
6773 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6774 handle_vs_inputs(&ctx, shaders[i]);
6775 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6776 prepare_gs_input_vgprs(&ctx);
6777
6778 nir_foreach_variable(variable, &shaders[i]->outputs)
6779 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6780
6781 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6782
6783 if (shader_count >= 2) {
6784 LLVMBuildBr(ctx.ac.builder, merge_block);
6785 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6786 }
6787
6788 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6789 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6790 shaders[i]->info.cull_distance_array_size > 4;
6791 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6792 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6793 shaders[i]->info.gs.vertices_out;
6794 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6795 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6796 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6797 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6798 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6799 }
6800 }
6801
6802 LLVMBuildRetVoid(ctx.builder);
6803
6804 ac_llvm_finalize_module(&ctx);
6805
6806 if (shader_count == 1)
6807 ac_nir_eliminate_const_vs_outputs(&ctx);
6808
6809 return ctx.module;
6810 }
6811
6812 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6813 {
6814 unsigned *retval = (unsigned *)context;
6815 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6816 char *description = LLVMGetDiagInfoDescription(di);
6817
6818 if (severity == LLVMDSError) {
6819 *retval = 1;
6820 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6821 description);
6822 }
6823
6824 LLVMDisposeMessage(description);
6825 }
6826
6827 static unsigned ac_llvm_compile(LLVMModuleRef M,
6828 struct ac_shader_binary *binary,
6829 LLVMTargetMachineRef tm)
6830 {
6831 unsigned retval = 0;
6832 char *err;
6833 LLVMContextRef llvm_ctx;
6834 LLVMMemoryBufferRef out_buffer;
6835 unsigned buffer_size;
6836 const char *buffer_data;
6837 LLVMBool mem_err;
6838
6839 /* Setup Diagnostic Handler*/
6840 llvm_ctx = LLVMGetModuleContext(M);
6841
6842 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6843 &retval);
6844
6845 /* Compile IR*/
6846 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6847 &err, &out_buffer);
6848
6849 /* Process Errors/Warnings */
6850 if (mem_err) {
6851 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6852 free(err);
6853 retval = 1;
6854 goto out;
6855 }
6856
6857 /* Extract Shader Code*/
6858 buffer_size = LLVMGetBufferSize(out_buffer);
6859 buffer_data = LLVMGetBufferStart(out_buffer);
6860
6861 ac_elf_read(buffer_data, buffer_size, binary);
6862
6863 /* Clean up */
6864 LLVMDisposeMemoryBuffer(out_buffer);
6865
6866 out:
6867 return retval;
6868 }
6869
6870 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6871 LLVMModuleRef llvm_module,
6872 struct ac_shader_binary *binary,
6873 struct ac_shader_config *config,
6874 struct ac_shader_variant_info *shader_info,
6875 gl_shader_stage stage,
6876 bool dump_shader, bool supports_spill)
6877 {
6878 if (dump_shader)
6879 ac_dump_module(llvm_module);
6880
6881 memset(binary, 0, sizeof(*binary));
6882 int v = ac_llvm_compile(llvm_module, binary, tm);
6883 if (v) {
6884 fprintf(stderr, "compile failed\n");
6885 }
6886
6887 if (dump_shader)
6888 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6889
6890 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6891
6892 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6893 LLVMDisposeModule(llvm_module);
6894 LLVMContextDispose(ctx);
6895
6896 if (stage == MESA_SHADER_FRAGMENT) {
6897 shader_info->num_input_vgprs = 0;
6898 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6899 shader_info->num_input_vgprs += 2;
6900 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6901 shader_info->num_input_vgprs += 2;
6902 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6903 shader_info->num_input_vgprs += 2;
6904 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6905 shader_info->num_input_vgprs += 3;
6906 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6907 shader_info->num_input_vgprs += 2;
6908 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6909 shader_info->num_input_vgprs += 2;
6910 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6911 shader_info->num_input_vgprs += 2;
6912 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6913 shader_info->num_input_vgprs += 1;
6914 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6915 shader_info->num_input_vgprs += 1;
6916 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6917 shader_info->num_input_vgprs += 1;
6918 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6919 shader_info->num_input_vgprs += 1;
6920 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6921 shader_info->num_input_vgprs += 1;
6922 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6923 shader_info->num_input_vgprs += 1;
6924 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6925 shader_info->num_input_vgprs += 1;
6926 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6927 shader_info->num_input_vgprs += 1;
6928 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6929 shader_info->num_input_vgprs += 1;
6930 }
6931 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6932
6933 /* +3 for scratch wave offset and VCC */
6934 config->num_sgprs = MAX2(config->num_sgprs,
6935 shader_info->num_input_sgprs + 3);
6936
6937 /* Enable 64-bit and 16-bit denormals, because there is no performance
6938 * cost.
6939 *
6940 * If denormals are enabled, all floating-point output modifiers are
6941 * ignored.
6942 *
6943 * Don't enable denormals for 32-bit floats, because:
6944 * - Floating-point output modifiers would be ignored by the hw.
6945 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6946 * have to stop using those.
6947 * - SI & CI would be very slow.
6948 */
6949 config->float_mode |= V_00B028_FP_64_DENORMS;
6950 }
6951
6952 static void
6953 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6954 {
6955 switch (nir->info.stage) {
6956 case MESA_SHADER_COMPUTE:
6957 for (int i = 0; i < 3; ++i)
6958 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6959 break;
6960 case MESA_SHADER_FRAGMENT:
6961 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6962 break;
6963 case MESA_SHADER_GEOMETRY:
6964 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6965 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6966 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6967 shader_info->gs.invocations = nir->info.gs.invocations;
6968 break;
6969 case MESA_SHADER_TESS_EVAL:
6970 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6971 shader_info->tes.spacing = nir->info.tess.spacing;
6972 shader_info->tes.ccw = nir->info.tess.ccw;
6973 shader_info->tes.point_mode = nir->info.tess.point_mode;
6974 shader_info->tes.as_es = options->key.tes.as_es;
6975 break;
6976 case MESA_SHADER_TESS_CTRL:
6977 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6978 break;
6979 case MESA_SHADER_VERTEX:
6980 shader_info->vs.as_es = options->key.vs.as_es;
6981 shader_info->vs.as_ls = options->key.vs.as_ls;
6982 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6983 if (options->key.vs.as_ls)
6984 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6985 break;
6986 default:
6987 break;
6988 }
6989 }
6990
6991 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6992 struct ac_shader_binary *binary,
6993 struct ac_shader_config *config,
6994 struct ac_shader_variant_info *shader_info,
6995 struct nir_shader *const *nir,
6996 int nir_count,
6997 const struct ac_nir_compiler_options *options,
6998 bool dump_shader)
6999 {
7000
7001 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7002 options);
7003
7004 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7005 for (int i = 0; i < nir_count; ++i)
7006 ac_fill_shader_info(shader_info, nir[i], options);
7007
7008 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7009 if (options->chip_class == GFX9) {
7010 if (nir_count == 2 &&
7011 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7012 shader_info->gs.es_type = nir[0]->info.stage;
7013 }
7014 }
7015 }
7016
7017 static void
7018 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7019 {
7020 LLVMValueRef args[9];
7021 args[0] = ctx->gsvs_ring;
7022 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7023 args[3] = ctx->ac.i32_0;
7024 args[4] = ctx->ac.i32_1; /* OFFEN */
7025 args[5] = ctx->ac.i32_0; /* IDXEN */
7026 args[6] = ctx->ac.i32_1; /* GLC */
7027 args[7] = ctx->ac.i32_1; /* SLC */
7028 args[8] = ctx->ac.i32_0; /* TFE */
7029
7030 int idx = 0;
7031
7032 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7033 int length = 4;
7034 int slot = idx;
7035 int slot_inc = 1;
7036 if (!(ctx->output_mask & (1ull << i)))
7037 continue;
7038
7039 if (i == VARYING_SLOT_CLIP_DIST0) {
7040 /* unpack clip and cull from a single set of slots */
7041 length = ctx->num_output_clips + ctx->num_output_culls;
7042 if (length > 4)
7043 slot_inc = 2;
7044 }
7045
7046 for (unsigned j = 0; j < length; j++) {
7047 LLVMValueRef value;
7048 args[2] = LLVMConstInt(ctx->ac.i32,
7049 (slot * 4 + j) *
7050 ctx->gs_max_out_vertices * 16 * 4, false);
7051
7052 value = ac_build_intrinsic(&ctx->ac,
7053 "llvm.SI.buffer.load.dword.i32.i32",
7054 ctx->ac.i32, args, 9,
7055 AC_FUNC_ATTR_READONLY |
7056 AC_FUNC_ATTR_LEGACY);
7057
7058 LLVMBuildStore(ctx->builder,
7059 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7060 }
7061 idx += slot_inc;
7062 }
7063 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7064 }
7065
7066 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7067 struct nir_shader *geom_shader,
7068 struct ac_shader_binary *binary,
7069 struct ac_shader_config *config,
7070 struct ac_shader_variant_info *shader_info,
7071 const struct ac_nir_compiler_options *options,
7072 bool dump_shader)
7073 {
7074 struct nir_to_llvm_context ctx = {0};
7075 ctx.context = LLVMContextCreate();
7076 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7077 ctx.options = options;
7078 ctx.shader_info = shader_info;
7079
7080 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7081 options->family);
7082 ctx.ac.module = ctx.module;
7083
7084 ctx.is_gs_copy_shader = true;
7085 LLVMSetTarget(ctx.module, "amdgcn--");
7086
7087 enum ac_float_mode float_mode =
7088 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7089 AC_FLOAT_MODE_DEFAULT;
7090
7091 ctx.builder = ac_create_builder(ctx.context, float_mode);
7092 ctx.ac.builder = ctx.builder;
7093 ctx.stage = MESA_SHADER_VERTEX;
7094
7095 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7096
7097 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7098 ac_setup_rings(&ctx);
7099
7100 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7101 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7102
7103 struct ac_nir_context nir_ctx = {};
7104 nir_ctx.ac = ctx.ac;
7105 nir_ctx.abi = &ctx.abi;
7106
7107 nir_ctx.nctx = &ctx;
7108 ctx.nir = &nir_ctx;
7109
7110 nir_foreach_variable(variable, &geom_shader->outputs) {
7111 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7112 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7113 }
7114
7115 ac_gs_copy_shader_emit(&ctx);
7116
7117 ctx.nir = NULL;
7118
7119 LLVMBuildRetVoid(ctx.builder);
7120
7121 ac_llvm_finalize_module(&ctx);
7122
7123 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7124 MESA_SHADER_VERTEX,
7125 dump_shader, options->supports_spill);
7126 }