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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "no-signed-zeros-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
547 gl_shader_stage stage)
548 {
549 switch (stage) {
550 case MESA_SHADER_VERTEX:
551 if (ctx->shader_info->info.needs_multiview_view_index ||
552 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
553 return true;
554 break;
555 case MESA_SHADER_TESS_EVAL:
556 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
557 return true;
558 case MESA_SHADER_GEOMETRY:
559 case MESA_SHADER_TESS_CTRL:
560 if (ctx->shader_info->info.needs_multiview_view_index)
561 return true;
562 default:
563 break;
564 }
565 return false;
566 }
567
568 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
569 gl_shader_stage stage,
570 bool needs_view_index,
571 struct user_sgpr_info *user_sgpr_info)
572 {
573 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
574
575 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
576 if (stage == MESA_SHADER_GEOMETRY ||
577 stage == MESA_SHADER_VERTEX ||
578 stage == MESA_SHADER_TESS_CTRL ||
579 stage == MESA_SHADER_TESS_EVAL ||
580 ctx->is_gs_copy_shader)
581 user_sgpr_info->need_ring_offsets = true;
582
583 if (stage == MESA_SHADER_FRAGMENT &&
584 ctx->shader_info->info.ps.needs_sample_positions)
585 user_sgpr_info->need_ring_offsets = true;
586
587 /* 2 user sgprs will nearly always be allocated for scratch/rings */
588 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
589 user_sgpr_info->sgpr_count += 2;
590 }
591
592 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
593 switch (stage) {
594 case MESA_SHADER_COMPUTE:
595 if (ctx->shader_info->info.cs.uses_grid_size)
596 user_sgpr_info->sgpr_count += 3;
597 break;
598 case MESA_SHADER_FRAGMENT:
599 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
600 break;
601 case MESA_SHADER_VERTEX:
602 if (!ctx->is_gs_copy_shader) {
603 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
604 if (ctx->shader_info->info.vs.needs_draw_id) {
605 user_sgpr_info->sgpr_count += 3;
606 } else {
607 user_sgpr_info->sgpr_count += 2;
608 }
609 }
610 if (ctx->options->key.vs.as_ls)
611 user_sgpr_info->sgpr_count++;
612 break;
613 case MESA_SHADER_TESS_CTRL:
614 user_sgpr_info->sgpr_count += 4;
615 break;
616 case MESA_SHADER_TESS_EVAL:
617 user_sgpr_info->sgpr_count += 1;
618 break;
619 case MESA_SHADER_GEOMETRY:
620 user_sgpr_info->sgpr_count += 2;
621 break;
622 default:
623 break;
624 }
625
626 if (needs_view_index)
627 user_sgpr_info->sgpr_count++;
628
629 if (ctx->shader_info->info.loads_push_constants)
630 user_sgpr_info->sgpr_count += 2;
631
632 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
633 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
634
635 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
636 user_sgpr_info->sgpr_count += 2;
637 user_sgpr_info->indirect_all_descriptor_sets = true;
638 } else {
639 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
640 }
641 }
642
643 static void
644 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
645 gl_shader_stage stage,
646 bool has_previous_stage,
647 gl_shader_stage previous_stage,
648 const struct user_sgpr_info *user_sgpr_info,
649 struct arg_info *args,
650 LLVMValueRef *desc_sets)
651 {
652 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
653 unsigned num_sets = ctx->options->layout ?
654 ctx->options->layout->num_sets : 0;
655 unsigned stage_mask = 1 << stage;
656
657 if (has_previous_stage)
658 stage_mask |= 1 << previous_stage;
659
660 /* 1 for each descriptor set */
661 if (!user_sgpr_info->indirect_all_descriptor_sets) {
662 for (unsigned i = 0; i < num_sets; ++i) {
663 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
664 add_array_arg(args, type,
665 &ctx->descriptor_sets[i]);
666 }
667 }
668 } else {
669 add_array_arg(args, const_array(type, 32), desc_sets);
670 }
671
672 if (ctx->shader_info->info.loads_push_constants) {
673 /* 1 for push constants and dynamic descriptors */
674 add_array_arg(args, type, &ctx->push_constants);
675 }
676 }
677
678 static void
679 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
680 gl_shader_stage stage,
681 bool has_previous_stage,
682 gl_shader_stage previous_stage,
683 struct arg_info *args)
684 {
685 if (!ctx->is_gs_copy_shader &&
686 (stage == MESA_SHADER_VERTEX ||
687 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
688 if (ctx->shader_info->info.vs.has_vertex_buffers) {
689 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
690 &ctx->vertex_buffers);
691 }
692 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
693 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
694 if (ctx->shader_info->info.vs.needs_draw_id) {
695 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
696 }
697 }
698 }
699
700 static void
701 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
702 {
703 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
704 if (!ctx->is_gs_copy_shader) {
705 if (ctx->options->key.vs.as_ls) {
706 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
707 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
708 } else {
709 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
710 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
711 }
712 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
713 }
714 }
715
716 static void
717 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
718 {
719 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
720 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
721 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
722 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
723 }
724
725 static void
726 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
727 bool has_previous_stage, gl_shader_stage previous_stage,
728 const struct user_sgpr_info *user_sgpr_info,
729 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
730 {
731 unsigned num_sets = ctx->options->layout ?
732 ctx->options->layout->num_sets : 0;
733 unsigned stage_mask = 1 << stage;
734
735 if (has_previous_stage)
736 stage_mask |= 1 << previous_stage;
737
738 if (!user_sgpr_info->indirect_all_descriptor_sets) {
739 for (unsigned i = 0; i < num_sets; ++i) {
740 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
741 set_loc_desc(ctx, i, user_sgpr_idx, 0);
742 } else
743 ctx->descriptor_sets[i] = NULL;
744 }
745 } else {
746 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
747 user_sgpr_idx, 2);
748
749 for (unsigned i = 0; i < num_sets; ++i) {
750 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
751 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
752 ctx->descriptor_sets[i] =
753 ac_build_load_to_sgpr(&ctx->ac,
754 desc_sets,
755 LLVMConstInt(ctx->ac.i32, i, false));
756
757 } else
758 ctx->descriptor_sets[i] = NULL;
759 }
760 ctx->shader_info->need_indirect_descriptor_sets = true;
761 }
762
763 if (ctx->shader_info->info.loads_push_constants) {
764 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
765 }
766 }
767
768 static void
769 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
770 gl_shader_stage stage, bool has_previous_stage,
771 gl_shader_stage previous_stage,
772 uint8_t *user_sgpr_idx)
773 {
774 if (!ctx->is_gs_copy_shader &&
775 (stage == MESA_SHADER_VERTEX ||
776 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
777 if (ctx->shader_info->info.vs.has_vertex_buffers) {
778 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
779 user_sgpr_idx, 2);
780 }
781
782 unsigned vs_num = 2;
783 if (ctx->shader_info->info.vs.needs_draw_id)
784 vs_num++;
785
786 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
787 user_sgpr_idx, vs_num);
788 }
789 }
790
791 static void create_function(struct nir_to_llvm_context *ctx,
792 gl_shader_stage stage,
793 bool has_previous_stage,
794 gl_shader_stage previous_stage)
795 {
796 uint8_t user_sgpr_idx;
797 struct user_sgpr_info user_sgpr_info;
798 struct arg_info args = {};
799 LLVMValueRef desc_sets;
800 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
801 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
802
803 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
804 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
805 &ctx->ring_offsets);
806 }
807
808 switch (stage) {
809 case MESA_SHADER_COMPUTE:
810 declare_global_input_sgprs(ctx, stage, has_previous_stage,
811 previous_stage, &user_sgpr_info,
812 &args, &desc_sets);
813
814 if (ctx->shader_info->info.cs.uses_grid_size) {
815 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
816 &ctx->num_work_groups);
817 }
818
819 for (int i = 0; i < 3; i++) {
820 ctx->workgroup_ids[i] = NULL;
821 if (ctx->shader_info->info.cs.uses_block_id[i]) {
822 add_arg(&args, ARG_SGPR, ctx->ac.i32,
823 &ctx->workgroup_ids[i]);
824 }
825 }
826
827 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
829 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
830 &ctx->local_invocation_ids);
831 break;
832 case MESA_SHADER_VERTEX:
833 declare_global_input_sgprs(ctx, stage, has_previous_stage,
834 previous_stage, &user_sgpr_info,
835 &args, &desc_sets);
836 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
837 previous_stage, &args);
838
839 if (needs_view_index)
840 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
841 if (ctx->options->key.vs.as_es)
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->es2gs_offset);
844 else if (ctx->options->key.vs.as_ls)
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->ls_out_layout);
847
848 declare_vs_input_vgprs(ctx, &args);
849 break;
850 case MESA_SHADER_TESS_CTRL:
851 if (has_previous_stage) {
852 // First 6 system regs
853 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->merged_wave_info);
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->tess_factor_offset);
858
859 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
860 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
861 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
862
863 declare_global_input_sgprs(ctx, stage,
864 has_previous_stage,
865 previous_stage,
866 &user_sgpr_info, &args,
867 &desc_sets);
868 declare_vs_specific_input_sgprs(ctx, stage,
869 has_previous_stage,
870 previous_stage, &args);
871
872 add_arg(&args, ARG_SGPR, ctx->ac.i32,
873 &ctx->ls_out_layout);
874
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_offchip_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_out_offsets);
879 add_arg(&args, ARG_SGPR, ctx->ac.i32,
880 &ctx->tcs_out_layout);
881 add_arg(&args, ARG_SGPR, ctx->ac.i32,
882 &ctx->tcs_in_layout);
883 if (needs_view_index)
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->view_index);
886
887 add_arg(&args, ARG_VGPR, ctx->ac.i32,
888 &ctx->abi.tcs_patch_id);
889 add_arg(&args, ARG_VGPR, ctx->ac.i32,
890 &ctx->abi.tcs_rel_ids);
891
892 declare_vs_input_vgprs(ctx, &args);
893 } else {
894 declare_global_input_sgprs(ctx, stage,
895 has_previous_stage,
896 previous_stage,
897 &user_sgpr_info, &args,
898 &desc_sets);
899
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->tcs_offchip_layout);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->tcs_out_offsets);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->tcs_out_layout);
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->tcs_in_layout);
908 if (needs_view_index)
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->view_index);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->tess_factor_offset);
915 add_arg(&args, ARG_VGPR, ctx->ac.i32,
916 &ctx->abi.tcs_patch_id);
917 add_arg(&args, ARG_VGPR, ctx->ac.i32,
918 &ctx->abi.tcs_rel_ids);
919 }
920 break;
921 case MESA_SHADER_TESS_EVAL:
922 declare_global_input_sgprs(ctx, stage, has_previous_stage,
923 previous_stage, &user_sgpr_info,
924 &args, &desc_sets);
925
926 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
927 if (needs_view_index)
928 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
929
930 if (ctx->options->key.tes.as_es) {
931 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
932 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->es2gs_offset);
935 } else {
936 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
938 }
939 declare_tes_input_vgprs(ctx, &args);
940 break;
941 case MESA_SHADER_GEOMETRY:
942 if (has_previous_stage) {
943 // First 6 system regs
944 add_arg(&args, ARG_SGPR, ctx->ac.i32,
945 &ctx->gs2vs_offset);
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->merged_wave_info);
948 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
949
950 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
951 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
952 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
953
954 declare_global_input_sgprs(ctx, stage,
955 has_previous_stage,
956 previous_stage,
957 &user_sgpr_info, &args,
958 &desc_sets);
959
960 if (previous_stage == MESA_SHADER_TESS_EVAL) {
961 add_arg(&args, ARG_SGPR, ctx->ac.i32,
962 &ctx->tcs_offchip_layout);
963 } else {
964 declare_vs_specific_input_sgprs(ctx, stage,
965 has_previous_stage,
966 previous_stage,
967 &args);
968 }
969
970 add_arg(&args, ARG_SGPR, ctx->ac.i32,
971 &ctx->gsvs_ring_stride);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_num_entries);
974 if (needs_view_index)
975 add_arg(&args, ARG_SGPR, ctx->ac.i32,
976 &ctx->view_index);
977
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[0]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->abi.gs_prim_id);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->abi.gs_invocation_id);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988
989 if (previous_stage == MESA_SHADER_VERTEX) {
990 declare_vs_input_vgprs(ctx, &args);
991 } else {
992 declare_tes_input_vgprs(ctx, &args);
993 }
994 } else {
995 declare_global_input_sgprs(ctx, stage,
996 has_previous_stage,
997 previous_stage,
998 &user_sgpr_info, &args,
999 &desc_sets);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1002 &ctx->gsvs_ring_stride);
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1004 &ctx->gsvs_num_entries);
1005 if (needs_view_index)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->view_index);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1010 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1011 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1012 &ctx->gs_vtx_offset[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1014 &ctx->gs_vtx_offset[1]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1016 &ctx->abi.gs_prim_id);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1018 &ctx->gs_vtx_offset[2]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1020 &ctx->gs_vtx_offset[3]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1022 &ctx->gs_vtx_offset[4]);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1024 &ctx->gs_vtx_offset[5]);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1026 &ctx->abi.gs_invocation_id);
1027 }
1028 break;
1029 case MESA_SHADER_FRAGMENT:
1030 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1031 previous_stage, &user_sgpr_info,
1032 &args, &desc_sets);
1033
1034 if (ctx->shader_info->info.ps.needs_sample_positions)
1035 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1036 &ctx->sample_pos_offset);
1037
1038 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1039 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1040 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1041 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1042 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1043 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1044 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1045 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1046 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1047 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1048 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1049 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1050 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1051 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1052 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1053 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1054 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1055 break;
1056 default:
1057 unreachable("Shader stage not implemented");
1058 }
1059
1060 ctx->main_function = create_llvm_function(
1061 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1062 ctx->max_workgroup_size,
1063 ctx->options->unsafe_math);
1064 set_llvm_calling_convention(ctx->main_function, stage);
1065
1066
1067 ctx->shader_info->num_input_vgprs = 0;
1068 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1069
1070 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1071
1072 if (ctx->stage != MESA_SHADER_FRAGMENT)
1073 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1074
1075 assign_arguments(ctx->main_function, &args);
1076
1077 user_sgpr_idx = 0;
1078
1079 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1080 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1081 &user_sgpr_idx, 2);
1082 if (ctx->options->supports_spill) {
1083 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1084 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1085 NULL, 0, AC_FUNC_ATTR_READNONE);
1086 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1087 const_array(ctx->ac.v4i32, 16), "");
1088 }
1089 }
1090
1091 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1092 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1093 if (has_previous_stage)
1094 user_sgpr_idx = 0;
1095
1096 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1097 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1098
1099 switch (stage) {
1100 case MESA_SHADER_COMPUTE:
1101 if (ctx->shader_info->info.cs.uses_grid_size) {
1102 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1103 &user_sgpr_idx, 3);
1104 }
1105 break;
1106 case MESA_SHADER_VERTEX:
1107 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1108 previous_stage, &user_sgpr_idx);
1109 if (ctx->view_index)
1110 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1111 if (ctx->options->key.vs.as_ls) {
1112 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1113 &user_sgpr_idx, 1);
1114 }
1115 if (ctx->options->key.vs.as_ls)
1116 ac_declare_lds_as_pointer(&ctx->ac);
1117 break;
1118 case MESA_SHADER_TESS_CTRL:
1119 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1120 previous_stage, &user_sgpr_idx);
1121 if (has_previous_stage)
1122 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1123 &user_sgpr_idx, 1);
1124 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1125 if (ctx->view_index)
1126 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1127 ac_declare_lds_as_pointer(&ctx->ac);
1128 break;
1129 case MESA_SHADER_TESS_EVAL:
1130 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1131 if (ctx->view_index)
1132 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1133 break;
1134 case MESA_SHADER_GEOMETRY:
1135 if (has_previous_stage) {
1136 if (previous_stage == MESA_SHADER_VERTEX)
1137 set_vs_specific_input_locs(ctx, stage,
1138 has_previous_stage,
1139 previous_stage,
1140 &user_sgpr_idx);
1141 else
1142 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1143 &user_sgpr_idx, 1);
1144 }
1145 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1146 &user_sgpr_idx, 2);
1147 if (ctx->view_index)
1148 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1149 if (has_previous_stage)
1150 ac_declare_lds_as_pointer(&ctx->ac);
1151 break;
1152 case MESA_SHADER_FRAGMENT:
1153 if (ctx->shader_info->info.ps.needs_sample_positions) {
1154 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1155 &user_sgpr_idx, 1);
1156 }
1157 break;
1158 default:
1159 unreachable("Shader stage not implemented");
1160 }
1161
1162 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1163 }
1164
1165 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1166 LLVMValueRef value, unsigned count)
1167 {
1168 unsigned num_components = ac_get_llvm_num_components(value);
1169 if (count == num_components)
1170 return value;
1171
1172 LLVMValueRef masks[] = {
1173 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1174 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1175
1176 if (count == 1)
1177 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1178 "");
1179
1180 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1181 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1182 }
1183
1184 static void
1185 build_store_values_extended(struct ac_llvm_context *ac,
1186 LLVMValueRef *values,
1187 unsigned value_count,
1188 unsigned value_stride,
1189 LLVMValueRef vec)
1190 {
1191 LLVMBuilderRef builder = ac->builder;
1192 unsigned i;
1193
1194 for (i = 0; i < value_count; i++) {
1195 LLVMValueRef ptr = values[i * value_stride];
1196 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1197 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1198 LLVMBuildStore(builder, value, ptr);
1199 }
1200 }
1201
1202 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1203 const nir_ssa_def *def)
1204 {
1205 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1206 if (def->num_components > 1) {
1207 type = LLVMVectorType(type, def->num_components);
1208 }
1209 return type;
1210 }
1211
1212 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1213 {
1214 assert(src.is_ssa);
1215 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1216 return (LLVMValueRef)entry->data;
1217 }
1218
1219
1220 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1221 const struct nir_block *b)
1222 {
1223 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1224 return (LLVMBasicBlockRef)entry->data;
1225 }
1226
1227 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1228 nir_alu_src src,
1229 unsigned num_components)
1230 {
1231 LLVMValueRef value = get_src(ctx, src.src);
1232 bool need_swizzle = false;
1233
1234 assert(value);
1235 LLVMTypeRef type = LLVMTypeOf(value);
1236 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1237 ? LLVMGetVectorSize(type)
1238 : 1;
1239
1240 for (unsigned i = 0; i < num_components; ++i) {
1241 assert(src.swizzle[i] < src_components);
1242 if (src.swizzle[i] != i)
1243 need_swizzle = true;
1244 }
1245
1246 if (need_swizzle || num_components != src_components) {
1247 LLVMValueRef masks[] = {
1248 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1249 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1250 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1251 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1252
1253 if (src_components > 1 && num_components == 1) {
1254 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1255 masks[0], "");
1256 } else if (src_components == 1 && num_components > 1) {
1257 LLVMValueRef values[] = {value, value, value, value};
1258 value = ac_build_gather_values(&ctx->ac, values, num_components);
1259 } else {
1260 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1261 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1262 swizzle, "");
1263 }
1264 }
1265 assert(!src.negate);
1266 assert(!src.abs);
1267 return value;
1268 }
1269
1270 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1271 LLVMIntPredicate pred, LLVMValueRef src0,
1272 LLVMValueRef src1)
1273 {
1274 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1275 return LLVMBuildSelect(ctx->builder, result,
1276 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1277 ctx->i32_0, "");
1278 }
1279
1280 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1281 LLVMRealPredicate pred, LLVMValueRef src0,
1282 LLVMValueRef src1)
1283 {
1284 LLVMValueRef result;
1285 src0 = ac_to_float(ctx, src0);
1286 src1 = ac_to_float(ctx, src1);
1287 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1288 return LLVMBuildSelect(ctx->builder, result,
1289 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1290 ctx->i32_0, "");
1291 }
1292
1293 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1294 const char *intrin,
1295 LLVMTypeRef result_type,
1296 LLVMValueRef src0)
1297 {
1298 char name[64];
1299 LLVMValueRef params[] = {
1300 ac_to_float(ctx, src0),
1301 };
1302
1303 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1304 get_elem_bits(ctx, result_type));
1305 assert(length < sizeof(name));
1306 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1307 }
1308
1309 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1310 const char *intrin,
1311 LLVMTypeRef result_type,
1312 LLVMValueRef src0, LLVMValueRef src1)
1313 {
1314 char name[64];
1315 LLVMValueRef params[] = {
1316 ac_to_float(ctx, src0),
1317 ac_to_float(ctx, src1),
1318 };
1319
1320 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1321 get_elem_bits(ctx, result_type));
1322 assert(length < sizeof(name));
1323 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1324 }
1325
1326 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1327 const char *intrin,
1328 LLVMTypeRef result_type,
1329 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1330 {
1331 char name[64];
1332 LLVMValueRef params[] = {
1333 ac_to_float(ctx, src0),
1334 ac_to_float(ctx, src1),
1335 ac_to_float(ctx, src2),
1336 };
1337
1338 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1339 get_elem_bits(ctx, result_type));
1340 assert(length < sizeof(name));
1341 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1342 }
1343
1344 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1346 {
1347 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1348 ctx->i32_0, "");
1349 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1350 }
1351
1352 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1353 LLVMIntPredicate pred,
1354 LLVMValueRef src0, LLVMValueRef src1)
1355 {
1356 return LLVMBuildSelect(ctx->builder,
1357 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1358 src0,
1359 src1, "");
1360
1361 }
1362 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0)
1364 {
1365 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1366 LLVMBuildNeg(ctx->builder, src0, ""));
1367 }
1368
1369 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0,
1371 unsigned bitsize)
1372 {
1373 LLVMValueRef cmp, val, zero, one;
1374 LLVMTypeRef type;
1375
1376 if (bitsize == 32) {
1377 type = ctx->f32;
1378 zero = ctx->f32_0;
1379 one = ctx->f32_1;
1380 } else {
1381 type = ctx->f64;
1382 zero = ctx->f64_0;
1383 one = ctx->f64_1;
1384 }
1385
1386 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1387 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1388 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1389 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1390 return val;
1391 }
1392
1393 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1394 LLVMValueRef src0, unsigned bitsize)
1395 {
1396 LLVMValueRef cmp, val, zero, one;
1397 LLVMTypeRef type;
1398
1399 if (bitsize == 32) {
1400 type = ctx->i32;
1401 zero = ctx->i32_0;
1402 one = ctx->i32_1;
1403 } else {
1404 type = ctx->i64;
1405 zero = ctx->i64_0;
1406 one = ctx->i64_1;
1407 }
1408
1409 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1410 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1411 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1412 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1413 return val;
1414 }
1415
1416 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1417 LLVMValueRef src0)
1418 {
1419 const char *intr = "llvm.floor.f32";
1420 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1421 LLVMValueRef params[] = {
1422 fsrc0,
1423 };
1424 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1425 ctx->f32, params, 1,
1426 AC_FUNC_ATTR_READNONE);
1427 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1428 }
1429
1430 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1431 const char *intrin,
1432 LLVMValueRef src0, LLVMValueRef src1)
1433 {
1434 LLVMTypeRef ret_type;
1435 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1436 LLVMValueRef res;
1437 LLVMValueRef params[] = { src0, src1 };
1438 ret_type = LLVMStructTypeInContext(ctx->context, types,
1439 2, true);
1440
1441 res = ac_build_intrinsic(ctx, intrin, ret_type,
1442 params, 2, AC_FUNC_ATTR_READNONE);
1443
1444 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1445 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1446 return res;
1447 }
1448
1449 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0)
1451 {
1452 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1453 }
1454
1455 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1456 LLVMValueRef src0)
1457 {
1458 src0 = ac_to_float(ctx, src0);
1459 return LLVMBuildSExt(ctx->builder,
1460 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1461 ctx->i32, "");
1462 }
1463
1464 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1465 LLVMValueRef src0,
1466 unsigned bitsize)
1467 {
1468 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1469
1470 if (bitsize == 32)
1471 return result;
1472
1473 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1474 }
1475
1476 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1477 LLVMValueRef src0)
1478 {
1479 return LLVMBuildSExt(ctx->builder,
1480 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1481 ctx->i32, "");
1482 }
1483
1484 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1485 LLVMValueRef src0)
1486 {
1487 LLVMValueRef result;
1488 LLVMValueRef cond = NULL;
1489
1490 src0 = ac_to_float(&ctx->ac, src0);
1491 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1492
1493 if (ctx->options->chip_class >= VI) {
1494 LLVMValueRef args[2];
1495 /* Check if the result is a denormal - and flush to 0 if so. */
1496 args[0] = result;
1497 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1498 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1499 }
1500
1501 /* need to convert back up to f32 */
1502 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1503
1504 if (ctx->options->chip_class >= VI)
1505 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1506 else {
1507 /* for SI/CIK */
1508 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1509 * so compare the result and flush to 0 if it's smaller.
1510 */
1511 LLVMValueRef temp, cond2;
1512 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1513 ctx->ac.f32, result);
1514 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1515 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1516 temp, "");
1517 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1518 temp, ctx->ac.f32_0, "");
1519 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1520 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1521 }
1522 return result;
1523 }
1524
1525 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1526 LLVMValueRef src0, LLVMValueRef src1)
1527 {
1528 LLVMValueRef dst64, result;
1529 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1530 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1531
1532 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1533 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1534 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0, LLVMValueRef src1)
1540 {
1541 LLVMValueRef dst64, result;
1542 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1543 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1544
1545 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1546 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1547 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1548 return result;
1549 }
1550
1551 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1552 bool is_signed,
1553 const LLVMValueRef srcs[3])
1554 {
1555 LLVMValueRef result;
1556 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1557
1558 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1559 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1560 return result;
1561 }
1562
1563 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0, LLVMValueRef src1,
1565 LLVMValueRef src2, LLVMValueRef src3)
1566 {
1567 LLVMValueRef bfi_args[3], result;
1568
1569 bfi_args[0] = LLVMBuildShl(ctx->builder,
1570 LLVMBuildSub(ctx->builder,
1571 LLVMBuildShl(ctx->builder,
1572 ctx->i32_1,
1573 src3, ""),
1574 ctx->i32_1, ""),
1575 src2, "");
1576 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1577 bfi_args[2] = src0;
1578
1579 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1580
1581 /* Calculate:
1582 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1583 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1584 */
1585 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1586 LLVMBuildAnd(ctx->builder, bfi_args[0],
1587 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1588
1589 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1590 return result;
1591 }
1592
1593 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1594 LLVMValueRef src0)
1595 {
1596 LLVMValueRef comp[2];
1597
1598 src0 = ac_to_float(ctx, src0);
1599 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1600 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1601
1602 return ac_build_cvt_pkrtz_f16(ctx, comp);
1603 }
1604
1605 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1606 LLVMValueRef src0)
1607 {
1608 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1609 LLVMValueRef temps[2], result, val;
1610 int i;
1611
1612 for (i = 0; i < 2; i++) {
1613 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1614 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1615 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1616 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1617 }
1618
1619 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1620 ctx->i32_0, "");
1621 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1622 ctx->i32_1, "");
1623 return result;
1624 }
1625
1626 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1627 nir_op op,
1628 LLVMValueRef src0)
1629 {
1630 unsigned mask;
1631 int idx;
1632 LLVMValueRef result;
1633
1634 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1635 mask = AC_TID_MASK_LEFT;
1636 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1637 mask = AC_TID_MASK_TOP;
1638 else
1639 mask = AC_TID_MASK_TOP_LEFT;
1640
1641 /* for DDX we want to next X pixel, DDY next Y pixel. */
1642 if (op == nir_op_fddx_fine ||
1643 op == nir_op_fddx_coarse ||
1644 op == nir_op_fddx)
1645 idx = 1;
1646 else
1647 idx = 2;
1648
1649 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1650 return result;
1651 }
1652
1653 /*
1654 * this takes an I,J coordinate pair,
1655 * and works out the X and Y derivatives.
1656 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1657 */
1658 static LLVMValueRef emit_ddxy_interp(
1659 struct ac_nir_context *ctx,
1660 LLVMValueRef interp_ij)
1661 {
1662 LLVMValueRef result[4], a;
1663 unsigned i;
1664
1665 for (i = 0; i < 2; i++) {
1666 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1667 LLVMConstInt(ctx->ac.i32, i, false), "");
1668 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1669 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1670 }
1671 return ac_build_gather_values(&ctx->ac, result, 4);
1672 }
1673
1674 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1675 {
1676 LLVMValueRef src[4], result = NULL;
1677 unsigned num_components = instr->dest.dest.ssa.num_components;
1678 unsigned src_components;
1679 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1680
1681 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1682 switch (instr->op) {
1683 case nir_op_vec2:
1684 case nir_op_vec3:
1685 case nir_op_vec4:
1686 src_components = 1;
1687 break;
1688 case nir_op_pack_half_2x16:
1689 src_components = 2;
1690 break;
1691 case nir_op_unpack_half_2x16:
1692 src_components = 1;
1693 break;
1694 default:
1695 src_components = num_components;
1696 break;
1697 }
1698 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1699 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1700
1701 switch (instr->op) {
1702 case nir_op_fmov:
1703 case nir_op_imov:
1704 result = src[0];
1705 break;
1706 case nir_op_fneg:
1707 src[0] = ac_to_float(&ctx->ac, src[0]);
1708 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1709 break;
1710 case nir_op_ineg:
1711 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1712 break;
1713 case nir_op_inot:
1714 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1715 break;
1716 case nir_op_iadd:
1717 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_fadd:
1720 src[0] = ac_to_float(&ctx->ac, src[0]);
1721 src[1] = ac_to_float(&ctx->ac, src[1]);
1722 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_fsub:
1725 src[0] = ac_to_float(&ctx->ac, src[0]);
1726 src[1] = ac_to_float(&ctx->ac, src[1]);
1727 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_isub:
1730 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_imul:
1733 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_imod:
1736 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1737 break;
1738 case nir_op_umod:
1739 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1740 break;
1741 case nir_op_fmod:
1742 src[0] = ac_to_float(&ctx->ac, src[0]);
1743 src[1] = ac_to_float(&ctx->ac, src[1]);
1744 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1745 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1746 ac_to_float_type(&ctx->ac, def_type), result);
1747 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1748 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1749 break;
1750 case nir_op_frem:
1751 src[0] = ac_to_float(&ctx->ac, src[0]);
1752 src[1] = ac_to_float(&ctx->ac, src[1]);
1753 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1754 break;
1755 case nir_op_irem:
1756 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1757 break;
1758 case nir_op_idiv:
1759 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_udiv:
1762 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1763 break;
1764 case nir_op_fmul:
1765 src[0] = ac_to_float(&ctx->ac, src[0]);
1766 src[1] = ac_to_float(&ctx->ac, src[1]);
1767 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1768 break;
1769 case nir_op_fdiv:
1770 src[0] = ac_to_float(&ctx->ac, src[0]);
1771 src[1] = ac_to_float(&ctx->ac, src[1]);
1772 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1773 break;
1774 case nir_op_frcp:
1775 src[0] = ac_to_float(&ctx->ac, src[0]);
1776 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1777 src[0]);
1778 break;
1779 case nir_op_iand:
1780 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1781 break;
1782 case nir_op_ior:
1783 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1784 break;
1785 case nir_op_ixor:
1786 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1787 break;
1788 case nir_op_ishl:
1789 result = LLVMBuildShl(ctx->ac.builder, src[0],
1790 LLVMBuildZExt(ctx->ac.builder, src[1],
1791 LLVMTypeOf(src[0]), ""),
1792 "");
1793 break;
1794 case nir_op_ishr:
1795 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1796 LLVMBuildZExt(ctx->ac.builder, src[1],
1797 LLVMTypeOf(src[0]), ""),
1798 "");
1799 break;
1800 case nir_op_ushr:
1801 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1802 LLVMBuildZExt(ctx->ac.builder, src[1],
1803 LLVMTypeOf(src[0]), ""),
1804 "");
1805 break;
1806 case nir_op_ilt:
1807 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1808 break;
1809 case nir_op_ine:
1810 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1811 break;
1812 case nir_op_ieq:
1813 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1814 break;
1815 case nir_op_ige:
1816 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1817 break;
1818 case nir_op_ult:
1819 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1820 break;
1821 case nir_op_uge:
1822 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1823 break;
1824 case nir_op_feq:
1825 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1826 break;
1827 case nir_op_fne:
1828 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1829 break;
1830 case nir_op_flt:
1831 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1832 break;
1833 case nir_op_fge:
1834 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1835 break;
1836 case nir_op_fabs:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_iabs:
1841 result = emit_iabs(&ctx->ac, src[0]);
1842 break;
1843 case nir_op_imax:
1844 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1845 break;
1846 case nir_op_imin:
1847 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1848 break;
1849 case nir_op_umax:
1850 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1851 break;
1852 case nir_op_umin:
1853 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1854 break;
1855 case nir_op_isign:
1856 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1857 break;
1858 case nir_op_fsign:
1859 src[0] = ac_to_float(&ctx->ac, src[0]);
1860 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1861 break;
1862 case nir_op_ffloor:
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1864 ac_to_float_type(&ctx->ac, def_type), src[0]);
1865 break;
1866 case nir_op_ftrunc:
1867 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1868 ac_to_float_type(&ctx->ac, def_type), src[0]);
1869 break;
1870 case nir_op_fceil:
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1872 ac_to_float_type(&ctx->ac, def_type), src[0]);
1873 break;
1874 case nir_op_fround_even:
1875 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1876 ac_to_float_type(&ctx->ac, def_type),src[0]);
1877 break;
1878 case nir_op_ffract:
1879 result = emit_ffract(&ctx->ac, src[0]);
1880 break;
1881 case nir_op_fsin:
1882 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1883 ac_to_float_type(&ctx->ac, def_type), src[0]);
1884 break;
1885 case nir_op_fcos:
1886 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1887 ac_to_float_type(&ctx->ac, def_type), src[0]);
1888 break;
1889 case nir_op_fsqrt:
1890 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1891 ac_to_float_type(&ctx->ac, def_type), src[0]);
1892 break;
1893 case nir_op_fexp2:
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1895 ac_to_float_type(&ctx->ac, def_type), src[0]);
1896 break;
1897 case nir_op_flog2:
1898 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1899 ac_to_float_type(&ctx->ac, def_type), src[0]);
1900 break;
1901 case nir_op_frsq:
1902 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1903 ac_to_float_type(&ctx->ac, def_type), src[0]);
1904 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1905 result);
1906 break;
1907 case nir_op_fpow:
1908 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1909 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1910 break;
1911 case nir_op_fmax:
1912 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1913 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1914 if (instr->dest.dest.ssa.bit_size == 32)
1915 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1916 ac_to_float_type(&ctx->ac, def_type),
1917 result);
1918 break;
1919 case nir_op_fmin:
1920 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1921 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1922 if (instr->dest.dest.ssa.bit_size == 32)
1923 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1924 ac_to_float_type(&ctx->ac, def_type),
1925 result);
1926 break;
1927 case nir_op_ffma:
1928 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1929 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1930 break;
1931 case nir_op_ibitfield_extract:
1932 result = emit_bitfield_extract(&ctx->ac, true, src);
1933 break;
1934 case nir_op_ubitfield_extract:
1935 result = emit_bitfield_extract(&ctx->ac, false, src);
1936 break;
1937 case nir_op_bitfield_insert:
1938 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1939 break;
1940 case nir_op_bitfield_reverse:
1941 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1942 break;
1943 case nir_op_bit_count:
1944 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1945 break;
1946 case nir_op_vec2:
1947 case nir_op_vec3:
1948 case nir_op_vec4:
1949 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1950 src[i] = ac_to_integer(&ctx->ac, src[i]);
1951 result = ac_build_gather_values(&ctx->ac, src, num_components);
1952 break;
1953 case nir_op_f2i32:
1954 case nir_op_f2i64:
1955 src[0] = ac_to_float(&ctx->ac, src[0]);
1956 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1957 break;
1958 case nir_op_f2u32:
1959 case nir_op_f2u64:
1960 src[0] = ac_to_float(&ctx->ac, src[0]);
1961 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1962 break;
1963 case nir_op_i2f32:
1964 case nir_op_i2f64:
1965 src[0] = ac_to_integer(&ctx->ac, src[0]);
1966 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1967 break;
1968 case nir_op_u2f32:
1969 case nir_op_u2f64:
1970 src[0] = ac_to_integer(&ctx->ac, src[0]);
1971 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1972 break;
1973 case nir_op_f2f64:
1974 src[0] = ac_to_float(&ctx->ac, src[0]);
1975 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1976 break;
1977 case nir_op_f2f32:
1978 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1979 break;
1980 case nir_op_u2u32:
1981 case nir_op_u2u64:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1984 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1985 else
1986 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1987 break;
1988 case nir_op_i2i32:
1989 case nir_op_i2i64:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1992 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1993 else
1994 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1995 break;
1996 case nir_op_bcsel:
1997 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1998 break;
1999 case nir_op_find_lsb:
2000 src[0] = ac_to_integer(&ctx->ac, src[0]);
2001 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
2002 break;
2003 case nir_op_ufind_msb:
2004 src[0] = ac_to_integer(&ctx->ac, src[0]);
2005 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
2006 break;
2007 case nir_op_ifind_msb:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2010 break;
2011 case nir_op_uadd_carry:
2012 src[0] = ac_to_integer(&ctx->ac, src[0]);
2013 src[1] = ac_to_integer(&ctx->ac, src[1]);
2014 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2015 break;
2016 case nir_op_usub_borrow:
2017 src[0] = ac_to_integer(&ctx->ac, src[0]);
2018 src[1] = ac_to_integer(&ctx->ac, src[1]);
2019 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2020 break;
2021 case nir_op_b2f:
2022 result = emit_b2f(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_f2b:
2025 result = emit_f2b(&ctx->ac, src[0]);
2026 break;
2027 case nir_op_b2i:
2028 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2029 break;
2030 case nir_op_i2b:
2031 src[0] = ac_to_integer(&ctx->ac, src[0]);
2032 result = emit_i2b(&ctx->ac, src[0]);
2033 break;
2034 case nir_op_fquantize2f16:
2035 result = emit_f2f16(ctx->nctx, src[0]);
2036 break;
2037 case nir_op_umul_high:
2038 src[0] = ac_to_integer(&ctx->ac, src[0]);
2039 src[1] = ac_to_integer(&ctx->ac, src[1]);
2040 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2041 break;
2042 case nir_op_imul_high:
2043 src[0] = ac_to_integer(&ctx->ac, src[0]);
2044 src[1] = ac_to_integer(&ctx->ac, src[1]);
2045 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2046 break;
2047 case nir_op_pack_half_2x16:
2048 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2049 break;
2050 case nir_op_unpack_half_2x16:
2051 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2052 break;
2053 case nir_op_fddx:
2054 case nir_op_fddy:
2055 case nir_op_fddx_fine:
2056 case nir_op_fddy_fine:
2057 case nir_op_fddx_coarse:
2058 case nir_op_fddy_coarse:
2059 result = emit_ddxy(ctx, instr->op, src[0]);
2060 break;
2061
2062 case nir_op_unpack_64_2x32_split_x: {
2063 assert(instr->src[0].src.ssa->num_components == 1);
2064 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2065 ctx->ac.v2i32,
2066 "");
2067 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2068 ctx->ac.i32_0, "");
2069 break;
2070 }
2071
2072 case nir_op_unpack_64_2x32_split_y: {
2073 assert(instr->src[0].src.ssa->num_components == 1);
2074 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2075 ctx->ac.v2i32,
2076 "");
2077 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2078 ctx->ac.i32_1, "");
2079 break;
2080 }
2081
2082 case nir_op_pack_64_2x32_split: {
2083 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2084 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2085 src[0], ctx->ac.i32_0, "");
2086 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2087 src[1], ctx->ac.i32_1, "");
2088 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2089 break;
2090 }
2091
2092 default:
2093 fprintf(stderr, "Unknown NIR alu instr: ");
2094 nir_print_instr(&instr->instr, stderr);
2095 fprintf(stderr, "\n");
2096 abort();
2097 }
2098
2099 if (result) {
2100 assert(instr->dest.dest.is_ssa);
2101 result = ac_to_integer(&ctx->ac, result);
2102 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2103 result);
2104 }
2105 }
2106
2107 static void visit_load_const(struct ac_nir_context *ctx,
2108 const nir_load_const_instr *instr)
2109 {
2110 LLVMValueRef values[4], value = NULL;
2111 LLVMTypeRef element_type =
2112 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2113
2114 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2115 switch (instr->def.bit_size) {
2116 case 32:
2117 values[i] = LLVMConstInt(element_type,
2118 instr->value.u32[i], false);
2119 break;
2120 case 64:
2121 values[i] = LLVMConstInt(element_type,
2122 instr->value.u64[i], false);
2123 break;
2124 default:
2125 fprintf(stderr,
2126 "unsupported nir load_const bit_size: %d\n",
2127 instr->def.bit_size);
2128 abort();
2129 }
2130 }
2131 if (instr->def.num_components > 1) {
2132 value = LLVMConstVector(values, instr->def.num_components);
2133 } else
2134 value = values[0];
2135
2136 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2137 }
2138
2139 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2140 LLVMTypeRef type)
2141 {
2142 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2143 return LLVMBuildBitCast(ctx->builder, ptr,
2144 LLVMPointerType(type, addr_space), "");
2145 }
2146
2147 static LLVMValueRef
2148 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2149 {
2150 LLVMValueRef size =
2151 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2152 LLVMConstInt(ctx->ac.i32, 2, false), "");
2153
2154 /* VI only */
2155 if (ctx->ac.chip_class == VI && in_elements) {
2156 /* On VI, the descriptor contains the size in bytes,
2157 * but TXQ must return the size in elements.
2158 * The stride is always non-zero for resources using TXQ.
2159 */
2160 LLVMValueRef stride =
2161 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2162 ctx->ac.i32_1, "");
2163 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2164 LLVMConstInt(ctx->ac.i32, 16, false), "");
2165 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2166 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2167
2168 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2169 }
2170 return size;
2171 }
2172
2173 /**
2174 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2175 * intrinsic names).
2176 */
2177 static void build_int_type_name(
2178 LLVMTypeRef type,
2179 char *buf, unsigned bufsize)
2180 {
2181 assert(bufsize >= 6);
2182
2183 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2184 snprintf(buf, bufsize, "v%ui32",
2185 LLVMGetVectorSize(type));
2186 else
2187 strcpy(buf, "i32");
2188 }
2189
2190 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2191 struct ac_image_args *args,
2192 const nir_tex_instr *instr)
2193 {
2194 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2195 LLVMValueRef coord = args->addr;
2196 LLVMValueRef half_texel[2];
2197 LLVMValueRef compare_cube_wa = NULL;
2198 LLVMValueRef result;
2199 int c;
2200 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2201
2202 //TODO Rect
2203 {
2204 struct ac_image_args txq_args = { 0 };
2205
2206 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2207 txq_args.opcode = ac_image_get_resinfo;
2208 txq_args.dmask = 0xf;
2209 txq_args.addr = ctx->i32_0;
2210 txq_args.resource = args->resource;
2211 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2212
2213 for (c = 0; c < 2; c++) {
2214 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2215 LLVMConstInt(ctx->i32, c, false), "");
2216 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2217 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2218 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2219 LLVMConstReal(ctx->f32, -0.5), "");
2220 }
2221 }
2222
2223 LLVMValueRef orig_coords = args->addr;
2224
2225 for (c = 0; c < 2; c++) {
2226 LLVMValueRef tmp;
2227 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2228 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2229 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2230 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2231 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2232 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2233 }
2234
2235
2236 /*
2237 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2238 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2239 * workaround by sampling using a scaled type and converting.
2240 * This is taken from amdgpu-pro shaders.
2241 */
2242 /* NOTE this produces some ugly code compared to amdgpu-pro,
2243 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2244 * and then reads them back. -pro generates two selects,
2245 * one s_cmp for the descriptor rewriting
2246 * one v_cmp for the coordinate and result changes.
2247 */
2248 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2249 LLVMValueRef tmp, tmp2;
2250
2251 /* workaround 8/8/8/8 uint/sint cube gather bug */
2252 /* first detect it then change to a scaled read and f2i */
2253 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2254 tmp2 = tmp;
2255
2256 /* extract the DATA_FORMAT */
2257 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2258 LLVMConstInt(ctx->i32, 6, false), false);
2259
2260 /* is the DATA_FORMAT == 8_8_8_8 */
2261 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2262
2263 if (stype == GLSL_TYPE_UINT)
2264 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2265 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2266 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2267 else
2268 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2269 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2270 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2271
2272 /* replace the NUM FORMAT in the descriptor */
2273 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2274 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2275
2276 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2277
2278 /* don't modify the coordinates for this case */
2279 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2280 }
2281 args->addr = coord;
2282 result = ac_build_image_opcode(ctx, args);
2283
2284 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2285 LLVMValueRef tmp, tmp2;
2286
2287 /* if the cube workaround is in place, f2i the result. */
2288 for (c = 0; c < 4; c++) {
2289 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2290 if (stype == GLSL_TYPE_UINT)
2291 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2292 else
2293 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2294 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2295 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2296 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2297 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2298 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2299 }
2300 }
2301 return result;
2302 }
2303
2304 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2305 const nir_tex_instr *instr,
2306 bool lod_is_zero,
2307 struct ac_image_args *args)
2308 {
2309 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2310 return ac_build_buffer_load_format(&ctx->ac,
2311 args->resource,
2312 args->addr,
2313 ctx->ac.i32_0,
2314 true);
2315 }
2316
2317 args->opcode = ac_image_sample;
2318 args->compare = instr->is_shadow;
2319
2320 switch (instr->op) {
2321 case nir_texop_txf:
2322 case nir_texop_txf_ms:
2323 case nir_texop_samples_identical:
2324 args->opcode = lod_is_zero ||
2325 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2326 ac_image_load : ac_image_load_mip;
2327 args->compare = false;
2328 args->offset = false;
2329 break;
2330 case nir_texop_txb:
2331 args->bias = true;
2332 break;
2333 case nir_texop_txl:
2334 if (lod_is_zero)
2335 args->level_zero = true;
2336 else
2337 args->lod = true;
2338 break;
2339 case nir_texop_txs:
2340 case nir_texop_query_levels:
2341 args->opcode = ac_image_get_resinfo;
2342 break;
2343 case nir_texop_tex:
2344 if (ctx->stage != MESA_SHADER_FRAGMENT)
2345 args->level_zero = true;
2346 break;
2347 case nir_texop_txd:
2348 args->deriv = true;
2349 break;
2350 case nir_texop_tg4:
2351 args->opcode = ac_image_gather4;
2352 args->level_zero = true;
2353 break;
2354 case nir_texop_lod:
2355 args->opcode = ac_image_get_lod;
2356 args->compare = false;
2357 args->offset = false;
2358 break;
2359 default:
2360 break;
2361 }
2362
2363 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2364 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2365 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2366 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2367 }
2368 }
2369 return ac_build_image_opcode(&ctx->ac, args);
2370 }
2371
2372 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2373 nir_intrinsic_instr *instr)
2374 {
2375 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2376 unsigned desc_set = nir_intrinsic_desc_set(instr);
2377 unsigned binding = nir_intrinsic_binding(instr);
2378 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2379 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2380 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2381 unsigned base_offset = layout->binding[binding].offset;
2382 LLVMValueRef offset, stride;
2383
2384 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2385 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2386 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2387 layout->binding[binding].dynamic_offset_offset;
2388 desc_ptr = ctx->push_constants;
2389 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2390 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2391 } else
2392 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2393
2394 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2395 index = LLVMBuildMul(ctx->builder, index, stride, "");
2396 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2397
2398 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2399 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2400 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2401
2402 return desc_ptr;
2403 }
2404
2405 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2406 nir_intrinsic_instr *instr)
2407 {
2408 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2409 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2410
2411 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2412 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2413 return result;
2414 }
2415
2416 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2417 nir_intrinsic_instr *instr)
2418 {
2419 LLVMValueRef ptr, addr;
2420
2421 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2422 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2423
2424 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2425 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2426
2427 return LLVMBuildLoad(ctx->builder, ptr, "");
2428 }
2429
2430 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2431 const nir_intrinsic_instr *instr)
2432 {
2433 LLVMValueRef index = get_src(ctx, instr->src[0]);
2434
2435 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2436 }
2437
2438 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2439 {
2440 uint32_t new_mask = 0;
2441 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2442 if (mask & (1u << i))
2443 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2444 return new_mask;
2445 }
2446
2447 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2448 unsigned start, unsigned count)
2449 {
2450 LLVMTypeRef type = LLVMTypeOf(src);
2451
2452 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2453 assert(start == 0);
2454 assert(count == 1);
2455 return src;
2456 }
2457
2458 unsigned src_elements = LLVMGetVectorSize(type);
2459 assert(start < src_elements);
2460 assert(start + count <= src_elements);
2461
2462 if (start == 0 && count == src_elements)
2463 return src;
2464
2465 if (count == 1)
2466 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2467
2468 assert(count <= 8);
2469 LLVMValueRef indices[8];
2470 for (unsigned i = 0; i < count; ++i)
2471 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2472
2473 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2474 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2475 }
2476
2477 static void visit_store_ssbo(struct ac_nir_context *ctx,
2478 nir_intrinsic_instr *instr)
2479 {
2480 const char *store_name;
2481 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2482 LLVMTypeRef data_type = ctx->ac.f32;
2483 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2484 int components_32bit = elem_size_mult * instr->num_components;
2485 unsigned writemask = nir_intrinsic_write_mask(instr);
2486 LLVMValueRef base_data, base_offset;
2487 LLVMValueRef params[6];
2488
2489 params[1] = ctx->abi->load_ssbo(ctx->abi,
2490 get_src(ctx, instr->src[1]), true);
2491 params[2] = ctx->ac.i32_0; /* vindex */
2492 params[4] = ctx->ac.i1false; /* glc */
2493 params[5] = ctx->ac.i1false; /* slc */
2494
2495 if (components_32bit > 1)
2496 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2497
2498 writemask = widen_mask(writemask, elem_size_mult);
2499
2500 base_data = ac_to_float(&ctx->ac, src_data);
2501 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2502 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2503 data_type, "");
2504 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2505 while (writemask) {
2506 int start, count;
2507 LLVMValueRef data;
2508 LLVMValueRef offset;
2509
2510 u_bit_scan_consecutive_range(&writemask, &start, &count);
2511
2512 /* Due to an LLVM limitation, split 3-element writes
2513 * into a 2-element and a 1-element write. */
2514 if (count == 3) {
2515 writemask |= 1 << (start + 2);
2516 count = 2;
2517 }
2518
2519 if (count > 4) {
2520 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2521 count = 4;
2522 }
2523
2524 if (count == 4) {
2525 store_name = "llvm.amdgcn.buffer.store.v4f32";
2526 } else if (count == 2) {
2527 store_name = "llvm.amdgcn.buffer.store.v2f32";
2528
2529 } else {
2530 assert(count == 1);
2531 store_name = "llvm.amdgcn.buffer.store.f32";
2532 }
2533 data = extract_vector_range(&ctx->ac, base_data, start, count);
2534
2535 offset = base_offset;
2536 if (start != 0) {
2537 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2538 }
2539 params[0] = data;
2540 params[3] = offset;
2541 ac_build_intrinsic(&ctx->ac, store_name,
2542 ctx->ac.voidt, params, 6, 0);
2543 }
2544 }
2545
2546 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2547 const nir_intrinsic_instr *instr)
2548 {
2549 const char *name;
2550 LLVMValueRef params[6];
2551 int arg_count = 0;
2552
2553 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2554 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2555 }
2556 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2557 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2558 get_src(ctx, instr->src[0]),
2559 true);
2560 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2561 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2562 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2563
2564 switch (instr->intrinsic) {
2565 case nir_intrinsic_ssbo_atomic_add:
2566 name = "llvm.amdgcn.buffer.atomic.add";
2567 break;
2568 case nir_intrinsic_ssbo_atomic_imin:
2569 name = "llvm.amdgcn.buffer.atomic.smin";
2570 break;
2571 case nir_intrinsic_ssbo_atomic_umin:
2572 name = "llvm.amdgcn.buffer.atomic.umin";
2573 break;
2574 case nir_intrinsic_ssbo_atomic_imax:
2575 name = "llvm.amdgcn.buffer.atomic.smax";
2576 break;
2577 case nir_intrinsic_ssbo_atomic_umax:
2578 name = "llvm.amdgcn.buffer.atomic.umax";
2579 break;
2580 case nir_intrinsic_ssbo_atomic_and:
2581 name = "llvm.amdgcn.buffer.atomic.and";
2582 break;
2583 case nir_intrinsic_ssbo_atomic_or:
2584 name = "llvm.amdgcn.buffer.atomic.or";
2585 break;
2586 case nir_intrinsic_ssbo_atomic_xor:
2587 name = "llvm.amdgcn.buffer.atomic.xor";
2588 break;
2589 case nir_intrinsic_ssbo_atomic_exchange:
2590 name = "llvm.amdgcn.buffer.atomic.swap";
2591 break;
2592 case nir_intrinsic_ssbo_atomic_comp_swap:
2593 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2594 break;
2595 default:
2596 abort();
2597 }
2598
2599 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2600 }
2601
2602 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2603 const nir_intrinsic_instr *instr)
2604 {
2605 LLVMValueRef results[2];
2606 int load_components;
2607 int num_components = instr->num_components;
2608 if (instr->dest.ssa.bit_size == 64)
2609 num_components *= 2;
2610
2611 for (int i = 0; i < num_components; i += load_components) {
2612 load_components = MIN2(num_components - i, 4);
2613 const char *load_name;
2614 LLVMTypeRef data_type = ctx->ac.f32;
2615 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2616 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2617
2618 if (load_components == 3)
2619 data_type = LLVMVectorType(ctx->ac.f32, 4);
2620 else if (load_components > 1)
2621 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2622
2623 if (load_components >= 3)
2624 load_name = "llvm.amdgcn.buffer.load.v4f32";
2625 else if (load_components == 2)
2626 load_name = "llvm.amdgcn.buffer.load.v2f32";
2627 else if (load_components == 1)
2628 load_name = "llvm.amdgcn.buffer.load.f32";
2629 else
2630 unreachable("unhandled number of components");
2631
2632 LLVMValueRef params[] = {
2633 ctx->abi->load_ssbo(ctx->abi,
2634 get_src(ctx, instr->src[0]),
2635 false),
2636 ctx->ac.i32_0,
2637 offset,
2638 ctx->ac.i1false,
2639 ctx->ac.i1false,
2640 };
2641
2642 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2643 }
2644
2645 assume(results[0]);
2646 LLVMValueRef ret = results[0];
2647 if (num_components > 4 || num_components == 3) {
2648 LLVMValueRef masks[] = {
2649 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2650 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2651 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2652 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2653 };
2654
2655 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2656 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2657 results[num_components > 4 ? 1 : 0], swizzle, "");
2658 }
2659
2660 return LLVMBuildBitCast(ctx->ac.builder, ret,
2661 get_def_type(ctx, &instr->dest.ssa), "");
2662 }
2663
2664 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2665 const nir_intrinsic_instr *instr)
2666 {
2667 LLVMValueRef ret;
2668 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2669 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2670 int num_components = instr->num_components;
2671
2672 if (ctx->abi->load_ubo)
2673 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2674
2675 if (instr->dest.ssa.bit_size == 64)
2676 num_components *= 2;
2677
2678 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2679 NULL, 0, false, false, true, true);
2680 ret = trim_vector(&ctx->ac, ret, num_components);
2681 return LLVMBuildBitCast(ctx->ac.builder, ret,
2682 get_def_type(ctx, &instr->dest.ssa), "");
2683 }
2684
2685 static void
2686 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2687 bool vs_in, unsigned *vertex_index_out,
2688 LLVMValueRef *vertex_index_ref,
2689 unsigned *const_out, LLVMValueRef *indir_out)
2690 {
2691 unsigned const_offset = 0;
2692 nir_deref *tail = &deref->deref;
2693 LLVMValueRef offset = NULL;
2694
2695 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2696 tail = tail->child;
2697 nir_deref_array *deref_array = nir_deref_as_array(tail);
2698 if (vertex_index_out)
2699 *vertex_index_out = deref_array->base_offset;
2700
2701 if (vertex_index_ref) {
2702 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2703 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2704 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2705 }
2706 *vertex_index_ref = vtx;
2707 }
2708 }
2709
2710 if (deref->var->data.compact) {
2711 assert(tail->child->deref_type == nir_deref_type_array);
2712 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2713 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2714 /* We always lower indirect dereferences for "compact" array vars. */
2715 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2716
2717 const_offset = deref_array->base_offset;
2718 goto out;
2719 }
2720
2721 while (tail->child != NULL) {
2722 const struct glsl_type *parent_type = tail->type;
2723 tail = tail->child;
2724
2725 if (tail->deref_type == nir_deref_type_array) {
2726 nir_deref_array *deref_array = nir_deref_as_array(tail);
2727 LLVMValueRef index, stride, local_offset;
2728 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2729
2730 const_offset += size * deref_array->base_offset;
2731 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2732 continue;
2733
2734 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2735 index = get_src(ctx, deref_array->indirect);
2736 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2737 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2738
2739 if (offset)
2740 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2741 else
2742 offset = local_offset;
2743 } else if (tail->deref_type == nir_deref_type_struct) {
2744 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2745
2746 for (unsigned i = 0; i < deref_struct->index; i++) {
2747 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2748 const_offset += glsl_count_attribute_slots(ft, vs_in);
2749 }
2750 } else
2751 unreachable("unsupported deref type");
2752
2753 }
2754 out:
2755 if (const_offset && offset)
2756 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2757 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2758 "");
2759
2760 *const_out = const_offset;
2761 *indir_out = offset;
2762 }
2763
2764
2765 /* The offchip buffer layout for TCS->TES is
2766 *
2767 * - attribute 0 of patch 0 vertex 0
2768 * - attribute 0 of patch 0 vertex 1
2769 * - attribute 0 of patch 0 vertex 2
2770 * ...
2771 * - attribute 0 of patch 1 vertex 0
2772 * - attribute 0 of patch 1 vertex 1
2773 * ...
2774 * - attribute 1 of patch 0 vertex 0
2775 * - attribute 1 of patch 0 vertex 1
2776 * ...
2777 * - per patch attribute 0 of patch 0
2778 * - per patch attribute 0 of patch 1
2779 * ...
2780 *
2781 * Note that every attribute has 4 components.
2782 */
2783 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2784 LLVMValueRef vertex_index,
2785 LLVMValueRef param_index)
2786 {
2787 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2788 LLVMValueRef param_stride, constant16;
2789 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2790
2791 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2792 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2793 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2794 num_patches, "");
2795
2796 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2797 if (vertex_index) {
2798 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2799 vertices_per_patch, "");
2800
2801 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2802 vertex_index, "");
2803
2804 param_stride = total_vertices;
2805 } else {
2806 base_addr = rel_patch_id;
2807 param_stride = num_patches;
2808 }
2809
2810 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2811 LLVMBuildMul(ctx->builder, param_index,
2812 param_stride, ""), "");
2813
2814 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2815
2816 if (!vertex_index) {
2817 LLVMValueRef patch_data_offset =
2818 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2819
2820 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2821 patch_data_offset, "");
2822 }
2823 return base_addr;
2824 }
2825
2826 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2827 unsigned param,
2828 unsigned const_index,
2829 bool is_compact,
2830 LLVMValueRef vertex_index,
2831 LLVMValueRef indir_index)
2832 {
2833 LLVMValueRef param_index;
2834
2835 if (indir_index)
2836 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2837 indir_index, "");
2838 else {
2839 if (const_index && !is_compact)
2840 param += const_index;
2841 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2842 }
2843 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2844 }
2845
2846 static void
2847 mark_tess_output(struct nir_to_llvm_context *ctx,
2848 bool is_patch, uint32_t param)
2849
2850 {
2851 if (is_patch) {
2852 ctx->tess_patch_outputs_written |= (1ull << param);
2853 } else
2854 ctx->tess_outputs_written |= (1ull << param);
2855 }
2856
2857 static LLVMValueRef
2858 get_dw_address(struct nir_to_llvm_context *ctx,
2859 LLVMValueRef dw_addr,
2860 unsigned param,
2861 unsigned const_index,
2862 bool compact_const_index,
2863 LLVMValueRef vertex_index,
2864 LLVMValueRef stride,
2865 LLVMValueRef indir_index)
2866
2867 {
2868
2869 if (vertex_index) {
2870 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2871 LLVMBuildMul(ctx->builder,
2872 vertex_index,
2873 stride, ""), "");
2874 }
2875
2876 if (indir_index)
2877 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2878 LLVMBuildMul(ctx->builder, indir_index,
2879 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2880 else if (const_index && !compact_const_index)
2881 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2882 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2883
2884 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2885 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2886
2887 if (const_index && compact_const_index)
2888 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2889 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2890 return dw_addr;
2891 }
2892
2893 static LLVMValueRef
2894 load_tcs_varyings(struct ac_shader_abi *abi,
2895 LLVMValueRef vertex_index,
2896 LLVMValueRef indir_index,
2897 unsigned const_index,
2898 unsigned location,
2899 unsigned driver_location,
2900 unsigned component,
2901 unsigned num_components,
2902 bool is_patch,
2903 bool is_compact,
2904 bool load_input)
2905 {
2906 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2907 LLVMValueRef dw_addr, stride;
2908 LLVMValueRef value[4], result;
2909 unsigned param = shader_io_get_unique_index(location);
2910
2911 if (load_input) {
2912 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2913 dw_addr = get_tcs_in_current_patch_offset(ctx);
2914 } else {
2915 if (!is_patch) {
2916 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2917 dw_addr = get_tcs_out_current_patch_offset(ctx);
2918 } else {
2919 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2920 stride = NULL;
2921 }
2922 }
2923
2924 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2925 indir_index);
2926
2927 for (unsigned i = 0; i < num_components + component; i++) {
2928 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2929 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2930 ctx->ac.i32_1, "");
2931 }
2932 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2933 return result;
2934 }
2935
2936 static void
2937 store_tcs_output(struct ac_shader_abi *abi,
2938 LLVMValueRef vertex_index,
2939 LLVMValueRef param_index,
2940 unsigned const_index,
2941 unsigned location,
2942 unsigned driver_location,
2943 LLVMValueRef src,
2944 unsigned component,
2945 bool is_patch,
2946 bool is_compact,
2947 unsigned writemask)
2948 {
2949 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2950 LLVMValueRef dw_addr;
2951 LLVMValueRef stride = NULL;
2952 LLVMValueRef buf_addr = NULL;
2953 unsigned param;
2954 bool store_lds = true;
2955
2956 if (is_patch) {
2957 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2958 store_lds = false;
2959 } else {
2960 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2961 store_lds = false;
2962 }
2963
2964 param = shader_io_get_unique_index(location);
2965 if (location == VARYING_SLOT_CLIP_DIST0 &&
2966 is_compact && const_index > 3) {
2967 const_index -= 3;
2968 param++;
2969 }
2970
2971 if (!is_patch) {
2972 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2973 dw_addr = get_tcs_out_current_patch_offset(ctx);
2974 } else {
2975 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2976 }
2977
2978 mark_tess_output(ctx, is_patch, param);
2979
2980 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2981 param_index);
2982 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2983 vertex_index, param_index);
2984
2985 bool is_tess_factor = false;
2986 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2987 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2988 is_tess_factor = true;
2989
2990 unsigned base = is_compact ? const_index : 0;
2991 for (unsigned chan = 0; chan < 8; chan++) {
2992 if (!(writemask & (1 << chan)))
2993 continue;
2994 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2995
2996 if (store_lds || is_tess_factor) {
2997 LLVMValueRef dw_addr_chan =
2998 LLVMBuildAdd(ctx->builder, dw_addr,
2999 LLVMConstInt(ctx->ac.i32, chan, false), "");
3000 ac_lds_store(&ctx->ac, dw_addr_chan, value);
3001 }
3002
3003 if (!is_tess_factor && writemask != 0xF)
3004 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
3005 buf_addr, ctx->oc_lds,
3006 4 * (base + chan), 1, 0, true, false);
3007 }
3008
3009 if (writemask == 0xF) {
3010 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3011 buf_addr, ctx->oc_lds,
3012 (base * 4), 1, 0, true, false);
3013 }
3014 }
3015
3016 static LLVMValueRef
3017 load_tes_input(struct ac_shader_abi *abi,
3018 LLVMValueRef vertex_index,
3019 LLVMValueRef param_index,
3020 unsigned const_index,
3021 unsigned location,
3022 unsigned driver_location,
3023 unsigned component,
3024 unsigned num_components,
3025 bool is_patch,
3026 bool is_compact,
3027 bool load_input)
3028 {
3029 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3030 LLVMValueRef buf_addr;
3031 LLVMValueRef result;
3032 unsigned param = shader_io_get_unique_index(location);
3033
3034 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3035 const_index -= 3;
3036 param++;
3037 }
3038
3039 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3040 is_compact, vertex_index, param_index);
3041
3042 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3043 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3044
3045 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3046 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3047 result = trim_vector(&ctx->ac, result, num_components);
3048 return result;
3049 }
3050
3051 static LLVMValueRef
3052 load_gs_input(struct ac_shader_abi *abi,
3053 unsigned location,
3054 unsigned driver_location,
3055 unsigned component,
3056 unsigned num_components,
3057 unsigned vertex_index,
3058 unsigned const_index,
3059 LLVMTypeRef type)
3060 {
3061 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3062 LLVMValueRef vtx_offset;
3063 LLVMValueRef args[9];
3064 unsigned param, vtx_offset_param;
3065 LLVMValueRef value[4], result;
3066
3067 vtx_offset_param = vertex_index;
3068 assert(vtx_offset_param < 6);
3069 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3070 LLVMConstInt(ctx->ac.i32, 4, false), "");
3071
3072 param = shader_io_get_unique_index(location);
3073
3074 for (unsigned i = component; i < num_components + component; i++) {
3075 if (ctx->ac.chip_class >= GFX9) {
3076 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3077 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3078 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3079 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3080 } else {
3081 args[0] = ctx->esgs_ring;
3082 args[1] = vtx_offset;
3083 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3084 args[3] = ctx->ac.i32_0;
3085 args[4] = ctx->ac.i32_1; /* OFFEN */
3086 args[5] = ctx->ac.i32_0; /* IDXEN */
3087 args[6] = ctx->ac.i32_1; /* GLC */
3088 args[7] = ctx->ac.i32_0; /* SLC */
3089 args[8] = ctx->ac.i32_0; /* TFE */
3090
3091 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3092 ctx->ac.i32, args, 9,
3093 AC_FUNC_ATTR_READONLY |
3094 AC_FUNC_ATTR_LEGACY);
3095 }
3096 }
3097 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3098
3099 return result;
3100 }
3101
3102 static LLVMValueRef
3103 build_gep_for_deref(struct ac_nir_context *ctx,
3104 nir_deref_var *deref)
3105 {
3106 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3107 assert(entry->data);
3108 LLVMValueRef val = entry->data;
3109 nir_deref *tail = deref->deref.child;
3110 while (tail != NULL) {
3111 LLVMValueRef offset;
3112 switch (tail->deref_type) {
3113 case nir_deref_type_array: {
3114 nir_deref_array *array = nir_deref_as_array(tail);
3115 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3116 if (array->deref_array_type ==
3117 nir_deref_array_type_indirect) {
3118 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3119 get_src(ctx,
3120 array->indirect),
3121 "");
3122 }
3123 break;
3124 }
3125 case nir_deref_type_struct: {
3126 nir_deref_struct *deref_struct =
3127 nir_deref_as_struct(tail);
3128 offset = LLVMConstInt(ctx->ac.i32,
3129 deref_struct->index, 0);
3130 break;
3131 }
3132 default:
3133 unreachable("bad deref type");
3134 }
3135 val = ac_build_gep0(&ctx->ac, val, offset);
3136 tail = tail->child;
3137 }
3138 return val;
3139 }
3140
3141 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3142 nir_intrinsic_instr *instr,
3143 bool load_inputs)
3144 {
3145 LLVMValueRef result;
3146 LLVMValueRef vertex_index = NULL;
3147 LLVMValueRef indir_index = NULL;
3148 unsigned const_index = 0;
3149 unsigned location = instr->variables[0]->var->data.location;
3150 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3151 const bool is_patch = instr->variables[0]->var->data.patch;
3152 const bool is_compact = instr->variables[0]->var->data.compact;
3153
3154 get_deref_offset(ctx, instr->variables[0],
3155 false, NULL, is_patch ? NULL : &vertex_index,
3156 &const_index, &indir_index);
3157
3158 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3159 const_index, location, driver_location,
3160 instr->variables[0]->var->data.location_frac,
3161 instr->num_components,
3162 is_patch, is_compact, load_inputs);
3163 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3164 }
3165
3166 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3167 nir_intrinsic_instr *instr)
3168 {
3169 LLVMValueRef values[8];
3170 int idx = instr->variables[0]->var->data.driver_location;
3171 int ve = instr->dest.ssa.num_components;
3172 unsigned comp = instr->variables[0]->var->data.location_frac;
3173 LLVMValueRef indir_index;
3174 LLVMValueRef ret;
3175 unsigned const_index;
3176 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3177 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3178 instr->variables[0]->var->data.mode == nir_var_shader_in;
3179 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3180 &const_index, &indir_index);
3181
3182 if (instr->dest.ssa.bit_size == 64)
3183 ve *= 2;
3184
3185 switch (instr->variables[0]->var->data.mode) {
3186 case nir_var_shader_in:
3187 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3188 ctx->stage == MESA_SHADER_TESS_EVAL) {
3189 return load_tess_varyings(ctx, instr, true);
3190 }
3191
3192 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3193 LLVMValueRef indir_index;
3194 unsigned const_index, vertex_index;
3195 get_deref_offset(ctx, instr->variables[0],
3196 false, &vertex_index, NULL,
3197 &const_index, &indir_index);
3198 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3199 instr->variables[0]->var->data.driver_location,
3200 instr->variables[0]->var->data.location_frac, ve,
3201 vertex_index, const_index,
3202 nir2llvmtype(ctx, instr->variables[0]->var->type));
3203 }
3204
3205 for (unsigned chan = comp; chan < ve + comp; chan++) {
3206 if (indir_index) {
3207 unsigned count = glsl_count_attribute_slots(
3208 instr->variables[0]->var->type,
3209 ctx->stage == MESA_SHADER_VERTEX);
3210 count -= chan / 4;
3211 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3212 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3213 stride, false, true);
3214
3215 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3216 tmp_vec,
3217 indir_index, "");
3218 } else
3219 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3220 }
3221 break;
3222 case nir_var_local:
3223 for (unsigned chan = 0; chan < ve; chan++) {
3224 if (indir_index) {
3225 unsigned count = glsl_count_attribute_slots(
3226 instr->variables[0]->var->type, false);
3227 count -= chan / 4;
3228 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3229 &ctx->ac, ctx->locals + idx + chan, count,
3230 stride, true, true);
3231
3232 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3233 tmp_vec,
3234 indir_index, "");
3235 } else {
3236 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3237 }
3238 }
3239 break;
3240 case nir_var_shared: {
3241 LLVMValueRef address = build_gep_for_deref(ctx,
3242 instr->variables[0]);
3243 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3244 return LLVMBuildBitCast(ctx->ac.builder, val,
3245 get_def_type(ctx, &instr->dest.ssa),
3246 "");
3247 }
3248 case nir_var_shader_out:
3249 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3250 return load_tess_varyings(ctx, instr, false);
3251 }
3252
3253 for (unsigned chan = comp; chan < ve + comp; chan++) {
3254 if (indir_index) {
3255 unsigned count = glsl_count_attribute_slots(
3256 instr->variables[0]->var->type, false);
3257 count -= chan / 4;
3258 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3259 &ctx->ac, ctx->outputs + idx + chan, count,
3260 stride, true, true);
3261
3262 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3263 tmp_vec,
3264 indir_index, "");
3265 } else {
3266 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3267 ctx->outputs[idx + chan + const_index * stride],
3268 "");
3269 }
3270 }
3271 break;
3272 default:
3273 unreachable("unhandle variable mode");
3274 }
3275 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3276 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3277 }
3278
3279 static void
3280 visit_store_var(struct ac_nir_context *ctx,
3281 nir_intrinsic_instr *instr)
3282 {
3283 LLVMValueRef temp_ptr, value;
3284 int idx = instr->variables[0]->var->data.driver_location;
3285 unsigned comp = instr->variables[0]->var->data.location_frac;
3286 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3287 int writemask = instr->const_index[0] << comp;
3288 LLVMValueRef indir_index;
3289 unsigned const_index;
3290 get_deref_offset(ctx, instr->variables[0], false,
3291 NULL, NULL, &const_index, &indir_index);
3292
3293 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3294
3295 src = LLVMBuildBitCast(ctx->ac.builder, src,
3296 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3297 "");
3298
3299 writemask = widen_mask(writemask, 2);
3300 }
3301
3302 switch (instr->variables[0]->var->data.mode) {
3303 case nir_var_shader_out:
3304
3305 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3306 LLVMValueRef vertex_index = NULL;
3307 LLVMValueRef indir_index = NULL;
3308 unsigned const_index = 0;
3309 const unsigned location = instr->variables[0]->var->data.location;
3310 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3311 const unsigned comp = instr->variables[0]->var->data.location_frac;
3312 const bool is_patch = instr->variables[0]->var->data.patch;
3313 const bool is_compact = instr->variables[0]->var->data.compact;
3314
3315 get_deref_offset(ctx, instr->variables[0],
3316 false, NULL, is_patch ? NULL : &vertex_index,
3317 &const_index, &indir_index);
3318
3319 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3320 const_index, location, driver_location,
3321 src, comp, is_patch, is_compact, writemask);
3322 return;
3323 }
3324
3325 for (unsigned chan = 0; chan < 8; chan++) {
3326 int stride = 4;
3327 if (!(writemask & (1 << chan)))
3328 continue;
3329
3330 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3331
3332 if (instr->variables[0]->var->data.compact)
3333 stride = 1;
3334 if (indir_index) {
3335 unsigned count = glsl_count_attribute_slots(
3336 instr->variables[0]->var->type, false);
3337 count -= chan / 4;
3338 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3339 &ctx->ac, ctx->outputs + idx + chan, count,
3340 stride, true, true);
3341
3342 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3343 value, indir_index, "");
3344 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3345 count, stride, tmp_vec);
3346
3347 } else {
3348 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3349
3350 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3351 }
3352 }
3353 break;
3354 case nir_var_local:
3355 for (unsigned chan = 0; chan < 8; chan++) {
3356 if (!(writemask & (1 << chan)))
3357 continue;
3358
3359 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3360 if (indir_index) {
3361 unsigned count = glsl_count_attribute_slots(
3362 instr->variables[0]->var->type, false);
3363 count -= chan / 4;
3364 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3365 &ctx->ac, ctx->locals + idx + chan, count,
3366 4, true, true);
3367
3368 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3369 value, indir_index, "");
3370 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3371 count, 4, tmp_vec);
3372 } else {
3373 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3374
3375 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3376 }
3377 }
3378 break;
3379 case nir_var_shared: {
3380 int writemask = instr->const_index[0];
3381 LLVMValueRef address = build_gep_for_deref(ctx,
3382 instr->variables[0]);
3383 LLVMValueRef val = get_src(ctx, instr->src[0]);
3384 unsigned components =
3385 glsl_get_vector_elements(
3386 nir_deref_tail(&instr->variables[0]->deref)->type);
3387 if (writemask == (1 << components) - 1) {
3388 val = LLVMBuildBitCast(
3389 ctx->ac.builder, val,
3390 LLVMGetElementType(LLVMTypeOf(address)), "");
3391 LLVMBuildStore(ctx->ac.builder, val, address);
3392 } else {
3393 for (unsigned chan = 0; chan < 4; chan++) {
3394 if (!(writemask & (1 << chan)))
3395 continue;
3396 LLVMValueRef ptr =
3397 LLVMBuildStructGEP(ctx->ac.builder,
3398 address, chan, "");
3399 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3400 chan);
3401 src = LLVMBuildBitCast(
3402 ctx->ac.builder, src,
3403 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3404 LLVMBuildStore(ctx->ac.builder, src, ptr);
3405 }
3406 }
3407 break;
3408 }
3409 default:
3410 break;
3411 }
3412 }
3413
3414 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3415 {
3416 switch (dim) {
3417 case GLSL_SAMPLER_DIM_BUF:
3418 return 1;
3419 case GLSL_SAMPLER_DIM_1D:
3420 return array ? 2 : 1;
3421 case GLSL_SAMPLER_DIM_2D:
3422 return array ? 3 : 2;
3423 case GLSL_SAMPLER_DIM_MS:
3424 return array ? 4 : 3;
3425 case GLSL_SAMPLER_DIM_3D:
3426 case GLSL_SAMPLER_DIM_CUBE:
3427 return 3;
3428 case GLSL_SAMPLER_DIM_RECT:
3429 case GLSL_SAMPLER_DIM_SUBPASS:
3430 return 2;
3431 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3432 return 3;
3433 default:
3434 break;
3435 }
3436 return 0;
3437 }
3438
3439
3440
3441 /* Adjust the sample index according to FMASK.
3442 *
3443 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3444 * which is the identity mapping. Each nibble says which physical sample
3445 * should be fetched to get that sample.
3446 *
3447 * For example, 0x11111100 means there are only 2 samples stored and
3448 * the second sample covers 3/4 of the pixel. When reading samples 0
3449 * and 1, return physical sample 0 (determined by the first two 0s
3450 * in FMASK), otherwise return physical sample 1.
3451 *
3452 * The sample index should be adjusted as follows:
3453 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3454 */
3455 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3456 LLVMValueRef coord_x, LLVMValueRef coord_y,
3457 LLVMValueRef coord_z,
3458 LLVMValueRef sample_index,
3459 LLVMValueRef fmask_desc_ptr)
3460 {
3461 LLVMValueRef fmask_load_address[4];
3462 LLVMValueRef res;
3463
3464 fmask_load_address[0] = coord_x;
3465 fmask_load_address[1] = coord_y;
3466 if (coord_z) {
3467 fmask_load_address[2] = coord_z;
3468 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3469 }
3470
3471 struct ac_image_args args = {0};
3472
3473 args.opcode = ac_image_load;
3474 args.da = coord_z ? true : false;
3475 args.resource = fmask_desc_ptr;
3476 args.dmask = 0xf;
3477 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3478
3479 res = ac_build_image_opcode(ctx, &args);
3480
3481 res = ac_to_integer(ctx, res);
3482 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3483 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3484
3485 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3486 res,
3487 ctx->i32_0, "");
3488
3489 LLVMValueRef sample_index4 =
3490 LLVMBuildMul(ctx->builder, sample_index, four, "");
3491 LLVMValueRef shifted_fmask =
3492 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3493 LLVMValueRef final_sample =
3494 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3495
3496 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3497 * resource descriptor is 0 (invalid),
3498 */
3499 LLVMValueRef fmask_desc =
3500 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3501 ctx->v8i32, "");
3502
3503 LLVMValueRef fmask_word1 =
3504 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3505 ctx->i32_1, "");
3506
3507 LLVMValueRef word1_is_nonzero =
3508 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3509 fmask_word1, ctx->i32_0, "");
3510
3511 /* Replace the MSAA sample index. */
3512 sample_index =
3513 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3514 final_sample, sample_index, "");
3515 return sample_index;
3516 }
3517
3518 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3519 const nir_intrinsic_instr *instr)
3520 {
3521 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3522
3523 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3524 LLVMValueRef coords[4];
3525 LLVMValueRef masks[] = {
3526 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3527 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3528 };
3529 LLVMValueRef res;
3530 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3531
3532 int count;
3533 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3534 bool is_array = glsl_sampler_type_is_array(type);
3535 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3536 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3537 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3538 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3539 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3540 count = image_type_to_components_count(dim, is_array);
3541
3542 if (is_ms) {
3543 LLVMValueRef fmask_load_address[3];
3544 int chan;
3545
3546 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3547 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3548 if (is_array)
3549 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3550 else
3551 fmask_load_address[2] = NULL;
3552 if (add_frag_pos) {
3553 for (chan = 0; chan < 2; ++chan)
3554 fmask_load_address[chan] =
3555 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3556 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3557 ctx->ac.i32, ""), "");
3558 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3559 }
3560 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3561 fmask_load_address[0],
3562 fmask_load_address[1],
3563 fmask_load_address[2],
3564 sample_index,
3565 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3566 }
3567 if (count == 1 && !gfx9_1d) {
3568 if (instr->src[0].ssa->num_components)
3569 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3570 else
3571 res = src0;
3572 } else {
3573 int chan;
3574 if (is_ms)
3575 count--;
3576 for (chan = 0; chan < count; ++chan) {
3577 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3578 }
3579 if (add_frag_pos) {
3580 for (chan = 0; chan < 2; ++chan)
3581 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3582 ctx->ac.i32, ""), "");
3583 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3584 count++;
3585 }
3586
3587 if (gfx9_1d) {
3588 if (is_array) {
3589 coords[2] = coords[1];
3590 coords[1] = ctx->ac.i32_0;
3591 } else
3592 coords[1] = ctx->ac.i32_0;
3593 count++;
3594 }
3595
3596 if (is_ms) {
3597 coords[count] = sample_index;
3598 count++;
3599 }
3600
3601 if (count == 3) {
3602 coords[3] = LLVMGetUndef(ctx->ac.i32);
3603 count = 4;
3604 }
3605 res = ac_build_gather_values(&ctx->ac, coords, count);
3606 }
3607 return res;
3608 }
3609
3610 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3611 const nir_intrinsic_instr *instr)
3612 {
3613 LLVMValueRef params[7];
3614 LLVMValueRef res;
3615 char intrinsic_name[64];
3616 const nir_variable *var = instr->variables[0]->var;
3617 const struct glsl_type *type = var->type;
3618
3619 if(instr->variables[0]->deref.child)
3620 type = instr->variables[0]->deref.child->type;
3621
3622 type = glsl_without_array(type);
3623 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3624 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3625 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3626 ctx->ac.i32_0, ""); /* vindex */
3627 params[2] = ctx->ac.i32_0; /* voffset */
3628 params[3] = ctx->ac.i1false; /* glc */
3629 params[4] = ctx->ac.i1false; /* slc */
3630 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3631 params, 5, 0);
3632
3633 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3634 res = ac_to_integer(&ctx->ac, res);
3635 } else {
3636 bool is_da = glsl_sampler_type_is_array(type) ||
3637 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3638 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3639 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3640 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3641 LLVMValueRef glc = ctx->ac.i1false;
3642 LLVMValueRef slc = ctx->ac.i1false;
3643
3644 params[0] = get_image_coords(ctx, instr);
3645 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3646 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3647 if (HAVE_LLVM <= 0x0309) {
3648 params[3] = ctx->ac.i1false; /* r128 */
3649 params[4] = da;
3650 params[5] = glc;
3651 params[6] = slc;
3652 } else {
3653 LLVMValueRef lwe = ctx->ac.i1false;
3654 params[3] = glc;
3655 params[4] = slc;
3656 params[5] = lwe;
3657 params[6] = da;
3658 }
3659
3660 ac_get_image_intr_name("llvm.amdgcn.image.load",
3661 ctx->ac.v4f32, /* vdata */
3662 LLVMTypeOf(params[0]), /* coords */
3663 LLVMTypeOf(params[1]), /* rsrc */
3664 intrinsic_name, sizeof(intrinsic_name));
3665
3666 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3667 params, 7, AC_FUNC_ATTR_READONLY);
3668 }
3669 return ac_to_integer(&ctx->ac, res);
3670 }
3671
3672 static void visit_image_store(struct ac_nir_context *ctx,
3673 nir_intrinsic_instr *instr)
3674 {
3675 LLVMValueRef params[8];
3676 char intrinsic_name[64];
3677 const nir_variable *var = instr->variables[0]->var;
3678 const struct glsl_type *type = glsl_without_array(var->type);
3679 LLVMValueRef glc = ctx->ac.i1false;
3680 bool force_glc = ctx->ac.chip_class == SI;
3681 if (force_glc)
3682 glc = ctx->ac.i1true;
3683
3684 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3685 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3686 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3687 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3688 ctx->ac.i32_0, ""); /* vindex */
3689 params[3] = ctx->ac.i32_0; /* voffset */
3690 params[4] = glc; /* glc */
3691 params[5] = ctx->ac.i1false; /* slc */
3692 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3693 params, 6, 0);
3694 } else {
3695 bool is_da = glsl_sampler_type_is_array(type) ||
3696 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3697 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3698 LLVMValueRef slc = ctx->ac.i1false;
3699
3700 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3701 params[1] = get_image_coords(ctx, instr); /* coords */
3702 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3703 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3704 if (HAVE_LLVM <= 0x0309) {
3705 params[4] = ctx->ac.i1false; /* r128 */
3706 params[5] = da;
3707 params[6] = glc;
3708 params[7] = slc;
3709 } else {
3710 LLVMValueRef lwe = ctx->ac.i1false;
3711 params[4] = glc;
3712 params[5] = slc;
3713 params[6] = lwe;
3714 params[7] = da;
3715 }
3716
3717 ac_get_image_intr_name("llvm.amdgcn.image.store",
3718 LLVMTypeOf(params[0]), /* vdata */
3719 LLVMTypeOf(params[1]), /* coords */
3720 LLVMTypeOf(params[2]), /* rsrc */
3721 intrinsic_name, sizeof(intrinsic_name));
3722
3723 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3724 params, 8, 0);
3725 }
3726
3727 }
3728
3729 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3730 const nir_intrinsic_instr *instr)
3731 {
3732 LLVMValueRef params[7];
3733 int param_count = 0;
3734 const nir_variable *var = instr->variables[0]->var;
3735
3736 const char *atomic_name;
3737 char intrinsic_name[41];
3738 const struct glsl_type *type = glsl_without_array(var->type);
3739 MAYBE_UNUSED int length;
3740
3741 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3742
3743 switch (instr->intrinsic) {
3744 case nir_intrinsic_image_atomic_add:
3745 atomic_name = "add";
3746 break;
3747 case nir_intrinsic_image_atomic_min:
3748 atomic_name = is_unsigned ? "umin" : "smin";
3749 break;
3750 case nir_intrinsic_image_atomic_max:
3751 atomic_name = is_unsigned ? "umax" : "smax";
3752 break;
3753 case nir_intrinsic_image_atomic_and:
3754 atomic_name = "and";
3755 break;
3756 case nir_intrinsic_image_atomic_or:
3757 atomic_name = "or";
3758 break;
3759 case nir_intrinsic_image_atomic_xor:
3760 atomic_name = "xor";
3761 break;
3762 case nir_intrinsic_image_atomic_exchange:
3763 atomic_name = "swap";
3764 break;
3765 case nir_intrinsic_image_atomic_comp_swap:
3766 atomic_name = "cmpswap";
3767 break;
3768 default:
3769 abort();
3770 }
3771
3772 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3773 params[param_count++] = get_src(ctx, instr->src[3]);
3774 params[param_count++] = get_src(ctx, instr->src[2]);
3775
3776 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3777 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3778 NULL, true, true);
3779 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3780 ctx->ac.i32_0, ""); /* vindex */
3781 params[param_count++] = ctx->ac.i32_0; /* voffset */
3782 params[param_count++] = ctx->ac.i1false; /* slc */
3783
3784 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3785 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3786 } else {
3787 char coords_type[8];
3788
3789 bool da = glsl_sampler_type_is_array(type) ||
3790 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3791
3792 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3793 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3794 NULL, true, true);
3795 params[param_count++] = ctx->ac.i1false; /* r128 */
3796 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3797 params[param_count++] = ctx->ac.i1false; /* slc */
3798
3799 build_int_type_name(LLVMTypeOf(coords),
3800 coords_type, sizeof(coords_type));
3801
3802 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3803 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3804 }
3805
3806 assert(length < sizeof(intrinsic_name));
3807 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3808 }
3809
3810 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3811 const nir_intrinsic_instr *instr)
3812 {
3813 LLVMValueRef res;
3814 const nir_variable *var = instr->variables[0]->var;
3815 const struct glsl_type *type = instr->variables[0]->var->type;
3816 bool da = glsl_sampler_type_is_array(var->type) ||
3817 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3818 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3819 if(instr->variables[0]->deref.child)
3820 type = instr->variables[0]->deref.child->type;
3821
3822 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3823 return get_buffer_size(ctx,
3824 get_sampler_desc(ctx, instr->variables[0],
3825 AC_DESC_BUFFER, NULL, true, false), true);
3826
3827 struct ac_image_args args = { 0 };
3828
3829 args.da = da;
3830 args.dmask = 0xf;
3831 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3832 args.opcode = ac_image_get_resinfo;
3833 args.addr = ctx->ac.i32_0;
3834
3835 res = ac_build_image_opcode(&ctx->ac, &args);
3836
3837 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3838
3839 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3840 glsl_sampler_type_is_array(type)) {
3841 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3842 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3843 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3844 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3845 }
3846 if (ctx->ac.chip_class >= GFX9 &&
3847 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3848 glsl_sampler_type_is_array(type)) {
3849 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3850 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3851 ctx->ac.i32_1, "");
3852
3853 }
3854 return res;
3855 }
3856
3857 #define NOOP_WAITCNT 0xf7f
3858 #define LGKM_CNT 0x07f
3859 #define VM_CNT 0xf70
3860
3861 static void emit_membar(struct nir_to_llvm_context *ctx,
3862 const nir_intrinsic_instr *instr)
3863 {
3864 unsigned waitcnt = NOOP_WAITCNT;
3865
3866 switch (instr->intrinsic) {
3867 case nir_intrinsic_memory_barrier:
3868 case nir_intrinsic_group_memory_barrier:
3869 waitcnt &= VM_CNT & LGKM_CNT;
3870 break;
3871 case nir_intrinsic_memory_barrier_atomic_counter:
3872 case nir_intrinsic_memory_barrier_buffer:
3873 case nir_intrinsic_memory_barrier_image:
3874 waitcnt &= VM_CNT;
3875 break;
3876 case nir_intrinsic_memory_barrier_shared:
3877 waitcnt &= LGKM_CNT;
3878 break;
3879 default:
3880 break;
3881 }
3882 if (waitcnt != NOOP_WAITCNT)
3883 ac_build_waitcnt(&ctx->ac, waitcnt);
3884 }
3885
3886 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3887 {
3888 /* SI only (thanks to a hw bug workaround):
3889 * The real barrier instruction isn’t needed, because an entire patch
3890 * always fits into a single wave.
3891 */
3892 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3893 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3894 return;
3895 }
3896 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3897 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3898 }
3899
3900 static void emit_discard(struct ac_nir_context *ctx,
3901 const nir_intrinsic_instr *instr)
3902 {
3903 LLVMValueRef cond;
3904
3905 if (instr->intrinsic == nir_intrinsic_discard_if) {
3906 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3907 get_src(ctx, instr->src[0]),
3908 ctx->ac.i32_0, "");
3909 } else {
3910 assert(instr->intrinsic == nir_intrinsic_discard);
3911 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3912 }
3913
3914 ac_build_kill_if_false(&ctx->ac, cond);
3915 }
3916
3917 static LLVMValueRef
3918 visit_load_helper_invocation(struct ac_nir_context *ctx)
3919 {
3920 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3921 "llvm.amdgcn.ps.live",
3922 ctx->ac.i1, NULL, 0,
3923 AC_FUNC_ATTR_READNONE);
3924 result = LLVMBuildNot(ctx->ac.builder, result, "");
3925 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3926 }
3927
3928 static LLVMValueRef
3929 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3930 {
3931 LLVMValueRef result;
3932 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3933 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3934 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3935
3936 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3937 }
3938
3939 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3940 const nir_intrinsic_instr *instr)
3941 {
3942 LLVMValueRef ptr, result;
3943 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3944 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3945
3946 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3947 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3948 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3949 ptr, src, src1,
3950 LLVMAtomicOrderingSequentiallyConsistent,
3951 LLVMAtomicOrderingSequentiallyConsistent,
3952 false);
3953 } else {
3954 LLVMAtomicRMWBinOp op;
3955 switch (instr->intrinsic) {
3956 case nir_intrinsic_var_atomic_add:
3957 op = LLVMAtomicRMWBinOpAdd;
3958 break;
3959 case nir_intrinsic_var_atomic_umin:
3960 op = LLVMAtomicRMWBinOpUMin;
3961 break;
3962 case nir_intrinsic_var_atomic_umax:
3963 op = LLVMAtomicRMWBinOpUMax;
3964 break;
3965 case nir_intrinsic_var_atomic_imin:
3966 op = LLVMAtomicRMWBinOpMin;
3967 break;
3968 case nir_intrinsic_var_atomic_imax:
3969 op = LLVMAtomicRMWBinOpMax;
3970 break;
3971 case nir_intrinsic_var_atomic_and:
3972 op = LLVMAtomicRMWBinOpAnd;
3973 break;
3974 case nir_intrinsic_var_atomic_or:
3975 op = LLVMAtomicRMWBinOpOr;
3976 break;
3977 case nir_intrinsic_var_atomic_xor:
3978 op = LLVMAtomicRMWBinOpXor;
3979 break;
3980 case nir_intrinsic_var_atomic_exchange:
3981 op = LLVMAtomicRMWBinOpXchg;
3982 break;
3983 default:
3984 return NULL;
3985 }
3986
3987 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3988 LLVMAtomicOrderingSequentiallyConsistent,
3989 false);
3990 }
3991 return result;
3992 }
3993
3994 #define INTERP_CENTER 0
3995 #define INTERP_CENTROID 1
3996 #define INTERP_SAMPLE 2
3997
3998 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3999 enum glsl_interp_mode interp, unsigned location)
4000 {
4001 switch (interp) {
4002 case INTERP_MODE_FLAT:
4003 default:
4004 return NULL;
4005 case INTERP_MODE_SMOOTH:
4006 case INTERP_MODE_NONE:
4007 if (location == INTERP_CENTER)
4008 return ctx->persp_center;
4009 else if (location == INTERP_CENTROID)
4010 return ctx->persp_centroid;
4011 else if (location == INTERP_SAMPLE)
4012 return ctx->persp_sample;
4013 break;
4014 case INTERP_MODE_NOPERSPECTIVE:
4015 if (location == INTERP_CENTER)
4016 return ctx->linear_center;
4017 else if (location == INTERP_CENTROID)
4018 return ctx->linear_centroid;
4019 else if (location == INTERP_SAMPLE)
4020 return ctx->linear_sample;
4021 break;
4022 }
4023 return NULL;
4024 }
4025
4026 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
4027 LLVMValueRef sample_id)
4028 {
4029 LLVMValueRef result;
4030 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4031
4032 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4033 const_array(ctx->ac.v2f32, 64), "");
4034
4035 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4036 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4037
4038 return result;
4039 }
4040
4041 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4042 {
4043 LLVMValueRef values[2];
4044
4045 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
4046 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
4047 return ac_build_gather_values(&ctx->ac, values, 2);
4048 }
4049
4050 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
4051 const nir_intrinsic_instr *instr)
4052 {
4053 LLVMValueRef result[4];
4054 LLVMValueRef interp_param, attr_number;
4055 unsigned location;
4056 unsigned chan;
4057 LLVMValueRef src_c0 = NULL;
4058 LLVMValueRef src_c1 = NULL;
4059 LLVMValueRef src0 = NULL;
4060 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4061 switch (instr->intrinsic) {
4062 case nir_intrinsic_interp_var_at_centroid:
4063 location = INTERP_CENTROID;
4064 break;
4065 case nir_intrinsic_interp_var_at_sample:
4066 case nir_intrinsic_interp_var_at_offset:
4067 location = INTERP_CENTER;
4068 src0 = get_src(ctx->nir, instr->src[0]);
4069 break;
4070 default:
4071 break;
4072 }
4073
4074 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4075 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4076 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4077 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4078 LLVMValueRef sample_position;
4079 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4080
4081 /* fetch sample ID */
4082 sample_position = load_sample_position(ctx, src0);
4083
4084 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4085 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4086 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4087 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4088 }
4089 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4090 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4091
4092 if (location == INTERP_CENTER) {
4093 LLVMValueRef ij_out[2];
4094 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4095
4096 /*
4097 * take the I then J parameters, and the DDX/Y for it, and
4098 * calculate the IJ inputs for the interpolator.
4099 * temp1 = ddx * offset/sample.x + I;
4100 * interp_param.I = ddy * offset/sample.y + temp1;
4101 * temp1 = ddx * offset/sample.x + J;
4102 * interp_param.J = ddy * offset/sample.y + temp1;
4103 */
4104 for (unsigned i = 0; i < 2; i++) {
4105 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4106 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4107 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4108 ddxy_out, ix_ll, "");
4109 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4110 ddxy_out, iy_ll, "");
4111 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4112 interp_param, ix_ll, "");
4113 LLVMValueRef temp1, temp2;
4114
4115 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4116 ctx->ac.f32, "");
4117
4118 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4119 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4120
4121 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4122 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4123
4124 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4125 temp2, ctx->ac.i32, "");
4126 }
4127 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4128
4129 }
4130
4131 for (chan = 0; chan < 4; chan++) {
4132 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4133
4134 if (interp_param) {
4135 interp_param = LLVMBuildBitCast(ctx->builder,
4136 interp_param, ctx->ac.v2f32, "");
4137 LLVMValueRef i = LLVMBuildExtractElement(
4138 ctx->builder, interp_param, ctx->ac.i32_0, "");
4139 LLVMValueRef j = LLVMBuildExtractElement(
4140 ctx->builder, interp_param, ctx->ac.i32_1, "");
4141
4142 result[chan] = ac_build_fs_interp(&ctx->ac,
4143 llvm_chan, attr_number,
4144 ctx->prim_mask, i, j);
4145 } else {
4146 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4147 LLVMConstInt(ctx->ac.i32, 2, false),
4148 llvm_chan, attr_number,
4149 ctx->prim_mask);
4150 }
4151 }
4152 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4153 instr->variables[0]->var->data.location_frac);
4154 }
4155
4156 static void
4157 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4158 {
4159 LLVMValueRef gs_next_vertex;
4160 LLVMValueRef can_emit;
4161 int idx;
4162 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4163
4164 assert(stream == 0);
4165
4166 /* Write vertex attribute values to GSVS ring */
4167 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4168 ctx->gs_next_vertex,
4169 "");
4170
4171 /* If this thread has already emitted the declared maximum number of
4172 * vertices, kill it: excessive vertex emissions are not supposed to
4173 * have any effect, and GS threads have no externally observable
4174 * effects other than emitting vertices.
4175 */
4176 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4177 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4178 ac_build_kill_if_false(&ctx->ac, can_emit);
4179
4180 /* loop num outputs */
4181 idx = 0;
4182 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4183 LLVMValueRef *out_ptr = &addrs[i * 4];
4184 int length = 4;
4185 int slot = idx;
4186 int slot_inc = 1;
4187
4188 if (!(ctx->output_mask & (1ull << i)))
4189 continue;
4190
4191 if (i == VARYING_SLOT_CLIP_DIST0) {
4192 /* pack clip and cull into a single set of slots */
4193 length = ctx->num_output_clips + ctx->num_output_culls;
4194 if (length > 4)
4195 slot_inc = 2;
4196 }
4197 for (unsigned j = 0; j < length; j++) {
4198 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4199 out_ptr[j], "");
4200 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4201 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4202 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4203
4204 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4205
4206 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4207 out_val, 1,
4208 voffset, ctx->gs2vs_offset, 0,
4209 1, 1, true, true);
4210 }
4211 idx += slot_inc;
4212 }
4213
4214 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4215 ctx->ac.i32_1, "");
4216 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4217
4218 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4219 }
4220
4221 static void
4222 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4223 {
4224 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4225 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4226 }
4227
4228 static LLVMValueRef
4229 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4230 unsigned num_components)
4231 {
4232 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4233
4234 LLVMValueRef coord[4] = {
4235 ctx->tes_u,
4236 ctx->tes_v,
4237 ctx->ac.f32_0,
4238 ctx->ac.f32_0,
4239 };
4240
4241 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4242 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4243 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4244
4245 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4246 return LLVMBuildBitCast(ctx->builder, result, type, "");
4247 }
4248
4249 static LLVMValueRef
4250 load_patch_vertices_in(struct ac_shader_abi *abi)
4251 {
4252 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4253 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4254 }
4255
4256 static void visit_intrinsic(struct ac_nir_context *ctx,
4257 nir_intrinsic_instr *instr)
4258 {
4259 LLVMValueRef result = NULL;
4260
4261 switch (instr->intrinsic) {
4262 case nir_intrinsic_ballot:
4263 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4264 break;
4265 case nir_intrinsic_read_invocation:
4266 case nir_intrinsic_read_first_invocation: {
4267 LLVMValueRef args[2];
4268
4269 /* Value */
4270 args[0] = get_src(ctx, instr->src[0]);
4271
4272 unsigned num_args;
4273 const char *intr_name;
4274 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4275 num_args = 2;
4276 intr_name = "llvm.amdgcn.readlane";
4277
4278 /* Invocation */
4279 args[1] = get_src(ctx, instr->src[1]);
4280 } else {
4281 num_args = 1;
4282 intr_name = "llvm.amdgcn.readfirstlane";
4283 }
4284
4285 /* We currently have no other way to prevent LLVM from lifting the icmp
4286 * calls to a dominating basic block.
4287 */
4288 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4289
4290 result = ac_build_intrinsic(&ctx->ac, intr_name,
4291 ctx->ac.i32, args, num_args,
4292 AC_FUNC_ATTR_READNONE |
4293 AC_FUNC_ATTR_CONVERGENT);
4294 break;
4295 }
4296 case nir_intrinsic_load_subgroup_invocation:
4297 result = ac_get_thread_id(&ctx->ac);
4298 break;
4299 case nir_intrinsic_load_work_group_id: {
4300 LLVMValueRef values[3];
4301
4302 for (int i = 0; i < 3; i++) {
4303 values[i] = ctx->nctx->workgroup_ids[i] ?
4304 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4305 }
4306
4307 result = ac_build_gather_values(&ctx->ac, values, 3);
4308 break;
4309 }
4310 case nir_intrinsic_load_base_vertex: {
4311 result = ctx->abi->base_vertex;
4312 break;
4313 }
4314 case nir_intrinsic_load_vertex_id_zero_base: {
4315 result = ctx->abi->vertex_id;
4316 break;
4317 }
4318 case nir_intrinsic_load_local_invocation_id: {
4319 result = ctx->nctx->local_invocation_ids;
4320 break;
4321 }
4322 case nir_intrinsic_load_base_instance:
4323 result = ctx->abi->start_instance;
4324 break;
4325 case nir_intrinsic_load_draw_id:
4326 result = ctx->abi->draw_id;
4327 break;
4328 case nir_intrinsic_load_view_index:
4329 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4330 break;
4331 case nir_intrinsic_load_invocation_id:
4332 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4333 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4334 else
4335 result = ctx->abi->gs_invocation_id;
4336 break;
4337 case nir_intrinsic_load_primitive_id:
4338 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4339 result = ctx->abi->gs_prim_id;
4340 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4341 result = ctx->abi->tcs_patch_id;
4342 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4343 result = ctx->abi->tes_patch_id;
4344 } else
4345 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4346 break;
4347 case nir_intrinsic_load_sample_id:
4348 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4349 break;
4350 case nir_intrinsic_load_sample_pos:
4351 result = load_sample_pos(ctx);
4352 break;
4353 case nir_intrinsic_load_sample_mask_in:
4354 result = ctx->abi->sample_coverage;
4355 break;
4356 case nir_intrinsic_load_frag_coord: {
4357 LLVMValueRef values[4] = {
4358 ctx->abi->frag_pos[0],
4359 ctx->abi->frag_pos[1],
4360 ctx->abi->frag_pos[2],
4361 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4362 };
4363 result = ac_build_gather_values(&ctx->ac, values, 4);
4364 break;
4365 }
4366 case nir_intrinsic_load_front_face:
4367 result = ctx->abi->front_face;
4368 break;
4369 case nir_intrinsic_load_helper_invocation:
4370 result = visit_load_helper_invocation(ctx);
4371 break;
4372 case nir_intrinsic_load_instance_id:
4373 result = ctx->abi->instance_id;
4374 break;
4375 case nir_intrinsic_load_num_work_groups:
4376 result = ctx->nctx->num_work_groups;
4377 break;
4378 case nir_intrinsic_load_local_invocation_index:
4379 result = visit_load_local_invocation_index(ctx->nctx);
4380 break;
4381 case nir_intrinsic_load_push_constant:
4382 result = visit_load_push_constant(ctx->nctx, instr);
4383 break;
4384 case nir_intrinsic_vulkan_resource_index:
4385 result = visit_vulkan_resource_index(ctx->nctx, instr);
4386 break;
4387 case nir_intrinsic_vulkan_resource_reindex:
4388 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4389 break;
4390 case nir_intrinsic_store_ssbo:
4391 visit_store_ssbo(ctx, instr);
4392 break;
4393 case nir_intrinsic_load_ssbo:
4394 result = visit_load_buffer(ctx, instr);
4395 break;
4396 case nir_intrinsic_ssbo_atomic_add:
4397 case nir_intrinsic_ssbo_atomic_imin:
4398 case nir_intrinsic_ssbo_atomic_umin:
4399 case nir_intrinsic_ssbo_atomic_imax:
4400 case nir_intrinsic_ssbo_atomic_umax:
4401 case nir_intrinsic_ssbo_atomic_and:
4402 case nir_intrinsic_ssbo_atomic_or:
4403 case nir_intrinsic_ssbo_atomic_xor:
4404 case nir_intrinsic_ssbo_atomic_exchange:
4405 case nir_intrinsic_ssbo_atomic_comp_swap:
4406 result = visit_atomic_ssbo(ctx, instr);
4407 break;
4408 case nir_intrinsic_load_ubo:
4409 result = visit_load_ubo_buffer(ctx, instr);
4410 break;
4411 case nir_intrinsic_get_buffer_size:
4412 result = visit_get_buffer_size(ctx, instr);
4413 break;
4414 case nir_intrinsic_load_var:
4415 result = visit_load_var(ctx, instr);
4416 break;
4417 case nir_intrinsic_store_var:
4418 visit_store_var(ctx, instr);
4419 break;
4420 case nir_intrinsic_image_load:
4421 result = visit_image_load(ctx, instr);
4422 break;
4423 case nir_intrinsic_image_store:
4424 visit_image_store(ctx, instr);
4425 break;
4426 case nir_intrinsic_image_atomic_add:
4427 case nir_intrinsic_image_atomic_min:
4428 case nir_intrinsic_image_atomic_max:
4429 case nir_intrinsic_image_atomic_and:
4430 case nir_intrinsic_image_atomic_or:
4431 case nir_intrinsic_image_atomic_xor:
4432 case nir_intrinsic_image_atomic_exchange:
4433 case nir_intrinsic_image_atomic_comp_swap:
4434 result = visit_image_atomic(ctx, instr);
4435 break;
4436 case nir_intrinsic_image_size:
4437 result = visit_image_size(ctx, instr);
4438 break;
4439 case nir_intrinsic_discard:
4440 case nir_intrinsic_discard_if:
4441 emit_discard(ctx, instr);
4442 break;
4443 case nir_intrinsic_memory_barrier:
4444 case nir_intrinsic_group_memory_barrier:
4445 case nir_intrinsic_memory_barrier_atomic_counter:
4446 case nir_intrinsic_memory_barrier_buffer:
4447 case nir_intrinsic_memory_barrier_image:
4448 case nir_intrinsic_memory_barrier_shared:
4449 emit_membar(ctx->nctx, instr);
4450 break;
4451 case nir_intrinsic_barrier:
4452 emit_barrier(&ctx->ac, ctx->stage);
4453 break;
4454 case nir_intrinsic_var_atomic_add:
4455 case nir_intrinsic_var_atomic_imin:
4456 case nir_intrinsic_var_atomic_umin:
4457 case nir_intrinsic_var_atomic_imax:
4458 case nir_intrinsic_var_atomic_umax:
4459 case nir_intrinsic_var_atomic_and:
4460 case nir_intrinsic_var_atomic_or:
4461 case nir_intrinsic_var_atomic_xor:
4462 case nir_intrinsic_var_atomic_exchange:
4463 case nir_intrinsic_var_atomic_comp_swap:
4464 result = visit_var_atomic(ctx->nctx, instr);
4465 break;
4466 case nir_intrinsic_interp_var_at_centroid:
4467 case nir_intrinsic_interp_var_at_sample:
4468 case nir_intrinsic_interp_var_at_offset:
4469 result = visit_interp(ctx->nctx, instr);
4470 break;
4471 case nir_intrinsic_emit_vertex:
4472 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4473 break;
4474 case nir_intrinsic_end_primitive:
4475 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4476 break;
4477 case nir_intrinsic_load_tess_coord: {
4478 LLVMTypeRef type = ctx->nctx ?
4479 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4480 NULL;
4481 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4482 break;
4483 }
4484 case nir_intrinsic_load_tess_level_outer:
4485 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4486 break;
4487 case nir_intrinsic_load_tess_level_inner:
4488 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4489 break;
4490 case nir_intrinsic_load_patch_vertices_in:
4491 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4492 break;
4493 case nir_intrinsic_vote_all: {
4494 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4495 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4496 break;
4497 }
4498 case nir_intrinsic_vote_any: {
4499 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4500 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4501 break;
4502 }
4503 case nir_intrinsic_vote_eq: {
4504 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4505 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4506 break;
4507 }
4508 default:
4509 fprintf(stderr, "Unknown intrinsic: ");
4510 nir_print_instr(&instr->instr, stderr);
4511 fprintf(stderr, "\n");
4512 break;
4513 }
4514 if (result) {
4515 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4516 }
4517 }
4518
4519 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4520 LLVMValueRef buffer_ptr, bool write)
4521 {
4522 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4523
4524 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4525 ctx->shader_info->fs.writes_memory = true;
4526
4527 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4528 }
4529
4530 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4531 {
4532 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4533
4534 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4535 }
4536
4537 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4538 unsigned descriptor_set,
4539 unsigned base_index,
4540 unsigned constant_index,
4541 LLVMValueRef index,
4542 enum ac_descriptor_type desc_type,
4543 bool image, bool write)
4544 {
4545 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4546 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4547 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4548 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4549 unsigned offset = binding->offset;
4550 unsigned stride = binding->size;
4551 unsigned type_size;
4552 LLVMBuilderRef builder = ctx->builder;
4553 LLVMTypeRef type;
4554
4555 assert(base_index < layout->binding_count);
4556
4557 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4558 ctx->shader_info->fs.writes_memory = true;
4559
4560 switch (desc_type) {
4561 case AC_DESC_IMAGE:
4562 type = ctx->ac.v8i32;
4563 type_size = 32;
4564 break;
4565 case AC_DESC_FMASK:
4566 type = ctx->ac.v8i32;
4567 offset += 32;
4568 type_size = 32;
4569 break;
4570 case AC_DESC_SAMPLER:
4571 type = ctx->ac.v4i32;
4572 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4573 offset += 64;
4574
4575 type_size = 16;
4576 break;
4577 case AC_DESC_BUFFER:
4578 type = ctx->ac.v4i32;
4579 type_size = 16;
4580 break;
4581 default:
4582 unreachable("invalid desc_type\n");
4583 }
4584
4585 offset += constant_index * stride;
4586
4587 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4588 (!index || binding->immutable_samplers_equal)) {
4589 if (binding->immutable_samplers_equal)
4590 constant_index = 0;
4591
4592 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4593
4594 LLVMValueRef constants[] = {
4595 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4596 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4597 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4598 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4599 };
4600 return ac_build_gather_values(&ctx->ac, constants, 4);
4601 }
4602
4603 assert(stride % type_size == 0);
4604
4605 if (!index)
4606 index = ctx->ac.i32_0;
4607
4608 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4609
4610 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4611 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4612
4613 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4614 }
4615
4616 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4617 const nir_deref_var *deref,
4618 enum ac_descriptor_type desc_type,
4619 const nir_tex_instr *tex_instr,
4620 bool image, bool write)
4621 {
4622 LLVMValueRef index = NULL;
4623 unsigned constant_index = 0;
4624 unsigned descriptor_set;
4625 unsigned base_index;
4626
4627 if (!deref) {
4628 assert(tex_instr && !image);
4629 descriptor_set = 0;
4630 base_index = tex_instr->sampler_index;
4631 } else {
4632 const nir_deref *tail = &deref->deref;
4633 while (tail->child) {
4634 const nir_deref_array *child = nir_deref_as_array(tail->child);
4635 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4636
4637 if (!array_size)
4638 array_size = 1;
4639
4640 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4641
4642 if (child->deref_array_type == nir_deref_array_type_indirect) {
4643 LLVMValueRef indirect = get_src(ctx, child->indirect);
4644
4645 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4646 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4647
4648 if (!index)
4649 index = indirect;
4650 else
4651 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4652 }
4653
4654 constant_index += child->base_offset * array_size;
4655
4656 tail = &child->deref;
4657 }
4658 descriptor_set = deref->var->data.descriptor_set;
4659 base_index = deref->var->data.binding;
4660 }
4661
4662 return ctx->abi->load_sampler_desc(ctx->abi,
4663 descriptor_set,
4664 base_index,
4665 constant_index, index,
4666 desc_type, image, write);
4667 }
4668
4669 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4670 struct ac_image_args *args,
4671 const nir_tex_instr *instr,
4672 nir_texop op,
4673 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4674 LLVMValueRef *param, unsigned count,
4675 unsigned dmask)
4676 {
4677 unsigned is_rect = 0;
4678 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4679
4680 if (op == nir_texop_lod)
4681 da = false;
4682 /* Pad to power of two vector */
4683 while (count < util_next_power_of_two(count))
4684 param[count++] = LLVMGetUndef(ctx->i32);
4685
4686 if (count > 1)
4687 args->addr = ac_build_gather_values(ctx, param, count);
4688 else
4689 args->addr = param[0];
4690
4691 args->resource = res_ptr;
4692 args->sampler = samp_ptr;
4693
4694 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4695 args->addr = param[0];
4696 return;
4697 }
4698
4699 args->dmask = dmask;
4700 args->unorm = is_rect;
4701 args->da = da;
4702 }
4703
4704 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4705 *
4706 * SI-CI:
4707 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4708 * filtering manually. The driver sets img7 to a mask clearing
4709 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4710 * s_and_b32 samp0, samp0, img7
4711 *
4712 * VI:
4713 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4714 */
4715 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4716 LLVMValueRef res, LLVMValueRef samp)
4717 {
4718 LLVMBuilderRef builder = ctx->ac.builder;
4719 LLVMValueRef img7, samp0;
4720
4721 if (ctx->ac.chip_class >= VI)
4722 return samp;
4723
4724 img7 = LLVMBuildExtractElement(builder, res,
4725 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4726 samp0 = LLVMBuildExtractElement(builder, samp,
4727 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4728 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4729 return LLVMBuildInsertElement(builder, samp, samp0,
4730 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4731 }
4732
4733 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4734 nir_tex_instr *instr,
4735 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4736 LLVMValueRef *fmask_ptr)
4737 {
4738 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4739 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4740 else
4741 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4742 if (samp_ptr) {
4743 if (instr->sampler)
4744 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4745 else
4746 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4747 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4748 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4749 }
4750 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4751 instr->op == nir_texop_samples_identical))
4752 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4753 }
4754
4755 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4756 LLVMValueRef coord)
4757 {
4758 coord = ac_to_float(ctx, coord);
4759 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4760 coord = ac_to_integer(ctx, coord);
4761 return coord;
4762 }
4763
4764 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4765 {
4766 LLVMValueRef result = NULL;
4767 struct ac_image_args args = { 0 };
4768 unsigned dmask = 0xf;
4769 LLVMValueRef address[16];
4770 LLVMValueRef coords[5];
4771 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4772 LLVMValueRef bias = NULL, offsets = NULL;
4773 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4774 LLVMValueRef ddx = NULL, ddy = NULL;
4775 LLVMValueRef derivs[6];
4776 unsigned chan, count = 0;
4777 unsigned const_src = 0, num_deriv_comp = 0;
4778 bool lod_is_zero = false;
4779
4780 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4781
4782 for (unsigned i = 0; i < instr->num_srcs; i++) {
4783 switch (instr->src[i].src_type) {
4784 case nir_tex_src_coord:
4785 coord = get_src(ctx, instr->src[i].src);
4786 break;
4787 case nir_tex_src_projector:
4788 break;
4789 case nir_tex_src_comparator:
4790 comparator = get_src(ctx, instr->src[i].src);
4791 break;
4792 case nir_tex_src_offset:
4793 offsets = get_src(ctx, instr->src[i].src);
4794 const_src = i;
4795 break;
4796 case nir_tex_src_bias:
4797 bias = get_src(ctx, instr->src[i].src);
4798 break;
4799 case nir_tex_src_lod: {
4800 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4801
4802 if (val && val->i32[0] == 0)
4803 lod_is_zero = true;
4804 lod = get_src(ctx, instr->src[i].src);
4805 break;
4806 }
4807 case nir_tex_src_ms_index:
4808 sample_index = get_src(ctx, instr->src[i].src);
4809 break;
4810 case nir_tex_src_ms_mcs:
4811 break;
4812 case nir_tex_src_ddx:
4813 ddx = get_src(ctx, instr->src[i].src);
4814 num_deriv_comp = instr->src[i].src.ssa->num_components;
4815 break;
4816 case nir_tex_src_ddy:
4817 ddy = get_src(ctx, instr->src[i].src);
4818 break;
4819 case nir_tex_src_texture_offset:
4820 case nir_tex_src_sampler_offset:
4821 case nir_tex_src_plane:
4822 default:
4823 break;
4824 }
4825 }
4826
4827 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4828 result = get_buffer_size(ctx, res_ptr, true);
4829 goto write_result;
4830 }
4831
4832 if (instr->op == nir_texop_texture_samples) {
4833 LLVMValueRef res, samples, is_msaa;
4834 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4835 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4836 LLVMConstInt(ctx->ac.i32, 3, false), "");
4837 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4838 LLVMConstInt(ctx->ac.i32, 28, false), "");
4839 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4840 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4841 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4842 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4843
4844 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4845 LLVMConstInt(ctx->ac.i32, 16, false), "");
4846 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4847 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4848 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4849 samples, "");
4850 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4851 ctx->ac.i32_1, "");
4852 result = samples;
4853 goto write_result;
4854 }
4855
4856 if (coord)
4857 for (chan = 0; chan < instr->coord_components; chan++)
4858 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4859
4860 if (offsets && instr->op != nir_texop_txf) {
4861 LLVMValueRef offset[3], pack;
4862 for (chan = 0; chan < 3; ++chan)
4863 offset[chan] = ctx->ac.i32_0;
4864
4865 args.offset = true;
4866 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4867 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4868 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4869 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4870 if (chan)
4871 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4872 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4873 }
4874 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4875 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4876 address[count++] = pack;
4877
4878 }
4879 /* pack LOD bias value */
4880 if (instr->op == nir_texop_txb && bias) {
4881 address[count++] = bias;
4882 }
4883
4884 /* Pack depth comparison value */
4885 if (instr->is_shadow && comparator) {
4886 LLVMValueRef z = ac_to_float(&ctx->ac,
4887 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4888
4889 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4890 * so the depth comparison value isn't clamped for Z16 and
4891 * Z24 anymore. Do it manually here.
4892 *
4893 * It's unnecessary if the original texture format was
4894 * Z32_FLOAT, but we don't know that here.
4895 */
4896 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4897 z = ac_build_clamp(&ctx->ac, z);
4898
4899 address[count++] = z;
4900 }
4901
4902 /* pack derivatives */
4903 if (ddx || ddy) {
4904 int num_src_deriv_channels, num_dest_deriv_channels;
4905 switch (instr->sampler_dim) {
4906 case GLSL_SAMPLER_DIM_3D:
4907 case GLSL_SAMPLER_DIM_CUBE:
4908 num_deriv_comp = 3;
4909 num_src_deriv_channels = 3;
4910 num_dest_deriv_channels = 3;
4911 break;
4912 case GLSL_SAMPLER_DIM_2D:
4913 default:
4914 num_src_deriv_channels = 2;
4915 num_dest_deriv_channels = 2;
4916 num_deriv_comp = 2;
4917 break;
4918 case GLSL_SAMPLER_DIM_1D:
4919 num_src_deriv_channels = 1;
4920 if (ctx->ac.chip_class >= GFX9) {
4921 num_dest_deriv_channels = 2;
4922 num_deriv_comp = 2;
4923 } else {
4924 num_dest_deriv_channels = 1;
4925 num_deriv_comp = 1;
4926 }
4927 break;
4928 }
4929
4930 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4931 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4932 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4933 }
4934 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4935 derivs[i] = ctx->ac.f32_0;
4936 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4937 }
4938 }
4939
4940 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4941 for (chan = 0; chan < instr->coord_components; chan++)
4942 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4943 if (instr->coord_components == 3)
4944 coords[3] = LLVMGetUndef(ctx->ac.f32);
4945 ac_prepare_cube_coords(&ctx->ac,
4946 instr->op == nir_texop_txd, instr->is_array,
4947 instr->op == nir_texop_lod, coords, derivs);
4948 if (num_deriv_comp)
4949 num_deriv_comp--;
4950 }
4951
4952 if (ddx || ddy) {
4953 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4954 address[count++] = derivs[i];
4955 }
4956
4957 /* Pack texture coordinates */
4958 if (coord) {
4959 address[count++] = coords[0];
4960 if (instr->coord_components > 1) {
4961 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4962 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4963 }
4964 address[count++] = coords[1];
4965 }
4966 if (instr->coord_components > 2) {
4967 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4968 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4969 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4970 instr->op != nir_texop_txf) {
4971 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4972 }
4973 address[count++] = coords[2];
4974 }
4975
4976 if (ctx->ac.chip_class >= GFX9) {
4977 LLVMValueRef filler;
4978 if (instr->op == nir_texop_txf)
4979 filler = ctx->ac.i32_0;
4980 else
4981 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4982
4983 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4984 /* No nir_texop_lod, because it does not take a slice
4985 * even with array textures. */
4986 if (instr->is_array && instr->op != nir_texop_lod ) {
4987 address[count] = address[count - 1];
4988 address[count - 1] = filler;
4989 count++;
4990 } else
4991 address[count++] = filler;
4992 }
4993 }
4994 }
4995
4996 /* Pack LOD */
4997 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4998 instr->op == nir_texop_txf)) {
4999 address[count++] = lod;
5000 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5001 address[count++] = sample_index;
5002 } else if(instr->op == nir_texop_txs) {
5003 count = 0;
5004 if (lod)
5005 address[count++] = lod;
5006 else
5007 address[count++] = ctx->ac.i32_0;
5008 }
5009
5010 for (chan = 0; chan < count; chan++) {
5011 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5012 address[chan], ctx->ac.i32, "");
5013 }
5014
5015 if (instr->op == nir_texop_samples_identical) {
5016 LLVMValueRef txf_address[4];
5017 struct ac_image_args txf_args = { 0 };
5018 unsigned txf_count = count;
5019 memcpy(txf_address, address, sizeof(txf_address));
5020
5021 if (!instr->is_array)
5022 txf_address[2] = ctx->ac.i32_0;
5023 txf_address[3] = ctx->ac.i32_0;
5024
5025 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5026 fmask_ptr, NULL,
5027 txf_address, txf_count, 0xf);
5028
5029 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5030
5031 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5032 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5033 goto write_result;
5034 }
5035
5036 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5037 instr->op != nir_texop_txs) {
5038 unsigned sample_chan = instr->is_array ? 3 : 2;
5039 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5040 address[0],
5041 address[1],
5042 instr->is_array ? address[2] : NULL,
5043 address[sample_chan],
5044 fmask_ptr);
5045 }
5046
5047 if (offsets && instr->op == nir_texop_txf) {
5048 nir_const_value *const_offset =
5049 nir_src_as_const_value(instr->src[const_src].src);
5050 int num_offsets = instr->src[const_src].src.ssa->num_components;
5051 assert(const_offset);
5052 num_offsets = MIN2(num_offsets, instr->coord_components);
5053 if (num_offsets > 2)
5054 address[2] = LLVMBuildAdd(ctx->ac.builder,
5055 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5056 if (num_offsets > 1)
5057 address[1] = LLVMBuildAdd(ctx->ac.builder,
5058 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5059 address[0] = LLVMBuildAdd(ctx->ac.builder,
5060 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5061
5062 }
5063
5064 /* TODO TG4 support */
5065 if (instr->op == nir_texop_tg4) {
5066 if (instr->is_shadow)
5067 dmask = 1;
5068 else
5069 dmask = 1 << instr->component;
5070 }
5071 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5072 res_ptr, samp_ptr, address, count, dmask);
5073
5074 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5075
5076 if (instr->op == nir_texop_query_levels)
5077 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5078 else if (instr->is_shadow && instr->is_new_style_shadow &&
5079 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5080 instr->op != nir_texop_tg4)
5081 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5082 else if (instr->op == nir_texop_txs &&
5083 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5084 instr->is_array) {
5085 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5086 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5087 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5088 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5089 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5090 } else if (ctx->ac.chip_class >= GFX9 &&
5091 instr->op == nir_texop_txs &&
5092 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5093 instr->is_array) {
5094 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5095 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5096 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5097 ctx->ac.i32_1, "");
5098 } else if (instr->dest.ssa.num_components != 4)
5099 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5100
5101 write_result:
5102 if (result) {
5103 assert(instr->dest.is_ssa);
5104 result = ac_to_integer(&ctx->ac, result);
5105 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5106 }
5107 }
5108
5109
5110 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5111 {
5112 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5113 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5114
5115 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5116 _mesa_hash_table_insert(ctx->phis, instr, result);
5117 }
5118
5119 static void visit_post_phi(struct ac_nir_context *ctx,
5120 nir_phi_instr *instr,
5121 LLVMValueRef llvm_phi)
5122 {
5123 nir_foreach_phi_src(src, instr) {
5124 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5125 LLVMValueRef llvm_src = get_src(ctx, src->src);
5126
5127 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5128 }
5129 }
5130
5131 static void phi_post_pass(struct ac_nir_context *ctx)
5132 {
5133 struct hash_entry *entry;
5134 hash_table_foreach(ctx->phis, entry) {
5135 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5136 (LLVMValueRef)entry->data);
5137 }
5138 }
5139
5140
5141 static void visit_ssa_undef(struct ac_nir_context *ctx,
5142 const nir_ssa_undef_instr *instr)
5143 {
5144 unsigned num_components = instr->def.num_components;
5145 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5146 LLVMValueRef undef;
5147
5148 if (num_components == 1)
5149 undef = LLVMGetUndef(type);
5150 else {
5151 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5152 }
5153 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5154 }
5155
5156 static void visit_jump(struct ac_nir_context *ctx,
5157 const nir_jump_instr *instr)
5158 {
5159 switch (instr->type) {
5160 case nir_jump_break:
5161 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5162 LLVMClearInsertionPosition(ctx->ac.builder);
5163 break;
5164 case nir_jump_continue:
5165 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5166 LLVMClearInsertionPosition(ctx->ac.builder);
5167 break;
5168 default:
5169 fprintf(stderr, "Unknown NIR jump instr: ");
5170 nir_print_instr(&instr->instr, stderr);
5171 fprintf(stderr, "\n");
5172 abort();
5173 }
5174 }
5175
5176 static void visit_cf_list(struct ac_nir_context *ctx,
5177 struct exec_list *list);
5178
5179 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5180 {
5181 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5182 nir_foreach_instr(instr, block)
5183 {
5184 switch (instr->type) {
5185 case nir_instr_type_alu:
5186 visit_alu(ctx, nir_instr_as_alu(instr));
5187 break;
5188 case nir_instr_type_load_const:
5189 visit_load_const(ctx, nir_instr_as_load_const(instr));
5190 break;
5191 case nir_instr_type_intrinsic:
5192 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5193 break;
5194 case nir_instr_type_tex:
5195 visit_tex(ctx, nir_instr_as_tex(instr));
5196 break;
5197 case nir_instr_type_phi:
5198 visit_phi(ctx, nir_instr_as_phi(instr));
5199 break;
5200 case nir_instr_type_ssa_undef:
5201 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5202 break;
5203 case nir_instr_type_jump:
5204 visit_jump(ctx, nir_instr_as_jump(instr));
5205 break;
5206 default:
5207 fprintf(stderr, "Unknown NIR instr type: ");
5208 nir_print_instr(instr, stderr);
5209 fprintf(stderr, "\n");
5210 abort();
5211 }
5212 }
5213
5214 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5215 }
5216
5217 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5218 {
5219 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5220
5221 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5222 LLVMBasicBlockRef merge_block =
5223 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5224 LLVMBasicBlockRef if_block =
5225 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5226 LLVMBasicBlockRef else_block = merge_block;
5227 if (!exec_list_is_empty(&if_stmt->else_list))
5228 else_block = LLVMAppendBasicBlockInContext(
5229 ctx->ac.context, fn, "");
5230
5231 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5232 ctx->ac.i32_0, "");
5233 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5234
5235 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5236 visit_cf_list(ctx, &if_stmt->then_list);
5237 if (LLVMGetInsertBlock(ctx->ac.builder))
5238 LLVMBuildBr(ctx->ac.builder, merge_block);
5239
5240 if (!exec_list_is_empty(&if_stmt->else_list)) {
5241 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5242 visit_cf_list(ctx, &if_stmt->else_list);
5243 if (LLVMGetInsertBlock(ctx->ac.builder))
5244 LLVMBuildBr(ctx->ac.builder, merge_block);
5245 }
5246
5247 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5248 }
5249
5250 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5251 {
5252 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5253 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5254 LLVMBasicBlockRef break_parent = ctx->break_block;
5255
5256 ctx->continue_block =
5257 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5258 ctx->break_block =
5259 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5260
5261 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5262 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5263 visit_cf_list(ctx, &loop->body);
5264
5265 if (LLVMGetInsertBlock(ctx->ac.builder))
5266 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5267 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5268
5269 ctx->continue_block = continue_parent;
5270 ctx->break_block = break_parent;
5271 }
5272
5273 static void visit_cf_list(struct ac_nir_context *ctx,
5274 struct exec_list *list)
5275 {
5276 foreach_list_typed(nir_cf_node, node, node, list)
5277 {
5278 switch (node->type) {
5279 case nir_cf_node_block:
5280 visit_block(ctx, nir_cf_node_as_block(node));
5281 break;
5282
5283 case nir_cf_node_if:
5284 visit_if(ctx, nir_cf_node_as_if(node));
5285 break;
5286
5287 case nir_cf_node_loop:
5288 visit_loop(ctx, nir_cf_node_as_loop(node));
5289 break;
5290
5291 default:
5292 assert(0);
5293 }
5294 }
5295 }
5296
5297 static void
5298 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5299 struct nir_variable *variable)
5300 {
5301 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5302 LLVMValueRef t_offset;
5303 LLVMValueRef t_list;
5304 LLVMValueRef input;
5305 LLVMValueRef buffer_index;
5306 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5307 int idx = variable->data.location;
5308 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5309
5310 variable->data.driver_location = idx * 4;
5311
5312 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5313 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5314 ctx->abi.start_instance, "");
5315 if (ctx->options->key.vs.as_ls) {
5316 ctx->shader_info->vs.vgpr_comp_cnt =
5317 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5318 } else {
5319 ctx->shader_info->vs.vgpr_comp_cnt =
5320 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5321 }
5322 } else
5323 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5324 ctx->abi.base_vertex, "");
5325
5326 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5327 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5328
5329 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5330
5331 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5332 buffer_index,
5333 ctx->ac.i32_0,
5334 true);
5335
5336 for (unsigned chan = 0; chan < 4; chan++) {
5337 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5338 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5339 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5340 input, llvm_chan, ""));
5341 }
5342 }
5343 }
5344
5345 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5346 unsigned attr,
5347 LLVMValueRef interp_param,
5348 LLVMValueRef prim_mask,
5349 LLVMValueRef result[4])
5350 {
5351 LLVMValueRef attr_number;
5352 unsigned chan;
5353 LLVMValueRef i, j;
5354 bool interp = interp_param != NULL;
5355
5356 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5357
5358 /* fs.constant returns the param from the middle vertex, so it's not
5359 * really useful for flat shading. It's meant to be used for custom
5360 * interpolation (but the intrinsic can't fetch from the other two
5361 * vertices).
5362 *
5363 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5364 * to do the right thing. The only reason we use fs.constant is that
5365 * fs.interp cannot be used on integers, because they can be equal
5366 * to NaN.
5367 */
5368 if (interp) {
5369 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5370 ctx->ac.v2f32, "");
5371
5372 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5373 ctx->ac.i32_0, "");
5374 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5375 ctx->ac.i32_1, "");
5376 }
5377
5378 for (chan = 0; chan < 4; chan++) {
5379 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5380
5381 if (interp) {
5382 result[chan] = ac_build_fs_interp(&ctx->ac,
5383 llvm_chan,
5384 attr_number,
5385 prim_mask, i, j);
5386 } else {
5387 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5388 LLVMConstInt(ctx->ac.i32, 2, false),
5389 llvm_chan,
5390 attr_number,
5391 prim_mask);
5392 }
5393 }
5394 }
5395
5396 static void
5397 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5398 struct nir_variable *variable)
5399 {
5400 int idx = variable->data.location;
5401 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5402 LLVMValueRef interp;
5403
5404 variable->data.driver_location = idx * 4;
5405 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5406
5407 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5408 unsigned interp_type;
5409 if (variable->data.sample) {
5410 interp_type = INTERP_SAMPLE;
5411 ctx->shader_info->info.ps.force_persample = true;
5412 } else if (variable->data.centroid)
5413 interp_type = INTERP_CENTROID;
5414 else
5415 interp_type = INTERP_CENTER;
5416
5417 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5418 } else
5419 interp = NULL;
5420
5421 for (unsigned i = 0; i < attrib_count; ++i)
5422 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5423
5424 }
5425
5426 static void
5427 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5428 struct nir_shader *nir) {
5429 nir_foreach_variable(variable, &nir->inputs)
5430 handle_vs_input_decl(ctx, variable);
5431 }
5432
5433 static void
5434 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5435 struct nir_shader *nir)
5436 {
5437 if (!ctx->options->key.fs.multisample)
5438 return;
5439
5440 bool uses_center = false;
5441 bool uses_centroid = false;
5442 nir_foreach_variable(variable, &nir->inputs) {
5443 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5444 variable->data.sample)
5445 continue;
5446
5447 if (variable->data.centroid)
5448 uses_centroid = true;
5449 else
5450 uses_center = true;
5451 }
5452
5453 if (uses_center && uses_centroid) {
5454 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5455 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5456 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5457 }
5458 }
5459
5460 static void
5461 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5462 struct nir_shader *nir)
5463 {
5464 prepare_interp_optimize(ctx, nir);
5465
5466 nir_foreach_variable(variable, &nir->inputs)
5467 handle_fs_input_decl(ctx, variable);
5468
5469 unsigned index = 0;
5470
5471 if (ctx->shader_info->info.ps.uses_input_attachments ||
5472 ctx->shader_info->info.needs_multiview_view_index)
5473 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5474
5475 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5476 LLVMValueRef interp_param;
5477 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5478
5479 if (!(ctx->input_mask & (1ull << i)))
5480 continue;
5481
5482 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5483 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5484 interp_param = *inputs;
5485 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5486 inputs);
5487
5488 if (!interp_param)
5489 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5490 ++index;
5491 } else if (i == VARYING_SLOT_POS) {
5492 for(int i = 0; i < 3; ++i)
5493 inputs[i] = ctx->abi.frag_pos[i];
5494
5495 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5496 ctx->abi.frag_pos[3]);
5497 }
5498 }
5499 ctx->shader_info->fs.num_interp = index;
5500 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5501 ctx->shader_info->fs.has_pcoord = true;
5502 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5503 ctx->shader_info->fs.prim_id_input = true;
5504 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5505 ctx->shader_info->fs.layer_input = true;
5506 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5507
5508 if (ctx->shader_info->info.needs_multiview_view_index)
5509 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5510 }
5511
5512 static LLVMValueRef
5513 ac_build_alloca(struct ac_llvm_context *ac,
5514 LLVMTypeRef type,
5515 const char *name)
5516 {
5517 LLVMBuilderRef builder = ac->builder;
5518 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5519 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5520 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5521 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5522 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5523 LLVMValueRef res;
5524
5525 if (first_instr) {
5526 LLVMPositionBuilderBefore(first_builder, first_instr);
5527 } else {
5528 LLVMPositionBuilderAtEnd(first_builder, first_block);
5529 }
5530
5531 res = LLVMBuildAlloca(first_builder, type, name);
5532 LLVMBuildStore(builder, LLVMConstNull(type), res);
5533
5534 LLVMDisposeBuilder(first_builder);
5535
5536 return res;
5537 }
5538
5539 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5540 LLVMTypeRef type,
5541 const char *name)
5542 {
5543 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5544 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5545 return ptr;
5546 }
5547
5548 static void
5549 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5550 struct nir_variable *variable,
5551 struct nir_shader *shader,
5552 gl_shader_stage stage)
5553 {
5554 int idx = variable->data.location + variable->data.index;
5555 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5556 uint64_t mask_attribs;
5557
5558 variable->data.driver_location = idx * 4;
5559
5560 /* tess ctrl has it's own load/store paths for outputs */
5561 if (stage == MESA_SHADER_TESS_CTRL)
5562 return;
5563
5564 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5565 if (stage == MESA_SHADER_VERTEX ||
5566 stage == MESA_SHADER_TESS_EVAL ||
5567 stage == MESA_SHADER_GEOMETRY) {
5568 if (idx == VARYING_SLOT_CLIP_DIST0) {
5569 int length = shader->info.clip_distance_array_size +
5570 shader->info.cull_distance_array_size;
5571 if (stage == MESA_SHADER_VERTEX) {
5572 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5573 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5574 }
5575 if (stage == MESA_SHADER_TESS_EVAL) {
5576 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5577 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5578 }
5579
5580 if (length > 4)
5581 attrib_count = 2;
5582 else
5583 attrib_count = 1;
5584 mask_attribs = 1ull << idx;
5585 }
5586 }
5587
5588 ctx->output_mask |= mask_attribs;
5589 }
5590
5591 static void
5592 handle_shader_output_decl(struct ac_nir_context *ctx,
5593 struct nir_shader *nir,
5594 struct nir_variable *variable)
5595 {
5596 unsigned output_loc = variable->data.driver_location / 4;
5597 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5598
5599 /* tess ctrl has it's own load/store paths for outputs */
5600 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5601 return;
5602
5603 if (ctx->stage == MESA_SHADER_VERTEX ||
5604 ctx->stage == MESA_SHADER_TESS_EVAL ||
5605 ctx->stage == MESA_SHADER_GEOMETRY) {
5606 int idx = variable->data.location + variable->data.index;
5607 if (idx == VARYING_SLOT_CLIP_DIST0) {
5608 int length = nir->info.clip_distance_array_size +
5609 nir->info.cull_distance_array_size;
5610
5611 if (length > 4)
5612 attrib_count = 2;
5613 else
5614 attrib_count = 1;
5615 }
5616 }
5617
5618 for (unsigned i = 0; i < attrib_count; ++i) {
5619 for (unsigned chan = 0; chan < 4; chan++) {
5620 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5621 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5622 }
5623 }
5624 }
5625
5626 static LLVMTypeRef
5627 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5628 enum glsl_base_type type)
5629 {
5630 switch (type) {
5631 case GLSL_TYPE_INT:
5632 case GLSL_TYPE_UINT:
5633 case GLSL_TYPE_BOOL:
5634 case GLSL_TYPE_SUBROUTINE:
5635 return ctx->ac.i32;
5636 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5637 return ctx->ac.f32;
5638 case GLSL_TYPE_INT64:
5639 case GLSL_TYPE_UINT64:
5640 return ctx->ac.i64;
5641 case GLSL_TYPE_DOUBLE:
5642 return ctx->ac.f64;
5643 default:
5644 unreachable("unknown GLSL type");
5645 }
5646 }
5647
5648 static LLVMTypeRef
5649 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5650 const struct glsl_type *type)
5651 {
5652 if (glsl_type_is_scalar(type)) {
5653 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5654 }
5655
5656 if (glsl_type_is_vector(type)) {
5657 return LLVMVectorType(
5658 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5659 glsl_get_vector_elements(type));
5660 }
5661
5662 if (glsl_type_is_matrix(type)) {
5663 return LLVMArrayType(
5664 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5665 glsl_get_matrix_columns(type));
5666 }
5667
5668 if (glsl_type_is_array(type)) {
5669 return LLVMArrayType(
5670 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5671 glsl_get_length(type));
5672 }
5673
5674 assert(glsl_type_is_struct(type));
5675
5676 LLVMTypeRef member_types[glsl_get_length(type)];
5677
5678 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5679 member_types[i] =
5680 glsl_to_llvm_type(ctx,
5681 glsl_get_struct_field(type, i));
5682 }
5683
5684 return LLVMStructTypeInContext(ctx->context, member_types,
5685 glsl_get_length(type), false);
5686 }
5687
5688 static void
5689 setup_locals(struct ac_nir_context *ctx,
5690 struct nir_function *func)
5691 {
5692 int i, j;
5693 ctx->num_locals = 0;
5694 nir_foreach_variable(variable, &func->impl->locals) {
5695 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5696 variable->data.driver_location = ctx->num_locals * 4;
5697 variable->data.location_frac = 0;
5698 ctx->num_locals += attrib_count;
5699 }
5700 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5701 if (!ctx->locals)
5702 return;
5703
5704 for (i = 0; i < ctx->num_locals; i++) {
5705 for (j = 0; j < 4; j++) {
5706 ctx->locals[i * 4 + j] =
5707 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5708 }
5709 }
5710 }
5711
5712 static void
5713 setup_shared(struct ac_nir_context *ctx,
5714 struct nir_shader *nir)
5715 {
5716 nir_foreach_variable(variable, &nir->shared) {
5717 LLVMValueRef shared =
5718 LLVMAddGlobalInAddressSpace(
5719 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5720 variable->name ? variable->name : "",
5721 LOCAL_ADDR_SPACE);
5722 _mesa_hash_table_insert(ctx->vars, variable, shared);
5723 }
5724 }
5725
5726 static LLVMValueRef
5727 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5728 {
5729 v = ac_to_float(ctx, v);
5730 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5731 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5732 }
5733
5734
5735 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5736 LLVMValueRef src0, LLVMValueRef src1)
5737 {
5738 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5739 LLVMValueRef comp[2];
5740
5741 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5742 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5743 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5744 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5745 }
5746
5747 /* Initialize arguments for the shader export intrinsic */
5748 static void
5749 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5750 LLVMValueRef *values,
5751 unsigned target,
5752 struct ac_export_args *args)
5753 {
5754 /* Default is 0xf. Adjusted below depending on the format. */
5755 args->enabled_channels = 0xf;
5756
5757 /* Specify whether the EXEC mask represents the valid mask */
5758 args->valid_mask = 0;
5759
5760 /* Specify whether this is the last export */
5761 args->done = 0;
5762
5763 /* Specify the target we are exporting */
5764 args->target = target;
5765
5766 args->compr = false;
5767 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5768 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5769 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5770 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5771
5772 if (!values)
5773 return;
5774
5775 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5776 LLVMValueRef val[4];
5777 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5778 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5779 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5780 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5781
5782 switch(col_format) {
5783 case V_028714_SPI_SHADER_ZERO:
5784 args->enabled_channels = 0; /* writemask */
5785 args->target = V_008DFC_SQ_EXP_NULL;
5786 break;
5787
5788 case V_028714_SPI_SHADER_32_R:
5789 args->enabled_channels = 1;
5790 args->out[0] = values[0];
5791 break;
5792
5793 case V_028714_SPI_SHADER_32_GR:
5794 args->enabled_channels = 0x3;
5795 args->out[0] = values[0];
5796 args->out[1] = values[1];
5797 break;
5798
5799 case V_028714_SPI_SHADER_32_AR:
5800 args->enabled_channels = 0x9;
5801 args->out[0] = values[0];
5802 args->out[3] = values[3];
5803 break;
5804
5805 case V_028714_SPI_SHADER_FP16_ABGR:
5806 args->compr = 1;
5807
5808 for (unsigned chan = 0; chan < 2; chan++) {
5809 LLVMValueRef pack_args[2] = {
5810 values[2 * chan],
5811 values[2 * chan + 1]
5812 };
5813 LLVMValueRef packed;
5814
5815 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5816 args->out[chan] = packed;
5817 }
5818 break;
5819
5820 case V_028714_SPI_SHADER_UNORM16_ABGR:
5821 for (unsigned chan = 0; chan < 4; chan++) {
5822 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5823 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5824 LLVMConstReal(ctx->ac.f32, 65535), "");
5825 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5826 LLVMConstReal(ctx->ac.f32, 0.5), "");
5827 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5828 ctx->ac.i32, "");
5829 }
5830
5831 args->compr = 1;
5832 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5833 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5834 break;
5835
5836 case V_028714_SPI_SHADER_SNORM16_ABGR:
5837 for (unsigned chan = 0; chan < 4; chan++) {
5838 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5839 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5840 LLVMConstReal(ctx->ac.f32, 32767), "");
5841
5842 /* If positive, add 0.5, else add -0.5. */
5843 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5844 LLVMBuildSelect(ctx->builder,
5845 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5846 val[chan], ctx->ac.f32_0, ""),
5847 LLVMConstReal(ctx->ac.f32, 0.5),
5848 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5849 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5850 }
5851
5852 args->compr = 1;
5853 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5854 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5855 break;
5856
5857 case V_028714_SPI_SHADER_UINT16_ABGR: {
5858 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5859 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5860 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5861
5862 for (unsigned chan = 0; chan < 4; chan++) {
5863 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5864 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5865 }
5866
5867 args->compr = 1;
5868 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5869 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5870 break;
5871 }
5872
5873 case V_028714_SPI_SHADER_SINT16_ABGR: {
5874 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5875 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5876 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5877 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5878 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5879 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5880
5881 /* Clamp. */
5882 for (unsigned chan = 0; chan < 4; chan++) {
5883 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5884 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5885 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5886 }
5887
5888 args->compr = 1;
5889 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5890 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5891 break;
5892 }
5893
5894 default:
5895 case V_028714_SPI_SHADER_32_ABGR:
5896 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5897 break;
5898 }
5899 } else
5900 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5901
5902 for (unsigned i = 0; i < 4; ++i)
5903 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5904 }
5905
5906 static void
5907 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5908 bool export_prim_id,
5909 struct ac_vs_output_info *outinfo)
5910 {
5911 uint32_t param_count = 0;
5912 unsigned target;
5913 unsigned pos_idx, num_pos_exports = 0;
5914 struct ac_export_args args, pos_args[4] = {};
5915 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5916 int i;
5917
5918 if (ctx->options->key.has_multiview_view_index) {
5919 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5920 if(!*tmp_out) {
5921 for(unsigned i = 0; i < 4; ++i)
5922 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5923 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5924 }
5925
5926 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5927 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5928 }
5929
5930 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5931 sizeof(outinfo->vs_output_param_offset));
5932
5933 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5934 LLVMValueRef slots[8];
5935 unsigned j;
5936
5937 if (outinfo->cull_dist_mask)
5938 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5939
5940 i = VARYING_SLOT_CLIP_DIST0;
5941 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5942 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5943 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5944
5945 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5946 slots[i] = LLVMGetUndef(ctx->ac.f32);
5947
5948 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5949 target = V_008DFC_SQ_EXP_POS + 3;
5950 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5951 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5952 &args, sizeof(args));
5953 }
5954
5955 target = V_008DFC_SQ_EXP_POS + 2;
5956 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5957 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5958 &args, sizeof(args));
5959
5960 }
5961
5962 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5963 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5964 for (unsigned j = 0; j < 4; j++)
5965 pos_values[j] = LLVMBuildLoad(ctx->builder,
5966 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5967 }
5968 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5969
5970 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5971 outinfo->writes_pointsize = true;
5972 psize_value = LLVMBuildLoad(ctx->builder,
5973 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5974 }
5975
5976 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5977 outinfo->writes_layer = true;
5978 layer_value = LLVMBuildLoad(ctx->builder,
5979 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5980 }
5981
5982 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5983 outinfo->writes_viewport_index = true;
5984 viewport_index_value = LLVMBuildLoad(ctx->builder,
5985 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5986 }
5987
5988 if (outinfo->writes_pointsize ||
5989 outinfo->writes_layer ||
5990 outinfo->writes_viewport_index) {
5991 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5992 (outinfo->writes_layer == true ? 4 : 0));
5993 pos_args[1].valid_mask = 0;
5994 pos_args[1].done = 0;
5995 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5996 pos_args[1].compr = 0;
5997 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5998 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5999 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6000 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6001
6002 if (outinfo->writes_pointsize == true)
6003 pos_args[1].out[0] = psize_value;
6004 if (outinfo->writes_layer == true)
6005 pos_args[1].out[2] = layer_value;
6006 if (outinfo->writes_viewport_index == true) {
6007 if (ctx->options->chip_class >= GFX9) {
6008 /* GFX9 has the layer in out.z[10:0] and the viewport
6009 * index in out.z[19:16].
6010 */
6011 LLVMValueRef v = viewport_index_value;
6012 v = ac_to_integer(&ctx->ac, v);
6013 v = LLVMBuildShl(ctx->builder, v,
6014 LLVMConstInt(ctx->ac.i32, 16, false),
6015 "");
6016 v = LLVMBuildOr(ctx->builder, v,
6017 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6018
6019 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6020 pos_args[1].enabled_channels |= 1 << 2;
6021 } else {
6022 pos_args[1].out[3] = viewport_index_value;
6023 pos_args[1].enabled_channels |= 1 << 3;
6024 }
6025 }
6026 }
6027 for (i = 0; i < 4; i++) {
6028 if (pos_args[i].out[0])
6029 num_pos_exports++;
6030 }
6031
6032 pos_idx = 0;
6033 for (i = 0; i < 4; i++) {
6034 if (!pos_args[i].out[0])
6035 continue;
6036
6037 /* Specify the target we are exporting */
6038 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6039 if (pos_idx == num_pos_exports)
6040 pos_args[i].done = 1;
6041 ac_build_export(&ctx->ac, &pos_args[i]);
6042 }
6043
6044 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6045 LLVMValueRef values[4];
6046 if (!(ctx->output_mask & (1ull << i)))
6047 continue;
6048
6049 for (unsigned j = 0; j < 4; j++)
6050 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6051 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6052
6053 if (i == VARYING_SLOT_LAYER) {
6054 target = V_008DFC_SQ_EXP_PARAM + param_count;
6055 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
6056 param_count++;
6057 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
6058 target = V_008DFC_SQ_EXP_PARAM + param_count;
6059 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6060 param_count++;
6061 } else if (i >= VARYING_SLOT_VAR0) {
6062 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
6063 target = V_008DFC_SQ_EXP_PARAM + param_count;
6064 outinfo->vs_output_param_offset[i] = param_count;
6065 param_count++;
6066 } else
6067 continue;
6068
6069 si_llvm_init_export_args(ctx, values, target, &args);
6070
6071 if (target >= V_008DFC_SQ_EXP_POS &&
6072 target <= (V_008DFC_SQ_EXP_POS + 3)) {
6073 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6074 &args, sizeof(args));
6075 } else {
6076 ac_build_export(&ctx->ac, &args);
6077 }
6078 }
6079
6080 if (export_prim_id) {
6081 LLVMValueRef values[4];
6082 target = V_008DFC_SQ_EXP_PARAM + param_count;
6083 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6084 param_count++;
6085
6086 values[0] = ctx->vs_prim_id;
6087 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6088 ctx->shader_info->vs.vgpr_comp_cnt);
6089 for (unsigned j = 1; j < 4; j++)
6090 values[j] = ctx->ac.f32_0;
6091 si_llvm_init_export_args(ctx, values, target, &args);
6092 ac_build_export(&ctx->ac, &args);
6093 outinfo->export_prim_id = true;
6094 }
6095
6096 outinfo->pos_exports = num_pos_exports;
6097 outinfo->param_exports = param_count;
6098 }
6099
6100 static void
6101 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6102 struct ac_es_output_info *outinfo)
6103 {
6104 int j;
6105 uint64_t max_output_written = 0;
6106 LLVMValueRef lds_base = NULL;
6107
6108 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6109 int param_index;
6110 int length = 4;
6111
6112 if (!(ctx->output_mask & (1ull << i)))
6113 continue;
6114
6115 if (i == VARYING_SLOT_CLIP_DIST0)
6116 length = ctx->num_output_clips + ctx->num_output_culls;
6117
6118 param_index = shader_io_get_unique_index(i);
6119
6120 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6121 }
6122
6123 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6124
6125 if (ctx->ac.chip_class >= GFX9) {
6126 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6127 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6128 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6129 LLVMConstInt(ctx->ac.i32, 24, false),
6130 LLVMConstInt(ctx->ac.i32, 4, false), false);
6131 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6132 LLVMBuildMul(ctx->ac.builder, wave_idx,
6133 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6134 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6135 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6136 }
6137
6138 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6139 LLVMValueRef dw_addr;
6140 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6141 int param_index;
6142 int length = 4;
6143
6144 if (!(ctx->output_mask & (1ull << i)))
6145 continue;
6146
6147 if (i == VARYING_SLOT_CLIP_DIST0)
6148 length = ctx->num_output_clips + ctx->num_output_culls;
6149
6150 param_index = shader_io_get_unique_index(i);
6151
6152 if (lds_base) {
6153 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6154 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6155 "");
6156 }
6157 for (j = 0; j < length; j++) {
6158 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6159 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6160
6161 if (ctx->ac.chip_class >= GFX9) {
6162 ac_lds_store(&ctx->ac, dw_addr,
6163 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6164 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6165 } else {
6166 ac_build_buffer_store_dword(&ctx->ac,
6167 ctx->esgs_ring,
6168 out_val, 1,
6169 NULL, ctx->es2gs_offset,
6170 (4 * param_index + j) * 4,
6171 1, 1, true, true);
6172 }
6173 }
6174 }
6175 }
6176
6177 static void
6178 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6179 {
6180 LLVMValueRef vertex_id = ctx->rel_auto_id;
6181 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6182 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6183 vertex_dw_stride, "");
6184
6185 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6186 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6187 int length = 4;
6188
6189 if (!(ctx->output_mask & (1ull << i)))
6190 continue;
6191
6192 if (i == VARYING_SLOT_CLIP_DIST0)
6193 length = ctx->num_output_clips + ctx->num_output_culls;
6194 int param = shader_io_get_unique_index(i);
6195 mark_tess_output(ctx, false, param);
6196 if (length > 4)
6197 mark_tess_output(ctx, false, param + 1);
6198 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6199 LLVMConstInt(ctx->ac.i32, param * 4, false),
6200 "");
6201 for (unsigned j = 0; j < length; j++) {
6202 ac_lds_store(&ctx->ac, dw_addr,
6203 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6204 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6205 }
6206 }
6207 }
6208
6209 struct ac_build_if_state
6210 {
6211 struct nir_to_llvm_context *ctx;
6212 LLVMValueRef condition;
6213 LLVMBasicBlockRef entry_block;
6214 LLVMBasicBlockRef true_block;
6215 LLVMBasicBlockRef false_block;
6216 LLVMBasicBlockRef merge_block;
6217 };
6218
6219 static LLVMBasicBlockRef
6220 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6221 {
6222 LLVMBasicBlockRef current_block;
6223 LLVMBasicBlockRef next_block;
6224 LLVMBasicBlockRef new_block;
6225
6226 /* get current basic block */
6227 current_block = LLVMGetInsertBlock(ctx->builder);
6228
6229 /* chqeck if there's another block after this one */
6230 next_block = LLVMGetNextBasicBlock(current_block);
6231 if (next_block) {
6232 /* insert the new block before the next block */
6233 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6234 }
6235 else {
6236 /* append new block after current block */
6237 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6238 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6239 }
6240 return new_block;
6241 }
6242
6243 static void
6244 ac_nir_build_if(struct ac_build_if_state *ifthen,
6245 struct nir_to_llvm_context *ctx,
6246 LLVMValueRef condition)
6247 {
6248 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6249
6250 memset(ifthen, 0, sizeof *ifthen);
6251 ifthen->ctx = ctx;
6252 ifthen->condition = condition;
6253 ifthen->entry_block = block;
6254
6255 /* create endif/merge basic block for the phi functions */
6256 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6257
6258 /* create/insert true_block before merge_block */
6259 ifthen->true_block =
6260 LLVMInsertBasicBlockInContext(ctx->context,
6261 ifthen->merge_block,
6262 "if-true-block");
6263
6264 /* successive code goes into the true block */
6265 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6266 }
6267
6268 /**
6269 * End a conditional.
6270 */
6271 static void
6272 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6273 {
6274 LLVMBuilderRef builder = ifthen->ctx->builder;
6275
6276 /* Insert branch to the merge block from current block */
6277 LLVMBuildBr(builder, ifthen->merge_block);
6278
6279 /*
6280 * Now patch in the various branch instructions.
6281 */
6282
6283 /* Insert the conditional branch instruction at the end of entry_block */
6284 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6285 if (ifthen->false_block) {
6286 /* we have an else clause */
6287 LLVMBuildCondBr(builder, ifthen->condition,
6288 ifthen->true_block, ifthen->false_block);
6289 }
6290 else {
6291 /* no else clause */
6292 LLVMBuildCondBr(builder, ifthen->condition,
6293 ifthen->true_block, ifthen->merge_block);
6294 }
6295
6296 /* Resume building code at end of the ifthen->merge_block */
6297 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6298 }
6299
6300 static void
6301 write_tess_factors(struct nir_to_llvm_context *ctx)
6302 {
6303 unsigned stride, outer_comps, inner_comps;
6304 struct ac_build_if_state if_ctx, inner_if_ctx;
6305 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6306 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6307 unsigned tess_inner_index, tess_outer_index;
6308 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6309 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6310 int i;
6311 emit_barrier(&ctx->ac, ctx->stage);
6312
6313 switch (ctx->options->key.tcs.primitive_mode) {
6314 case GL_ISOLINES:
6315 stride = 2;
6316 outer_comps = 2;
6317 inner_comps = 0;
6318 break;
6319 case GL_TRIANGLES:
6320 stride = 4;
6321 outer_comps = 3;
6322 inner_comps = 1;
6323 break;
6324 case GL_QUADS:
6325 stride = 6;
6326 outer_comps = 4;
6327 inner_comps = 2;
6328 break;
6329 default:
6330 return;
6331 }
6332
6333 ac_nir_build_if(&if_ctx, ctx,
6334 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6335 invocation_id, ctx->ac.i32_0, ""));
6336
6337 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6338 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6339
6340 mark_tess_output(ctx, true, tess_inner_index);
6341 mark_tess_output(ctx, true, tess_outer_index);
6342 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6343 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6344 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6345 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6346 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6347
6348 for (i = 0; i < 4; i++) {
6349 inner[i] = LLVMGetUndef(ctx->ac.i32);
6350 outer[i] = LLVMGetUndef(ctx->ac.i32);
6351 }
6352
6353 // LINES reverseal
6354 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6355 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6356 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6357 ctx->ac.i32_1, "");
6358 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6359 } else {
6360 for (i = 0; i < outer_comps; i++) {
6361 outer[i] = out[i] =
6362 ac_lds_load(&ctx->ac, lds_outer);
6363 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6364 ctx->ac.i32_1, "");
6365 }
6366 for (i = 0; i < inner_comps; i++) {
6367 inner[i] = out[outer_comps+i] =
6368 ac_lds_load(&ctx->ac, lds_inner);
6369 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6370 ctx->ac.i32_1, "");
6371 }
6372 }
6373
6374 /* Convert the outputs to vectors for stores. */
6375 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6376 vec1 = NULL;
6377
6378 if (stride > 4)
6379 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6380
6381
6382 buffer = ctx->hs_ring_tess_factor;
6383 tf_base = ctx->tess_factor_offset;
6384 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6385 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6386 unsigned tf_offset = 0;
6387
6388 if (ctx->options->chip_class <= VI) {
6389 ac_nir_build_if(&inner_if_ctx, ctx,
6390 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6391 rel_patch_id, ctx->ac.i32_0, ""));
6392
6393 /* Store the dynamic HS control word. */
6394 ac_build_buffer_store_dword(&ctx->ac, buffer,
6395 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6396 1, ctx->ac.i32_0, tf_base,
6397 0, 1, 0, true, false);
6398 tf_offset += 4;
6399
6400 ac_nir_build_endif(&inner_if_ctx);
6401 }
6402
6403 /* Store the tessellation factors. */
6404 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6405 MIN2(stride, 4), byteoffset, tf_base,
6406 tf_offset, 1, 0, true, false);
6407 if (vec1)
6408 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6409 stride - 4, byteoffset, tf_base,
6410 16 + tf_offset, 1, 0, true, false);
6411
6412 //store to offchip for TES to read - only if TES reads them
6413 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6414 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6415 LLVMValueRef tf_inner_offset;
6416 unsigned param_outer, param_inner;
6417
6418 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6419 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6420 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6421
6422 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6423 util_next_power_of_two(outer_comps));
6424
6425 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6426 outer_comps, tf_outer_offset,
6427 ctx->oc_lds, 0, 1, 0, true, false);
6428 if (inner_comps) {
6429 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6430 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6431 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6432
6433 inner_vec = inner_comps == 1 ? inner[0] :
6434 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6435 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6436 inner_comps, tf_inner_offset,
6437 ctx->oc_lds, 0, 1, 0, true, false);
6438 }
6439 }
6440 ac_nir_build_endif(&if_ctx);
6441 }
6442
6443 static void
6444 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6445 {
6446 write_tess_factors(ctx);
6447 }
6448
6449 static bool
6450 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6451 LLVMValueRef *color, unsigned param, bool is_last,
6452 struct ac_export_args *args)
6453 {
6454 /* Export */
6455 si_llvm_init_export_args(ctx, color, param,
6456 args);
6457
6458 if (is_last) {
6459 args->valid_mask = 1; /* whether the EXEC mask is valid */
6460 args->done = 1; /* DONE bit */
6461 } else if (!args->enabled_channels)
6462 return false; /* unnecessary NULL export */
6463
6464 return true;
6465 }
6466
6467 static void
6468 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6469 LLVMValueRef depth, LLVMValueRef stencil,
6470 LLVMValueRef samplemask)
6471 {
6472 struct ac_export_args args;
6473
6474 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6475
6476 ac_build_export(&ctx->ac, &args);
6477 }
6478
6479 static void
6480 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6481 {
6482 unsigned index = 0;
6483 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6484 struct ac_export_args color_args[8];
6485
6486 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6487 LLVMValueRef values[4];
6488
6489 if (!(ctx->output_mask & (1ull << i)))
6490 continue;
6491
6492 if (i == FRAG_RESULT_DEPTH) {
6493 ctx->shader_info->fs.writes_z = true;
6494 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6495 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6496 } else if (i == FRAG_RESULT_STENCIL) {
6497 ctx->shader_info->fs.writes_stencil = true;
6498 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6499 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6500 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6501 ctx->shader_info->fs.writes_sample_mask = true;
6502 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6503 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6504 } else {
6505 bool last = false;
6506 for (unsigned j = 0; j < 4; j++)
6507 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6508 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6509
6510 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6511 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6512
6513 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6514 if (ret)
6515 index++;
6516 }
6517 }
6518
6519 for (unsigned i = 0; i < index; i++)
6520 ac_build_export(&ctx->ac, &color_args[i]);
6521 if (depth || stencil || samplemask)
6522 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6523 else if (!index) {
6524 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6525 ac_build_export(&ctx->ac, &color_args[0]);
6526 }
6527 }
6528
6529 static void
6530 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6531 {
6532 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6533 }
6534
6535 static void
6536 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6537 LLVMValueRef *addrs)
6538 {
6539 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6540
6541 switch (ctx->stage) {
6542 case MESA_SHADER_VERTEX:
6543 if (ctx->options->key.vs.as_ls)
6544 handle_ls_outputs_post(ctx);
6545 else if (ctx->options->key.vs.as_es)
6546 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6547 else
6548 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6549 &ctx->shader_info->vs.outinfo);
6550 break;
6551 case MESA_SHADER_FRAGMENT:
6552 handle_fs_outputs_post(ctx);
6553 break;
6554 case MESA_SHADER_GEOMETRY:
6555 emit_gs_epilogue(ctx);
6556 break;
6557 case MESA_SHADER_TESS_CTRL:
6558 handle_tcs_outputs_post(ctx);
6559 break;
6560 case MESA_SHADER_TESS_EVAL:
6561 if (ctx->options->key.tes.as_es)
6562 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6563 else
6564 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6565 &ctx->shader_info->tes.outinfo);
6566 break;
6567 default:
6568 break;
6569 }
6570 }
6571
6572 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6573 {
6574 LLVMPassManagerRef passmgr;
6575 /* Create the pass manager */
6576 passmgr = LLVMCreateFunctionPassManagerForModule(
6577 ctx->module);
6578
6579 /* This pass should eliminate all the load and store instructions */
6580 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6581
6582 /* Add some optimization passes */
6583 LLVMAddScalarReplAggregatesPass(passmgr);
6584 LLVMAddLICMPass(passmgr);
6585 LLVMAddAggressiveDCEPass(passmgr);
6586 LLVMAddCFGSimplificationPass(passmgr);
6587 LLVMAddInstructionCombiningPass(passmgr);
6588
6589 /* Run the pass */
6590 LLVMInitializeFunctionPassManager(passmgr);
6591 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6592 LLVMFinalizeFunctionPassManager(passmgr);
6593
6594 LLVMDisposeBuilder(ctx->builder);
6595 LLVMDisposePassManager(passmgr);
6596 }
6597
6598 static void
6599 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6600 {
6601 struct ac_vs_output_info *outinfo;
6602
6603 switch (ctx->stage) {
6604 case MESA_SHADER_FRAGMENT:
6605 case MESA_SHADER_COMPUTE:
6606 case MESA_SHADER_TESS_CTRL:
6607 case MESA_SHADER_GEOMETRY:
6608 return;
6609 case MESA_SHADER_VERTEX:
6610 if (ctx->options->key.vs.as_ls ||
6611 ctx->options->key.vs.as_es)
6612 return;
6613 outinfo = &ctx->shader_info->vs.outinfo;
6614 break;
6615 case MESA_SHADER_TESS_EVAL:
6616 if (ctx->options->key.vs.as_es)
6617 return;
6618 outinfo = &ctx->shader_info->tes.outinfo;
6619 break;
6620 default:
6621 unreachable("Unhandled shader type");
6622 }
6623
6624 ac_optimize_vs_outputs(&ctx->ac,
6625 ctx->main_function,
6626 outinfo->vs_output_param_offset,
6627 VARYING_SLOT_MAX,
6628 &outinfo->param_exports);
6629 }
6630
6631 static void
6632 ac_setup_rings(struct nir_to_llvm_context *ctx)
6633 {
6634 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6635 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6636 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6637 }
6638
6639 if (ctx->is_gs_copy_shader) {
6640 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6641 }
6642 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6643 LLVMValueRef tmp;
6644 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6645 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6646
6647 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6648
6649 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6650 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6651 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6652 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6653 }
6654
6655 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6656 ctx->stage == MESA_SHADER_TESS_EVAL) {
6657 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6658 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6659 }
6660 }
6661
6662 static unsigned
6663 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6664 const struct nir_shader *nir)
6665 {
6666 switch (nir->info.stage) {
6667 case MESA_SHADER_TESS_CTRL:
6668 return chip_class >= CIK ? 128 : 64;
6669 case MESA_SHADER_GEOMETRY:
6670 return chip_class >= GFX9 ? 128 : 64;
6671 case MESA_SHADER_COMPUTE:
6672 break;
6673 default:
6674 return 0;
6675 }
6676
6677 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6678 nir->info.cs.local_size[1] *
6679 nir->info.cs.local_size[2];
6680 return max_workgroup_size;
6681 }
6682
6683 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6684 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6685 {
6686 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6687 LLVMConstInt(ctx->ac.i32, 8, false),
6688 LLVMConstInt(ctx->ac.i32, 8, false), false);
6689 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6690 ctx->ac.i32_0, "");
6691 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6692 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6693 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6694 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6695 }
6696
6697 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6698 {
6699 for(int i = 5; i >= 0; --i) {
6700 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6701 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6702 LLVMConstInt(ctx->ac.i32, 16, false), false);
6703 }
6704
6705 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6706 LLVMConstInt(ctx->ac.i32, 16, false),
6707 LLVMConstInt(ctx->ac.i32, 8, false), false);
6708 }
6709
6710 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6711 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6712 {
6713 struct ac_nir_context ctx = {};
6714 struct nir_function *func;
6715
6716 ctx.ac = *ac;
6717 ctx.abi = abi;
6718
6719 ctx.nctx = nctx;
6720 if (nctx)
6721 nctx->nir = &ctx;
6722
6723 ctx.stage = nir->info.stage;
6724
6725 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6726
6727 nir_foreach_variable(variable, &nir->outputs)
6728 handle_shader_output_decl(&ctx, nir, variable);
6729
6730 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6731 _mesa_key_pointer_equal);
6732 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6733 _mesa_key_pointer_equal);
6734 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6735 _mesa_key_pointer_equal);
6736
6737 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6738
6739 setup_locals(&ctx, func);
6740
6741 if (nir->info.stage == MESA_SHADER_COMPUTE)
6742 setup_shared(&ctx, nir);
6743
6744 visit_cf_list(&ctx, &func->impl->body);
6745 phi_post_pass(&ctx);
6746
6747 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6748 ctx.outputs);
6749
6750 free(ctx.locals);
6751 ralloc_free(ctx.defs);
6752 ralloc_free(ctx.phis);
6753 ralloc_free(ctx.vars);
6754
6755 if (nctx)
6756 nctx->nir = NULL;
6757 }
6758
6759 static
6760 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6761 struct nir_shader *const *shaders,
6762 int shader_count,
6763 struct ac_shader_variant_info *shader_info,
6764 const struct ac_nir_compiler_options *options)
6765 {
6766 struct nir_to_llvm_context ctx = {0};
6767 unsigned i;
6768 ctx.options = options;
6769 ctx.shader_info = shader_info;
6770 ctx.context = LLVMContextCreate();
6771 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6772
6773 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6774 options->family);
6775 ctx.ac.module = ctx.module;
6776 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6777
6778 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6779 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6780 LLVMSetDataLayout(ctx.module, data_layout_str);
6781 LLVMDisposeTargetData(data_layout);
6782 LLVMDisposeMessage(data_layout_str);
6783
6784 enum ac_float_mode float_mode =
6785 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6786 AC_FLOAT_MODE_DEFAULT;
6787
6788 ctx.builder = ac_create_builder(ctx.context, float_mode);
6789 ctx.ac.builder = ctx.builder;
6790
6791 memset(shader_info, 0, sizeof(*shader_info));
6792
6793 for(int i = 0; i < shader_count; ++i)
6794 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6795
6796 for (i = 0; i < AC_UD_MAX_SETS; i++)
6797 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6798 for (i = 0; i < AC_UD_MAX_UD; i++)
6799 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6800
6801 ctx.max_workgroup_size = 0;
6802 for (int i = 0; i < shader_count; ++i) {
6803 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6804 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6805 shaders[i]));
6806 }
6807
6808 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6809 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6810
6811 ctx.abi.inputs = &ctx.inputs[0];
6812 ctx.abi.emit_outputs = handle_shader_outputs_post;
6813 ctx.abi.emit_vertex = visit_emit_vertex;
6814 ctx.abi.load_ubo = radv_load_ubo;
6815 ctx.abi.load_ssbo = radv_load_ssbo;
6816 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6817 ctx.abi.clamp_shadow_reference = false;
6818
6819 if (shader_count >= 2)
6820 ac_init_exec_full_mask(&ctx.ac);
6821
6822 if (ctx.ac.chip_class == GFX9 &&
6823 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6824 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6825
6826 for(int i = 0; i < shader_count; ++i) {
6827 ctx.stage = shaders[i]->info.stage;
6828 ctx.output_mask = 0;
6829 ctx.tess_outputs_written = 0;
6830 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6831 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6832
6833 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6834 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6835 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6836 ctx.abi.load_inputs = load_gs_input;
6837 ctx.abi.emit_primitive = visit_end_primitive;
6838 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6839 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6840 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6841 ctx.abi.load_tess_varyings = load_tcs_varyings;
6842 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6843 ctx.abi.store_tcs_outputs = store_tcs_output;
6844 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6845 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6846 ctx.abi.load_tess_varyings = load_tes_input;
6847 ctx.abi.load_tess_coord = load_tess_coord;
6848 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6849 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6850 if (shader_info->info.vs.needs_instance_id) {
6851 if (ctx.options->key.vs.as_ls) {
6852 ctx.shader_info->vs.vgpr_comp_cnt =
6853 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6854 } else {
6855 ctx.shader_info->vs.vgpr_comp_cnt =
6856 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6857 }
6858 }
6859 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6860 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6861 }
6862
6863 if (i)
6864 emit_barrier(&ctx.ac, ctx.stage);
6865
6866 ac_setup_rings(&ctx);
6867
6868 LLVMBasicBlockRef merge_block;
6869 if (shader_count >= 2) {
6870 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6871 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6872 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6873
6874 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6875 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6876 LLVMConstInt(ctx.ac.i32, 8, false), false);
6877 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6878 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6879 thread_id, count, "");
6880 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6881
6882 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6883 }
6884
6885 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6886 handle_fs_inputs(&ctx, shaders[i]);
6887 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6888 handle_vs_inputs(&ctx, shaders[i]);
6889 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6890 prepare_gs_input_vgprs(&ctx);
6891
6892 nir_foreach_variable(variable, &shaders[i]->outputs)
6893 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6894
6895 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6896
6897 if (shader_count >= 2) {
6898 LLVMBuildBr(ctx.ac.builder, merge_block);
6899 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6900 }
6901
6902 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6903 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6904 shaders[i]->info.cull_distance_array_size > 4;
6905 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6906 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6907 shaders[i]->info.gs.vertices_out;
6908 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6909 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6910 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6911 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6912 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6913 }
6914 }
6915
6916 LLVMBuildRetVoid(ctx.builder);
6917
6918 if (options->dump_preoptir)
6919 ac_dump_module(ctx.module);
6920
6921 ac_llvm_finalize_module(&ctx);
6922
6923 if (shader_count == 1)
6924 ac_nir_eliminate_const_vs_outputs(&ctx);
6925
6926 return ctx.module;
6927 }
6928
6929 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6930 {
6931 unsigned *retval = (unsigned *)context;
6932 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6933 char *description = LLVMGetDiagInfoDescription(di);
6934
6935 if (severity == LLVMDSError) {
6936 *retval = 1;
6937 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6938 description);
6939 }
6940
6941 LLVMDisposeMessage(description);
6942 }
6943
6944 static unsigned ac_llvm_compile(LLVMModuleRef M,
6945 struct ac_shader_binary *binary,
6946 LLVMTargetMachineRef tm)
6947 {
6948 unsigned retval = 0;
6949 char *err;
6950 LLVMContextRef llvm_ctx;
6951 LLVMMemoryBufferRef out_buffer;
6952 unsigned buffer_size;
6953 const char *buffer_data;
6954 LLVMBool mem_err;
6955
6956 /* Setup Diagnostic Handler*/
6957 llvm_ctx = LLVMGetModuleContext(M);
6958
6959 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6960 &retval);
6961
6962 /* Compile IR*/
6963 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6964 &err, &out_buffer);
6965
6966 /* Process Errors/Warnings */
6967 if (mem_err) {
6968 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6969 free(err);
6970 retval = 1;
6971 goto out;
6972 }
6973
6974 /* Extract Shader Code*/
6975 buffer_size = LLVMGetBufferSize(out_buffer);
6976 buffer_data = LLVMGetBufferStart(out_buffer);
6977
6978 ac_elf_read(buffer_data, buffer_size, binary);
6979
6980 /* Clean up */
6981 LLVMDisposeMemoryBuffer(out_buffer);
6982
6983 out:
6984 return retval;
6985 }
6986
6987 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6988 LLVMModuleRef llvm_module,
6989 struct ac_shader_binary *binary,
6990 struct ac_shader_config *config,
6991 struct ac_shader_variant_info *shader_info,
6992 gl_shader_stage stage,
6993 bool dump_shader, bool supports_spill)
6994 {
6995 if (dump_shader)
6996 ac_dump_module(llvm_module);
6997
6998 memset(binary, 0, sizeof(*binary));
6999 int v = ac_llvm_compile(llvm_module, binary, tm);
7000 if (v) {
7001 fprintf(stderr, "compile failed\n");
7002 }
7003
7004 if (dump_shader)
7005 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7006
7007 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7008
7009 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7010 LLVMDisposeModule(llvm_module);
7011 LLVMContextDispose(ctx);
7012
7013 if (stage == MESA_SHADER_FRAGMENT) {
7014 shader_info->num_input_vgprs = 0;
7015 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7016 shader_info->num_input_vgprs += 2;
7017 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7018 shader_info->num_input_vgprs += 2;
7019 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7020 shader_info->num_input_vgprs += 2;
7021 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7022 shader_info->num_input_vgprs += 3;
7023 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7024 shader_info->num_input_vgprs += 2;
7025 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7026 shader_info->num_input_vgprs += 2;
7027 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7028 shader_info->num_input_vgprs += 2;
7029 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7030 shader_info->num_input_vgprs += 1;
7031 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7032 shader_info->num_input_vgprs += 1;
7033 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7034 shader_info->num_input_vgprs += 1;
7035 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7036 shader_info->num_input_vgprs += 1;
7037 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7038 shader_info->num_input_vgprs += 1;
7039 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7040 shader_info->num_input_vgprs += 1;
7041 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7042 shader_info->num_input_vgprs += 1;
7043 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7044 shader_info->num_input_vgprs += 1;
7045 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7046 shader_info->num_input_vgprs += 1;
7047 }
7048 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7049
7050 /* +3 for scratch wave offset and VCC */
7051 config->num_sgprs = MAX2(config->num_sgprs,
7052 shader_info->num_input_sgprs + 3);
7053
7054 /* Enable 64-bit and 16-bit denormals, because there is no performance
7055 * cost.
7056 *
7057 * If denormals are enabled, all floating-point output modifiers are
7058 * ignored.
7059 *
7060 * Don't enable denormals for 32-bit floats, because:
7061 * - Floating-point output modifiers would be ignored by the hw.
7062 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7063 * have to stop using those.
7064 * - SI & CI would be very slow.
7065 */
7066 config->float_mode |= V_00B028_FP_64_DENORMS;
7067 }
7068
7069 static void
7070 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7071 {
7072 switch (nir->info.stage) {
7073 case MESA_SHADER_COMPUTE:
7074 for (int i = 0; i < 3; ++i)
7075 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7076 break;
7077 case MESA_SHADER_FRAGMENT:
7078 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7079 break;
7080 case MESA_SHADER_GEOMETRY:
7081 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7082 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7083 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7084 shader_info->gs.invocations = nir->info.gs.invocations;
7085 break;
7086 case MESA_SHADER_TESS_EVAL:
7087 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7088 shader_info->tes.spacing = nir->info.tess.spacing;
7089 shader_info->tes.ccw = nir->info.tess.ccw;
7090 shader_info->tes.point_mode = nir->info.tess.point_mode;
7091 shader_info->tes.as_es = options->key.tes.as_es;
7092 break;
7093 case MESA_SHADER_TESS_CTRL:
7094 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7095 break;
7096 case MESA_SHADER_VERTEX:
7097 shader_info->vs.as_es = options->key.vs.as_es;
7098 shader_info->vs.as_ls = options->key.vs.as_ls;
7099 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7100 if (options->key.vs.as_ls)
7101 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7102 break;
7103 default:
7104 break;
7105 }
7106 }
7107
7108 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7109 struct ac_shader_binary *binary,
7110 struct ac_shader_config *config,
7111 struct ac_shader_variant_info *shader_info,
7112 struct nir_shader *const *nir,
7113 int nir_count,
7114 const struct ac_nir_compiler_options *options,
7115 bool dump_shader)
7116 {
7117
7118 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7119 options);
7120
7121 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7122 for (int i = 0; i < nir_count; ++i)
7123 ac_fill_shader_info(shader_info, nir[i], options);
7124
7125 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7126 if (options->chip_class == GFX9) {
7127 if (nir_count == 2 &&
7128 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7129 shader_info->gs.es_type = nir[0]->info.stage;
7130 }
7131 }
7132 }
7133
7134 static void
7135 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7136 {
7137 LLVMValueRef args[9];
7138 args[0] = ctx->gsvs_ring;
7139 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7140 args[3] = ctx->ac.i32_0;
7141 args[4] = ctx->ac.i32_1; /* OFFEN */
7142 args[5] = ctx->ac.i32_0; /* IDXEN */
7143 args[6] = ctx->ac.i32_1; /* GLC */
7144 args[7] = ctx->ac.i32_1; /* SLC */
7145 args[8] = ctx->ac.i32_0; /* TFE */
7146
7147 int idx = 0;
7148
7149 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7150 int length = 4;
7151 int slot = idx;
7152 int slot_inc = 1;
7153 if (!(ctx->output_mask & (1ull << i)))
7154 continue;
7155
7156 if (i == VARYING_SLOT_CLIP_DIST0) {
7157 /* unpack clip and cull from a single set of slots */
7158 length = ctx->num_output_clips + ctx->num_output_culls;
7159 if (length > 4)
7160 slot_inc = 2;
7161 }
7162
7163 for (unsigned j = 0; j < length; j++) {
7164 LLVMValueRef value;
7165 args[2] = LLVMConstInt(ctx->ac.i32,
7166 (slot * 4 + j) *
7167 ctx->gs_max_out_vertices * 16 * 4, false);
7168
7169 value = ac_build_intrinsic(&ctx->ac,
7170 "llvm.SI.buffer.load.dword.i32.i32",
7171 ctx->ac.i32, args, 9,
7172 AC_FUNC_ATTR_READONLY |
7173 AC_FUNC_ATTR_LEGACY);
7174
7175 LLVMBuildStore(ctx->builder,
7176 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7177 }
7178 idx += slot_inc;
7179 }
7180 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7181 }
7182
7183 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7184 struct nir_shader *geom_shader,
7185 struct ac_shader_binary *binary,
7186 struct ac_shader_config *config,
7187 struct ac_shader_variant_info *shader_info,
7188 const struct ac_nir_compiler_options *options,
7189 bool dump_shader)
7190 {
7191 struct nir_to_llvm_context ctx = {0};
7192 ctx.context = LLVMContextCreate();
7193 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7194 ctx.options = options;
7195 ctx.shader_info = shader_info;
7196
7197 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7198 options->family);
7199 ctx.ac.module = ctx.module;
7200
7201 ctx.is_gs_copy_shader = true;
7202 LLVMSetTarget(ctx.module, "amdgcn--");
7203
7204 enum ac_float_mode float_mode =
7205 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7206 AC_FLOAT_MODE_DEFAULT;
7207
7208 ctx.builder = ac_create_builder(ctx.context, float_mode);
7209 ctx.ac.builder = ctx.builder;
7210 ctx.stage = MESA_SHADER_VERTEX;
7211
7212 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7213
7214 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7215 ac_setup_rings(&ctx);
7216
7217 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7218 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7219
7220 struct ac_nir_context nir_ctx = {};
7221 nir_ctx.ac = ctx.ac;
7222 nir_ctx.abi = &ctx.abi;
7223
7224 nir_ctx.nctx = &ctx;
7225 ctx.nir = &nir_ctx;
7226
7227 nir_foreach_variable(variable, &geom_shader->outputs) {
7228 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7229 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7230 }
7231
7232 ac_gs_copy_shader_emit(&ctx);
7233
7234 ctx.nir = NULL;
7235
7236 LLVMBuildRetVoid(ctx.builder);
7237
7238 ac_llvm_finalize_module(&ctx);
7239
7240 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7241 MESA_SHADER_VERTEX,
7242 dump_shader, options->supports_spill);
7243 }