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ac/nir: fix a crash in load_gs_input() on pre-GFX9 chips
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 struct hash_table *defs;
87 struct hash_table *phis;
88
89 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
90 LLVMValueRef ring_offsets;
91 LLVMValueRef push_constants;
92 LLVMValueRef view_index;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids[3];
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef merged_wave_info;
110 LLVMValueRef tess_factor_offset;
111 LLVMValueRef tes_rel_patch_id;
112 LLVMValueRef tes_u;
113 LLVMValueRef tes_v;
114
115 LLVMValueRef gsvs_ring_stride;
116 LLVMValueRef gsvs_num_entries;
117 LLVMValueRef gs2vs_offset;
118 LLVMValueRef gs_wave_id;
119 LLVMValueRef gs_vtx_offset[6];
120
121 LLVMValueRef esgs_ring;
122 LLVMValueRef gsvs_ring;
123 LLVMValueRef hs_ring_tess_offchip;
124 LLVMValueRef hs_ring_tess_factor;
125
126 LLVMValueRef sample_pos_offset;
127 LLVMValueRef persp_sample, persp_center, persp_centroid;
128 LLVMValueRef linear_sample, linear_center, linear_centroid;
129
130 gl_shader_stage stage;
131
132 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
133
134 uint64_t input_mask;
135 uint64_t output_mask;
136 uint8_t num_output_clips;
137 uint8_t num_output_culls;
138
139 bool is_gs_copy_shader;
140 LLVMValueRef gs_next_vertex;
141 unsigned gs_max_out_vertices;
142
143 unsigned tes_primitive_mode;
144 uint64_t tess_outputs_written;
145 uint64_t tess_patch_outputs_written;
146
147 uint32_t tcs_patch_outputs_read;
148 uint64_t tcs_outputs_read;
149 };
150
151 static inline struct nir_to_llvm_context *
152 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
153 {
154 struct nir_to_llvm_context *ctx = NULL;
155 return container_of(abi, ctx, abi);
156 }
157
158 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
159 const nir_deref_var *deref,
160 enum ac_descriptor_type desc_type,
161 const nir_tex_instr *instr,
162 bool image, bool write);
163
164 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
165 {
166 return (index * 4) + chan;
167 }
168
169 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
170 {
171 /* handle patch indices separate */
172 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
173 return 0;
174 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
175 return 1;
176 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
177 return 2 + (slot - VARYING_SLOT_PATCH0);
178
179 if (slot == VARYING_SLOT_POS)
180 return 0;
181 if (slot == VARYING_SLOT_PSIZ)
182 return 1;
183 if (slot == VARYING_SLOT_CLIP_DIST0)
184 return 2;
185 /* 3 is reserved for clip dist as well */
186 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
187 return 4 + (slot - VARYING_SLOT_VAR0);
188 unreachable("illegal slot in get unique index\n");
189 }
190
191 static void set_llvm_calling_convention(LLVMValueRef func,
192 gl_shader_stage stage)
193 {
194 enum radeon_llvm_calling_convention calling_conv;
195
196 switch (stage) {
197 case MESA_SHADER_VERTEX:
198 case MESA_SHADER_TESS_EVAL:
199 calling_conv = RADEON_LLVM_AMDGPU_VS;
200 break;
201 case MESA_SHADER_GEOMETRY:
202 calling_conv = RADEON_LLVM_AMDGPU_GS;
203 break;
204 case MESA_SHADER_TESS_CTRL:
205 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
206 break;
207 case MESA_SHADER_FRAGMENT:
208 calling_conv = RADEON_LLVM_AMDGPU_PS;
209 break;
210 case MESA_SHADER_COMPUTE:
211 calling_conv = RADEON_LLVM_AMDGPU_CS;
212 break;
213 default:
214 unreachable("Unhandle shader type");
215 }
216
217 LLVMSetFunctionCallConv(func, calling_conv);
218 }
219
220 #define MAX_ARGS 23
221 struct arg_info {
222 LLVMTypeRef types[MAX_ARGS];
223 LLVMValueRef *assign[MAX_ARGS];
224 unsigned array_params_mask;
225 uint8_t count;
226 uint8_t sgpr_count;
227 uint8_t num_sgprs_used;
228 uint8_t num_vgprs_used;
229 };
230
231 enum ac_arg_regfile {
232 ARG_SGPR,
233 ARG_VGPR,
234 };
235
236 static void
237 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
238 LLVMValueRef *param_ptr)
239 {
240 assert(info->count < MAX_ARGS);
241
242 info->assign[info->count] = param_ptr;
243 info->types[info->count] = type;
244 info->count++;
245
246 if (regfile == ARG_SGPR) {
247 info->num_sgprs_used += ac_get_type_size(type) / 4;
248 info->sgpr_count++;
249 } else {
250 assert(regfile == ARG_VGPR);
251 info->num_vgprs_used += ac_get_type_size(type) / 4;
252 }
253 }
254
255 static inline void
256 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
257 {
258 info->array_params_mask |= (1 << info->count);
259 add_arg(info, ARG_SGPR, type, param_ptr);
260 }
261
262 static void assign_arguments(LLVMValueRef main_function,
263 struct arg_info *info)
264 {
265 unsigned i;
266 for (i = 0; i < info->count; i++) {
267 if (info->assign[i])
268 *info->assign[i] = LLVMGetParam(main_function, i);
269 }
270 }
271
272 static LLVMValueRef
273 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
274 LLVMBuilderRef builder, LLVMTypeRef *return_types,
275 unsigned num_return_elems,
276 struct arg_info *args,
277 unsigned max_workgroup_size,
278 bool unsafe_math)
279 {
280 LLVMTypeRef main_function_type, ret_type;
281 LLVMBasicBlockRef main_function_body;
282
283 if (num_return_elems)
284 ret_type = LLVMStructTypeInContext(ctx, return_types,
285 num_return_elems, true);
286 else
287 ret_type = LLVMVoidTypeInContext(ctx);
288
289 /* Setup the function */
290 main_function_type =
291 LLVMFunctionType(ret_type, args->types, args->count, 0);
292 LLVMValueRef main_function =
293 LLVMAddFunction(module, "main", main_function_type);
294 main_function_body =
295 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
296 LLVMPositionBuilderAtEnd(builder, main_function_body);
297
298 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
299 for (unsigned i = 0; i < args->sgpr_count; ++i) {
300 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
301
302 if (args->array_params_mask & (1 << i)) {
303 LLVMValueRef P = LLVMGetParam(main_function, i);
304 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
305 ac_add_attr_dereferenceable(P, UINT64_MAX);
306 }
307 }
308
309 if (max_workgroup_size) {
310 ac_llvm_add_target_dep_function_attr(main_function,
311 "amdgpu-max-work-group-size",
312 max_workgroup_size);
313 }
314 if (unsafe_math) {
315 /* These were copied from some LLVM test. */
316 LLVMAddTargetDependentFunctionAttr(main_function,
317 "less-precise-fpmad",
318 "true");
319 LLVMAddTargetDependentFunctionAttr(main_function,
320 "no-infs-fp-math",
321 "true");
322 LLVMAddTargetDependentFunctionAttr(main_function,
323 "no-nans-fp-math",
324 "true");
325 LLVMAddTargetDependentFunctionAttr(main_function,
326 "unsafe-fp-math",
327 "true");
328 LLVMAddTargetDependentFunctionAttr(main_function,
329 "no-signed-zeros-fp-math",
330 "true");
331 }
332 return main_function;
333 }
334
335 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
336 {
337 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
338 type = LLVMGetElementType(type);
339
340 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
341 return LLVMGetIntTypeWidth(type);
342
343 if (type == ctx->f16)
344 return 16;
345 if (type == ctx->f32)
346 return 32;
347 if (type == ctx->f64)
348 return 64;
349
350 unreachable("Unhandled type kind in get_elem_bits");
351 }
352
353 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
354 LLVMValueRef param, unsigned rshift,
355 unsigned bitwidth)
356 {
357 LLVMValueRef value = param;
358 if (rshift)
359 value = LLVMBuildLShr(ctx->builder, value,
360 LLVMConstInt(ctx->i32, rshift, false), "");
361
362 if (rshift + bitwidth < 32) {
363 unsigned mask = (1 << bitwidth) - 1;
364 value = LLVMBuildAnd(ctx->builder, value,
365 LLVMConstInt(ctx->i32, mask, false), "");
366 }
367 return value;
368 }
369
370 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
371 {
372 switch (ctx->stage) {
373 case MESA_SHADER_TESS_CTRL:
374 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
375 case MESA_SHADER_TESS_EVAL:
376 return ctx->tes_rel_patch_id;
377 break;
378 default:
379 unreachable("Illegal stage");
380 }
381 }
382
383 /* Tessellation shaders pass outputs to the next shader using LDS.
384 *
385 * LS outputs = TCS inputs
386 * TCS outputs = TES inputs
387 *
388 * The LDS layout is:
389 * - TCS inputs for patch 0
390 * - TCS inputs for patch 1
391 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
392 * - ...
393 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
394 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
395 * - TCS outputs for patch 1
396 * - Per-patch TCS outputs for patch 1
397 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
398 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
399 * - ...
400 *
401 * All three shaders VS(LS), TCS, TES share the same LDS space.
402 */
403 static LLVMValueRef
404 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
405 {
406 if (ctx->stage == MESA_SHADER_VERTEX)
407 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
408 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
409 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
410 else {
411 assert(0);
412 return NULL;
413 }
414 }
415
416 static LLVMValueRef
417 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
418 {
419 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
420 }
421
422 static LLVMValueRef
423 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
424 {
425 return LLVMBuildMul(ctx->builder,
426 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
427 LLVMConstInt(ctx->ac.i32, 4, false), "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
432 {
433 return LLVMBuildMul(ctx->builder,
434 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
435 LLVMConstInt(ctx->ac.i32, 4, false), "");
436 }
437
438 static LLVMValueRef
439 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
440 {
441 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
442 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
443
444 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
445 }
446
447 static LLVMValueRef
448 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
449 {
450 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
451 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
452 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
453
454 return LLVMBuildAdd(ctx->builder, patch0_offset,
455 LLVMBuildMul(ctx->builder, patch_stride,
456 rel_patch_id, ""),
457 "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 LLVMValueRef patch0_patch_data_offset =
464 get_tcs_out_patch0_patch_data_offset(ctx);
465 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
466 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
467
468 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
469 LLVMBuildMul(ctx->builder, patch_stride,
470 rel_patch_id, ""),
471 "");
472 }
473
474 static void
475 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
476 uint32_t indirect_offset)
477 {
478 ud_info->sgpr_idx = *sgpr_idx;
479 ud_info->num_sgprs = num_sgprs;
480 ud_info->indirect = indirect_offset > 0;
481 ud_info->indirect_offset = indirect_offset;
482 *sgpr_idx += num_sgprs;
483 }
484
485 static void
486 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
487 uint8_t num_sgprs)
488 {
489 struct ac_userdata_info *ud_info =
490 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
491 assert(ud_info);
492
493 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
494 }
495
496 static void
497 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
498 uint32_t indirect_offset)
499 {
500 struct ac_userdata_info *ud_info =
501 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
502 assert(ud_info);
503
504 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
505 }
506
507 struct user_sgpr_info {
508 bool need_ring_offsets;
509 uint8_t sgpr_count;
510 bool indirect_all_descriptor_sets;
511 };
512
513 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
514 gl_shader_stage stage)
515 {
516 switch (stage) {
517 case MESA_SHADER_VERTEX:
518 if (ctx->shader_info->info.needs_multiview_view_index ||
519 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
520 return true;
521 break;
522 case MESA_SHADER_TESS_EVAL:
523 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
524 return true;
525 break;
526 case MESA_SHADER_GEOMETRY:
527 case MESA_SHADER_TESS_CTRL:
528 if (ctx->shader_info->info.needs_multiview_view_index)
529 return true;
530 break;
531 default:
532 break;
533 }
534 return false;
535 }
536
537 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
538 gl_shader_stage stage,
539 bool needs_view_index,
540 struct user_sgpr_info *user_sgpr_info)
541 {
542 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
543
544 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
545 if (stage == MESA_SHADER_GEOMETRY ||
546 stage == MESA_SHADER_VERTEX ||
547 stage == MESA_SHADER_TESS_CTRL ||
548 stage == MESA_SHADER_TESS_EVAL ||
549 ctx->is_gs_copy_shader)
550 user_sgpr_info->need_ring_offsets = true;
551
552 if (stage == MESA_SHADER_FRAGMENT &&
553 ctx->shader_info->info.ps.needs_sample_positions)
554 user_sgpr_info->need_ring_offsets = true;
555
556 /* 2 user sgprs will nearly always be allocated for scratch/rings */
557 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
558 user_sgpr_info->sgpr_count += 2;
559 }
560
561 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
562 switch (stage) {
563 case MESA_SHADER_COMPUTE:
564 if (ctx->shader_info->info.cs.uses_grid_size)
565 user_sgpr_info->sgpr_count += 3;
566 break;
567 case MESA_SHADER_FRAGMENT:
568 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
569 break;
570 case MESA_SHADER_VERTEX:
571 if (!ctx->is_gs_copy_shader) {
572 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
573 if (ctx->shader_info->info.vs.needs_draw_id) {
574 user_sgpr_info->sgpr_count += 3;
575 } else {
576 user_sgpr_info->sgpr_count += 2;
577 }
578 }
579 if (ctx->options->key.vs.as_ls)
580 user_sgpr_info->sgpr_count++;
581 break;
582 case MESA_SHADER_TESS_CTRL:
583 user_sgpr_info->sgpr_count += 4;
584 break;
585 case MESA_SHADER_TESS_EVAL:
586 user_sgpr_info->sgpr_count += 1;
587 break;
588 case MESA_SHADER_GEOMETRY:
589 user_sgpr_info->sgpr_count += 2;
590 break;
591 default:
592 break;
593 }
594
595 if (needs_view_index)
596 user_sgpr_info->sgpr_count++;
597
598 if (ctx->shader_info->info.loads_push_constants)
599 user_sgpr_info->sgpr_count += 2;
600
601 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
602 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
603
604 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
605 user_sgpr_info->sgpr_count += 2;
606 user_sgpr_info->indirect_all_descriptor_sets = true;
607 } else {
608 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
609 }
610 }
611
612 static void
613 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
614 gl_shader_stage stage,
615 bool has_previous_stage,
616 gl_shader_stage previous_stage,
617 const struct user_sgpr_info *user_sgpr_info,
618 struct arg_info *args,
619 LLVMValueRef *desc_sets)
620 {
621 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
622 unsigned num_sets = ctx->options->layout ?
623 ctx->options->layout->num_sets : 0;
624 unsigned stage_mask = 1 << stage;
625
626 if (has_previous_stage)
627 stage_mask |= 1 << previous_stage;
628
629 /* 1 for each descriptor set */
630 if (!user_sgpr_info->indirect_all_descriptor_sets) {
631 for (unsigned i = 0; i < num_sets; ++i) {
632 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
633 add_array_arg(args, type,
634 &ctx->descriptor_sets[i]);
635 }
636 }
637 } else {
638 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
639 }
640
641 if (ctx->shader_info->info.loads_push_constants) {
642 /* 1 for push constants and dynamic descriptors */
643 add_array_arg(args, type, &ctx->push_constants);
644 }
645 }
646
647 static void
648 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
649 gl_shader_stage stage,
650 bool has_previous_stage,
651 gl_shader_stage previous_stage,
652 struct arg_info *args)
653 {
654 if (!ctx->is_gs_copy_shader &&
655 (stage == MESA_SHADER_VERTEX ||
656 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
657 if (ctx->shader_info->info.vs.has_vertex_buffers) {
658 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
659 &ctx->vertex_buffers);
660 }
661 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
663 if (ctx->shader_info->info.vs.needs_draw_id) {
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
665 }
666 }
667 }
668
669 static void
670 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
671 {
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
673 if (!ctx->is_gs_copy_shader) {
674 if (ctx->options->key.vs.as_ls) {
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
677 } else {
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
680 }
681 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
682 }
683 }
684
685 static void
686 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
687 {
688 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
689 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
690 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
691 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
692 }
693
694 static void
695 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
696 bool has_previous_stage, gl_shader_stage previous_stage,
697 const struct user_sgpr_info *user_sgpr_info,
698 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
699 {
700 unsigned num_sets = ctx->options->layout ?
701 ctx->options->layout->num_sets : 0;
702 unsigned stage_mask = 1 << stage;
703
704 if (has_previous_stage)
705 stage_mask |= 1 << previous_stage;
706
707 if (!user_sgpr_info->indirect_all_descriptor_sets) {
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
710 set_loc_desc(ctx, i, user_sgpr_idx, 0);
711 } else
712 ctx->descriptor_sets[i] = NULL;
713 }
714 } else {
715 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
716 user_sgpr_idx, 2);
717
718 for (unsigned i = 0; i < num_sets; ++i) {
719 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
720 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
721 ctx->descriptor_sets[i] =
722 ac_build_load_to_sgpr(&ctx->ac,
723 desc_sets,
724 LLVMConstInt(ctx->ac.i32, i, false));
725
726 } else
727 ctx->descriptor_sets[i] = NULL;
728 }
729 ctx->shader_info->need_indirect_descriptor_sets = true;
730 }
731
732 if (ctx->shader_info->info.loads_push_constants) {
733 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
734 }
735 }
736
737 static void
738 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
739 gl_shader_stage stage, bool has_previous_stage,
740 gl_shader_stage previous_stage,
741 uint8_t *user_sgpr_idx)
742 {
743 if (!ctx->is_gs_copy_shader &&
744 (stage == MESA_SHADER_VERTEX ||
745 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers) {
747 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
748 user_sgpr_idx, 2);
749 }
750
751 unsigned vs_num = 2;
752 if (ctx->shader_info->info.vs.needs_draw_id)
753 vs_num++;
754
755 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
756 user_sgpr_idx, vs_num);
757 }
758 }
759
760 static void create_function(struct nir_to_llvm_context *ctx,
761 gl_shader_stage stage,
762 bool has_previous_stage,
763 gl_shader_stage previous_stage)
764 {
765 uint8_t user_sgpr_idx;
766 struct user_sgpr_info user_sgpr_info;
767 struct arg_info args = {};
768 LLVMValueRef desc_sets;
769 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
770 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
771
772 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
773 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
774 &ctx->ring_offsets);
775 }
776
777 switch (stage) {
778 case MESA_SHADER_COMPUTE:
779 declare_global_input_sgprs(ctx, stage, has_previous_stage,
780 previous_stage, &user_sgpr_info,
781 &args, &desc_sets);
782
783 if (ctx->shader_info->info.cs.uses_grid_size) {
784 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
785 &ctx->num_work_groups);
786 }
787
788 for (int i = 0; i < 3; i++) {
789 ctx->workgroup_ids[i] = NULL;
790 if (ctx->shader_info->info.cs.uses_block_id[i]) {
791 add_arg(&args, ARG_SGPR, ctx->ac.i32,
792 &ctx->workgroup_ids[i]);
793 }
794 }
795
796 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
798 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
799 &ctx->local_invocation_ids);
800 break;
801 case MESA_SHADER_VERTEX:
802 declare_global_input_sgprs(ctx, stage, has_previous_stage,
803 previous_stage, &user_sgpr_info,
804 &args, &desc_sets);
805 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
806 previous_stage, &args);
807
808 if (needs_view_index)
809 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
810 if (ctx->options->key.vs.as_es)
811 add_arg(&args, ARG_SGPR, ctx->ac.i32,
812 &ctx->es2gs_offset);
813 else if (ctx->options->key.vs.as_ls)
814 add_arg(&args, ARG_SGPR, ctx->ac.i32,
815 &ctx->ls_out_layout);
816
817 declare_vs_input_vgprs(ctx, &args);
818 break;
819 case MESA_SHADER_TESS_CTRL:
820 if (has_previous_stage) {
821 // First 6 system regs
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
823 add_arg(&args, ARG_SGPR, ctx->ac.i32,
824 &ctx->merged_wave_info);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->tess_factor_offset);
827
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
829 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
831
832 declare_global_input_sgprs(ctx, stage,
833 has_previous_stage,
834 previous_stage,
835 &user_sgpr_info, &args,
836 &desc_sets);
837 declare_vs_specific_input_sgprs(ctx, stage,
838 has_previous_stage,
839 previous_stage, &args);
840
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->ls_out_layout);
843
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_offchip_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_out_offsets);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_layout);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_in_layout);
852 if (needs_view_index)
853 add_arg(&args, ARG_SGPR, ctx->ac.i32,
854 &ctx->view_index);
855
856 add_arg(&args, ARG_VGPR, ctx->ac.i32,
857 &ctx->abi.tcs_patch_id);
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_rel_ids);
860
861 declare_vs_input_vgprs(ctx, &args);
862 } else {
863 declare_global_input_sgprs(ctx, stage,
864 has_previous_stage,
865 previous_stage,
866 &user_sgpr_info, &args,
867 &desc_sets);
868
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_offchip_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_out_offsets);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_layout);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_in_layout);
877 if (needs_view_index)
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->view_index);
880
881 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
882 add_arg(&args, ARG_SGPR, ctx->ac.i32,
883 &ctx->tess_factor_offset);
884 add_arg(&args, ARG_VGPR, ctx->ac.i32,
885 &ctx->abi.tcs_patch_id);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_rel_ids);
888 }
889 break;
890 case MESA_SHADER_TESS_EVAL:
891 declare_global_input_sgprs(ctx, stage, has_previous_stage,
892 previous_stage, &user_sgpr_info,
893 &args, &desc_sets);
894
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
896 if (needs_view_index)
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
898
899 if (ctx->options->key.tes.as_es) {
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->es2gs_offset);
904 } else {
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
906 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
907 }
908 declare_tes_input_vgprs(ctx, &args);
909 break;
910 case MESA_SHADER_GEOMETRY:
911 if (has_previous_stage) {
912 // First 6 system regs
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->gs2vs_offset);
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->merged_wave_info);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
918
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
920 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
922
923 declare_global_input_sgprs(ctx, stage,
924 has_previous_stage,
925 previous_stage,
926 &user_sgpr_info, &args,
927 &desc_sets);
928
929 if (previous_stage == MESA_SHADER_TESS_EVAL) {
930 add_arg(&args, ARG_SGPR, ctx->ac.i32,
931 &ctx->tcs_offchip_layout);
932 } else {
933 declare_vs_specific_input_sgprs(ctx, stage,
934 has_previous_stage,
935 previous_stage,
936 &args);
937 }
938
939 add_arg(&args, ARG_SGPR, ctx->ac.i32,
940 &ctx->gsvs_ring_stride);
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_num_entries);
943 if (needs_view_index)
944 add_arg(&args, ARG_SGPR, ctx->ac.i32,
945 &ctx->view_index);
946
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->gs_vtx_offset[0]);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[2]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->abi.gs_prim_id);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_invocation_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->gs_vtx_offset[4]);
957
958 if (previous_stage == MESA_SHADER_VERTEX) {
959 declare_vs_input_vgprs(ctx, &args);
960 } else {
961 declare_tes_input_vgprs(ctx, &args);
962 }
963 } else {
964 declare_global_input_sgprs(ctx, stage,
965 has_previous_stage,
966 previous_stage,
967 &user_sgpr_info, &args,
968 &desc_sets);
969
970 add_arg(&args, ARG_SGPR, ctx->ac.i32,
971 &ctx->gsvs_ring_stride);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_num_entries);
974 if (needs_view_index)
975 add_arg(&args, ARG_SGPR, ctx->ac.i32,
976 &ctx->view_index);
977
978 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
979 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[0]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[1]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->abi.gs_prim_id);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[2]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[3]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[4]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[5]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->abi.gs_invocation_id);
996 }
997 break;
998 case MESA_SHADER_FRAGMENT:
999 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1000 previous_stage, &user_sgpr_info,
1001 &args, &desc_sets);
1002
1003 if (ctx->shader_info->info.ps.needs_sample_positions)
1004 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1005 &ctx->sample_pos_offset);
1006
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1016 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1024 break;
1025 default:
1026 unreachable("Shader stage not implemented");
1027 }
1028
1029 ctx->main_function = create_llvm_function(
1030 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1031 ctx->max_workgroup_size,
1032 ctx->options->unsafe_math);
1033 set_llvm_calling_convention(ctx->main_function, stage);
1034
1035
1036 ctx->shader_info->num_input_vgprs = 0;
1037 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1038
1039 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1040
1041 if (ctx->stage != MESA_SHADER_FRAGMENT)
1042 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1043
1044 assign_arguments(ctx->main_function, &args);
1045
1046 user_sgpr_idx = 0;
1047
1048 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1049 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1050 &user_sgpr_idx, 2);
1051 if (ctx->options->supports_spill) {
1052 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1053 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1054 NULL, 0, AC_FUNC_ATTR_READNONE);
1055 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1056 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1057 }
1058 }
1059
1060 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1061 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1062 if (has_previous_stage)
1063 user_sgpr_idx = 0;
1064
1065 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1066 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1067
1068 switch (stage) {
1069 case MESA_SHADER_COMPUTE:
1070 if (ctx->shader_info->info.cs.uses_grid_size) {
1071 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1072 &user_sgpr_idx, 3);
1073 }
1074 break;
1075 case MESA_SHADER_VERTEX:
1076 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1077 previous_stage, &user_sgpr_idx);
1078 if (ctx->view_index)
1079 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1080 if (ctx->options->key.vs.as_ls) {
1081 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1082 &user_sgpr_idx, 1);
1083 }
1084 if (ctx->options->key.vs.as_ls)
1085 ac_declare_lds_as_pointer(&ctx->ac);
1086 break;
1087 case MESA_SHADER_TESS_CTRL:
1088 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1089 previous_stage, &user_sgpr_idx);
1090 if (has_previous_stage)
1091 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1092 &user_sgpr_idx, 1);
1093 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1094 if (ctx->view_index)
1095 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1096 ac_declare_lds_as_pointer(&ctx->ac);
1097 break;
1098 case MESA_SHADER_TESS_EVAL:
1099 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1100 if (ctx->view_index)
1101 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1102 break;
1103 case MESA_SHADER_GEOMETRY:
1104 if (has_previous_stage) {
1105 if (previous_stage == MESA_SHADER_VERTEX)
1106 set_vs_specific_input_locs(ctx, stage,
1107 has_previous_stage,
1108 previous_stage,
1109 &user_sgpr_idx);
1110 else
1111 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1112 &user_sgpr_idx, 1);
1113 }
1114 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1115 &user_sgpr_idx, 2);
1116 if (ctx->view_index)
1117 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1118 if (has_previous_stage)
1119 ac_declare_lds_as_pointer(&ctx->ac);
1120 break;
1121 case MESA_SHADER_FRAGMENT:
1122 if (ctx->shader_info->info.ps.needs_sample_positions) {
1123 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1124 &user_sgpr_idx, 1);
1125 }
1126 break;
1127 default:
1128 unreachable("Shader stage not implemented");
1129 }
1130
1131 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1132 }
1133
1134 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1135 LLVMValueRef value, unsigned count)
1136 {
1137 unsigned num_components = ac_get_llvm_num_components(value);
1138 if (count == num_components)
1139 return value;
1140
1141 LLVMValueRef masks[] = {
1142 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1143 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1144
1145 if (count == 1)
1146 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1147 "");
1148
1149 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1150 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1151 }
1152
1153 static void
1154 build_store_values_extended(struct ac_llvm_context *ac,
1155 LLVMValueRef *values,
1156 unsigned value_count,
1157 unsigned value_stride,
1158 LLVMValueRef vec)
1159 {
1160 LLVMBuilderRef builder = ac->builder;
1161 unsigned i;
1162
1163 for (i = 0; i < value_count; i++) {
1164 LLVMValueRef ptr = values[i * value_stride];
1165 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1166 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1167 LLVMBuildStore(builder, value, ptr);
1168 }
1169 }
1170
1171 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1172 const nir_ssa_def *def)
1173 {
1174 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1175 if (def->num_components > 1) {
1176 type = LLVMVectorType(type, def->num_components);
1177 }
1178 return type;
1179 }
1180
1181 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1182 {
1183 assert(src.is_ssa);
1184 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1185 return (LLVMValueRef)entry->data;
1186 }
1187
1188
1189 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1190 const struct nir_block *b)
1191 {
1192 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1193 return (LLVMBasicBlockRef)entry->data;
1194 }
1195
1196 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1197 nir_alu_src src,
1198 unsigned num_components)
1199 {
1200 LLVMValueRef value = get_src(ctx, src.src);
1201 bool need_swizzle = false;
1202
1203 assert(value);
1204 LLVMTypeRef type = LLVMTypeOf(value);
1205 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1206 ? LLVMGetVectorSize(type)
1207 : 1;
1208
1209 for (unsigned i = 0; i < num_components; ++i) {
1210 assert(src.swizzle[i] < src_components);
1211 if (src.swizzle[i] != i)
1212 need_swizzle = true;
1213 }
1214
1215 if (need_swizzle || num_components != src_components) {
1216 LLVMValueRef masks[] = {
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1221
1222 if (src_components > 1 && num_components == 1) {
1223 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1224 masks[0], "");
1225 } else if (src_components == 1 && num_components > 1) {
1226 LLVMValueRef values[] = {value, value, value, value};
1227 value = ac_build_gather_values(&ctx->ac, values, num_components);
1228 } else {
1229 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1230 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1231 swizzle, "");
1232 }
1233 }
1234 assert(!src.negate);
1235 assert(!src.abs);
1236 return value;
1237 }
1238
1239 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1240 LLVMIntPredicate pred, LLVMValueRef src0,
1241 LLVMValueRef src1)
1242 {
1243 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1244 return LLVMBuildSelect(ctx->builder, result,
1245 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1246 ctx->i32_0, "");
1247 }
1248
1249 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1250 LLVMRealPredicate pred, LLVMValueRef src0,
1251 LLVMValueRef src1)
1252 {
1253 LLVMValueRef result;
1254 src0 = ac_to_float(ctx, src0);
1255 src1 = ac_to_float(ctx, src1);
1256 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1257 return LLVMBuildSelect(ctx->builder, result,
1258 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1259 ctx->i32_0, "");
1260 }
1261
1262 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1263 const char *intrin,
1264 LLVMTypeRef result_type,
1265 LLVMValueRef src0)
1266 {
1267 char name[64];
1268 LLVMValueRef params[] = {
1269 ac_to_float(ctx, src0),
1270 };
1271
1272 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1273 get_elem_bits(ctx, result_type));
1274 assert(length < sizeof(name));
1275 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1276 }
1277
1278 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1279 const char *intrin,
1280 LLVMTypeRef result_type,
1281 LLVMValueRef src0, LLVMValueRef src1)
1282 {
1283 char name[64];
1284 LLVMValueRef params[] = {
1285 ac_to_float(ctx, src0),
1286 ac_to_float(ctx, src1),
1287 };
1288
1289 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1290 get_elem_bits(ctx, result_type));
1291 assert(length < sizeof(name));
1292 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1293 }
1294
1295 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1296 const char *intrin,
1297 LLVMTypeRef result_type,
1298 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1299 {
1300 char name[64];
1301 LLVMValueRef params[] = {
1302 ac_to_float(ctx, src0),
1303 ac_to_float(ctx, src1),
1304 ac_to_float(ctx, src2),
1305 };
1306
1307 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1308 get_elem_bits(ctx, result_type));
1309 assert(length < sizeof(name));
1310 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1311 }
1312
1313 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1314 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1315 {
1316 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1317 ctx->i32_0, "");
1318 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1319 }
1320
1321 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1322 LLVMIntPredicate pred,
1323 LLVMValueRef src0, LLVMValueRef src1)
1324 {
1325 return LLVMBuildSelect(ctx->builder,
1326 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1327 src0,
1328 src1, "");
1329
1330 }
1331 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1335 LLVMBuildNeg(ctx->builder, src0, ""));
1336 }
1337
1338 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0,
1340 unsigned bitsize)
1341 {
1342 LLVMValueRef cmp, val, zero, one;
1343 LLVMTypeRef type;
1344
1345 if (bitsize == 32) {
1346 type = ctx->f32;
1347 zero = ctx->f32_0;
1348 one = ctx->f32_1;
1349 } else {
1350 type = ctx->f64;
1351 zero = ctx->f64_0;
1352 one = ctx->f64_1;
1353 }
1354
1355 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1356 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1357 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1359 return val;
1360 }
1361
1362 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0, unsigned bitsize)
1364 {
1365 LLVMValueRef cmp, val, zero, one;
1366 LLVMTypeRef type;
1367
1368 if (bitsize == 32) {
1369 type = ctx->i32;
1370 zero = ctx->i32_0;
1371 one = ctx->i32_1;
1372 } else {
1373 type = ctx->i64;
1374 zero = ctx->i64_0;
1375 one = ctx->i64_1;
1376 }
1377
1378 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1379 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1380 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1381 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1382 return val;
1383 }
1384
1385 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1386 LLVMValueRef src0, unsigned bitsize)
1387 {
1388 LLVMTypeRef type;
1389 char *intr;
1390
1391 if (bitsize == 32) {
1392 intr = "llvm.floor.f32";
1393 type = ctx->f32;
1394 } else {
1395 intr = "llvm.floor.f64";
1396 type = ctx->f64;
1397 }
1398
1399 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1400 LLVMValueRef params[] = {
1401 fsrc0,
1402 };
1403 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1404 AC_FUNC_ATTR_READNONE);
1405 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1406 }
1407
1408 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1409 const char *intrin,
1410 LLVMValueRef src0, LLVMValueRef src1)
1411 {
1412 LLVMTypeRef ret_type;
1413 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1414 LLVMValueRef res;
1415 LLVMValueRef params[] = { src0, src1 };
1416 ret_type = LLVMStructTypeInContext(ctx->context, types,
1417 2, true);
1418
1419 res = ac_build_intrinsic(ctx, intrin, ret_type,
1420 params, 2, AC_FUNC_ATTR_READNONE);
1421
1422 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1423 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1424 return res;
1425 }
1426
1427 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1431 }
1432
1433 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 src0 = ac_to_float(ctx, src0);
1437 return LLVMBuildSExt(ctx->builder,
1438 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1439 ctx->i32, "");
1440 }
1441
1442 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1443 LLVMValueRef src0,
1444 unsigned bitsize)
1445 {
1446 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1447
1448 if (bitsize == 32)
1449 return result;
1450
1451 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1452 }
1453
1454 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1455 LLVMValueRef src0)
1456 {
1457 return LLVMBuildSExt(ctx->builder,
1458 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1459 ctx->i32, "");
1460 }
1461
1462 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1463 LLVMValueRef src0)
1464 {
1465 LLVMValueRef result;
1466 LLVMValueRef cond = NULL;
1467
1468 src0 = ac_to_float(&ctx->ac, src0);
1469 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1470
1471 if (ctx->options->chip_class >= VI) {
1472 LLVMValueRef args[2];
1473 /* Check if the result is a denormal - and flush to 0 if so. */
1474 args[0] = result;
1475 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1476 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1477 }
1478
1479 /* need to convert back up to f32 */
1480 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1481
1482 if (ctx->options->chip_class >= VI)
1483 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1484 else {
1485 /* for SI/CIK */
1486 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1487 * so compare the result and flush to 0 if it's smaller.
1488 */
1489 LLVMValueRef temp, cond2;
1490 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1491 ctx->ac.f32, result);
1492 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1493 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1494 temp, "");
1495 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1496 temp, ctx->ac.f32_0, "");
1497 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1498 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1499 }
1500 return result;
1501 }
1502
1503 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1504 LLVMValueRef src0, LLVMValueRef src1)
1505 {
1506 LLVMValueRef dst64, result;
1507 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1508 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1509
1510 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1511 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1512 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1513 return result;
1514 }
1515
1516 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1517 LLVMValueRef src0, LLVMValueRef src1)
1518 {
1519 LLVMValueRef dst64, result;
1520 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1521 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1522
1523 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1524 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1525 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1526 return result;
1527 }
1528
1529 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1530 bool is_signed,
1531 const LLVMValueRef srcs[3])
1532 {
1533 LLVMValueRef result;
1534 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1535
1536 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1537 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1538 return result;
1539 }
1540
1541 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1542 LLVMValueRef src0, LLVMValueRef src1,
1543 LLVMValueRef src2, LLVMValueRef src3)
1544 {
1545 LLVMValueRef bfi_args[3], result;
1546
1547 bfi_args[0] = LLVMBuildShl(ctx->builder,
1548 LLVMBuildSub(ctx->builder,
1549 LLVMBuildShl(ctx->builder,
1550 ctx->i32_1,
1551 src3, ""),
1552 ctx->i32_1, ""),
1553 src2, "");
1554 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1555 bfi_args[2] = src0;
1556
1557 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1558
1559 /* Calculate:
1560 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1561 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1562 */
1563 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1564 LLVMBuildAnd(ctx->builder, bfi_args[0],
1565 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1566
1567 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1568 return result;
1569 }
1570
1571 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1572 LLVMValueRef src0)
1573 {
1574 LLVMValueRef comp[2];
1575
1576 src0 = ac_to_float(ctx, src0);
1577 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1578 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1579
1580 return ac_build_cvt_pkrtz_f16(ctx, comp);
1581 }
1582
1583 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1584 LLVMValueRef src0)
1585 {
1586 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1587 LLVMValueRef temps[2], result, val;
1588 int i;
1589
1590 for (i = 0; i < 2; i++) {
1591 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1592 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1593 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1594 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1595 }
1596
1597 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1598 ctx->i32_0, "");
1599 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1600 ctx->i32_1, "");
1601 return result;
1602 }
1603
1604 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1605 nir_op op,
1606 LLVMValueRef src0)
1607 {
1608 unsigned mask;
1609 int idx;
1610 LLVMValueRef result;
1611
1612 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1613 mask = AC_TID_MASK_LEFT;
1614 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1615 mask = AC_TID_MASK_TOP;
1616 else
1617 mask = AC_TID_MASK_TOP_LEFT;
1618
1619 /* for DDX we want to next X pixel, DDY next Y pixel. */
1620 if (op == nir_op_fddx_fine ||
1621 op == nir_op_fddx_coarse ||
1622 op == nir_op_fddx)
1623 idx = 1;
1624 else
1625 idx = 2;
1626
1627 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1628 return result;
1629 }
1630
1631 /*
1632 * this takes an I,J coordinate pair,
1633 * and works out the X and Y derivatives.
1634 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1635 */
1636 static LLVMValueRef emit_ddxy_interp(
1637 struct ac_nir_context *ctx,
1638 LLVMValueRef interp_ij)
1639 {
1640 LLVMValueRef result[4], a;
1641 unsigned i;
1642
1643 for (i = 0; i < 2; i++) {
1644 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1645 LLVMConstInt(ctx->ac.i32, i, false), "");
1646 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1647 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1648 }
1649 return ac_build_gather_values(&ctx->ac, result, 4);
1650 }
1651
1652 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1653 {
1654 LLVMValueRef src[4], result = NULL;
1655 unsigned num_components = instr->dest.dest.ssa.num_components;
1656 unsigned src_components;
1657 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1658
1659 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1660 switch (instr->op) {
1661 case nir_op_vec2:
1662 case nir_op_vec3:
1663 case nir_op_vec4:
1664 src_components = 1;
1665 break;
1666 case nir_op_pack_half_2x16:
1667 src_components = 2;
1668 break;
1669 case nir_op_unpack_half_2x16:
1670 src_components = 1;
1671 break;
1672 default:
1673 src_components = num_components;
1674 break;
1675 }
1676 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1677 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1678
1679 switch (instr->op) {
1680 case nir_op_fmov:
1681 case nir_op_imov:
1682 result = src[0];
1683 break;
1684 case nir_op_fneg:
1685 src[0] = ac_to_float(&ctx->ac, src[0]);
1686 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1687 break;
1688 case nir_op_ineg:
1689 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1690 break;
1691 case nir_op_inot:
1692 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1693 break;
1694 case nir_op_iadd:
1695 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_fadd:
1698 src[0] = ac_to_float(&ctx->ac, src[0]);
1699 src[1] = ac_to_float(&ctx->ac, src[1]);
1700 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_fsub:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 src[1] = ac_to_float(&ctx->ac, src[1]);
1705 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1706 break;
1707 case nir_op_isub:
1708 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1709 break;
1710 case nir_op_imul:
1711 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_imod:
1714 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_umod:
1717 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_fmod:
1720 src[0] = ac_to_float(&ctx->ac, src[0]);
1721 src[1] = ac_to_float(&ctx->ac, src[1]);
1722 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1723 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1724 ac_to_float_type(&ctx->ac, def_type), result);
1725 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1726 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1727 break;
1728 case nir_op_frem:
1729 src[0] = ac_to_float(&ctx->ac, src[0]);
1730 src[1] = ac_to_float(&ctx->ac, src[1]);
1731 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1732 break;
1733 case nir_op_irem:
1734 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1735 break;
1736 case nir_op_idiv:
1737 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_udiv:
1740 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_fmul:
1743 src[0] = ac_to_float(&ctx->ac, src[0]);
1744 src[1] = ac_to_float(&ctx->ac, src[1]);
1745 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1746 break;
1747 case nir_op_fdiv:
1748 src[0] = ac_to_float(&ctx->ac, src[0]);
1749 src[1] = ac_to_float(&ctx->ac, src[1]);
1750 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1751 break;
1752 case nir_op_frcp:
1753 src[0] = ac_to_float(&ctx->ac, src[0]);
1754 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1755 src[0]);
1756 break;
1757 case nir_op_iand:
1758 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1759 break;
1760 case nir_op_ior:
1761 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1762 break;
1763 case nir_op_ixor:
1764 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1765 break;
1766 case nir_op_ishl:
1767 result = LLVMBuildShl(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ishr:
1773 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1774 LLVMBuildZExt(ctx->ac.builder, src[1],
1775 LLVMTypeOf(src[0]), ""),
1776 "");
1777 break;
1778 case nir_op_ushr:
1779 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1780 LLVMBuildZExt(ctx->ac.builder, src[1],
1781 LLVMTypeOf(src[0]), ""),
1782 "");
1783 break;
1784 case nir_op_ilt:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1786 break;
1787 case nir_op_ine:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1789 break;
1790 case nir_op_ieq:
1791 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1792 break;
1793 case nir_op_ige:
1794 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1795 break;
1796 case nir_op_ult:
1797 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1798 break;
1799 case nir_op_uge:
1800 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1801 break;
1802 case nir_op_feq:
1803 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1804 break;
1805 case nir_op_fne:
1806 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1807 break;
1808 case nir_op_flt:
1809 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1810 break;
1811 case nir_op_fge:
1812 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1813 break;
1814 case nir_op_fabs:
1815 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1816 ac_to_float_type(&ctx->ac, def_type), src[0]);
1817 break;
1818 case nir_op_iabs:
1819 result = emit_iabs(&ctx->ac, src[0]);
1820 break;
1821 case nir_op_imax:
1822 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1823 break;
1824 case nir_op_imin:
1825 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1826 break;
1827 case nir_op_umax:
1828 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1829 break;
1830 case nir_op_umin:
1831 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1832 break;
1833 case nir_op_isign:
1834 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1835 break;
1836 case nir_op_fsign:
1837 src[0] = ac_to_float(&ctx->ac, src[0]);
1838 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1839 break;
1840 case nir_op_ffloor:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 break;
1844 case nir_op_ftrunc:
1845 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1846 ac_to_float_type(&ctx->ac, def_type), src[0]);
1847 break;
1848 case nir_op_fceil:
1849 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1850 ac_to_float_type(&ctx->ac, def_type), src[0]);
1851 break;
1852 case nir_op_fround_even:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1854 ac_to_float_type(&ctx->ac, def_type),src[0]);
1855 break;
1856 case nir_op_ffract:
1857 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1858 break;
1859 case nir_op_fsin:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_fcos:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_fsqrt:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 break;
1871 case nir_op_fexp2:
1872 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1873 ac_to_float_type(&ctx->ac, def_type), src[0]);
1874 break;
1875 case nir_op_flog2:
1876 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1877 ac_to_float_type(&ctx->ac, def_type), src[0]);
1878 break;
1879 case nir_op_frsq:
1880 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1881 ac_to_float_type(&ctx->ac, def_type), src[0]);
1882 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1883 result);
1884 break;
1885 case nir_op_fpow:
1886 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1887 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1888 break;
1889 case nir_op_fmax:
1890 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1891 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1892 if (ctx->ac.chip_class < GFX9 &&
1893 instr->dest.dest.ssa.bit_size == 32) {
1894 /* Only pre-GFX9 chips do not flush denorms. */
1895 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1896 ac_to_float_type(&ctx->ac, def_type),
1897 result);
1898 }
1899 break;
1900 case nir_op_fmin:
1901 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1902 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1903 if (ctx->ac.chip_class < GFX9 &&
1904 instr->dest.dest.ssa.bit_size == 32) {
1905 /* Only pre-GFX9 chips do not flush denorms. */
1906 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1907 ac_to_float_type(&ctx->ac, def_type),
1908 result);
1909 }
1910 break;
1911 case nir_op_ffma:
1912 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1913 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1914 break;
1915 case nir_op_ibitfield_extract:
1916 result = emit_bitfield_extract(&ctx->ac, true, src);
1917 break;
1918 case nir_op_ubitfield_extract:
1919 result = emit_bitfield_extract(&ctx->ac, false, src);
1920 break;
1921 case nir_op_bitfield_insert:
1922 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1923 break;
1924 case nir_op_bitfield_reverse:
1925 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1926 break;
1927 case nir_op_bit_count:
1928 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1929 break;
1930 case nir_op_vec2:
1931 case nir_op_vec3:
1932 case nir_op_vec4:
1933 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1934 src[i] = ac_to_integer(&ctx->ac, src[i]);
1935 result = ac_build_gather_values(&ctx->ac, src, num_components);
1936 break;
1937 case nir_op_f2i32:
1938 case nir_op_f2i64:
1939 src[0] = ac_to_float(&ctx->ac, src[0]);
1940 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1941 break;
1942 case nir_op_f2u32:
1943 case nir_op_f2u64:
1944 src[0] = ac_to_float(&ctx->ac, src[0]);
1945 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1946 break;
1947 case nir_op_i2f32:
1948 case nir_op_i2f64:
1949 src[0] = ac_to_integer(&ctx->ac, src[0]);
1950 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1951 break;
1952 case nir_op_u2f32:
1953 case nir_op_u2f64:
1954 src[0] = ac_to_integer(&ctx->ac, src[0]);
1955 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1956 break;
1957 case nir_op_f2f64:
1958 src[0] = ac_to_float(&ctx->ac, src[0]);
1959 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1960 break;
1961 case nir_op_f2f32:
1962 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1963 break;
1964 case nir_op_u2u32:
1965 case nir_op_u2u64:
1966 src[0] = ac_to_integer(&ctx->ac, src[0]);
1967 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1968 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1969 else
1970 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1971 break;
1972 case nir_op_i2i32:
1973 case nir_op_i2i64:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1976 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1977 else
1978 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1979 break;
1980 case nir_op_bcsel:
1981 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1982 break;
1983 case nir_op_find_lsb:
1984 src[0] = ac_to_integer(&ctx->ac, src[0]);
1985 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1986 break;
1987 case nir_op_ufind_msb:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1990 break;
1991 case nir_op_ifind_msb:
1992 src[0] = ac_to_integer(&ctx->ac, src[0]);
1993 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1994 break;
1995 case nir_op_uadd_carry:
1996 src[0] = ac_to_integer(&ctx->ac, src[0]);
1997 src[1] = ac_to_integer(&ctx->ac, src[1]);
1998 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1999 break;
2000 case nir_op_usub_borrow:
2001 src[0] = ac_to_integer(&ctx->ac, src[0]);
2002 src[1] = ac_to_integer(&ctx->ac, src[1]);
2003 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2004 break;
2005 case nir_op_b2f:
2006 result = emit_b2f(&ctx->ac, src[0]);
2007 break;
2008 case nir_op_f2b:
2009 result = emit_f2b(&ctx->ac, src[0]);
2010 break;
2011 case nir_op_b2i:
2012 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2013 break;
2014 case nir_op_i2b:
2015 src[0] = ac_to_integer(&ctx->ac, src[0]);
2016 result = emit_i2b(&ctx->ac, src[0]);
2017 break;
2018 case nir_op_fquantize2f16:
2019 result = emit_f2f16(ctx->nctx, src[0]);
2020 break;
2021 case nir_op_umul_high:
2022 src[0] = ac_to_integer(&ctx->ac, src[0]);
2023 src[1] = ac_to_integer(&ctx->ac, src[1]);
2024 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2025 break;
2026 case nir_op_imul_high:
2027 src[0] = ac_to_integer(&ctx->ac, src[0]);
2028 src[1] = ac_to_integer(&ctx->ac, src[1]);
2029 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2030 break;
2031 case nir_op_pack_half_2x16:
2032 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2033 break;
2034 case nir_op_unpack_half_2x16:
2035 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2036 break;
2037 case nir_op_fddx:
2038 case nir_op_fddy:
2039 case nir_op_fddx_fine:
2040 case nir_op_fddy_fine:
2041 case nir_op_fddx_coarse:
2042 case nir_op_fddy_coarse:
2043 result = emit_ddxy(ctx, instr->op, src[0]);
2044 break;
2045
2046 case nir_op_unpack_64_2x32_split_x: {
2047 assert(instr->src[0].src.ssa->num_components == 1);
2048 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2049 ctx->ac.v2i32,
2050 "");
2051 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2052 ctx->ac.i32_0, "");
2053 break;
2054 }
2055
2056 case nir_op_unpack_64_2x32_split_y: {
2057 assert(instr->src[0].src.ssa->num_components == 1);
2058 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2059 ctx->ac.v2i32,
2060 "");
2061 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2062 ctx->ac.i32_1, "");
2063 break;
2064 }
2065
2066 case nir_op_pack_64_2x32_split: {
2067 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2068 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2069 src[0], ctx->ac.i32_0, "");
2070 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2071 src[1], ctx->ac.i32_1, "");
2072 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2073 break;
2074 }
2075
2076 default:
2077 fprintf(stderr, "Unknown NIR alu instr: ");
2078 nir_print_instr(&instr->instr, stderr);
2079 fprintf(stderr, "\n");
2080 abort();
2081 }
2082
2083 if (result) {
2084 assert(instr->dest.dest.is_ssa);
2085 result = ac_to_integer(&ctx->ac, result);
2086 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2087 result);
2088 }
2089 }
2090
2091 static void visit_load_const(struct ac_nir_context *ctx,
2092 const nir_load_const_instr *instr)
2093 {
2094 LLVMValueRef values[4], value = NULL;
2095 LLVMTypeRef element_type =
2096 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2097
2098 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2099 switch (instr->def.bit_size) {
2100 case 32:
2101 values[i] = LLVMConstInt(element_type,
2102 instr->value.u32[i], false);
2103 break;
2104 case 64:
2105 values[i] = LLVMConstInt(element_type,
2106 instr->value.u64[i], false);
2107 break;
2108 default:
2109 fprintf(stderr,
2110 "unsupported nir load_const bit_size: %d\n",
2111 instr->def.bit_size);
2112 abort();
2113 }
2114 }
2115 if (instr->def.num_components > 1) {
2116 value = LLVMConstVector(values, instr->def.num_components);
2117 } else
2118 value = values[0];
2119
2120 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2121 }
2122
2123 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2124 LLVMTypeRef type)
2125 {
2126 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2127 return LLVMBuildBitCast(ctx->builder, ptr,
2128 LLVMPointerType(type, addr_space), "");
2129 }
2130
2131 static LLVMValueRef
2132 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2133 {
2134 LLVMValueRef size =
2135 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2136 LLVMConstInt(ctx->ac.i32, 2, false), "");
2137
2138 /* VI only */
2139 if (ctx->ac.chip_class == VI && in_elements) {
2140 /* On VI, the descriptor contains the size in bytes,
2141 * but TXQ must return the size in elements.
2142 * The stride is always non-zero for resources using TXQ.
2143 */
2144 LLVMValueRef stride =
2145 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2146 ctx->ac.i32_1, "");
2147 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2148 LLVMConstInt(ctx->ac.i32, 16, false), "");
2149 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2150 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2151
2152 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2153 }
2154 return size;
2155 }
2156
2157 /**
2158 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2159 * intrinsic names).
2160 */
2161 static void build_int_type_name(
2162 LLVMTypeRef type,
2163 char *buf, unsigned bufsize)
2164 {
2165 assert(bufsize >= 6);
2166
2167 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2168 snprintf(buf, bufsize, "v%ui32",
2169 LLVMGetVectorSize(type));
2170 else
2171 strcpy(buf, "i32");
2172 }
2173
2174 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2175 struct ac_image_args *args,
2176 const nir_tex_instr *instr)
2177 {
2178 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2179 LLVMValueRef coord = args->addr;
2180 LLVMValueRef half_texel[2];
2181 LLVMValueRef compare_cube_wa = NULL;
2182 LLVMValueRef result;
2183 int c;
2184 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2185
2186 //TODO Rect
2187 {
2188 struct ac_image_args txq_args = { 0 };
2189
2190 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2191 txq_args.opcode = ac_image_get_resinfo;
2192 txq_args.dmask = 0xf;
2193 txq_args.addr = ctx->i32_0;
2194 txq_args.resource = args->resource;
2195 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2196
2197 for (c = 0; c < 2; c++) {
2198 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2199 LLVMConstInt(ctx->i32, c, false), "");
2200 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2201 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2202 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2203 LLVMConstReal(ctx->f32, -0.5), "");
2204 }
2205 }
2206
2207 LLVMValueRef orig_coords = args->addr;
2208
2209 for (c = 0; c < 2; c++) {
2210 LLVMValueRef tmp;
2211 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2212 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2213 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2214 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2215 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2216 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2217 }
2218
2219
2220 /*
2221 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2222 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2223 * workaround by sampling using a scaled type and converting.
2224 * This is taken from amdgpu-pro shaders.
2225 */
2226 /* NOTE this produces some ugly code compared to amdgpu-pro,
2227 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2228 * and then reads them back. -pro generates two selects,
2229 * one s_cmp for the descriptor rewriting
2230 * one v_cmp for the coordinate and result changes.
2231 */
2232 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2233 LLVMValueRef tmp, tmp2;
2234
2235 /* workaround 8/8/8/8 uint/sint cube gather bug */
2236 /* first detect it then change to a scaled read and f2i */
2237 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2238 tmp2 = tmp;
2239
2240 /* extract the DATA_FORMAT */
2241 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2242 LLVMConstInt(ctx->i32, 6, false), false);
2243
2244 /* is the DATA_FORMAT == 8_8_8_8 */
2245 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2246
2247 if (stype == GLSL_TYPE_UINT)
2248 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2249 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2250 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2251 else
2252 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2253 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2254 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2255
2256 /* replace the NUM FORMAT in the descriptor */
2257 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2258 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2259
2260 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2261
2262 /* don't modify the coordinates for this case */
2263 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2264 }
2265 args->addr = coord;
2266 result = ac_build_image_opcode(ctx, args);
2267
2268 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2269 LLVMValueRef tmp, tmp2;
2270
2271 /* if the cube workaround is in place, f2i the result. */
2272 for (c = 0; c < 4; c++) {
2273 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2274 if (stype == GLSL_TYPE_UINT)
2275 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2276 else
2277 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2278 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2279 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2280 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2281 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2282 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2283 }
2284 }
2285 return result;
2286 }
2287
2288 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2289 const nir_tex_instr *instr,
2290 bool lod_is_zero,
2291 struct ac_image_args *args)
2292 {
2293 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2294 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2295
2296 return ac_build_buffer_load_format(&ctx->ac,
2297 args->resource,
2298 args->addr,
2299 ctx->ac.i32_0,
2300 util_last_bit(mask),
2301 false, true);
2302 }
2303
2304 args->opcode = ac_image_sample;
2305 args->compare = instr->is_shadow;
2306
2307 switch (instr->op) {
2308 case nir_texop_txf:
2309 case nir_texop_txf_ms:
2310 case nir_texop_samples_identical:
2311 args->opcode = lod_is_zero ||
2312 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2313 ac_image_load : ac_image_load_mip;
2314 args->compare = false;
2315 args->offset = false;
2316 break;
2317 case nir_texop_txb:
2318 args->bias = true;
2319 break;
2320 case nir_texop_txl:
2321 if (lod_is_zero)
2322 args->level_zero = true;
2323 else
2324 args->lod = true;
2325 break;
2326 case nir_texop_txs:
2327 case nir_texop_query_levels:
2328 args->opcode = ac_image_get_resinfo;
2329 break;
2330 case nir_texop_tex:
2331 if (ctx->stage != MESA_SHADER_FRAGMENT)
2332 args->level_zero = true;
2333 break;
2334 case nir_texop_txd:
2335 args->deriv = true;
2336 break;
2337 case nir_texop_tg4:
2338 args->opcode = ac_image_gather4;
2339 args->level_zero = true;
2340 break;
2341 case nir_texop_lod:
2342 args->opcode = ac_image_get_lod;
2343 args->compare = false;
2344 args->offset = false;
2345 break;
2346 default:
2347 break;
2348 }
2349
2350 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2351 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2352 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2353 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2354 }
2355 }
2356 return ac_build_image_opcode(&ctx->ac, args);
2357 }
2358
2359 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2360 nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2363 unsigned desc_set = nir_intrinsic_desc_set(instr);
2364 unsigned binding = nir_intrinsic_binding(instr);
2365 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2366 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2367 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2368 unsigned base_offset = layout->binding[binding].offset;
2369 LLVMValueRef offset, stride;
2370
2371 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2372 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2373 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2374 layout->binding[binding].dynamic_offset_offset;
2375 desc_ptr = ctx->push_constants;
2376 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2377 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2378 } else
2379 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2380
2381 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2382 index = LLVMBuildMul(ctx->builder, index, stride, "");
2383 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2384
2385 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2386 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2387 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2388
2389 return desc_ptr;
2390 }
2391
2392 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2393 nir_intrinsic_instr *instr)
2394 {
2395 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2396 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2397
2398 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2399 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2400 return result;
2401 }
2402
2403 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2404 nir_intrinsic_instr *instr)
2405 {
2406 LLVMValueRef ptr, addr;
2407
2408 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2409 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2410
2411 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2412 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2413
2414 return LLVMBuildLoad(ctx->builder, ptr, "");
2415 }
2416
2417 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2418 const nir_intrinsic_instr *instr)
2419 {
2420 LLVMValueRef index = get_src(ctx, instr->src[0]);
2421
2422 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2423 }
2424
2425 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2426 {
2427 uint32_t new_mask = 0;
2428 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2429 if (mask & (1u << i))
2430 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2431 return new_mask;
2432 }
2433
2434 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2435 unsigned start, unsigned count)
2436 {
2437 LLVMTypeRef type = LLVMTypeOf(src);
2438
2439 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2440 assert(start == 0);
2441 assert(count == 1);
2442 return src;
2443 }
2444
2445 unsigned src_elements = LLVMGetVectorSize(type);
2446 assert(start < src_elements);
2447 assert(start + count <= src_elements);
2448
2449 if (start == 0 && count == src_elements)
2450 return src;
2451
2452 if (count == 1)
2453 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2454
2455 assert(count <= 8);
2456 LLVMValueRef indices[8];
2457 for (unsigned i = 0; i < count; ++i)
2458 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2459
2460 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2461 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2462 }
2463
2464 static void visit_store_ssbo(struct ac_nir_context *ctx,
2465 nir_intrinsic_instr *instr)
2466 {
2467 const char *store_name;
2468 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2469 LLVMTypeRef data_type = ctx->ac.f32;
2470 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2471 int components_32bit = elem_size_mult * instr->num_components;
2472 unsigned writemask = nir_intrinsic_write_mask(instr);
2473 LLVMValueRef base_data, base_offset;
2474 LLVMValueRef params[6];
2475
2476 params[1] = ctx->abi->load_ssbo(ctx->abi,
2477 get_src(ctx, instr->src[1]), true);
2478 params[2] = ctx->ac.i32_0; /* vindex */
2479 params[4] = ctx->ac.i1false; /* glc */
2480 params[5] = ctx->ac.i1false; /* slc */
2481
2482 if (components_32bit > 1)
2483 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2484
2485 writemask = widen_mask(writemask, elem_size_mult);
2486
2487 base_data = ac_to_float(&ctx->ac, src_data);
2488 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2489 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2490 data_type, "");
2491 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2492 while (writemask) {
2493 int start, count;
2494 LLVMValueRef data;
2495 LLVMValueRef offset;
2496
2497 u_bit_scan_consecutive_range(&writemask, &start, &count);
2498
2499 /* Due to an LLVM limitation, split 3-element writes
2500 * into a 2-element and a 1-element write. */
2501 if (count == 3) {
2502 writemask |= 1 << (start + 2);
2503 count = 2;
2504 }
2505
2506 if (count > 4) {
2507 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2508 count = 4;
2509 }
2510
2511 if (count == 4) {
2512 store_name = "llvm.amdgcn.buffer.store.v4f32";
2513 } else if (count == 2) {
2514 store_name = "llvm.amdgcn.buffer.store.v2f32";
2515
2516 } else {
2517 assert(count == 1);
2518 store_name = "llvm.amdgcn.buffer.store.f32";
2519 }
2520 data = extract_vector_range(&ctx->ac, base_data, start, count);
2521
2522 offset = base_offset;
2523 if (start != 0) {
2524 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2525 }
2526 params[0] = data;
2527 params[3] = offset;
2528 ac_build_intrinsic(&ctx->ac, store_name,
2529 ctx->ac.voidt, params, 6, 0);
2530 }
2531 }
2532
2533 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2534 const nir_intrinsic_instr *instr)
2535 {
2536 const char *name;
2537 LLVMValueRef params[6];
2538 int arg_count = 0;
2539
2540 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2541 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2542 }
2543 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2544 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2545 get_src(ctx, instr->src[0]),
2546 true);
2547 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2548 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2549 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2550
2551 switch (instr->intrinsic) {
2552 case nir_intrinsic_ssbo_atomic_add:
2553 name = "llvm.amdgcn.buffer.atomic.add";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imin:
2556 name = "llvm.amdgcn.buffer.atomic.smin";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umin:
2559 name = "llvm.amdgcn.buffer.atomic.umin";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_imax:
2562 name = "llvm.amdgcn.buffer.atomic.smax";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_umax:
2565 name = "llvm.amdgcn.buffer.atomic.umax";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_and:
2568 name = "llvm.amdgcn.buffer.atomic.and";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_or:
2571 name = "llvm.amdgcn.buffer.atomic.or";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_xor:
2574 name = "llvm.amdgcn.buffer.atomic.xor";
2575 break;
2576 case nir_intrinsic_ssbo_atomic_exchange:
2577 name = "llvm.amdgcn.buffer.atomic.swap";
2578 break;
2579 case nir_intrinsic_ssbo_atomic_comp_swap:
2580 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2581 break;
2582 default:
2583 abort();
2584 }
2585
2586 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2587 }
2588
2589 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2590 const nir_intrinsic_instr *instr)
2591 {
2592 LLVMValueRef results[2];
2593 int load_components;
2594 int num_components = instr->num_components;
2595 if (instr->dest.ssa.bit_size == 64)
2596 num_components *= 2;
2597
2598 for (int i = 0; i < num_components; i += load_components) {
2599 load_components = MIN2(num_components - i, 4);
2600 const char *load_name;
2601 LLVMTypeRef data_type = ctx->ac.f32;
2602 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2603 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2604
2605 if (load_components == 3)
2606 data_type = LLVMVectorType(ctx->ac.f32, 4);
2607 else if (load_components > 1)
2608 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2609
2610 if (load_components >= 3)
2611 load_name = "llvm.amdgcn.buffer.load.v4f32";
2612 else if (load_components == 2)
2613 load_name = "llvm.amdgcn.buffer.load.v2f32";
2614 else if (load_components == 1)
2615 load_name = "llvm.amdgcn.buffer.load.f32";
2616 else
2617 unreachable("unhandled number of components");
2618
2619 LLVMValueRef params[] = {
2620 ctx->abi->load_ssbo(ctx->abi,
2621 get_src(ctx, instr->src[0]),
2622 false),
2623 ctx->ac.i32_0,
2624 offset,
2625 ctx->ac.i1false,
2626 ctx->ac.i1false,
2627 };
2628
2629 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2630 }
2631
2632 assume(results[0]);
2633 LLVMValueRef ret = results[0];
2634 if (num_components > 4 || num_components == 3) {
2635 LLVMValueRef masks[] = {
2636 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2637 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2638 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2639 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2640 };
2641
2642 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2643 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2644 results[num_components > 4 ? 1 : 0], swizzle, "");
2645 }
2646
2647 return LLVMBuildBitCast(ctx->ac.builder, ret,
2648 get_def_type(ctx, &instr->dest.ssa), "");
2649 }
2650
2651 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2652 const nir_intrinsic_instr *instr)
2653 {
2654 LLVMValueRef ret;
2655 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2656 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2657 int num_components = instr->num_components;
2658
2659 if (ctx->abi->load_ubo)
2660 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2661
2662 if (instr->dest.ssa.bit_size == 64)
2663 num_components *= 2;
2664
2665 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2666 NULL, 0, false, false, true, true);
2667 ret = trim_vector(&ctx->ac, ret, num_components);
2668 return LLVMBuildBitCast(ctx->ac.builder, ret,
2669 get_def_type(ctx, &instr->dest.ssa), "");
2670 }
2671
2672 static void
2673 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2674 bool vs_in, unsigned *vertex_index_out,
2675 LLVMValueRef *vertex_index_ref,
2676 unsigned *const_out, LLVMValueRef *indir_out)
2677 {
2678 unsigned const_offset = 0;
2679 nir_deref *tail = &deref->deref;
2680 LLVMValueRef offset = NULL;
2681
2682 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2683 tail = tail->child;
2684 nir_deref_array *deref_array = nir_deref_as_array(tail);
2685 if (vertex_index_out)
2686 *vertex_index_out = deref_array->base_offset;
2687
2688 if (vertex_index_ref) {
2689 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2690 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2691 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2692 }
2693 *vertex_index_ref = vtx;
2694 }
2695 }
2696
2697 if (deref->var->data.compact) {
2698 assert(tail->child->deref_type == nir_deref_type_array);
2699 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2700 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2701 /* We always lower indirect dereferences for "compact" array vars. */
2702 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2703
2704 const_offset = deref_array->base_offset;
2705 goto out;
2706 }
2707
2708 while (tail->child != NULL) {
2709 const struct glsl_type *parent_type = tail->type;
2710 tail = tail->child;
2711
2712 if (tail->deref_type == nir_deref_type_array) {
2713 nir_deref_array *deref_array = nir_deref_as_array(tail);
2714 LLVMValueRef index, stride, local_offset;
2715 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2716
2717 const_offset += size * deref_array->base_offset;
2718 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2719 continue;
2720
2721 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2722 index = get_src(ctx, deref_array->indirect);
2723 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2724 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2725
2726 if (offset)
2727 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2728 else
2729 offset = local_offset;
2730 } else if (tail->deref_type == nir_deref_type_struct) {
2731 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2732
2733 for (unsigned i = 0; i < deref_struct->index; i++) {
2734 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2735 const_offset += glsl_count_attribute_slots(ft, vs_in);
2736 }
2737 } else
2738 unreachable("unsupported deref type");
2739
2740 }
2741 out:
2742 if (const_offset && offset)
2743 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2744 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2745 "");
2746
2747 *const_out = const_offset;
2748 *indir_out = offset;
2749 }
2750
2751
2752 /* The offchip buffer layout for TCS->TES is
2753 *
2754 * - attribute 0 of patch 0 vertex 0
2755 * - attribute 0 of patch 0 vertex 1
2756 * - attribute 0 of patch 0 vertex 2
2757 * ...
2758 * - attribute 0 of patch 1 vertex 0
2759 * - attribute 0 of patch 1 vertex 1
2760 * ...
2761 * - attribute 1 of patch 0 vertex 0
2762 * - attribute 1 of patch 0 vertex 1
2763 * ...
2764 * - per patch attribute 0 of patch 0
2765 * - per patch attribute 0 of patch 1
2766 * ...
2767 *
2768 * Note that every attribute has 4 components.
2769 */
2770 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2771 LLVMValueRef vertex_index,
2772 LLVMValueRef param_index)
2773 {
2774 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2775 LLVMValueRef param_stride, constant16;
2776 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2777
2778 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2779 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2780 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2781 num_patches, "");
2782
2783 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2784 if (vertex_index) {
2785 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2786 vertices_per_patch, "");
2787
2788 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2789 vertex_index, "");
2790
2791 param_stride = total_vertices;
2792 } else {
2793 base_addr = rel_patch_id;
2794 param_stride = num_patches;
2795 }
2796
2797 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2798 LLVMBuildMul(ctx->builder, param_index,
2799 param_stride, ""), "");
2800
2801 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2802
2803 if (!vertex_index) {
2804 LLVMValueRef patch_data_offset =
2805 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2806
2807 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2808 patch_data_offset, "");
2809 }
2810 return base_addr;
2811 }
2812
2813 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2814 unsigned param,
2815 unsigned const_index,
2816 bool is_compact,
2817 LLVMValueRef vertex_index,
2818 LLVMValueRef indir_index)
2819 {
2820 LLVMValueRef param_index;
2821
2822 if (indir_index)
2823 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2824 indir_index, "");
2825 else {
2826 if (const_index && !is_compact)
2827 param += const_index;
2828 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2829 }
2830 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2831 }
2832
2833 static void
2834 mark_tess_output(struct nir_to_llvm_context *ctx,
2835 bool is_patch, uint32_t param)
2836
2837 {
2838 if (is_patch) {
2839 ctx->tess_patch_outputs_written |= (1ull << param);
2840 } else
2841 ctx->tess_outputs_written |= (1ull << param);
2842 }
2843
2844 static LLVMValueRef
2845 get_dw_address(struct nir_to_llvm_context *ctx,
2846 LLVMValueRef dw_addr,
2847 unsigned param,
2848 unsigned const_index,
2849 bool compact_const_index,
2850 LLVMValueRef vertex_index,
2851 LLVMValueRef stride,
2852 LLVMValueRef indir_index)
2853
2854 {
2855
2856 if (vertex_index) {
2857 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2858 LLVMBuildMul(ctx->builder,
2859 vertex_index,
2860 stride, ""), "");
2861 }
2862
2863 if (indir_index)
2864 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2865 LLVMBuildMul(ctx->builder, indir_index,
2866 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2867 else if (const_index && !compact_const_index)
2868 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2869 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2870
2871 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2872 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2873
2874 if (const_index && compact_const_index)
2875 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2876 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2877 return dw_addr;
2878 }
2879
2880 static LLVMValueRef
2881 load_tcs_varyings(struct ac_shader_abi *abi,
2882 LLVMValueRef vertex_index,
2883 LLVMValueRef indir_index,
2884 unsigned const_index,
2885 unsigned location,
2886 unsigned driver_location,
2887 unsigned component,
2888 unsigned num_components,
2889 bool is_patch,
2890 bool is_compact,
2891 bool load_input)
2892 {
2893 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2894 LLVMValueRef dw_addr, stride;
2895 LLVMValueRef value[4], result;
2896 unsigned param = shader_io_get_unique_index(location);
2897
2898 if (load_input) {
2899 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2900 dw_addr = get_tcs_in_current_patch_offset(ctx);
2901 } else {
2902 if (!is_patch) {
2903 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2904 dw_addr = get_tcs_out_current_patch_offset(ctx);
2905 } else {
2906 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2907 stride = NULL;
2908 }
2909 }
2910
2911 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2912 indir_index);
2913
2914 for (unsigned i = 0; i < num_components + component; i++) {
2915 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2916 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2917 ctx->ac.i32_1, "");
2918 }
2919 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2920 return result;
2921 }
2922
2923 static void
2924 store_tcs_output(struct ac_shader_abi *abi,
2925 LLVMValueRef vertex_index,
2926 LLVMValueRef param_index,
2927 unsigned const_index,
2928 unsigned location,
2929 unsigned driver_location,
2930 LLVMValueRef src,
2931 unsigned component,
2932 bool is_patch,
2933 bool is_compact,
2934 unsigned writemask)
2935 {
2936 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2937 LLVMValueRef dw_addr;
2938 LLVMValueRef stride = NULL;
2939 LLVMValueRef buf_addr = NULL;
2940 unsigned param;
2941 bool store_lds = true;
2942
2943 if (is_patch) {
2944 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2945 store_lds = false;
2946 } else {
2947 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2948 store_lds = false;
2949 }
2950
2951 param = shader_io_get_unique_index(location);
2952 if (location == VARYING_SLOT_CLIP_DIST0 &&
2953 is_compact && const_index > 3) {
2954 const_index -= 3;
2955 param++;
2956 }
2957
2958 if (!is_patch) {
2959 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2960 dw_addr = get_tcs_out_current_patch_offset(ctx);
2961 } else {
2962 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2963 }
2964
2965 mark_tess_output(ctx, is_patch, param);
2966
2967 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2968 param_index);
2969 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2970 vertex_index, param_index);
2971
2972 bool is_tess_factor = false;
2973 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2974 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2975 is_tess_factor = true;
2976
2977 unsigned base = is_compact ? const_index : 0;
2978 for (unsigned chan = 0; chan < 8; chan++) {
2979 if (!(writemask & (1 << chan)))
2980 continue;
2981 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2982
2983 if (store_lds || is_tess_factor) {
2984 LLVMValueRef dw_addr_chan =
2985 LLVMBuildAdd(ctx->builder, dw_addr,
2986 LLVMConstInt(ctx->ac.i32, chan, false), "");
2987 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2988 }
2989
2990 if (!is_tess_factor && writemask != 0xF)
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2992 buf_addr, ctx->oc_lds,
2993 4 * (base + chan), 1, 0, true, false);
2994 }
2995
2996 if (writemask == 0xF) {
2997 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2998 buf_addr, ctx->oc_lds,
2999 (base * 4), 1, 0, true, false);
3000 }
3001 }
3002
3003 static LLVMValueRef
3004 load_tes_input(struct ac_shader_abi *abi,
3005 LLVMValueRef vertex_index,
3006 LLVMValueRef param_index,
3007 unsigned const_index,
3008 unsigned location,
3009 unsigned driver_location,
3010 unsigned component,
3011 unsigned num_components,
3012 bool is_patch,
3013 bool is_compact,
3014 bool load_input)
3015 {
3016 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3017 LLVMValueRef buf_addr;
3018 LLVMValueRef result;
3019 unsigned param = shader_io_get_unique_index(location);
3020
3021 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3022 const_index -= 3;
3023 param++;
3024 }
3025
3026 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3027 is_compact, vertex_index, param_index);
3028
3029 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3030 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3031
3032 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3033 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3034 result = trim_vector(&ctx->ac, result, num_components);
3035 return result;
3036 }
3037
3038 static LLVMValueRef
3039 load_gs_input(struct ac_shader_abi *abi,
3040 unsigned location,
3041 unsigned driver_location,
3042 unsigned component,
3043 unsigned num_components,
3044 unsigned vertex_index,
3045 unsigned const_index,
3046 LLVMTypeRef type)
3047 {
3048 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3049 LLVMValueRef vtx_offset;
3050 unsigned param, vtx_offset_param;
3051 LLVMValueRef value[4], result;
3052
3053 vtx_offset_param = vertex_index;
3054 assert(vtx_offset_param < 6);
3055 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3056 LLVMConstInt(ctx->ac.i32, 4, false), "");
3057
3058 param = shader_io_get_unique_index(location);
3059
3060 for (unsigned i = component; i < num_components + component; i++) {
3061 if (ctx->ac.chip_class >= GFX9) {
3062 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3063 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3064 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3065 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3066 } else {
3067 LLVMValueRef soffset =
3068 LLVMConstInt(ctx->ac.i32,
3069 (param * 4 + i + const_index) * 256,
3070 false);
3071
3072 value[i] = ac_build_buffer_load(&ctx->ac,
3073 ctx->esgs_ring, 1,
3074 ctx->ac.i32_0,
3075 vtx_offset, soffset,
3076 0, 1, 0, true, false);
3077
3078 value[i] = LLVMBuildBitCast(ctx->builder, value[i],
3079 type, "");
3080 }
3081 }
3082 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3083
3084 return result;
3085 }
3086
3087 static LLVMValueRef
3088 build_gep_for_deref(struct ac_nir_context *ctx,
3089 nir_deref_var *deref)
3090 {
3091 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3092 assert(entry->data);
3093 LLVMValueRef val = entry->data;
3094 nir_deref *tail = deref->deref.child;
3095 while (tail != NULL) {
3096 LLVMValueRef offset;
3097 switch (tail->deref_type) {
3098 case nir_deref_type_array: {
3099 nir_deref_array *array = nir_deref_as_array(tail);
3100 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3101 if (array->deref_array_type ==
3102 nir_deref_array_type_indirect) {
3103 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3104 get_src(ctx,
3105 array->indirect),
3106 "");
3107 }
3108 break;
3109 }
3110 case nir_deref_type_struct: {
3111 nir_deref_struct *deref_struct =
3112 nir_deref_as_struct(tail);
3113 offset = LLVMConstInt(ctx->ac.i32,
3114 deref_struct->index, 0);
3115 break;
3116 }
3117 default:
3118 unreachable("bad deref type");
3119 }
3120 val = ac_build_gep0(&ctx->ac, val, offset);
3121 tail = tail->child;
3122 }
3123 return val;
3124 }
3125
3126 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3127 nir_intrinsic_instr *instr,
3128 bool load_inputs)
3129 {
3130 LLVMValueRef result;
3131 LLVMValueRef vertex_index = NULL;
3132 LLVMValueRef indir_index = NULL;
3133 unsigned const_index = 0;
3134 unsigned location = instr->variables[0]->var->data.location;
3135 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3136 const bool is_patch = instr->variables[0]->var->data.patch;
3137 const bool is_compact = instr->variables[0]->var->data.compact;
3138
3139 get_deref_offset(ctx, instr->variables[0],
3140 false, NULL, is_patch ? NULL : &vertex_index,
3141 &const_index, &indir_index);
3142
3143 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3144 const_index, location, driver_location,
3145 instr->variables[0]->var->data.location_frac,
3146 instr->num_components,
3147 is_patch, is_compact, load_inputs);
3148 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3149 }
3150
3151 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3152 nir_intrinsic_instr *instr)
3153 {
3154 LLVMValueRef values[8];
3155 int idx = instr->variables[0]->var->data.driver_location;
3156 int ve = instr->dest.ssa.num_components;
3157 unsigned comp = instr->variables[0]->var->data.location_frac;
3158 LLVMValueRef indir_index;
3159 LLVMValueRef ret;
3160 unsigned const_index;
3161 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3162 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3163 instr->variables[0]->var->data.mode == nir_var_shader_in;
3164 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3165 &const_index, &indir_index);
3166
3167 if (instr->dest.ssa.bit_size == 64)
3168 ve *= 2;
3169
3170 switch (instr->variables[0]->var->data.mode) {
3171 case nir_var_shader_in:
3172 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3173 ctx->stage == MESA_SHADER_TESS_EVAL) {
3174 return load_tess_varyings(ctx, instr, true);
3175 }
3176
3177 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3178 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3179 LLVMValueRef indir_index;
3180 unsigned const_index, vertex_index;
3181 get_deref_offset(ctx, instr->variables[0],
3182 false, &vertex_index, NULL,
3183 &const_index, &indir_index);
3184
3185 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3186 instr->variables[0]->var->data.driver_location,
3187 instr->variables[0]->var->data.location_frac, ve,
3188 vertex_index, const_index, type);
3189 }
3190
3191 for (unsigned chan = comp; chan < ve + comp; chan++) {
3192 if (indir_index) {
3193 unsigned count = glsl_count_attribute_slots(
3194 instr->variables[0]->var->type,
3195 ctx->stage == MESA_SHADER_VERTEX);
3196 count -= chan / 4;
3197 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3198 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3199 stride, false, true);
3200
3201 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3202 tmp_vec,
3203 indir_index, "");
3204 } else
3205 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3206 }
3207 break;
3208 case nir_var_local:
3209 for (unsigned chan = 0; chan < ve; chan++) {
3210 if (indir_index) {
3211 unsigned count = glsl_count_attribute_slots(
3212 instr->variables[0]->var->type, false);
3213 count -= chan / 4;
3214 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3215 &ctx->ac, ctx->locals + idx + chan, count,
3216 stride, true, true);
3217
3218 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3219 tmp_vec,
3220 indir_index, "");
3221 } else {
3222 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3223 }
3224 }
3225 break;
3226 case nir_var_shared: {
3227 LLVMValueRef address = build_gep_for_deref(ctx,
3228 instr->variables[0]);
3229 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3230 return LLVMBuildBitCast(ctx->ac.builder, val,
3231 get_def_type(ctx, &instr->dest.ssa),
3232 "");
3233 }
3234 case nir_var_shader_out:
3235 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3236 return load_tess_varyings(ctx, instr, false);
3237 }
3238
3239 for (unsigned chan = comp; chan < ve + comp; chan++) {
3240 if (indir_index) {
3241 unsigned count = glsl_count_attribute_slots(
3242 instr->variables[0]->var->type, false);
3243 count -= chan / 4;
3244 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3245 &ctx->ac, ctx->outputs + idx + chan, count,
3246 stride, true, true);
3247
3248 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3249 tmp_vec,
3250 indir_index, "");
3251 } else {
3252 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3253 ctx->outputs[idx + chan + const_index * stride],
3254 "");
3255 }
3256 }
3257 break;
3258 default:
3259 unreachable("unhandle variable mode");
3260 }
3261 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3262 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3263 }
3264
3265 static void
3266 visit_store_var(struct ac_nir_context *ctx,
3267 nir_intrinsic_instr *instr)
3268 {
3269 LLVMValueRef temp_ptr, value;
3270 int idx = instr->variables[0]->var->data.driver_location;
3271 unsigned comp = instr->variables[0]->var->data.location_frac;
3272 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3273 int writemask = instr->const_index[0] << comp;
3274 LLVMValueRef indir_index;
3275 unsigned const_index;
3276 get_deref_offset(ctx, instr->variables[0], false,
3277 NULL, NULL, &const_index, &indir_index);
3278
3279 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3280
3281 src = LLVMBuildBitCast(ctx->ac.builder, src,
3282 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3283 "");
3284
3285 writemask = widen_mask(writemask, 2);
3286 }
3287
3288 switch (instr->variables[0]->var->data.mode) {
3289 case nir_var_shader_out:
3290
3291 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3292 LLVMValueRef vertex_index = NULL;
3293 LLVMValueRef indir_index = NULL;
3294 unsigned const_index = 0;
3295 const unsigned location = instr->variables[0]->var->data.location;
3296 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3297 const unsigned comp = instr->variables[0]->var->data.location_frac;
3298 const bool is_patch = instr->variables[0]->var->data.patch;
3299 const bool is_compact = instr->variables[0]->var->data.compact;
3300
3301 get_deref_offset(ctx, instr->variables[0],
3302 false, NULL, is_patch ? NULL : &vertex_index,
3303 &const_index, &indir_index);
3304
3305 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3306 const_index, location, driver_location,
3307 src, comp, is_patch, is_compact, writemask);
3308 return;
3309 }
3310
3311 for (unsigned chan = 0; chan < 8; chan++) {
3312 int stride = 4;
3313 if (!(writemask & (1 << chan)))
3314 continue;
3315
3316 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3317
3318 if (instr->variables[0]->var->data.compact)
3319 stride = 1;
3320 if (indir_index) {
3321 unsigned count = glsl_count_attribute_slots(
3322 instr->variables[0]->var->type, false);
3323 count -= chan / 4;
3324 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3325 &ctx->ac, ctx->outputs + idx + chan, count,
3326 stride, true, true);
3327
3328 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3329 value, indir_index, "");
3330 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3331 count, stride, tmp_vec);
3332
3333 } else {
3334 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3335
3336 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3337 }
3338 }
3339 break;
3340 case nir_var_local:
3341 for (unsigned chan = 0; chan < 8; chan++) {
3342 if (!(writemask & (1 << chan)))
3343 continue;
3344
3345 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3346 if (indir_index) {
3347 unsigned count = glsl_count_attribute_slots(
3348 instr->variables[0]->var->type, false);
3349 count -= chan / 4;
3350 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3351 &ctx->ac, ctx->locals + idx + chan, count,
3352 4, true, true);
3353
3354 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3355 value, indir_index, "");
3356 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3357 count, 4, tmp_vec);
3358 } else {
3359 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3360
3361 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3362 }
3363 }
3364 break;
3365 case nir_var_shared: {
3366 int writemask = instr->const_index[0];
3367 LLVMValueRef address = build_gep_for_deref(ctx,
3368 instr->variables[0]);
3369 LLVMValueRef val = get_src(ctx, instr->src[0]);
3370 unsigned components =
3371 glsl_get_vector_elements(
3372 nir_deref_tail(&instr->variables[0]->deref)->type);
3373 if (writemask == (1 << components) - 1) {
3374 val = LLVMBuildBitCast(
3375 ctx->ac.builder, val,
3376 LLVMGetElementType(LLVMTypeOf(address)), "");
3377 LLVMBuildStore(ctx->ac.builder, val, address);
3378 } else {
3379 for (unsigned chan = 0; chan < 4; chan++) {
3380 if (!(writemask & (1 << chan)))
3381 continue;
3382 LLVMValueRef ptr =
3383 LLVMBuildStructGEP(ctx->ac.builder,
3384 address, chan, "");
3385 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3386 chan);
3387 src = LLVMBuildBitCast(
3388 ctx->ac.builder, src,
3389 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3390 LLVMBuildStore(ctx->ac.builder, src, ptr);
3391 }
3392 }
3393 break;
3394 }
3395 default:
3396 break;
3397 }
3398 }
3399
3400 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3401 {
3402 switch (dim) {
3403 case GLSL_SAMPLER_DIM_BUF:
3404 return 1;
3405 case GLSL_SAMPLER_DIM_1D:
3406 return array ? 2 : 1;
3407 case GLSL_SAMPLER_DIM_2D:
3408 return array ? 3 : 2;
3409 case GLSL_SAMPLER_DIM_MS:
3410 return array ? 4 : 3;
3411 case GLSL_SAMPLER_DIM_3D:
3412 case GLSL_SAMPLER_DIM_CUBE:
3413 return 3;
3414 case GLSL_SAMPLER_DIM_RECT:
3415 case GLSL_SAMPLER_DIM_SUBPASS:
3416 return 2;
3417 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3418 return 3;
3419 default:
3420 break;
3421 }
3422 return 0;
3423 }
3424
3425
3426
3427 /* Adjust the sample index according to FMASK.
3428 *
3429 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3430 * which is the identity mapping. Each nibble says which physical sample
3431 * should be fetched to get that sample.
3432 *
3433 * For example, 0x11111100 means there are only 2 samples stored and
3434 * the second sample covers 3/4 of the pixel. When reading samples 0
3435 * and 1, return physical sample 0 (determined by the first two 0s
3436 * in FMASK), otherwise return physical sample 1.
3437 *
3438 * The sample index should be adjusted as follows:
3439 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3440 */
3441 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3442 LLVMValueRef coord_x, LLVMValueRef coord_y,
3443 LLVMValueRef coord_z,
3444 LLVMValueRef sample_index,
3445 LLVMValueRef fmask_desc_ptr)
3446 {
3447 LLVMValueRef fmask_load_address[4];
3448 LLVMValueRef res;
3449
3450 fmask_load_address[0] = coord_x;
3451 fmask_load_address[1] = coord_y;
3452 if (coord_z) {
3453 fmask_load_address[2] = coord_z;
3454 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3455 }
3456
3457 struct ac_image_args args = {0};
3458
3459 args.opcode = ac_image_load;
3460 args.da = coord_z ? true : false;
3461 args.resource = fmask_desc_ptr;
3462 args.dmask = 0xf;
3463 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3464
3465 res = ac_build_image_opcode(ctx, &args);
3466
3467 res = ac_to_integer(ctx, res);
3468 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3469 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3470
3471 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3472 res,
3473 ctx->i32_0, "");
3474
3475 LLVMValueRef sample_index4 =
3476 LLVMBuildMul(ctx->builder, sample_index, four, "");
3477 LLVMValueRef shifted_fmask =
3478 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3479 LLVMValueRef final_sample =
3480 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3481
3482 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3483 * resource descriptor is 0 (invalid),
3484 */
3485 LLVMValueRef fmask_desc =
3486 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3487 ctx->v8i32, "");
3488
3489 LLVMValueRef fmask_word1 =
3490 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3491 ctx->i32_1, "");
3492
3493 LLVMValueRef word1_is_nonzero =
3494 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3495 fmask_word1, ctx->i32_0, "");
3496
3497 /* Replace the MSAA sample index. */
3498 sample_index =
3499 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3500 final_sample, sample_index, "");
3501 return sample_index;
3502 }
3503
3504 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3505 const nir_intrinsic_instr *instr)
3506 {
3507 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3508
3509 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3510 LLVMValueRef coords[4];
3511 LLVMValueRef masks[] = {
3512 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3513 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3514 };
3515 LLVMValueRef res;
3516 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3517
3518 int count;
3519 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3520 bool is_array = glsl_sampler_type_is_array(type);
3521 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3522 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3523 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3524 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3525 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3526 count = image_type_to_components_count(dim, is_array);
3527
3528 if (is_ms) {
3529 LLVMValueRef fmask_load_address[3];
3530 int chan;
3531
3532 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3533 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3534 if (is_array)
3535 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3536 else
3537 fmask_load_address[2] = NULL;
3538 if (add_frag_pos) {
3539 for (chan = 0; chan < 2; ++chan)
3540 fmask_load_address[chan] =
3541 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3542 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3543 ctx->ac.i32, ""), "");
3544 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3545 }
3546 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3547 fmask_load_address[0],
3548 fmask_load_address[1],
3549 fmask_load_address[2],
3550 sample_index,
3551 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3552 }
3553 if (count == 1 && !gfx9_1d) {
3554 if (instr->src[0].ssa->num_components)
3555 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3556 else
3557 res = src0;
3558 } else {
3559 int chan;
3560 if (is_ms)
3561 count--;
3562 for (chan = 0; chan < count; ++chan) {
3563 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3564 }
3565 if (add_frag_pos) {
3566 for (chan = 0; chan < 2; ++chan)
3567 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3568 ctx->ac.i32, ""), "");
3569 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3570 count++;
3571 }
3572
3573 if (gfx9_1d) {
3574 if (is_array) {
3575 coords[2] = coords[1];
3576 coords[1] = ctx->ac.i32_0;
3577 } else
3578 coords[1] = ctx->ac.i32_0;
3579 count++;
3580 }
3581
3582 if (is_ms) {
3583 coords[count] = sample_index;
3584 count++;
3585 }
3586
3587 if (count == 3) {
3588 coords[3] = LLVMGetUndef(ctx->ac.i32);
3589 count = 4;
3590 }
3591 res = ac_build_gather_values(&ctx->ac, coords, count);
3592 }
3593 return res;
3594 }
3595
3596 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3597 const nir_intrinsic_instr *instr)
3598 {
3599 LLVMValueRef params[7];
3600 LLVMValueRef res;
3601 char intrinsic_name[64];
3602 const nir_variable *var = instr->variables[0]->var;
3603 const struct glsl_type *type = var->type;
3604
3605 if(instr->variables[0]->deref.child)
3606 type = instr->variables[0]->deref.child->type;
3607
3608 type = glsl_without_array(type);
3609
3610 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3611 if (dim == GLSL_SAMPLER_DIM_BUF) {
3612 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3613 unsigned num_channels = util_last_bit(mask);
3614 LLVMValueRef rsrc, vindex;
3615
3616 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3617 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3618 ctx->ac.i32_0, "");
3619
3620 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3621 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3622 ctx->ac.i32_0, num_channels,
3623 false, false);
3624 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3625
3626 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3627 res = ac_to_integer(&ctx->ac, res);
3628 } else {
3629 bool is_da = glsl_sampler_type_is_array(type) ||
3630 dim == GLSL_SAMPLER_DIM_CUBE ||
3631 dim == GLSL_SAMPLER_DIM_3D ||
3632 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3633 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3634 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3635 LLVMValueRef glc = ctx->ac.i1false;
3636 LLVMValueRef slc = ctx->ac.i1false;
3637
3638 params[0] = get_image_coords(ctx, instr);
3639 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3640 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3641 params[3] = glc;
3642 params[4] = slc;
3643 params[5] = ctx->ac.i1false;
3644 params[6] = da;
3645
3646 ac_get_image_intr_name("llvm.amdgcn.image.load",
3647 ctx->ac.v4f32, /* vdata */
3648 LLVMTypeOf(params[0]), /* coords */
3649 LLVMTypeOf(params[1]), /* rsrc */
3650 intrinsic_name, sizeof(intrinsic_name));
3651
3652 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3653 params, 7, AC_FUNC_ATTR_READONLY);
3654 }
3655 return ac_to_integer(&ctx->ac, res);
3656 }
3657
3658 static void visit_image_store(struct ac_nir_context *ctx,
3659 nir_intrinsic_instr *instr)
3660 {
3661 LLVMValueRef params[8];
3662 char intrinsic_name[64];
3663 const nir_variable *var = instr->variables[0]->var;
3664 const struct glsl_type *type = glsl_without_array(var->type);
3665 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3666 LLVMValueRef glc = ctx->ac.i1false;
3667 bool force_glc = ctx->ac.chip_class == SI;
3668 if (force_glc)
3669 glc = ctx->ac.i1true;
3670
3671 if (dim == GLSL_SAMPLER_DIM_BUF) {
3672 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3673 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3674 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3675 ctx->ac.i32_0, ""); /* vindex */
3676 params[3] = ctx->ac.i32_0; /* voffset */
3677 params[4] = glc; /* glc */
3678 params[5] = ctx->ac.i1false; /* slc */
3679 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3680 params, 6, 0);
3681 } else {
3682 bool is_da = glsl_sampler_type_is_array(type) ||
3683 dim == GLSL_SAMPLER_DIM_CUBE ||
3684 dim == GLSL_SAMPLER_DIM_3D;
3685 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3686 LLVMValueRef slc = ctx->ac.i1false;
3687
3688 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3689 params[1] = get_image_coords(ctx, instr); /* coords */
3690 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3691 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3692 params[4] = glc;
3693 params[5] = slc;
3694 params[6] = ctx->ac.i1false;
3695 params[7] = da;
3696
3697 ac_get_image_intr_name("llvm.amdgcn.image.store",
3698 LLVMTypeOf(params[0]), /* vdata */
3699 LLVMTypeOf(params[1]), /* coords */
3700 LLVMTypeOf(params[2]), /* rsrc */
3701 intrinsic_name, sizeof(intrinsic_name));
3702
3703 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3704 params, 8, 0);
3705 }
3706
3707 }
3708
3709 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3710 const nir_intrinsic_instr *instr)
3711 {
3712 LLVMValueRef params[7];
3713 int param_count = 0;
3714 const nir_variable *var = instr->variables[0]->var;
3715
3716 const char *atomic_name;
3717 char intrinsic_name[41];
3718 const struct glsl_type *type = glsl_without_array(var->type);
3719 MAYBE_UNUSED int length;
3720
3721 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3722
3723 switch (instr->intrinsic) {
3724 case nir_intrinsic_image_atomic_add:
3725 atomic_name = "add";
3726 break;
3727 case nir_intrinsic_image_atomic_min:
3728 atomic_name = is_unsigned ? "umin" : "smin";
3729 break;
3730 case nir_intrinsic_image_atomic_max:
3731 atomic_name = is_unsigned ? "umax" : "smax";
3732 break;
3733 case nir_intrinsic_image_atomic_and:
3734 atomic_name = "and";
3735 break;
3736 case nir_intrinsic_image_atomic_or:
3737 atomic_name = "or";
3738 break;
3739 case nir_intrinsic_image_atomic_xor:
3740 atomic_name = "xor";
3741 break;
3742 case nir_intrinsic_image_atomic_exchange:
3743 atomic_name = "swap";
3744 break;
3745 case nir_intrinsic_image_atomic_comp_swap:
3746 atomic_name = "cmpswap";
3747 break;
3748 default:
3749 abort();
3750 }
3751
3752 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3753 params[param_count++] = get_src(ctx, instr->src[3]);
3754 params[param_count++] = get_src(ctx, instr->src[2]);
3755
3756 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3757 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3758 NULL, true, true);
3759 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3760 ctx->ac.i32_0, ""); /* vindex */
3761 params[param_count++] = ctx->ac.i32_0; /* voffset */
3762 params[param_count++] = ctx->ac.i1false; /* slc */
3763
3764 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3765 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3766 } else {
3767 char coords_type[8];
3768
3769 bool da = glsl_sampler_type_is_array(type) ||
3770 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3771
3772 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3773 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3774 NULL, true, true);
3775 params[param_count++] = ctx->ac.i1false; /* r128 */
3776 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3777 params[param_count++] = ctx->ac.i1false; /* slc */
3778
3779 build_int_type_name(LLVMTypeOf(coords),
3780 coords_type, sizeof(coords_type));
3781
3782 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3783 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3784 }
3785
3786 assert(length < sizeof(intrinsic_name));
3787 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3788 }
3789
3790 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3791 const nir_intrinsic_instr *instr)
3792 {
3793 LLVMValueRef res;
3794 const nir_variable *var = instr->variables[0]->var;
3795 const struct glsl_type *type = instr->variables[0]->var->type;
3796 bool da = glsl_sampler_type_is_array(var->type) ||
3797 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3798 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3799 if(instr->variables[0]->deref.child)
3800 type = instr->variables[0]->deref.child->type;
3801
3802 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3803 return get_buffer_size(ctx,
3804 get_sampler_desc(ctx, instr->variables[0],
3805 AC_DESC_BUFFER, NULL, true, false), true);
3806
3807 struct ac_image_args args = { 0 };
3808
3809 args.da = da;
3810 args.dmask = 0xf;
3811 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3812 args.opcode = ac_image_get_resinfo;
3813 args.addr = ctx->ac.i32_0;
3814
3815 res = ac_build_image_opcode(&ctx->ac, &args);
3816
3817 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3818
3819 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3820 glsl_sampler_type_is_array(type)) {
3821 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3822 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3823 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3824 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3825 }
3826 if (ctx->ac.chip_class >= GFX9 &&
3827 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3828 glsl_sampler_type_is_array(type)) {
3829 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3830 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3831 ctx->ac.i32_1, "");
3832
3833 }
3834 return res;
3835 }
3836
3837 #define NOOP_WAITCNT 0xf7f
3838 #define LGKM_CNT 0x07f
3839 #define VM_CNT 0xf70
3840
3841 static void emit_membar(struct nir_to_llvm_context *ctx,
3842 const nir_intrinsic_instr *instr)
3843 {
3844 unsigned waitcnt = NOOP_WAITCNT;
3845
3846 switch (instr->intrinsic) {
3847 case nir_intrinsic_memory_barrier:
3848 case nir_intrinsic_group_memory_barrier:
3849 waitcnt &= VM_CNT & LGKM_CNT;
3850 break;
3851 case nir_intrinsic_memory_barrier_atomic_counter:
3852 case nir_intrinsic_memory_barrier_buffer:
3853 case nir_intrinsic_memory_barrier_image:
3854 waitcnt &= VM_CNT;
3855 break;
3856 case nir_intrinsic_memory_barrier_shared:
3857 waitcnt &= LGKM_CNT;
3858 break;
3859 default:
3860 break;
3861 }
3862 if (waitcnt != NOOP_WAITCNT)
3863 ac_build_waitcnt(&ctx->ac, waitcnt);
3864 }
3865
3866 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3867 {
3868 /* SI only (thanks to a hw bug workaround):
3869 * The real barrier instruction isn’t needed, because an entire patch
3870 * always fits into a single wave.
3871 */
3872 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3873 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3874 return;
3875 }
3876 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3877 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3878 }
3879
3880 static void emit_discard(struct ac_nir_context *ctx,
3881 const nir_intrinsic_instr *instr)
3882 {
3883 LLVMValueRef cond;
3884
3885 if (instr->intrinsic == nir_intrinsic_discard_if) {
3886 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3887 get_src(ctx, instr->src[0]),
3888 ctx->ac.i32_0, "");
3889 } else {
3890 assert(instr->intrinsic == nir_intrinsic_discard);
3891 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3892 }
3893
3894 ac_build_kill_if_false(&ctx->ac, cond);
3895 }
3896
3897 static LLVMValueRef
3898 visit_load_helper_invocation(struct ac_nir_context *ctx)
3899 {
3900 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3901 "llvm.amdgcn.ps.live",
3902 ctx->ac.i1, NULL, 0,
3903 AC_FUNC_ATTR_READNONE);
3904 result = LLVMBuildNot(ctx->ac.builder, result, "");
3905 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3906 }
3907
3908 static LLVMValueRef
3909 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3910 {
3911 LLVMValueRef result;
3912 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3913 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3914 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3915
3916 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3917 }
3918
3919 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3920 const nir_intrinsic_instr *instr)
3921 {
3922 LLVMValueRef ptr, result;
3923 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3924 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3925
3926 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3927 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3928 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3929 ptr, src, src1,
3930 LLVMAtomicOrderingSequentiallyConsistent,
3931 LLVMAtomicOrderingSequentiallyConsistent,
3932 false);
3933 } else {
3934 LLVMAtomicRMWBinOp op;
3935 switch (instr->intrinsic) {
3936 case nir_intrinsic_var_atomic_add:
3937 op = LLVMAtomicRMWBinOpAdd;
3938 break;
3939 case nir_intrinsic_var_atomic_umin:
3940 op = LLVMAtomicRMWBinOpUMin;
3941 break;
3942 case nir_intrinsic_var_atomic_umax:
3943 op = LLVMAtomicRMWBinOpUMax;
3944 break;
3945 case nir_intrinsic_var_atomic_imin:
3946 op = LLVMAtomicRMWBinOpMin;
3947 break;
3948 case nir_intrinsic_var_atomic_imax:
3949 op = LLVMAtomicRMWBinOpMax;
3950 break;
3951 case nir_intrinsic_var_atomic_and:
3952 op = LLVMAtomicRMWBinOpAnd;
3953 break;
3954 case nir_intrinsic_var_atomic_or:
3955 op = LLVMAtomicRMWBinOpOr;
3956 break;
3957 case nir_intrinsic_var_atomic_xor:
3958 op = LLVMAtomicRMWBinOpXor;
3959 break;
3960 case nir_intrinsic_var_atomic_exchange:
3961 op = LLVMAtomicRMWBinOpXchg;
3962 break;
3963 default:
3964 return NULL;
3965 }
3966
3967 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3968 LLVMAtomicOrderingSequentiallyConsistent,
3969 false);
3970 }
3971 return result;
3972 }
3973
3974 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3975 enum glsl_interp_mode interp, unsigned location)
3976 {
3977 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3978
3979 switch (interp) {
3980 case INTERP_MODE_FLAT:
3981 default:
3982 return NULL;
3983 case INTERP_MODE_SMOOTH:
3984 case INTERP_MODE_NONE:
3985 if (location == INTERP_CENTER)
3986 return ctx->persp_center;
3987 else if (location == INTERP_CENTROID)
3988 return ctx->persp_centroid;
3989 else if (location == INTERP_SAMPLE)
3990 return ctx->persp_sample;
3991 break;
3992 case INTERP_MODE_NOPERSPECTIVE:
3993 if (location == INTERP_CENTER)
3994 return ctx->linear_center;
3995 else if (location == INTERP_CENTROID)
3996 return ctx->linear_centroid;
3997 else if (location == INTERP_SAMPLE)
3998 return ctx->linear_sample;
3999 break;
4000 }
4001 return NULL;
4002 }
4003
4004 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4005 LLVMValueRef sample_id)
4006 {
4007 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4008
4009 LLVMValueRef result;
4010 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4011
4012 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4013 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4014
4015 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4016 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4017
4018 return result;
4019 }
4020
4021 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4022 {
4023 LLVMValueRef values[2];
4024
4025 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4026 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4027 return ac_build_gather_values(&ctx->ac, values, 2);
4028 }
4029
4030 static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
4031 {
4032 uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? ctx->nctx->options->key.fs.log2_num_samples : ctx->nctx->options->key.fs.log2_ps_iter_samples;
4033
4034 /* The bit pattern matches that used by fixed function fragment
4035 * processing. */
4036 static const uint16_t ps_iter_masks[] = {
4037 0xffff, /* not used */
4038 0x5555,
4039 0x1111,
4040 0x0101,
4041 0x0001,
4042 };
4043 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4044
4045 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4046
4047 LLVMValueRef result, sample_id;
4048 sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4049 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4050 result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, "");
4051 return result;
4052 }
4053
4054 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4055 const nir_intrinsic_instr *instr)
4056 {
4057 LLVMValueRef result[4];
4058 LLVMValueRef interp_param, attr_number;
4059 unsigned location;
4060 unsigned chan;
4061 LLVMValueRef src_c0 = NULL;
4062 LLVMValueRef src_c1 = NULL;
4063 LLVMValueRef src0 = NULL;
4064 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4065 switch (instr->intrinsic) {
4066 case nir_intrinsic_interp_var_at_centroid:
4067 location = INTERP_CENTROID;
4068 break;
4069 case nir_intrinsic_interp_var_at_sample:
4070 case nir_intrinsic_interp_var_at_offset:
4071 location = INTERP_CENTER;
4072 src0 = get_src(ctx, instr->src[0]);
4073 break;
4074 default:
4075 break;
4076 }
4077
4078 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4079 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4080 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4081 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4082 LLVMValueRef sample_position;
4083 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4084
4085 /* fetch sample ID */
4086 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4087
4088 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4089 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4090 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4091 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4092 }
4093 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4094 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4095
4096 if (location == INTERP_CENTER) {
4097 LLVMValueRef ij_out[2];
4098 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4099
4100 /*
4101 * take the I then J parameters, and the DDX/Y for it, and
4102 * calculate the IJ inputs for the interpolator.
4103 * temp1 = ddx * offset/sample.x + I;
4104 * interp_param.I = ddy * offset/sample.y + temp1;
4105 * temp1 = ddx * offset/sample.x + J;
4106 * interp_param.J = ddy * offset/sample.y + temp1;
4107 */
4108 for (unsigned i = 0; i < 2; i++) {
4109 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4110 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4111 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4112 ddxy_out, ix_ll, "");
4113 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4114 ddxy_out, iy_ll, "");
4115 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4116 interp_param, ix_ll, "");
4117 LLVMValueRef temp1, temp2;
4118
4119 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4120 ctx->ac.f32, "");
4121
4122 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4123 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4124
4125 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4126 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4127
4128 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4129 temp2, ctx->ac.i32, "");
4130 }
4131 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4132
4133 }
4134
4135 for (chan = 0; chan < 4; chan++) {
4136 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4137
4138 if (interp_param) {
4139 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4140 interp_param, ctx->ac.v2f32, "");
4141 LLVMValueRef i = LLVMBuildExtractElement(
4142 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4143 LLVMValueRef j = LLVMBuildExtractElement(
4144 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4145
4146 result[chan] = ac_build_fs_interp(&ctx->ac,
4147 llvm_chan, attr_number,
4148 ctx->abi->prim_mask, i, j);
4149 } else {
4150 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4151 LLVMConstInt(ctx->ac.i32, 2, false),
4152 llvm_chan, attr_number,
4153 ctx->abi->prim_mask);
4154 }
4155 }
4156 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4157 instr->variables[0]->var->data.location_frac);
4158 }
4159
4160 static void
4161 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4162 {
4163 LLVMValueRef gs_next_vertex;
4164 LLVMValueRef can_emit;
4165 int idx;
4166 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4167
4168 assert(stream == 0);
4169
4170 /* Write vertex attribute values to GSVS ring */
4171 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4172 ctx->gs_next_vertex,
4173 "");
4174
4175 /* If this thread has already emitted the declared maximum number of
4176 * vertices, kill it: excessive vertex emissions are not supposed to
4177 * have any effect, and GS threads have no externally observable
4178 * effects other than emitting vertices.
4179 */
4180 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4181 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4182 ac_build_kill_if_false(&ctx->ac, can_emit);
4183
4184 /* loop num outputs */
4185 idx = 0;
4186 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4187 LLVMValueRef *out_ptr = &addrs[i * 4];
4188 int length = 4;
4189 int slot = idx;
4190 int slot_inc = 1;
4191
4192 if (!(ctx->output_mask & (1ull << i)))
4193 continue;
4194
4195 if (i == VARYING_SLOT_CLIP_DIST0) {
4196 /* pack clip and cull into a single set of slots */
4197 length = ctx->num_output_clips + ctx->num_output_culls;
4198 if (length > 4)
4199 slot_inc = 2;
4200 }
4201 for (unsigned j = 0; j < length; j++) {
4202 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4203 out_ptr[j], "");
4204 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4205 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4206 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4207
4208 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4209
4210 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4211 out_val, 1,
4212 voffset, ctx->gs2vs_offset, 0,
4213 1, 1, true, true);
4214 }
4215 idx += slot_inc;
4216 }
4217
4218 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4219 ctx->ac.i32_1, "");
4220 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4221
4222 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4223 }
4224
4225 static void
4226 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4227 {
4228 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4229 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4230 }
4231
4232 static LLVMValueRef
4233 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4234 unsigned num_components)
4235 {
4236 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4237
4238 LLVMValueRef coord[4] = {
4239 ctx->tes_u,
4240 ctx->tes_v,
4241 ctx->ac.f32_0,
4242 ctx->ac.f32_0,
4243 };
4244
4245 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4246 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4247 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4248
4249 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4250 return LLVMBuildBitCast(ctx->builder, result, type, "");
4251 }
4252
4253 static LLVMValueRef
4254 load_patch_vertices_in(struct ac_shader_abi *abi)
4255 {
4256 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4257 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4258 }
4259
4260 static void visit_intrinsic(struct ac_nir_context *ctx,
4261 nir_intrinsic_instr *instr)
4262 {
4263 LLVMValueRef result = NULL;
4264
4265 switch (instr->intrinsic) {
4266 case nir_intrinsic_ballot:
4267 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4268 break;
4269 case nir_intrinsic_read_invocation:
4270 case nir_intrinsic_read_first_invocation: {
4271 LLVMValueRef args[2];
4272
4273 /* Value */
4274 args[0] = get_src(ctx, instr->src[0]);
4275
4276 unsigned num_args;
4277 const char *intr_name;
4278 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4279 num_args = 2;
4280 intr_name = "llvm.amdgcn.readlane";
4281
4282 /* Invocation */
4283 args[1] = get_src(ctx, instr->src[1]);
4284 } else {
4285 num_args = 1;
4286 intr_name = "llvm.amdgcn.readfirstlane";
4287 }
4288
4289 /* We currently have no other way to prevent LLVM from lifting the icmp
4290 * calls to a dominating basic block.
4291 */
4292 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4293
4294 result = ac_build_intrinsic(&ctx->ac, intr_name,
4295 ctx->ac.i32, args, num_args,
4296 AC_FUNC_ATTR_READNONE |
4297 AC_FUNC_ATTR_CONVERGENT);
4298 break;
4299 }
4300 case nir_intrinsic_load_subgroup_invocation:
4301 result = ac_get_thread_id(&ctx->ac);
4302 break;
4303 case nir_intrinsic_load_work_group_id: {
4304 LLVMValueRef values[3];
4305
4306 for (int i = 0; i < 3; i++) {
4307 values[i] = ctx->nctx->workgroup_ids[i] ?
4308 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4309 }
4310
4311 result = ac_build_gather_values(&ctx->ac, values, 3);
4312 break;
4313 }
4314 case nir_intrinsic_load_base_vertex: {
4315 result = ctx->abi->base_vertex;
4316 break;
4317 }
4318 case nir_intrinsic_load_vertex_id_zero_base: {
4319 result = ctx->abi->vertex_id;
4320 break;
4321 }
4322 case nir_intrinsic_load_local_invocation_id: {
4323 result = ctx->nctx->local_invocation_ids;
4324 break;
4325 }
4326 case nir_intrinsic_load_base_instance:
4327 result = ctx->abi->start_instance;
4328 break;
4329 case nir_intrinsic_load_draw_id:
4330 result = ctx->abi->draw_id;
4331 break;
4332 case nir_intrinsic_load_view_index:
4333 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4334 break;
4335 case nir_intrinsic_load_invocation_id:
4336 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4337 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4338 else
4339 result = ctx->abi->gs_invocation_id;
4340 break;
4341 case nir_intrinsic_load_primitive_id:
4342 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4343 result = ctx->abi->gs_prim_id;
4344 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4345 result = ctx->abi->tcs_patch_id;
4346 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4347 result = ctx->abi->tes_patch_id;
4348 } else
4349 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4350 break;
4351 case nir_intrinsic_load_sample_id:
4352 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4353 break;
4354 case nir_intrinsic_load_sample_pos:
4355 result = load_sample_pos(ctx);
4356 break;
4357 case nir_intrinsic_load_sample_mask_in:
4358 if (ctx->nctx)
4359 result = load_sample_mask_in(ctx);
4360 else
4361 result = ctx->abi->sample_coverage;
4362 break;
4363 case nir_intrinsic_load_frag_coord: {
4364 LLVMValueRef values[4] = {
4365 ctx->abi->frag_pos[0],
4366 ctx->abi->frag_pos[1],
4367 ctx->abi->frag_pos[2],
4368 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4369 };
4370 result = ac_build_gather_values(&ctx->ac, values, 4);
4371 break;
4372 }
4373 case nir_intrinsic_load_front_face:
4374 result = ctx->abi->front_face;
4375 break;
4376 case nir_intrinsic_load_helper_invocation:
4377 result = visit_load_helper_invocation(ctx);
4378 break;
4379 case nir_intrinsic_load_instance_id:
4380 result = ctx->abi->instance_id;
4381 break;
4382 case nir_intrinsic_load_num_work_groups:
4383 result = ctx->nctx->num_work_groups;
4384 break;
4385 case nir_intrinsic_load_local_invocation_index:
4386 result = visit_load_local_invocation_index(ctx->nctx);
4387 break;
4388 case nir_intrinsic_load_push_constant:
4389 result = visit_load_push_constant(ctx->nctx, instr);
4390 break;
4391 case nir_intrinsic_vulkan_resource_index:
4392 result = visit_vulkan_resource_index(ctx->nctx, instr);
4393 break;
4394 case nir_intrinsic_vulkan_resource_reindex:
4395 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4396 break;
4397 case nir_intrinsic_store_ssbo:
4398 visit_store_ssbo(ctx, instr);
4399 break;
4400 case nir_intrinsic_load_ssbo:
4401 result = visit_load_buffer(ctx, instr);
4402 break;
4403 case nir_intrinsic_ssbo_atomic_add:
4404 case nir_intrinsic_ssbo_atomic_imin:
4405 case nir_intrinsic_ssbo_atomic_umin:
4406 case nir_intrinsic_ssbo_atomic_imax:
4407 case nir_intrinsic_ssbo_atomic_umax:
4408 case nir_intrinsic_ssbo_atomic_and:
4409 case nir_intrinsic_ssbo_atomic_or:
4410 case nir_intrinsic_ssbo_atomic_xor:
4411 case nir_intrinsic_ssbo_atomic_exchange:
4412 case nir_intrinsic_ssbo_atomic_comp_swap:
4413 result = visit_atomic_ssbo(ctx, instr);
4414 break;
4415 case nir_intrinsic_load_ubo:
4416 result = visit_load_ubo_buffer(ctx, instr);
4417 break;
4418 case nir_intrinsic_get_buffer_size:
4419 result = visit_get_buffer_size(ctx, instr);
4420 break;
4421 case nir_intrinsic_load_var:
4422 result = visit_load_var(ctx, instr);
4423 break;
4424 case nir_intrinsic_store_var:
4425 visit_store_var(ctx, instr);
4426 break;
4427 case nir_intrinsic_image_load:
4428 result = visit_image_load(ctx, instr);
4429 break;
4430 case nir_intrinsic_image_store:
4431 visit_image_store(ctx, instr);
4432 break;
4433 case nir_intrinsic_image_atomic_add:
4434 case nir_intrinsic_image_atomic_min:
4435 case nir_intrinsic_image_atomic_max:
4436 case nir_intrinsic_image_atomic_and:
4437 case nir_intrinsic_image_atomic_or:
4438 case nir_intrinsic_image_atomic_xor:
4439 case nir_intrinsic_image_atomic_exchange:
4440 case nir_intrinsic_image_atomic_comp_swap:
4441 result = visit_image_atomic(ctx, instr);
4442 break;
4443 case nir_intrinsic_image_size:
4444 result = visit_image_size(ctx, instr);
4445 break;
4446 case nir_intrinsic_discard:
4447 case nir_intrinsic_discard_if:
4448 emit_discard(ctx, instr);
4449 break;
4450 case nir_intrinsic_memory_barrier:
4451 case nir_intrinsic_group_memory_barrier:
4452 case nir_intrinsic_memory_barrier_atomic_counter:
4453 case nir_intrinsic_memory_barrier_buffer:
4454 case nir_intrinsic_memory_barrier_image:
4455 case nir_intrinsic_memory_barrier_shared:
4456 emit_membar(ctx->nctx, instr);
4457 break;
4458 case nir_intrinsic_barrier:
4459 emit_barrier(&ctx->ac, ctx->stage);
4460 break;
4461 case nir_intrinsic_var_atomic_add:
4462 case nir_intrinsic_var_atomic_imin:
4463 case nir_intrinsic_var_atomic_umin:
4464 case nir_intrinsic_var_atomic_imax:
4465 case nir_intrinsic_var_atomic_umax:
4466 case nir_intrinsic_var_atomic_and:
4467 case nir_intrinsic_var_atomic_or:
4468 case nir_intrinsic_var_atomic_xor:
4469 case nir_intrinsic_var_atomic_exchange:
4470 case nir_intrinsic_var_atomic_comp_swap:
4471 result = visit_var_atomic(ctx->nctx, instr);
4472 break;
4473 case nir_intrinsic_interp_var_at_centroid:
4474 case nir_intrinsic_interp_var_at_sample:
4475 case nir_intrinsic_interp_var_at_offset:
4476 result = visit_interp(ctx, instr);
4477 break;
4478 case nir_intrinsic_emit_vertex:
4479 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4480 break;
4481 case nir_intrinsic_end_primitive:
4482 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4483 break;
4484 case nir_intrinsic_load_tess_coord: {
4485 LLVMTypeRef type = ctx->nctx ?
4486 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4487 NULL;
4488 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4489 break;
4490 }
4491 case nir_intrinsic_load_tess_level_outer:
4492 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4493 break;
4494 case nir_intrinsic_load_tess_level_inner:
4495 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4496 break;
4497 case nir_intrinsic_load_patch_vertices_in:
4498 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4499 break;
4500 case nir_intrinsic_vote_all: {
4501 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4502 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4503 break;
4504 }
4505 case nir_intrinsic_vote_any: {
4506 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4507 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4508 break;
4509 }
4510 case nir_intrinsic_vote_eq: {
4511 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4512 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4513 break;
4514 }
4515 default:
4516 fprintf(stderr, "Unknown intrinsic: ");
4517 nir_print_instr(&instr->instr, stderr);
4518 fprintf(stderr, "\n");
4519 break;
4520 }
4521 if (result) {
4522 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4523 }
4524 }
4525
4526 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4527 LLVMValueRef buffer_ptr, bool write)
4528 {
4529 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4530 LLVMValueRef result;
4531
4532 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4533
4534 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4535 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4536
4537 return result;
4538 }
4539
4540 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4541 {
4542 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4543 LLVMValueRef result;
4544
4545 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4546
4547 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4548 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4549
4550 return result;
4551 }
4552
4553 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4554 unsigned descriptor_set,
4555 unsigned base_index,
4556 unsigned constant_index,
4557 LLVMValueRef index,
4558 enum ac_descriptor_type desc_type,
4559 bool image, bool write)
4560 {
4561 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4562 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4563 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4564 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4565 unsigned offset = binding->offset;
4566 unsigned stride = binding->size;
4567 unsigned type_size;
4568 LLVMBuilderRef builder = ctx->builder;
4569 LLVMTypeRef type;
4570
4571 assert(base_index < layout->binding_count);
4572
4573 switch (desc_type) {
4574 case AC_DESC_IMAGE:
4575 type = ctx->ac.v8i32;
4576 type_size = 32;
4577 break;
4578 case AC_DESC_FMASK:
4579 type = ctx->ac.v8i32;
4580 offset += 32;
4581 type_size = 32;
4582 break;
4583 case AC_DESC_SAMPLER:
4584 type = ctx->ac.v4i32;
4585 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4586 offset += 64;
4587
4588 type_size = 16;
4589 break;
4590 case AC_DESC_BUFFER:
4591 type = ctx->ac.v4i32;
4592 type_size = 16;
4593 break;
4594 default:
4595 unreachable("invalid desc_type\n");
4596 }
4597
4598 offset += constant_index * stride;
4599
4600 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4601 (!index || binding->immutable_samplers_equal)) {
4602 if (binding->immutable_samplers_equal)
4603 constant_index = 0;
4604
4605 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4606
4607 LLVMValueRef constants[] = {
4608 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4609 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4610 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4611 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4612 };
4613 return ac_build_gather_values(&ctx->ac, constants, 4);
4614 }
4615
4616 assert(stride % type_size == 0);
4617
4618 if (!index)
4619 index = ctx->ac.i32_0;
4620
4621 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4622
4623 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4624 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4625
4626 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4627 }
4628
4629 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4630 const nir_deref_var *deref,
4631 enum ac_descriptor_type desc_type,
4632 const nir_tex_instr *tex_instr,
4633 bool image, bool write)
4634 {
4635 LLVMValueRef index = NULL;
4636 unsigned constant_index = 0;
4637 unsigned descriptor_set;
4638 unsigned base_index;
4639
4640 if (!deref) {
4641 assert(tex_instr && !image);
4642 descriptor_set = 0;
4643 base_index = tex_instr->sampler_index;
4644 } else {
4645 const nir_deref *tail = &deref->deref;
4646 while (tail->child) {
4647 const nir_deref_array *child = nir_deref_as_array(tail->child);
4648 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4649
4650 if (!array_size)
4651 array_size = 1;
4652
4653 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4654
4655 if (child->deref_array_type == nir_deref_array_type_indirect) {
4656 LLVMValueRef indirect = get_src(ctx, child->indirect);
4657
4658 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4659 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4660
4661 if (!index)
4662 index = indirect;
4663 else
4664 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4665 }
4666
4667 constant_index += child->base_offset * array_size;
4668
4669 tail = &child->deref;
4670 }
4671 descriptor_set = deref->var->data.descriptor_set;
4672 base_index = deref->var->data.binding;
4673 }
4674
4675 return ctx->abi->load_sampler_desc(ctx->abi,
4676 descriptor_set,
4677 base_index,
4678 constant_index, index,
4679 desc_type, image, write);
4680 }
4681
4682 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4683 struct ac_image_args *args,
4684 const nir_tex_instr *instr,
4685 nir_texop op,
4686 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4687 LLVMValueRef *param, unsigned count,
4688 unsigned dmask)
4689 {
4690 unsigned is_rect = 0;
4691 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4692
4693 if (op == nir_texop_lod)
4694 da = false;
4695 /* Pad to power of two vector */
4696 while (count < util_next_power_of_two(count))
4697 param[count++] = LLVMGetUndef(ctx->i32);
4698
4699 if (count > 1)
4700 args->addr = ac_build_gather_values(ctx, param, count);
4701 else
4702 args->addr = param[0];
4703
4704 args->resource = res_ptr;
4705 args->sampler = samp_ptr;
4706
4707 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4708 args->addr = param[0];
4709 return;
4710 }
4711
4712 args->dmask = dmask;
4713 args->unorm = is_rect;
4714 args->da = da;
4715 }
4716
4717 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4718 *
4719 * SI-CI:
4720 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4721 * filtering manually. The driver sets img7 to a mask clearing
4722 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4723 * s_and_b32 samp0, samp0, img7
4724 *
4725 * VI:
4726 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4727 */
4728 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4729 LLVMValueRef res, LLVMValueRef samp)
4730 {
4731 LLVMBuilderRef builder = ctx->ac.builder;
4732 LLVMValueRef img7, samp0;
4733
4734 if (ctx->ac.chip_class >= VI)
4735 return samp;
4736
4737 img7 = LLVMBuildExtractElement(builder, res,
4738 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4739 samp0 = LLVMBuildExtractElement(builder, samp,
4740 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4741 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4742 return LLVMBuildInsertElement(builder, samp, samp0,
4743 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4744 }
4745
4746 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4747 nir_tex_instr *instr,
4748 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4749 LLVMValueRef *fmask_ptr)
4750 {
4751 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4752 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4753 else
4754 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4755 if (samp_ptr) {
4756 if (instr->sampler)
4757 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4758 else
4759 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4760 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4761 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4762 }
4763 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4764 instr->op == nir_texop_samples_identical))
4765 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4766 }
4767
4768 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4769 LLVMValueRef coord)
4770 {
4771 coord = ac_to_float(ctx, coord);
4772 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4773 coord = ac_to_integer(ctx, coord);
4774 return coord;
4775 }
4776
4777 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4778 {
4779 LLVMValueRef result = NULL;
4780 struct ac_image_args args = { 0 };
4781 unsigned dmask = 0xf;
4782 LLVMValueRef address[16];
4783 LLVMValueRef coords[5];
4784 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4785 LLVMValueRef bias = NULL, offsets = NULL;
4786 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4787 LLVMValueRef ddx = NULL, ddy = NULL;
4788 LLVMValueRef derivs[6];
4789 unsigned chan, count = 0;
4790 unsigned const_src = 0, num_deriv_comp = 0;
4791 bool lod_is_zero = false;
4792
4793 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4794
4795 for (unsigned i = 0; i < instr->num_srcs; i++) {
4796 switch (instr->src[i].src_type) {
4797 case nir_tex_src_coord:
4798 coord = get_src(ctx, instr->src[i].src);
4799 break;
4800 case nir_tex_src_projector:
4801 break;
4802 case nir_tex_src_comparator:
4803 comparator = get_src(ctx, instr->src[i].src);
4804 break;
4805 case nir_tex_src_offset:
4806 offsets = get_src(ctx, instr->src[i].src);
4807 const_src = i;
4808 break;
4809 case nir_tex_src_bias:
4810 bias = get_src(ctx, instr->src[i].src);
4811 break;
4812 case nir_tex_src_lod: {
4813 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4814
4815 if (val && val->i32[0] == 0)
4816 lod_is_zero = true;
4817 lod = get_src(ctx, instr->src[i].src);
4818 break;
4819 }
4820 case nir_tex_src_ms_index:
4821 sample_index = get_src(ctx, instr->src[i].src);
4822 break;
4823 case nir_tex_src_ms_mcs:
4824 break;
4825 case nir_tex_src_ddx:
4826 ddx = get_src(ctx, instr->src[i].src);
4827 num_deriv_comp = instr->src[i].src.ssa->num_components;
4828 break;
4829 case nir_tex_src_ddy:
4830 ddy = get_src(ctx, instr->src[i].src);
4831 break;
4832 case nir_tex_src_texture_offset:
4833 case nir_tex_src_sampler_offset:
4834 case nir_tex_src_plane:
4835 default:
4836 break;
4837 }
4838 }
4839
4840 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4841 result = get_buffer_size(ctx, res_ptr, true);
4842 goto write_result;
4843 }
4844
4845 if (instr->op == nir_texop_texture_samples) {
4846 LLVMValueRef res, samples, is_msaa;
4847 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4848 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4849 LLVMConstInt(ctx->ac.i32, 3, false), "");
4850 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4851 LLVMConstInt(ctx->ac.i32, 28, false), "");
4852 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4853 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4854 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4855 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4856
4857 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4858 LLVMConstInt(ctx->ac.i32, 16, false), "");
4859 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4860 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4861 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4862 samples, "");
4863 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4864 ctx->ac.i32_1, "");
4865 result = samples;
4866 goto write_result;
4867 }
4868
4869 if (coord)
4870 for (chan = 0; chan < instr->coord_components; chan++)
4871 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4872
4873 if (offsets && instr->op != nir_texop_txf) {
4874 LLVMValueRef offset[3], pack;
4875 for (chan = 0; chan < 3; ++chan)
4876 offset[chan] = ctx->ac.i32_0;
4877
4878 args.offset = true;
4879 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4880 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4881 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4882 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4883 if (chan)
4884 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4885 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4886 }
4887 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4888 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4889 address[count++] = pack;
4890
4891 }
4892 /* pack LOD bias value */
4893 if (instr->op == nir_texop_txb && bias) {
4894 address[count++] = bias;
4895 }
4896
4897 /* Pack depth comparison value */
4898 if (instr->is_shadow && comparator) {
4899 LLVMValueRef z = ac_to_float(&ctx->ac,
4900 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4901
4902 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4903 * so the depth comparison value isn't clamped for Z16 and
4904 * Z24 anymore. Do it manually here.
4905 *
4906 * It's unnecessary if the original texture format was
4907 * Z32_FLOAT, but we don't know that here.
4908 */
4909 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4910 z = ac_build_clamp(&ctx->ac, z);
4911
4912 address[count++] = z;
4913 }
4914
4915 /* pack derivatives */
4916 if (ddx || ddy) {
4917 int num_src_deriv_channels, num_dest_deriv_channels;
4918 switch (instr->sampler_dim) {
4919 case GLSL_SAMPLER_DIM_3D:
4920 case GLSL_SAMPLER_DIM_CUBE:
4921 num_deriv_comp = 3;
4922 num_src_deriv_channels = 3;
4923 num_dest_deriv_channels = 3;
4924 break;
4925 case GLSL_SAMPLER_DIM_2D:
4926 default:
4927 num_src_deriv_channels = 2;
4928 num_dest_deriv_channels = 2;
4929 num_deriv_comp = 2;
4930 break;
4931 case GLSL_SAMPLER_DIM_1D:
4932 num_src_deriv_channels = 1;
4933 if (ctx->ac.chip_class >= GFX9) {
4934 num_dest_deriv_channels = 2;
4935 num_deriv_comp = 2;
4936 } else {
4937 num_dest_deriv_channels = 1;
4938 num_deriv_comp = 1;
4939 }
4940 break;
4941 }
4942
4943 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4944 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4945 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4946 }
4947 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4948 derivs[i] = ctx->ac.f32_0;
4949 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4950 }
4951 }
4952
4953 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4954 for (chan = 0; chan < instr->coord_components; chan++)
4955 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4956 if (instr->coord_components == 3)
4957 coords[3] = LLVMGetUndef(ctx->ac.f32);
4958 ac_prepare_cube_coords(&ctx->ac,
4959 instr->op == nir_texop_txd, instr->is_array,
4960 instr->op == nir_texop_lod, coords, derivs);
4961 if (num_deriv_comp)
4962 num_deriv_comp--;
4963 }
4964
4965 if (ddx || ddy) {
4966 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4967 address[count++] = derivs[i];
4968 }
4969
4970 /* Pack texture coordinates */
4971 if (coord) {
4972 address[count++] = coords[0];
4973 if (instr->coord_components > 1) {
4974 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4975 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4976 }
4977 address[count++] = coords[1];
4978 }
4979 if (instr->coord_components > 2) {
4980 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4981 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4982 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4983 instr->op != nir_texop_txf) {
4984 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4985 }
4986 address[count++] = coords[2];
4987 }
4988
4989 if (ctx->ac.chip_class >= GFX9) {
4990 LLVMValueRef filler;
4991 if (instr->op == nir_texop_txf)
4992 filler = ctx->ac.i32_0;
4993 else
4994 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4995
4996 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4997 /* No nir_texop_lod, because it does not take a slice
4998 * even with array textures. */
4999 if (instr->is_array && instr->op != nir_texop_lod ) {
5000 address[count] = address[count - 1];
5001 address[count - 1] = filler;
5002 count++;
5003 } else
5004 address[count++] = filler;
5005 }
5006 }
5007 }
5008
5009 /* Pack LOD */
5010 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5011 instr->op == nir_texop_txf)) {
5012 address[count++] = lod;
5013 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5014 address[count++] = sample_index;
5015 } else if(instr->op == nir_texop_txs) {
5016 count = 0;
5017 if (lod)
5018 address[count++] = lod;
5019 else
5020 address[count++] = ctx->ac.i32_0;
5021 }
5022
5023 for (chan = 0; chan < count; chan++) {
5024 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5025 address[chan], ctx->ac.i32, "");
5026 }
5027
5028 if (instr->op == nir_texop_samples_identical) {
5029 LLVMValueRef txf_address[4];
5030 struct ac_image_args txf_args = { 0 };
5031 unsigned txf_count = count;
5032 memcpy(txf_address, address, sizeof(txf_address));
5033
5034 if (!instr->is_array)
5035 txf_address[2] = ctx->ac.i32_0;
5036 txf_address[3] = ctx->ac.i32_0;
5037
5038 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5039 fmask_ptr, NULL,
5040 txf_address, txf_count, 0xf);
5041
5042 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5043
5044 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5045 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5046 goto write_result;
5047 }
5048
5049 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5050 instr->op != nir_texop_txs) {
5051 unsigned sample_chan = instr->is_array ? 3 : 2;
5052 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5053 address[0],
5054 address[1],
5055 instr->is_array ? address[2] : NULL,
5056 address[sample_chan],
5057 fmask_ptr);
5058 }
5059
5060 if (offsets && instr->op == nir_texop_txf) {
5061 nir_const_value *const_offset =
5062 nir_src_as_const_value(instr->src[const_src].src);
5063 int num_offsets = instr->src[const_src].src.ssa->num_components;
5064 assert(const_offset);
5065 num_offsets = MIN2(num_offsets, instr->coord_components);
5066 if (num_offsets > 2)
5067 address[2] = LLVMBuildAdd(ctx->ac.builder,
5068 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5069 if (num_offsets > 1)
5070 address[1] = LLVMBuildAdd(ctx->ac.builder,
5071 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5072 address[0] = LLVMBuildAdd(ctx->ac.builder,
5073 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5074
5075 }
5076
5077 /* TODO TG4 support */
5078 if (instr->op == nir_texop_tg4) {
5079 if (instr->is_shadow)
5080 dmask = 1;
5081 else
5082 dmask = 1 << instr->component;
5083 }
5084 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5085 res_ptr, samp_ptr, address, count, dmask);
5086
5087 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5088
5089 if (instr->op == nir_texop_query_levels)
5090 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5091 else if (instr->is_shadow && instr->is_new_style_shadow &&
5092 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5093 instr->op != nir_texop_tg4)
5094 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5095 else if (instr->op == nir_texop_txs &&
5096 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5097 instr->is_array) {
5098 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5099 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5100 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5101 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5102 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5103 } else if (ctx->ac.chip_class >= GFX9 &&
5104 instr->op == nir_texop_txs &&
5105 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5106 instr->is_array) {
5107 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5108 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5109 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5110 ctx->ac.i32_1, "");
5111 } else if (instr->dest.ssa.num_components != 4)
5112 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5113
5114 write_result:
5115 if (result) {
5116 assert(instr->dest.is_ssa);
5117 result = ac_to_integer(&ctx->ac, result);
5118 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5119 }
5120 }
5121
5122
5123 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5124 {
5125 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5126 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5127
5128 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5129 _mesa_hash_table_insert(ctx->phis, instr, result);
5130 }
5131
5132 static void visit_post_phi(struct ac_nir_context *ctx,
5133 nir_phi_instr *instr,
5134 LLVMValueRef llvm_phi)
5135 {
5136 nir_foreach_phi_src(src, instr) {
5137 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5138 LLVMValueRef llvm_src = get_src(ctx, src->src);
5139
5140 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5141 }
5142 }
5143
5144 static void phi_post_pass(struct ac_nir_context *ctx)
5145 {
5146 struct hash_entry *entry;
5147 hash_table_foreach(ctx->phis, entry) {
5148 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5149 (LLVMValueRef)entry->data);
5150 }
5151 }
5152
5153
5154 static void visit_ssa_undef(struct ac_nir_context *ctx,
5155 const nir_ssa_undef_instr *instr)
5156 {
5157 unsigned num_components = instr->def.num_components;
5158 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5159 LLVMValueRef undef;
5160
5161 if (num_components == 1)
5162 undef = LLVMGetUndef(type);
5163 else {
5164 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5165 }
5166 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5167 }
5168
5169 static void visit_jump(struct ac_nir_context *ctx,
5170 const nir_jump_instr *instr)
5171 {
5172 switch (instr->type) {
5173 case nir_jump_break:
5174 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5175 LLVMClearInsertionPosition(ctx->ac.builder);
5176 break;
5177 case nir_jump_continue:
5178 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5179 LLVMClearInsertionPosition(ctx->ac.builder);
5180 break;
5181 default:
5182 fprintf(stderr, "Unknown NIR jump instr: ");
5183 nir_print_instr(&instr->instr, stderr);
5184 fprintf(stderr, "\n");
5185 abort();
5186 }
5187 }
5188
5189 static void visit_cf_list(struct ac_nir_context *ctx,
5190 struct exec_list *list);
5191
5192 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5193 {
5194 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5195 nir_foreach_instr(instr, block)
5196 {
5197 switch (instr->type) {
5198 case nir_instr_type_alu:
5199 visit_alu(ctx, nir_instr_as_alu(instr));
5200 break;
5201 case nir_instr_type_load_const:
5202 visit_load_const(ctx, nir_instr_as_load_const(instr));
5203 break;
5204 case nir_instr_type_intrinsic:
5205 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5206 break;
5207 case nir_instr_type_tex:
5208 visit_tex(ctx, nir_instr_as_tex(instr));
5209 break;
5210 case nir_instr_type_phi:
5211 visit_phi(ctx, nir_instr_as_phi(instr));
5212 break;
5213 case nir_instr_type_ssa_undef:
5214 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5215 break;
5216 case nir_instr_type_jump:
5217 visit_jump(ctx, nir_instr_as_jump(instr));
5218 break;
5219 default:
5220 fprintf(stderr, "Unknown NIR instr type: ");
5221 nir_print_instr(instr, stderr);
5222 fprintf(stderr, "\n");
5223 abort();
5224 }
5225 }
5226
5227 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5228 }
5229
5230 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5231 {
5232 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5233
5234 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5235 LLVMBasicBlockRef merge_block =
5236 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5237 LLVMBasicBlockRef if_block =
5238 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5239 LLVMBasicBlockRef else_block = merge_block;
5240 if (!exec_list_is_empty(&if_stmt->else_list))
5241 else_block = LLVMAppendBasicBlockInContext(
5242 ctx->ac.context, fn, "");
5243
5244 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5245 ctx->ac.i32_0, "");
5246 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5247
5248 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5249 visit_cf_list(ctx, &if_stmt->then_list);
5250 if (LLVMGetInsertBlock(ctx->ac.builder))
5251 LLVMBuildBr(ctx->ac.builder, merge_block);
5252
5253 if (!exec_list_is_empty(&if_stmt->else_list)) {
5254 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5255 visit_cf_list(ctx, &if_stmt->else_list);
5256 if (LLVMGetInsertBlock(ctx->ac.builder))
5257 LLVMBuildBr(ctx->ac.builder, merge_block);
5258 }
5259
5260 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5261 }
5262
5263 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5264 {
5265 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5266 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5267 LLVMBasicBlockRef break_parent = ctx->break_block;
5268
5269 ctx->continue_block =
5270 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5271 ctx->break_block =
5272 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5273
5274 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5275 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5276 visit_cf_list(ctx, &loop->body);
5277
5278 if (LLVMGetInsertBlock(ctx->ac.builder))
5279 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5280 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5281
5282 ctx->continue_block = continue_parent;
5283 ctx->break_block = break_parent;
5284 }
5285
5286 static void visit_cf_list(struct ac_nir_context *ctx,
5287 struct exec_list *list)
5288 {
5289 foreach_list_typed(nir_cf_node, node, node, list)
5290 {
5291 switch (node->type) {
5292 case nir_cf_node_block:
5293 visit_block(ctx, nir_cf_node_as_block(node));
5294 break;
5295
5296 case nir_cf_node_if:
5297 visit_if(ctx, nir_cf_node_as_if(node));
5298 break;
5299
5300 case nir_cf_node_loop:
5301 visit_loop(ctx, nir_cf_node_as_loop(node));
5302 break;
5303
5304 default:
5305 assert(0);
5306 }
5307 }
5308 }
5309
5310 static void
5311 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5312 struct nir_variable *variable)
5313 {
5314 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5315 LLVMValueRef t_offset;
5316 LLVMValueRef t_list;
5317 LLVMValueRef input;
5318 LLVMValueRef buffer_index;
5319 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5320 int idx = variable->data.location;
5321 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5322
5323 variable->data.driver_location = idx * 4;
5324
5325 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5326 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5327 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5328 ctx->abi.start_instance, "");
5329 if (ctx->options->key.vs.as_ls) {
5330 ctx->shader_info->vs.vgpr_comp_cnt =
5331 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5332 } else {
5333 ctx->shader_info->vs.vgpr_comp_cnt =
5334 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5335 }
5336 } else
5337 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5338 ctx->abi.base_vertex, "");
5339 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5340
5341 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5342
5343 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5344 buffer_index,
5345 ctx->ac.i32_0,
5346 4, false, true);
5347
5348 for (unsigned chan = 0; chan < 4; chan++) {
5349 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5350 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5351 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5352 input, llvm_chan, ""));
5353 }
5354 }
5355 }
5356
5357 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5358 unsigned attr,
5359 LLVMValueRef interp_param,
5360 LLVMValueRef prim_mask,
5361 LLVMValueRef result[4])
5362 {
5363 LLVMValueRef attr_number;
5364 unsigned chan;
5365 LLVMValueRef i, j;
5366 bool interp = interp_param != NULL;
5367
5368 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5369
5370 /* fs.constant returns the param from the middle vertex, so it's not
5371 * really useful for flat shading. It's meant to be used for custom
5372 * interpolation (but the intrinsic can't fetch from the other two
5373 * vertices).
5374 *
5375 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5376 * to do the right thing. The only reason we use fs.constant is that
5377 * fs.interp cannot be used on integers, because they can be equal
5378 * to NaN.
5379 */
5380 if (interp) {
5381 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5382 ctx->ac.v2f32, "");
5383
5384 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5385 ctx->ac.i32_0, "");
5386 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5387 ctx->ac.i32_1, "");
5388 }
5389
5390 for (chan = 0; chan < 4; chan++) {
5391 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5392
5393 if (interp) {
5394 result[chan] = ac_build_fs_interp(&ctx->ac,
5395 llvm_chan,
5396 attr_number,
5397 prim_mask, i, j);
5398 } else {
5399 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5400 LLVMConstInt(ctx->ac.i32, 2, false),
5401 llvm_chan,
5402 attr_number,
5403 prim_mask);
5404 }
5405 }
5406 }
5407
5408 static void
5409 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5410 struct nir_variable *variable)
5411 {
5412 int idx = variable->data.location;
5413 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5414 LLVMValueRef interp;
5415
5416 variable->data.driver_location = idx * 4;
5417 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5418
5419 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5420 unsigned interp_type;
5421 if (variable->data.sample) {
5422 interp_type = INTERP_SAMPLE;
5423 ctx->shader_info->info.ps.force_persample = true;
5424 } else if (variable->data.centroid)
5425 interp_type = INTERP_CENTROID;
5426 else
5427 interp_type = INTERP_CENTER;
5428
5429 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5430 } else
5431 interp = NULL;
5432
5433 for (unsigned i = 0; i < attrib_count; ++i)
5434 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5435
5436 }
5437
5438 static void
5439 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5440 struct nir_shader *nir) {
5441 nir_foreach_variable(variable, &nir->inputs)
5442 handle_vs_input_decl(ctx, variable);
5443 }
5444
5445 static void
5446 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5447 struct nir_shader *nir)
5448 {
5449 if (!ctx->options->key.fs.multisample)
5450 return;
5451
5452 bool uses_center = false;
5453 bool uses_centroid = false;
5454 nir_foreach_variable(variable, &nir->inputs) {
5455 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5456 variable->data.sample)
5457 continue;
5458
5459 if (variable->data.centroid)
5460 uses_centroid = true;
5461 else
5462 uses_center = true;
5463 }
5464
5465 if (uses_center && uses_centroid) {
5466 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5467 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5468 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5469 }
5470 }
5471
5472 static void
5473 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5474 struct nir_shader *nir)
5475 {
5476 prepare_interp_optimize(ctx, nir);
5477
5478 nir_foreach_variable(variable, &nir->inputs)
5479 handle_fs_input_decl(ctx, variable);
5480
5481 unsigned index = 0;
5482
5483 if (ctx->shader_info->info.ps.uses_input_attachments ||
5484 ctx->shader_info->info.needs_multiview_view_index)
5485 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5486
5487 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5488 LLVMValueRef interp_param;
5489 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5490
5491 if (!(ctx->input_mask & (1ull << i)))
5492 continue;
5493
5494 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5495 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5496 interp_param = *inputs;
5497 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5498 inputs);
5499
5500 if (!interp_param)
5501 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5502 ++index;
5503 } else if (i == VARYING_SLOT_POS) {
5504 for(int i = 0; i < 3; ++i)
5505 inputs[i] = ctx->abi.frag_pos[i];
5506
5507 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5508 ctx->abi.frag_pos[3]);
5509 }
5510 }
5511 ctx->shader_info->fs.num_interp = index;
5512 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5513 ctx->shader_info->fs.has_pcoord = true;
5514 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5515 ctx->shader_info->fs.prim_id_input = true;
5516 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5517 ctx->shader_info->fs.layer_input = true;
5518 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5519
5520 if (ctx->shader_info->info.needs_multiview_view_index)
5521 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5522 }
5523
5524 static LLVMValueRef
5525 ac_build_alloca(struct ac_llvm_context *ac,
5526 LLVMTypeRef type,
5527 const char *name)
5528 {
5529 LLVMBuilderRef builder = ac->builder;
5530 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5531 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5532 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5533 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5534 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5535 LLVMValueRef res;
5536
5537 if (first_instr) {
5538 LLVMPositionBuilderBefore(first_builder, first_instr);
5539 } else {
5540 LLVMPositionBuilderAtEnd(first_builder, first_block);
5541 }
5542
5543 res = LLVMBuildAlloca(first_builder, type, name);
5544 LLVMBuildStore(builder, LLVMConstNull(type), res);
5545
5546 LLVMDisposeBuilder(first_builder);
5547
5548 return res;
5549 }
5550
5551 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5552 LLVMTypeRef type,
5553 const char *name)
5554 {
5555 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5556 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5557 return ptr;
5558 }
5559
5560 static void
5561 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5562 struct nir_variable *variable,
5563 struct nir_shader *shader,
5564 gl_shader_stage stage)
5565 {
5566 int idx = variable->data.location + variable->data.index;
5567 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5568 uint64_t mask_attribs;
5569
5570 variable->data.driver_location = idx * 4;
5571
5572 /* tess ctrl has it's own load/store paths for outputs */
5573 if (stage == MESA_SHADER_TESS_CTRL)
5574 return;
5575
5576 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5577 if (stage == MESA_SHADER_VERTEX ||
5578 stage == MESA_SHADER_TESS_EVAL ||
5579 stage == MESA_SHADER_GEOMETRY) {
5580 if (idx == VARYING_SLOT_CLIP_DIST0) {
5581 int length = shader->info.clip_distance_array_size +
5582 shader->info.cull_distance_array_size;
5583 if (stage == MESA_SHADER_VERTEX) {
5584 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5585 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5586 }
5587 if (stage == MESA_SHADER_TESS_EVAL) {
5588 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5589 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5590 }
5591
5592 if (length > 4)
5593 attrib_count = 2;
5594 else
5595 attrib_count = 1;
5596 mask_attribs = 1ull << idx;
5597 }
5598 }
5599
5600 ctx->output_mask |= mask_attribs;
5601 }
5602
5603 static void
5604 handle_shader_output_decl(struct ac_nir_context *ctx,
5605 struct nir_shader *nir,
5606 struct nir_variable *variable)
5607 {
5608 unsigned output_loc = variable->data.driver_location / 4;
5609 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5610
5611 /* tess ctrl has it's own load/store paths for outputs */
5612 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5613 return;
5614
5615 if (ctx->stage == MESA_SHADER_VERTEX ||
5616 ctx->stage == MESA_SHADER_TESS_EVAL ||
5617 ctx->stage == MESA_SHADER_GEOMETRY) {
5618 int idx = variable->data.location + variable->data.index;
5619 if (idx == VARYING_SLOT_CLIP_DIST0) {
5620 int length = nir->info.clip_distance_array_size +
5621 nir->info.cull_distance_array_size;
5622
5623 if (length > 4)
5624 attrib_count = 2;
5625 else
5626 attrib_count = 1;
5627 }
5628 }
5629
5630 for (unsigned i = 0; i < attrib_count; ++i) {
5631 for (unsigned chan = 0; chan < 4; chan++) {
5632 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5633 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5634 }
5635 }
5636 }
5637
5638 static LLVMTypeRef
5639 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5640 enum glsl_base_type type)
5641 {
5642 switch (type) {
5643 case GLSL_TYPE_INT:
5644 case GLSL_TYPE_UINT:
5645 case GLSL_TYPE_BOOL:
5646 case GLSL_TYPE_SUBROUTINE:
5647 return ctx->ac.i32;
5648 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5649 return ctx->ac.f32;
5650 case GLSL_TYPE_INT64:
5651 case GLSL_TYPE_UINT64:
5652 return ctx->ac.i64;
5653 case GLSL_TYPE_DOUBLE:
5654 return ctx->ac.f64;
5655 default:
5656 unreachable("unknown GLSL type");
5657 }
5658 }
5659
5660 static LLVMTypeRef
5661 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5662 const struct glsl_type *type)
5663 {
5664 if (glsl_type_is_scalar(type)) {
5665 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5666 }
5667
5668 if (glsl_type_is_vector(type)) {
5669 return LLVMVectorType(
5670 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5671 glsl_get_vector_elements(type));
5672 }
5673
5674 if (glsl_type_is_matrix(type)) {
5675 return LLVMArrayType(
5676 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5677 glsl_get_matrix_columns(type));
5678 }
5679
5680 if (glsl_type_is_array(type)) {
5681 return LLVMArrayType(
5682 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5683 glsl_get_length(type));
5684 }
5685
5686 assert(glsl_type_is_struct(type));
5687
5688 LLVMTypeRef member_types[glsl_get_length(type)];
5689
5690 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5691 member_types[i] =
5692 glsl_to_llvm_type(ctx,
5693 glsl_get_struct_field(type, i));
5694 }
5695
5696 return LLVMStructTypeInContext(ctx->context, member_types,
5697 glsl_get_length(type), false);
5698 }
5699
5700 static void
5701 setup_locals(struct ac_nir_context *ctx,
5702 struct nir_function *func)
5703 {
5704 int i, j;
5705 ctx->num_locals = 0;
5706 nir_foreach_variable(variable, &func->impl->locals) {
5707 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5708 variable->data.driver_location = ctx->num_locals * 4;
5709 variable->data.location_frac = 0;
5710 ctx->num_locals += attrib_count;
5711 }
5712 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5713 if (!ctx->locals)
5714 return;
5715
5716 for (i = 0; i < ctx->num_locals; i++) {
5717 for (j = 0; j < 4; j++) {
5718 ctx->locals[i * 4 + j] =
5719 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5720 }
5721 }
5722 }
5723
5724 static void
5725 setup_shared(struct ac_nir_context *ctx,
5726 struct nir_shader *nir)
5727 {
5728 nir_foreach_variable(variable, &nir->shared) {
5729 LLVMValueRef shared =
5730 LLVMAddGlobalInAddressSpace(
5731 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5732 variable->name ? variable->name : "",
5733 AC_LOCAL_ADDR_SPACE);
5734 _mesa_hash_table_insert(ctx->vars, variable, shared);
5735 }
5736 }
5737
5738 static LLVMValueRef
5739 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5740 {
5741 v = ac_to_float(ctx, v);
5742 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5743 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5744 }
5745
5746
5747 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5748 LLVMValueRef src0, LLVMValueRef src1)
5749 {
5750 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5751 LLVMValueRef comp[2];
5752
5753 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5754 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5755 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5756 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5757 }
5758
5759 /* Initialize arguments for the shader export intrinsic */
5760 static void
5761 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5762 LLVMValueRef *values,
5763 unsigned target,
5764 struct ac_export_args *args)
5765 {
5766 /* Default is 0xf. Adjusted below depending on the format. */
5767 args->enabled_channels = 0xf;
5768
5769 /* Specify whether the EXEC mask represents the valid mask */
5770 args->valid_mask = 0;
5771
5772 /* Specify whether this is the last export */
5773 args->done = 0;
5774
5775 /* Specify the target we are exporting */
5776 args->target = target;
5777
5778 args->compr = false;
5779 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5780 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5781 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5782 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5783
5784 if (!values)
5785 return;
5786
5787 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5788 LLVMValueRef val[4];
5789 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5790 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5791 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5792 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5793
5794 switch(col_format) {
5795 case V_028714_SPI_SHADER_ZERO:
5796 args->enabled_channels = 0; /* writemask */
5797 args->target = V_008DFC_SQ_EXP_NULL;
5798 break;
5799
5800 case V_028714_SPI_SHADER_32_R:
5801 args->enabled_channels = 1;
5802 args->out[0] = values[0];
5803 break;
5804
5805 case V_028714_SPI_SHADER_32_GR:
5806 args->enabled_channels = 0x3;
5807 args->out[0] = values[0];
5808 args->out[1] = values[1];
5809 break;
5810
5811 case V_028714_SPI_SHADER_32_AR:
5812 args->enabled_channels = 0x9;
5813 args->out[0] = values[0];
5814 args->out[3] = values[3];
5815 break;
5816
5817 case V_028714_SPI_SHADER_FP16_ABGR:
5818 args->compr = 1;
5819
5820 for (unsigned chan = 0; chan < 2; chan++) {
5821 LLVMValueRef pack_args[2] = {
5822 values[2 * chan],
5823 values[2 * chan + 1]
5824 };
5825 LLVMValueRef packed;
5826
5827 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5828 args->out[chan] = packed;
5829 }
5830 break;
5831
5832 case V_028714_SPI_SHADER_UNORM16_ABGR:
5833 for (unsigned chan = 0; chan < 4; chan++) {
5834 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5835 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5836 LLVMConstReal(ctx->ac.f32, 65535), "");
5837 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5838 LLVMConstReal(ctx->ac.f32, 0.5), "");
5839 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5840 ctx->ac.i32, "");
5841 }
5842
5843 args->compr = 1;
5844 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5845 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5846 break;
5847
5848 case V_028714_SPI_SHADER_SNORM16_ABGR:
5849 for (unsigned chan = 0; chan < 4; chan++) {
5850 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5851 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5852 LLVMConstReal(ctx->ac.f32, 32767), "");
5853
5854 /* If positive, add 0.5, else add -0.5. */
5855 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5856 LLVMBuildSelect(ctx->builder,
5857 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5858 val[chan], ctx->ac.f32_0, ""),
5859 LLVMConstReal(ctx->ac.f32, 0.5),
5860 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5861 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5862 }
5863
5864 args->compr = 1;
5865 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5866 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5867 break;
5868
5869 case V_028714_SPI_SHADER_UINT16_ABGR: {
5870 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5871 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5872 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5873
5874 for (unsigned chan = 0; chan < 4; chan++) {
5875 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5876 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5877 }
5878
5879 args->compr = 1;
5880 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5881 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5882 break;
5883 }
5884
5885 case V_028714_SPI_SHADER_SINT16_ABGR: {
5886 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5887 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5888 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5889 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5890 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5891 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5892
5893 /* Clamp. */
5894 for (unsigned chan = 0; chan < 4; chan++) {
5895 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5896 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5897 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5898 }
5899
5900 args->compr = 1;
5901 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5902 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5903 break;
5904 }
5905
5906 default:
5907 case V_028714_SPI_SHADER_32_ABGR:
5908 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5909 break;
5910 }
5911 } else
5912 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5913
5914 for (unsigned i = 0; i < 4; ++i)
5915 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5916 }
5917
5918 static void
5919 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5920 bool export_prim_id,
5921 struct ac_vs_output_info *outinfo)
5922 {
5923 uint32_t param_count = 0;
5924 unsigned target;
5925 unsigned pos_idx, num_pos_exports = 0;
5926 struct ac_export_args args, pos_args[4] = {};
5927 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5928 int i;
5929
5930 if (ctx->options->key.has_multiview_view_index) {
5931 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5932 if(!*tmp_out) {
5933 for(unsigned i = 0; i < 4; ++i)
5934 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5935 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5936 }
5937
5938 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5939 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5940 }
5941
5942 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5943 sizeof(outinfo->vs_output_param_offset));
5944
5945 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5946 LLVMValueRef slots[8];
5947 unsigned j;
5948
5949 if (outinfo->cull_dist_mask)
5950 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5951
5952 i = VARYING_SLOT_CLIP_DIST0;
5953 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5954 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5955 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5956
5957 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5958 slots[i] = LLVMGetUndef(ctx->ac.f32);
5959
5960 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5961 target = V_008DFC_SQ_EXP_POS + 3;
5962 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5963 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5964 &args, sizeof(args));
5965 }
5966
5967 target = V_008DFC_SQ_EXP_POS + 2;
5968 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5969 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5970 &args, sizeof(args));
5971
5972 }
5973
5974 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5975 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5976 for (unsigned j = 0; j < 4; j++)
5977 pos_values[j] = LLVMBuildLoad(ctx->builder,
5978 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5979 }
5980 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5981
5982 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5983 outinfo->writes_pointsize = true;
5984 psize_value = LLVMBuildLoad(ctx->builder,
5985 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5986 }
5987
5988 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5989 outinfo->writes_layer = true;
5990 layer_value = LLVMBuildLoad(ctx->builder,
5991 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5992 }
5993
5994 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5995 outinfo->writes_viewport_index = true;
5996 viewport_index_value = LLVMBuildLoad(ctx->builder,
5997 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5998 }
5999
6000 if (outinfo->writes_pointsize ||
6001 outinfo->writes_layer ||
6002 outinfo->writes_viewport_index) {
6003 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6004 (outinfo->writes_layer == true ? 4 : 0));
6005 pos_args[1].valid_mask = 0;
6006 pos_args[1].done = 0;
6007 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6008 pos_args[1].compr = 0;
6009 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6010 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6011 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6012 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6013
6014 if (outinfo->writes_pointsize == true)
6015 pos_args[1].out[0] = psize_value;
6016 if (outinfo->writes_layer == true)
6017 pos_args[1].out[2] = layer_value;
6018 if (outinfo->writes_viewport_index == true) {
6019 if (ctx->options->chip_class >= GFX9) {
6020 /* GFX9 has the layer in out.z[10:0] and the viewport
6021 * index in out.z[19:16].
6022 */
6023 LLVMValueRef v = viewport_index_value;
6024 v = ac_to_integer(&ctx->ac, v);
6025 v = LLVMBuildShl(ctx->builder, v,
6026 LLVMConstInt(ctx->ac.i32, 16, false),
6027 "");
6028 v = LLVMBuildOr(ctx->builder, v,
6029 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6030
6031 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6032 pos_args[1].enabled_channels |= 1 << 2;
6033 } else {
6034 pos_args[1].out[3] = viewport_index_value;
6035 pos_args[1].enabled_channels |= 1 << 3;
6036 }
6037 }
6038 }
6039 for (i = 0; i < 4; i++) {
6040 if (pos_args[i].out[0])
6041 num_pos_exports++;
6042 }
6043
6044 pos_idx = 0;
6045 for (i = 0; i < 4; i++) {
6046 if (!pos_args[i].out[0])
6047 continue;
6048
6049 /* Specify the target we are exporting */
6050 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6051 if (pos_idx == num_pos_exports)
6052 pos_args[i].done = 1;
6053 ac_build_export(&ctx->ac, &pos_args[i]);
6054 }
6055
6056 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6057 LLVMValueRef values[4];
6058 if (!(ctx->output_mask & (1ull << i)))
6059 continue;
6060
6061 for (unsigned j = 0; j < 4; j++)
6062 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6063 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6064
6065 if (i == VARYING_SLOT_LAYER) {
6066 target = V_008DFC_SQ_EXP_PARAM + param_count;
6067 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
6068 param_count++;
6069 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
6070 target = V_008DFC_SQ_EXP_PARAM + param_count;
6071 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6072 param_count++;
6073 } else if (i >= VARYING_SLOT_VAR0) {
6074 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
6075 target = V_008DFC_SQ_EXP_PARAM + param_count;
6076 outinfo->vs_output_param_offset[i] = param_count;
6077 param_count++;
6078 } else
6079 continue;
6080
6081 si_llvm_init_export_args(ctx, values, target, &args);
6082
6083 if (target >= V_008DFC_SQ_EXP_POS &&
6084 target <= (V_008DFC_SQ_EXP_POS + 3)) {
6085 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6086 &args, sizeof(args));
6087 } else {
6088 ac_build_export(&ctx->ac, &args);
6089 }
6090 }
6091
6092 if (export_prim_id) {
6093 LLVMValueRef values[4];
6094 target = V_008DFC_SQ_EXP_PARAM + param_count;
6095 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6096 param_count++;
6097
6098 values[0] = ctx->vs_prim_id;
6099 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6100 ctx->shader_info->vs.vgpr_comp_cnt);
6101 for (unsigned j = 1; j < 4; j++)
6102 values[j] = ctx->ac.f32_0;
6103 si_llvm_init_export_args(ctx, values, target, &args);
6104 ac_build_export(&ctx->ac, &args);
6105 outinfo->export_prim_id = true;
6106 }
6107
6108 outinfo->pos_exports = num_pos_exports;
6109 outinfo->param_exports = param_count;
6110 }
6111
6112 static void
6113 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6114 struct ac_es_output_info *outinfo)
6115 {
6116 int j;
6117 uint64_t max_output_written = 0;
6118 LLVMValueRef lds_base = NULL;
6119
6120 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6121 int param_index;
6122 int length = 4;
6123
6124 if (!(ctx->output_mask & (1ull << i)))
6125 continue;
6126
6127 if (i == VARYING_SLOT_CLIP_DIST0)
6128 length = ctx->num_output_clips + ctx->num_output_culls;
6129
6130 param_index = shader_io_get_unique_index(i);
6131
6132 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6133 }
6134
6135 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6136
6137 if (ctx->ac.chip_class >= GFX9) {
6138 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6139 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6140 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6141 LLVMConstInt(ctx->ac.i32, 24, false),
6142 LLVMConstInt(ctx->ac.i32, 4, false), false);
6143 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6144 LLVMBuildMul(ctx->ac.builder, wave_idx,
6145 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6146 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6147 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6148 }
6149
6150 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6151 LLVMValueRef dw_addr;
6152 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6153 int param_index;
6154 int length = 4;
6155
6156 if (!(ctx->output_mask & (1ull << i)))
6157 continue;
6158
6159 if (i == VARYING_SLOT_CLIP_DIST0)
6160 length = ctx->num_output_clips + ctx->num_output_culls;
6161
6162 param_index = shader_io_get_unique_index(i);
6163
6164 if (lds_base) {
6165 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6166 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6167 "");
6168 }
6169 for (j = 0; j < length; j++) {
6170 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6171 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6172
6173 if (ctx->ac.chip_class >= GFX9) {
6174 ac_lds_store(&ctx->ac, dw_addr,
6175 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6176 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6177 } else {
6178 ac_build_buffer_store_dword(&ctx->ac,
6179 ctx->esgs_ring,
6180 out_val, 1,
6181 NULL, ctx->es2gs_offset,
6182 (4 * param_index + j) * 4,
6183 1, 1, true, true);
6184 }
6185 }
6186 }
6187 }
6188
6189 static void
6190 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6191 {
6192 LLVMValueRef vertex_id = ctx->rel_auto_id;
6193 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6194 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6195 vertex_dw_stride, "");
6196
6197 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6198 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6199 int length = 4;
6200
6201 if (!(ctx->output_mask & (1ull << i)))
6202 continue;
6203
6204 if (i == VARYING_SLOT_CLIP_DIST0)
6205 length = ctx->num_output_clips + ctx->num_output_culls;
6206 int param = shader_io_get_unique_index(i);
6207 mark_tess_output(ctx, false, param);
6208 if (length > 4)
6209 mark_tess_output(ctx, false, param + 1);
6210 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6211 LLVMConstInt(ctx->ac.i32, param * 4, false),
6212 "");
6213 for (unsigned j = 0; j < length; j++) {
6214 ac_lds_store(&ctx->ac, dw_addr,
6215 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6216 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6217 }
6218 }
6219 }
6220
6221 struct ac_build_if_state
6222 {
6223 struct nir_to_llvm_context *ctx;
6224 LLVMValueRef condition;
6225 LLVMBasicBlockRef entry_block;
6226 LLVMBasicBlockRef true_block;
6227 LLVMBasicBlockRef false_block;
6228 LLVMBasicBlockRef merge_block;
6229 };
6230
6231 static LLVMBasicBlockRef
6232 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6233 {
6234 LLVMBasicBlockRef current_block;
6235 LLVMBasicBlockRef next_block;
6236 LLVMBasicBlockRef new_block;
6237
6238 /* get current basic block */
6239 current_block = LLVMGetInsertBlock(ctx->builder);
6240
6241 /* chqeck if there's another block after this one */
6242 next_block = LLVMGetNextBasicBlock(current_block);
6243 if (next_block) {
6244 /* insert the new block before the next block */
6245 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6246 }
6247 else {
6248 /* append new block after current block */
6249 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6250 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6251 }
6252 return new_block;
6253 }
6254
6255 static void
6256 ac_nir_build_if(struct ac_build_if_state *ifthen,
6257 struct nir_to_llvm_context *ctx,
6258 LLVMValueRef condition)
6259 {
6260 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6261
6262 memset(ifthen, 0, sizeof *ifthen);
6263 ifthen->ctx = ctx;
6264 ifthen->condition = condition;
6265 ifthen->entry_block = block;
6266
6267 /* create endif/merge basic block for the phi functions */
6268 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6269
6270 /* create/insert true_block before merge_block */
6271 ifthen->true_block =
6272 LLVMInsertBasicBlockInContext(ctx->context,
6273 ifthen->merge_block,
6274 "if-true-block");
6275
6276 /* successive code goes into the true block */
6277 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6278 }
6279
6280 /**
6281 * End a conditional.
6282 */
6283 static void
6284 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6285 {
6286 LLVMBuilderRef builder = ifthen->ctx->builder;
6287
6288 /* Insert branch to the merge block from current block */
6289 LLVMBuildBr(builder, ifthen->merge_block);
6290
6291 /*
6292 * Now patch in the various branch instructions.
6293 */
6294
6295 /* Insert the conditional branch instruction at the end of entry_block */
6296 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6297 if (ifthen->false_block) {
6298 /* we have an else clause */
6299 LLVMBuildCondBr(builder, ifthen->condition,
6300 ifthen->true_block, ifthen->false_block);
6301 }
6302 else {
6303 /* no else clause */
6304 LLVMBuildCondBr(builder, ifthen->condition,
6305 ifthen->true_block, ifthen->merge_block);
6306 }
6307
6308 /* Resume building code at end of the ifthen->merge_block */
6309 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6310 }
6311
6312 static void
6313 write_tess_factors(struct nir_to_llvm_context *ctx)
6314 {
6315 unsigned stride, outer_comps, inner_comps;
6316 struct ac_build_if_state if_ctx, inner_if_ctx;
6317 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6318 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6319 unsigned tess_inner_index, tess_outer_index;
6320 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6321 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6322 int i;
6323 emit_barrier(&ctx->ac, ctx->stage);
6324
6325 switch (ctx->options->key.tcs.primitive_mode) {
6326 case GL_ISOLINES:
6327 stride = 2;
6328 outer_comps = 2;
6329 inner_comps = 0;
6330 break;
6331 case GL_TRIANGLES:
6332 stride = 4;
6333 outer_comps = 3;
6334 inner_comps = 1;
6335 break;
6336 case GL_QUADS:
6337 stride = 6;
6338 outer_comps = 4;
6339 inner_comps = 2;
6340 break;
6341 default:
6342 return;
6343 }
6344
6345 ac_nir_build_if(&if_ctx, ctx,
6346 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6347 invocation_id, ctx->ac.i32_0, ""));
6348
6349 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6350 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6351
6352 mark_tess_output(ctx, true, tess_inner_index);
6353 mark_tess_output(ctx, true, tess_outer_index);
6354 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6355 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6356 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6357 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6358 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6359
6360 for (i = 0; i < 4; i++) {
6361 inner[i] = LLVMGetUndef(ctx->ac.i32);
6362 outer[i] = LLVMGetUndef(ctx->ac.i32);
6363 }
6364
6365 // LINES reverseal
6366 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6367 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6368 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6369 ctx->ac.i32_1, "");
6370 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6371 } else {
6372 for (i = 0; i < outer_comps; i++) {
6373 outer[i] = out[i] =
6374 ac_lds_load(&ctx->ac, lds_outer);
6375 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6376 ctx->ac.i32_1, "");
6377 }
6378 for (i = 0; i < inner_comps; i++) {
6379 inner[i] = out[outer_comps+i] =
6380 ac_lds_load(&ctx->ac, lds_inner);
6381 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6382 ctx->ac.i32_1, "");
6383 }
6384 }
6385
6386 /* Convert the outputs to vectors for stores. */
6387 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6388 vec1 = NULL;
6389
6390 if (stride > 4)
6391 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6392
6393
6394 buffer = ctx->hs_ring_tess_factor;
6395 tf_base = ctx->tess_factor_offset;
6396 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6397 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6398 unsigned tf_offset = 0;
6399
6400 if (ctx->options->chip_class <= VI) {
6401 ac_nir_build_if(&inner_if_ctx, ctx,
6402 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6403 rel_patch_id, ctx->ac.i32_0, ""));
6404
6405 /* Store the dynamic HS control word. */
6406 ac_build_buffer_store_dword(&ctx->ac, buffer,
6407 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6408 1, ctx->ac.i32_0, tf_base,
6409 0, 1, 0, true, false);
6410 tf_offset += 4;
6411
6412 ac_nir_build_endif(&inner_if_ctx);
6413 }
6414
6415 /* Store the tessellation factors. */
6416 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6417 MIN2(stride, 4), byteoffset, tf_base,
6418 tf_offset, 1, 0, true, false);
6419 if (vec1)
6420 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6421 stride - 4, byteoffset, tf_base,
6422 16 + tf_offset, 1, 0, true, false);
6423
6424 //store to offchip for TES to read - only if TES reads them
6425 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6426 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6427 LLVMValueRef tf_inner_offset;
6428 unsigned param_outer, param_inner;
6429
6430 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6431 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6432 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6433
6434 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6435 util_next_power_of_two(outer_comps));
6436
6437 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6438 outer_comps, tf_outer_offset,
6439 ctx->oc_lds, 0, 1, 0, true, false);
6440 if (inner_comps) {
6441 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6442 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6443 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6444
6445 inner_vec = inner_comps == 1 ? inner[0] :
6446 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6447 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6448 inner_comps, tf_inner_offset,
6449 ctx->oc_lds, 0, 1, 0, true, false);
6450 }
6451 }
6452 ac_nir_build_endif(&if_ctx);
6453 }
6454
6455 static void
6456 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6457 {
6458 write_tess_factors(ctx);
6459 }
6460
6461 static bool
6462 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6463 LLVMValueRef *color, unsigned param, bool is_last,
6464 struct ac_export_args *args)
6465 {
6466 /* Export */
6467 si_llvm_init_export_args(ctx, color, param,
6468 args);
6469
6470 if (is_last) {
6471 args->valid_mask = 1; /* whether the EXEC mask is valid */
6472 args->done = 1; /* DONE bit */
6473 } else if (!args->enabled_channels)
6474 return false; /* unnecessary NULL export */
6475
6476 return true;
6477 }
6478
6479 static void
6480 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6481 LLVMValueRef depth, LLVMValueRef stencil,
6482 LLVMValueRef samplemask)
6483 {
6484 struct ac_export_args args;
6485
6486 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6487
6488 ac_build_export(&ctx->ac, &args);
6489 }
6490
6491 static void
6492 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6493 {
6494 unsigned index = 0;
6495 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6496 struct ac_export_args color_args[8];
6497
6498 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6499 LLVMValueRef values[4];
6500
6501 if (!(ctx->output_mask & (1ull << i)))
6502 continue;
6503
6504 if (i == FRAG_RESULT_DEPTH) {
6505 ctx->shader_info->fs.writes_z = true;
6506 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6507 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6508 } else if (i == FRAG_RESULT_STENCIL) {
6509 ctx->shader_info->fs.writes_stencil = true;
6510 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6511 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6512 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6513 ctx->shader_info->fs.writes_sample_mask = true;
6514 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6515 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6516 } else {
6517 bool last = false;
6518 for (unsigned j = 0; j < 4; j++)
6519 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6520 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6521
6522 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6523 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6524
6525 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6526 if (ret)
6527 index++;
6528 }
6529 }
6530
6531 for (unsigned i = 0; i < index; i++)
6532 ac_build_export(&ctx->ac, &color_args[i]);
6533 if (depth || stencil || samplemask)
6534 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6535 else if (!index) {
6536 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6537 ac_build_export(&ctx->ac, &color_args[0]);
6538 }
6539 }
6540
6541 static void
6542 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6543 {
6544 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6545 }
6546
6547 static void
6548 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6549 LLVMValueRef *addrs)
6550 {
6551 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6552
6553 switch (ctx->stage) {
6554 case MESA_SHADER_VERTEX:
6555 if (ctx->options->key.vs.as_ls)
6556 handle_ls_outputs_post(ctx);
6557 else if (ctx->options->key.vs.as_es)
6558 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6559 else
6560 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6561 &ctx->shader_info->vs.outinfo);
6562 break;
6563 case MESA_SHADER_FRAGMENT:
6564 handle_fs_outputs_post(ctx);
6565 break;
6566 case MESA_SHADER_GEOMETRY:
6567 emit_gs_epilogue(ctx);
6568 break;
6569 case MESA_SHADER_TESS_CTRL:
6570 handle_tcs_outputs_post(ctx);
6571 break;
6572 case MESA_SHADER_TESS_EVAL:
6573 if (ctx->options->key.tes.as_es)
6574 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6575 else
6576 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6577 &ctx->shader_info->tes.outinfo);
6578 break;
6579 default:
6580 break;
6581 }
6582 }
6583
6584 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6585 {
6586 LLVMPassManagerRef passmgr;
6587 /* Create the pass manager */
6588 passmgr = LLVMCreateFunctionPassManagerForModule(
6589 ctx->module);
6590
6591 /* This pass should eliminate all the load and store instructions */
6592 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6593
6594 /* Add some optimization passes */
6595 LLVMAddScalarReplAggregatesPass(passmgr);
6596 LLVMAddLICMPass(passmgr);
6597 LLVMAddAggressiveDCEPass(passmgr);
6598 LLVMAddCFGSimplificationPass(passmgr);
6599 LLVMAddInstructionCombiningPass(passmgr);
6600
6601 /* Run the pass */
6602 LLVMInitializeFunctionPassManager(passmgr);
6603 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6604 LLVMFinalizeFunctionPassManager(passmgr);
6605
6606 LLVMDisposeBuilder(ctx->builder);
6607 LLVMDisposePassManager(passmgr);
6608 }
6609
6610 static void
6611 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6612 {
6613 struct ac_vs_output_info *outinfo;
6614
6615 switch (ctx->stage) {
6616 case MESA_SHADER_FRAGMENT:
6617 case MESA_SHADER_COMPUTE:
6618 case MESA_SHADER_TESS_CTRL:
6619 case MESA_SHADER_GEOMETRY:
6620 return;
6621 case MESA_SHADER_VERTEX:
6622 if (ctx->options->key.vs.as_ls ||
6623 ctx->options->key.vs.as_es)
6624 return;
6625 outinfo = &ctx->shader_info->vs.outinfo;
6626 break;
6627 case MESA_SHADER_TESS_EVAL:
6628 if (ctx->options->key.vs.as_es)
6629 return;
6630 outinfo = &ctx->shader_info->tes.outinfo;
6631 break;
6632 default:
6633 unreachable("Unhandled shader type");
6634 }
6635
6636 ac_optimize_vs_outputs(&ctx->ac,
6637 ctx->main_function,
6638 outinfo->vs_output_param_offset,
6639 VARYING_SLOT_MAX,
6640 &outinfo->param_exports);
6641 }
6642
6643 static void
6644 ac_setup_rings(struct nir_to_llvm_context *ctx)
6645 {
6646 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6647 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6648 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6649 }
6650
6651 if (ctx->is_gs_copy_shader) {
6652 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6653 }
6654 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6655 LLVMValueRef tmp;
6656 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6657 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6658
6659 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6660
6661 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6662 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6663 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6664 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6665 }
6666
6667 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6668 ctx->stage == MESA_SHADER_TESS_EVAL) {
6669 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6670 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6671 }
6672 }
6673
6674 static unsigned
6675 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6676 const struct nir_shader *nir)
6677 {
6678 switch (nir->info.stage) {
6679 case MESA_SHADER_TESS_CTRL:
6680 return chip_class >= CIK ? 128 : 64;
6681 case MESA_SHADER_GEOMETRY:
6682 return chip_class >= GFX9 ? 128 : 64;
6683 case MESA_SHADER_COMPUTE:
6684 break;
6685 default:
6686 return 0;
6687 }
6688
6689 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6690 nir->info.cs.local_size[1] *
6691 nir->info.cs.local_size[2];
6692 return max_workgroup_size;
6693 }
6694
6695 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6696 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6697 {
6698 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6699 LLVMConstInt(ctx->ac.i32, 8, false),
6700 LLVMConstInt(ctx->ac.i32, 8, false), false);
6701 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6702 ctx->ac.i32_0, "");
6703 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6704 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6705 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6706 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6707 }
6708
6709 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6710 {
6711 for(int i = 5; i >= 0; --i) {
6712 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6713 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6714 LLVMConstInt(ctx->ac.i32, 16, false), false);
6715 }
6716
6717 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6718 LLVMConstInt(ctx->ac.i32, 16, false),
6719 LLVMConstInt(ctx->ac.i32, 8, false), false);
6720 }
6721
6722 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6723 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6724 {
6725 struct ac_nir_context ctx = {};
6726 struct nir_function *func;
6727
6728 ctx.ac = *ac;
6729 ctx.abi = abi;
6730
6731 ctx.nctx = nctx;
6732 if (nctx)
6733 nctx->nir = &ctx;
6734
6735 ctx.stage = nir->info.stage;
6736
6737 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6738
6739 nir_foreach_variable(variable, &nir->outputs)
6740 handle_shader_output_decl(&ctx, nir, variable);
6741
6742 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6743 _mesa_key_pointer_equal);
6744 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6745 _mesa_key_pointer_equal);
6746 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6747 _mesa_key_pointer_equal);
6748
6749 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6750
6751 setup_locals(&ctx, func);
6752
6753 if (nir->info.stage == MESA_SHADER_COMPUTE)
6754 setup_shared(&ctx, nir);
6755
6756 visit_cf_list(&ctx, &func->impl->body);
6757 phi_post_pass(&ctx);
6758
6759 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6760 ctx.outputs);
6761
6762 free(ctx.locals);
6763 ralloc_free(ctx.defs);
6764 ralloc_free(ctx.phis);
6765 ralloc_free(ctx.vars);
6766
6767 if (nctx)
6768 nctx->nir = NULL;
6769 }
6770
6771 static
6772 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6773 struct nir_shader *const *shaders,
6774 int shader_count,
6775 struct ac_shader_variant_info *shader_info,
6776 const struct ac_nir_compiler_options *options)
6777 {
6778 struct nir_to_llvm_context ctx = {0};
6779 unsigned i;
6780 ctx.options = options;
6781 ctx.shader_info = shader_info;
6782 ctx.context = LLVMContextCreate();
6783 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6784
6785 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6786 options->family);
6787 ctx.ac.module = ctx.module;
6788 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6789
6790 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6791 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6792 LLVMSetDataLayout(ctx.module, data_layout_str);
6793 LLVMDisposeTargetData(data_layout);
6794 LLVMDisposeMessage(data_layout_str);
6795
6796 enum ac_float_mode float_mode =
6797 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6798 AC_FLOAT_MODE_DEFAULT;
6799
6800 ctx.builder = ac_create_builder(ctx.context, float_mode);
6801 ctx.ac.builder = ctx.builder;
6802
6803 memset(shader_info, 0, sizeof(*shader_info));
6804
6805 for(int i = 0; i < shader_count; ++i)
6806 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6807
6808 for (i = 0; i < AC_UD_MAX_SETS; i++)
6809 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6810 for (i = 0; i < AC_UD_MAX_UD; i++)
6811 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6812
6813 ctx.max_workgroup_size = 0;
6814 for (int i = 0; i < shader_count; ++i) {
6815 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6816 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6817 shaders[i]));
6818 }
6819
6820 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6821 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6822
6823 ctx.abi.inputs = &ctx.inputs[0];
6824 ctx.abi.emit_outputs = handle_shader_outputs_post;
6825 ctx.abi.emit_vertex = visit_emit_vertex;
6826 ctx.abi.load_ubo = radv_load_ubo;
6827 ctx.abi.load_ssbo = radv_load_ssbo;
6828 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6829 ctx.abi.clamp_shadow_reference = false;
6830
6831 if (shader_count >= 2)
6832 ac_init_exec_full_mask(&ctx.ac);
6833
6834 if (ctx.ac.chip_class == GFX9 &&
6835 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6836 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6837
6838 for(int i = 0; i < shader_count; ++i) {
6839 ctx.stage = shaders[i]->info.stage;
6840 ctx.output_mask = 0;
6841 ctx.tess_outputs_written = 0;
6842 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6843 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6844
6845 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6846 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6847 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6848 ctx.abi.load_inputs = load_gs_input;
6849 ctx.abi.emit_primitive = visit_end_primitive;
6850 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6851 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6852 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6853 ctx.abi.load_tess_varyings = load_tcs_varyings;
6854 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6855 ctx.abi.store_tcs_outputs = store_tcs_output;
6856 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6857 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6858 ctx.abi.load_tess_varyings = load_tes_input;
6859 ctx.abi.load_tess_coord = load_tess_coord;
6860 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6861 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6862 if (shader_info->info.vs.needs_instance_id) {
6863 if (ctx.options->key.vs.as_ls) {
6864 ctx.shader_info->vs.vgpr_comp_cnt =
6865 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6866 } else {
6867 ctx.shader_info->vs.vgpr_comp_cnt =
6868 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6869 }
6870 }
6871 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6872 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6873 ctx.abi.lookup_interp_param = lookup_interp_param;
6874 ctx.abi.load_sample_position = load_sample_position;
6875 }
6876
6877 if (i)
6878 emit_barrier(&ctx.ac, ctx.stage);
6879
6880 ac_setup_rings(&ctx);
6881
6882 LLVMBasicBlockRef merge_block;
6883 if (shader_count >= 2) {
6884 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6885 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6886 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6887
6888 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6889 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6890 LLVMConstInt(ctx.ac.i32, 8, false), false);
6891 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6892 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6893 thread_id, count, "");
6894 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6895
6896 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6897 }
6898
6899 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6900 handle_fs_inputs(&ctx, shaders[i]);
6901 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6902 handle_vs_inputs(&ctx, shaders[i]);
6903 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6904 prepare_gs_input_vgprs(&ctx);
6905
6906 nir_foreach_variable(variable, &shaders[i]->outputs)
6907 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6908
6909 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6910
6911 if (shader_count >= 2) {
6912 LLVMBuildBr(ctx.ac.builder, merge_block);
6913 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6914 }
6915
6916 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6917 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6918 shaders[i]->info.cull_distance_array_size > 4;
6919 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6920 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6921 shaders[i]->info.gs.vertices_out;
6922 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6923 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6924 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6925 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6926 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6927 }
6928 }
6929
6930 LLVMBuildRetVoid(ctx.builder);
6931
6932 if (options->dump_preoptir)
6933 ac_dump_module(ctx.module);
6934
6935 ac_llvm_finalize_module(&ctx);
6936
6937 if (shader_count == 1)
6938 ac_nir_eliminate_const_vs_outputs(&ctx);
6939
6940 return ctx.module;
6941 }
6942
6943 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6944 {
6945 unsigned *retval = (unsigned *)context;
6946 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6947 char *description = LLVMGetDiagInfoDescription(di);
6948
6949 if (severity == LLVMDSError) {
6950 *retval = 1;
6951 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6952 description);
6953 }
6954
6955 LLVMDisposeMessage(description);
6956 }
6957
6958 static unsigned ac_llvm_compile(LLVMModuleRef M,
6959 struct ac_shader_binary *binary,
6960 LLVMTargetMachineRef tm)
6961 {
6962 unsigned retval = 0;
6963 char *err;
6964 LLVMContextRef llvm_ctx;
6965 LLVMMemoryBufferRef out_buffer;
6966 unsigned buffer_size;
6967 const char *buffer_data;
6968 LLVMBool mem_err;
6969
6970 /* Setup Diagnostic Handler*/
6971 llvm_ctx = LLVMGetModuleContext(M);
6972
6973 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6974 &retval);
6975
6976 /* Compile IR*/
6977 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6978 &err, &out_buffer);
6979
6980 /* Process Errors/Warnings */
6981 if (mem_err) {
6982 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6983 free(err);
6984 retval = 1;
6985 goto out;
6986 }
6987
6988 /* Extract Shader Code*/
6989 buffer_size = LLVMGetBufferSize(out_buffer);
6990 buffer_data = LLVMGetBufferStart(out_buffer);
6991
6992 ac_elf_read(buffer_data, buffer_size, binary);
6993
6994 /* Clean up */
6995 LLVMDisposeMemoryBuffer(out_buffer);
6996
6997 out:
6998 return retval;
6999 }
7000
7001 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7002 LLVMModuleRef llvm_module,
7003 struct ac_shader_binary *binary,
7004 struct ac_shader_config *config,
7005 struct ac_shader_variant_info *shader_info,
7006 gl_shader_stage stage,
7007 bool dump_shader, bool supports_spill)
7008 {
7009 if (dump_shader)
7010 ac_dump_module(llvm_module);
7011
7012 memset(binary, 0, sizeof(*binary));
7013 int v = ac_llvm_compile(llvm_module, binary, tm);
7014 if (v) {
7015 fprintf(stderr, "compile failed\n");
7016 }
7017
7018 if (dump_shader)
7019 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7020
7021 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7022
7023 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7024 LLVMDisposeModule(llvm_module);
7025 LLVMContextDispose(ctx);
7026
7027 if (stage == MESA_SHADER_FRAGMENT) {
7028 shader_info->num_input_vgprs = 0;
7029 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7030 shader_info->num_input_vgprs += 2;
7031 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7032 shader_info->num_input_vgprs += 2;
7033 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7034 shader_info->num_input_vgprs += 2;
7035 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7036 shader_info->num_input_vgprs += 3;
7037 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7038 shader_info->num_input_vgprs += 2;
7039 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7040 shader_info->num_input_vgprs += 2;
7041 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7042 shader_info->num_input_vgprs += 2;
7043 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7044 shader_info->num_input_vgprs += 1;
7045 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7046 shader_info->num_input_vgprs += 1;
7047 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7048 shader_info->num_input_vgprs += 1;
7049 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7050 shader_info->num_input_vgprs += 1;
7051 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7052 shader_info->num_input_vgprs += 1;
7053 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7054 shader_info->num_input_vgprs += 1;
7055 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7056 shader_info->num_input_vgprs += 1;
7057 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7058 shader_info->num_input_vgprs += 1;
7059 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7060 shader_info->num_input_vgprs += 1;
7061 }
7062 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7063
7064 /* +3 for scratch wave offset and VCC */
7065 config->num_sgprs = MAX2(config->num_sgprs,
7066 shader_info->num_input_sgprs + 3);
7067
7068 /* Enable 64-bit and 16-bit denormals, because there is no performance
7069 * cost.
7070 *
7071 * If denormals are enabled, all floating-point output modifiers are
7072 * ignored.
7073 *
7074 * Don't enable denormals for 32-bit floats, because:
7075 * - Floating-point output modifiers would be ignored by the hw.
7076 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7077 * have to stop using those.
7078 * - SI & CI would be very slow.
7079 */
7080 config->float_mode |= V_00B028_FP_64_DENORMS;
7081 }
7082
7083 static void
7084 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7085 {
7086 switch (nir->info.stage) {
7087 case MESA_SHADER_COMPUTE:
7088 for (int i = 0; i < 3; ++i)
7089 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7090 break;
7091 case MESA_SHADER_FRAGMENT:
7092 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7093 break;
7094 case MESA_SHADER_GEOMETRY:
7095 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7096 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7097 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7098 shader_info->gs.invocations = nir->info.gs.invocations;
7099 break;
7100 case MESA_SHADER_TESS_EVAL:
7101 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7102 shader_info->tes.spacing = nir->info.tess.spacing;
7103 shader_info->tes.ccw = nir->info.tess.ccw;
7104 shader_info->tes.point_mode = nir->info.tess.point_mode;
7105 shader_info->tes.as_es = options->key.tes.as_es;
7106 break;
7107 case MESA_SHADER_TESS_CTRL:
7108 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7109 break;
7110 case MESA_SHADER_VERTEX:
7111 shader_info->vs.as_es = options->key.vs.as_es;
7112 shader_info->vs.as_ls = options->key.vs.as_ls;
7113 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7114 if (options->key.vs.as_ls)
7115 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7116 break;
7117 default:
7118 break;
7119 }
7120 }
7121
7122 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7123 struct ac_shader_binary *binary,
7124 struct ac_shader_config *config,
7125 struct ac_shader_variant_info *shader_info,
7126 struct nir_shader *const *nir,
7127 int nir_count,
7128 const struct ac_nir_compiler_options *options,
7129 bool dump_shader)
7130 {
7131
7132 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7133 options);
7134
7135 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7136 for (int i = 0; i < nir_count; ++i)
7137 ac_fill_shader_info(shader_info, nir[i], options);
7138
7139 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7140 if (options->chip_class == GFX9) {
7141 if (nir_count == 2 &&
7142 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7143 shader_info->gs.es_type = nir[0]->info.stage;
7144 }
7145 }
7146 }
7147
7148 static void
7149 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7150 {
7151 LLVMValueRef vtx_offset =
7152 LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
7153 LLVMConstInt(ctx->ac.i32, 4, false), "");
7154 int idx = 0;
7155
7156 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7157 int length = 4;
7158 int slot = idx;
7159 int slot_inc = 1;
7160 if (!(ctx->output_mask & (1ull << i)))
7161 continue;
7162
7163 if (i == VARYING_SLOT_CLIP_DIST0) {
7164 /* unpack clip and cull from a single set of slots */
7165 length = ctx->num_output_clips + ctx->num_output_culls;
7166 if (length > 4)
7167 slot_inc = 2;
7168 }
7169
7170 for (unsigned j = 0; j < length; j++) {
7171 LLVMValueRef value, soffset;
7172
7173 soffset = LLVMConstInt(ctx->ac.i32,
7174 (slot * 4 + j) *
7175 ctx->gs_max_out_vertices * 16 * 4, false);
7176
7177 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7178 1, ctx->ac.i32_0,
7179 vtx_offset, soffset,
7180 0, 1, 1, true, false);
7181
7182 LLVMBuildStore(ctx->builder,
7183 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7184 }
7185 idx += slot_inc;
7186 }
7187 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7188 }
7189
7190 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7191 struct nir_shader *geom_shader,
7192 struct ac_shader_binary *binary,
7193 struct ac_shader_config *config,
7194 struct ac_shader_variant_info *shader_info,
7195 const struct ac_nir_compiler_options *options,
7196 bool dump_shader)
7197 {
7198 struct nir_to_llvm_context ctx = {0};
7199 ctx.context = LLVMContextCreate();
7200 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7201 ctx.options = options;
7202 ctx.shader_info = shader_info;
7203
7204 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7205 options->family);
7206 ctx.ac.module = ctx.module;
7207
7208 ctx.is_gs_copy_shader = true;
7209 LLVMSetTarget(ctx.module, "amdgcn--");
7210
7211 enum ac_float_mode float_mode =
7212 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7213 AC_FLOAT_MODE_DEFAULT;
7214
7215 ctx.builder = ac_create_builder(ctx.context, float_mode);
7216 ctx.ac.builder = ctx.builder;
7217 ctx.stage = MESA_SHADER_VERTEX;
7218
7219 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7220
7221 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7222 ac_setup_rings(&ctx);
7223
7224 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7225 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7226
7227 struct ac_nir_context nir_ctx = {};
7228 nir_ctx.ac = ctx.ac;
7229 nir_ctx.abi = &ctx.abi;
7230
7231 nir_ctx.nctx = &ctx;
7232 ctx.nir = &nir_ctx;
7233
7234 nir_foreach_variable(variable, &geom_shader->outputs) {
7235 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7236 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7237 }
7238
7239 ac_gs_copy_shader_emit(&ctx);
7240
7241 ctx.nir = NULL;
7242
7243 LLVMBuildRetVoid(ctx.builder);
7244
7245 ac_llvm_finalize_module(&ctx);
7246
7247 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7248 MESA_SHADER_VERTEX,
7249 dump_shader, options->supports_spill);
7250 }