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ac: remove ac_shader_variant_info::fs::output_mask
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.loads_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
604 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
605
606 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
607 user_sgpr_info->sgpr_count += 2;
608 user_sgpr_info->indirect_all_descriptor_sets = true;
609 } else {
610 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
611 }
612 }
613
614 static void
615 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 const struct user_sgpr_info *user_sgpr_info,
620 struct arg_info *args,
621 LLVMValueRef *desc_sets)
622 {
623 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
624 unsigned num_sets = ctx->options->layout ?
625 ctx->options->layout->num_sets : 0;
626 unsigned stage_mask = 1 << stage;
627
628 if (has_previous_stage)
629 stage_mask |= 1 << previous_stage;
630
631 /* 1 for each descriptor set */
632 if (!user_sgpr_info->indirect_all_descriptor_sets) {
633 for (unsigned i = 0; i < num_sets; ++i) {
634 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
635 add_array_arg(args, type,
636 &ctx->descriptor_sets[i]);
637 }
638 }
639 } else {
640 add_array_arg(args, const_array(type, 32), desc_sets);
641 }
642
643 if (ctx->shader_info->info.loads_push_constants) {
644 /* 1 for push constants and dynamic descriptors */
645 add_array_arg(args, type, &ctx->push_constants);
646 }
647 }
648
649 static void
650 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
651 gl_shader_stage stage,
652 bool has_previous_stage,
653 gl_shader_stage previous_stage,
654 struct arg_info *args)
655 {
656 if (!ctx->is_gs_copy_shader &&
657 (stage == MESA_SHADER_VERTEX ||
658 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
659 if (ctx->shader_info->info.vs.has_vertex_buffers) {
660 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
661 &ctx->vertex_buffers);
662 }
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
665 if (ctx->shader_info->info.vs.needs_draw_id) {
666 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
667 }
668 }
669 }
670
671 static void
672 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
675 if (!ctx->is_gs_copy_shader) {
676 if (ctx->options->key.vs.as_ls) {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 } else {
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
682 }
683 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
684 }
685 }
686
687 static void
688 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
689 {
690 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
691 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
692 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
693 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
694 }
695
696 static void
697 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
698 bool has_previous_stage, gl_shader_stage previous_stage,
699 const struct user_sgpr_info *user_sgpr_info,
700 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
701 {
702 unsigned num_sets = ctx->options->layout ?
703 ctx->options->layout->num_sets : 0;
704 unsigned stage_mask = 1 << stage;
705
706 if (has_previous_stage)
707 stage_mask |= 1 << previous_stage;
708
709 if (!user_sgpr_info->indirect_all_descriptor_sets) {
710 for (unsigned i = 0; i < num_sets; ++i) {
711 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
712 set_loc_desc(ctx, i, user_sgpr_idx, 0);
713 } else
714 ctx->descriptor_sets[i] = NULL;
715 }
716 } else {
717 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
718 user_sgpr_idx, 2);
719
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
722 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
723 ctx->descriptor_sets[i] =
724 ac_build_load_to_sgpr(&ctx->ac,
725 desc_sets,
726 LLVMConstInt(ctx->ac.i32, i, false));
727
728 } else
729 ctx->descriptor_sets[i] = NULL;
730 }
731 ctx->shader_info->need_indirect_descriptor_sets = true;
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
736 }
737 }
738
739 static void
740 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
741 gl_shader_stage stage, bool has_previous_stage,
742 gl_shader_stage previous_stage,
743 uint8_t *user_sgpr_idx)
744 {
745 if (!ctx->is_gs_copy_shader &&
746 (stage == MESA_SHADER_VERTEX ||
747 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
748 if (ctx->shader_info->info.vs.has_vertex_buffers) {
749 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
750 user_sgpr_idx, 2);
751 }
752
753 unsigned vs_num = 2;
754 if (ctx->shader_info->info.vs.needs_draw_id)
755 vs_num++;
756
757 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
758 user_sgpr_idx, vs_num);
759 }
760 }
761
762 static void create_function(struct nir_to_llvm_context *ctx,
763 gl_shader_stage stage,
764 bool has_previous_stage,
765 gl_shader_stage previous_stage)
766 {
767 uint8_t user_sgpr_idx;
768 struct user_sgpr_info user_sgpr_info;
769 struct arg_info args = {};
770 LLVMValueRef desc_sets;
771
772 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
773
774 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
775 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
776 &ctx->ring_offsets);
777 }
778
779 switch (stage) {
780 case MESA_SHADER_COMPUTE:
781 declare_global_input_sgprs(ctx, stage, has_previous_stage,
782 previous_stage, &user_sgpr_info,
783 &args, &desc_sets);
784
785 if (ctx->shader_info->info.cs.uses_grid_size) {
786 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
787 &ctx->num_work_groups);
788 }
789
790 for (int i = 0; i < 3; i++) {
791 ctx->workgroup_ids[i] = NULL;
792 if (ctx->shader_info->info.cs.uses_block_id[i]) {
793 add_arg(&args, ARG_SGPR, ctx->ac.i32,
794 &ctx->workgroup_ids[i]);
795 }
796 }
797
798 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
799 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
800 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
801 &ctx->local_invocation_ids);
802 break;
803 case MESA_SHADER_VERTEX:
804 declare_global_input_sgprs(ctx, stage, has_previous_stage,
805 previous_stage, &user_sgpr_info,
806 &args, &desc_sets);
807 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
808 previous_stage, &args);
809
810 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
812 if (ctx->options->key.vs.as_es)
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->es2gs_offset);
815 else if (ctx->options->key.vs.as_ls)
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->ls_out_layout);
818
819 declare_vs_input_vgprs(ctx, &args);
820 break;
821 case MESA_SHADER_TESS_CTRL:
822 if (has_previous_stage) {
823 // First 6 system regs
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->merged_wave_info);
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tess_factor_offset);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
831 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
832 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
833
834 declare_global_input_sgprs(ctx, stage,
835 has_previous_stage,
836 previous_stage,
837 &user_sgpr_info, &args,
838 &desc_sets);
839 declare_vs_specific_input_sgprs(ctx, stage,
840 has_previous_stage,
841 previous_stage, &args);
842
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->ls_out_layout);
845
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_offchip_layout);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_offsets);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_out_layout);
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_in_layout);
854 if (ctx->shader_info->info.needs_multiview_view_index)
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->view_index);
857
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_patch_id);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_rel_ids);
862
863 declare_vs_input_vgprs(ctx, &args);
864 } else {
865 declare_global_input_sgprs(ctx, stage,
866 has_previous_stage,
867 previous_stage,
868 &user_sgpr_info, &args,
869 &desc_sets);
870
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_offchip_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_offsets);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_out_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_in_layout);
879 if (ctx->shader_info->info.needs_multiview_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->view_index);
882
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->tess_factor_offset);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_patch_id);
888 add_arg(&args, ARG_VGPR, ctx->ac.i32,
889 &ctx->abi.tcs_rel_ids);
890 }
891 break;
892 case MESA_SHADER_TESS_EVAL:
893 declare_global_input_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, &user_sgpr_info,
895 &args, &desc_sets);
896
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
898 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
900
901 if (ctx->options->key.tes.as_es) {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->es2gs_offset);
906 } else {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
909 }
910 declare_tes_input_vgprs(ctx, &args);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 if (has_previous_stage) {
914 // First 6 system regs
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->gs2vs_offset);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->merged_wave_info);
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
920
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
924
925 declare_global_input_sgprs(ctx, stage,
926 has_previous_stage,
927 previous_stage,
928 &user_sgpr_info, &args,
929 &desc_sets);
930
931 if (previous_stage == MESA_SHADER_TESS_EVAL) {
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->tcs_offchip_layout);
934 } else {
935 declare_vs_specific_input_sgprs(ctx, stage,
936 has_previous_stage,
937 previous_stage,
938 &args);
939 }
940
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_ring_stride);
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->gsvs_num_entries);
945 if (ctx->shader_info->info.needs_multiview_view_index)
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->view_index);
948
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[0]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[2]);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_prim_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.gs_invocation_id);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32,
958 &ctx->gs_vtx_offset[4]);
959
960 if (previous_stage == MESA_SHADER_VERTEX) {
961 declare_vs_input_vgprs(ctx, &args);
962 } else {
963 declare_tes_input_vgprs(ctx, &args);
964 }
965 } else {
966 declare_global_input_sgprs(ctx, stage,
967 has_previous_stage,
968 previous_stage,
969 &user_sgpr_info, &args,
970 &desc_sets);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_ring_stride);
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->gsvs_num_entries);
976 if (ctx->shader_info->info.needs_multiview_view_index)
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->view_index);
979
980 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[0]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[1]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->abi.gs_prim_id);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[2]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[3]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[4]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->gs_vtx_offset[5]);
996 add_arg(&args, ARG_VGPR, ctx->ac.i32,
997 &ctx->abi.gs_invocation_id);
998 }
999 break;
1000 case MESA_SHADER_FRAGMENT:
1001 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1002 previous_stage, &user_sgpr_info,
1003 &args, &desc_sets);
1004
1005 if (ctx->shader_info->info.ps.needs_sample_positions)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->sample_pos_offset);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1016 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1026 break;
1027 default:
1028 unreachable("Shader stage not implemented");
1029 }
1030
1031 ctx->main_function = create_llvm_function(
1032 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1033 ctx->max_workgroup_size,
1034 ctx->options->unsafe_math);
1035 set_llvm_calling_convention(ctx->main_function, stage);
1036
1037
1038 ctx->shader_info->num_input_vgprs = 0;
1039 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1040
1041 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1042
1043 if (ctx->stage != MESA_SHADER_FRAGMENT)
1044 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1045
1046 assign_arguments(ctx->main_function, &args);
1047
1048 user_sgpr_idx = 0;
1049
1050 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1051 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1052 &user_sgpr_idx, 2);
1053 if (ctx->options->supports_spill) {
1054 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1055 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1056 NULL, 0, AC_FUNC_ATTR_READNONE);
1057 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1058 const_array(ctx->ac.v4i32, 16), "");
1059 }
1060 }
1061
1062 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1063 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1064 if (has_previous_stage)
1065 user_sgpr_idx = 0;
1066
1067 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1068 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1069
1070 switch (stage) {
1071 case MESA_SHADER_COMPUTE:
1072 if (ctx->shader_info->info.cs.uses_grid_size) {
1073 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1074 &user_sgpr_idx, 3);
1075 }
1076 break;
1077 case MESA_SHADER_VERTEX:
1078 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1079 previous_stage, &user_sgpr_idx);
1080 if (ctx->view_index)
1081 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1082 if (ctx->options->key.vs.as_ls) {
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 }
1086 if (ctx->options->key.vs.as_ls)
1087 ac_declare_lds_as_pointer(&ctx->ac);
1088 break;
1089 case MESA_SHADER_TESS_CTRL:
1090 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1091 previous_stage, &user_sgpr_idx);
1092 if (has_previous_stage)
1093 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1094 &user_sgpr_idx, 1);
1095 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 ac_declare_lds_as_pointer(&ctx->ac);
1099 break;
1100 case MESA_SHADER_TESS_EVAL:
1101 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1102 if (ctx->view_index)
1103 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1104 break;
1105 case MESA_SHADER_GEOMETRY:
1106 if (has_previous_stage) {
1107 if (previous_stage == MESA_SHADER_VERTEX)
1108 set_vs_specific_input_locs(ctx, stage,
1109 has_previous_stage,
1110 previous_stage,
1111 &user_sgpr_idx);
1112 else
1113 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1114 &user_sgpr_idx, 1);
1115 }
1116 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1117 &user_sgpr_idx, 2);
1118 if (ctx->view_index)
1119 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1120 if (has_previous_stage)
1121 ac_declare_lds_as_pointer(&ctx->ac);
1122 break;
1123 case MESA_SHADER_FRAGMENT:
1124 if (ctx->shader_info->info.ps.needs_sample_positions) {
1125 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1126 &user_sgpr_idx, 1);
1127 }
1128 break;
1129 default:
1130 unreachable("Shader stage not implemented");
1131 }
1132
1133 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1134 }
1135
1136 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1137 LLVMValueRef value, unsigned count)
1138 {
1139 unsigned num_components = ac_get_llvm_num_components(value);
1140 if (count == num_components)
1141 return value;
1142
1143 LLVMValueRef masks[] = {
1144 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1145 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1146
1147 if (count == 1)
1148 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1149 "");
1150
1151 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1152 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1153 }
1154
1155 static void
1156 build_store_values_extended(struct ac_llvm_context *ac,
1157 LLVMValueRef *values,
1158 unsigned value_count,
1159 unsigned value_stride,
1160 LLVMValueRef vec)
1161 {
1162 LLVMBuilderRef builder = ac->builder;
1163 unsigned i;
1164
1165 for (i = 0; i < value_count; i++) {
1166 LLVMValueRef ptr = values[i * value_stride];
1167 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1168 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1169 LLVMBuildStore(builder, value, ptr);
1170 }
1171 }
1172
1173 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1174 const nir_ssa_def *def)
1175 {
1176 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1177 if (def->num_components > 1) {
1178 type = LLVMVectorType(type, def->num_components);
1179 }
1180 return type;
1181 }
1182
1183 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1184 {
1185 assert(src.is_ssa);
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1187 return (LLVMValueRef)entry->data;
1188 }
1189
1190
1191 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1192 const struct nir_block *b)
1193 {
1194 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1195 return (LLVMBasicBlockRef)entry->data;
1196 }
1197
1198 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1199 nir_alu_src src,
1200 unsigned num_components)
1201 {
1202 LLVMValueRef value = get_src(ctx, src.src);
1203 bool need_swizzle = false;
1204
1205 assert(value);
1206 LLVMTypeRef type = LLVMTypeOf(value);
1207 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1208 ? LLVMGetVectorSize(type)
1209 : 1;
1210
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1321 }
1322
1323 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1324 LLVMIntPredicate pred,
1325 LLVMValueRef src0, LLVMValueRef src1)
1326 {
1327 return LLVMBuildSelect(ctx->builder,
1328 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1329 src0,
1330 src1, "");
1331
1332 }
1333 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1337 LLVMBuildNeg(ctx->builder, src0, ""));
1338 }
1339
1340 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0,
1342 unsigned bitsize)
1343 {
1344 LLVMValueRef cmp, val, zero, one;
1345 LLVMTypeRef type;
1346
1347 if (bitsize == 32) {
1348 type = ctx->f32;
1349 zero = ctx->f32_0;
1350 one = ctx->f32_1;
1351 } else {
1352 type = ctx->f64;
1353 zero = ctx->f64_0;
1354 one = ctx->f64_1;
1355 }
1356
1357 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1359 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1360 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1361 return val;
1362 }
1363
1364 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0, unsigned bitsize)
1366 {
1367 LLVMValueRef cmp, val, zero, one;
1368 LLVMTypeRef type;
1369
1370 if (bitsize == 32) {
1371 type = ctx->i32;
1372 zero = ctx->i32_0;
1373 one = ctx->i32_1;
1374 } else {
1375 type = ctx->i64;
1376 zero = ctx->i64_0;
1377 one = ctx->i64_1;
1378 }
1379
1380 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1381 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1382 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1383 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1384 return val;
1385 }
1386
1387 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1388 LLVMValueRef src0)
1389 {
1390 const char *intr = "llvm.floor.f32";
1391 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1392 LLVMValueRef params[] = {
1393 fsrc0,
1394 };
1395 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1396 ctx->f32, params, 1,
1397 AC_FUNC_ATTR_READNONE);
1398 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1399 }
1400
1401 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1402 const char *intrin,
1403 LLVMValueRef src0, LLVMValueRef src1)
1404 {
1405 LLVMTypeRef ret_type;
1406 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1407 LLVMValueRef res;
1408 LLVMValueRef params[] = { src0, src1 };
1409 ret_type = LLVMStructTypeInContext(ctx->context, types,
1410 2, true);
1411
1412 res = ac_build_intrinsic(ctx, intrin, ret_type,
1413 params, 2, AC_FUNC_ATTR_READNONE);
1414
1415 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1416 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1417 return res;
1418 }
1419
1420 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1421 LLVMValueRef src0)
1422 {
1423 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1424 }
1425
1426 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 src0 = ac_to_float(ctx, src0);
1430 return LLVMBuildSExt(ctx->builder,
1431 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1432 ctx->i32, "");
1433 }
1434
1435 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1436 LLVMValueRef src0,
1437 unsigned bitsize)
1438 {
1439 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1440
1441 if (bitsize == 32)
1442 return result;
1443
1444 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1445 }
1446
1447 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1448 LLVMValueRef src0)
1449 {
1450 return LLVMBuildSExt(ctx->builder,
1451 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1452 ctx->i32, "");
1453 }
1454
1455 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1456 LLVMValueRef src0)
1457 {
1458 LLVMValueRef result;
1459 LLVMValueRef cond = NULL;
1460
1461 src0 = ac_to_float(&ctx->ac, src0);
1462 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1463
1464 if (ctx->options->chip_class >= VI) {
1465 LLVMValueRef args[2];
1466 /* Check if the result is a denormal - and flush to 0 if so. */
1467 args[0] = result;
1468 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1469 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1470 }
1471
1472 /* need to convert back up to f32 */
1473 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1474
1475 if (ctx->options->chip_class >= VI)
1476 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1477 else {
1478 /* for SI/CIK */
1479 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1480 * so compare the result and flush to 0 if it's smaller.
1481 */
1482 LLVMValueRef temp, cond2;
1483 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1484 ctx->ac.f32, result);
1485 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1486 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1487 temp, "");
1488 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1489 temp, ctx->ac.f32_0, "");
1490 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1491 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1492 }
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1523 bool is_signed,
1524 const LLVMValueRef srcs[3])
1525 {
1526 LLVMValueRef result;
1527 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1528
1529 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1530 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1531 return result;
1532 }
1533
1534 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1535 LLVMValueRef src0, LLVMValueRef src1,
1536 LLVMValueRef src2, LLVMValueRef src3)
1537 {
1538 LLVMValueRef bfi_args[3], result;
1539
1540 bfi_args[0] = LLVMBuildShl(ctx->builder,
1541 LLVMBuildSub(ctx->builder,
1542 LLVMBuildShl(ctx->builder,
1543 ctx->i32_1,
1544 src3, ""),
1545 ctx->i32_1, ""),
1546 src2, "");
1547 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1548 bfi_args[2] = src0;
1549
1550 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1551
1552 /* Calculate:
1553 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1554 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1555 */
1556 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1557 LLVMBuildAnd(ctx->builder, bfi_args[0],
1558 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1559
1560 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1561 return result;
1562 }
1563
1564 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1565 LLVMValueRef src0)
1566 {
1567 LLVMValueRef comp[2];
1568
1569 src0 = ac_to_float(ctx, src0);
1570 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1571 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1572
1573 return ac_build_cvt_pkrtz_f16(ctx, comp);
1574 }
1575
1576 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1577 LLVMValueRef src0)
1578 {
1579 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1580 LLVMValueRef temps[2], result, val;
1581 int i;
1582
1583 for (i = 0; i < 2; i++) {
1584 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1585 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1586 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1587 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1588 }
1589
1590 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1591 ctx->i32_0, "");
1592 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1593 ctx->i32_1, "");
1594 return result;
1595 }
1596
1597 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1598 nir_op op,
1599 LLVMValueRef src0)
1600 {
1601 unsigned mask;
1602 int idx;
1603 LLVMValueRef result;
1604
1605 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1606 mask = AC_TID_MASK_LEFT;
1607 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1608 mask = AC_TID_MASK_TOP;
1609 else
1610 mask = AC_TID_MASK_TOP_LEFT;
1611
1612 /* for DDX we want to next X pixel, DDY next Y pixel. */
1613 if (op == nir_op_fddx_fine ||
1614 op == nir_op_fddx_coarse ||
1615 op == nir_op_fddx)
1616 idx = 1;
1617 else
1618 idx = 2;
1619
1620 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1621 return result;
1622 }
1623
1624 /*
1625 * this takes an I,J coordinate pair,
1626 * and works out the X and Y derivatives.
1627 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1628 */
1629 static LLVMValueRef emit_ddxy_interp(
1630 struct ac_nir_context *ctx,
1631 LLVMValueRef interp_ij)
1632 {
1633 LLVMValueRef result[4], a;
1634 unsigned i;
1635
1636 for (i = 0; i < 2; i++) {
1637 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1638 LLVMConstInt(ctx->ac.i32, i, false), "");
1639 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1640 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1641 }
1642 return ac_build_gather_values(&ctx->ac, result, 4);
1643 }
1644
1645 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1646 {
1647 LLVMValueRef src[4], result = NULL;
1648 unsigned num_components = instr->dest.dest.ssa.num_components;
1649 unsigned src_components;
1650 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1651
1652 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1653 switch (instr->op) {
1654 case nir_op_vec2:
1655 case nir_op_vec3:
1656 case nir_op_vec4:
1657 src_components = 1;
1658 break;
1659 case nir_op_pack_half_2x16:
1660 src_components = 2;
1661 break;
1662 case nir_op_unpack_half_2x16:
1663 src_components = 1;
1664 break;
1665 default:
1666 src_components = num_components;
1667 break;
1668 }
1669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1670 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1671
1672 switch (instr->op) {
1673 case nir_op_fmov:
1674 case nir_op_imov:
1675 result = src[0];
1676 break;
1677 case nir_op_fneg:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1680 break;
1681 case nir_op_ineg:
1682 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1683 break;
1684 case nir_op_inot:
1685 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_iadd:
1688 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_fadd:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fsub:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_isub:
1701 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_imul:
1704 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_imod:
1707 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_umod:
1710 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_fmod:
1713 src[0] = ac_to_float(&ctx->ac, src[0]);
1714 src[1] = ac_to_float(&ctx->ac, src[1]);
1715 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1717 ac_to_float_type(&ctx->ac, def_type), result);
1718 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1719 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1720 break;
1721 case nir_op_frem:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_irem:
1727 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_idiv:
1730 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_udiv:
1733 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_fmul:
1736 src[0] = ac_to_float(&ctx->ac, src[0]);
1737 src[1] = ac_to_float(&ctx->ac, src[1]);
1738 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_fdiv:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 src[1] = ac_to_float(&ctx->ac, src[1]);
1743 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1744 break;
1745 case nir_op_frcp:
1746 src[0] = ac_to_float(&ctx->ac, src[0]);
1747 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1748 src[0]);
1749 break;
1750 case nir_op_iand:
1751 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_ior:
1754 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1755 break;
1756 case nir_op_ixor:
1757 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1758 break;
1759 case nir_op_ishl:
1760 result = LLVMBuildShl(ctx->ac.builder, src[0],
1761 LLVMBuildZExt(ctx->ac.builder, src[1],
1762 LLVMTypeOf(src[0]), ""),
1763 "");
1764 break;
1765 case nir_op_ishr:
1766 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1767 LLVMBuildZExt(ctx->ac.builder, src[1],
1768 LLVMTypeOf(src[0]), ""),
1769 "");
1770 break;
1771 case nir_op_ushr:
1772 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1773 LLVMBuildZExt(ctx->ac.builder, src[1],
1774 LLVMTypeOf(src[0]), ""),
1775 "");
1776 break;
1777 case nir_op_ilt:
1778 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1779 break;
1780 case nir_op_ine:
1781 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1782 break;
1783 case nir_op_ieq:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1785 break;
1786 case nir_op_ige:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1788 break;
1789 case nir_op_ult:
1790 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1791 break;
1792 case nir_op_uge:
1793 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1794 break;
1795 case nir_op_feq:
1796 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1797 break;
1798 case nir_op_fne:
1799 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1800 break;
1801 case nir_op_flt:
1802 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1803 break;
1804 case nir_op_fge:
1805 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1806 break;
1807 case nir_op_fabs:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1809 ac_to_float_type(&ctx->ac, def_type), src[0]);
1810 break;
1811 case nir_op_iabs:
1812 result = emit_iabs(&ctx->ac, src[0]);
1813 break;
1814 case nir_op_imax:
1815 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1816 break;
1817 case nir_op_imin:
1818 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1819 break;
1820 case nir_op_umax:
1821 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1822 break;
1823 case nir_op_umin:
1824 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1825 break;
1826 case nir_op_isign:
1827 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1828 break;
1829 case nir_op_fsign:
1830 src[0] = ac_to_float(&ctx->ac, src[0]);
1831 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1832 break;
1833 case nir_op_ffloor:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_ftrunc:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fceil:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_fround_even:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1847 ac_to_float_type(&ctx->ac, def_type),src[0]);
1848 break;
1849 case nir_op_ffract:
1850 result = emit_ffract(&ctx->ac, src[0]);
1851 break;
1852 case nir_op_fsin:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1854 ac_to_float_type(&ctx->ac, def_type), src[0]);
1855 break;
1856 case nir_op_fcos:
1857 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1858 ac_to_float_type(&ctx->ac, def_type), src[0]);
1859 break;
1860 case nir_op_fsqrt:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fexp2:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_flog2:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_frsq:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1876 result);
1877 break;
1878 case nir_op_fpow:
1879 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1880 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1881 break;
1882 case nir_op_fmax:
1883 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1884 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1885 if (instr->dest.dest.ssa.bit_size == 32)
1886 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1887 ac_to_float_type(&ctx->ac, def_type),
1888 result);
1889 break;
1890 case nir_op_fmin:
1891 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1892 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1893 if (instr->dest.dest.ssa.bit_size == 32)
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1895 ac_to_float_type(&ctx->ac, def_type),
1896 result);
1897 break;
1898 case nir_op_ffma:
1899 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1900 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1901 break;
1902 case nir_op_ibitfield_extract:
1903 result = emit_bitfield_extract(&ctx->ac, true, src);
1904 break;
1905 case nir_op_ubitfield_extract:
1906 result = emit_bitfield_extract(&ctx->ac, false, src);
1907 break;
1908 case nir_op_bitfield_insert:
1909 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1910 break;
1911 case nir_op_bitfield_reverse:
1912 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1913 break;
1914 case nir_op_bit_count:
1915 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1916 break;
1917 case nir_op_vec2:
1918 case nir_op_vec3:
1919 case nir_op_vec4:
1920 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1921 src[i] = ac_to_integer(&ctx->ac, src[i]);
1922 result = ac_build_gather_values(&ctx->ac, src, num_components);
1923 break;
1924 case nir_op_f2i32:
1925 case nir_op_f2i64:
1926 src[0] = ac_to_float(&ctx->ac, src[0]);
1927 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1928 break;
1929 case nir_op_f2u32:
1930 case nir_op_f2u64:
1931 src[0] = ac_to_float(&ctx->ac, src[0]);
1932 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1933 break;
1934 case nir_op_i2f32:
1935 case nir_op_i2f64:
1936 src[0] = ac_to_integer(&ctx->ac, src[0]);
1937 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1938 break;
1939 case nir_op_u2f32:
1940 case nir_op_u2f64:
1941 src[0] = ac_to_integer(&ctx->ac, src[0]);
1942 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1943 break;
1944 case nir_op_f2f64:
1945 src[0] = ac_to_float(&ctx->ac, src[0]);
1946 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1947 break;
1948 case nir_op_f2f32:
1949 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1950 break;
1951 case nir_op_u2u32:
1952 case nir_op_u2u64:
1953 src[0] = ac_to_integer(&ctx->ac, src[0]);
1954 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1955 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1956 else
1957 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1958 break;
1959 case nir_op_i2i32:
1960 case nir_op_i2i64:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1963 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1964 else
1965 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1966 break;
1967 case nir_op_bcsel:
1968 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1969 break;
1970 case nir_op_find_lsb:
1971 src[0] = ac_to_integer(&ctx->ac, src[0]);
1972 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1973 break;
1974 case nir_op_ufind_msb:
1975 src[0] = ac_to_integer(&ctx->ac, src[0]);
1976 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1977 break;
1978 case nir_op_ifind_msb:
1979 src[0] = ac_to_integer(&ctx->ac, src[0]);
1980 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1981 break;
1982 case nir_op_uadd_carry:
1983 src[0] = ac_to_integer(&ctx->ac, src[0]);
1984 src[1] = ac_to_integer(&ctx->ac, src[1]);
1985 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1986 break;
1987 case nir_op_usub_borrow:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 src[1] = ac_to_integer(&ctx->ac, src[1]);
1990 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1991 break;
1992 case nir_op_b2f:
1993 result = emit_b2f(&ctx->ac, src[0]);
1994 break;
1995 case nir_op_f2b:
1996 result = emit_f2b(&ctx->ac, src[0]);
1997 break;
1998 case nir_op_b2i:
1999 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2000 break;
2001 case nir_op_i2b:
2002 src[0] = ac_to_integer(&ctx->ac, src[0]);
2003 result = emit_i2b(&ctx->ac, src[0]);
2004 break;
2005 case nir_op_fquantize2f16:
2006 result = emit_f2f16(ctx->nctx, src[0]);
2007 break;
2008 case nir_op_umul_high:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 src[1] = ac_to_integer(&ctx->ac, src[1]);
2011 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2012 break;
2013 case nir_op_imul_high:
2014 src[0] = ac_to_integer(&ctx->ac, src[0]);
2015 src[1] = ac_to_integer(&ctx->ac, src[1]);
2016 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2017 break;
2018 case nir_op_pack_half_2x16:
2019 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2020 break;
2021 case nir_op_unpack_half_2x16:
2022 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_fddx:
2025 case nir_op_fddy:
2026 case nir_op_fddx_fine:
2027 case nir_op_fddy_fine:
2028 case nir_op_fddx_coarse:
2029 case nir_op_fddy_coarse:
2030 result = emit_ddxy(ctx, instr->op, src[0]);
2031 break;
2032
2033 case nir_op_unpack_64_2x32_split_x: {
2034 assert(instr->src[0].src.ssa->num_components == 1);
2035 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2036 ctx->ac.v2i32,
2037 "");
2038 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2039 ctx->ac.i32_0, "");
2040 break;
2041 }
2042
2043 case nir_op_unpack_64_2x32_split_y: {
2044 assert(instr->src[0].src.ssa->num_components == 1);
2045 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2046 ctx->ac.v2i32,
2047 "");
2048 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2049 ctx->ac.i32_1, "");
2050 break;
2051 }
2052
2053 case nir_op_pack_64_2x32_split: {
2054 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2055 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2056 src[0], ctx->ac.i32_0, "");
2057 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2058 src[1], ctx->ac.i32_1, "");
2059 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2060 break;
2061 }
2062
2063 default:
2064 fprintf(stderr, "Unknown NIR alu instr: ");
2065 nir_print_instr(&instr->instr, stderr);
2066 fprintf(stderr, "\n");
2067 abort();
2068 }
2069
2070 if (result) {
2071 assert(instr->dest.dest.is_ssa);
2072 result = ac_to_integer(&ctx->ac, result);
2073 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2074 result);
2075 }
2076 }
2077
2078 static void visit_load_const(struct ac_nir_context *ctx,
2079 const nir_load_const_instr *instr)
2080 {
2081 LLVMValueRef values[4], value = NULL;
2082 LLVMTypeRef element_type =
2083 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2084
2085 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2086 switch (instr->def.bit_size) {
2087 case 32:
2088 values[i] = LLVMConstInt(element_type,
2089 instr->value.u32[i], false);
2090 break;
2091 case 64:
2092 values[i] = LLVMConstInt(element_type,
2093 instr->value.u64[i], false);
2094 break;
2095 default:
2096 fprintf(stderr,
2097 "unsupported nir load_const bit_size: %d\n",
2098 instr->def.bit_size);
2099 abort();
2100 }
2101 }
2102 if (instr->def.num_components > 1) {
2103 value = LLVMConstVector(values, instr->def.num_components);
2104 } else
2105 value = values[0];
2106
2107 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2108 }
2109
2110 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2111 LLVMTypeRef type)
2112 {
2113 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2114 return LLVMBuildBitCast(ctx->builder, ptr,
2115 LLVMPointerType(type, addr_space), "");
2116 }
2117
2118 static LLVMValueRef
2119 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2120 {
2121 LLVMValueRef size =
2122 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2123 LLVMConstInt(ctx->ac.i32, 2, false), "");
2124
2125 /* VI only */
2126 if (ctx->ac.chip_class == VI && in_elements) {
2127 /* On VI, the descriptor contains the size in bytes,
2128 * but TXQ must return the size in elements.
2129 * The stride is always non-zero for resources using TXQ.
2130 */
2131 LLVMValueRef stride =
2132 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2133 ctx->ac.i32_1, "");
2134 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2135 LLVMConstInt(ctx->ac.i32, 16, false), "");
2136 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2137 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2138
2139 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2140 }
2141 return size;
2142 }
2143
2144 /**
2145 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2146 * intrinsic names).
2147 */
2148 static void build_int_type_name(
2149 LLVMTypeRef type,
2150 char *buf, unsigned bufsize)
2151 {
2152 assert(bufsize >= 6);
2153
2154 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2155 snprintf(buf, bufsize, "v%ui32",
2156 LLVMGetVectorSize(type));
2157 else
2158 strcpy(buf, "i32");
2159 }
2160
2161 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2162 struct ac_image_args *args,
2163 const nir_tex_instr *instr)
2164 {
2165 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2166 LLVMValueRef coord = args->addr;
2167 LLVMValueRef half_texel[2];
2168 LLVMValueRef compare_cube_wa = NULL;
2169 LLVMValueRef result;
2170 int c;
2171 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2172
2173 //TODO Rect
2174 {
2175 struct ac_image_args txq_args = { 0 };
2176
2177 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2178 txq_args.opcode = ac_image_get_resinfo;
2179 txq_args.dmask = 0xf;
2180 txq_args.addr = ctx->i32_0;
2181 txq_args.resource = args->resource;
2182 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2183
2184 for (c = 0; c < 2; c++) {
2185 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2186 LLVMConstInt(ctx->i32, c, false), "");
2187 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2188 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2189 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2190 LLVMConstReal(ctx->f32, -0.5), "");
2191 }
2192 }
2193
2194 LLVMValueRef orig_coords = args->addr;
2195
2196 for (c = 0; c < 2; c++) {
2197 LLVMValueRef tmp;
2198 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2199 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2200 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2201 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2202 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2203 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2204 }
2205
2206
2207 /*
2208 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2209 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2210 * workaround by sampling using a scaled type and converting.
2211 * This is taken from amdgpu-pro shaders.
2212 */
2213 /* NOTE this produces some ugly code compared to amdgpu-pro,
2214 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2215 * and then reads them back. -pro generates two selects,
2216 * one s_cmp for the descriptor rewriting
2217 * one v_cmp for the coordinate and result changes.
2218 */
2219 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2220 LLVMValueRef tmp, tmp2;
2221
2222 /* workaround 8/8/8/8 uint/sint cube gather bug */
2223 /* first detect it then change to a scaled read and f2i */
2224 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2225 tmp2 = tmp;
2226
2227 /* extract the DATA_FORMAT */
2228 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2229 LLVMConstInt(ctx->i32, 6, false), false);
2230
2231 /* is the DATA_FORMAT == 8_8_8_8 */
2232 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2233
2234 if (stype == GLSL_TYPE_UINT)
2235 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2236 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2237 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2238 else
2239 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2240 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2241 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2242
2243 /* replace the NUM FORMAT in the descriptor */
2244 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2245 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2246
2247 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2248
2249 /* don't modify the coordinates for this case */
2250 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2251 }
2252 args->addr = coord;
2253 result = ac_build_image_opcode(ctx, args);
2254
2255 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2256 LLVMValueRef tmp, tmp2;
2257
2258 /* if the cube workaround is in place, f2i the result. */
2259 for (c = 0; c < 4; c++) {
2260 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2261 if (stype == GLSL_TYPE_UINT)
2262 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2263 else
2264 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2265 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2266 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2267 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2268 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2269 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2270 }
2271 }
2272 return result;
2273 }
2274
2275 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2276 const nir_tex_instr *instr,
2277 bool lod_is_zero,
2278 struct ac_image_args *args)
2279 {
2280 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2281 return ac_build_buffer_load_format(&ctx->ac,
2282 args->resource,
2283 args->addr,
2284 ctx->ac.i32_0,
2285 true);
2286 }
2287
2288 args->opcode = ac_image_sample;
2289 args->compare = instr->is_shadow;
2290
2291 switch (instr->op) {
2292 case nir_texop_txf:
2293 case nir_texop_txf_ms:
2294 case nir_texop_samples_identical:
2295 args->opcode = lod_is_zero ||
2296 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2297 ac_image_load : ac_image_load_mip;
2298 args->compare = false;
2299 args->offset = false;
2300 break;
2301 case nir_texop_txb:
2302 args->bias = true;
2303 break;
2304 case nir_texop_txl:
2305 if (lod_is_zero)
2306 args->level_zero = true;
2307 else
2308 args->lod = true;
2309 break;
2310 case nir_texop_txs:
2311 case nir_texop_query_levels:
2312 args->opcode = ac_image_get_resinfo;
2313 break;
2314 case nir_texop_tex:
2315 if (ctx->stage != MESA_SHADER_FRAGMENT)
2316 args->level_zero = true;
2317 break;
2318 case nir_texop_txd:
2319 args->deriv = true;
2320 break;
2321 case nir_texop_tg4:
2322 args->opcode = ac_image_gather4;
2323 args->level_zero = true;
2324 break;
2325 case nir_texop_lod:
2326 args->opcode = ac_image_get_lod;
2327 args->compare = false;
2328 args->offset = false;
2329 break;
2330 default:
2331 break;
2332 }
2333
2334 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2335 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2336 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2337 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2338 }
2339 }
2340 return ac_build_image_opcode(&ctx->ac, args);
2341 }
2342
2343 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2344 nir_intrinsic_instr *instr)
2345 {
2346 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2347 unsigned desc_set = nir_intrinsic_desc_set(instr);
2348 unsigned binding = nir_intrinsic_binding(instr);
2349 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2350 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2351 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2352 unsigned base_offset = layout->binding[binding].offset;
2353 LLVMValueRef offset, stride;
2354
2355 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2356 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2357 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2358 layout->binding[binding].dynamic_offset_offset;
2359 desc_ptr = ctx->push_constants;
2360 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2361 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2362 } else
2363 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2364
2365 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2366 index = LLVMBuildMul(ctx->builder, index, stride, "");
2367 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2368
2369 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2370 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2371 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2372
2373 return desc_ptr;
2374 }
2375
2376 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2377 nir_intrinsic_instr *instr)
2378 {
2379 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2380 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2381
2382 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2383 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2384 return result;
2385 }
2386
2387 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2388 nir_intrinsic_instr *instr)
2389 {
2390 LLVMValueRef ptr, addr;
2391
2392 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2393 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2394
2395 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2396 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2397
2398 return LLVMBuildLoad(ctx->builder, ptr, "");
2399 }
2400
2401 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2402 const nir_intrinsic_instr *instr)
2403 {
2404 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2405
2406 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2407 }
2408 static void visit_store_ssbo(struct ac_nir_context *ctx,
2409 nir_intrinsic_instr *instr)
2410 {
2411 const char *store_name;
2412 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2413 LLVMTypeRef data_type = ctx->ac.f32;
2414 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2415 int components_32bit = elem_size_mult * instr->num_components;
2416 unsigned writemask = nir_intrinsic_write_mask(instr);
2417 LLVMValueRef base_data, base_offset;
2418 LLVMValueRef params[6];
2419
2420 params[1] = ctx->abi->load_ssbo(ctx->abi,
2421 get_src(ctx, instr->src[1]), true);
2422 params[2] = ctx->ac.i32_0; /* vindex */
2423 params[4] = ctx->ac.i1false; /* glc */
2424 params[5] = ctx->ac.i1false; /* slc */
2425
2426 if (components_32bit > 1)
2427 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2428
2429 base_data = ac_to_float(&ctx->ac, src_data);
2430 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2431 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2432 data_type, "");
2433 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2434 while (writemask) {
2435 int start, count;
2436 LLVMValueRef data;
2437 LLVMValueRef offset;
2438 LLVMValueRef tmp;
2439 u_bit_scan_consecutive_range(&writemask, &start, &count);
2440
2441 /* Due to an LLVM limitation, split 3-element writes
2442 * into a 2-element and a 1-element write. */
2443 if (count == 3) {
2444 writemask |= 1 << (start + 2);
2445 count = 2;
2446 }
2447
2448 start *= elem_size_mult;
2449 count *= elem_size_mult;
2450
2451 if (count > 4) {
2452 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2453 count = 4;
2454 }
2455
2456 if (count == 4) {
2457 store_name = "llvm.amdgcn.buffer.store.v4f32";
2458 data = base_data;
2459 } else if (count == 2) {
2460 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2461 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2462 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2463 ctx->ac.i32_0, "");
2464
2465 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2466 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2467 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2468 ctx->ac.i32_1, "");
2469 store_name = "llvm.amdgcn.buffer.store.v2f32";
2470
2471 } else {
2472 assert(count == 1);
2473 if (ac_get_llvm_num_components(base_data) > 1)
2474 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2475 LLVMConstInt(ctx->ac.i32, start, false), "");
2476 else
2477 data = base_data;
2478 store_name = "llvm.amdgcn.buffer.store.f32";
2479 }
2480
2481 offset = base_offset;
2482 if (start != 0) {
2483 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2484 }
2485 params[0] = data;
2486 params[3] = offset;
2487 ac_build_intrinsic(&ctx->ac, store_name,
2488 ctx->ac.voidt, params, 6, 0);
2489 }
2490 }
2491
2492 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2493 const nir_intrinsic_instr *instr)
2494 {
2495 const char *name;
2496 LLVMValueRef params[6];
2497 int arg_count = 0;
2498
2499 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2500 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2501 }
2502 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2503 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2504 get_src(ctx, instr->src[0]),
2505 true);
2506 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2507 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2508 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2509
2510 switch (instr->intrinsic) {
2511 case nir_intrinsic_ssbo_atomic_add:
2512 name = "llvm.amdgcn.buffer.atomic.add";
2513 break;
2514 case nir_intrinsic_ssbo_atomic_imin:
2515 name = "llvm.amdgcn.buffer.atomic.smin";
2516 break;
2517 case nir_intrinsic_ssbo_atomic_umin:
2518 name = "llvm.amdgcn.buffer.atomic.umin";
2519 break;
2520 case nir_intrinsic_ssbo_atomic_imax:
2521 name = "llvm.amdgcn.buffer.atomic.smax";
2522 break;
2523 case nir_intrinsic_ssbo_atomic_umax:
2524 name = "llvm.amdgcn.buffer.atomic.umax";
2525 break;
2526 case nir_intrinsic_ssbo_atomic_and:
2527 name = "llvm.amdgcn.buffer.atomic.and";
2528 break;
2529 case nir_intrinsic_ssbo_atomic_or:
2530 name = "llvm.amdgcn.buffer.atomic.or";
2531 break;
2532 case nir_intrinsic_ssbo_atomic_xor:
2533 name = "llvm.amdgcn.buffer.atomic.xor";
2534 break;
2535 case nir_intrinsic_ssbo_atomic_exchange:
2536 name = "llvm.amdgcn.buffer.atomic.swap";
2537 break;
2538 case nir_intrinsic_ssbo_atomic_comp_swap:
2539 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2540 break;
2541 default:
2542 abort();
2543 }
2544
2545 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2546 }
2547
2548 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2549 const nir_intrinsic_instr *instr)
2550 {
2551 LLVMValueRef results[2];
2552 int load_components;
2553 int num_components = instr->num_components;
2554 if (instr->dest.ssa.bit_size == 64)
2555 num_components *= 2;
2556
2557 for (int i = 0; i < num_components; i += load_components) {
2558 load_components = MIN2(num_components - i, 4);
2559 const char *load_name;
2560 LLVMTypeRef data_type = ctx->ac.f32;
2561 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2562 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2563
2564 if (load_components == 3)
2565 data_type = LLVMVectorType(ctx->ac.f32, 4);
2566 else if (load_components > 1)
2567 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2568
2569 if (load_components >= 3)
2570 load_name = "llvm.amdgcn.buffer.load.v4f32";
2571 else if (load_components == 2)
2572 load_name = "llvm.amdgcn.buffer.load.v2f32";
2573 else if (load_components == 1)
2574 load_name = "llvm.amdgcn.buffer.load.f32";
2575 else
2576 unreachable("unhandled number of components");
2577
2578 LLVMValueRef params[] = {
2579 ctx->abi->load_ssbo(ctx->abi,
2580 get_src(ctx, instr->src[0]),
2581 false),
2582 ctx->ac.i32_0,
2583 offset,
2584 ctx->ac.i1false,
2585 ctx->ac.i1false,
2586 };
2587
2588 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2589
2590 }
2591
2592 assume(results[0]);
2593 LLVMValueRef ret = results[0];
2594 if (num_components > 4 || num_components == 3) {
2595 LLVMValueRef masks[] = {
2596 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2597 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2598 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2599 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2600 };
2601
2602 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2603 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2604 results[num_components > 4 ? 1 : 0], swizzle, "");
2605 }
2606
2607 return LLVMBuildBitCast(ctx->ac.builder, ret,
2608 get_def_type(ctx, &instr->dest.ssa), "");
2609 }
2610
2611 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2612 const nir_intrinsic_instr *instr)
2613 {
2614 LLVMValueRef ret;
2615 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2616 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2617 int num_components = instr->num_components;
2618
2619 if (ctx->abi->load_ubo)
2620 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2621
2622 if (instr->dest.ssa.bit_size == 64)
2623 num_components *= 2;
2624
2625 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2626 NULL, 0, false, false, true, true);
2627 ret = trim_vector(&ctx->ac, ret, num_components);
2628 return LLVMBuildBitCast(ctx->ac.builder, ret,
2629 get_def_type(ctx, &instr->dest.ssa), "");
2630 }
2631
2632 static void
2633 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2634 bool vs_in, unsigned *vertex_index_out,
2635 LLVMValueRef *vertex_index_ref,
2636 unsigned *const_out, LLVMValueRef *indir_out)
2637 {
2638 unsigned const_offset = 0;
2639 nir_deref *tail = &deref->deref;
2640 LLVMValueRef offset = NULL;
2641
2642 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2643 tail = tail->child;
2644 nir_deref_array *deref_array = nir_deref_as_array(tail);
2645 if (vertex_index_out)
2646 *vertex_index_out = deref_array->base_offset;
2647
2648 if (vertex_index_ref) {
2649 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2650 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2651 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2652 }
2653 *vertex_index_ref = vtx;
2654 }
2655 }
2656
2657 if (deref->var->data.compact) {
2658 assert(tail->child->deref_type == nir_deref_type_array);
2659 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2660 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2661 /* We always lower indirect dereferences for "compact" array vars. */
2662 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2663
2664 const_offset = deref_array->base_offset;
2665 goto out;
2666 }
2667
2668 while (tail->child != NULL) {
2669 const struct glsl_type *parent_type = tail->type;
2670 tail = tail->child;
2671
2672 if (tail->deref_type == nir_deref_type_array) {
2673 nir_deref_array *deref_array = nir_deref_as_array(tail);
2674 LLVMValueRef index, stride, local_offset;
2675 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2676
2677 const_offset += size * deref_array->base_offset;
2678 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2679 continue;
2680
2681 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2682 index = get_src(ctx, deref_array->indirect);
2683 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2684 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2685
2686 if (offset)
2687 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2688 else
2689 offset = local_offset;
2690 } else if (tail->deref_type == nir_deref_type_struct) {
2691 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2692
2693 for (unsigned i = 0; i < deref_struct->index; i++) {
2694 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2695 const_offset += glsl_count_attribute_slots(ft, vs_in);
2696 }
2697 } else
2698 unreachable("unsupported deref type");
2699
2700 }
2701 out:
2702 if (const_offset && offset)
2703 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2704 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2705 "");
2706
2707 *const_out = const_offset;
2708 *indir_out = offset;
2709 }
2710
2711
2712 /* The offchip buffer layout for TCS->TES is
2713 *
2714 * - attribute 0 of patch 0 vertex 0
2715 * - attribute 0 of patch 0 vertex 1
2716 * - attribute 0 of patch 0 vertex 2
2717 * ...
2718 * - attribute 0 of patch 1 vertex 0
2719 * - attribute 0 of patch 1 vertex 1
2720 * ...
2721 * - attribute 1 of patch 0 vertex 0
2722 * - attribute 1 of patch 0 vertex 1
2723 * ...
2724 * - per patch attribute 0 of patch 0
2725 * - per patch attribute 0 of patch 1
2726 * ...
2727 *
2728 * Note that every attribute has 4 components.
2729 */
2730 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2731 LLVMValueRef vertex_index,
2732 LLVMValueRef param_index)
2733 {
2734 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2735 LLVMValueRef param_stride, constant16;
2736 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2737
2738 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2739 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2740 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2741 num_patches, "");
2742
2743 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2744 if (vertex_index) {
2745 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2746 vertices_per_patch, "");
2747
2748 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2749 vertex_index, "");
2750
2751 param_stride = total_vertices;
2752 } else {
2753 base_addr = rel_patch_id;
2754 param_stride = num_patches;
2755 }
2756
2757 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2758 LLVMBuildMul(ctx->builder, param_index,
2759 param_stride, ""), "");
2760
2761 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2762
2763 if (!vertex_index) {
2764 LLVMValueRef patch_data_offset =
2765 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2766
2767 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2768 patch_data_offset, "");
2769 }
2770 return base_addr;
2771 }
2772
2773 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2774 unsigned param,
2775 unsigned const_index,
2776 bool is_compact,
2777 LLVMValueRef vertex_index,
2778 LLVMValueRef indir_index)
2779 {
2780 LLVMValueRef param_index;
2781
2782 if (indir_index)
2783 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2784 indir_index, "");
2785 else {
2786 if (const_index && !is_compact)
2787 param += const_index;
2788 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2789 }
2790 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2791 }
2792
2793 static void
2794 mark_tess_output(struct nir_to_llvm_context *ctx,
2795 bool is_patch, uint32_t param)
2796
2797 {
2798 if (is_patch) {
2799 ctx->tess_patch_outputs_written |= (1ull << param);
2800 } else
2801 ctx->tess_outputs_written |= (1ull << param);
2802 }
2803
2804 static LLVMValueRef
2805 get_dw_address(struct nir_to_llvm_context *ctx,
2806 LLVMValueRef dw_addr,
2807 unsigned param,
2808 unsigned const_index,
2809 bool compact_const_index,
2810 LLVMValueRef vertex_index,
2811 LLVMValueRef stride,
2812 LLVMValueRef indir_index)
2813
2814 {
2815
2816 if (vertex_index) {
2817 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2818 LLVMBuildMul(ctx->builder,
2819 vertex_index,
2820 stride, ""), "");
2821 }
2822
2823 if (indir_index)
2824 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2825 LLVMBuildMul(ctx->builder, indir_index,
2826 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2827 else if (const_index && !compact_const_index)
2828 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2829 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2830
2831 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2832 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2833
2834 if (const_index && compact_const_index)
2835 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2836 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2837 return dw_addr;
2838 }
2839
2840 static LLVMValueRef
2841 load_tcs_input(struct ac_shader_abi *abi,
2842 LLVMValueRef vertex_index,
2843 LLVMValueRef indir_index,
2844 unsigned const_index,
2845 unsigned location,
2846 unsigned driver_location,
2847 unsigned component,
2848 unsigned num_components,
2849 bool is_patch,
2850 bool is_compact)
2851 {
2852 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2853 LLVMValueRef dw_addr, stride;
2854 LLVMValueRef value[4], result;
2855 unsigned param = shader_io_get_unique_index(location);
2856
2857 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2858 dw_addr = get_tcs_in_current_patch_offset(ctx);
2859 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2860 indir_index);
2861
2862 for (unsigned i = 0; i < num_components + component; i++) {
2863 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2864 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2865 ctx->ac.i32_1, "");
2866 }
2867 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2868 return result;
2869 }
2870
2871 static LLVMValueRef
2872 load_tcs_output(struct nir_to_llvm_context *ctx,
2873 nir_intrinsic_instr *instr)
2874 {
2875 LLVMValueRef dw_addr;
2876 LLVMValueRef stride = NULL;
2877 LLVMValueRef value[4], result;
2878 LLVMValueRef vertex_index = NULL;
2879 LLVMValueRef indir_index = NULL;
2880 unsigned const_index = 0;
2881 unsigned param;
2882 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2883 const bool is_compact = instr->variables[0]->var->data.compact;
2884 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2885 get_deref_offset(ctx->nir, instr->variables[0],
2886 false, NULL, per_vertex ? &vertex_index : NULL,
2887 &const_index, &indir_index);
2888
2889 if (!instr->variables[0]->var->data.patch) {
2890 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2891 dw_addr = get_tcs_out_current_patch_offset(ctx);
2892 } else {
2893 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2894 }
2895
2896 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2897 indir_index);
2898
2899 unsigned comp = instr->variables[0]->var->data.location_frac;
2900 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2901 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2902 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2903 ctx->ac.i32_1, "");
2904 }
2905 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2906 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2907 return result;
2908 }
2909
2910 static void
2911 store_tcs_output(struct ac_shader_abi *abi,
2912 LLVMValueRef vertex_index,
2913 LLVMValueRef param_index,
2914 unsigned const_index,
2915 unsigned location,
2916 unsigned driver_location,
2917 LLVMValueRef src,
2918 unsigned component,
2919 bool is_patch,
2920 bool is_compact,
2921 unsigned writemask)
2922 {
2923 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2924 LLVMValueRef dw_addr;
2925 LLVMValueRef stride = NULL;
2926 LLVMValueRef buf_addr = NULL;
2927 unsigned param;
2928 bool store_lds = true;
2929
2930 if (is_patch) {
2931 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2932 store_lds = false;
2933 } else {
2934 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2935 store_lds = false;
2936 }
2937
2938 param = shader_io_get_unique_index(location);
2939 if (location == VARYING_SLOT_CLIP_DIST0 &&
2940 is_compact && const_index > 3) {
2941 const_index -= 3;
2942 param++;
2943 }
2944
2945 if (!is_patch) {
2946 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2947 dw_addr = get_tcs_out_current_patch_offset(ctx);
2948 } else {
2949 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2950 }
2951
2952 mark_tess_output(ctx, is_patch, param);
2953
2954 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2955 param_index);
2956 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2957 vertex_index, param_index);
2958
2959 bool is_tess_factor = false;
2960 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2961 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2962 is_tess_factor = true;
2963
2964 unsigned base = is_compact ? const_index : 0;
2965 for (unsigned chan = 0; chan < 8; chan++) {
2966 if (!(writemask & (1 << chan)))
2967 continue;
2968 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2969
2970 if (store_lds || is_tess_factor)
2971 ac_lds_store(&ctx->ac, dw_addr, value);
2972
2973 if (!is_tess_factor && writemask != 0xF)
2974 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2975 buf_addr, ctx->oc_lds,
2976 4 * (base + chan), 1, 0, true, false);
2977
2978 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2979 ctx->ac.i32_1, "");
2980 }
2981
2982 if (writemask == 0xF) {
2983 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2984 buf_addr, ctx->oc_lds,
2985 (base * 4), 1, 0, true, false);
2986 }
2987 }
2988
2989 static LLVMValueRef
2990 load_tes_input(struct ac_shader_abi *abi,
2991 LLVMValueRef vertex_index,
2992 LLVMValueRef param_index,
2993 unsigned const_index,
2994 unsigned location,
2995 unsigned driver_location,
2996 unsigned component,
2997 unsigned num_components,
2998 bool is_patch,
2999 bool is_compact)
3000 {
3001 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3002 LLVMValueRef buf_addr;
3003 LLVMValueRef result;
3004 unsigned param = shader_io_get_unique_index(location);
3005
3006 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3007 const_index -= 3;
3008 param++;
3009 }
3010
3011 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3012 is_compact, vertex_index, param_index);
3013
3014 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3015 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3016
3017 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3018 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3019 result = trim_vector(&ctx->ac, result, num_components);
3020 return result;
3021 }
3022
3023 static LLVMValueRef
3024 load_gs_input(struct ac_shader_abi *abi,
3025 unsigned location,
3026 unsigned driver_location,
3027 unsigned component,
3028 unsigned num_components,
3029 unsigned vertex_index,
3030 unsigned const_index,
3031 LLVMTypeRef type)
3032 {
3033 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3034 LLVMValueRef vtx_offset;
3035 LLVMValueRef args[9];
3036 unsigned param, vtx_offset_param;
3037 LLVMValueRef value[4], result;
3038
3039 vtx_offset_param = vertex_index;
3040 assert(vtx_offset_param < 6);
3041 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3042 LLVMConstInt(ctx->ac.i32, 4, false), "");
3043
3044 param = shader_io_get_unique_index(location);
3045
3046 for (unsigned i = component; i < num_components + component; i++) {
3047 if (ctx->ac.chip_class >= GFX9) {
3048 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3049 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3050 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3051 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3052 } else {
3053 args[0] = ctx->esgs_ring;
3054 args[1] = vtx_offset;
3055 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3056 args[3] = ctx->ac.i32_0;
3057 args[4] = ctx->ac.i32_1; /* OFFEN */
3058 args[5] = ctx->ac.i32_0; /* IDXEN */
3059 args[6] = ctx->ac.i32_1; /* GLC */
3060 args[7] = ctx->ac.i32_0; /* SLC */
3061 args[8] = ctx->ac.i32_0; /* TFE */
3062
3063 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3064 ctx->ac.i32, args, 9,
3065 AC_FUNC_ATTR_READONLY |
3066 AC_FUNC_ATTR_LEGACY);
3067 }
3068 }
3069 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3070
3071 return result;
3072 }
3073
3074 static LLVMValueRef
3075 build_gep_for_deref(struct ac_nir_context *ctx,
3076 nir_deref_var *deref)
3077 {
3078 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3079 assert(entry->data);
3080 LLVMValueRef val = entry->data;
3081 nir_deref *tail = deref->deref.child;
3082 while (tail != NULL) {
3083 LLVMValueRef offset;
3084 switch (tail->deref_type) {
3085 case nir_deref_type_array: {
3086 nir_deref_array *array = nir_deref_as_array(tail);
3087 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3088 if (array->deref_array_type ==
3089 nir_deref_array_type_indirect) {
3090 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3091 get_src(ctx,
3092 array->indirect),
3093 "");
3094 }
3095 break;
3096 }
3097 case nir_deref_type_struct: {
3098 nir_deref_struct *deref_struct =
3099 nir_deref_as_struct(tail);
3100 offset = LLVMConstInt(ctx->ac.i32,
3101 deref_struct->index, 0);
3102 break;
3103 }
3104 default:
3105 unreachable("bad deref type");
3106 }
3107 val = ac_build_gep0(&ctx->ac, val, offset);
3108 tail = tail->child;
3109 }
3110 return val;
3111 }
3112
3113 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3114 nir_intrinsic_instr *instr)
3115 {
3116 LLVMValueRef values[8];
3117 int idx = instr->variables[0]->var->data.driver_location;
3118 int ve = instr->dest.ssa.num_components;
3119 unsigned comp = instr->variables[0]->var->data.location_frac;
3120 LLVMValueRef indir_index;
3121 LLVMValueRef ret;
3122 unsigned const_index;
3123 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3124 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3125 instr->variables[0]->var->data.mode == nir_var_shader_in;
3126 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3127 &const_index, &indir_index);
3128
3129 if (instr->dest.ssa.bit_size == 64)
3130 ve *= 2;
3131
3132 switch (instr->variables[0]->var->data.mode) {
3133 case nir_var_shader_in:
3134 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3135 ctx->stage == MESA_SHADER_TESS_EVAL) {
3136 LLVMValueRef result;
3137 LLVMValueRef vertex_index = NULL;
3138 LLVMValueRef indir_index = NULL;
3139 unsigned const_index = 0;
3140 unsigned location = instr->variables[0]->var->data.location;
3141 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3142 const bool is_patch = instr->variables[0]->var->data.patch;
3143 const bool is_compact = instr->variables[0]->var->data.compact;
3144
3145 get_deref_offset(ctx, instr->variables[0],
3146 false, NULL, is_patch ? NULL : &vertex_index,
3147 &const_index, &indir_index);
3148
3149 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3150 const_index, location, driver_location,
3151 instr->variables[0]->var->data.location_frac,
3152 instr->num_components,
3153 is_patch, is_compact);
3154 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3155 }
3156
3157 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3158 LLVMValueRef indir_index;
3159 unsigned const_index, vertex_index;
3160 get_deref_offset(ctx, instr->variables[0],
3161 false, &vertex_index, NULL,
3162 &const_index, &indir_index);
3163 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3164 instr->variables[0]->var->data.driver_location,
3165 instr->variables[0]->var->data.location_frac, ve,
3166 vertex_index, const_index,
3167 nir2llvmtype(ctx, instr->variables[0]->var->type));
3168 }
3169
3170 for (unsigned chan = comp; chan < ve + comp; chan++) {
3171 if (indir_index) {
3172 unsigned count = glsl_count_attribute_slots(
3173 instr->variables[0]->var->type,
3174 ctx->stage == MESA_SHADER_VERTEX);
3175 count -= chan / 4;
3176 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3177 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3178 stride, false, true);
3179
3180 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3181 tmp_vec,
3182 indir_index, "");
3183 } else
3184 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3185 }
3186 break;
3187 case nir_var_local:
3188 for (unsigned chan = 0; chan < ve; chan++) {
3189 if (indir_index) {
3190 unsigned count = glsl_count_attribute_slots(
3191 instr->variables[0]->var->type, false);
3192 count -= chan / 4;
3193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3194 &ctx->ac, ctx->locals + idx + chan, count,
3195 stride, true, true);
3196
3197 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3198 tmp_vec,
3199 indir_index, "");
3200 } else {
3201 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3202 }
3203 }
3204 break;
3205 case nir_var_shared: {
3206 LLVMValueRef address = build_gep_for_deref(ctx,
3207 instr->variables[0]);
3208 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3209 return LLVMBuildBitCast(ctx->ac.builder, val,
3210 get_def_type(ctx, &instr->dest.ssa),
3211 "");
3212 }
3213 case nir_var_shader_out:
3214 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3215 return load_tcs_output(ctx->nctx, instr);
3216
3217 for (unsigned chan = comp; chan < ve + comp; chan++) {
3218 if (indir_index) {
3219 unsigned count = glsl_count_attribute_slots(
3220 instr->variables[0]->var->type, false);
3221 count -= chan / 4;
3222 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3223 &ctx->ac, ctx->outputs + idx + chan, count,
3224 stride, true, true);
3225
3226 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3227 tmp_vec,
3228 indir_index, "");
3229 } else {
3230 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3231 ctx->outputs[idx + chan + const_index * stride],
3232 "");
3233 }
3234 }
3235 break;
3236 default:
3237 unreachable("unhandle variable mode");
3238 }
3239 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3240 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3241 }
3242
3243 static void
3244 visit_store_var(struct ac_nir_context *ctx,
3245 nir_intrinsic_instr *instr)
3246 {
3247 LLVMValueRef temp_ptr, value;
3248 int idx = instr->variables[0]->var->data.driver_location;
3249 unsigned comp = instr->variables[0]->var->data.location_frac;
3250 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3251 int writemask = instr->const_index[0] << comp;
3252 LLVMValueRef indir_index;
3253 unsigned const_index;
3254 get_deref_offset(ctx, instr->variables[0], false,
3255 NULL, NULL, &const_index, &indir_index);
3256
3257 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3258 int old_writemask = writemask;
3259
3260 src = LLVMBuildBitCast(ctx->ac.builder, src,
3261 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3262 "");
3263
3264 writemask = 0;
3265 for (unsigned chan = 0; chan < 4; chan++) {
3266 if (old_writemask & (1 << chan))
3267 writemask |= 3u << (2 * chan);
3268 }
3269 }
3270
3271 switch (instr->variables[0]->var->data.mode) {
3272 case nir_var_shader_out:
3273
3274 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3275 LLVMValueRef vertex_index = NULL;
3276 LLVMValueRef indir_index = NULL;
3277 unsigned const_index = 0;
3278 const unsigned location = instr->variables[0]->var->data.location;
3279 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3280 const unsigned comp = instr->variables[0]->var->data.location_frac;
3281 const bool is_patch = instr->variables[0]->var->data.patch;
3282 const bool is_compact = instr->variables[0]->var->data.compact;
3283
3284 get_deref_offset(ctx, instr->variables[0],
3285 false, NULL, is_patch ? NULL : &vertex_index,
3286 &const_index, &indir_index);
3287
3288 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3289 const_index, location, driver_location,
3290 src, comp, is_patch, is_compact, writemask);
3291 return;
3292 }
3293
3294 for (unsigned chan = 0; chan < 8; chan++) {
3295 int stride = 4;
3296 if (!(writemask & (1 << chan)))
3297 continue;
3298
3299 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3300
3301 if (instr->variables[0]->var->data.compact)
3302 stride = 1;
3303 if (indir_index) {
3304 unsigned count = glsl_count_attribute_slots(
3305 instr->variables[0]->var->type, false);
3306 count -= chan / 4;
3307 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3308 &ctx->ac, ctx->outputs + idx + chan, count,
3309 stride, true, true);
3310
3311 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3312 value, indir_index, "");
3313 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3314 count, stride, tmp_vec);
3315
3316 } else {
3317 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3318
3319 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3320 }
3321 }
3322 break;
3323 case nir_var_local:
3324 for (unsigned chan = 0; chan < 8; chan++) {
3325 if (!(writemask & (1 << chan)))
3326 continue;
3327
3328 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3329 if (indir_index) {
3330 unsigned count = glsl_count_attribute_slots(
3331 instr->variables[0]->var->type, false);
3332 count -= chan / 4;
3333 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3334 &ctx->ac, ctx->locals + idx + chan, count,
3335 4, true, true);
3336
3337 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3338 value, indir_index, "");
3339 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3340 count, 4, tmp_vec);
3341 } else {
3342 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3343
3344 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3345 }
3346 }
3347 break;
3348 case nir_var_shared: {
3349 int writemask = instr->const_index[0];
3350 LLVMValueRef address = build_gep_for_deref(ctx,
3351 instr->variables[0]);
3352 LLVMValueRef val = get_src(ctx, instr->src[0]);
3353 unsigned components =
3354 glsl_get_vector_elements(
3355 nir_deref_tail(&instr->variables[0]->deref)->type);
3356 if (writemask == (1 << components) - 1) {
3357 val = LLVMBuildBitCast(
3358 ctx->ac.builder, val,
3359 LLVMGetElementType(LLVMTypeOf(address)), "");
3360 LLVMBuildStore(ctx->ac.builder, val, address);
3361 } else {
3362 for (unsigned chan = 0; chan < 4; chan++) {
3363 if (!(writemask & (1 << chan)))
3364 continue;
3365 LLVMValueRef ptr =
3366 LLVMBuildStructGEP(ctx->ac.builder,
3367 address, chan, "");
3368 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3369 chan);
3370 src = LLVMBuildBitCast(
3371 ctx->ac.builder, src,
3372 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3373 LLVMBuildStore(ctx->ac.builder, src, ptr);
3374 }
3375 }
3376 break;
3377 }
3378 default:
3379 break;
3380 }
3381 }
3382
3383 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3384 {
3385 switch (dim) {
3386 case GLSL_SAMPLER_DIM_BUF:
3387 return 1;
3388 case GLSL_SAMPLER_DIM_1D:
3389 return array ? 2 : 1;
3390 case GLSL_SAMPLER_DIM_2D:
3391 return array ? 3 : 2;
3392 case GLSL_SAMPLER_DIM_MS:
3393 return array ? 4 : 3;
3394 case GLSL_SAMPLER_DIM_3D:
3395 case GLSL_SAMPLER_DIM_CUBE:
3396 return 3;
3397 case GLSL_SAMPLER_DIM_RECT:
3398 case GLSL_SAMPLER_DIM_SUBPASS:
3399 return 2;
3400 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3401 return 3;
3402 default:
3403 break;
3404 }
3405 return 0;
3406 }
3407
3408
3409
3410 /* Adjust the sample index according to FMASK.
3411 *
3412 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3413 * which is the identity mapping. Each nibble says which physical sample
3414 * should be fetched to get that sample.
3415 *
3416 * For example, 0x11111100 means there are only 2 samples stored and
3417 * the second sample covers 3/4 of the pixel. When reading samples 0
3418 * and 1, return physical sample 0 (determined by the first two 0s
3419 * in FMASK), otherwise return physical sample 1.
3420 *
3421 * The sample index should be adjusted as follows:
3422 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3423 */
3424 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3425 LLVMValueRef coord_x, LLVMValueRef coord_y,
3426 LLVMValueRef coord_z,
3427 LLVMValueRef sample_index,
3428 LLVMValueRef fmask_desc_ptr)
3429 {
3430 LLVMValueRef fmask_load_address[4];
3431 LLVMValueRef res;
3432
3433 fmask_load_address[0] = coord_x;
3434 fmask_load_address[1] = coord_y;
3435 if (coord_z) {
3436 fmask_load_address[2] = coord_z;
3437 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3438 }
3439
3440 struct ac_image_args args = {0};
3441
3442 args.opcode = ac_image_load;
3443 args.da = coord_z ? true : false;
3444 args.resource = fmask_desc_ptr;
3445 args.dmask = 0xf;
3446 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3447
3448 res = ac_build_image_opcode(ctx, &args);
3449
3450 res = ac_to_integer(ctx, res);
3451 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3452 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3453
3454 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3455 res,
3456 ctx->i32_0, "");
3457
3458 LLVMValueRef sample_index4 =
3459 LLVMBuildMul(ctx->builder, sample_index, four, "");
3460 LLVMValueRef shifted_fmask =
3461 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3462 LLVMValueRef final_sample =
3463 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3464
3465 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3466 * resource descriptor is 0 (invalid),
3467 */
3468 LLVMValueRef fmask_desc =
3469 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3470 ctx->v8i32, "");
3471
3472 LLVMValueRef fmask_word1 =
3473 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3474 ctx->i32_1, "");
3475
3476 LLVMValueRef word1_is_nonzero =
3477 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3478 fmask_word1, ctx->i32_0, "");
3479
3480 /* Replace the MSAA sample index. */
3481 sample_index =
3482 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3483 final_sample, sample_index, "");
3484 return sample_index;
3485 }
3486
3487 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3488 const nir_intrinsic_instr *instr)
3489 {
3490 const struct glsl_type *type = instr->variables[0]->var->type;
3491 if(instr->variables[0]->deref.child)
3492 type = instr->variables[0]->deref.child->type;
3493
3494 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3495 LLVMValueRef coords[4];
3496 LLVMValueRef masks[] = {
3497 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3498 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3499 };
3500 LLVMValueRef res;
3501 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3502
3503 int count;
3504 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3505 bool is_array = glsl_sampler_type_is_array(type);
3506 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3507 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3508 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3509 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3510 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3511 count = image_type_to_components_count(dim, is_array);
3512
3513 if (is_ms) {
3514 LLVMValueRef fmask_load_address[3];
3515 int chan;
3516
3517 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3518 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3519 if (is_array)
3520 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3521 else
3522 fmask_load_address[2] = NULL;
3523 if (add_frag_pos) {
3524 for (chan = 0; chan < 2; ++chan)
3525 fmask_load_address[chan] =
3526 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3527 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3528 ctx->ac.i32, ""), "");
3529 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3530 }
3531 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3532 fmask_load_address[0],
3533 fmask_load_address[1],
3534 fmask_load_address[2],
3535 sample_index,
3536 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3537 }
3538 if (count == 1 && !gfx9_1d) {
3539 if (instr->src[0].ssa->num_components)
3540 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3541 else
3542 res = src0;
3543 } else {
3544 int chan;
3545 if (is_ms)
3546 count--;
3547 for (chan = 0; chan < count; ++chan) {
3548 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3549 }
3550 if (add_frag_pos) {
3551 for (chan = 0; chan < 2; ++chan)
3552 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3553 ctx->ac.i32, ""), "");
3554 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3555 count++;
3556 }
3557
3558 if (gfx9_1d) {
3559 if (is_array) {
3560 coords[2] = coords[1];
3561 coords[1] = ctx->ac.i32_0;
3562 } else
3563 coords[1] = ctx->ac.i32_0;
3564 count++;
3565 }
3566
3567 if (is_ms) {
3568 coords[count] = sample_index;
3569 count++;
3570 }
3571
3572 if (count == 3) {
3573 coords[3] = LLVMGetUndef(ctx->ac.i32);
3574 count = 4;
3575 }
3576 res = ac_build_gather_values(&ctx->ac, coords, count);
3577 }
3578 return res;
3579 }
3580
3581 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3582 const nir_intrinsic_instr *instr)
3583 {
3584 LLVMValueRef params[7];
3585 LLVMValueRef res;
3586 char intrinsic_name[64];
3587 const nir_variable *var = instr->variables[0]->var;
3588 const struct glsl_type *type = var->type;
3589
3590 if(instr->variables[0]->deref.child)
3591 type = instr->variables[0]->deref.child->type;
3592
3593 type = glsl_without_array(type);
3594 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3595 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3596 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3597 ctx->ac.i32_0, ""); /* vindex */
3598 params[2] = ctx->ac.i32_0; /* voffset */
3599 params[3] = ctx->ac.i1false; /* glc */
3600 params[4] = ctx->ac.i1false; /* slc */
3601 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3602 params, 5, 0);
3603
3604 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3605 res = ac_to_integer(&ctx->ac, res);
3606 } else {
3607 bool is_da = glsl_sampler_type_is_array(type) ||
3608 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3609 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3610 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3611 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3612 LLVMValueRef glc = ctx->ac.i1false;
3613 LLVMValueRef slc = ctx->ac.i1false;
3614
3615 params[0] = get_image_coords(ctx, instr);
3616 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3617 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3618 if (HAVE_LLVM <= 0x0309) {
3619 params[3] = ctx->ac.i1false; /* r128 */
3620 params[4] = da;
3621 params[5] = glc;
3622 params[6] = slc;
3623 } else {
3624 LLVMValueRef lwe = ctx->ac.i1false;
3625 params[3] = glc;
3626 params[4] = slc;
3627 params[5] = lwe;
3628 params[6] = da;
3629 }
3630
3631 ac_get_image_intr_name("llvm.amdgcn.image.load",
3632 ctx->ac.v4f32, /* vdata */
3633 LLVMTypeOf(params[0]), /* coords */
3634 LLVMTypeOf(params[1]), /* rsrc */
3635 intrinsic_name, sizeof(intrinsic_name));
3636
3637 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3638 params, 7, AC_FUNC_ATTR_READONLY);
3639 }
3640 return ac_to_integer(&ctx->ac, res);
3641 }
3642
3643 static void visit_image_store(struct ac_nir_context *ctx,
3644 nir_intrinsic_instr *instr)
3645 {
3646 LLVMValueRef params[8];
3647 char intrinsic_name[64];
3648 const nir_variable *var = instr->variables[0]->var;
3649 const struct glsl_type *type = glsl_without_array(var->type);
3650 LLVMValueRef glc = ctx->ac.i1false;
3651 bool force_glc = ctx->ac.chip_class == SI;
3652 if (force_glc)
3653 glc = ctx->ac.i1true;
3654
3655 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3656 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3657 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3658 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3659 ctx->ac.i32_0, ""); /* vindex */
3660 params[3] = ctx->ac.i32_0; /* voffset */
3661 params[4] = glc; /* glc */
3662 params[5] = ctx->ac.i1false; /* slc */
3663 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3664 params, 6, 0);
3665 } else {
3666 bool is_da = glsl_sampler_type_is_array(type) ||
3667 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3668 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3669 LLVMValueRef slc = ctx->ac.i1false;
3670
3671 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3672 params[1] = get_image_coords(ctx, instr); /* coords */
3673 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3674 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3675 if (HAVE_LLVM <= 0x0309) {
3676 params[4] = ctx->ac.i1false; /* r128 */
3677 params[5] = da;
3678 params[6] = glc;
3679 params[7] = slc;
3680 } else {
3681 LLVMValueRef lwe = ctx->ac.i1false;
3682 params[4] = glc;
3683 params[5] = slc;
3684 params[6] = lwe;
3685 params[7] = da;
3686 }
3687
3688 ac_get_image_intr_name("llvm.amdgcn.image.store",
3689 LLVMTypeOf(params[0]), /* vdata */
3690 LLVMTypeOf(params[1]), /* coords */
3691 LLVMTypeOf(params[2]), /* rsrc */
3692 intrinsic_name, sizeof(intrinsic_name));
3693
3694 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3695 params, 8, 0);
3696 }
3697
3698 }
3699
3700 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3701 const nir_intrinsic_instr *instr)
3702 {
3703 LLVMValueRef params[7];
3704 int param_count = 0;
3705 const nir_variable *var = instr->variables[0]->var;
3706
3707 const char *atomic_name;
3708 char intrinsic_name[41];
3709 const struct glsl_type *type = glsl_without_array(var->type);
3710 MAYBE_UNUSED int length;
3711
3712 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3713
3714 switch (instr->intrinsic) {
3715 case nir_intrinsic_image_atomic_add:
3716 atomic_name = "add";
3717 break;
3718 case nir_intrinsic_image_atomic_min:
3719 atomic_name = is_unsigned ? "umin" : "smin";
3720 break;
3721 case nir_intrinsic_image_atomic_max:
3722 atomic_name = is_unsigned ? "umax" : "smax";
3723 break;
3724 case nir_intrinsic_image_atomic_and:
3725 atomic_name = "and";
3726 break;
3727 case nir_intrinsic_image_atomic_or:
3728 atomic_name = "or";
3729 break;
3730 case nir_intrinsic_image_atomic_xor:
3731 atomic_name = "xor";
3732 break;
3733 case nir_intrinsic_image_atomic_exchange:
3734 atomic_name = "swap";
3735 break;
3736 case nir_intrinsic_image_atomic_comp_swap:
3737 atomic_name = "cmpswap";
3738 break;
3739 default:
3740 abort();
3741 }
3742
3743 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3744 params[param_count++] = get_src(ctx, instr->src[3]);
3745 params[param_count++] = get_src(ctx, instr->src[2]);
3746
3747 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3748 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3749 NULL, true, true);
3750 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3751 ctx->ac.i32_0, ""); /* vindex */
3752 params[param_count++] = ctx->ac.i32_0; /* voffset */
3753 params[param_count++] = ctx->ac.i1false; /* slc */
3754
3755 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3756 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3757 } else {
3758 char coords_type[8];
3759
3760 bool da = glsl_sampler_type_is_array(type) ||
3761 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3762
3763 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3764 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3765 NULL, true, true);
3766 params[param_count++] = ctx->ac.i1false; /* r128 */
3767 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3768 params[param_count++] = ctx->ac.i1false; /* slc */
3769
3770 build_int_type_name(LLVMTypeOf(coords),
3771 coords_type, sizeof(coords_type));
3772
3773 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3774 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3775 }
3776
3777 assert(length < sizeof(intrinsic_name));
3778 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3779 }
3780
3781 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3782 const nir_intrinsic_instr *instr)
3783 {
3784 LLVMValueRef res;
3785 const nir_variable *var = instr->variables[0]->var;
3786 const struct glsl_type *type = instr->variables[0]->var->type;
3787 bool da = glsl_sampler_type_is_array(var->type) ||
3788 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3789 if(instr->variables[0]->deref.child)
3790 type = instr->variables[0]->deref.child->type;
3791
3792 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3793 return get_buffer_size(ctx,
3794 get_sampler_desc(ctx, instr->variables[0],
3795 AC_DESC_BUFFER, NULL, true, false), true);
3796
3797 struct ac_image_args args = { 0 };
3798
3799 args.da = da;
3800 args.dmask = 0xf;
3801 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3802 args.opcode = ac_image_get_resinfo;
3803 args.addr = ctx->ac.i32_0;
3804
3805 res = ac_build_image_opcode(&ctx->ac, &args);
3806
3807 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3808
3809 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3810 glsl_sampler_type_is_array(type)) {
3811 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3812 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3813 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3814 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3815 }
3816 if (ctx->ac.chip_class >= GFX9 &&
3817 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3818 glsl_sampler_type_is_array(type)) {
3819 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3820 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3821 ctx->ac.i32_1, "");
3822
3823 }
3824 return res;
3825 }
3826
3827 #define NOOP_WAITCNT 0xf7f
3828 #define LGKM_CNT 0x07f
3829 #define VM_CNT 0xf70
3830
3831 static void emit_membar(struct nir_to_llvm_context *ctx,
3832 const nir_intrinsic_instr *instr)
3833 {
3834 unsigned waitcnt = NOOP_WAITCNT;
3835
3836 switch (instr->intrinsic) {
3837 case nir_intrinsic_memory_barrier:
3838 case nir_intrinsic_group_memory_barrier:
3839 waitcnt &= VM_CNT & LGKM_CNT;
3840 break;
3841 case nir_intrinsic_memory_barrier_atomic_counter:
3842 case nir_intrinsic_memory_barrier_buffer:
3843 case nir_intrinsic_memory_barrier_image:
3844 waitcnt &= VM_CNT;
3845 break;
3846 case nir_intrinsic_memory_barrier_shared:
3847 waitcnt &= LGKM_CNT;
3848 break;
3849 default:
3850 break;
3851 }
3852 if (waitcnt != NOOP_WAITCNT)
3853 ac_build_waitcnt(&ctx->ac, waitcnt);
3854 }
3855
3856 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3857 {
3858 /* SI only (thanks to a hw bug workaround):
3859 * The real barrier instruction isn’t needed, because an entire patch
3860 * always fits into a single wave.
3861 */
3862 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3863 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3864 return;
3865 }
3866 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3867 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3868 }
3869
3870 static void emit_discard_if(struct ac_nir_context *ctx,
3871 const nir_intrinsic_instr *instr)
3872 {
3873 LLVMValueRef cond;
3874
3875 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3876 get_src(ctx, instr->src[0]),
3877 ctx->ac.i32_0, "");
3878 ac_build_kill_if_false(&ctx->ac, cond);
3879 }
3880
3881 static LLVMValueRef
3882 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3883 {
3884 LLVMValueRef result;
3885 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3886 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3887 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3888
3889 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3890 }
3891
3892 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3893 const nir_intrinsic_instr *instr)
3894 {
3895 LLVMValueRef ptr, result;
3896 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3897 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3898
3899 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3900 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3901 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3902 ptr, src, src1,
3903 LLVMAtomicOrderingSequentiallyConsistent,
3904 LLVMAtomicOrderingSequentiallyConsistent,
3905 false);
3906 } else {
3907 LLVMAtomicRMWBinOp op;
3908 switch (instr->intrinsic) {
3909 case nir_intrinsic_var_atomic_add:
3910 op = LLVMAtomicRMWBinOpAdd;
3911 break;
3912 case nir_intrinsic_var_atomic_umin:
3913 op = LLVMAtomicRMWBinOpUMin;
3914 break;
3915 case nir_intrinsic_var_atomic_umax:
3916 op = LLVMAtomicRMWBinOpUMax;
3917 break;
3918 case nir_intrinsic_var_atomic_imin:
3919 op = LLVMAtomicRMWBinOpMin;
3920 break;
3921 case nir_intrinsic_var_atomic_imax:
3922 op = LLVMAtomicRMWBinOpMax;
3923 break;
3924 case nir_intrinsic_var_atomic_and:
3925 op = LLVMAtomicRMWBinOpAnd;
3926 break;
3927 case nir_intrinsic_var_atomic_or:
3928 op = LLVMAtomicRMWBinOpOr;
3929 break;
3930 case nir_intrinsic_var_atomic_xor:
3931 op = LLVMAtomicRMWBinOpXor;
3932 break;
3933 case nir_intrinsic_var_atomic_exchange:
3934 op = LLVMAtomicRMWBinOpXchg;
3935 break;
3936 default:
3937 return NULL;
3938 }
3939
3940 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3941 LLVMAtomicOrderingSequentiallyConsistent,
3942 false);
3943 }
3944 return result;
3945 }
3946
3947 #define INTERP_CENTER 0
3948 #define INTERP_CENTROID 1
3949 #define INTERP_SAMPLE 2
3950
3951 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3952 enum glsl_interp_mode interp, unsigned location)
3953 {
3954 switch (interp) {
3955 case INTERP_MODE_FLAT:
3956 default:
3957 return NULL;
3958 case INTERP_MODE_SMOOTH:
3959 case INTERP_MODE_NONE:
3960 if (location == INTERP_CENTER)
3961 return ctx->persp_center;
3962 else if (location == INTERP_CENTROID)
3963 return ctx->persp_centroid;
3964 else if (location == INTERP_SAMPLE)
3965 return ctx->persp_sample;
3966 break;
3967 case INTERP_MODE_NOPERSPECTIVE:
3968 if (location == INTERP_CENTER)
3969 return ctx->linear_center;
3970 else if (location == INTERP_CENTROID)
3971 return ctx->linear_centroid;
3972 else if (location == INTERP_SAMPLE)
3973 return ctx->linear_sample;
3974 break;
3975 }
3976 return NULL;
3977 }
3978
3979 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3980 LLVMValueRef sample_id)
3981 {
3982 LLVMValueRef result;
3983 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3984
3985 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3986 const_array(ctx->ac.v2f32, 64), "");
3987
3988 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3989 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3990
3991 return result;
3992 }
3993
3994 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3995 {
3996 LLVMValueRef values[2];
3997
3998 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3999 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
4000 return ac_build_gather_values(&ctx->ac, values, 2);
4001 }
4002
4003 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
4004 const nir_intrinsic_instr *instr)
4005 {
4006 LLVMValueRef result[4];
4007 LLVMValueRef interp_param, attr_number;
4008 unsigned location;
4009 unsigned chan;
4010 LLVMValueRef src_c0 = NULL;
4011 LLVMValueRef src_c1 = NULL;
4012 LLVMValueRef src0 = NULL;
4013 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4014 switch (instr->intrinsic) {
4015 case nir_intrinsic_interp_var_at_centroid:
4016 location = INTERP_CENTROID;
4017 break;
4018 case nir_intrinsic_interp_var_at_sample:
4019 case nir_intrinsic_interp_var_at_offset:
4020 location = INTERP_CENTER;
4021 src0 = get_src(ctx->nir, instr->src[0]);
4022 break;
4023 default:
4024 break;
4025 }
4026
4027 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4028 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4029 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4030 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4031 LLVMValueRef sample_position;
4032 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4033
4034 /* fetch sample ID */
4035 sample_position = load_sample_position(ctx, src0);
4036
4037 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4038 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4039 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4040 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4041 }
4042 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4043 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4044
4045 if (location == INTERP_CENTER) {
4046 LLVMValueRef ij_out[2];
4047 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4048
4049 /*
4050 * take the I then J parameters, and the DDX/Y for it, and
4051 * calculate the IJ inputs for the interpolator.
4052 * temp1 = ddx * offset/sample.x + I;
4053 * interp_param.I = ddy * offset/sample.y + temp1;
4054 * temp1 = ddx * offset/sample.x + J;
4055 * interp_param.J = ddy * offset/sample.y + temp1;
4056 */
4057 for (unsigned i = 0; i < 2; i++) {
4058 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4059 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4060 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4061 ddxy_out, ix_ll, "");
4062 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4063 ddxy_out, iy_ll, "");
4064 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4065 interp_param, ix_ll, "");
4066 LLVMValueRef temp1, temp2;
4067
4068 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4069 ctx->ac.f32, "");
4070
4071 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4072 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4073
4074 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4075 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4076
4077 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4078 temp2, ctx->ac.i32, "");
4079 }
4080 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4081
4082 }
4083
4084 for (chan = 0; chan < 4; chan++) {
4085 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4086
4087 if (interp_param) {
4088 interp_param = LLVMBuildBitCast(ctx->builder,
4089 interp_param, ctx->ac.v2f32, "");
4090 LLVMValueRef i = LLVMBuildExtractElement(
4091 ctx->builder, interp_param, ctx->ac.i32_0, "");
4092 LLVMValueRef j = LLVMBuildExtractElement(
4093 ctx->builder, interp_param, ctx->ac.i32_1, "");
4094
4095 result[chan] = ac_build_fs_interp(&ctx->ac,
4096 llvm_chan, attr_number,
4097 ctx->prim_mask, i, j);
4098 } else {
4099 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4100 LLVMConstInt(ctx->ac.i32, 2, false),
4101 llvm_chan, attr_number,
4102 ctx->prim_mask);
4103 }
4104 }
4105 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4106 instr->variables[0]->var->data.location_frac);
4107 }
4108
4109 static void
4110 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4111 {
4112 LLVMValueRef gs_next_vertex;
4113 LLVMValueRef can_emit;
4114 int idx;
4115 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4116
4117 /* Write vertex attribute values to GSVS ring */
4118 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4119 ctx->gs_next_vertex,
4120 "");
4121
4122 /* If this thread has already emitted the declared maximum number of
4123 * vertices, kill it: excessive vertex emissions are not supposed to
4124 * have any effect, and GS threads have no externally observable
4125 * effects other than emitting vertices.
4126 */
4127 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4128 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4129 ac_build_kill_if_false(&ctx->ac, can_emit);
4130
4131 /* loop num outputs */
4132 idx = 0;
4133 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4134 LLVMValueRef *out_ptr = &addrs[i * 4];
4135 int length = 4;
4136 int slot = idx;
4137 int slot_inc = 1;
4138
4139 if (!(ctx->output_mask & (1ull << i)))
4140 continue;
4141
4142 if (i == VARYING_SLOT_CLIP_DIST0) {
4143 /* pack clip and cull into a single set of slots */
4144 length = ctx->num_output_clips + ctx->num_output_culls;
4145 if (length > 4)
4146 slot_inc = 2;
4147 }
4148 for (unsigned j = 0; j < length; j++) {
4149 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4150 out_ptr[j], "");
4151 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4152 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4153 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4154
4155 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4156
4157 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4158 out_val, 1,
4159 voffset, ctx->gs2vs_offset, 0,
4160 1, 1, true, true);
4161 }
4162 idx += slot_inc;
4163 }
4164
4165 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4166 ctx->ac.i32_1, "");
4167 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4168
4169 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4170 }
4171
4172 static void
4173 visit_end_primitive(struct nir_to_llvm_context *ctx,
4174 const nir_intrinsic_instr *instr)
4175 {
4176 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4177 }
4178
4179 static LLVMValueRef
4180 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4181 unsigned num_components)
4182 {
4183 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4184
4185 LLVMValueRef coord[4] = {
4186 ctx->tes_u,
4187 ctx->tes_v,
4188 ctx->ac.f32_0,
4189 ctx->ac.f32_0,
4190 };
4191
4192 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4193 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4194 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4195
4196 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4197 return LLVMBuildBitCast(ctx->builder, result, type, "");
4198 }
4199
4200 static LLVMValueRef
4201 load_patch_vertices_in(struct ac_shader_abi *abi)
4202 {
4203 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4204 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4205 }
4206
4207 static void visit_intrinsic(struct ac_nir_context *ctx,
4208 nir_intrinsic_instr *instr)
4209 {
4210 LLVMValueRef result = NULL;
4211
4212 switch (instr->intrinsic) {
4213 case nir_intrinsic_load_work_group_id: {
4214 LLVMValueRef values[3];
4215
4216 for (int i = 0; i < 3; i++) {
4217 values[i] = ctx->nctx->workgroup_ids[i] ?
4218 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4219 }
4220
4221 result = ac_build_gather_values(&ctx->ac, values, 3);
4222 break;
4223 }
4224 case nir_intrinsic_load_base_vertex: {
4225 result = ctx->abi->base_vertex;
4226 break;
4227 }
4228 case nir_intrinsic_load_vertex_id_zero_base: {
4229 result = ctx->abi->vertex_id;
4230 break;
4231 }
4232 case nir_intrinsic_load_local_invocation_id: {
4233 result = ctx->nctx->local_invocation_ids;
4234 break;
4235 }
4236 case nir_intrinsic_load_base_instance:
4237 result = ctx->abi->start_instance;
4238 break;
4239 case nir_intrinsic_load_draw_id:
4240 result = ctx->abi->draw_id;
4241 break;
4242 case nir_intrinsic_load_view_index:
4243 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4244 break;
4245 case nir_intrinsic_load_invocation_id:
4246 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4247 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4248 else
4249 result = ctx->abi->gs_invocation_id;
4250 break;
4251 case nir_intrinsic_load_primitive_id:
4252 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4253 result = ctx->abi->gs_prim_id;
4254 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4255 result = ctx->abi->tcs_patch_id;
4256 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4257 result = ctx->abi->tes_patch_id;
4258 } else
4259 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4260 break;
4261 case nir_intrinsic_load_sample_id:
4262 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4263 break;
4264 case nir_intrinsic_load_sample_pos:
4265 result = load_sample_pos(ctx);
4266 break;
4267 case nir_intrinsic_load_sample_mask_in:
4268 result = ctx->abi->sample_coverage;
4269 break;
4270 case nir_intrinsic_load_frag_coord: {
4271 LLVMValueRef values[4] = {
4272 ctx->abi->frag_pos[0],
4273 ctx->abi->frag_pos[1],
4274 ctx->abi->frag_pos[2],
4275 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4276 };
4277 result = ac_build_gather_values(&ctx->ac, values, 4);
4278 break;
4279 }
4280 case nir_intrinsic_load_front_face:
4281 result = ctx->abi->front_face;
4282 break;
4283 case nir_intrinsic_load_instance_id:
4284 result = ctx->abi->instance_id;
4285 break;
4286 case nir_intrinsic_load_num_work_groups:
4287 result = ctx->nctx->num_work_groups;
4288 break;
4289 case nir_intrinsic_load_local_invocation_index:
4290 result = visit_load_local_invocation_index(ctx->nctx);
4291 break;
4292 case nir_intrinsic_load_push_constant:
4293 result = visit_load_push_constant(ctx->nctx, instr);
4294 break;
4295 case nir_intrinsic_vulkan_resource_index:
4296 result = visit_vulkan_resource_index(ctx->nctx, instr);
4297 break;
4298 case nir_intrinsic_vulkan_resource_reindex:
4299 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4300 break;
4301 case nir_intrinsic_store_ssbo:
4302 visit_store_ssbo(ctx, instr);
4303 break;
4304 case nir_intrinsic_load_ssbo:
4305 result = visit_load_buffer(ctx, instr);
4306 break;
4307 case nir_intrinsic_ssbo_atomic_add:
4308 case nir_intrinsic_ssbo_atomic_imin:
4309 case nir_intrinsic_ssbo_atomic_umin:
4310 case nir_intrinsic_ssbo_atomic_imax:
4311 case nir_intrinsic_ssbo_atomic_umax:
4312 case nir_intrinsic_ssbo_atomic_and:
4313 case nir_intrinsic_ssbo_atomic_or:
4314 case nir_intrinsic_ssbo_atomic_xor:
4315 case nir_intrinsic_ssbo_atomic_exchange:
4316 case nir_intrinsic_ssbo_atomic_comp_swap:
4317 result = visit_atomic_ssbo(ctx, instr);
4318 break;
4319 case nir_intrinsic_load_ubo:
4320 result = visit_load_ubo_buffer(ctx, instr);
4321 break;
4322 case nir_intrinsic_get_buffer_size:
4323 result = visit_get_buffer_size(ctx, instr);
4324 break;
4325 case nir_intrinsic_load_var:
4326 result = visit_load_var(ctx, instr);
4327 break;
4328 case nir_intrinsic_store_var:
4329 visit_store_var(ctx, instr);
4330 break;
4331 case nir_intrinsic_image_load:
4332 result = visit_image_load(ctx, instr);
4333 break;
4334 case nir_intrinsic_image_store:
4335 visit_image_store(ctx, instr);
4336 break;
4337 case nir_intrinsic_image_atomic_add:
4338 case nir_intrinsic_image_atomic_min:
4339 case nir_intrinsic_image_atomic_max:
4340 case nir_intrinsic_image_atomic_and:
4341 case nir_intrinsic_image_atomic_or:
4342 case nir_intrinsic_image_atomic_xor:
4343 case nir_intrinsic_image_atomic_exchange:
4344 case nir_intrinsic_image_atomic_comp_swap:
4345 result = visit_image_atomic(ctx, instr);
4346 break;
4347 case nir_intrinsic_image_size:
4348 result = visit_image_size(ctx, instr);
4349 break;
4350 case nir_intrinsic_discard:
4351 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4352 LLVMVoidTypeInContext(ctx->ac.context),
4353 NULL, 0, AC_FUNC_ATTR_LEGACY);
4354 break;
4355 case nir_intrinsic_discard_if:
4356 emit_discard_if(ctx, instr);
4357 break;
4358 case nir_intrinsic_memory_barrier:
4359 case nir_intrinsic_group_memory_barrier:
4360 case nir_intrinsic_memory_barrier_atomic_counter:
4361 case nir_intrinsic_memory_barrier_buffer:
4362 case nir_intrinsic_memory_barrier_image:
4363 case nir_intrinsic_memory_barrier_shared:
4364 emit_membar(ctx->nctx, instr);
4365 break;
4366 case nir_intrinsic_barrier:
4367 emit_barrier(&ctx->ac, ctx->stage);
4368 break;
4369 case nir_intrinsic_var_atomic_add:
4370 case nir_intrinsic_var_atomic_imin:
4371 case nir_intrinsic_var_atomic_umin:
4372 case nir_intrinsic_var_atomic_imax:
4373 case nir_intrinsic_var_atomic_umax:
4374 case nir_intrinsic_var_atomic_and:
4375 case nir_intrinsic_var_atomic_or:
4376 case nir_intrinsic_var_atomic_xor:
4377 case nir_intrinsic_var_atomic_exchange:
4378 case nir_intrinsic_var_atomic_comp_swap:
4379 result = visit_var_atomic(ctx->nctx, instr);
4380 break;
4381 case nir_intrinsic_interp_var_at_centroid:
4382 case nir_intrinsic_interp_var_at_sample:
4383 case nir_intrinsic_interp_var_at_offset:
4384 result = visit_interp(ctx->nctx, instr);
4385 break;
4386 case nir_intrinsic_emit_vertex:
4387 assert(instr->const_index[0] == 0);
4388 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4389 break;
4390 case nir_intrinsic_end_primitive:
4391 visit_end_primitive(ctx->nctx, instr);
4392 break;
4393 case nir_intrinsic_load_tess_coord: {
4394 LLVMTypeRef type = ctx->nctx ?
4395 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4396 NULL;
4397 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4398 break;
4399 }
4400 case nir_intrinsic_load_tess_level_outer:
4401 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4402 break;
4403 case nir_intrinsic_load_tess_level_inner:
4404 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4405 break;
4406 case nir_intrinsic_load_patch_vertices_in:
4407 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4408 break;
4409 default:
4410 fprintf(stderr, "Unknown intrinsic: ");
4411 nir_print_instr(&instr->instr, stderr);
4412 fprintf(stderr, "\n");
4413 break;
4414 }
4415 if (result) {
4416 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4417 }
4418 }
4419
4420 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4421 LLVMValueRef buffer_ptr, bool write)
4422 {
4423 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4424
4425 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4426 ctx->shader_info->fs.writes_memory = true;
4427
4428 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4429 }
4430
4431 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4432 {
4433 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4434
4435 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4436 }
4437
4438 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4439 unsigned descriptor_set,
4440 unsigned base_index,
4441 unsigned constant_index,
4442 LLVMValueRef index,
4443 enum ac_descriptor_type desc_type,
4444 bool image, bool write)
4445 {
4446 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4447 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4448 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4449 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4450 unsigned offset = binding->offset;
4451 unsigned stride = binding->size;
4452 unsigned type_size;
4453 LLVMBuilderRef builder = ctx->builder;
4454 LLVMTypeRef type;
4455
4456 assert(base_index < layout->binding_count);
4457
4458 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4459 ctx->shader_info->fs.writes_memory = true;
4460
4461 switch (desc_type) {
4462 case AC_DESC_IMAGE:
4463 type = ctx->ac.v8i32;
4464 type_size = 32;
4465 break;
4466 case AC_DESC_FMASK:
4467 type = ctx->ac.v8i32;
4468 offset += 32;
4469 type_size = 32;
4470 break;
4471 case AC_DESC_SAMPLER:
4472 type = ctx->ac.v4i32;
4473 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4474 offset += 64;
4475
4476 type_size = 16;
4477 break;
4478 case AC_DESC_BUFFER:
4479 type = ctx->ac.v4i32;
4480 type_size = 16;
4481 break;
4482 default:
4483 unreachable("invalid desc_type\n");
4484 }
4485
4486 offset += constant_index * stride;
4487
4488 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4489 (!index || binding->immutable_samplers_equal)) {
4490 if (binding->immutable_samplers_equal)
4491 constant_index = 0;
4492
4493 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4494
4495 LLVMValueRef constants[] = {
4496 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4497 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4498 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4499 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4500 };
4501 return ac_build_gather_values(&ctx->ac, constants, 4);
4502 }
4503
4504 assert(stride % type_size == 0);
4505
4506 if (!index)
4507 index = ctx->ac.i32_0;
4508
4509 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4510
4511 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4512 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4513
4514 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4515 }
4516
4517 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4518 const nir_deref_var *deref,
4519 enum ac_descriptor_type desc_type,
4520 const nir_tex_instr *tex_instr,
4521 bool image, bool write)
4522 {
4523 LLVMValueRef index = NULL;
4524 unsigned constant_index = 0;
4525 unsigned descriptor_set;
4526 unsigned base_index;
4527
4528 if (!deref) {
4529 assert(tex_instr && !image);
4530 descriptor_set = 0;
4531 base_index = tex_instr->sampler_index;
4532 } else {
4533 const nir_deref *tail = &deref->deref;
4534 while (tail->child) {
4535 const nir_deref_array *child = nir_deref_as_array(tail->child);
4536 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4537
4538 if (!array_size)
4539 array_size = 1;
4540
4541 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4542
4543 if (child->deref_array_type == nir_deref_array_type_indirect) {
4544 LLVMValueRef indirect = get_src(ctx, child->indirect);
4545
4546 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4547 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4548
4549 if (!index)
4550 index = indirect;
4551 else
4552 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4553 }
4554
4555 constant_index += child->base_offset * array_size;
4556
4557 tail = &child->deref;
4558 }
4559 descriptor_set = deref->var->data.descriptor_set;
4560 base_index = deref->var->data.binding;
4561 }
4562
4563 return ctx->abi->load_sampler_desc(ctx->abi,
4564 descriptor_set,
4565 base_index,
4566 constant_index, index,
4567 desc_type, image, write);
4568 }
4569
4570 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4571 struct ac_image_args *args,
4572 const nir_tex_instr *instr,
4573 nir_texop op,
4574 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4575 LLVMValueRef *param, unsigned count,
4576 unsigned dmask)
4577 {
4578 unsigned is_rect = 0;
4579 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4580
4581 if (op == nir_texop_lod)
4582 da = false;
4583 /* Pad to power of two vector */
4584 while (count < util_next_power_of_two(count))
4585 param[count++] = LLVMGetUndef(ctx->i32);
4586
4587 if (count > 1)
4588 args->addr = ac_build_gather_values(ctx, param, count);
4589 else
4590 args->addr = param[0];
4591
4592 args->resource = res_ptr;
4593 args->sampler = samp_ptr;
4594
4595 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4596 args->addr = param[0];
4597 return;
4598 }
4599
4600 args->dmask = dmask;
4601 args->unorm = is_rect;
4602 args->da = da;
4603 }
4604
4605 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4606 *
4607 * SI-CI:
4608 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4609 * filtering manually. The driver sets img7 to a mask clearing
4610 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4611 * s_and_b32 samp0, samp0, img7
4612 *
4613 * VI:
4614 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4615 */
4616 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4617 LLVMValueRef res, LLVMValueRef samp)
4618 {
4619 LLVMBuilderRef builder = ctx->ac.builder;
4620 LLVMValueRef img7, samp0;
4621
4622 if (ctx->ac.chip_class >= VI)
4623 return samp;
4624
4625 img7 = LLVMBuildExtractElement(builder, res,
4626 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4627 samp0 = LLVMBuildExtractElement(builder, samp,
4628 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4629 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4630 return LLVMBuildInsertElement(builder, samp, samp0,
4631 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4632 }
4633
4634 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4635 nir_tex_instr *instr,
4636 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4637 LLVMValueRef *fmask_ptr)
4638 {
4639 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4640 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4641 else
4642 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4643 if (samp_ptr) {
4644 if (instr->sampler)
4645 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4646 else
4647 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4648 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4649 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4650 }
4651 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4652 instr->op == nir_texop_samples_identical))
4653 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4654 }
4655
4656 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4657 LLVMValueRef coord)
4658 {
4659 coord = ac_to_float(ctx, coord);
4660 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4661 coord = ac_to_integer(ctx, coord);
4662 return coord;
4663 }
4664
4665 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4666 {
4667 LLVMValueRef result = NULL;
4668 struct ac_image_args args = { 0 };
4669 unsigned dmask = 0xf;
4670 LLVMValueRef address[16];
4671 LLVMValueRef coords[5];
4672 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4673 LLVMValueRef bias = NULL, offsets = NULL;
4674 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4675 LLVMValueRef ddx = NULL, ddy = NULL;
4676 LLVMValueRef derivs[6];
4677 unsigned chan, count = 0;
4678 unsigned const_src = 0, num_deriv_comp = 0;
4679 bool lod_is_zero = false;
4680
4681 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4682
4683 for (unsigned i = 0; i < instr->num_srcs; i++) {
4684 switch (instr->src[i].src_type) {
4685 case nir_tex_src_coord:
4686 coord = get_src(ctx, instr->src[i].src);
4687 break;
4688 case nir_tex_src_projector:
4689 break;
4690 case nir_tex_src_comparator:
4691 comparator = get_src(ctx, instr->src[i].src);
4692 break;
4693 case nir_tex_src_offset:
4694 offsets = get_src(ctx, instr->src[i].src);
4695 const_src = i;
4696 break;
4697 case nir_tex_src_bias:
4698 bias = get_src(ctx, instr->src[i].src);
4699 break;
4700 case nir_tex_src_lod: {
4701 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4702
4703 if (val && val->i32[0] == 0)
4704 lod_is_zero = true;
4705 lod = get_src(ctx, instr->src[i].src);
4706 break;
4707 }
4708 case nir_tex_src_ms_index:
4709 sample_index = get_src(ctx, instr->src[i].src);
4710 break;
4711 case nir_tex_src_ms_mcs:
4712 break;
4713 case nir_tex_src_ddx:
4714 ddx = get_src(ctx, instr->src[i].src);
4715 num_deriv_comp = instr->src[i].src.ssa->num_components;
4716 break;
4717 case nir_tex_src_ddy:
4718 ddy = get_src(ctx, instr->src[i].src);
4719 break;
4720 case nir_tex_src_texture_offset:
4721 case nir_tex_src_sampler_offset:
4722 case nir_tex_src_plane:
4723 default:
4724 break;
4725 }
4726 }
4727
4728 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4729 result = get_buffer_size(ctx, res_ptr, true);
4730 goto write_result;
4731 }
4732
4733 if (instr->op == nir_texop_texture_samples) {
4734 LLVMValueRef res, samples, is_msaa;
4735 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4736 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4737 LLVMConstInt(ctx->ac.i32, 3, false), "");
4738 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4739 LLVMConstInt(ctx->ac.i32, 28, false), "");
4740 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4741 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4742 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4743 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4744
4745 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4746 LLVMConstInt(ctx->ac.i32, 16, false), "");
4747 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4748 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4749 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4750 samples, "");
4751 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4752 ctx->ac.i32_1, "");
4753 result = samples;
4754 goto write_result;
4755 }
4756
4757 if (coord)
4758 for (chan = 0; chan < instr->coord_components; chan++)
4759 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4760
4761 if (offsets && instr->op != nir_texop_txf) {
4762 LLVMValueRef offset[3], pack;
4763 for (chan = 0; chan < 3; ++chan)
4764 offset[chan] = ctx->ac.i32_0;
4765
4766 args.offset = true;
4767 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4768 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4769 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4770 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4771 if (chan)
4772 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4773 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4774 }
4775 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4776 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4777 address[count++] = pack;
4778
4779 }
4780 /* pack LOD bias value */
4781 if (instr->op == nir_texop_txb && bias) {
4782 address[count++] = bias;
4783 }
4784
4785 /* Pack depth comparison value */
4786 if (instr->is_shadow && comparator) {
4787 LLVMValueRef z = ac_to_float(&ctx->ac,
4788 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4789
4790 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4791 * so the depth comparison value isn't clamped for Z16 and
4792 * Z24 anymore. Do it manually here.
4793 *
4794 * It's unnecessary if the original texture format was
4795 * Z32_FLOAT, but we don't know that here.
4796 */
4797 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4798 z = ac_build_clamp(&ctx->ac, z);
4799
4800 address[count++] = z;
4801 }
4802
4803 /* pack derivatives */
4804 if (ddx || ddy) {
4805 int num_src_deriv_channels, num_dest_deriv_channels;
4806 switch (instr->sampler_dim) {
4807 case GLSL_SAMPLER_DIM_3D:
4808 case GLSL_SAMPLER_DIM_CUBE:
4809 num_deriv_comp = 3;
4810 num_src_deriv_channels = 3;
4811 num_dest_deriv_channels = 3;
4812 break;
4813 case GLSL_SAMPLER_DIM_2D:
4814 default:
4815 num_src_deriv_channels = 2;
4816 num_dest_deriv_channels = 2;
4817 num_deriv_comp = 2;
4818 break;
4819 case GLSL_SAMPLER_DIM_1D:
4820 num_src_deriv_channels = 1;
4821 if (ctx->ac.chip_class >= GFX9) {
4822 num_dest_deriv_channels = 2;
4823 num_deriv_comp = 2;
4824 } else {
4825 num_dest_deriv_channels = 1;
4826 num_deriv_comp = 1;
4827 }
4828 break;
4829 }
4830
4831 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4832 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4833 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4834 }
4835 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4836 derivs[i] = ctx->ac.f32_0;
4837 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4838 }
4839 }
4840
4841 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4842 for (chan = 0; chan < instr->coord_components; chan++)
4843 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4844 if (instr->coord_components == 3)
4845 coords[3] = LLVMGetUndef(ctx->ac.f32);
4846 ac_prepare_cube_coords(&ctx->ac,
4847 instr->op == nir_texop_txd, instr->is_array,
4848 instr->op == nir_texop_lod, coords, derivs);
4849 if (num_deriv_comp)
4850 num_deriv_comp--;
4851 }
4852
4853 if (ddx || ddy) {
4854 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4855 address[count++] = derivs[i];
4856 }
4857
4858 /* Pack texture coordinates */
4859 if (coord) {
4860 address[count++] = coords[0];
4861 if (instr->coord_components > 1) {
4862 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4863 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4864 }
4865 address[count++] = coords[1];
4866 }
4867 if (instr->coord_components > 2) {
4868 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4869 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4870 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4871 instr->op != nir_texop_txf) {
4872 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4873 }
4874 address[count++] = coords[2];
4875 }
4876
4877 if (ctx->ac.chip_class >= GFX9) {
4878 LLVMValueRef filler;
4879 if (instr->op == nir_texop_txf)
4880 filler = ctx->ac.i32_0;
4881 else
4882 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4883
4884 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4885 /* No nir_texop_lod, because it does not take a slice
4886 * even with array textures. */
4887 if (instr->is_array && instr->op != nir_texop_lod ) {
4888 address[count] = address[count - 1];
4889 address[count - 1] = filler;
4890 count++;
4891 } else
4892 address[count++] = filler;
4893 }
4894 }
4895 }
4896
4897 /* Pack LOD */
4898 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4899 instr->op == nir_texop_txf)) {
4900 address[count++] = lod;
4901 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4902 address[count++] = sample_index;
4903 } else if(instr->op == nir_texop_txs) {
4904 count = 0;
4905 if (lod)
4906 address[count++] = lod;
4907 else
4908 address[count++] = ctx->ac.i32_0;
4909 }
4910
4911 for (chan = 0; chan < count; chan++) {
4912 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4913 address[chan], ctx->ac.i32, "");
4914 }
4915
4916 if (instr->op == nir_texop_samples_identical) {
4917 LLVMValueRef txf_address[4];
4918 struct ac_image_args txf_args = { 0 };
4919 unsigned txf_count = count;
4920 memcpy(txf_address, address, sizeof(txf_address));
4921
4922 if (!instr->is_array)
4923 txf_address[2] = ctx->ac.i32_0;
4924 txf_address[3] = ctx->ac.i32_0;
4925
4926 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4927 fmask_ptr, NULL,
4928 txf_address, txf_count, 0xf);
4929
4930 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4931
4932 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4933 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4934 goto write_result;
4935 }
4936
4937 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4938 instr->op != nir_texop_txs) {
4939 unsigned sample_chan = instr->is_array ? 3 : 2;
4940 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4941 address[0],
4942 address[1],
4943 instr->is_array ? address[2] : NULL,
4944 address[sample_chan],
4945 fmask_ptr);
4946 }
4947
4948 if (offsets && instr->op == nir_texop_txf) {
4949 nir_const_value *const_offset =
4950 nir_src_as_const_value(instr->src[const_src].src);
4951 int num_offsets = instr->src[const_src].src.ssa->num_components;
4952 assert(const_offset);
4953 num_offsets = MIN2(num_offsets, instr->coord_components);
4954 if (num_offsets > 2)
4955 address[2] = LLVMBuildAdd(ctx->ac.builder,
4956 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4957 if (num_offsets > 1)
4958 address[1] = LLVMBuildAdd(ctx->ac.builder,
4959 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4960 address[0] = LLVMBuildAdd(ctx->ac.builder,
4961 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4962
4963 }
4964
4965 /* TODO TG4 support */
4966 if (instr->op == nir_texop_tg4) {
4967 if (instr->is_shadow)
4968 dmask = 1;
4969 else
4970 dmask = 1 << instr->component;
4971 }
4972 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4973 res_ptr, samp_ptr, address, count, dmask);
4974
4975 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4976
4977 if (instr->op == nir_texop_query_levels)
4978 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4979 else if (instr->is_shadow && instr->is_new_style_shadow &&
4980 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4981 instr->op != nir_texop_tg4)
4982 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4983 else if (instr->op == nir_texop_txs &&
4984 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4985 instr->is_array) {
4986 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4987 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4988 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4989 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4990 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4991 } else if (ctx->ac.chip_class >= GFX9 &&
4992 instr->op == nir_texop_txs &&
4993 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4994 instr->is_array) {
4995 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4996 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4997 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4998 ctx->ac.i32_1, "");
4999 } else if (instr->dest.ssa.num_components != 4)
5000 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5001
5002 write_result:
5003 if (result) {
5004 assert(instr->dest.is_ssa);
5005 result = ac_to_integer(&ctx->ac, result);
5006 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5007 }
5008 }
5009
5010
5011 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5012 {
5013 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5014 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5015
5016 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5017 _mesa_hash_table_insert(ctx->phis, instr, result);
5018 }
5019
5020 static void visit_post_phi(struct ac_nir_context *ctx,
5021 nir_phi_instr *instr,
5022 LLVMValueRef llvm_phi)
5023 {
5024 nir_foreach_phi_src(src, instr) {
5025 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5026 LLVMValueRef llvm_src = get_src(ctx, src->src);
5027
5028 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5029 }
5030 }
5031
5032 static void phi_post_pass(struct ac_nir_context *ctx)
5033 {
5034 struct hash_entry *entry;
5035 hash_table_foreach(ctx->phis, entry) {
5036 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5037 (LLVMValueRef)entry->data);
5038 }
5039 }
5040
5041
5042 static void visit_ssa_undef(struct ac_nir_context *ctx,
5043 const nir_ssa_undef_instr *instr)
5044 {
5045 unsigned num_components = instr->def.num_components;
5046 LLVMValueRef undef;
5047
5048 if (num_components == 1)
5049 undef = LLVMGetUndef(ctx->ac.i32);
5050 else {
5051 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5052 }
5053 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5054 }
5055
5056 static void visit_jump(struct ac_nir_context *ctx,
5057 const nir_jump_instr *instr)
5058 {
5059 switch (instr->type) {
5060 case nir_jump_break:
5061 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5062 LLVMClearInsertionPosition(ctx->ac.builder);
5063 break;
5064 case nir_jump_continue:
5065 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5066 LLVMClearInsertionPosition(ctx->ac.builder);
5067 break;
5068 default:
5069 fprintf(stderr, "Unknown NIR jump instr: ");
5070 nir_print_instr(&instr->instr, stderr);
5071 fprintf(stderr, "\n");
5072 abort();
5073 }
5074 }
5075
5076 static void visit_cf_list(struct ac_nir_context *ctx,
5077 struct exec_list *list);
5078
5079 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5080 {
5081 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5082 nir_foreach_instr(instr, block)
5083 {
5084 switch (instr->type) {
5085 case nir_instr_type_alu:
5086 visit_alu(ctx, nir_instr_as_alu(instr));
5087 break;
5088 case nir_instr_type_load_const:
5089 visit_load_const(ctx, nir_instr_as_load_const(instr));
5090 break;
5091 case nir_instr_type_intrinsic:
5092 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5093 break;
5094 case nir_instr_type_tex:
5095 visit_tex(ctx, nir_instr_as_tex(instr));
5096 break;
5097 case nir_instr_type_phi:
5098 visit_phi(ctx, nir_instr_as_phi(instr));
5099 break;
5100 case nir_instr_type_ssa_undef:
5101 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5102 break;
5103 case nir_instr_type_jump:
5104 visit_jump(ctx, nir_instr_as_jump(instr));
5105 break;
5106 default:
5107 fprintf(stderr, "Unknown NIR instr type: ");
5108 nir_print_instr(instr, stderr);
5109 fprintf(stderr, "\n");
5110 abort();
5111 }
5112 }
5113
5114 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5115 }
5116
5117 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5118 {
5119 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5120
5121 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5122 LLVMBasicBlockRef merge_block =
5123 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5124 LLVMBasicBlockRef if_block =
5125 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5126 LLVMBasicBlockRef else_block = merge_block;
5127 if (!exec_list_is_empty(&if_stmt->else_list))
5128 else_block = LLVMAppendBasicBlockInContext(
5129 ctx->ac.context, fn, "");
5130
5131 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5132 ctx->ac.i32_0, "");
5133 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5134
5135 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5136 visit_cf_list(ctx, &if_stmt->then_list);
5137 if (LLVMGetInsertBlock(ctx->ac.builder))
5138 LLVMBuildBr(ctx->ac.builder, merge_block);
5139
5140 if (!exec_list_is_empty(&if_stmt->else_list)) {
5141 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5142 visit_cf_list(ctx, &if_stmt->else_list);
5143 if (LLVMGetInsertBlock(ctx->ac.builder))
5144 LLVMBuildBr(ctx->ac.builder, merge_block);
5145 }
5146
5147 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5148 }
5149
5150 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5151 {
5152 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5153 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5154 LLVMBasicBlockRef break_parent = ctx->break_block;
5155
5156 ctx->continue_block =
5157 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5158 ctx->break_block =
5159 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5160
5161 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5162 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5163 visit_cf_list(ctx, &loop->body);
5164
5165 if (LLVMGetInsertBlock(ctx->ac.builder))
5166 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5167 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5168
5169 ctx->continue_block = continue_parent;
5170 ctx->break_block = break_parent;
5171 }
5172
5173 static void visit_cf_list(struct ac_nir_context *ctx,
5174 struct exec_list *list)
5175 {
5176 foreach_list_typed(nir_cf_node, node, node, list)
5177 {
5178 switch (node->type) {
5179 case nir_cf_node_block:
5180 visit_block(ctx, nir_cf_node_as_block(node));
5181 break;
5182
5183 case nir_cf_node_if:
5184 visit_if(ctx, nir_cf_node_as_if(node));
5185 break;
5186
5187 case nir_cf_node_loop:
5188 visit_loop(ctx, nir_cf_node_as_loop(node));
5189 break;
5190
5191 default:
5192 assert(0);
5193 }
5194 }
5195 }
5196
5197 static void
5198 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5199 struct nir_variable *variable)
5200 {
5201 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5202 LLVMValueRef t_offset;
5203 LLVMValueRef t_list;
5204 LLVMValueRef input;
5205 LLVMValueRef buffer_index;
5206 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5207 int idx = variable->data.location;
5208 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5209
5210 variable->data.driver_location = idx * 4;
5211
5212 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5213 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5214 ctx->abi.start_instance, "");
5215 if (ctx->options->key.vs.as_ls) {
5216 ctx->shader_info->vs.vgpr_comp_cnt =
5217 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5218 } else {
5219 ctx->shader_info->vs.vgpr_comp_cnt =
5220 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5221 }
5222 } else
5223 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5224 ctx->abi.base_vertex, "");
5225
5226 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5227 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5228
5229 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5230
5231 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5232 buffer_index,
5233 ctx->ac.i32_0,
5234 true);
5235
5236 for (unsigned chan = 0; chan < 4; chan++) {
5237 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5238 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5239 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5240 input, llvm_chan, ""));
5241 }
5242 }
5243 }
5244
5245 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5246 unsigned attr,
5247 LLVMValueRef interp_param,
5248 LLVMValueRef prim_mask,
5249 LLVMValueRef result[4])
5250 {
5251 LLVMValueRef attr_number;
5252 unsigned chan;
5253 LLVMValueRef i, j;
5254 bool interp = interp_param != NULL;
5255
5256 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5257
5258 /* fs.constant returns the param from the middle vertex, so it's not
5259 * really useful for flat shading. It's meant to be used for custom
5260 * interpolation (but the intrinsic can't fetch from the other two
5261 * vertices).
5262 *
5263 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5264 * to do the right thing. The only reason we use fs.constant is that
5265 * fs.interp cannot be used on integers, because they can be equal
5266 * to NaN.
5267 */
5268 if (interp) {
5269 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5270 ctx->ac.v2f32, "");
5271
5272 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5273 ctx->ac.i32_0, "");
5274 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5275 ctx->ac.i32_1, "");
5276 }
5277
5278 for (chan = 0; chan < 4; chan++) {
5279 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5280
5281 if (interp) {
5282 result[chan] = ac_build_fs_interp(&ctx->ac,
5283 llvm_chan,
5284 attr_number,
5285 prim_mask, i, j);
5286 } else {
5287 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5288 LLVMConstInt(ctx->ac.i32, 2, false),
5289 llvm_chan,
5290 attr_number,
5291 prim_mask);
5292 }
5293 }
5294 }
5295
5296 static void
5297 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5298 struct nir_variable *variable)
5299 {
5300 int idx = variable->data.location;
5301 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5302 LLVMValueRef interp;
5303
5304 variable->data.driver_location = idx * 4;
5305 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5306
5307 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5308 unsigned interp_type;
5309 if (variable->data.sample) {
5310 interp_type = INTERP_SAMPLE;
5311 ctx->shader_info->info.ps.force_persample = true;
5312 } else if (variable->data.centroid)
5313 interp_type = INTERP_CENTROID;
5314 else
5315 interp_type = INTERP_CENTER;
5316
5317 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5318 } else
5319 interp = NULL;
5320
5321 for (unsigned i = 0; i < attrib_count; ++i)
5322 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5323
5324 }
5325
5326 static void
5327 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5328 struct nir_shader *nir) {
5329 nir_foreach_variable(variable, &nir->inputs)
5330 handle_vs_input_decl(ctx, variable);
5331 }
5332
5333 static void
5334 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5335 struct nir_shader *nir)
5336 {
5337 if (!ctx->options->key.fs.multisample)
5338 return;
5339
5340 bool uses_center = false;
5341 bool uses_centroid = false;
5342 nir_foreach_variable(variable, &nir->inputs) {
5343 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5344 variable->data.sample)
5345 continue;
5346
5347 if (variable->data.centroid)
5348 uses_centroid = true;
5349 else
5350 uses_center = true;
5351 }
5352
5353 if (uses_center && uses_centroid) {
5354 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5355 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5356 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5357 }
5358 }
5359
5360 static void
5361 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5362 struct nir_shader *nir)
5363 {
5364 prepare_interp_optimize(ctx, nir);
5365
5366 nir_foreach_variable(variable, &nir->inputs)
5367 handle_fs_input_decl(ctx, variable);
5368
5369 unsigned index = 0;
5370
5371 if (ctx->shader_info->info.ps.uses_input_attachments ||
5372 ctx->shader_info->info.needs_multiview_view_index)
5373 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5374
5375 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5376 LLVMValueRef interp_param;
5377 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5378
5379 if (!(ctx->input_mask & (1ull << i)))
5380 continue;
5381
5382 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5383 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5384 interp_param = *inputs;
5385 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5386 inputs);
5387
5388 if (!interp_param)
5389 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5390 ++index;
5391 } else if (i == VARYING_SLOT_POS) {
5392 for(int i = 0; i < 3; ++i)
5393 inputs[i] = ctx->abi.frag_pos[i];
5394
5395 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5396 ctx->abi.frag_pos[3]);
5397 }
5398 }
5399 ctx->shader_info->fs.num_interp = index;
5400 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5401 ctx->shader_info->fs.has_pcoord = true;
5402 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5403 ctx->shader_info->fs.prim_id_input = true;
5404 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5405 ctx->shader_info->fs.layer_input = true;
5406 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5407
5408 if (ctx->shader_info->info.needs_multiview_view_index)
5409 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5410 }
5411
5412 static LLVMValueRef
5413 ac_build_alloca(struct ac_llvm_context *ac,
5414 LLVMTypeRef type,
5415 const char *name)
5416 {
5417 LLVMBuilderRef builder = ac->builder;
5418 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5419 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5420 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5421 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5422 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5423 LLVMValueRef res;
5424
5425 if (first_instr) {
5426 LLVMPositionBuilderBefore(first_builder, first_instr);
5427 } else {
5428 LLVMPositionBuilderAtEnd(first_builder, first_block);
5429 }
5430
5431 res = LLVMBuildAlloca(first_builder, type, name);
5432 LLVMBuildStore(builder, LLVMConstNull(type), res);
5433
5434 LLVMDisposeBuilder(first_builder);
5435
5436 return res;
5437 }
5438
5439 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5440 LLVMTypeRef type,
5441 const char *name)
5442 {
5443 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5444 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5445 return ptr;
5446 }
5447
5448 static void
5449 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5450 struct nir_variable *variable,
5451 struct nir_shader *shader,
5452 gl_shader_stage stage)
5453 {
5454 int idx = variable->data.location + variable->data.index;
5455 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5456 uint64_t mask_attribs;
5457
5458 variable->data.driver_location = idx * 4;
5459
5460 /* tess ctrl has it's own load/store paths for outputs */
5461 if (stage == MESA_SHADER_TESS_CTRL)
5462 return;
5463
5464 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5465 if (stage == MESA_SHADER_VERTEX ||
5466 stage == MESA_SHADER_TESS_EVAL ||
5467 stage == MESA_SHADER_GEOMETRY) {
5468 if (idx == VARYING_SLOT_CLIP_DIST0) {
5469 int length = shader->info.clip_distance_array_size +
5470 shader->info.cull_distance_array_size;
5471 if (stage == MESA_SHADER_VERTEX) {
5472 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5473 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5474 }
5475 if (stage == MESA_SHADER_TESS_EVAL) {
5476 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5477 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5478 }
5479
5480 if (length > 4)
5481 attrib_count = 2;
5482 else
5483 attrib_count = 1;
5484 mask_attribs = 1ull << idx;
5485 }
5486 }
5487
5488 ctx->output_mask |= mask_attribs;
5489 }
5490
5491 static void
5492 handle_shader_output_decl(struct ac_nir_context *ctx,
5493 struct nir_shader *nir,
5494 struct nir_variable *variable)
5495 {
5496 unsigned output_loc = variable->data.driver_location / 4;
5497 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5498
5499 /* tess ctrl has it's own load/store paths for outputs */
5500 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5501 return;
5502
5503 if (ctx->stage == MESA_SHADER_VERTEX ||
5504 ctx->stage == MESA_SHADER_TESS_EVAL ||
5505 ctx->stage == MESA_SHADER_GEOMETRY) {
5506 int idx = variable->data.location + variable->data.index;
5507 if (idx == VARYING_SLOT_CLIP_DIST0) {
5508 int length = nir->info.clip_distance_array_size +
5509 nir->info.cull_distance_array_size;
5510
5511 if (length > 4)
5512 attrib_count = 2;
5513 else
5514 attrib_count = 1;
5515 }
5516 }
5517
5518 for (unsigned i = 0; i < attrib_count; ++i) {
5519 for (unsigned chan = 0; chan < 4; chan++) {
5520 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5521 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5522 }
5523 }
5524 }
5525
5526 static LLVMTypeRef
5527 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5528 enum glsl_base_type type)
5529 {
5530 switch (type) {
5531 case GLSL_TYPE_INT:
5532 case GLSL_TYPE_UINT:
5533 case GLSL_TYPE_BOOL:
5534 case GLSL_TYPE_SUBROUTINE:
5535 return ctx->ac.i32;
5536 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5537 return ctx->ac.f32;
5538 case GLSL_TYPE_INT64:
5539 case GLSL_TYPE_UINT64:
5540 return ctx->ac.i64;
5541 case GLSL_TYPE_DOUBLE:
5542 return ctx->ac.f64;
5543 default:
5544 unreachable("unknown GLSL type");
5545 }
5546 }
5547
5548 static LLVMTypeRef
5549 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5550 const struct glsl_type *type)
5551 {
5552 if (glsl_type_is_scalar(type)) {
5553 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5554 }
5555
5556 if (glsl_type_is_vector(type)) {
5557 return LLVMVectorType(
5558 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5559 glsl_get_vector_elements(type));
5560 }
5561
5562 if (glsl_type_is_matrix(type)) {
5563 return LLVMArrayType(
5564 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5565 glsl_get_matrix_columns(type));
5566 }
5567
5568 if (glsl_type_is_array(type)) {
5569 return LLVMArrayType(
5570 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5571 glsl_get_length(type));
5572 }
5573
5574 assert(glsl_type_is_struct(type));
5575
5576 LLVMTypeRef member_types[glsl_get_length(type)];
5577
5578 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5579 member_types[i] =
5580 glsl_to_llvm_type(ctx,
5581 glsl_get_struct_field(type, i));
5582 }
5583
5584 return LLVMStructTypeInContext(ctx->context, member_types,
5585 glsl_get_length(type), false);
5586 }
5587
5588 static void
5589 setup_locals(struct ac_nir_context *ctx,
5590 struct nir_function *func)
5591 {
5592 int i, j;
5593 ctx->num_locals = 0;
5594 nir_foreach_variable(variable, &func->impl->locals) {
5595 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5596 variable->data.driver_location = ctx->num_locals * 4;
5597 variable->data.location_frac = 0;
5598 ctx->num_locals += attrib_count;
5599 }
5600 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5601 if (!ctx->locals)
5602 return;
5603
5604 for (i = 0; i < ctx->num_locals; i++) {
5605 for (j = 0; j < 4; j++) {
5606 ctx->locals[i * 4 + j] =
5607 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5608 }
5609 }
5610 }
5611
5612 static void
5613 setup_shared(struct ac_nir_context *ctx,
5614 struct nir_shader *nir)
5615 {
5616 nir_foreach_variable(variable, &nir->shared) {
5617 LLVMValueRef shared =
5618 LLVMAddGlobalInAddressSpace(
5619 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5620 variable->name ? variable->name : "",
5621 LOCAL_ADDR_SPACE);
5622 _mesa_hash_table_insert(ctx->vars, variable, shared);
5623 }
5624 }
5625
5626 static LLVMValueRef
5627 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5628 {
5629 v = ac_to_float(ctx, v);
5630 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5631 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5632 }
5633
5634
5635 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5636 LLVMValueRef src0, LLVMValueRef src1)
5637 {
5638 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5639 LLVMValueRef comp[2];
5640
5641 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5642 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5643 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5644 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5645 }
5646
5647 /* Initialize arguments for the shader export intrinsic */
5648 static void
5649 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5650 LLVMValueRef *values,
5651 unsigned target,
5652 struct ac_export_args *args)
5653 {
5654 /* Default is 0xf. Adjusted below depending on the format. */
5655 args->enabled_channels = 0xf;
5656
5657 /* Specify whether the EXEC mask represents the valid mask */
5658 args->valid_mask = 0;
5659
5660 /* Specify whether this is the last export */
5661 args->done = 0;
5662
5663 /* Specify the target we are exporting */
5664 args->target = target;
5665
5666 args->compr = false;
5667 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5668 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5669 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5670 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5671
5672 if (!values)
5673 return;
5674
5675 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5676 LLVMValueRef val[4];
5677 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5678 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5679 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5680 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5681
5682 switch(col_format) {
5683 case V_028714_SPI_SHADER_ZERO:
5684 args->enabled_channels = 0; /* writemask */
5685 args->target = V_008DFC_SQ_EXP_NULL;
5686 break;
5687
5688 case V_028714_SPI_SHADER_32_R:
5689 args->enabled_channels = 1;
5690 args->out[0] = values[0];
5691 break;
5692
5693 case V_028714_SPI_SHADER_32_GR:
5694 args->enabled_channels = 0x3;
5695 args->out[0] = values[0];
5696 args->out[1] = values[1];
5697 break;
5698
5699 case V_028714_SPI_SHADER_32_AR:
5700 args->enabled_channels = 0x9;
5701 args->out[0] = values[0];
5702 args->out[3] = values[3];
5703 break;
5704
5705 case V_028714_SPI_SHADER_FP16_ABGR:
5706 args->compr = 1;
5707
5708 for (unsigned chan = 0; chan < 2; chan++) {
5709 LLVMValueRef pack_args[2] = {
5710 values[2 * chan],
5711 values[2 * chan + 1]
5712 };
5713 LLVMValueRef packed;
5714
5715 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5716 args->out[chan] = packed;
5717 }
5718 break;
5719
5720 case V_028714_SPI_SHADER_UNORM16_ABGR:
5721 for (unsigned chan = 0; chan < 4; chan++) {
5722 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5723 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5724 LLVMConstReal(ctx->ac.f32, 65535), "");
5725 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5726 LLVMConstReal(ctx->ac.f32, 0.5), "");
5727 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5728 ctx->ac.i32, "");
5729 }
5730
5731 args->compr = 1;
5732 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5733 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5734 break;
5735
5736 case V_028714_SPI_SHADER_SNORM16_ABGR:
5737 for (unsigned chan = 0; chan < 4; chan++) {
5738 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5739 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5740 LLVMConstReal(ctx->ac.f32, 32767), "");
5741
5742 /* If positive, add 0.5, else add -0.5. */
5743 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5744 LLVMBuildSelect(ctx->builder,
5745 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5746 val[chan], ctx->ac.f32_0, ""),
5747 LLVMConstReal(ctx->ac.f32, 0.5),
5748 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5749 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5750 }
5751
5752 args->compr = 1;
5753 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5754 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5755 break;
5756
5757 case V_028714_SPI_SHADER_UINT16_ABGR: {
5758 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5759 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5760 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5761
5762 for (unsigned chan = 0; chan < 4; chan++) {
5763 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5764 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5765 }
5766
5767 args->compr = 1;
5768 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5769 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5770 break;
5771 }
5772
5773 case V_028714_SPI_SHADER_SINT16_ABGR: {
5774 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5775 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5776 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5777 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5778 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5779 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5780
5781 /* Clamp. */
5782 for (unsigned chan = 0; chan < 4; chan++) {
5783 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5784 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5785 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5786 }
5787
5788 args->compr = 1;
5789 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5790 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5791 break;
5792 }
5793
5794 default:
5795 case V_028714_SPI_SHADER_32_ABGR:
5796 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5797 break;
5798 }
5799 } else
5800 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5801
5802 for (unsigned i = 0; i < 4; ++i)
5803 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5804 }
5805
5806 static void
5807 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5808 bool export_prim_id,
5809 struct ac_vs_output_info *outinfo)
5810 {
5811 uint32_t param_count = 0;
5812 unsigned target;
5813 unsigned pos_idx, num_pos_exports = 0;
5814 struct ac_export_args args, pos_args[4] = {};
5815 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5816 int i;
5817
5818 if (ctx->options->key.has_multiview_view_index) {
5819 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5820 if(!*tmp_out) {
5821 for(unsigned i = 0; i < 4; ++i)
5822 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5823 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5824 }
5825
5826 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5827 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5828 }
5829
5830 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5831 sizeof(outinfo->vs_output_param_offset));
5832
5833 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5834 LLVMValueRef slots[8];
5835 unsigned j;
5836
5837 if (outinfo->cull_dist_mask)
5838 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5839
5840 i = VARYING_SLOT_CLIP_DIST0;
5841 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5842 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5843 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5844
5845 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5846 slots[i] = LLVMGetUndef(ctx->ac.f32);
5847
5848 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5849 target = V_008DFC_SQ_EXP_POS + 3;
5850 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5851 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5852 &args, sizeof(args));
5853 }
5854
5855 target = V_008DFC_SQ_EXP_POS + 2;
5856 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5857 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5858 &args, sizeof(args));
5859
5860 }
5861
5862 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5863 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5864 for (unsigned j = 0; j < 4; j++)
5865 pos_values[j] = LLVMBuildLoad(ctx->builder,
5866 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5867 }
5868 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5869
5870 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5871 outinfo->writes_pointsize = true;
5872 psize_value = LLVMBuildLoad(ctx->builder,
5873 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5874 }
5875
5876 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5877 outinfo->writes_layer = true;
5878 layer_value = LLVMBuildLoad(ctx->builder,
5879 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5880 }
5881
5882 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5883 outinfo->writes_viewport_index = true;
5884 viewport_index_value = LLVMBuildLoad(ctx->builder,
5885 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5886 }
5887
5888 if (outinfo->writes_pointsize ||
5889 outinfo->writes_layer ||
5890 outinfo->writes_viewport_index) {
5891 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5892 (outinfo->writes_layer == true ? 4 : 0));
5893 pos_args[1].valid_mask = 0;
5894 pos_args[1].done = 0;
5895 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5896 pos_args[1].compr = 0;
5897 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5898 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5899 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5900 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5901
5902 if (outinfo->writes_pointsize == true)
5903 pos_args[1].out[0] = psize_value;
5904 if (outinfo->writes_layer == true)
5905 pos_args[1].out[2] = layer_value;
5906 if (outinfo->writes_viewport_index == true) {
5907 if (ctx->options->chip_class >= GFX9) {
5908 /* GFX9 has the layer in out.z[10:0] and the viewport
5909 * index in out.z[19:16].
5910 */
5911 LLVMValueRef v = viewport_index_value;
5912 v = ac_to_integer(&ctx->ac, v);
5913 v = LLVMBuildShl(ctx->builder, v,
5914 LLVMConstInt(ctx->ac.i32, 16, false),
5915 "");
5916 v = LLVMBuildOr(ctx->builder, v,
5917 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5918
5919 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5920 pos_args[1].enabled_channels |= 1 << 2;
5921 } else {
5922 pos_args[1].out[3] = viewport_index_value;
5923 pos_args[1].enabled_channels |= 1 << 3;
5924 }
5925 }
5926 }
5927 for (i = 0; i < 4; i++) {
5928 if (pos_args[i].out[0])
5929 num_pos_exports++;
5930 }
5931
5932 pos_idx = 0;
5933 for (i = 0; i < 4; i++) {
5934 if (!pos_args[i].out[0])
5935 continue;
5936
5937 /* Specify the target we are exporting */
5938 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5939 if (pos_idx == num_pos_exports)
5940 pos_args[i].done = 1;
5941 ac_build_export(&ctx->ac, &pos_args[i]);
5942 }
5943
5944 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5945 LLVMValueRef values[4];
5946 if (!(ctx->output_mask & (1ull << i)))
5947 continue;
5948
5949 for (unsigned j = 0; j < 4; j++)
5950 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5951 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5952
5953 if (i == VARYING_SLOT_LAYER) {
5954 target = V_008DFC_SQ_EXP_PARAM + param_count;
5955 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5956 param_count++;
5957 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5958 target = V_008DFC_SQ_EXP_PARAM + param_count;
5959 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5960 param_count++;
5961 } else if (i >= VARYING_SLOT_VAR0) {
5962 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5963 target = V_008DFC_SQ_EXP_PARAM + param_count;
5964 outinfo->vs_output_param_offset[i] = param_count;
5965 param_count++;
5966 } else
5967 continue;
5968
5969 si_llvm_init_export_args(ctx, values, target, &args);
5970
5971 if (target >= V_008DFC_SQ_EXP_POS &&
5972 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5973 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5974 &args, sizeof(args));
5975 } else {
5976 ac_build_export(&ctx->ac, &args);
5977 }
5978 }
5979
5980 if (export_prim_id) {
5981 LLVMValueRef values[4];
5982 target = V_008DFC_SQ_EXP_PARAM + param_count;
5983 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5984 param_count++;
5985
5986 values[0] = ctx->vs_prim_id;
5987 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5988 ctx->shader_info->vs.vgpr_comp_cnt);
5989 for (unsigned j = 1; j < 4; j++)
5990 values[j] = ctx->ac.f32_0;
5991 si_llvm_init_export_args(ctx, values, target, &args);
5992 ac_build_export(&ctx->ac, &args);
5993 outinfo->export_prim_id = true;
5994 }
5995
5996 outinfo->pos_exports = num_pos_exports;
5997 outinfo->param_exports = param_count;
5998 }
5999
6000 static void
6001 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6002 struct ac_es_output_info *outinfo)
6003 {
6004 int j;
6005 uint64_t max_output_written = 0;
6006 LLVMValueRef lds_base = NULL;
6007
6008 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6009 int param_index;
6010 int length = 4;
6011
6012 if (!(ctx->output_mask & (1ull << i)))
6013 continue;
6014
6015 if (i == VARYING_SLOT_CLIP_DIST0)
6016 length = ctx->num_output_clips + ctx->num_output_culls;
6017
6018 param_index = shader_io_get_unique_index(i);
6019
6020 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6021 }
6022
6023 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6024
6025 if (ctx->ac.chip_class >= GFX9) {
6026 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6027 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6028 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6029 LLVMConstInt(ctx->ac.i32, 24, false),
6030 LLVMConstInt(ctx->ac.i32, 4, false), false);
6031 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6032 LLVMBuildMul(ctx->ac.builder, wave_idx,
6033 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6034 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6035 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6036 }
6037
6038 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6039 LLVMValueRef dw_addr;
6040 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6041 int param_index;
6042 int length = 4;
6043
6044 if (!(ctx->output_mask & (1ull << i)))
6045 continue;
6046
6047 if (i == VARYING_SLOT_CLIP_DIST0)
6048 length = ctx->num_output_clips + ctx->num_output_culls;
6049
6050 param_index = shader_io_get_unique_index(i);
6051
6052 if (lds_base) {
6053 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6054 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6055 "");
6056 }
6057 for (j = 0; j < length; j++) {
6058 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6059 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6060
6061 if (ctx->ac.chip_class >= GFX9) {
6062 ac_lds_store(&ctx->ac, dw_addr,
6063 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6064 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6065 } else {
6066 ac_build_buffer_store_dword(&ctx->ac,
6067 ctx->esgs_ring,
6068 out_val, 1,
6069 NULL, ctx->es2gs_offset,
6070 (4 * param_index + j) * 4,
6071 1, 1, true, true);
6072 }
6073 }
6074 }
6075 }
6076
6077 static void
6078 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6079 {
6080 LLVMValueRef vertex_id = ctx->rel_auto_id;
6081 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6082 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6083 vertex_dw_stride, "");
6084
6085 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6086 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6087 int length = 4;
6088
6089 if (!(ctx->output_mask & (1ull << i)))
6090 continue;
6091
6092 if (i == VARYING_SLOT_CLIP_DIST0)
6093 length = ctx->num_output_clips + ctx->num_output_culls;
6094 int param = shader_io_get_unique_index(i);
6095 mark_tess_output(ctx, false, param);
6096 if (length > 4)
6097 mark_tess_output(ctx, false, param + 1);
6098 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6099 LLVMConstInt(ctx->ac.i32, param * 4, false),
6100 "");
6101 for (unsigned j = 0; j < length; j++) {
6102 ac_lds_store(&ctx->ac, dw_addr,
6103 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6104 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6105 }
6106 }
6107 }
6108
6109 struct ac_build_if_state
6110 {
6111 struct nir_to_llvm_context *ctx;
6112 LLVMValueRef condition;
6113 LLVMBasicBlockRef entry_block;
6114 LLVMBasicBlockRef true_block;
6115 LLVMBasicBlockRef false_block;
6116 LLVMBasicBlockRef merge_block;
6117 };
6118
6119 static LLVMBasicBlockRef
6120 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6121 {
6122 LLVMBasicBlockRef current_block;
6123 LLVMBasicBlockRef next_block;
6124 LLVMBasicBlockRef new_block;
6125
6126 /* get current basic block */
6127 current_block = LLVMGetInsertBlock(ctx->builder);
6128
6129 /* chqeck if there's another block after this one */
6130 next_block = LLVMGetNextBasicBlock(current_block);
6131 if (next_block) {
6132 /* insert the new block before the next block */
6133 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6134 }
6135 else {
6136 /* append new block after current block */
6137 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6138 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6139 }
6140 return new_block;
6141 }
6142
6143 static void
6144 ac_nir_build_if(struct ac_build_if_state *ifthen,
6145 struct nir_to_llvm_context *ctx,
6146 LLVMValueRef condition)
6147 {
6148 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6149
6150 memset(ifthen, 0, sizeof *ifthen);
6151 ifthen->ctx = ctx;
6152 ifthen->condition = condition;
6153 ifthen->entry_block = block;
6154
6155 /* create endif/merge basic block for the phi functions */
6156 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6157
6158 /* create/insert true_block before merge_block */
6159 ifthen->true_block =
6160 LLVMInsertBasicBlockInContext(ctx->context,
6161 ifthen->merge_block,
6162 "if-true-block");
6163
6164 /* successive code goes into the true block */
6165 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6166 }
6167
6168 /**
6169 * End a conditional.
6170 */
6171 static void
6172 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6173 {
6174 LLVMBuilderRef builder = ifthen->ctx->builder;
6175
6176 /* Insert branch to the merge block from current block */
6177 LLVMBuildBr(builder, ifthen->merge_block);
6178
6179 /*
6180 * Now patch in the various branch instructions.
6181 */
6182
6183 /* Insert the conditional branch instruction at the end of entry_block */
6184 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6185 if (ifthen->false_block) {
6186 /* we have an else clause */
6187 LLVMBuildCondBr(builder, ifthen->condition,
6188 ifthen->true_block, ifthen->false_block);
6189 }
6190 else {
6191 /* no else clause */
6192 LLVMBuildCondBr(builder, ifthen->condition,
6193 ifthen->true_block, ifthen->merge_block);
6194 }
6195
6196 /* Resume building code at end of the ifthen->merge_block */
6197 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6198 }
6199
6200 static void
6201 write_tess_factors(struct nir_to_llvm_context *ctx)
6202 {
6203 unsigned stride, outer_comps, inner_comps;
6204 struct ac_build_if_state if_ctx, inner_if_ctx;
6205 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6206 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6207 unsigned tess_inner_index, tess_outer_index;
6208 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6209 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6210 int i;
6211 emit_barrier(&ctx->ac, ctx->stage);
6212
6213 switch (ctx->options->key.tcs.primitive_mode) {
6214 case GL_ISOLINES:
6215 stride = 2;
6216 outer_comps = 2;
6217 inner_comps = 0;
6218 break;
6219 case GL_TRIANGLES:
6220 stride = 4;
6221 outer_comps = 3;
6222 inner_comps = 1;
6223 break;
6224 case GL_QUADS:
6225 stride = 6;
6226 outer_comps = 4;
6227 inner_comps = 2;
6228 break;
6229 default:
6230 return;
6231 }
6232
6233 ac_nir_build_if(&if_ctx, ctx,
6234 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6235 invocation_id, ctx->ac.i32_0, ""));
6236
6237 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6238 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6239
6240 mark_tess_output(ctx, true, tess_inner_index);
6241 mark_tess_output(ctx, true, tess_outer_index);
6242 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6243 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6244 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6245 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6246 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6247
6248 for (i = 0; i < 4; i++) {
6249 inner[i] = LLVMGetUndef(ctx->ac.i32);
6250 outer[i] = LLVMGetUndef(ctx->ac.i32);
6251 }
6252
6253 // LINES reverseal
6254 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6255 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6256 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6257 ctx->ac.i32_1, "");
6258 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6259 } else {
6260 for (i = 0; i < outer_comps; i++) {
6261 outer[i] = out[i] =
6262 ac_lds_load(&ctx->ac, lds_outer);
6263 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6264 ctx->ac.i32_1, "");
6265 }
6266 for (i = 0; i < inner_comps; i++) {
6267 inner[i] = out[outer_comps+i] =
6268 ac_lds_load(&ctx->ac, lds_inner);
6269 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6270 ctx->ac.i32_1, "");
6271 }
6272 }
6273
6274 /* Convert the outputs to vectors for stores. */
6275 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6276 vec1 = NULL;
6277
6278 if (stride > 4)
6279 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6280
6281
6282 buffer = ctx->hs_ring_tess_factor;
6283 tf_base = ctx->tess_factor_offset;
6284 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6285 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6286 unsigned tf_offset = 0;
6287
6288 if (ctx->options->chip_class <= VI) {
6289 ac_nir_build_if(&inner_if_ctx, ctx,
6290 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6291 rel_patch_id, ctx->ac.i32_0, ""));
6292
6293 /* Store the dynamic HS control word. */
6294 ac_build_buffer_store_dword(&ctx->ac, buffer,
6295 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6296 1, ctx->ac.i32_0, tf_base,
6297 0, 1, 0, true, false);
6298 tf_offset += 4;
6299
6300 ac_nir_build_endif(&inner_if_ctx);
6301 }
6302
6303 /* Store the tessellation factors. */
6304 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6305 MIN2(stride, 4), byteoffset, tf_base,
6306 tf_offset, 1, 0, true, false);
6307 if (vec1)
6308 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6309 stride - 4, byteoffset, tf_base,
6310 16 + tf_offset, 1, 0, true, false);
6311
6312 //store to offchip for TES to read - only if TES reads them
6313 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6314 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6315 LLVMValueRef tf_inner_offset;
6316 unsigned param_outer, param_inner;
6317
6318 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6319 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6320 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6321
6322 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6323 util_next_power_of_two(outer_comps));
6324
6325 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6326 outer_comps, tf_outer_offset,
6327 ctx->oc_lds, 0, 1, 0, true, false);
6328 if (inner_comps) {
6329 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6330 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6331 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6332
6333 inner_vec = inner_comps == 1 ? inner[0] :
6334 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6335 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6336 inner_comps, tf_inner_offset,
6337 ctx->oc_lds, 0, 1, 0, true, false);
6338 }
6339 }
6340 ac_nir_build_endif(&if_ctx);
6341 }
6342
6343 static void
6344 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6345 {
6346 write_tess_factors(ctx);
6347 }
6348
6349 static bool
6350 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6351 LLVMValueRef *color, unsigned param, bool is_last,
6352 struct ac_export_args *args)
6353 {
6354 /* Export */
6355 si_llvm_init_export_args(ctx, color, param,
6356 args);
6357
6358 if (is_last) {
6359 args->valid_mask = 1; /* whether the EXEC mask is valid */
6360 args->done = 1; /* DONE bit */
6361 } else if (!args->enabled_channels)
6362 return false; /* unnecessary NULL export */
6363
6364 return true;
6365 }
6366
6367 static void
6368 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6369 LLVMValueRef depth, LLVMValueRef stencil,
6370 LLVMValueRef samplemask)
6371 {
6372 struct ac_export_args args;
6373
6374 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6375
6376 ac_build_export(&ctx->ac, &args);
6377 }
6378
6379 static void
6380 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6381 {
6382 unsigned index = 0;
6383 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6384 struct ac_export_args color_args[8];
6385
6386 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6387 LLVMValueRef values[4];
6388
6389 if (!(ctx->output_mask & (1ull << i)))
6390 continue;
6391
6392 if (i == FRAG_RESULT_DEPTH) {
6393 ctx->shader_info->fs.writes_z = true;
6394 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6395 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6396 } else if (i == FRAG_RESULT_STENCIL) {
6397 ctx->shader_info->fs.writes_stencil = true;
6398 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6399 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6400 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6401 ctx->shader_info->fs.writes_sample_mask = true;
6402 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6403 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6404 } else {
6405 bool last = false;
6406 for (unsigned j = 0; j < 4; j++)
6407 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6408 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6409
6410 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6411 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6412
6413 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6414 if (ret)
6415 index++;
6416 }
6417 }
6418
6419 for (unsigned i = 0; i < index; i++)
6420 ac_build_export(&ctx->ac, &color_args[i]);
6421 if (depth || stencil || samplemask)
6422 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6423 else if (!index) {
6424 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6425 ac_build_export(&ctx->ac, &color_args[0]);
6426 }
6427 }
6428
6429 static void
6430 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6431 {
6432 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6433 }
6434
6435 static void
6436 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6437 LLVMValueRef *addrs)
6438 {
6439 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6440
6441 switch (ctx->stage) {
6442 case MESA_SHADER_VERTEX:
6443 if (ctx->options->key.vs.as_ls)
6444 handle_ls_outputs_post(ctx);
6445 else if (ctx->options->key.vs.as_es)
6446 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6447 else
6448 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6449 &ctx->shader_info->vs.outinfo);
6450 break;
6451 case MESA_SHADER_FRAGMENT:
6452 handle_fs_outputs_post(ctx);
6453 break;
6454 case MESA_SHADER_GEOMETRY:
6455 emit_gs_epilogue(ctx);
6456 break;
6457 case MESA_SHADER_TESS_CTRL:
6458 handle_tcs_outputs_post(ctx);
6459 break;
6460 case MESA_SHADER_TESS_EVAL:
6461 if (ctx->options->key.tes.as_es)
6462 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6463 else
6464 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6465 &ctx->shader_info->tes.outinfo);
6466 break;
6467 default:
6468 break;
6469 }
6470 }
6471
6472 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6473 {
6474 LLVMPassManagerRef passmgr;
6475 /* Create the pass manager */
6476 passmgr = LLVMCreateFunctionPassManagerForModule(
6477 ctx->module);
6478
6479 /* This pass should eliminate all the load and store instructions */
6480 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6481
6482 /* Add some optimization passes */
6483 LLVMAddScalarReplAggregatesPass(passmgr);
6484 LLVMAddLICMPass(passmgr);
6485 LLVMAddAggressiveDCEPass(passmgr);
6486 LLVMAddCFGSimplificationPass(passmgr);
6487 LLVMAddInstructionCombiningPass(passmgr);
6488
6489 /* Run the pass */
6490 LLVMInitializeFunctionPassManager(passmgr);
6491 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6492 LLVMFinalizeFunctionPassManager(passmgr);
6493
6494 LLVMDisposeBuilder(ctx->builder);
6495 LLVMDisposePassManager(passmgr);
6496 }
6497
6498 static void
6499 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6500 {
6501 struct ac_vs_output_info *outinfo;
6502
6503 switch (ctx->stage) {
6504 case MESA_SHADER_FRAGMENT:
6505 case MESA_SHADER_COMPUTE:
6506 case MESA_SHADER_TESS_CTRL:
6507 case MESA_SHADER_GEOMETRY:
6508 return;
6509 case MESA_SHADER_VERTEX:
6510 if (ctx->options->key.vs.as_ls ||
6511 ctx->options->key.vs.as_es)
6512 return;
6513 outinfo = &ctx->shader_info->vs.outinfo;
6514 break;
6515 case MESA_SHADER_TESS_EVAL:
6516 if (ctx->options->key.vs.as_es)
6517 return;
6518 outinfo = &ctx->shader_info->tes.outinfo;
6519 break;
6520 default:
6521 unreachable("Unhandled shader type");
6522 }
6523
6524 ac_optimize_vs_outputs(&ctx->ac,
6525 ctx->main_function,
6526 outinfo->vs_output_param_offset,
6527 VARYING_SLOT_MAX,
6528 &outinfo->param_exports);
6529 }
6530
6531 static void
6532 ac_setup_rings(struct nir_to_llvm_context *ctx)
6533 {
6534 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6535 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6536 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6537 }
6538
6539 if (ctx->is_gs_copy_shader) {
6540 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6541 }
6542 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6543 LLVMValueRef tmp;
6544 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6545 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6546
6547 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6548
6549 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6550 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6551 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6552 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6553 }
6554
6555 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6556 ctx->stage == MESA_SHADER_TESS_EVAL) {
6557 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6558 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6559 }
6560 }
6561
6562 static unsigned
6563 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6564 const struct nir_shader *nir)
6565 {
6566 switch (nir->info.stage) {
6567 case MESA_SHADER_TESS_CTRL:
6568 return chip_class >= CIK ? 128 : 64;
6569 case MESA_SHADER_GEOMETRY:
6570 return chip_class >= GFX9 ? 128 : 64;
6571 case MESA_SHADER_COMPUTE:
6572 break;
6573 default:
6574 return 0;
6575 }
6576
6577 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6578 nir->info.cs.local_size[1] *
6579 nir->info.cs.local_size[2];
6580 return max_workgroup_size;
6581 }
6582
6583 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6584 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6585 {
6586 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6587 LLVMConstInt(ctx->ac.i32, 8, false),
6588 LLVMConstInt(ctx->ac.i32, 8, false), false);
6589 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6590 ctx->ac.i32_0, "");
6591 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6592 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6593 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6594 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6595 }
6596
6597 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6598 {
6599 for(int i = 5; i >= 0; --i) {
6600 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6601 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6602 LLVMConstInt(ctx->ac.i32, 16, false), false);
6603 }
6604
6605 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6606 LLVMConstInt(ctx->ac.i32, 16, false),
6607 LLVMConstInt(ctx->ac.i32, 8, false), false);
6608 }
6609
6610 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6611 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6612 {
6613 struct ac_nir_context ctx = {};
6614 struct nir_function *func;
6615
6616 ctx.ac = *ac;
6617 ctx.abi = abi;
6618
6619 ctx.nctx = nctx;
6620 if (nctx)
6621 nctx->nir = &ctx;
6622
6623 ctx.stage = nir->info.stage;
6624
6625 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6626
6627 nir_foreach_variable(variable, &nir->outputs)
6628 handle_shader_output_decl(&ctx, nir, variable);
6629
6630 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6631 _mesa_key_pointer_equal);
6632 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6633 _mesa_key_pointer_equal);
6634 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6635 _mesa_key_pointer_equal);
6636
6637 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6638
6639 setup_locals(&ctx, func);
6640
6641 if (nir->info.stage == MESA_SHADER_COMPUTE)
6642 setup_shared(&ctx, nir);
6643
6644 visit_cf_list(&ctx, &func->impl->body);
6645 phi_post_pass(&ctx);
6646
6647 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6648 ctx.outputs);
6649
6650 free(ctx.locals);
6651 ralloc_free(ctx.defs);
6652 ralloc_free(ctx.phis);
6653 ralloc_free(ctx.vars);
6654
6655 if (nctx)
6656 nctx->nir = NULL;
6657 }
6658
6659 static
6660 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6661 struct nir_shader *const *shaders,
6662 int shader_count,
6663 struct ac_shader_variant_info *shader_info,
6664 const struct ac_nir_compiler_options *options)
6665 {
6666 struct nir_to_llvm_context ctx = {0};
6667 unsigned i;
6668 ctx.options = options;
6669 ctx.shader_info = shader_info;
6670 ctx.context = LLVMContextCreate();
6671 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6672
6673 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6674 options->family);
6675 ctx.ac.module = ctx.module;
6676 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6677
6678 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6679 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6680 LLVMSetDataLayout(ctx.module, data_layout_str);
6681 LLVMDisposeTargetData(data_layout);
6682 LLVMDisposeMessage(data_layout_str);
6683
6684 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6685 ctx.ac.builder = ctx.builder;
6686
6687 memset(shader_info, 0, sizeof(*shader_info));
6688
6689 for(int i = 0; i < shader_count; ++i)
6690 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6691
6692 for (i = 0; i < AC_UD_MAX_SETS; i++)
6693 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6694 for (i = 0; i < AC_UD_MAX_UD; i++)
6695 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6696
6697 ctx.max_workgroup_size = 0;
6698 for (int i = 0; i < shader_count; ++i) {
6699 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6700 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6701 shaders[i]));
6702 }
6703
6704 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6705 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6706
6707 ctx.abi.inputs = &ctx.inputs[0];
6708 ctx.abi.emit_outputs = handle_shader_outputs_post;
6709 ctx.abi.emit_vertex = visit_emit_vertex;
6710 ctx.abi.load_ubo = radv_load_ubo;
6711 ctx.abi.load_ssbo = radv_load_ssbo;
6712 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6713 ctx.abi.clamp_shadow_reference = false;
6714
6715 if (shader_count >= 2)
6716 ac_init_exec_full_mask(&ctx.ac);
6717
6718 if (ctx.ac.chip_class == GFX9 &&
6719 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6720 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6721
6722 for(int i = 0; i < shader_count; ++i) {
6723 ctx.stage = shaders[i]->info.stage;
6724 ctx.output_mask = 0;
6725 ctx.tess_outputs_written = 0;
6726 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6727 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6728
6729 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6730 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6731 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6732 ctx.abi.load_inputs = load_gs_input;
6733 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6734 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6735 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6736 ctx.abi.load_tess_inputs = load_tcs_input;
6737 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6738 ctx.abi.store_tcs_outputs = store_tcs_output;
6739 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6740 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6741 ctx.abi.load_tess_inputs = load_tes_input;
6742 ctx.abi.load_tess_coord = load_tess_coord;
6743 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6744 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6745 if (shader_info->info.vs.needs_instance_id) {
6746 if (ctx.ac.chip_class == GFX9 &&
6747 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) {
6748 ctx.shader_info->vs.vgpr_comp_cnt =
6749 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6750 } else {
6751 ctx.shader_info->vs.vgpr_comp_cnt =
6752 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6753 }
6754 }
6755 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6756 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6757 }
6758
6759 if (i)
6760 emit_barrier(&ctx.ac, ctx.stage);
6761
6762 ac_setup_rings(&ctx);
6763
6764 LLVMBasicBlockRef merge_block;
6765 if (shader_count >= 2) {
6766 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6767 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6768 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6769
6770 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6771 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6772 LLVMConstInt(ctx.ac.i32, 8, false), false);
6773 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6774 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6775 thread_id, count, "");
6776 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6777
6778 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6779 }
6780
6781 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6782 handle_fs_inputs(&ctx, shaders[i]);
6783 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6784 handle_vs_inputs(&ctx, shaders[i]);
6785 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6786 prepare_gs_input_vgprs(&ctx);
6787
6788 nir_foreach_variable(variable, &shaders[i]->outputs)
6789 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6790
6791 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6792
6793 if (shader_count >= 2) {
6794 LLVMBuildBr(ctx.ac.builder, merge_block);
6795 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6796 }
6797
6798 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6799 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6800 shaders[i]->info.cull_distance_array_size > 4;
6801 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6802 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6803 shaders[i]->info.gs.vertices_out;
6804 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6805 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6806 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6807 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6808 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6809 }
6810 }
6811
6812 LLVMBuildRetVoid(ctx.builder);
6813
6814 ac_llvm_finalize_module(&ctx);
6815
6816 if (shader_count == 1)
6817 ac_nir_eliminate_const_vs_outputs(&ctx);
6818
6819 return ctx.module;
6820 }
6821
6822 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6823 {
6824 unsigned *retval = (unsigned *)context;
6825 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6826 char *description = LLVMGetDiagInfoDescription(di);
6827
6828 if (severity == LLVMDSError) {
6829 *retval = 1;
6830 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6831 description);
6832 }
6833
6834 LLVMDisposeMessage(description);
6835 }
6836
6837 static unsigned ac_llvm_compile(LLVMModuleRef M,
6838 struct ac_shader_binary *binary,
6839 LLVMTargetMachineRef tm)
6840 {
6841 unsigned retval = 0;
6842 char *err;
6843 LLVMContextRef llvm_ctx;
6844 LLVMMemoryBufferRef out_buffer;
6845 unsigned buffer_size;
6846 const char *buffer_data;
6847 LLVMBool mem_err;
6848
6849 /* Setup Diagnostic Handler*/
6850 llvm_ctx = LLVMGetModuleContext(M);
6851
6852 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6853 &retval);
6854
6855 /* Compile IR*/
6856 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6857 &err, &out_buffer);
6858
6859 /* Process Errors/Warnings */
6860 if (mem_err) {
6861 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6862 free(err);
6863 retval = 1;
6864 goto out;
6865 }
6866
6867 /* Extract Shader Code*/
6868 buffer_size = LLVMGetBufferSize(out_buffer);
6869 buffer_data = LLVMGetBufferStart(out_buffer);
6870
6871 ac_elf_read(buffer_data, buffer_size, binary);
6872
6873 /* Clean up */
6874 LLVMDisposeMemoryBuffer(out_buffer);
6875
6876 out:
6877 return retval;
6878 }
6879
6880 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6881 LLVMModuleRef llvm_module,
6882 struct ac_shader_binary *binary,
6883 struct ac_shader_config *config,
6884 struct ac_shader_variant_info *shader_info,
6885 gl_shader_stage stage,
6886 bool dump_shader, bool supports_spill)
6887 {
6888 if (dump_shader)
6889 ac_dump_module(llvm_module);
6890
6891 memset(binary, 0, sizeof(*binary));
6892 int v = ac_llvm_compile(llvm_module, binary, tm);
6893 if (v) {
6894 fprintf(stderr, "compile failed\n");
6895 }
6896
6897 if (dump_shader)
6898 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6899
6900 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6901
6902 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6903 LLVMDisposeModule(llvm_module);
6904 LLVMContextDispose(ctx);
6905
6906 if (stage == MESA_SHADER_FRAGMENT) {
6907 shader_info->num_input_vgprs = 0;
6908 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6909 shader_info->num_input_vgprs += 2;
6910 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6911 shader_info->num_input_vgprs += 2;
6912 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6913 shader_info->num_input_vgprs += 2;
6914 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6915 shader_info->num_input_vgprs += 3;
6916 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6917 shader_info->num_input_vgprs += 2;
6918 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6919 shader_info->num_input_vgprs += 2;
6920 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6921 shader_info->num_input_vgprs += 2;
6922 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6923 shader_info->num_input_vgprs += 1;
6924 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6925 shader_info->num_input_vgprs += 1;
6926 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6927 shader_info->num_input_vgprs += 1;
6928 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6929 shader_info->num_input_vgprs += 1;
6930 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6931 shader_info->num_input_vgprs += 1;
6932 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6933 shader_info->num_input_vgprs += 1;
6934 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6935 shader_info->num_input_vgprs += 1;
6936 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6937 shader_info->num_input_vgprs += 1;
6938 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6939 shader_info->num_input_vgprs += 1;
6940 }
6941 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6942
6943 /* +3 for scratch wave offset and VCC */
6944 config->num_sgprs = MAX2(config->num_sgprs,
6945 shader_info->num_input_sgprs + 3);
6946
6947 /* Enable 64-bit and 16-bit denormals, because there is no performance
6948 * cost.
6949 *
6950 * If denormals are enabled, all floating-point output modifiers are
6951 * ignored.
6952 *
6953 * Don't enable denormals for 32-bit floats, because:
6954 * - Floating-point output modifiers would be ignored by the hw.
6955 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6956 * have to stop using those.
6957 * - SI & CI would be very slow.
6958 */
6959 config->float_mode |= V_00B028_FP_64_DENORMS;
6960 }
6961
6962 static void
6963 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6964 {
6965 switch (nir->info.stage) {
6966 case MESA_SHADER_COMPUTE:
6967 for (int i = 0; i < 3; ++i)
6968 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6969 break;
6970 case MESA_SHADER_FRAGMENT:
6971 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6972 break;
6973 case MESA_SHADER_GEOMETRY:
6974 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6975 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6976 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6977 shader_info->gs.invocations = nir->info.gs.invocations;
6978 break;
6979 case MESA_SHADER_TESS_EVAL:
6980 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6981 shader_info->tes.spacing = nir->info.tess.spacing;
6982 shader_info->tes.ccw = nir->info.tess.ccw;
6983 shader_info->tes.point_mode = nir->info.tess.point_mode;
6984 shader_info->tes.as_es = options->key.tes.as_es;
6985 break;
6986 case MESA_SHADER_TESS_CTRL:
6987 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6988 break;
6989 case MESA_SHADER_VERTEX:
6990 shader_info->vs.as_es = options->key.vs.as_es;
6991 shader_info->vs.as_ls = options->key.vs.as_ls;
6992 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6993 if (options->key.vs.as_ls)
6994 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6995 break;
6996 default:
6997 break;
6998 }
6999 }
7000
7001 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7002 struct ac_shader_binary *binary,
7003 struct ac_shader_config *config,
7004 struct ac_shader_variant_info *shader_info,
7005 struct nir_shader *const *nir,
7006 int nir_count,
7007 const struct ac_nir_compiler_options *options,
7008 bool dump_shader)
7009 {
7010
7011 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7012 options);
7013
7014 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7015 for (int i = 0; i < nir_count; ++i)
7016 ac_fill_shader_info(shader_info, nir[i], options);
7017
7018 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7019 if (options->chip_class == GFX9) {
7020 if (nir_count == 2 &&
7021 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7022 shader_info->gs.es_type = nir[0]->info.stage;
7023 }
7024 }
7025 }
7026
7027 static void
7028 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7029 {
7030 LLVMValueRef args[9];
7031 args[0] = ctx->gsvs_ring;
7032 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7033 args[3] = ctx->ac.i32_0;
7034 args[4] = ctx->ac.i32_1; /* OFFEN */
7035 args[5] = ctx->ac.i32_0; /* IDXEN */
7036 args[6] = ctx->ac.i32_1; /* GLC */
7037 args[7] = ctx->ac.i32_1; /* SLC */
7038 args[8] = ctx->ac.i32_0; /* TFE */
7039
7040 int idx = 0;
7041
7042 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7043 int length = 4;
7044 int slot = idx;
7045 int slot_inc = 1;
7046 if (!(ctx->output_mask & (1ull << i)))
7047 continue;
7048
7049 if (i == VARYING_SLOT_CLIP_DIST0) {
7050 /* unpack clip and cull from a single set of slots */
7051 length = ctx->num_output_clips + ctx->num_output_culls;
7052 if (length > 4)
7053 slot_inc = 2;
7054 }
7055
7056 for (unsigned j = 0; j < length; j++) {
7057 LLVMValueRef value;
7058 args[2] = LLVMConstInt(ctx->ac.i32,
7059 (slot * 4 + j) *
7060 ctx->gs_max_out_vertices * 16 * 4, false);
7061
7062 value = ac_build_intrinsic(&ctx->ac,
7063 "llvm.SI.buffer.load.dword.i32.i32",
7064 ctx->ac.i32, args, 9,
7065 AC_FUNC_ATTR_READONLY |
7066 AC_FUNC_ATTR_LEGACY);
7067
7068 LLVMBuildStore(ctx->builder,
7069 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7070 }
7071 idx += slot_inc;
7072 }
7073 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7074 }
7075
7076 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7077 struct nir_shader *geom_shader,
7078 struct ac_shader_binary *binary,
7079 struct ac_shader_config *config,
7080 struct ac_shader_variant_info *shader_info,
7081 const struct ac_nir_compiler_options *options,
7082 bool dump_shader)
7083 {
7084 struct nir_to_llvm_context ctx = {0};
7085 ctx.context = LLVMContextCreate();
7086 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7087 ctx.options = options;
7088 ctx.shader_info = shader_info;
7089
7090 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7091 options->family);
7092 ctx.ac.module = ctx.module;
7093
7094 ctx.is_gs_copy_shader = true;
7095 LLVMSetTarget(ctx.module, "amdgcn--");
7096
7097 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7098 ctx.ac.builder = ctx.builder;
7099 ctx.stage = MESA_SHADER_VERTEX;
7100
7101 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7102
7103 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7104 ac_setup_rings(&ctx);
7105
7106 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7107 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7108
7109 struct ac_nir_context nir_ctx = {};
7110 nir_ctx.ac = ctx.ac;
7111 nir_ctx.abi = &ctx.abi;
7112
7113 nir_ctx.nctx = &ctx;
7114 ctx.nir = &nir_ctx;
7115
7116 nir_foreach_variable(variable, &geom_shader->outputs) {
7117 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7118 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7119 }
7120
7121 ac_gs_copy_shader_emit(&ctx);
7122
7123 ctx.nir = NULL;
7124
7125 LLVMBuildRetVoid(ctx.builder);
7126
7127 ac_llvm_finalize_module(&ctx);
7128
7129 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7130 MESA_SHADER_VERTEX,
7131 dump_shader, options->supports_spill);
7132 }