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ac: rename and move si_const_array into common code
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 struct hash_table *defs;
87 struct hash_table *phis;
88
89 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
90 LLVMValueRef ring_offsets;
91 LLVMValueRef push_constants;
92 LLVMValueRef view_index;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids[3];
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef merged_wave_info;
110 LLVMValueRef tess_factor_offset;
111 LLVMValueRef tes_rel_patch_id;
112 LLVMValueRef tes_u;
113 LLVMValueRef tes_v;
114
115 LLVMValueRef gsvs_ring_stride;
116 LLVMValueRef gsvs_num_entries;
117 LLVMValueRef gs2vs_offset;
118 LLVMValueRef gs_wave_id;
119 LLVMValueRef gs_vtx_offset[6];
120
121 LLVMValueRef esgs_ring;
122 LLVMValueRef gsvs_ring;
123 LLVMValueRef hs_ring_tess_offchip;
124 LLVMValueRef hs_ring_tess_factor;
125
126 LLVMValueRef prim_mask;
127 LLVMValueRef sample_pos_offset;
128 LLVMValueRef persp_sample, persp_center, persp_centroid;
129 LLVMValueRef linear_sample, linear_center, linear_centroid;
130
131 gl_shader_stage stage;
132
133 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
134
135 uint64_t input_mask;
136 uint64_t output_mask;
137 uint8_t num_output_clips;
138 uint8_t num_output_culls;
139
140 bool is_gs_copy_shader;
141 LLVMValueRef gs_next_vertex;
142 unsigned gs_max_out_vertices;
143
144 unsigned tes_primitive_mode;
145 uint64_t tess_outputs_written;
146 uint64_t tess_patch_outputs_written;
147
148 uint32_t tcs_patch_outputs_read;
149 uint64_t tcs_outputs_read;
150 };
151
152 static inline struct nir_to_llvm_context *
153 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
154 {
155 struct nir_to_llvm_context *ctx = NULL;
156 return container_of(abi, ctx, abi);
157 }
158
159 static LLVMTypeRef
160 nir2llvmtype(struct ac_nir_context *ctx,
161 const struct glsl_type *type)
162 {
163 switch (glsl_get_base_type(glsl_without_array(type))) {
164 case GLSL_TYPE_UINT:
165 case GLSL_TYPE_INT:
166 return ctx->ac.i32;
167 case GLSL_TYPE_UINT64:
168 case GLSL_TYPE_INT64:
169 return ctx->ac.i64;
170 case GLSL_TYPE_DOUBLE:
171 return ctx->ac.f64;
172 case GLSL_TYPE_FLOAT:
173 return ctx->ac.f32;
174 default:
175 assert(!"Unsupported type in nir2llvmtype()");
176 break;
177 }
178 return 0;
179 }
180
181 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
182 const nir_deref_var *deref,
183 enum ac_descriptor_type desc_type,
184 const nir_tex_instr *instr,
185 bool image, bool write);
186
187 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
188 {
189 return (index * 4) + chan;
190 }
191
192 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
193 {
194 /* handle patch indices separate */
195 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
196 return 0;
197 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
198 return 1;
199 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
200 return 2 + (slot - VARYING_SLOT_PATCH0);
201
202 if (slot == VARYING_SLOT_POS)
203 return 0;
204 if (slot == VARYING_SLOT_PSIZ)
205 return 1;
206 if (slot == VARYING_SLOT_CLIP_DIST0)
207 return 2;
208 /* 3 is reserved for clip dist as well */
209 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
210 return 4 + (slot - VARYING_SLOT_VAR0);
211 unreachable("illegal slot in get unique index\n");
212 }
213
214 static void set_llvm_calling_convention(LLVMValueRef func,
215 gl_shader_stage stage)
216 {
217 enum radeon_llvm_calling_convention calling_conv;
218
219 switch (stage) {
220 case MESA_SHADER_VERTEX:
221 case MESA_SHADER_TESS_EVAL:
222 calling_conv = RADEON_LLVM_AMDGPU_VS;
223 break;
224 case MESA_SHADER_GEOMETRY:
225 calling_conv = RADEON_LLVM_AMDGPU_GS;
226 break;
227 case MESA_SHADER_TESS_CTRL:
228 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_FRAGMENT:
231 calling_conv = RADEON_LLVM_AMDGPU_PS;
232 break;
233 case MESA_SHADER_COMPUTE:
234 calling_conv = RADEON_LLVM_AMDGPU_CS;
235 break;
236 default:
237 unreachable("Unhandle shader type");
238 }
239
240 LLVMSetFunctionCallConv(func, calling_conv);
241 }
242
243 #define MAX_ARGS 23
244 struct arg_info {
245 LLVMTypeRef types[MAX_ARGS];
246 LLVMValueRef *assign[MAX_ARGS];
247 unsigned array_params_mask;
248 uint8_t count;
249 uint8_t sgpr_count;
250 uint8_t num_sgprs_used;
251 uint8_t num_vgprs_used;
252 };
253
254 enum ac_arg_regfile {
255 ARG_SGPR,
256 ARG_VGPR,
257 };
258
259 static void
260 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
261 LLVMValueRef *param_ptr)
262 {
263 assert(info->count < MAX_ARGS);
264
265 info->assign[info->count] = param_ptr;
266 info->types[info->count] = type;
267 info->count++;
268
269 if (regfile == ARG_SGPR) {
270 info->num_sgprs_used += ac_get_type_size(type) / 4;
271 info->sgpr_count++;
272 } else {
273 assert(regfile == ARG_VGPR);
274 info->num_vgprs_used += ac_get_type_size(type) / 4;
275 }
276 }
277
278 static inline void
279 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
280 {
281 info->array_params_mask |= (1 << info->count);
282 add_arg(info, ARG_SGPR, type, param_ptr);
283 }
284
285 static void assign_arguments(LLVMValueRef main_function,
286 struct arg_info *info)
287 {
288 unsigned i;
289 for (i = 0; i < info->count; i++) {
290 if (info->assign[i])
291 *info->assign[i] = LLVMGetParam(main_function, i);
292 }
293 }
294
295 static LLVMValueRef
296 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
297 LLVMBuilderRef builder, LLVMTypeRef *return_types,
298 unsigned num_return_elems,
299 struct arg_info *args,
300 unsigned max_workgroup_size,
301 bool unsafe_math)
302 {
303 LLVMTypeRef main_function_type, ret_type;
304 LLVMBasicBlockRef main_function_body;
305
306 if (num_return_elems)
307 ret_type = LLVMStructTypeInContext(ctx, return_types,
308 num_return_elems, true);
309 else
310 ret_type = LLVMVoidTypeInContext(ctx);
311
312 /* Setup the function */
313 main_function_type =
314 LLVMFunctionType(ret_type, args->types, args->count, 0);
315 LLVMValueRef main_function =
316 LLVMAddFunction(module, "main", main_function_type);
317 main_function_body =
318 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
319 LLVMPositionBuilderAtEnd(builder, main_function_body);
320
321 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
322 for (unsigned i = 0; i < args->sgpr_count; ++i) {
323 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
324
325 if (args->array_params_mask & (1 << i)) {
326 LLVMValueRef P = LLVMGetParam(main_function, i);
327 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
328 ac_add_attr_dereferenceable(P, UINT64_MAX);
329 }
330 }
331
332 if (max_workgroup_size) {
333 ac_llvm_add_target_dep_function_attr(main_function,
334 "amdgpu-max-work-group-size",
335 max_workgroup_size);
336 }
337 if (unsafe_math) {
338 /* These were copied from some LLVM test. */
339 LLVMAddTargetDependentFunctionAttr(main_function,
340 "less-precise-fpmad",
341 "true");
342 LLVMAddTargetDependentFunctionAttr(main_function,
343 "no-infs-fp-math",
344 "true");
345 LLVMAddTargetDependentFunctionAttr(main_function,
346 "no-nans-fp-math",
347 "true");
348 LLVMAddTargetDependentFunctionAttr(main_function,
349 "unsafe-fp-math",
350 "true");
351 LLVMAddTargetDependentFunctionAttr(main_function,
352 "no-signed-zeros-fp-math",
353 "true");
354 }
355 return main_function;
356 }
357
358 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
359 {
360 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
361 type = LLVMGetElementType(type);
362
363 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
364 return LLVMGetIntTypeWidth(type);
365
366 if (type == ctx->f16)
367 return 16;
368 if (type == ctx->f32)
369 return 32;
370 if (type == ctx->f64)
371 return 64;
372
373 unreachable("Unhandled type kind in get_elem_bits");
374 }
375
376 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
377 LLVMValueRef param, unsigned rshift,
378 unsigned bitwidth)
379 {
380 LLVMValueRef value = param;
381 if (rshift)
382 value = LLVMBuildLShr(ctx->builder, value,
383 LLVMConstInt(ctx->i32, rshift, false), "");
384
385 if (rshift + bitwidth < 32) {
386 unsigned mask = (1 << bitwidth) - 1;
387 value = LLVMBuildAnd(ctx->builder, value,
388 LLVMConstInt(ctx->i32, mask, false), "");
389 }
390 return value;
391 }
392
393 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
394 {
395 switch (ctx->stage) {
396 case MESA_SHADER_TESS_CTRL:
397 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
398 case MESA_SHADER_TESS_EVAL:
399 return ctx->tes_rel_patch_id;
400 break;
401 default:
402 unreachable("Illegal stage");
403 }
404 }
405
406 /* Tessellation shaders pass outputs to the next shader using LDS.
407 *
408 * LS outputs = TCS inputs
409 * TCS outputs = TES inputs
410 *
411 * The LDS layout is:
412 * - TCS inputs for patch 0
413 * - TCS inputs for patch 1
414 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
415 * - ...
416 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
417 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
418 * - TCS outputs for patch 1
419 * - Per-patch TCS outputs for patch 1
420 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
421 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
422 * - ...
423 *
424 * All three shaders VS(LS), TCS, TES share the same LDS space.
425 */
426 static LLVMValueRef
427 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
428 {
429 if (ctx->stage == MESA_SHADER_VERTEX)
430 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
431 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
432 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
433 else {
434 assert(0);
435 return NULL;
436 }
437 }
438
439 static LLVMValueRef
440 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
441 {
442 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
443 }
444
445 static LLVMValueRef
446 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
447 {
448 return LLVMBuildMul(ctx->builder,
449 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
450 LLVMConstInt(ctx->ac.i32, 4, false), "");
451 }
452
453 static LLVMValueRef
454 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
455 {
456 return LLVMBuildMul(ctx->builder,
457 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
458 LLVMConstInt(ctx->ac.i32, 4, false), "");
459 }
460
461 static LLVMValueRef
462 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
463 {
464 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
465 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
466
467 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
468 }
469
470 static LLVMValueRef
471 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
472 {
473 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
474 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildAdd(ctx->builder, patch0_offset,
478 LLVMBuildMul(ctx->builder, patch_stride,
479 rel_patch_id, ""),
480 "");
481 }
482
483 static LLVMValueRef
484 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
485 {
486 LLVMValueRef patch0_patch_data_offset =
487 get_tcs_out_patch0_patch_data_offset(ctx);
488 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
489 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
490
491 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
492 LLVMBuildMul(ctx->builder, patch_stride,
493 rel_patch_id, ""),
494 "");
495 }
496
497 static void
498 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
499 uint32_t indirect_offset)
500 {
501 ud_info->sgpr_idx = *sgpr_idx;
502 ud_info->num_sgprs = num_sgprs;
503 ud_info->indirect = indirect_offset > 0;
504 ud_info->indirect_offset = indirect_offset;
505 *sgpr_idx += num_sgprs;
506 }
507
508 static void
509 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
510 uint8_t num_sgprs)
511 {
512 struct ac_userdata_info *ud_info =
513 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
514 assert(ud_info);
515
516 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
517 }
518
519 static void
520 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
521 uint32_t indirect_offset)
522 {
523 struct ac_userdata_info *ud_info =
524 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
525 assert(ud_info);
526
527 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
528 }
529
530 struct user_sgpr_info {
531 bool need_ring_offsets;
532 uint8_t sgpr_count;
533 bool indirect_all_descriptor_sets;
534 };
535
536 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
537 gl_shader_stage stage)
538 {
539 switch (stage) {
540 case MESA_SHADER_VERTEX:
541 if (ctx->shader_info->info.needs_multiview_view_index ||
542 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
543 return true;
544 break;
545 case MESA_SHADER_TESS_EVAL:
546 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
547 return true;
548 break;
549 case MESA_SHADER_GEOMETRY:
550 case MESA_SHADER_TESS_CTRL:
551 if (ctx->shader_info->info.needs_multiview_view_index)
552 return true;
553 break;
554 default:
555 break;
556 }
557 return false;
558 }
559
560 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
561 gl_shader_stage stage,
562 bool needs_view_index,
563 struct user_sgpr_info *user_sgpr_info)
564 {
565 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
566
567 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
568 if (stage == MESA_SHADER_GEOMETRY ||
569 stage == MESA_SHADER_VERTEX ||
570 stage == MESA_SHADER_TESS_CTRL ||
571 stage == MESA_SHADER_TESS_EVAL ||
572 ctx->is_gs_copy_shader)
573 user_sgpr_info->need_ring_offsets = true;
574
575 if (stage == MESA_SHADER_FRAGMENT &&
576 ctx->shader_info->info.ps.needs_sample_positions)
577 user_sgpr_info->need_ring_offsets = true;
578
579 /* 2 user sgprs will nearly always be allocated for scratch/rings */
580 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
581 user_sgpr_info->sgpr_count += 2;
582 }
583
584 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
585 switch (stage) {
586 case MESA_SHADER_COMPUTE:
587 if (ctx->shader_info->info.cs.uses_grid_size)
588 user_sgpr_info->sgpr_count += 3;
589 break;
590 case MESA_SHADER_FRAGMENT:
591 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
592 break;
593 case MESA_SHADER_VERTEX:
594 if (!ctx->is_gs_copy_shader) {
595 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
596 if (ctx->shader_info->info.vs.needs_draw_id) {
597 user_sgpr_info->sgpr_count += 3;
598 } else {
599 user_sgpr_info->sgpr_count += 2;
600 }
601 }
602 if (ctx->options->key.vs.as_ls)
603 user_sgpr_info->sgpr_count++;
604 break;
605 case MESA_SHADER_TESS_CTRL:
606 user_sgpr_info->sgpr_count += 4;
607 break;
608 case MESA_SHADER_TESS_EVAL:
609 user_sgpr_info->sgpr_count += 1;
610 break;
611 case MESA_SHADER_GEOMETRY:
612 user_sgpr_info->sgpr_count += 2;
613 break;
614 default:
615 break;
616 }
617
618 if (needs_view_index)
619 user_sgpr_info->sgpr_count++;
620
621 if (ctx->shader_info->info.loads_push_constants)
622 user_sgpr_info->sgpr_count += 2;
623
624 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
625 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
626
627 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
628 user_sgpr_info->sgpr_count += 2;
629 user_sgpr_info->indirect_all_descriptor_sets = true;
630 } else {
631 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
632 }
633 }
634
635 static void
636 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
637 gl_shader_stage stage,
638 bool has_previous_stage,
639 gl_shader_stage previous_stage,
640 const struct user_sgpr_info *user_sgpr_info,
641 struct arg_info *args,
642 LLVMValueRef *desc_sets)
643 {
644 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
645 unsigned num_sets = ctx->options->layout ?
646 ctx->options->layout->num_sets : 0;
647 unsigned stage_mask = 1 << stage;
648
649 if (has_previous_stage)
650 stage_mask |= 1 << previous_stage;
651
652 /* 1 for each descriptor set */
653 if (!user_sgpr_info->indirect_all_descriptor_sets) {
654 for (unsigned i = 0; i < num_sets; ++i) {
655 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
656 add_array_arg(args, type,
657 &ctx->descriptor_sets[i]);
658 }
659 }
660 } else {
661 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
662 }
663
664 if (ctx->shader_info->info.loads_push_constants) {
665 /* 1 for push constants and dynamic descriptors */
666 add_array_arg(args, type, &ctx->push_constants);
667 }
668 }
669
670 static void
671 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
672 gl_shader_stage stage,
673 bool has_previous_stage,
674 gl_shader_stage previous_stage,
675 struct arg_info *args)
676 {
677 if (!ctx->is_gs_copy_shader &&
678 (stage == MESA_SHADER_VERTEX ||
679 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
680 if (ctx->shader_info->info.vs.has_vertex_buffers) {
681 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
682 &ctx->vertex_buffers);
683 }
684 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
685 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
686 if (ctx->shader_info->info.vs.needs_draw_id) {
687 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
688 }
689 }
690 }
691
692 static void
693 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
694 {
695 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
696 if (!ctx->is_gs_copy_shader) {
697 if (ctx->options->key.vs.as_ls) {
698 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
699 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
700 } else {
701 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
702 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
703 }
704 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
705 }
706 }
707
708 static void
709 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
710 {
711 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
712 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
713 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
714 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
715 }
716
717 static void
718 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
719 bool has_previous_stage, gl_shader_stage previous_stage,
720 const struct user_sgpr_info *user_sgpr_info,
721 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
722 {
723 unsigned num_sets = ctx->options->layout ?
724 ctx->options->layout->num_sets : 0;
725 unsigned stage_mask = 1 << stage;
726
727 if (has_previous_stage)
728 stage_mask |= 1 << previous_stage;
729
730 if (!user_sgpr_info->indirect_all_descriptor_sets) {
731 for (unsigned i = 0; i < num_sets; ++i) {
732 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
733 set_loc_desc(ctx, i, user_sgpr_idx, 0);
734 } else
735 ctx->descriptor_sets[i] = NULL;
736 }
737 } else {
738 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
739 user_sgpr_idx, 2);
740
741 for (unsigned i = 0; i < num_sets; ++i) {
742 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
743 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
744 ctx->descriptor_sets[i] =
745 ac_build_load_to_sgpr(&ctx->ac,
746 desc_sets,
747 LLVMConstInt(ctx->ac.i32, i, false));
748
749 } else
750 ctx->descriptor_sets[i] = NULL;
751 }
752 ctx->shader_info->need_indirect_descriptor_sets = true;
753 }
754
755 if (ctx->shader_info->info.loads_push_constants) {
756 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
757 }
758 }
759
760 static void
761 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
762 gl_shader_stage stage, bool has_previous_stage,
763 gl_shader_stage previous_stage,
764 uint8_t *user_sgpr_idx)
765 {
766 if (!ctx->is_gs_copy_shader &&
767 (stage == MESA_SHADER_VERTEX ||
768 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
769 if (ctx->shader_info->info.vs.has_vertex_buffers) {
770 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
771 user_sgpr_idx, 2);
772 }
773
774 unsigned vs_num = 2;
775 if (ctx->shader_info->info.vs.needs_draw_id)
776 vs_num++;
777
778 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
779 user_sgpr_idx, vs_num);
780 }
781 }
782
783 static void create_function(struct nir_to_llvm_context *ctx,
784 gl_shader_stage stage,
785 bool has_previous_stage,
786 gl_shader_stage previous_stage)
787 {
788 uint8_t user_sgpr_idx;
789 struct user_sgpr_info user_sgpr_info;
790 struct arg_info args = {};
791 LLVMValueRef desc_sets;
792 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
793 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
794
795 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
796 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
797 &ctx->ring_offsets);
798 }
799
800 switch (stage) {
801 case MESA_SHADER_COMPUTE:
802 declare_global_input_sgprs(ctx, stage, has_previous_stage,
803 previous_stage, &user_sgpr_info,
804 &args, &desc_sets);
805
806 if (ctx->shader_info->info.cs.uses_grid_size) {
807 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
808 &ctx->num_work_groups);
809 }
810
811 for (int i = 0; i < 3; i++) {
812 ctx->workgroup_ids[i] = NULL;
813 if (ctx->shader_info->info.cs.uses_block_id[i]) {
814 add_arg(&args, ARG_SGPR, ctx->ac.i32,
815 &ctx->workgroup_ids[i]);
816 }
817 }
818
819 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
820 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
821 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
822 &ctx->local_invocation_ids);
823 break;
824 case MESA_SHADER_VERTEX:
825 declare_global_input_sgprs(ctx, stage, has_previous_stage,
826 previous_stage, &user_sgpr_info,
827 &args, &desc_sets);
828 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
829 previous_stage, &args);
830
831 if (needs_view_index)
832 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
833 if (ctx->options->key.vs.as_es)
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->es2gs_offset);
836 else if (ctx->options->key.vs.as_ls)
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->ls_out_layout);
839
840 declare_vs_input_vgprs(ctx, &args);
841 break;
842 case MESA_SHADER_TESS_CTRL:
843 if (has_previous_stage) {
844 // First 6 system regs
845 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->merged_wave_info);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tess_factor_offset);
850
851 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
852 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
853 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
854
855 declare_global_input_sgprs(ctx, stage,
856 has_previous_stage,
857 previous_stage,
858 &user_sgpr_info, &args,
859 &desc_sets);
860 declare_vs_specific_input_sgprs(ctx, stage,
861 has_previous_stage,
862 previous_stage, &args);
863
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->ls_out_layout);
866
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_offchip_layout);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_offsets);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_out_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_in_layout);
875 if (needs_view_index)
876 add_arg(&args, ARG_SGPR, ctx->ac.i32,
877 &ctx->view_index);
878
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_patch_id);
881 add_arg(&args, ARG_VGPR, ctx->ac.i32,
882 &ctx->abi.tcs_rel_ids);
883
884 declare_vs_input_vgprs(ctx, &args);
885 } else {
886 declare_global_input_sgprs(ctx, stage,
887 has_previous_stage,
888 previous_stage,
889 &user_sgpr_info, &args,
890 &desc_sets);
891
892 add_arg(&args, ARG_SGPR, ctx->ac.i32,
893 &ctx->tcs_offchip_layout);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32,
895 &ctx->tcs_out_offsets);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->tcs_out_layout);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->tcs_in_layout);
900 if (needs_view_index)
901 add_arg(&args, ARG_SGPR, ctx->ac.i32,
902 &ctx->view_index);
903
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
905 add_arg(&args, ARG_SGPR, ctx->ac.i32,
906 &ctx->tess_factor_offset);
907 add_arg(&args, ARG_VGPR, ctx->ac.i32,
908 &ctx->abi.tcs_patch_id);
909 add_arg(&args, ARG_VGPR, ctx->ac.i32,
910 &ctx->abi.tcs_rel_ids);
911 }
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 declare_global_input_sgprs(ctx, stage, has_previous_stage,
915 previous_stage, &user_sgpr_info,
916 &args, &desc_sets);
917
918 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
919 if (needs_view_index)
920 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
921
922 if (ctx->options->key.tes.as_es) {
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
924 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
925 add_arg(&args, ARG_SGPR, ctx->ac.i32,
926 &ctx->es2gs_offset);
927 } else {
928 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
929 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
930 }
931 declare_tes_input_vgprs(ctx, &args);
932 break;
933 case MESA_SHADER_GEOMETRY:
934 if (has_previous_stage) {
935 // First 6 system regs
936 add_arg(&args, ARG_SGPR, ctx->ac.i32,
937 &ctx->gs2vs_offset);
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->merged_wave_info);
940 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
941
942 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
943 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
944 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
945
946 declare_global_input_sgprs(ctx, stage,
947 has_previous_stage,
948 previous_stage,
949 &user_sgpr_info, &args,
950 &desc_sets);
951
952 if (previous_stage == MESA_SHADER_TESS_EVAL) {
953 add_arg(&args, ARG_SGPR, ctx->ac.i32,
954 &ctx->tcs_offchip_layout);
955 } else {
956 declare_vs_specific_input_sgprs(ctx, stage,
957 has_previous_stage,
958 previous_stage,
959 &args);
960 }
961
962 add_arg(&args, ARG_SGPR, ctx->ac.i32,
963 &ctx->gsvs_ring_stride);
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_num_entries);
966 if (needs_view_index)
967 add_arg(&args, ARG_SGPR, ctx->ac.i32,
968 &ctx->view_index);
969
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->gs_vtx_offset[0]);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->gs_vtx_offset[2]);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->abi.gs_prim_id);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->abi.gs_invocation_id);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[4]);
980
981 if (previous_stage == MESA_SHADER_VERTEX) {
982 declare_vs_input_vgprs(ctx, &args);
983 } else {
984 declare_tes_input_vgprs(ctx, &args);
985 }
986 } else {
987 declare_global_input_sgprs(ctx, stage,
988 has_previous_stage,
989 previous_stage,
990 &user_sgpr_info, &args,
991 &desc_sets);
992
993 add_arg(&args, ARG_SGPR, ctx->ac.i32,
994 &ctx->gsvs_ring_stride);
995 add_arg(&args, ARG_SGPR, ctx->ac.i32,
996 &ctx->gsvs_num_entries);
997 if (needs_view_index)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->view_index);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1003 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1004 &ctx->gs_vtx_offset[0]);
1005 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1006 &ctx->gs_vtx_offset[1]);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1008 &ctx->abi.gs_prim_id);
1009 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1010 &ctx->gs_vtx_offset[2]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1012 &ctx->gs_vtx_offset[3]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1014 &ctx->gs_vtx_offset[4]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1016 &ctx->gs_vtx_offset[5]);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1018 &ctx->abi.gs_invocation_id);
1019 }
1020 break;
1021 case MESA_SHADER_FRAGMENT:
1022 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1023 previous_stage, &user_sgpr_info,
1024 &args, &desc_sets);
1025
1026 if (ctx->shader_info->info.ps.needs_sample_positions)
1027 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1028 &ctx->sample_pos_offset);
1029
1030 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1031 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1032 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1033 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1034 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1035 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1036 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1037 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1038 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1039 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1040 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1041 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1042 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1043 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1044 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1045 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1046 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1047 break;
1048 default:
1049 unreachable("Shader stage not implemented");
1050 }
1051
1052 ctx->main_function = create_llvm_function(
1053 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1054 ctx->max_workgroup_size,
1055 ctx->options->unsafe_math);
1056 set_llvm_calling_convention(ctx->main_function, stage);
1057
1058
1059 ctx->shader_info->num_input_vgprs = 0;
1060 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1061
1062 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1063
1064 if (ctx->stage != MESA_SHADER_FRAGMENT)
1065 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1066
1067 assign_arguments(ctx->main_function, &args);
1068
1069 user_sgpr_idx = 0;
1070
1071 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1072 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1073 &user_sgpr_idx, 2);
1074 if (ctx->options->supports_spill) {
1075 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1076 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1077 NULL, 0, AC_FUNC_ATTR_READNONE);
1078 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1079 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1080 }
1081 }
1082
1083 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1084 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1085 if (has_previous_stage)
1086 user_sgpr_idx = 0;
1087
1088 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1089 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1090
1091 switch (stage) {
1092 case MESA_SHADER_COMPUTE:
1093 if (ctx->shader_info->info.cs.uses_grid_size) {
1094 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1095 &user_sgpr_idx, 3);
1096 }
1097 break;
1098 case MESA_SHADER_VERTEX:
1099 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1100 previous_stage, &user_sgpr_idx);
1101 if (ctx->view_index)
1102 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1103 if (ctx->options->key.vs.as_ls) {
1104 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1105 &user_sgpr_idx, 1);
1106 }
1107 if (ctx->options->key.vs.as_ls)
1108 ac_declare_lds_as_pointer(&ctx->ac);
1109 break;
1110 case MESA_SHADER_TESS_CTRL:
1111 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1112 previous_stage, &user_sgpr_idx);
1113 if (has_previous_stage)
1114 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1115 &user_sgpr_idx, 1);
1116 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1117 if (ctx->view_index)
1118 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1119 ac_declare_lds_as_pointer(&ctx->ac);
1120 break;
1121 case MESA_SHADER_TESS_EVAL:
1122 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1123 if (ctx->view_index)
1124 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1125 break;
1126 case MESA_SHADER_GEOMETRY:
1127 if (has_previous_stage) {
1128 if (previous_stage == MESA_SHADER_VERTEX)
1129 set_vs_specific_input_locs(ctx, stage,
1130 has_previous_stage,
1131 previous_stage,
1132 &user_sgpr_idx);
1133 else
1134 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1135 &user_sgpr_idx, 1);
1136 }
1137 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1138 &user_sgpr_idx, 2);
1139 if (ctx->view_index)
1140 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1141 if (has_previous_stage)
1142 ac_declare_lds_as_pointer(&ctx->ac);
1143 break;
1144 case MESA_SHADER_FRAGMENT:
1145 if (ctx->shader_info->info.ps.needs_sample_positions) {
1146 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1147 &user_sgpr_idx, 1);
1148 }
1149 break;
1150 default:
1151 unreachable("Shader stage not implemented");
1152 }
1153
1154 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1155 }
1156
1157 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1158 LLVMValueRef value, unsigned count)
1159 {
1160 unsigned num_components = ac_get_llvm_num_components(value);
1161 if (count == num_components)
1162 return value;
1163
1164 LLVMValueRef masks[] = {
1165 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1166 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1167
1168 if (count == 1)
1169 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1170 "");
1171
1172 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1173 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1174 }
1175
1176 static void
1177 build_store_values_extended(struct ac_llvm_context *ac,
1178 LLVMValueRef *values,
1179 unsigned value_count,
1180 unsigned value_stride,
1181 LLVMValueRef vec)
1182 {
1183 LLVMBuilderRef builder = ac->builder;
1184 unsigned i;
1185
1186 for (i = 0; i < value_count; i++) {
1187 LLVMValueRef ptr = values[i * value_stride];
1188 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1189 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1190 LLVMBuildStore(builder, value, ptr);
1191 }
1192 }
1193
1194 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1195 const nir_ssa_def *def)
1196 {
1197 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1198 if (def->num_components > 1) {
1199 type = LLVMVectorType(type, def->num_components);
1200 }
1201 return type;
1202 }
1203
1204 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1205 {
1206 assert(src.is_ssa);
1207 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1208 return (LLVMValueRef)entry->data;
1209 }
1210
1211
1212 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1213 const struct nir_block *b)
1214 {
1215 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1216 return (LLVMBasicBlockRef)entry->data;
1217 }
1218
1219 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1220 nir_alu_src src,
1221 unsigned num_components)
1222 {
1223 LLVMValueRef value = get_src(ctx, src.src);
1224 bool need_swizzle = false;
1225
1226 assert(value);
1227 LLVMTypeRef type = LLVMTypeOf(value);
1228 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1229 ? LLVMGetVectorSize(type)
1230 : 1;
1231
1232 for (unsigned i = 0; i < num_components; ++i) {
1233 assert(src.swizzle[i] < src_components);
1234 if (src.swizzle[i] != i)
1235 need_swizzle = true;
1236 }
1237
1238 if (need_swizzle || num_components != src_components) {
1239 LLVMValueRef masks[] = {
1240 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1241 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1242 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1243 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1244
1245 if (src_components > 1 && num_components == 1) {
1246 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1247 masks[0], "");
1248 } else if (src_components == 1 && num_components > 1) {
1249 LLVMValueRef values[] = {value, value, value, value};
1250 value = ac_build_gather_values(&ctx->ac, values, num_components);
1251 } else {
1252 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1253 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1254 swizzle, "");
1255 }
1256 }
1257 assert(!src.negate);
1258 assert(!src.abs);
1259 return value;
1260 }
1261
1262 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1263 LLVMIntPredicate pred, LLVMValueRef src0,
1264 LLVMValueRef src1)
1265 {
1266 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1267 return LLVMBuildSelect(ctx->builder, result,
1268 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1269 ctx->i32_0, "");
1270 }
1271
1272 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1273 LLVMRealPredicate pred, LLVMValueRef src0,
1274 LLVMValueRef src1)
1275 {
1276 LLVMValueRef result;
1277 src0 = ac_to_float(ctx, src0);
1278 src1 = ac_to_float(ctx, src1);
1279 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1280 return LLVMBuildSelect(ctx->builder, result,
1281 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1282 ctx->i32_0, "");
1283 }
1284
1285 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1286 const char *intrin,
1287 LLVMTypeRef result_type,
1288 LLVMValueRef src0)
1289 {
1290 char name[64];
1291 LLVMValueRef params[] = {
1292 ac_to_float(ctx, src0),
1293 };
1294
1295 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1296 get_elem_bits(ctx, result_type));
1297 assert(length < sizeof(name));
1298 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1299 }
1300
1301 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1302 const char *intrin,
1303 LLVMTypeRef result_type,
1304 LLVMValueRef src0, LLVMValueRef src1)
1305 {
1306 char name[64];
1307 LLVMValueRef params[] = {
1308 ac_to_float(ctx, src0),
1309 ac_to_float(ctx, src1),
1310 };
1311
1312 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1313 get_elem_bits(ctx, result_type));
1314 assert(length < sizeof(name));
1315 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1316 }
1317
1318 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1319 const char *intrin,
1320 LLVMTypeRef result_type,
1321 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1322 {
1323 char name[64];
1324 LLVMValueRef params[] = {
1325 ac_to_float(ctx, src0),
1326 ac_to_float(ctx, src1),
1327 ac_to_float(ctx, src2),
1328 };
1329
1330 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1331 get_elem_bits(ctx, result_type));
1332 assert(length < sizeof(name));
1333 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1334 }
1335
1336 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1337 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1338 {
1339 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1340 ctx->i32_0, "");
1341 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1342 }
1343
1344 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1345 LLVMIntPredicate pred,
1346 LLVMValueRef src0, LLVMValueRef src1)
1347 {
1348 return LLVMBuildSelect(ctx->builder,
1349 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1350 src0,
1351 src1, "");
1352
1353 }
1354 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1355 LLVMValueRef src0)
1356 {
1357 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1358 LLVMBuildNeg(ctx->builder, src0, ""));
1359 }
1360
1361 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1362 LLVMValueRef src0,
1363 unsigned bitsize)
1364 {
1365 LLVMValueRef cmp, val, zero, one;
1366 LLVMTypeRef type;
1367
1368 if (bitsize == 32) {
1369 type = ctx->f32;
1370 zero = ctx->f32_0;
1371 one = ctx->f32_1;
1372 } else {
1373 type = ctx->f64;
1374 zero = ctx->f64_0;
1375 one = ctx->f64_1;
1376 }
1377
1378 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1379 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1380 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1381 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1382 return val;
1383 }
1384
1385 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1386 LLVMValueRef src0, unsigned bitsize)
1387 {
1388 LLVMValueRef cmp, val, zero, one;
1389 LLVMTypeRef type;
1390
1391 if (bitsize == 32) {
1392 type = ctx->i32;
1393 zero = ctx->i32_0;
1394 one = ctx->i32_1;
1395 } else {
1396 type = ctx->i64;
1397 zero = ctx->i64_0;
1398 one = ctx->i64_1;
1399 }
1400
1401 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1402 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1403 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1404 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1405 return val;
1406 }
1407
1408 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1409 LLVMValueRef src0)
1410 {
1411 const char *intr = "llvm.floor.f32";
1412 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1413 LLVMValueRef params[] = {
1414 fsrc0,
1415 };
1416 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1417 ctx->f32, params, 1,
1418 AC_FUNC_ATTR_READNONE);
1419 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1420 }
1421
1422 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1423 const char *intrin,
1424 LLVMValueRef src0, LLVMValueRef src1)
1425 {
1426 LLVMTypeRef ret_type;
1427 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1428 LLVMValueRef res;
1429 LLVMValueRef params[] = { src0, src1 };
1430 ret_type = LLVMStructTypeInContext(ctx->context, types,
1431 2, true);
1432
1433 res = ac_build_intrinsic(ctx, intrin, ret_type,
1434 params, 2, AC_FUNC_ATTR_READNONE);
1435
1436 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1437 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1438 return res;
1439 }
1440
1441 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1442 LLVMValueRef src0)
1443 {
1444 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1445 }
1446
1447 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1448 LLVMValueRef src0)
1449 {
1450 src0 = ac_to_float(ctx, src0);
1451 return LLVMBuildSExt(ctx->builder,
1452 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1453 ctx->i32, "");
1454 }
1455
1456 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1457 LLVMValueRef src0,
1458 unsigned bitsize)
1459 {
1460 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1461
1462 if (bitsize == 32)
1463 return result;
1464
1465 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1466 }
1467
1468 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1469 LLVMValueRef src0)
1470 {
1471 return LLVMBuildSExt(ctx->builder,
1472 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1473 ctx->i32, "");
1474 }
1475
1476 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1477 LLVMValueRef src0)
1478 {
1479 LLVMValueRef result;
1480 LLVMValueRef cond = NULL;
1481
1482 src0 = ac_to_float(&ctx->ac, src0);
1483 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1484
1485 if (ctx->options->chip_class >= VI) {
1486 LLVMValueRef args[2];
1487 /* Check if the result is a denormal - and flush to 0 if so. */
1488 args[0] = result;
1489 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1490 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1491 }
1492
1493 /* need to convert back up to f32 */
1494 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1495
1496 if (ctx->options->chip_class >= VI)
1497 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1498 else {
1499 /* for SI/CIK */
1500 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1501 * so compare the result and flush to 0 if it's smaller.
1502 */
1503 LLVMValueRef temp, cond2;
1504 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1505 ctx->ac.f32, result);
1506 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1507 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1508 temp, "");
1509 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1510 temp, ctx->ac.f32_0, "");
1511 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1512 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1513 }
1514 return result;
1515 }
1516
1517 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1518 LLVMValueRef src0, LLVMValueRef src1)
1519 {
1520 LLVMValueRef dst64, result;
1521 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1522 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1523
1524 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1525 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1526 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1527 return result;
1528 }
1529
1530 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1531 LLVMValueRef src0, LLVMValueRef src1)
1532 {
1533 LLVMValueRef dst64, result;
1534 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1535 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1536
1537 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1538 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1539 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1540 return result;
1541 }
1542
1543 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1544 bool is_signed,
1545 const LLVMValueRef srcs[3])
1546 {
1547 LLVMValueRef result;
1548 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1549
1550 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1551 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1552 return result;
1553 }
1554
1555 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1556 LLVMValueRef src0, LLVMValueRef src1,
1557 LLVMValueRef src2, LLVMValueRef src3)
1558 {
1559 LLVMValueRef bfi_args[3], result;
1560
1561 bfi_args[0] = LLVMBuildShl(ctx->builder,
1562 LLVMBuildSub(ctx->builder,
1563 LLVMBuildShl(ctx->builder,
1564 ctx->i32_1,
1565 src3, ""),
1566 ctx->i32_1, ""),
1567 src2, "");
1568 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1569 bfi_args[2] = src0;
1570
1571 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1572
1573 /* Calculate:
1574 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1575 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1576 */
1577 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1578 LLVMBuildAnd(ctx->builder, bfi_args[0],
1579 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1580
1581 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1582 return result;
1583 }
1584
1585 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1586 LLVMValueRef src0)
1587 {
1588 LLVMValueRef comp[2];
1589
1590 src0 = ac_to_float(ctx, src0);
1591 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1592 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1593
1594 return ac_build_cvt_pkrtz_f16(ctx, comp);
1595 }
1596
1597 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1598 LLVMValueRef src0)
1599 {
1600 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1601 LLVMValueRef temps[2], result, val;
1602 int i;
1603
1604 for (i = 0; i < 2; i++) {
1605 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1606 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1607 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1608 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1609 }
1610
1611 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1612 ctx->i32_0, "");
1613 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1614 ctx->i32_1, "");
1615 return result;
1616 }
1617
1618 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1619 nir_op op,
1620 LLVMValueRef src0)
1621 {
1622 unsigned mask;
1623 int idx;
1624 LLVMValueRef result;
1625
1626 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1627 mask = AC_TID_MASK_LEFT;
1628 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1629 mask = AC_TID_MASK_TOP;
1630 else
1631 mask = AC_TID_MASK_TOP_LEFT;
1632
1633 /* for DDX we want to next X pixel, DDY next Y pixel. */
1634 if (op == nir_op_fddx_fine ||
1635 op == nir_op_fddx_coarse ||
1636 op == nir_op_fddx)
1637 idx = 1;
1638 else
1639 idx = 2;
1640
1641 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1642 return result;
1643 }
1644
1645 /*
1646 * this takes an I,J coordinate pair,
1647 * and works out the X and Y derivatives.
1648 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1649 */
1650 static LLVMValueRef emit_ddxy_interp(
1651 struct ac_nir_context *ctx,
1652 LLVMValueRef interp_ij)
1653 {
1654 LLVMValueRef result[4], a;
1655 unsigned i;
1656
1657 for (i = 0; i < 2; i++) {
1658 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1659 LLVMConstInt(ctx->ac.i32, i, false), "");
1660 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1661 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1662 }
1663 return ac_build_gather_values(&ctx->ac, result, 4);
1664 }
1665
1666 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1667 {
1668 LLVMValueRef src[4], result = NULL;
1669 unsigned num_components = instr->dest.dest.ssa.num_components;
1670 unsigned src_components;
1671 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1672
1673 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1674 switch (instr->op) {
1675 case nir_op_vec2:
1676 case nir_op_vec3:
1677 case nir_op_vec4:
1678 src_components = 1;
1679 break;
1680 case nir_op_pack_half_2x16:
1681 src_components = 2;
1682 break;
1683 case nir_op_unpack_half_2x16:
1684 src_components = 1;
1685 break;
1686 default:
1687 src_components = num_components;
1688 break;
1689 }
1690 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1691 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1692
1693 switch (instr->op) {
1694 case nir_op_fmov:
1695 case nir_op_imov:
1696 result = src[0];
1697 break;
1698 case nir_op_fneg:
1699 src[0] = ac_to_float(&ctx->ac, src[0]);
1700 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1701 break;
1702 case nir_op_ineg:
1703 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1704 break;
1705 case nir_op_inot:
1706 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1707 break;
1708 case nir_op_iadd:
1709 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_fadd:
1712 src[0] = ac_to_float(&ctx->ac, src[0]);
1713 src[1] = ac_to_float(&ctx->ac, src[1]);
1714 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_fsub:
1717 src[0] = ac_to_float(&ctx->ac, src[0]);
1718 src[1] = ac_to_float(&ctx->ac, src[1]);
1719 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1720 break;
1721 case nir_op_isub:
1722 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_imul:
1725 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_imod:
1728 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1729 break;
1730 case nir_op_umod:
1731 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1732 break;
1733 case nir_op_fmod:
1734 src[0] = ac_to_float(&ctx->ac, src[0]);
1735 src[1] = ac_to_float(&ctx->ac, src[1]);
1736 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1737 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1738 ac_to_float_type(&ctx->ac, def_type), result);
1739 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1740 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1741 break;
1742 case nir_op_frem:
1743 src[0] = ac_to_float(&ctx->ac, src[0]);
1744 src[1] = ac_to_float(&ctx->ac, src[1]);
1745 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1746 break;
1747 case nir_op_irem:
1748 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1749 break;
1750 case nir_op_idiv:
1751 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_udiv:
1754 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1755 break;
1756 case nir_op_fmul:
1757 src[0] = ac_to_float(&ctx->ac, src[0]);
1758 src[1] = ac_to_float(&ctx->ac, src[1]);
1759 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_fdiv:
1762 src[0] = ac_to_float(&ctx->ac, src[0]);
1763 src[1] = ac_to_float(&ctx->ac, src[1]);
1764 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1765 break;
1766 case nir_op_frcp:
1767 src[0] = ac_to_float(&ctx->ac, src[0]);
1768 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1769 src[0]);
1770 break;
1771 case nir_op_iand:
1772 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1773 break;
1774 case nir_op_ior:
1775 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1776 break;
1777 case nir_op_ixor:
1778 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1779 break;
1780 case nir_op_ishl:
1781 result = LLVMBuildShl(ctx->ac.builder, src[0],
1782 LLVMBuildZExt(ctx->ac.builder, src[1],
1783 LLVMTypeOf(src[0]), ""),
1784 "");
1785 break;
1786 case nir_op_ishr:
1787 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1788 LLVMBuildZExt(ctx->ac.builder, src[1],
1789 LLVMTypeOf(src[0]), ""),
1790 "");
1791 break;
1792 case nir_op_ushr:
1793 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1794 LLVMBuildZExt(ctx->ac.builder, src[1],
1795 LLVMTypeOf(src[0]), ""),
1796 "");
1797 break;
1798 case nir_op_ilt:
1799 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1800 break;
1801 case nir_op_ine:
1802 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1803 break;
1804 case nir_op_ieq:
1805 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1806 break;
1807 case nir_op_ige:
1808 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1809 break;
1810 case nir_op_ult:
1811 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1812 break;
1813 case nir_op_uge:
1814 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1815 break;
1816 case nir_op_feq:
1817 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1818 break;
1819 case nir_op_fne:
1820 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1821 break;
1822 case nir_op_flt:
1823 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1824 break;
1825 case nir_op_fge:
1826 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1827 break;
1828 case nir_op_fabs:
1829 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1830 ac_to_float_type(&ctx->ac, def_type), src[0]);
1831 break;
1832 case nir_op_iabs:
1833 result = emit_iabs(&ctx->ac, src[0]);
1834 break;
1835 case nir_op_imax:
1836 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1837 break;
1838 case nir_op_imin:
1839 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1840 break;
1841 case nir_op_umax:
1842 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1843 break;
1844 case nir_op_umin:
1845 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1846 break;
1847 case nir_op_isign:
1848 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1849 break;
1850 case nir_op_fsign:
1851 src[0] = ac_to_float(&ctx->ac, src[0]);
1852 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1853 break;
1854 case nir_op_ffloor:
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1856 ac_to_float_type(&ctx->ac, def_type), src[0]);
1857 break;
1858 case nir_op_ftrunc:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 break;
1862 case nir_op_fceil:
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1864 ac_to_float_type(&ctx->ac, def_type), src[0]);
1865 break;
1866 case nir_op_fround_even:
1867 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1868 ac_to_float_type(&ctx->ac, def_type),src[0]);
1869 break;
1870 case nir_op_ffract:
1871 result = emit_ffract(&ctx->ac, src[0]);
1872 break;
1873 case nir_op_fsin:
1874 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1875 ac_to_float_type(&ctx->ac, def_type), src[0]);
1876 break;
1877 case nir_op_fcos:
1878 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1879 ac_to_float_type(&ctx->ac, def_type), src[0]);
1880 break;
1881 case nir_op_fsqrt:
1882 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1883 ac_to_float_type(&ctx->ac, def_type), src[0]);
1884 break;
1885 case nir_op_fexp2:
1886 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1887 ac_to_float_type(&ctx->ac, def_type), src[0]);
1888 break;
1889 case nir_op_flog2:
1890 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1891 ac_to_float_type(&ctx->ac, def_type), src[0]);
1892 break;
1893 case nir_op_frsq:
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1895 ac_to_float_type(&ctx->ac, def_type), src[0]);
1896 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1897 result);
1898 break;
1899 case nir_op_fpow:
1900 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1901 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1902 break;
1903 case nir_op_fmax:
1904 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1905 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1906 if (ctx->ac.chip_class < GFX9 &&
1907 instr->dest.dest.ssa.bit_size == 32) {
1908 /* Only pre-GFX9 chips do not flush denorms. */
1909 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1910 ac_to_float_type(&ctx->ac, def_type),
1911 result);
1912 }
1913 break;
1914 case nir_op_fmin:
1915 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1916 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1917 if (ctx->ac.chip_class < GFX9 &&
1918 instr->dest.dest.ssa.bit_size == 32) {
1919 /* Only pre-GFX9 chips do not flush denorms. */
1920 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1921 ac_to_float_type(&ctx->ac, def_type),
1922 result);
1923 }
1924 break;
1925 case nir_op_ffma:
1926 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1927 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1928 break;
1929 case nir_op_ibitfield_extract:
1930 result = emit_bitfield_extract(&ctx->ac, true, src);
1931 break;
1932 case nir_op_ubitfield_extract:
1933 result = emit_bitfield_extract(&ctx->ac, false, src);
1934 break;
1935 case nir_op_bitfield_insert:
1936 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1937 break;
1938 case nir_op_bitfield_reverse:
1939 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1940 break;
1941 case nir_op_bit_count:
1942 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1943 break;
1944 case nir_op_vec2:
1945 case nir_op_vec3:
1946 case nir_op_vec4:
1947 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1948 src[i] = ac_to_integer(&ctx->ac, src[i]);
1949 result = ac_build_gather_values(&ctx->ac, src, num_components);
1950 break;
1951 case nir_op_f2i32:
1952 case nir_op_f2i64:
1953 src[0] = ac_to_float(&ctx->ac, src[0]);
1954 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1955 break;
1956 case nir_op_f2u32:
1957 case nir_op_f2u64:
1958 src[0] = ac_to_float(&ctx->ac, src[0]);
1959 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1960 break;
1961 case nir_op_i2f32:
1962 case nir_op_i2f64:
1963 src[0] = ac_to_integer(&ctx->ac, src[0]);
1964 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1965 break;
1966 case nir_op_u2f32:
1967 case nir_op_u2f64:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1970 break;
1971 case nir_op_f2f64:
1972 src[0] = ac_to_float(&ctx->ac, src[0]);
1973 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1974 break;
1975 case nir_op_f2f32:
1976 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1977 break;
1978 case nir_op_u2u32:
1979 case nir_op_u2u64:
1980 src[0] = ac_to_integer(&ctx->ac, src[0]);
1981 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1982 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1983 else
1984 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1985 break;
1986 case nir_op_i2i32:
1987 case nir_op_i2i64:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1990 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1991 else
1992 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1993 break;
1994 case nir_op_bcsel:
1995 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1996 break;
1997 case nir_op_find_lsb:
1998 src[0] = ac_to_integer(&ctx->ac, src[0]);
1999 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
2000 break;
2001 case nir_op_ufind_msb:
2002 src[0] = ac_to_integer(&ctx->ac, src[0]);
2003 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
2004 break;
2005 case nir_op_ifind_msb:
2006 src[0] = ac_to_integer(&ctx->ac, src[0]);
2007 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2008 break;
2009 case nir_op_uadd_carry:
2010 src[0] = ac_to_integer(&ctx->ac, src[0]);
2011 src[1] = ac_to_integer(&ctx->ac, src[1]);
2012 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2013 break;
2014 case nir_op_usub_borrow:
2015 src[0] = ac_to_integer(&ctx->ac, src[0]);
2016 src[1] = ac_to_integer(&ctx->ac, src[1]);
2017 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2018 break;
2019 case nir_op_b2f:
2020 result = emit_b2f(&ctx->ac, src[0]);
2021 break;
2022 case nir_op_f2b:
2023 result = emit_f2b(&ctx->ac, src[0]);
2024 break;
2025 case nir_op_b2i:
2026 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2027 break;
2028 case nir_op_i2b:
2029 src[0] = ac_to_integer(&ctx->ac, src[0]);
2030 result = emit_i2b(&ctx->ac, src[0]);
2031 break;
2032 case nir_op_fquantize2f16:
2033 result = emit_f2f16(ctx->nctx, src[0]);
2034 break;
2035 case nir_op_umul_high:
2036 src[0] = ac_to_integer(&ctx->ac, src[0]);
2037 src[1] = ac_to_integer(&ctx->ac, src[1]);
2038 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2039 break;
2040 case nir_op_imul_high:
2041 src[0] = ac_to_integer(&ctx->ac, src[0]);
2042 src[1] = ac_to_integer(&ctx->ac, src[1]);
2043 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2044 break;
2045 case nir_op_pack_half_2x16:
2046 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2047 break;
2048 case nir_op_unpack_half_2x16:
2049 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2050 break;
2051 case nir_op_fddx:
2052 case nir_op_fddy:
2053 case nir_op_fddx_fine:
2054 case nir_op_fddy_fine:
2055 case nir_op_fddx_coarse:
2056 case nir_op_fddy_coarse:
2057 result = emit_ddxy(ctx, instr->op, src[0]);
2058 break;
2059
2060 case nir_op_unpack_64_2x32_split_x: {
2061 assert(instr->src[0].src.ssa->num_components == 1);
2062 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2063 ctx->ac.v2i32,
2064 "");
2065 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2066 ctx->ac.i32_0, "");
2067 break;
2068 }
2069
2070 case nir_op_unpack_64_2x32_split_y: {
2071 assert(instr->src[0].src.ssa->num_components == 1);
2072 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2073 ctx->ac.v2i32,
2074 "");
2075 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2076 ctx->ac.i32_1, "");
2077 break;
2078 }
2079
2080 case nir_op_pack_64_2x32_split: {
2081 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2082 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2083 src[0], ctx->ac.i32_0, "");
2084 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2085 src[1], ctx->ac.i32_1, "");
2086 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2087 break;
2088 }
2089
2090 default:
2091 fprintf(stderr, "Unknown NIR alu instr: ");
2092 nir_print_instr(&instr->instr, stderr);
2093 fprintf(stderr, "\n");
2094 abort();
2095 }
2096
2097 if (result) {
2098 assert(instr->dest.dest.is_ssa);
2099 result = ac_to_integer(&ctx->ac, result);
2100 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2101 result);
2102 }
2103 }
2104
2105 static void visit_load_const(struct ac_nir_context *ctx,
2106 const nir_load_const_instr *instr)
2107 {
2108 LLVMValueRef values[4], value = NULL;
2109 LLVMTypeRef element_type =
2110 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2111
2112 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2113 switch (instr->def.bit_size) {
2114 case 32:
2115 values[i] = LLVMConstInt(element_type,
2116 instr->value.u32[i], false);
2117 break;
2118 case 64:
2119 values[i] = LLVMConstInt(element_type,
2120 instr->value.u64[i], false);
2121 break;
2122 default:
2123 fprintf(stderr,
2124 "unsupported nir load_const bit_size: %d\n",
2125 instr->def.bit_size);
2126 abort();
2127 }
2128 }
2129 if (instr->def.num_components > 1) {
2130 value = LLVMConstVector(values, instr->def.num_components);
2131 } else
2132 value = values[0];
2133
2134 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2135 }
2136
2137 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2138 LLVMTypeRef type)
2139 {
2140 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2141 return LLVMBuildBitCast(ctx->builder, ptr,
2142 LLVMPointerType(type, addr_space), "");
2143 }
2144
2145 static LLVMValueRef
2146 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2147 {
2148 LLVMValueRef size =
2149 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2150 LLVMConstInt(ctx->ac.i32, 2, false), "");
2151
2152 /* VI only */
2153 if (ctx->ac.chip_class == VI && in_elements) {
2154 /* On VI, the descriptor contains the size in bytes,
2155 * but TXQ must return the size in elements.
2156 * The stride is always non-zero for resources using TXQ.
2157 */
2158 LLVMValueRef stride =
2159 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2160 ctx->ac.i32_1, "");
2161 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2162 LLVMConstInt(ctx->ac.i32, 16, false), "");
2163 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2164 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2165
2166 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2167 }
2168 return size;
2169 }
2170
2171 /**
2172 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2173 * intrinsic names).
2174 */
2175 static void build_int_type_name(
2176 LLVMTypeRef type,
2177 char *buf, unsigned bufsize)
2178 {
2179 assert(bufsize >= 6);
2180
2181 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2182 snprintf(buf, bufsize, "v%ui32",
2183 LLVMGetVectorSize(type));
2184 else
2185 strcpy(buf, "i32");
2186 }
2187
2188 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2189 struct ac_image_args *args,
2190 const nir_tex_instr *instr)
2191 {
2192 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2193 LLVMValueRef coord = args->addr;
2194 LLVMValueRef half_texel[2];
2195 LLVMValueRef compare_cube_wa = NULL;
2196 LLVMValueRef result;
2197 int c;
2198 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2199
2200 //TODO Rect
2201 {
2202 struct ac_image_args txq_args = { 0 };
2203
2204 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2205 txq_args.opcode = ac_image_get_resinfo;
2206 txq_args.dmask = 0xf;
2207 txq_args.addr = ctx->i32_0;
2208 txq_args.resource = args->resource;
2209 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2210
2211 for (c = 0; c < 2; c++) {
2212 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2213 LLVMConstInt(ctx->i32, c, false), "");
2214 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2215 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2216 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2217 LLVMConstReal(ctx->f32, -0.5), "");
2218 }
2219 }
2220
2221 LLVMValueRef orig_coords = args->addr;
2222
2223 for (c = 0; c < 2; c++) {
2224 LLVMValueRef tmp;
2225 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2226 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2227 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2228 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2229 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2230 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2231 }
2232
2233
2234 /*
2235 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2236 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2237 * workaround by sampling using a scaled type and converting.
2238 * This is taken from amdgpu-pro shaders.
2239 */
2240 /* NOTE this produces some ugly code compared to amdgpu-pro,
2241 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2242 * and then reads them back. -pro generates two selects,
2243 * one s_cmp for the descriptor rewriting
2244 * one v_cmp for the coordinate and result changes.
2245 */
2246 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2247 LLVMValueRef tmp, tmp2;
2248
2249 /* workaround 8/8/8/8 uint/sint cube gather bug */
2250 /* first detect it then change to a scaled read and f2i */
2251 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2252 tmp2 = tmp;
2253
2254 /* extract the DATA_FORMAT */
2255 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2256 LLVMConstInt(ctx->i32, 6, false), false);
2257
2258 /* is the DATA_FORMAT == 8_8_8_8 */
2259 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2260
2261 if (stype == GLSL_TYPE_UINT)
2262 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2263 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2264 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2265 else
2266 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2267 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2268 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2269
2270 /* replace the NUM FORMAT in the descriptor */
2271 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2272 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2273
2274 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2275
2276 /* don't modify the coordinates for this case */
2277 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2278 }
2279 args->addr = coord;
2280 result = ac_build_image_opcode(ctx, args);
2281
2282 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2283 LLVMValueRef tmp, tmp2;
2284
2285 /* if the cube workaround is in place, f2i the result. */
2286 for (c = 0; c < 4; c++) {
2287 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2288 if (stype == GLSL_TYPE_UINT)
2289 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2290 else
2291 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2292 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2293 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2294 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2295 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2296 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2297 }
2298 }
2299 return result;
2300 }
2301
2302 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2303 const nir_tex_instr *instr,
2304 bool lod_is_zero,
2305 struct ac_image_args *args)
2306 {
2307 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2308 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2309
2310 return ac_build_buffer_load_format(&ctx->ac,
2311 args->resource,
2312 args->addr,
2313 ctx->ac.i32_0,
2314 util_last_bit(mask),
2315 true);
2316 }
2317
2318 args->opcode = ac_image_sample;
2319 args->compare = instr->is_shadow;
2320
2321 switch (instr->op) {
2322 case nir_texop_txf:
2323 case nir_texop_txf_ms:
2324 case nir_texop_samples_identical:
2325 args->opcode = lod_is_zero ||
2326 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2327 ac_image_load : ac_image_load_mip;
2328 args->compare = false;
2329 args->offset = false;
2330 break;
2331 case nir_texop_txb:
2332 args->bias = true;
2333 break;
2334 case nir_texop_txl:
2335 if (lod_is_zero)
2336 args->level_zero = true;
2337 else
2338 args->lod = true;
2339 break;
2340 case nir_texop_txs:
2341 case nir_texop_query_levels:
2342 args->opcode = ac_image_get_resinfo;
2343 break;
2344 case nir_texop_tex:
2345 if (ctx->stage != MESA_SHADER_FRAGMENT)
2346 args->level_zero = true;
2347 break;
2348 case nir_texop_txd:
2349 args->deriv = true;
2350 break;
2351 case nir_texop_tg4:
2352 args->opcode = ac_image_gather4;
2353 args->level_zero = true;
2354 break;
2355 case nir_texop_lod:
2356 args->opcode = ac_image_get_lod;
2357 args->compare = false;
2358 args->offset = false;
2359 break;
2360 default:
2361 break;
2362 }
2363
2364 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2365 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2366 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2367 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2368 }
2369 }
2370 return ac_build_image_opcode(&ctx->ac, args);
2371 }
2372
2373 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2374 nir_intrinsic_instr *instr)
2375 {
2376 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2377 unsigned desc_set = nir_intrinsic_desc_set(instr);
2378 unsigned binding = nir_intrinsic_binding(instr);
2379 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2380 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2381 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2382 unsigned base_offset = layout->binding[binding].offset;
2383 LLVMValueRef offset, stride;
2384
2385 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2386 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2387 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2388 layout->binding[binding].dynamic_offset_offset;
2389 desc_ptr = ctx->push_constants;
2390 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2391 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2392 } else
2393 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2394
2395 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2396 index = LLVMBuildMul(ctx->builder, index, stride, "");
2397 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2398
2399 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2400 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2401 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2402
2403 return desc_ptr;
2404 }
2405
2406 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2407 nir_intrinsic_instr *instr)
2408 {
2409 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2410 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2411
2412 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2413 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2414 return result;
2415 }
2416
2417 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2418 nir_intrinsic_instr *instr)
2419 {
2420 LLVMValueRef ptr, addr;
2421
2422 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2423 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2424
2425 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2426 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2427
2428 return LLVMBuildLoad(ctx->builder, ptr, "");
2429 }
2430
2431 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2432 const nir_intrinsic_instr *instr)
2433 {
2434 LLVMValueRef index = get_src(ctx, instr->src[0]);
2435
2436 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2437 }
2438
2439 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2440 {
2441 uint32_t new_mask = 0;
2442 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2443 if (mask & (1u << i))
2444 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2445 return new_mask;
2446 }
2447
2448 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2449 unsigned start, unsigned count)
2450 {
2451 LLVMTypeRef type = LLVMTypeOf(src);
2452
2453 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2454 assert(start == 0);
2455 assert(count == 1);
2456 return src;
2457 }
2458
2459 unsigned src_elements = LLVMGetVectorSize(type);
2460 assert(start < src_elements);
2461 assert(start + count <= src_elements);
2462
2463 if (start == 0 && count == src_elements)
2464 return src;
2465
2466 if (count == 1)
2467 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2468
2469 assert(count <= 8);
2470 LLVMValueRef indices[8];
2471 for (unsigned i = 0; i < count; ++i)
2472 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2473
2474 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2475 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2476 }
2477
2478 static void visit_store_ssbo(struct ac_nir_context *ctx,
2479 nir_intrinsic_instr *instr)
2480 {
2481 const char *store_name;
2482 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2483 LLVMTypeRef data_type = ctx->ac.f32;
2484 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2485 int components_32bit = elem_size_mult * instr->num_components;
2486 unsigned writemask = nir_intrinsic_write_mask(instr);
2487 LLVMValueRef base_data, base_offset;
2488 LLVMValueRef params[6];
2489
2490 params[1] = ctx->abi->load_ssbo(ctx->abi,
2491 get_src(ctx, instr->src[1]), true);
2492 params[2] = ctx->ac.i32_0; /* vindex */
2493 params[4] = ctx->ac.i1false; /* glc */
2494 params[5] = ctx->ac.i1false; /* slc */
2495
2496 if (components_32bit > 1)
2497 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2498
2499 writemask = widen_mask(writemask, elem_size_mult);
2500
2501 base_data = ac_to_float(&ctx->ac, src_data);
2502 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2503 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2504 data_type, "");
2505 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2506 while (writemask) {
2507 int start, count;
2508 LLVMValueRef data;
2509 LLVMValueRef offset;
2510
2511 u_bit_scan_consecutive_range(&writemask, &start, &count);
2512
2513 /* Due to an LLVM limitation, split 3-element writes
2514 * into a 2-element and a 1-element write. */
2515 if (count == 3) {
2516 writemask |= 1 << (start + 2);
2517 count = 2;
2518 }
2519
2520 if (count > 4) {
2521 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2522 count = 4;
2523 }
2524
2525 if (count == 4) {
2526 store_name = "llvm.amdgcn.buffer.store.v4f32";
2527 } else if (count == 2) {
2528 store_name = "llvm.amdgcn.buffer.store.v2f32";
2529
2530 } else {
2531 assert(count == 1);
2532 store_name = "llvm.amdgcn.buffer.store.f32";
2533 }
2534 data = extract_vector_range(&ctx->ac, base_data, start, count);
2535
2536 offset = base_offset;
2537 if (start != 0) {
2538 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2539 }
2540 params[0] = data;
2541 params[3] = offset;
2542 ac_build_intrinsic(&ctx->ac, store_name,
2543 ctx->ac.voidt, params, 6, 0);
2544 }
2545 }
2546
2547 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2548 const nir_intrinsic_instr *instr)
2549 {
2550 const char *name;
2551 LLVMValueRef params[6];
2552 int arg_count = 0;
2553
2554 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2555 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2556 }
2557 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2558 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2559 get_src(ctx, instr->src[0]),
2560 true);
2561 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2562 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2563 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2564
2565 switch (instr->intrinsic) {
2566 case nir_intrinsic_ssbo_atomic_add:
2567 name = "llvm.amdgcn.buffer.atomic.add";
2568 break;
2569 case nir_intrinsic_ssbo_atomic_imin:
2570 name = "llvm.amdgcn.buffer.atomic.smin";
2571 break;
2572 case nir_intrinsic_ssbo_atomic_umin:
2573 name = "llvm.amdgcn.buffer.atomic.umin";
2574 break;
2575 case nir_intrinsic_ssbo_atomic_imax:
2576 name = "llvm.amdgcn.buffer.atomic.smax";
2577 break;
2578 case nir_intrinsic_ssbo_atomic_umax:
2579 name = "llvm.amdgcn.buffer.atomic.umax";
2580 break;
2581 case nir_intrinsic_ssbo_atomic_and:
2582 name = "llvm.amdgcn.buffer.atomic.and";
2583 break;
2584 case nir_intrinsic_ssbo_atomic_or:
2585 name = "llvm.amdgcn.buffer.atomic.or";
2586 break;
2587 case nir_intrinsic_ssbo_atomic_xor:
2588 name = "llvm.amdgcn.buffer.atomic.xor";
2589 break;
2590 case nir_intrinsic_ssbo_atomic_exchange:
2591 name = "llvm.amdgcn.buffer.atomic.swap";
2592 break;
2593 case nir_intrinsic_ssbo_atomic_comp_swap:
2594 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2595 break;
2596 default:
2597 abort();
2598 }
2599
2600 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2601 }
2602
2603 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2604 const nir_intrinsic_instr *instr)
2605 {
2606 LLVMValueRef results[2];
2607 int load_components;
2608 int num_components = instr->num_components;
2609 if (instr->dest.ssa.bit_size == 64)
2610 num_components *= 2;
2611
2612 for (int i = 0; i < num_components; i += load_components) {
2613 load_components = MIN2(num_components - i, 4);
2614 const char *load_name;
2615 LLVMTypeRef data_type = ctx->ac.f32;
2616 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2617 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2618
2619 if (load_components == 3)
2620 data_type = LLVMVectorType(ctx->ac.f32, 4);
2621 else if (load_components > 1)
2622 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2623
2624 if (load_components >= 3)
2625 load_name = "llvm.amdgcn.buffer.load.v4f32";
2626 else if (load_components == 2)
2627 load_name = "llvm.amdgcn.buffer.load.v2f32";
2628 else if (load_components == 1)
2629 load_name = "llvm.amdgcn.buffer.load.f32";
2630 else
2631 unreachable("unhandled number of components");
2632
2633 LLVMValueRef params[] = {
2634 ctx->abi->load_ssbo(ctx->abi,
2635 get_src(ctx, instr->src[0]),
2636 false),
2637 ctx->ac.i32_0,
2638 offset,
2639 ctx->ac.i1false,
2640 ctx->ac.i1false,
2641 };
2642
2643 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2644 }
2645
2646 assume(results[0]);
2647 LLVMValueRef ret = results[0];
2648 if (num_components > 4 || num_components == 3) {
2649 LLVMValueRef masks[] = {
2650 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2651 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2652 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2653 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2654 };
2655
2656 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2657 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2658 results[num_components > 4 ? 1 : 0], swizzle, "");
2659 }
2660
2661 return LLVMBuildBitCast(ctx->ac.builder, ret,
2662 get_def_type(ctx, &instr->dest.ssa), "");
2663 }
2664
2665 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2666 const nir_intrinsic_instr *instr)
2667 {
2668 LLVMValueRef ret;
2669 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2670 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2671 int num_components = instr->num_components;
2672
2673 if (ctx->abi->load_ubo)
2674 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2675
2676 if (instr->dest.ssa.bit_size == 64)
2677 num_components *= 2;
2678
2679 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2680 NULL, 0, false, false, true, true);
2681 ret = trim_vector(&ctx->ac, ret, num_components);
2682 return LLVMBuildBitCast(ctx->ac.builder, ret,
2683 get_def_type(ctx, &instr->dest.ssa), "");
2684 }
2685
2686 static void
2687 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2688 bool vs_in, unsigned *vertex_index_out,
2689 LLVMValueRef *vertex_index_ref,
2690 unsigned *const_out, LLVMValueRef *indir_out)
2691 {
2692 unsigned const_offset = 0;
2693 nir_deref *tail = &deref->deref;
2694 LLVMValueRef offset = NULL;
2695
2696 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2697 tail = tail->child;
2698 nir_deref_array *deref_array = nir_deref_as_array(tail);
2699 if (vertex_index_out)
2700 *vertex_index_out = deref_array->base_offset;
2701
2702 if (vertex_index_ref) {
2703 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2704 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2705 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2706 }
2707 *vertex_index_ref = vtx;
2708 }
2709 }
2710
2711 if (deref->var->data.compact) {
2712 assert(tail->child->deref_type == nir_deref_type_array);
2713 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2714 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2715 /* We always lower indirect dereferences for "compact" array vars. */
2716 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2717
2718 const_offset = deref_array->base_offset;
2719 goto out;
2720 }
2721
2722 while (tail->child != NULL) {
2723 const struct glsl_type *parent_type = tail->type;
2724 tail = tail->child;
2725
2726 if (tail->deref_type == nir_deref_type_array) {
2727 nir_deref_array *deref_array = nir_deref_as_array(tail);
2728 LLVMValueRef index, stride, local_offset;
2729 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2730
2731 const_offset += size * deref_array->base_offset;
2732 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2733 continue;
2734
2735 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2736 index = get_src(ctx, deref_array->indirect);
2737 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2738 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2739
2740 if (offset)
2741 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2742 else
2743 offset = local_offset;
2744 } else if (tail->deref_type == nir_deref_type_struct) {
2745 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2746
2747 for (unsigned i = 0; i < deref_struct->index; i++) {
2748 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2749 const_offset += glsl_count_attribute_slots(ft, vs_in);
2750 }
2751 } else
2752 unreachable("unsupported deref type");
2753
2754 }
2755 out:
2756 if (const_offset && offset)
2757 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2758 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2759 "");
2760
2761 *const_out = const_offset;
2762 *indir_out = offset;
2763 }
2764
2765
2766 /* The offchip buffer layout for TCS->TES is
2767 *
2768 * - attribute 0 of patch 0 vertex 0
2769 * - attribute 0 of patch 0 vertex 1
2770 * - attribute 0 of patch 0 vertex 2
2771 * ...
2772 * - attribute 0 of patch 1 vertex 0
2773 * - attribute 0 of patch 1 vertex 1
2774 * ...
2775 * - attribute 1 of patch 0 vertex 0
2776 * - attribute 1 of patch 0 vertex 1
2777 * ...
2778 * - per patch attribute 0 of patch 0
2779 * - per patch attribute 0 of patch 1
2780 * ...
2781 *
2782 * Note that every attribute has 4 components.
2783 */
2784 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2785 LLVMValueRef vertex_index,
2786 LLVMValueRef param_index)
2787 {
2788 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2789 LLVMValueRef param_stride, constant16;
2790 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2791
2792 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2793 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2794 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2795 num_patches, "");
2796
2797 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2798 if (vertex_index) {
2799 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2800 vertices_per_patch, "");
2801
2802 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2803 vertex_index, "");
2804
2805 param_stride = total_vertices;
2806 } else {
2807 base_addr = rel_patch_id;
2808 param_stride = num_patches;
2809 }
2810
2811 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2812 LLVMBuildMul(ctx->builder, param_index,
2813 param_stride, ""), "");
2814
2815 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2816
2817 if (!vertex_index) {
2818 LLVMValueRef patch_data_offset =
2819 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2820
2821 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2822 patch_data_offset, "");
2823 }
2824 return base_addr;
2825 }
2826
2827 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2828 unsigned param,
2829 unsigned const_index,
2830 bool is_compact,
2831 LLVMValueRef vertex_index,
2832 LLVMValueRef indir_index)
2833 {
2834 LLVMValueRef param_index;
2835
2836 if (indir_index)
2837 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2838 indir_index, "");
2839 else {
2840 if (const_index && !is_compact)
2841 param += const_index;
2842 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2843 }
2844 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2845 }
2846
2847 static void
2848 mark_tess_output(struct nir_to_llvm_context *ctx,
2849 bool is_patch, uint32_t param)
2850
2851 {
2852 if (is_patch) {
2853 ctx->tess_patch_outputs_written |= (1ull << param);
2854 } else
2855 ctx->tess_outputs_written |= (1ull << param);
2856 }
2857
2858 static LLVMValueRef
2859 get_dw_address(struct nir_to_llvm_context *ctx,
2860 LLVMValueRef dw_addr,
2861 unsigned param,
2862 unsigned const_index,
2863 bool compact_const_index,
2864 LLVMValueRef vertex_index,
2865 LLVMValueRef stride,
2866 LLVMValueRef indir_index)
2867
2868 {
2869
2870 if (vertex_index) {
2871 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2872 LLVMBuildMul(ctx->builder,
2873 vertex_index,
2874 stride, ""), "");
2875 }
2876
2877 if (indir_index)
2878 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2879 LLVMBuildMul(ctx->builder, indir_index,
2880 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2881 else if (const_index && !compact_const_index)
2882 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2883 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2884
2885 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2886 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2887
2888 if (const_index && compact_const_index)
2889 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2890 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2891 return dw_addr;
2892 }
2893
2894 static LLVMValueRef
2895 load_tcs_varyings(struct ac_shader_abi *abi,
2896 LLVMValueRef vertex_index,
2897 LLVMValueRef indir_index,
2898 unsigned const_index,
2899 unsigned location,
2900 unsigned driver_location,
2901 unsigned component,
2902 unsigned num_components,
2903 bool is_patch,
2904 bool is_compact,
2905 bool load_input)
2906 {
2907 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2908 LLVMValueRef dw_addr, stride;
2909 LLVMValueRef value[4], result;
2910 unsigned param = shader_io_get_unique_index(location);
2911
2912 if (load_input) {
2913 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2914 dw_addr = get_tcs_in_current_patch_offset(ctx);
2915 } else {
2916 if (!is_patch) {
2917 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2918 dw_addr = get_tcs_out_current_patch_offset(ctx);
2919 } else {
2920 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2921 stride = NULL;
2922 }
2923 }
2924
2925 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2926 indir_index);
2927
2928 for (unsigned i = 0; i < num_components + component; i++) {
2929 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2930 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2931 ctx->ac.i32_1, "");
2932 }
2933 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2934 return result;
2935 }
2936
2937 static void
2938 store_tcs_output(struct ac_shader_abi *abi,
2939 LLVMValueRef vertex_index,
2940 LLVMValueRef param_index,
2941 unsigned const_index,
2942 unsigned location,
2943 unsigned driver_location,
2944 LLVMValueRef src,
2945 unsigned component,
2946 bool is_patch,
2947 bool is_compact,
2948 unsigned writemask)
2949 {
2950 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2951 LLVMValueRef dw_addr;
2952 LLVMValueRef stride = NULL;
2953 LLVMValueRef buf_addr = NULL;
2954 unsigned param;
2955 bool store_lds = true;
2956
2957 if (is_patch) {
2958 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2959 store_lds = false;
2960 } else {
2961 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2962 store_lds = false;
2963 }
2964
2965 param = shader_io_get_unique_index(location);
2966 if (location == VARYING_SLOT_CLIP_DIST0 &&
2967 is_compact && const_index > 3) {
2968 const_index -= 3;
2969 param++;
2970 }
2971
2972 if (!is_patch) {
2973 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2974 dw_addr = get_tcs_out_current_patch_offset(ctx);
2975 } else {
2976 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2977 }
2978
2979 mark_tess_output(ctx, is_patch, param);
2980
2981 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2982 param_index);
2983 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2984 vertex_index, param_index);
2985
2986 bool is_tess_factor = false;
2987 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2988 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2989 is_tess_factor = true;
2990
2991 unsigned base = is_compact ? const_index : 0;
2992 for (unsigned chan = 0; chan < 8; chan++) {
2993 if (!(writemask & (1 << chan)))
2994 continue;
2995 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2996
2997 if (store_lds || is_tess_factor) {
2998 LLVMValueRef dw_addr_chan =
2999 LLVMBuildAdd(ctx->builder, dw_addr,
3000 LLVMConstInt(ctx->ac.i32, chan, false), "");
3001 ac_lds_store(&ctx->ac, dw_addr_chan, value);
3002 }
3003
3004 if (!is_tess_factor && writemask != 0xF)
3005 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
3006 buf_addr, ctx->oc_lds,
3007 4 * (base + chan), 1, 0, true, false);
3008 }
3009
3010 if (writemask == 0xF) {
3011 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3012 buf_addr, ctx->oc_lds,
3013 (base * 4), 1, 0, true, false);
3014 }
3015 }
3016
3017 static LLVMValueRef
3018 load_tes_input(struct ac_shader_abi *abi,
3019 LLVMValueRef vertex_index,
3020 LLVMValueRef param_index,
3021 unsigned const_index,
3022 unsigned location,
3023 unsigned driver_location,
3024 unsigned component,
3025 unsigned num_components,
3026 bool is_patch,
3027 bool is_compact,
3028 bool load_input)
3029 {
3030 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3031 LLVMValueRef buf_addr;
3032 LLVMValueRef result;
3033 unsigned param = shader_io_get_unique_index(location);
3034
3035 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3036 const_index -= 3;
3037 param++;
3038 }
3039
3040 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3041 is_compact, vertex_index, param_index);
3042
3043 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3044 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3045
3046 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3047 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3048 result = trim_vector(&ctx->ac, result, num_components);
3049 return result;
3050 }
3051
3052 static LLVMValueRef
3053 load_gs_input(struct ac_shader_abi *abi,
3054 unsigned location,
3055 unsigned driver_location,
3056 unsigned component,
3057 unsigned num_components,
3058 unsigned vertex_index,
3059 unsigned const_index,
3060 LLVMTypeRef type)
3061 {
3062 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3063 LLVMValueRef vtx_offset;
3064 LLVMValueRef args[9];
3065 unsigned param, vtx_offset_param;
3066 LLVMValueRef value[4], result;
3067
3068 vtx_offset_param = vertex_index;
3069 assert(vtx_offset_param < 6);
3070 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3071 LLVMConstInt(ctx->ac.i32, 4, false), "");
3072
3073 param = shader_io_get_unique_index(location);
3074
3075 for (unsigned i = component; i < num_components + component; i++) {
3076 if (ctx->ac.chip_class >= GFX9) {
3077 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3078 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3079 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3080 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3081 } else {
3082 args[0] = ctx->esgs_ring;
3083 args[1] = vtx_offset;
3084 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3085 args[3] = ctx->ac.i32_0;
3086 args[4] = ctx->ac.i32_1; /* OFFEN */
3087 args[5] = ctx->ac.i32_0; /* IDXEN */
3088 args[6] = ctx->ac.i32_1; /* GLC */
3089 args[7] = ctx->ac.i32_0; /* SLC */
3090 args[8] = ctx->ac.i32_0; /* TFE */
3091
3092 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3093 ctx->ac.i32, args, 9,
3094 AC_FUNC_ATTR_READONLY |
3095 AC_FUNC_ATTR_LEGACY);
3096 }
3097 }
3098 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3099
3100 return result;
3101 }
3102
3103 static LLVMValueRef
3104 build_gep_for_deref(struct ac_nir_context *ctx,
3105 nir_deref_var *deref)
3106 {
3107 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3108 assert(entry->data);
3109 LLVMValueRef val = entry->data;
3110 nir_deref *tail = deref->deref.child;
3111 while (tail != NULL) {
3112 LLVMValueRef offset;
3113 switch (tail->deref_type) {
3114 case nir_deref_type_array: {
3115 nir_deref_array *array = nir_deref_as_array(tail);
3116 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3117 if (array->deref_array_type ==
3118 nir_deref_array_type_indirect) {
3119 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3120 get_src(ctx,
3121 array->indirect),
3122 "");
3123 }
3124 break;
3125 }
3126 case nir_deref_type_struct: {
3127 nir_deref_struct *deref_struct =
3128 nir_deref_as_struct(tail);
3129 offset = LLVMConstInt(ctx->ac.i32,
3130 deref_struct->index, 0);
3131 break;
3132 }
3133 default:
3134 unreachable("bad deref type");
3135 }
3136 val = ac_build_gep0(&ctx->ac, val, offset);
3137 tail = tail->child;
3138 }
3139 return val;
3140 }
3141
3142 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3143 nir_intrinsic_instr *instr,
3144 bool load_inputs)
3145 {
3146 LLVMValueRef result;
3147 LLVMValueRef vertex_index = NULL;
3148 LLVMValueRef indir_index = NULL;
3149 unsigned const_index = 0;
3150 unsigned location = instr->variables[0]->var->data.location;
3151 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3152 const bool is_patch = instr->variables[0]->var->data.patch;
3153 const bool is_compact = instr->variables[0]->var->data.compact;
3154
3155 get_deref_offset(ctx, instr->variables[0],
3156 false, NULL, is_patch ? NULL : &vertex_index,
3157 &const_index, &indir_index);
3158
3159 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3160 const_index, location, driver_location,
3161 instr->variables[0]->var->data.location_frac,
3162 instr->num_components,
3163 is_patch, is_compact, load_inputs);
3164 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3165 }
3166
3167 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3168 nir_intrinsic_instr *instr)
3169 {
3170 LLVMValueRef values[8];
3171 int idx = instr->variables[0]->var->data.driver_location;
3172 int ve = instr->dest.ssa.num_components;
3173 unsigned comp = instr->variables[0]->var->data.location_frac;
3174 LLVMValueRef indir_index;
3175 LLVMValueRef ret;
3176 unsigned const_index;
3177 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3178 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3179 instr->variables[0]->var->data.mode == nir_var_shader_in;
3180 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3181 &const_index, &indir_index);
3182
3183 if (instr->dest.ssa.bit_size == 64)
3184 ve *= 2;
3185
3186 switch (instr->variables[0]->var->data.mode) {
3187 case nir_var_shader_in:
3188 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3189 ctx->stage == MESA_SHADER_TESS_EVAL) {
3190 return load_tess_varyings(ctx, instr, true);
3191 }
3192
3193 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3194 LLVMValueRef indir_index;
3195 unsigned const_index, vertex_index;
3196 get_deref_offset(ctx, instr->variables[0],
3197 false, &vertex_index, NULL,
3198 &const_index, &indir_index);
3199 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3200 instr->variables[0]->var->data.driver_location,
3201 instr->variables[0]->var->data.location_frac, ve,
3202 vertex_index, const_index,
3203 nir2llvmtype(ctx, instr->variables[0]->var->type));
3204 }
3205
3206 for (unsigned chan = comp; chan < ve + comp; chan++) {
3207 if (indir_index) {
3208 unsigned count = glsl_count_attribute_slots(
3209 instr->variables[0]->var->type,
3210 ctx->stage == MESA_SHADER_VERTEX);
3211 count -= chan / 4;
3212 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3213 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3214 stride, false, true);
3215
3216 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3217 tmp_vec,
3218 indir_index, "");
3219 } else
3220 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3221 }
3222 break;
3223 case nir_var_local:
3224 for (unsigned chan = 0; chan < ve; chan++) {
3225 if (indir_index) {
3226 unsigned count = glsl_count_attribute_slots(
3227 instr->variables[0]->var->type, false);
3228 count -= chan / 4;
3229 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3230 &ctx->ac, ctx->locals + idx + chan, count,
3231 stride, true, true);
3232
3233 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3234 tmp_vec,
3235 indir_index, "");
3236 } else {
3237 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3238 }
3239 }
3240 break;
3241 case nir_var_shared: {
3242 LLVMValueRef address = build_gep_for_deref(ctx,
3243 instr->variables[0]);
3244 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3245 return LLVMBuildBitCast(ctx->ac.builder, val,
3246 get_def_type(ctx, &instr->dest.ssa),
3247 "");
3248 }
3249 case nir_var_shader_out:
3250 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3251 return load_tess_varyings(ctx, instr, false);
3252 }
3253
3254 for (unsigned chan = comp; chan < ve + comp; chan++) {
3255 if (indir_index) {
3256 unsigned count = glsl_count_attribute_slots(
3257 instr->variables[0]->var->type, false);
3258 count -= chan / 4;
3259 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3260 &ctx->ac, ctx->outputs + idx + chan, count,
3261 stride, true, true);
3262
3263 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3264 tmp_vec,
3265 indir_index, "");
3266 } else {
3267 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3268 ctx->outputs[idx + chan + const_index * stride],
3269 "");
3270 }
3271 }
3272 break;
3273 default:
3274 unreachable("unhandle variable mode");
3275 }
3276 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3277 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3278 }
3279
3280 static void
3281 visit_store_var(struct ac_nir_context *ctx,
3282 nir_intrinsic_instr *instr)
3283 {
3284 LLVMValueRef temp_ptr, value;
3285 int idx = instr->variables[0]->var->data.driver_location;
3286 unsigned comp = instr->variables[0]->var->data.location_frac;
3287 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3288 int writemask = instr->const_index[0] << comp;
3289 LLVMValueRef indir_index;
3290 unsigned const_index;
3291 get_deref_offset(ctx, instr->variables[0], false,
3292 NULL, NULL, &const_index, &indir_index);
3293
3294 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3295
3296 src = LLVMBuildBitCast(ctx->ac.builder, src,
3297 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3298 "");
3299
3300 writemask = widen_mask(writemask, 2);
3301 }
3302
3303 switch (instr->variables[0]->var->data.mode) {
3304 case nir_var_shader_out:
3305
3306 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3307 LLVMValueRef vertex_index = NULL;
3308 LLVMValueRef indir_index = NULL;
3309 unsigned const_index = 0;
3310 const unsigned location = instr->variables[0]->var->data.location;
3311 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3312 const unsigned comp = instr->variables[0]->var->data.location_frac;
3313 const bool is_patch = instr->variables[0]->var->data.patch;
3314 const bool is_compact = instr->variables[0]->var->data.compact;
3315
3316 get_deref_offset(ctx, instr->variables[0],
3317 false, NULL, is_patch ? NULL : &vertex_index,
3318 &const_index, &indir_index);
3319
3320 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3321 const_index, location, driver_location,
3322 src, comp, is_patch, is_compact, writemask);
3323 return;
3324 }
3325
3326 for (unsigned chan = 0; chan < 8; chan++) {
3327 int stride = 4;
3328 if (!(writemask & (1 << chan)))
3329 continue;
3330
3331 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3332
3333 if (instr->variables[0]->var->data.compact)
3334 stride = 1;
3335 if (indir_index) {
3336 unsigned count = glsl_count_attribute_slots(
3337 instr->variables[0]->var->type, false);
3338 count -= chan / 4;
3339 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3340 &ctx->ac, ctx->outputs + idx + chan, count,
3341 stride, true, true);
3342
3343 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3344 value, indir_index, "");
3345 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3346 count, stride, tmp_vec);
3347
3348 } else {
3349 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3350
3351 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3352 }
3353 }
3354 break;
3355 case nir_var_local:
3356 for (unsigned chan = 0; chan < 8; chan++) {
3357 if (!(writemask & (1 << chan)))
3358 continue;
3359
3360 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3361 if (indir_index) {
3362 unsigned count = glsl_count_attribute_slots(
3363 instr->variables[0]->var->type, false);
3364 count -= chan / 4;
3365 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3366 &ctx->ac, ctx->locals + idx + chan, count,
3367 4, true, true);
3368
3369 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3370 value, indir_index, "");
3371 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3372 count, 4, tmp_vec);
3373 } else {
3374 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3375
3376 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3377 }
3378 }
3379 break;
3380 case nir_var_shared: {
3381 int writemask = instr->const_index[0];
3382 LLVMValueRef address = build_gep_for_deref(ctx,
3383 instr->variables[0]);
3384 LLVMValueRef val = get_src(ctx, instr->src[0]);
3385 unsigned components =
3386 glsl_get_vector_elements(
3387 nir_deref_tail(&instr->variables[0]->deref)->type);
3388 if (writemask == (1 << components) - 1) {
3389 val = LLVMBuildBitCast(
3390 ctx->ac.builder, val,
3391 LLVMGetElementType(LLVMTypeOf(address)), "");
3392 LLVMBuildStore(ctx->ac.builder, val, address);
3393 } else {
3394 for (unsigned chan = 0; chan < 4; chan++) {
3395 if (!(writemask & (1 << chan)))
3396 continue;
3397 LLVMValueRef ptr =
3398 LLVMBuildStructGEP(ctx->ac.builder,
3399 address, chan, "");
3400 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3401 chan);
3402 src = LLVMBuildBitCast(
3403 ctx->ac.builder, src,
3404 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3405 LLVMBuildStore(ctx->ac.builder, src, ptr);
3406 }
3407 }
3408 break;
3409 }
3410 default:
3411 break;
3412 }
3413 }
3414
3415 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3416 {
3417 switch (dim) {
3418 case GLSL_SAMPLER_DIM_BUF:
3419 return 1;
3420 case GLSL_SAMPLER_DIM_1D:
3421 return array ? 2 : 1;
3422 case GLSL_SAMPLER_DIM_2D:
3423 return array ? 3 : 2;
3424 case GLSL_SAMPLER_DIM_MS:
3425 return array ? 4 : 3;
3426 case GLSL_SAMPLER_DIM_3D:
3427 case GLSL_SAMPLER_DIM_CUBE:
3428 return 3;
3429 case GLSL_SAMPLER_DIM_RECT:
3430 case GLSL_SAMPLER_DIM_SUBPASS:
3431 return 2;
3432 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3433 return 3;
3434 default:
3435 break;
3436 }
3437 return 0;
3438 }
3439
3440
3441
3442 /* Adjust the sample index according to FMASK.
3443 *
3444 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3445 * which is the identity mapping. Each nibble says which physical sample
3446 * should be fetched to get that sample.
3447 *
3448 * For example, 0x11111100 means there are only 2 samples stored and
3449 * the second sample covers 3/4 of the pixel. When reading samples 0
3450 * and 1, return physical sample 0 (determined by the first two 0s
3451 * in FMASK), otherwise return physical sample 1.
3452 *
3453 * The sample index should be adjusted as follows:
3454 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3455 */
3456 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3457 LLVMValueRef coord_x, LLVMValueRef coord_y,
3458 LLVMValueRef coord_z,
3459 LLVMValueRef sample_index,
3460 LLVMValueRef fmask_desc_ptr)
3461 {
3462 LLVMValueRef fmask_load_address[4];
3463 LLVMValueRef res;
3464
3465 fmask_load_address[0] = coord_x;
3466 fmask_load_address[1] = coord_y;
3467 if (coord_z) {
3468 fmask_load_address[2] = coord_z;
3469 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3470 }
3471
3472 struct ac_image_args args = {0};
3473
3474 args.opcode = ac_image_load;
3475 args.da = coord_z ? true : false;
3476 args.resource = fmask_desc_ptr;
3477 args.dmask = 0xf;
3478 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3479
3480 res = ac_build_image_opcode(ctx, &args);
3481
3482 res = ac_to_integer(ctx, res);
3483 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3484 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3485
3486 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3487 res,
3488 ctx->i32_0, "");
3489
3490 LLVMValueRef sample_index4 =
3491 LLVMBuildMul(ctx->builder, sample_index, four, "");
3492 LLVMValueRef shifted_fmask =
3493 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3494 LLVMValueRef final_sample =
3495 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3496
3497 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3498 * resource descriptor is 0 (invalid),
3499 */
3500 LLVMValueRef fmask_desc =
3501 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3502 ctx->v8i32, "");
3503
3504 LLVMValueRef fmask_word1 =
3505 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3506 ctx->i32_1, "");
3507
3508 LLVMValueRef word1_is_nonzero =
3509 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3510 fmask_word1, ctx->i32_0, "");
3511
3512 /* Replace the MSAA sample index. */
3513 sample_index =
3514 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3515 final_sample, sample_index, "");
3516 return sample_index;
3517 }
3518
3519 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3520 const nir_intrinsic_instr *instr)
3521 {
3522 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3523
3524 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3525 LLVMValueRef coords[4];
3526 LLVMValueRef masks[] = {
3527 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3528 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3529 };
3530 LLVMValueRef res;
3531 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3532
3533 int count;
3534 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3535 bool is_array = glsl_sampler_type_is_array(type);
3536 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3537 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3538 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3539 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3540 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3541 count = image_type_to_components_count(dim, is_array);
3542
3543 if (is_ms) {
3544 LLVMValueRef fmask_load_address[3];
3545 int chan;
3546
3547 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3548 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3549 if (is_array)
3550 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3551 else
3552 fmask_load_address[2] = NULL;
3553 if (add_frag_pos) {
3554 for (chan = 0; chan < 2; ++chan)
3555 fmask_load_address[chan] =
3556 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3557 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3558 ctx->ac.i32, ""), "");
3559 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3560 }
3561 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3562 fmask_load_address[0],
3563 fmask_load_address[1],
3564 fmask_load_address[2],
3565 sample_index,
3566 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3567 }
3568 if (count == 1 && !gfx9_1d) {
3569 if (instr->src[0].ssa->num_components)
3570 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3571 else
3572 res = src0;
3573 } else {
3574 int chan;
3575 if (is_ms)
3576 count--;
3577 for (chan = 0; chan < count; ++chan) {
3578 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3579 }
3580 if (add_frag_pos) {
3581 for (chan = 0; chan < 2; ++chan)
3582 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3583 ctx->ac.i32, ""), "");
3584 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3585 count++;
3586 }
3587
3588 if (gfx9_1d) {
3589 if (is_array) {
3590 coords[2] = coords[1];
3591 coords[1] = ctx->ac.i32_0;
3592 } else
3593 coords[1] = ctx->ac.i32_0;
3594 count++;
3595 }
3596
3597 if (is_ms) {
3598 coords[count] = sample_index;
3599 count++;
3600 }
3601
3602 if (count == 3) {
3603 coords[3] = LLVMGetUndef(ctx->ac.i32);
3604 count = 4;
3605 }
3606 res = ac_build_gather_values(&ctx->ac, coords, count);
3607 }
3608 return res;
3609 }
3610
3611 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3612 const nir_intrinsic_instr *instr)
3613 {
3614 LLVMValueRef params[7];
3615 LLVMValueRef res;
3616 char intrinsic_name[64];
3617 const nir_variable *var = instr->variables[0]->var;
3618 const struct glsl_type *type = var->type;
3619
3620 if(instr->variables[0]->deref.child)
3621 type = instr->variables[0]->deref.child->type;
3622
3623 type = glsl_without_array(type);
3624 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3625 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3626 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3627 ctx->ac.i32_0, ""); /* vindex */
3628 params[2] = ctx->ac.i32_0; /* voffset */
3629 params[3] = ctx->ac.i1false; /* glc */
3630 params[4] = ctx->ac.i1false; /* slc */
3631 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3632 params, 5, 0);
3633
3634 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3635 res = ac_to_integer(&ctx->ac, res);
3636 } else {
3637 bool is_da = glsl_sampler_type_is_array(type) ||
3638 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3639 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D ||
3640 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3641 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3642 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3643 LLVMValueRef glc = ctx->ac.i1false;
3644 LLVMValueRef slc = ctx->ac.i1false;
3645
3646 params[0] = get_image_coords(ctx, instr);
3647 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3648 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3649 if (HAVE_LLVM <= 0x0309) {
3650 params[3] = ctx->ac.i1false; /* r128 */
3651 params[4] = da;
3652 params[5] = glc;
3653 params[6] = slc;
3654 } else {
3655 LLVMValueRef lwe = ctx->ac.i1false;
3656 params[3] = glc;
3657 params[4] = slc;
3658 params[5] = lwe;
3659 params[6] = da;
3660 }
3661
3662 ac_get_image_intr_name("llvm.amdgcn.image.load",
3663 ctx->ac.v4f32, /* vdata */
3664 LLVMTypeOf(params[0]), /* coords */
3665 LLVMTypeOf(params[1]), /* rsrc */
3666 intrinsic_name, sizeof(intrinsic_name));
3667
3668 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3669 params, 7, AC_FUNC_ATTR_READONLY);
3670 }
3671 return ac_to_integer(&ctx->ac, res);
3672 }
3673
3674 static void visit_image_store(struct ac_nir_context *ctx,
3675 nir_intrinsic_instr *instr)
3676 {
3677 LLVMValueRef params[8];
3678 char intrinsic_name[64];
3679 const nir_variable *var = instr->variables[0]->var;
3680 const struct glsl_type *type = glsl_without_array(var->type);
3681 LLVMValueRef glc = ctx->ac.i1false;
3682 bool force_glc = ctx->ac.chip_class == SI;
3683 if (force_glc)
3684 glc = ctx->ac.i1true;
3685
3686 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3687 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3688 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3689 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3690 ctx->ac.i32_0, ""); /* vindex */
3691 params[3] = ctx->ac.i32_0; /* voffset */
3692 params[4] = glc; /* glc */
3693 params[5] = ctx->ac.i1false; /* slc */
3694 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3695 params, 6, 0);
3696 } else {
3697 bool is_da = glsl_sampler_type_is_array(type) ||
3698 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3699 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3700 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3701 LLVMValueRef slc = ctx->ac.i1false;
3702
3703 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3704 params[1] = get_image_coords(ctx, instr); /* coords */
3705 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3706 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3707 if (HAVE_LLVM <= 0x0309) {
3708 params[4] = ctx->ac.i1false; /* r128 */
3709 params[5] = da;
3710 params[6] = glc;
3711 params[7] = slc;
3712 } else {
3713 LLVMValueRef lwe = ctx->ac.i1false;
3714 params[4] = glc;
3715 params[5] = slc;
3716 params[6] = lwe;
3717 params[7] = da;
3718 }
3719
3720 ac_get_image_intr_name("llvm.amdgcn.image.store",
3721 LLVMTypeOf(params[0]), /* vdata */
3722 LLVMTypeOf(params[1]), /* coords */
3723 LLVMTypeOf(params[2]), /* rsrc */
3724 intrinsic_name, sizeof(intrinsic_name));
3725
3726 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3727 params, 8, 0);
3728 }
3729
3730 }
3731
3732 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3733 const nir_intrinsic_instr *instr)
3734 {
3735 LLVMValueRef params[7];
3736 int param_count = 0;
3737 const nir_variable *var = instr->variables[0]->var;
3738
3739 const char *atomic_name;
3740 char intrinsic_name[41];
3741 const struct glsl_type *type = glsl_without_array(var->type);
3742 MAYBE_UNUSED int length;
3743
3744 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3745
3746 switch (instr->intrinsic) {
3747 case nir_intrinsic_image_atomic_add:
3748 atomic_name = "add";
3749 break;
3750 case nir_intrinsic_image_atomic_min:
3751 atomic_name = is_unsigned ? "umin" : "smin";
3752 break;
3753 case nir_intrinsic_image_atomic_max:
3754 atomic_name = is_unsigned ? "umax" : "smax";
3755 break;
3756 case nir_intrinsic_image_atomic_and:
3757 atomic_name = "and";
3758 break;
3759 case nir_intrinsic_image_atomic_or:
3760 atomic_name = "or";
3761 break;
3762 case nir_intrinsic_image_atomic_xor:
3763 atomic_name = "xor";
3764 break;
3765 case nir_intrinsic_image_atomic_exchange:
3766 atomic_name = "swap";
3767 break;
3768 case nir_intrinsic_image_atomic_comp_swap:
3769 atomic_name = "cmpswap";
3770 break;
3771 default:
3772 abort();
3773 }
3774
3775 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3776 params[param_count++] = get_src(ctx, instr->src[3]);
3777 params[param_count++] = get_src(ctx, instr->src[2]);
3778
3779 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3780 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3781 NULL, true, true);
3782 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3783 ctx->ac.i32_0, ""); /* vindex */
3784 params[param_count++] = ctx->ac.i32_0; /* voffset */
3785 params[param_count++] = ctx->ac.i1false; /* slc */
3786
3787 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3788 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3789 } else {
3790 char coords_type[8];
3791
3792 bool da = glsl_sampler_type_is_array(type) ||
3793 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3794
3795 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3796 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3797 NULL, true, true);
3798 params[param_count++] = ctx->ac.i1false; /* r128 */
3799 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3800 params[param_count++] = ctx->ac.i1false; /* slc */
3801
3802 build_int_type_name(LLVMTypeOf(coords),
3803 coords_type, sizeof(coords_type));
3804
3805 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3806 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3807 }
3808
3809 assert(length < sizeof(intrinsic_name));
3810 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3811 }
3812
3813 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3814 const nir_intrinsic_instr *instr)
3815 {
3816 LLVMValueRef res;
3817 const nir_variable *var = instr->variables[0]->var;
3818 const struct glsl_type *type = instr->variables[0]->var->type;
3819 bool da = glsl_sampler_type_is_array(var->type) ||
3820 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3821 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3822 if(instr->variables[0]->deref.child)
3823 type = instr->variables[0]->deref.child->type;
3824
3825 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3826 return get_buffer_size(ctx,
3827 get_sampler_desc(ctx, instr->variables[0],
3828 AC_DESC_BUFFER, NULL, true, false), true);
3829
3830 struct ac_image_args args = { 0 };
3831
3832 args.da = da;
3833 args.dmask = 0xf;
3834 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3835 args.opcode = ac_image_get_resinfo;
3836 args.addr = ctx->ac.i32_0;
3837
3838 res = ac_build_image_opcode(&ctx->ac, &args);
3839
3840 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3841
3842 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3843 glsl_sampler_type_is_array(type)) {
3844 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3845 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3846 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3847 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3848 }
3849 if (ctx->ac.chip_class >= GFX9 &&
3850 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3851 glsl_sampler_type_is_array(type)) {
3852 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3853 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3854 ctx->ac.i32_1, "");
3855
3856 }
3857 return res;
3858 }
3859
3860 #define NOOP_WAITCNT 0xf7f
3861 #define LGKM_CNT 0x07f
3862 #define VM_CNT 0xf70
3863
3864 static void emit_membar(struct nir_to_llvm_context *ctx,
3865 const nir_intrinsic_instr *instr)
3866 {
3867 unsigned waitcnt = NOOP_WAITCNT;
3868
3869 switch (instr->intrinsic) {
3870 case nir_intrinsic_memory_barrier:
3871 case nir_intrinsic_group_memory_barrier:
3872 waitcnt &= VM_CNT & LGKM_CNT;
3873 break;
3874 case nir_intrinsic_memory_barrier_atomic_counter:
3875 case nir_intrinsic_memory_barrier_buffer:
3876 case nir_intrinsic_memory_barrier_image:
3877 waitcnt &= VM_CNT;
3878 break;
3879 case nir_intrinsic_memory_barrier_shared:
3880 waitcnt &= LGKM_CNT;
3881 break;
3882 default:
3883 break;
3884 }
3885 if (waitcnt != NOOP_WAITCNT)
3886 ac_build_waitcnt(&ctx->ac, waitcnt);
3887 }
3888
3889 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3890 {
3891 /* SI only (thanks to a hw bug workaround):
3892 * The real barrier instruction isn’t needed, because an entire patch
3893 * always fits into a single wave.
3894 */
3895 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3896 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3897 return;
3898 }
3899 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3900 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3901 }
3902
3903 static void emit_discard(struct ac_nir_context *ctx,
3904 const nir_intrinsic_instr *instr)
3905 {
3906 LLVMValueRef cond;
3907
3908 if (instr->intrinsic == nir_intrinsic_discard_if) {
3909 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3910 get_src(ctx, instr->src[0]),
3911 ctx->ac.i32_0, "");
3912 } else {
3913 assert(instr->intrinsic == nir_intrinsic_discard);
3914 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3915 }
3916
3917 ac_build_kill_if_false(&ctx->ac, cond);
3918 }
3919
3920 static LLVMValueRef
3921 visit_load_helper_invocation(struct ac_nir_context *ctx)
3922 {
3923 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3924 "llvm.amdgcn.ps.live",
3925 ctx->ac.i1, NULL, 0,
3926 AC_FUNC_ATTR_READNONE);
3927 result = LLVMBuildNot(ctx->ac.builder, result, "");
3928 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3929 }
3930
3931 static LLVMValueRef
3932 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3933 {
3934 LLVMValueRef result;
3935 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3936 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3937 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3938
3939 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3940 }
3941
3942 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3943 const nir_intrinsic_instr *instr)
3944 {
3945 LLVMValueRef ptr, result;
3946 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3947 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3948
3949 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3950 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3951 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3952 ptr, src, src1,
3953 LLVMAtomicOrderingSequentiallyConsistent,
3954 LLVMAtomicOrderingSequentiallyConsistent,
3955 false);
3956 } else {
3957 LLVMAtomicRMWBinOp op;
3958 switch (instr->intrinsic) {
3959 case nir_intrinsic_var_atomic_add:
3960 op = LLVMAtomicRMWBinOpAdd;
3961 break;
3962 case nir_intrinsic_var_atomic_umin:
3963 op = LLVMAtomicRMWBinOpUMin;
3964 break;
3965 case nir_intrinsic_var_atomic_umax:
3966 op = LLVMAtomicRMWBinOpUMax;
3967 break;
3968 case nir_intrinsic_var_atomic_imin:
3969 op = LLVMAtomicRMWBinOpMin;
3970 break;
3971 case nir_intrinsic_var_atomic_imax:
3972 op = LLVMAtomicRMWBinOpMax;
3973 break;
3974 case nir_intrinsic_var_atomic_and:
3975 op = LLVMAtomicRMWBinOpAnd;
3976 break;
3977 case nir_intrinsic_var_atomic_or:
3978 op = LLVMAtomicRMWBinOpOr;
3979 break;
3980 case nir_intrinsic_var_atomic_xor:
3981 op = LLVMAtomicRMWBinOpXor;
3982 break;
3983 case nir_intrinsic_var_atomic_exchange:
3984 op = LLVMAtomicRMWBinOpXchg;
3985 break;
3986 default:
3987 return NULL;
3988 }
3989
3990 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3991 LLVMAtomicOrderingSequentiallyConsistent,
3992 false);
3993 }
3994 return result;
3995 }
3996
3997 #define INTERP_CENTER 0
3998 #define INTERP_CENTROID 1
3999 #define INTERP_SAMPLE 2
4000
4001 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
4002 enum glsl_interp_mode interp, unsigned location)
4003 {
4004 switch (interp) {
4005 case INTERP_MODE_FLAT:
4006 default:
4007 return NULL;
4008 case INTERP_MODE_SMOOTH:
4009 case INTERP_MODE_NONE:
4010 if (location == INTERP_CENTER)
4011 return ctx->persp_center;
4012 else if (location == INTERP_CENTROID)
4013 return ctx->persp_centroid;
4014 else if (location == INTERP_SAMPLE)
4015 return ctx->persp_sample;
4016 break;
4017 case INTERP_MODE_NOPERSPECTIVE:
4018 if (location == INTERP_CENTER)
4019 return ctx->linear_center;
4020 else if (location == INTERP_CENTROID)
4021 return ctx->linear_centroid;
4022 else if (location == INTERP_SAMPLE)
4023 return ctx->linear_sample;
4024 break;
4025 }
4026 return NULL;
4027 }
4028
4029 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
4030 LLVMValueRef sample_id)
4031 {
4032 LLVMValueRef result;
4033 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4034
4035 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4036 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4037
4038 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4039 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4040
4041 return result;
4042 }
4043
4044 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4045 {
4046 LLVMValueRef values[2];
4047
4048 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
4049 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
4050 return ac_build_gather_values(&ctx->ac, values, 2);
4051 }
4052
4053 static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
4054 {
4055 uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? ctx->nctx->options->key.fs.log2_num_samples : ctx->nctx->options->key.fs.log2_ps_iter_samples;
4056
4057 /* The bit pattern matches that used by fixed function fragment
4058 * processing. */
4059 static const uint16_t ps_iter_masks[] = {
4060 0xffff, /* not used */
4061 0x5555,
4062 0x1111,
4063 0x0101,
4064 0x0001,
4065 };
4066 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4067
4068 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4069
4070 LLVMValueRef result, sample_id;
4071 sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4072 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4073 result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, "");
4074 return result;
4075 }
4076
4077 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
4078 const nir_intrinsic_instr *instr)
4079 {
4080 LLVMValueRef result[4];
4081 LLVMValueRef interp_param, attr_number;
4082 unsigned location;
4083 unsigned chan;
4084 LLVMValueRef src_c0 = NULL;
4085 LLVMValueRef src_c1 = NULL;
4086 LLVMValueRef src0 = NULL;
4087 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4088 switch (instr->intrinsic) {
4089 case nir_intrinsic_interp_var_at_centroid:
4090 location = INTERP_CENTROID;
4091 break;
4092 case nir_intrinsic_interp_var_at_sample:
4093 case nir_intrinsic_interp_var_at_offset:
4094 location = INTERP_CENTER;
4095 src0 = get_src(ctx->nir, instr->src[0]);
4096 break;
4097 default:
4098 break;
4099 }
4100
4101 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4102 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4103 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4104 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4105 LLVMValueRef sample_position;
4106 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4107
4108 /* fetch sample ID */
4109 sample_position = load_sample_position(ctx, src0);
4110
4111 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4112 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4113 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4114 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4115 }
4116 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4117 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4118
4119 if (location == INTERP_CENTER) {
4120 LLVMValueRef ij_out[2];
4121 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4122
4123 /*
4124 * take the I then J parameters, and the DDX/Y for it, and
4125 * calculate the IJ inputs for the interpolator.
4126 * temp1 = ddx * offset/sample.x + I;
4127 * interp_param.I = ddy * offset/sample.y + temp1;
4128 * temp1 = ddx * offset/sample.x + J;
4129 * interp_param.J = ddy * offset/sample.y + temp1;
4130 */
4131 for (unsigned i = 0; i < 2; i++) {
4132 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4133 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4134 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4135 ddxy_out, ix_ll, "");
4136 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4137 ddxy_out, iy_ll, "");
4138 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4139 interp_param, ix_ll, "");
4140 LLVMValueRef temp1, temp2;
4141
4142 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4143 ctx->ac.f32, "");
4144
4145 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4146 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4147
4148 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4149 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4150
4151 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4152 temp2, ctx->ac.i32, "");
4153 }
4154 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4155
4156 }
4157
4158 for (chan = 0; chan < 4; chan++) {
4159 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4160
4161 if (interp_param) {
4162 interp_param = LLVMBuildBitCast(ctx->builder,
4163 interp_param, ctx->ac.v2f32, "");
4164 LLVMValueRef i = LLVMBuildExtractElement(
4165 ctx->builder, interp_param, ctx->ac.i32_0, "");
4166 LLVMValueRef j = LLVMBuildExtractElement(
4167 ctx->builder, interp_param, ctx->ac.i32_1, "");
4168
4169 result[chan] = ac_build_fs_interp(&ctx->ac,
4170 llvm_chan, attr_number,
4171 ctx->prim_mask, i, j);
4172 } else {
4173 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4174 LLVMConstInt(ctx->ac.i32, 2, false),
4175 llvm_chan, attr_number,
4176 ctx->prim_mask);
4177 }
4178 }
4179 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4180 instr->variables[0]->var->data.location_frac);
4181 }
4182
4183 static void
4184 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4185 {
4186 LLVMValueRef gs_next_vertex;
4187 LLVMValueRef can_emit;
4188 int idx;
4189 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4190
4191 assert(stream == 0);
4192
4193 /* Write vertex attribute values to GSVS ring */
4194 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4195 ctx->gs_next_vertex,
4196 "");
4197
4198 /* If this thread has already emitted the declared maximum number of
4199 * vertices, kill it: excessive vertex emissions are not supposed to
4200 * have any effect, and GS threads have no externally observable
4201 * effects other than emitting vertices.
4202 */
4203 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4204 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4205 ac_build_kill_if_false(&ctx->ac, can_emit);
4206
4207 /* loop num outputs */
4208 idx = 0;
4209 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4210 LLVMValueRef *out_ptr = &addrs[i * 4];
4211 int length = 4;
4212 int slot = idx;
4213 int slot_inc = 1;
4214
4215 if (!(ctx->output_mask & (1ull << i)))
4216 continue;
4217
4218 if (i == VARYING_SLOT_CLIP_DIST0) {
4219 /* pack clip and cull into a single set of slots */
4220 length = ctx->num_output_clips + ctx->num_output_culls;
4221 if (length > 4)
4222 slot_inc = 2;
4223 }
4224 for (unsigned j = 0; j < length; j++) {
4225 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4226 out_ptr[j], "");
4227 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4228 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4229 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4230
4231 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4232
4233 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4234 out_val, 1,
4235 voffset, ctx->gs2vs_offset, 0,
4236 1, 1, true, true);
4237 }
4238 idx += slot_inc;
4239 }
4240
4241 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4242 ctx->ac.i32_1, "");
4243 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4244
4245 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4246 }
4247
4248 static void
4249 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4250 {
4251 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4252 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4253 }
4254
4255 static LLVMValueRef
4256 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4257 unsigned num_components)
4258 {
4259 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4260
4261 LLVMValueRef coord[4] = {
4262 ctx->tes_u,
4263 ctx->tes_v,
4264 ctx->ac.f32_0,
4265 ctx->ac.f32_0,
4266 };
4267
4268 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4269 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4270 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4271
4272 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4273 return LLVMBuildBitCast(ctx->builder, result, type, "");
4274 }
4275
4276 static LLVMValueRef
4277 load_patch_vertices_in(struct ac_shader_abi *abi)
4278 {
4279 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4280 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4281 }
4282
4283 static void visit_intrinsic(struct ac_nir_context *ctx,
4284 nir_intrinsic_instr *instr)
4285 {
4286 LLVMValueRef result = NULL;
4287
4288 switch (instr->intrinsic) {
4289 case nir_intrinsic_ballot:
4290 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4291 break;
4292 case nir_intrinsic_read_invocation:
4293 case nir_intrinsic_read_first_invocation: {
4294 LLVMValueRef args[2];
4295
4296 /* Value */
4297 args[0] = get_src(ctx, instr->src[0]);
4298
4299 unsigned num_args;
4300 const char *intr_name;
4301 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4302 num_args = 2;
4303 intr_name = "llvm.amdgcn.readlane";
4304
4305 /* Invocation */
4306 args[1] = get_src(ctx, instr->src[1]);
4307 } else {
4308 num_args = 1;
4309 intr_name = "llvm.amdgcn.readfirstlane";
4310 }
4311
4312 /* We currently have no other way to prevent LLVM from lifting the icmp
4313 * calls to a dominating basic block.
4314 */
4315 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4316
4317 result = ac_build_intrinsic(&ctx->ac, intr_name,
4318 ctx->ac.i32, args, num_args,
4319 AC_FUNC_ATTR_READNONE |
4320 AC_FUNC_ATTR_CONVERGENT);
4321 break;
4322 }
4323 case nir_intrinsic_load_subgroup_invocation:
4324 result = ac_get_thread_id(&ctx->ac);
4325 break;
4326 case nir_intrinsic_load_work_group_id: {
4327 LLVMValueRef values[3];
4328
4329 for (int i = 0; i < 3; i++) {
4330 values[i] = ctx->nctx->workgroup_ids[i] ?
4331 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4332 }
4333
4334 result = ac_build_gather_values(&ctx->ac, values, 3);
4335 break;
4336 }
4337 case nir_intrinsic_load_base_vertex: {
4338 result = ctx->abi->base_vertex;
4339 break;
4340 }
4341 case nir_intrinsic_load_vertex_id_zero_base: {
4342 result = ctx->abi->vertex_id;
4343 break;
4344 }
4345 case nir_intrinsic_load_local_invocation_id: {
4346 result = ctx->nctx->local_invocation_ids;
4347 break;
4348 }
4349 case nir_intrinsic_load_base_instance:
4350 result = ctx->abi->start_instance;
4351 break;
4352 case nir_intrinsic_load_draw_id:
4353 result = ctx->abi->draw_id;
4354 break;
4355 case nir_intrinsic_load_view_index:
4356 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4357 break;
4358 case nir_intrinsic_load_invocation_id:
4359 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4360 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4361 else
4362 result = ctx->abi->gs_invocation_id;
4363 break;
4364 case nir_intrinsic_load_primitive_id:
4365 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4366 result = ctx->abi->gs_prim_id;
4367 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4368 result = ctx->abi->tcs_patch_id;
4369 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4370 result = ctx->abi->tes_patch_id;
4371 } else
4372 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4373 break;
4374 case nir_intrinsic_load_sample_id:
4375 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4376 break;
4377 case nir_intrinsic_load_sample_pos:
4378 result = load_sample_pos(ctx);
4379 break;
4380 case nir_intrinsic_load_sample_mask_in:
4381 if (ctx->nctx)
4382 result = load_sample_mask_in(ctx);
4383 else
4384 result = ctx->abi->sample_coverage;
4385 break;
4386 case nir_intrinsic_load_frag_coord: {
4387 LLVMValueRef values[4] = {
4388 ctx->abi->frag_pos[0],
4389 ctx->abi->frag_pos[1],
4390 ctx->abi->frag_pos[2],
4391 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4392 };
4393 result = ac_build_gather_values(&ctx->ac, values, 4);
4394 break;
4395 }
4396 case nir_intrinsic_load_front_face:
4397 result = ctx->abi->front_face;
4398 break;
4399 case nir_intrinsic_load_helper_invocation:
4400 result = visit_load_helper_invocation(ctx);
4401 break;
4402 case nir_intrinsic_load_instance_id:
4403 result = ctx->abi->instance_id;
4404 break;
4405 case nir_intrinsic_load_num_work_groups:
4406 result = ctx->nctx->num_work_groups;
4407 break;
4408 case nir_intrinsic_load_local_invocation_index:
4409 result = visit_load_local_invocation_index(ctx->nctx);
4410 break;
4411 case nir_intrinsic_load_push_constant:
4412 result = visit_load_push_constant(ctx->nctx, instr);
4413 break;
4414 case nir_intrinsic_vulkan_resource_index:
4415 result = visit_vulkan_resource_index(ctx->nctx, instr);
4416 break;
4417 case nir_intrinsic_vulkan_resource_reindex:
4418 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4419 break;
4420 case nir_intrinsic_store_ssbo:
4421 visit_store_ssbo(ctx, instr);
4422 break;
4423 case nir_intrinsic_load_ssbo:
4424 result = visit_load_buffer(ctx, instr);
4425 break;
4426 case nir_intrinsic_ssbo_atomic_add:
4427 case nir_intrinsic_ssbo_atomic_imin:
4428 case nir_intrinsic_ssbo_atomic_umin:
4429 case nir_intrinsic_ssbo_atomic_imax:
4430 case nir_intrinsic_ssbo_atomic_umax:
4431 case nir_intrinsic_ssbo_atomic_and:
4432 case nir_intrinsic_ssbo_atomic_or:
4433 case nir_intrinsic_ssbo_atomic_xor:
4434 case nir_intrinsic_ssbo_atomic_exchange:
4435 case nir_intrinsic_ssbo_atomic_comp_swap:
4436 result = visit_atomic_ssbo(ctx, instr);
4437 break;
4438 case nir_intrinsic_load_ubo:
4439 result = visit_load_ubo_buffer(ctx, instr);
4440 break;
4441 case nir_intrinsic_get_buffer_size:
4442 result = visit_get_buffer_size(ctx, instr);
4443 break;
4444 case nir_intrinsic_load_var:
4445 result = visit_load_var(ctx, instr);
4446 break;
4447 case nir_intrinsic_store_var:
4448 visit_store_var(ctx, instr);
4449 break;
4450 case nir_intrinsic_image_load:
4451 result = visit_image_load(ctx, instr);
4452 break;
4453 case nir_intrinsic_image_store:
4454 visit_image_store(ctx, instr);
4455 break;
4456 case nir_intrinsic_image_atomic_add:
4457 case nir_intrinsic_image_atomic_min:
4458 case nir_intrinsic_image_atomic_max:
4459 case nir_intrinsic_image_atomic_and:
4460 case nir_intrinsic_image_atomic_or:
4461 case nir_intrinsic_image_atomic_xor:
4462 case nir_intrinsic_image_atomic_exchange:
4463 case nir_intrinsic_image_atomic_comp_swap:
4464 result = visit_image_atomic(ctx, instr);
4465 break;
4466 case nir_intrinsic_image_size:
4467 result = visit_image_size(ctx, instr);
4468 break;
4469 case nir_intrinsic_discard:
4470 case nir_intrinsic_discard_if:
4471 emit_discard(ctx, instr);
4472 break;
4473 case nir_intrinsic_memory_barrier:
4474 case nir_intrinsic_group_memory_barrier:
4475 case nir_intrinsic_memory_barrier_atomic_counter:
4476 case nir_intrinsic_memory_barrier_buffer:
4477 case nir_intrinsic_memory_barrier_image:
4478 case nir_intrinsic_memory_barrier_shared:
4479 emit_membar(ctx->nctx, instr);
4480 break;
4481 case nir_intrinsic_barrier:
4482 emit_barrier(&ctx->ac, ctx->stage);
4483 break;
4484 case nir_intrinsic_var_atomic_add:
4485 case nir_intrinsic_var_atomic_imin:
4486 case nir_intrinsic_var_atomic_umin:
4487 case nir_intrinsic_var_atomic_imax:
4488 case nir_intrinsic_var_atomic_umax:
4489 case nir_intrinsic_var_atomic_and:
4490 case nir_intrinsic_var_atomic_or:
4491 case nir_intrinsic_var_atomic_xor:
4492 case nir_intrinsic_var_atomic_exchange:
4493 case nir_intrinsic_var_atomic_comp_swap:
4494 result = visit_var_atomic(ctx->nctx, instr);
4495 break;
4496 case nir_intrinsic_interp_var_at_centroid:
4497 case nir_intrinsic_interp_var_at_sample:
4498 case nir_intrinsic_interp_var_at_offset:
4499 result = visit_interp(ctx->nctx, instr);
4500 break;
4501 case nir_intrinsic_emit_vertex:
4502 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4503 break;
4504 case nir_intrinsic_end_primitive:
4505 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4506 break;
4507 case nir_intrinsic_load_tess_coord: {
4508 LLVMTypeRef type = ctx->nctx ?
4509 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4510 NULL;
4511 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4512 break;
4513 }
4514 case nir_intrinsic_load_tess_level_outer:
4515 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4516 break;
4517 case nir_intrinsic_load_tess_level_inner:
4518 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4519 break;
4520 case nir_intrinsic_load_patch_vertices_in:
4521 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4522 break;
4523 case nir_intrinsic_vote_all: {
4524 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4525 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4526 break;
4527 }
4528 case nir_intrinsic_vote_any: {
4529 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4530 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4531 break;
4532 }
4533 case nir_intrinsic_vote_eq: {
4534 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4535 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4536 break;
4537 }
4538 default:
4539 fprintf(stderr, "Unknown intrinsic: ");
4540 nir_print_instr(&instr->instr, stderr);
4541 fprintf(stderr, "\n");
4542 break;
4543 }
4544 if (result) {
4545 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4546 }
4547 }
4548
4549 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4550 LLVMValueRef buffer_ptr, bool write)
4551 {
4552 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4553 LLVMValueRef result;
4554
4555 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4556
4557 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4558 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4559
4560 return result;
4561 }
4562
4563 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4564 {
4565 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4566 LLVMValueRef result;
4567
4568 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4569
4570 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4571 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4572
4573 return result;
4574 }
4575
4576 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4577 unsigned descriptor_set,
4578 unsigned base_index,
4579 unsigned constant_index,
4580 LLVMValueRef index,
4581 enum ac_descriptor_type desc_type,
4582 bool image, bool write)
4583 {
4584 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4585 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4586 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4587 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4588 unsigned offset = binding->offset;
4589 unsigned stride = binding->size;
4590 unsigned type_size;
4591 LLVMBuilderRef builder = ctx->builder;
4592 LLVMTypeRef type;
4593
4594 assert(base_index < layout->binding_count);
4595
4596 switch (desc_type) {
4597 case AC_DESC_IMAGE:
4598 type = ctx->ac.v8i32;
4599 type_size = 32;
4600 break;
4601 case AC_DESC_FMASK:
4602 type = ctx->ac.v8i32;
4603 offset += 32;
4604 type_size = 32;
4605 break;
4606 case AC_DESC_SAMPLER:
4607 type = ctx->ac.v4i32;
4608 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4609 offset += 64;
4610
4611 type_size = 16;
4612 break;
4613 case AC_DESC_BUFFER:
4614 type = ctx->ac.v4i32;
4615 type_size = 16;
4616 break;
4617 default:
4618 unreachable("invalid desc_type\n");
4619 }
4620
4621 offset += constant_index * stride;
4622
4623 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4624 (!index || binding->immutable_samplers_equal)) {
4625 if (binding->immutable_samplers_equal)
4626 constant_index = 0;
4627
4628 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4629
4630 LLVMValueRef constants[] = {
4631 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4632 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4633 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4634 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4635 };
4636 return ac_build_gather_values(&ctx->ac, constants, 4);
4637 }
4638
4639 assert(stride % type_size == 0);
4640
4641 if (!index)
4642 index = ctx->ac.i32_0;
4643
4644 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4645
4646 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4647 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4648
4649 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4650 }
4651
4652 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4653 const nir_deref_var *deref,
4654 enum ac_descriptor_type desc_type,
4655 const nir_tex_instr *tex_instr,
4656 bool image, bool write)
4657 {
4658 LLVMValueRef index = NULL;
4659 unsigned constant_index = 0;
4660 unsigned descriptor_set;
4661 unsigned base_index;
4662
4663 if (!deref) {
4664 assert(tex_instr && !image);
4665 descriptor_set = 0;
4666 base_index = tex_instr->sampler_index;
4667 } else {
4668 const nir_deref *tail = &deref->deref;
4669 while (tail->child) {
4670 const nir_deref_array *child = nir_deref_as_array(tail->child);
4671 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4672
4673 if (!array_size)
4674 array_size = 1;
4675
4676 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4677
4678 if (child->deref_array_type == nir_deref_array_type_indirect) {
4679 LLVMValueRef indirect = get_src(ctx, child->indirect);
4680
4681 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4682 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4683
4684 if (!index)
4685 index = indirect;
4686 else
4687 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4688 }
4689
4690 constant_index += child->base_offset * array_size;
4691
4692 tail = &child->deref;
4693 }
4694 descriptor_set = deref->var->data.descriptor_set;
4695 base_index = deref->var->data.binding;
4696 }
4697
4698 return ctx->abi->load_sampler_desc(ctx->abi,
4699 descriptor_set,
4700 base_index,
4701 constant_index, index,
4702 desc_type, image, write);
4703 }
4704
4705 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4706 struct ac_image_args *args,
4707 const nir_tex_instr *instr,
4708 nir_texop op,
4709 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4710 LLVMValueRef *param, unsigned count,
4711 unsigned dmask)
4712 {
4713 unsigned is_rect = 0;
4714 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4715
4716 if (op == nir_texop_lod)
4717 da = false;
4718 /* Pad to power of two vector */
4719 while (count < util_next_power_of_two(count))
4720 param[count++] = LLVMGetUndef(ctx->i32);
4721
4722 if (count > 1)
4723 args->addr = ac_build_gather_values(ctx, param, count);
4724 else
4725 args->addr = param[0];
4726
4727 args->resource = res_ptr;
4728 args->sampler = samp_ptr;
4729
4730 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4731 args->addr = param[0];
4732 return;
4733 }
4734
4735 args->dmask = dmask;
4736 args->unorm = is_rect;
4737 args->da = da;
4738 }
4739
4740 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4741 *
4742 * SI-CI:
4743 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4744 * filtering manually. The driver sets img7 to a mask clearing
4745 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4746 * s_and_b32 samp0, samp0, img7
4747 *
4748 * VI:
4749 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4750 */
4751 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4752 LLVMValueRef res, LLVMValueRef samp)
4753 {
4754 LLVMBuilderRef builder = ctx->ac.builder;
4755 LLVMValueRef img7, samp0;
4756
4757 if (ctx->ac.chip_class >= VI)
4758 return samp;
4759
4760 img7 = LLVMBuildExtractElement(builder, res,
4761 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4762 samp0 = LLVMBuildExtractElement(builder, samp,
4763 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4764 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4765 return LLVMBuildInsertElement(builder, samp, samp0,
4766 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4767 }
4768
4769 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4770 nir_tex_instr *instr,
4771 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4772 LLVMValueRef *fmask_ptr)
4773 {
4774 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4775 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4776 else
4777 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4778 if (samp_ptr) {
4779 if (instr->sampler)
4780 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4781 else
4782 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4783 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4784 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4785 }
4786 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4787 instr->op == nir_texop_samples_identical))
4788 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4789 }
4790
4791 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4792 LLVMValueRef coord)
4793 {
4794 coord = ac_to_float(ctx, coord);
4795 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4796 coord = ac_to_integer(ctx, coord);
4797 return coord;
4798 }
4799
4800 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4801 {
4802 LLVMValueRef result = NULL;
4803 struct ac_image_args args = { 0 };
4804 unsigned dmask = 0xf;
4805 LLVMValueRef address[16];
4806 LLVMValueRef coords[5];
4807 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4808 LLVMValueRef bias = NULL, offsets = NULL;
4809 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4810 LLVMValueRef ddx = NULL, ddy = NULL;
4811 LLVMValueRef derivs[6];
4812 unsigned chan, count = 0;
4813 unsigned const_src = 0, num_deriv_comp = 0;
4814 bool lod_is_zero = false;
4815
4816 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4817
4818 for (unsigned i = 0; i < instr->num_srcs; i++) {
4819 switch (instr->src[i].src_type) {
4820 case nir_tex_src_coord:
4821 coord = get_src(ctx, instr->src[i].src);
4822 break;
4823 case nir_tex_src_projector:
4824 break;
4825 case nir_tex_src_comparator:
4826 comparator = get_src(ctx, instr->src[i].src);
4827 break;
4828 case nir_tex_src_offset:
4829 offsets = get_src(ctx, instr->src[i].src);
4830 const_src = i;
4831 break;
4832 case nir_tex_src_bias:
4833 bias = get_src(ctx, instr->src[i].src);
4834 break;
4835 case nir_tex_src_lod: {
4836 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4837
4838 if (val && val->i32[0] == 0)
4839 lod_is_zero = true;
4840 lod = get_src(ctx, instr->src[i].src);
4841 break;
4842 }
4843 case nir_tex_src_ms_index:
4844 sample_index = get_src(ctx, instr->src[i].src);
4845 break;
4846 case nir_tex_src_ms_mcs:
4847 break;
4848 case nir_tex_src_ddx:
4849 ddx = get_src(ctx, instr->src[i].src);
4850 num_deriv_comp = instr->src[i].src.ssa->num_components;
4851 break;
4852 case nir_tex_src_ddy:
4853 ddy = get_src(ctx, instr->src[i].src);
4854 break;
4855 case nir_tex_src_texture_offset:
4856 case nir_tex_src_sampler_offset:
4857 case nir_tex_src_plane:
4858 default:
4859 break;
4860 }
4861 }
4862
4863 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4864 result = get_buffer_size(ctx, res_ptr, true);
4865 goto write_result;
4866 }
4867
4868 if (instr->op == nir_texop_texture_samples) {
4869 LLVMValueRef res, samples, is_msaa;
4870 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4871 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4872 LLVMConstInt(ctx->ac.i32, 3, false), "");
4873 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4874 LLVMConstInt(ctx->ac.i32, 28, false), "");
4875 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4876 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4877 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4878 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4879
4880 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4881 LLVMConstInt(ctx->ac.i32, 16, false), "");
4882 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4883 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4884 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4885 samples, "");
4886 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4887 ctx->ac.i32_1, "");
4888 result = samples;
4889 goto write_result;
4890 }
4891
4892 if (coord)
4893 for (chan = 0; chan < instr->coord_components; chan++)
4894 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4895
4896 if (offsets && instr->op != nir_texop_txf) {
4897 LLVMValueRef offset[3], pack;
4898 for (chan = 0; chan < 3; ++chan)
4899 offset[chan] = ctx->ac.i32_0;
4900
4901 args.offset = true;
4902 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4903 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4904 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4905 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4906 if (chan)
4907 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4908 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4909 }
4910 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4911 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4912 address[count++] = pack;
4913
4914 }
4915 /* pack LOD bias value */
4916 if (instr->op == nir_texop_txb && bias) {
4917 address[count++] = bias;
4918 }
4919
4920 /* Pack depth comparison value */
4921 if (instr->is_shadow && comparator) {
4922 LLVMValueRef z = ac_to_float(&ctx->ac,
4923 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4924
4925 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4926 * so the depth comparison value isn't clamped for Z16 and
4927 * Z24 anymore. Do it manually here.
4928 *
4929 * It's unnecessary if the original texture format was
4930 * Z32_FLOAT, but we don't know that here.
4931 */
4932 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4933 z = ac_build_clamp(&ctx->ac, z);
4934
4935 address[count++] = z;
4936 }
4937
4938 /* pack derivatives */
4939 if (ddx || ddy) {
4940 int num_src_deriv_channels, num_dest_deriv_channels;
4941 switch (instr->sampler_dim) {
4942 case GLSL_SAMPLER_DIM_3D:
4943 case GLSL_SAMPLER_DIM_CUBE:
4944 num_deriv_comp = 3;
4945 num_src_deriv_channels = 3;
4946 num_dest_deriv_channels = 3;
4947 break;
4948 case GLSL_SAMPLER_DIM_2D:
4949 default:
4950 num_src_deriv_channels = 2;
4951 num_dest_deriv_channels = 2;
4952 num_deriv_comp = 2;
4953 break;
4954 case GLSL_SAMPLER_DIM_1D:
4955 num_src_deriv_channels = 1;
4956 if (ctx->ac.chip_class >= GFX9) {
4957 num_dest_deriv_channels = 2;
4958 num_deriv_comp = 2;
4959 } else {
4960 num_dest_deriv_channels = 1;
4961 num_deriv_comp = 1;
4962 }
4963 break;
4964 }
4965
4966 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4967 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4968 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4969 }
4970 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4971 derivs[i] = ctx->ac.f32_0;
4972 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4973 }
4974 }
4975
4976 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4977 for (chan = 0; chan < instr->coord_components; chan++)
4978 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4979 if (instr->coord_components == 3)
4980 coords[3] = LLVMGetUndef(ctx->ac.f32);
4981 ac_prepare_cube_coords(&ctx->ac,
4982 instr->op == nir_texop_txd, instr->is_array,
4983 instr->op == nir_texop_lod, coords, derivs);
4984 if (num_deriv_comp)
4985 num_deriv_comp--;
4986 }
4987
4988 if (ddx || ddy) {
4989 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4990 address[count++] = derivs[i];
4991 }
4992
4993 /* Pack texture coordinates */
4994 if (coord) {
4995 address[count++] = coords[0];
4996 if (instr->coord_components > 1) {
4997 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4998 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4999 }
5000 address[count++] = coords[1];
5001 }
5002 if (instr->coord_components > 2) {
5003 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5004 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5005 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5006 instr->op != nir_texop_txf) {
5007 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5008 }
5009 address[count++] = coords[2];
5010 }
5011
5012 if (ctx->ac.chip_class >= GFX9) {
5013 LLVMValueRef filler;
5014 if (instr->op == nir_texop_txf)
5015 filler = ctx->ac.i32_0;
5016 else
5017 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5018
5019 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5020 /* No nir_texop_lod, because it does not take a slice
5021 * even with array textures. */
5022 if (instr->is_array && instr->op != nir_texop_lod ) {
5023 address[count] = address[count - 1];
5024 address[count - 1] = filler;
5025 count++;
5026 } else
5027 address[count++] = filler;
5028 }
5029 }
5030 }
5031
5032 /* Pack LOD */
5033 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5034 instr->op == nir_texop_txf)) {
5035 address[count++] = lod;
5036 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5037 address[count++] = sample_index;
5038 } else if(instr->op == nir_texop_txs) {
5039 count = 0;
5040 if (lod)
5041 address[count++] = lod;
5042 else
5043 address[count++] = ctx->ac.i32_0;
5044 }
5045
5046 for (chan = 0; chan < count; chan++) {
5047 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5048 address[chan], ctx->ac.i32, "");
5049 }
5050
5051 if (instr->op == nir_texop_samples_identical) {
5052 LLVMValueRef txf_address[4];
5053 struct ac_image_args txf_args = { 0 };
5054 unsigned txf_count = count;
5055 memcpy(txf_address, address, sizeof(txf_address));
5056
5057 if (!instr->is_array)
5058 txf_address[2] = ctx->ac.i32_0;
5059 txf_address[3] = ctx->ac.i32_0;
5060
5061 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5062 fmask_ptr, NULL,
5063 txf_address, txf_count, 0xf);
5064
5065 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5066
5067 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5068 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5069 goto write_result;
5070 }
5071
5072 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5073 instr->op != nir_texop_txs) {
5074 unsigned sample_chan = instr->is_array ? 3 : 2;
5075 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5076 address[0],
5077 address[1],
5078 instr->is_array ? address[2] : NULL,
5079 address[sample_chan],
5080 fmask_ptr);
5081 }
5082
5083 if (offsets && instr->op == nir_texop_txf) {
5084 nir_const_value *const_offset =
5085 nir_src_as_const_value(instr->src[const_src].src);
5086 int num_offsets = instr->src[const_src].src.ssa->num_components;
5087 assert(const_offset);
5088 num_offsets = MIN2(num_offsets, instr->coord_components);
5089 if (num_offsets > 2)
5090 address[2] = LLVMBuildAdd(ctx->ac.builder,
5091 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5092 if (num_offsets > 1)
5093 address[1] = LLVMBuildAdd(ctx->ac.builder,
5094 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5095 address[0] = LLVMBuildAdd(ctx->ac.builder,
5096 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5097
5098 }
5099
5100 /* TODO TG4 support */
5101 if (instr->op == nir_texop_tg4) {
5102 if (instr->is_shadow)
5103 dmask = 1;
5104 else
5105 dmask = 1 << instr->component;
5106 }
5107 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5108 res_ptr, samp_ptr, address, count, dmask);
5109
5110 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5111
5112 if (instr->op == nir_texop_query_levels)
5113 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5114 else if (instr->is_shadow && instr->is_new_style_shadow &&
5115 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5116 instr->op != nir_texop_tg4)
5117 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5118 else if (instr->op == nir_texop_txs &&
5119 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5120 instr->is_array) {
5121 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5122 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5123 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5124 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5125 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5126 } else if (ctx->ac.chip_class >= GFX9 &&
5127 instr->op == nir_texop_txs &&
5128 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5129 instr->is_array) {
5130 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5131 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5132 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5133 ctx->ac.i32_1, "");
5134 } else if (instr->dest.ssa.num_components != 4)
5135 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5136
5137 write_result:
5138 if (result) {
5139 assert(instr->dest.is_ssa);
5140 result = ac_to_integer(&ctx->ac, result);
5141 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5142 }
5143 }
5144
5145
5146 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5147 {
5148 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5149 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5150
5151 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5152 _mesa_hash_table_insert(ctx->phis, instr, result);
5153 }
5154
5155 static void visit_post_phi(struct ac_nir_context *ctx,
5156 nir_phi_instr *instr,
5157 LLVMValueRef llvm_phi)
5158 {
5159 nir_foreach_phi_src(src, instr) {
5160 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5161 LLVMValueRef llvm_src = get_src(ctx, src->src);
5162
5163 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5164 }
5165 }
5166
5167 static void phi_post_pass(struct ac_nir_context *ctx)
5168 {
5169 struct hash_entry *entry;
5170 hash_table_foreach(ctx->phis, entry) {
5171 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5172 (LLVMValueRef)entry->data);
5173 }
5174 }
5175
5176
5177 static void visit_ssa_undef(struct ac_nir_context *ctx,
5178 const nir_ssa_undef_instr *instr)
5179 {
5180 unsigned num_components = instr->def.num_components;
5181 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5182 LLVMValueRef undef;
5183
5184 if (num_components == 1)
5185 undef = LLVMGetUndef(type);
5186 else {
5187 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5188 }
5189 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5190 }
5191
5192 static void visit_jump(struct ac_nir_context *ctx,
5193 const nir_jump_instr *instr)
5194 {
5195 switch (instr->type) {
5196 case nir_jump_break:
5197 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5198 LLVMClearInsertionPosition(ctx->ac.builder);
5199 break;
5200 case nir_jump_continue:
5201 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5202 LLVMClearInsertionPosition(ctx->ac.builder);
5203 break;
5204 default:
5205 fprintf(stderr, "Unknown NIR jump instr: ");
5206 nir_print_instr(&instr->instr, stderr);
5207 fprintf(stderr, "\n");
5208 abort();
5209 }
5210 }
5211
5212 static void visit_cf_list(struct ac_nir_context *ctx,
5213 struct exec_list *list);
5214
5215 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5216 {
5217 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5218 nir_foreach_instr(instr, block)
5219 {
5220 switch (instr->type) {
5221 case nir_instr_type_alu:
5222 visit_alu(ctx, nir_instr_as_alu(instr));
5223 break;
5224 case nir_instr_type_load_const:
5225 visit_load_const(ctx, nir_instr_as_load_const(instr));
5226 break;
5227 case nir_instr_type_intrinsic:
5228 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5229 break;
5230 case nir_instr_type_tex:
5231 visit_tex(ctx, nir_instr_as_tex(instr));
5232 break;
5233 case nir_instr_type_phi:
5234 visit_phi(ctx, nir_instr_as_phi(instr));
5235 break;
5236 case nir_instr_type_ssa_undef:
5237 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5238 break;
5239 case nir_instr_type_jump:
5240 visit_jump(ctx, nir_instr_as_jump(instr));
5241 break;
5242 default:
5243 fprintf(stderr, "Unknown NIR instr type: ");
5244 nir_print_instr(instr, stderr);
5245 fprintf(stderr, "\n");
5246 abort();
5247 }
5248 }
5249
5250 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5251 }
5252
5253 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5254 {
5255 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5256
5257 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5258 LLVMBasicBlockRef merge_block =
5259 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5260 LLVMBasicBlockRef if_block =
5261 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5262 LLVMBasicBlockRef else_block = merge_block;
5263 if (!exec_list_is_empty(&if_stmt->else_list))
5264 else_block = LLVMAppendBasicBlockInContext(
5265 ctx->ac.context, fn, "");
5266
5267 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5268 ctx->ac.i32_0, "");
5269 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5270
5271 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5272 visit_cf_list(ctx, &if_stmt->then_list);
5273 if (LLVMGetInsertBlock(ctx->ac.builder))
5274 LLVMBuildBr(ctx->ac.builder, merge_block);
5275
5276 if (!exec_list_is_empty(&if_stmt->else_list)) {
5277 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5278 visit_cf_list(ctx, &if_stmt->else_list);
5279 if (LLVMGetInsertBlock(ctx->ac.builder))
5280 LLVMBuildBr(ctx->ac.builder, merge_block);
5281 }
5282
5283 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5284 }
5285
5286 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5287 {
5288 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5289 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5290 LLVMBasicBlockRef break_parent = ctx->break_block;
5291
5292 ctx->continue_block =
5293 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5294 ctx->break_block =
5295 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5296
5297 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5298 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5299 visit_cf_list(ctx, &loop->body);
5300
5301 if (LLVMGetInsertBlock(ctx->ac.builder))
5302 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5303 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5304
5305 ctx->continue_block = continue_parent;
5306 ctx->break_block = break_parent;
5307 }
5308
5309 static void visit_cf_list(struct ac_nir_context *ctx,
5310 struct exec_list *list)
5311 {
5312 foreach_list_typed(nir_cf_node, node, node, list)
5313 {
5314 switch (node->type) {
5315 case nir_cf_node_block:
5316 visit_block(ctx, nir_cf_node_as_block(node));
5317 break;
5318
5319 case nir_cf_node_if:
5320 visit_if(ctx, nir_cf_node_as_if(node));
5321 break;
5322
5323 case nir_cf_node_loop:
5324 visit_loop(ctx, nir_cf_node_as_loop(node));
5325 break;
5326
5327 default:
5328 assert(0);
5329 }
5330 }
5331 }
5332
5333 static void
5334 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5335 struct nir_variable *variable)
5336 {
5337 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5338 LLVMValueRef t_offset;
5339 LLVMValueRef t_list;
5340 LLVMValueRef input;
5341 LLVMValueRef buffer_index;
5342 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5343 int idx = variable->data.location;
5344 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5345
5346 variable->data.driver_location = idx * 4;
5347
5348 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5349 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5350 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5351 ctx->abi.start_instance, "");
5352 if (ctx->options->key.vs.as_ls) {
5353 ctx->shader_info->vs.vgpr_comp_cnt =
5354 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5355 } else {
5356 ctx->shader_info->vs.vgpr_comp_cnt =
5357 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5358 }
5359 } else
5360 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5361 ctx->abi.base_vertex, "");
5362 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5363
5364 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5365
5366 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5367 buffer_index,
5368 ctx->ac.i32_0,
5369 4, true);
5370
5371 for (unsigned chan = 0; chan < 4; chan++) {
5372 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5373 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5374 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5375 input, llvm_chan, ""));
5376 }
5377 }
5378 }
5379
5380 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5381 unsigned attr,
5382 LLVMValueRef interp_param,
5383 LLVMValueRef prim_mask,
5384 LLVMValueRef result[4])
5385 {
5386 LLVMValueRef attr_number;
5387 unsigned chan;
5388 LLVMValueRef i, j;
5389 bool interp = interp_param != NULL;
5390
5391 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5392
5393 /* fs.constant returns the param from the middle vertex, so it's not
5394 * really useful for flat shading. It's meant to be used for custom
5395 * interpolation (but the intrinsic can't fetch from the other two
5396 * vertices).
5397 *
5398 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5399 * to do the right thing. The only reason we use fs.constant is that
5400 * fs.interp cannot be used on integers, because they can be equal
5401 * to NaN.
5402 */
5403 if (interp) {
5404 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5405 ctx->ac.v2f32, "");
5406
5407 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5408 ctx->ac.i32_0, "");
5409 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5410 ctx->ac.i32_1, "");
5411 }
5412
5413 for (chan = 0; chan < 4; chan++) {
5414 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5415
5416 if (interp) {
5417 result[chan] = ac_build_fs_interp(&ctx->ac,
5418 llvm_chan,
5419 attr_number,
5420 prim_mask, i, j);
5421 } else {
5422 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5423 LLVMConstInt(ctx->ac.i32, 2, false),
5424 llvm_chan,
5425 attr_number,
5426 prim_mask);
5427 }
5428 }
5429 }
5430
5431 static void
5432 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5433 struct nir_variable *variable)
5434 {
5435 int idx = variable->data.location;
5436 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5437 LLVMValueRef interp;
5438
5439 variable->data.driver_location = idx * 4;
5440 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5441
5442 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5443 unsigned interp_type;
5444 if (variable->data.sample) {
5445 interp_type = INTERP_SAMPLE;
5446 ctx->shader_info->info.ps.force_persample = true;
5447 } else if (variable->data.centroid)
5448 interp_type = INTERP_CENTROID;
5449 else
5450 interp_type = INTERP_CENTER;
5451
5452 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5453 } else
5454 interp = NULL;
5455
5456 for (unsigned i = 0; i < attrib_count; ++i)
5457 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5458
5459 }
5460
5461 static void
5462 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5463 struct nir_shader *nir) {
5464 nir_foreach_variable(variable, &nir->inputs)
5465 handle_vs_input_decl(ctx, variable);
5466 }
5467
5468 static void
5469 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5470 struct nir_shader *nir)
5471 {
5472 if (!ctx->options->key.fs.multisample)
5473 return;
5474
5475 bool uses_center = false;
5476 bool uses_centroid = false;
5477 nir_foreach_variable(variable, &nir->inputs) {
5478 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5479 variable->data.sample)
5480 continue;
5481
5482 if (variable->data.centroid)
5483 uses_centroid = true;
5484 else
5485 uses_center = true;
5486 }
5487
5488 if (uses_center && uses_centroid) {
5489 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5490 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5491 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5492 }
5493 }
5494
5495 static void
5496 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5497 struct nir_shader *nir)
5498 {
5499 prepare_interp_optimize(ctx, nir);
5500
5501 nir_foreach_variable(variable, &nir->inputs)
5502 handle_fs_input_decl(ctx, variable);
5503
5504 unsigned index = 0;
5505
5506 if (ctx->shader_info->info.ps.uses_input_attachments ||
5507 ctx->shader_info->info.needs_multiview_view_index)
5508 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5509
5510 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5511 LLVMValueRef interp_param;
5512 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5513
5514 if (!(ctx->input_mask & (1ull << i)))
5515 continue;
5516
5517 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5518 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5519 interp_param = *inputs;
5520 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5521 inputs);
5522
5523 if (!interp_param)
5524 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5525 ++index;
5526 } else if (i == VARYING_SLOT_POS) {
5527 for(int i = 0; i < 3; ++i)
5528 inputs[i] = ctx->abi.frag_pos[i];
5529
5530 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5531 ctx->abi.frag_pos[3]);
5532 }
5533 }
5534 ctx->shader_info->fs.num_interp = index;
5535 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5536 ctx->shader_info->fs.has_pcoord = true;
5537 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5538 ctx->shader_info->fs.prim_id_input = true;
5539 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5540 ctx->shader_info->fs.layer_input = true;
5541 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5542
5543 if (ctx->shader_info->info.needs_multiview_view_index)
5544 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5545 }
5546
5547 static LLVMValueRef
5548 ac_build_alloca(struct ac_llvm_context *ac,
5549 LLVMTypeRef type,
5550 const char *name)
5551 {
5552 LLVMBuilderRef builder = ac->builder;
5553 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5554 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5555 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5556 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5557 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5558 LLVMValueRef res;
5559
5560 if (first_instr) {
5561 LLVMPositionBuilderBefore(first_builder, first_instr);
5562 } else {
5563 LLVMPositionBuilderAtEnd(first_builder, first_block);
5564 }
5565
5566 res = LLVMBuildAlloca(first_builder, type, name);
5567 LLVMBuildStore(builder, LLVMConstNull(type), res);
5568
5569 LLVMDisposeBuilder(first_builder);
5570
5571 return res;
5572 }
5573
5574 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5575 LLVMTypeRef type,
5576 const char *name)
5577 {
5578 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5579 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5580 return ptr;
5581 }
5582
5583 static void
5584 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5585 struct nir_variable *variable,
5586 struct nir_shader *shader,
5587 gl_shader_stage stage)
5588 {
5589 int idx = variable->data.location + variable->data.index;
5590 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5591 uint64_t mask_attribs;
5592
5593 variable->data.driver_location = idx * 4;
5594
5595 /* tess ctrl has it's own load/store paths for outputs */
5596 if (stage == MESA_SHADER_TESS_CTRL)
5597 return;
5598
5599 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5600 if (stage == MESA_SHADER_VERTEX ||
5601 stage == MESA_SHADER_TESS_EVAL ||
5602 stage == MESA_SHADER_GEOMETRY) {
5603 if (idx == VARYING_SLOT_CLIP_DIST0) {
5604 int length = shader->info.clip_distance_array_size +
5605 shader->info.cull_distance_array_size;
5606 if (stage == MESA_SHADER_VERTEX) {
5607 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5608 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5609 }
5610 if (stage == MESA_SHADER_TESS_EVAL) {
5611 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5612 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5613 }
5614
5615 if (length > 4)
5616 attrib_count = 2;
5617 else
5618 attrib_count = 1;
5619 mask_attribs = 1ull << idx;
5620 }
5621 }
5622
5623 ctx->output_mask |= mask_attribs;
5624 }
5625
5626 static void
5627 handle_shader_output_decl(struct ac_nir_context *ctx,
5628 struct nir_shader *nir,
5629 struct nir_variable *variable)
5630 {
5631 unsigned output_loc = variable->data.driver_location / 4;
5632 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5633
5634 /* tess ctrl has it's own load/store paths for outputs */
5635 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5636 return;
5637
5638 if (ctx->stage == MESA_SHADER_VERTEX ||
5639 ctx->stage == MESA_SHADER_TESS_EVAL ||
5640 ctx->stage == MESA_SHADER_GEOMETRY) {
5641 int idx = variable->data.location + variable->data.index;
5642 if (idx == VARYING_SLOT_CLIP_DIST0) {
5643 int length = nir->info.clip_distance_array_size +
5644 nir->info.cull_distance_array_size;
5645
5646 if (length > 4)
5647 attrib_count = 2;
5648 else
5649 attrib_count = 1;
5650 }
5651 }
5652
5653 for (unsigned i = 0; i < attrib_count; ++i) {
5654 for (unsigned chan = 0; chan < 4; chan++) {
5655 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5656 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5657 }
5658 }
5659 }
5660
5661 static LLVMTypeRef
5662 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5663 enum glsl_base_type type)
5664 {
5665 switch (type) {
5666 case GLSL_TYPE_INT:
5667 case GLSL_TYPE_UINT:
5668 case GLSL_TYPE_BOOL:
5669 case GLSL_TYPE_SUBROUTINE:
5670 return ctx->ac.i32;
5671 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5672 return ctx->ac.f32;
5673 case GLSL_TYPE_INT64:
5674 case GLSL_TYPE_UINT64:
5675 return ctx->ac.i64;
5676 case GLSL_TYPE_DOUBLE:
5677 return ctx->ac.f64;
5678 default:
5679 unreachable("unknown GLSL type");
5680 }
5681 }
5682
5683 static LLVMTypeRef
5684 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5685 const struct glsl_type *type)
5686 {
5687 if (glsl_type_is_scalar(type)) {
5688 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5689 }
5690
5691 if (glsl_type_is_vector(type)) {
5692 return LLVMVectorType(
5693 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5694 glsl_get_vector_elements(type));
5695 }
5696
5697 if (glsl_type_is_matrix(type)) {
5698 return LLVMArrayType(
5699 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5700 glsl_get_matrix_columns(type));
5701 }
5702
5703 if (glsl_type_is_array(type)) {
5704 return LLVMArrayType(
5705 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5706 glsl_get_length(type));
5707 }
5708
5709 assert(glsl_type_is_struct(type));
5710
5711 LLVMTypeRef member_types[glsl_get_length(type)];
5712
5713 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5714 member_types[i] =
5715 glsl_to_llvm_type(ctx,
5716 glsl_get_struct_field(type, i));
5717 }
5718
5719 return LLVMStructTypeInContext(ctx->context, member_types,
5720 glsl_get_length(type), false);
5721 }
5722
5723 static void
5724 setup_locals(struct ac_nir_context *ctx,
5725 struct nir_function *func)
5726 {
5727 int i, j;
5728 ctx->num_locals = 0;
5729 nir_foreach_variable(variable, &func->impl->locals) {
5730 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5731 variable->data.driver_location = ctx->num_locals * 4;
5732 variable->data.location_frac = 0;
5733 ctx->num_locals += attrib_count;
5734 }
5735 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5736 if (!ctx->locals)
5737 return;
5738
5739 for (i = 0; i < ctx->num_locals; i++) {
5740 for (j = 0; j < 4; j++) {
5741 ctx->locals[i * 4 + j] =
5742 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5743 }
5744 }
5745 }
5746
5747 static void
5748 setup_shared(struct ac_nir_context *ctx,
5749 struct nir_shader *nir)
5750 {
5751 nir_foreach_variable(variable, &nir->shared) {
5752 LLVMValueRef shared =
5753 LLVMAddGlobalInAddressSpace(
5754 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5755 variable->name ? variable->name : "",
5756 AC_LOCAL_ADDR_SPACE);
5757 _mesa_hash_table_insert(ctx->vars, variable, shared);
5758 }
5759 }
5760
5761 static LLVMValueRef
5762 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5763 {
5764 v = ac_to_float(ctx, v);
5765 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5766 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5767 }
5768
5769
5770 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5771 LLVMValueRef src0, LLVMValueRef src1)
5772 {
5773 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5774 LLVMValueRef comp[2];
5775
5776 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5777 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5778 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5779 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5780 }
5781
5782 /* Initialize arguments for the shader export intrinsic */
5783 static void
5784 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5785 LLVMValueRef *values,
5786 unsigned target,
5787 struct ac_export_args *args)
5788 {
5789 /* Default is 0xf. Adjusted below depending on the format. */
5790 args->enabled_channels = 0xf;
5791
5792 /* Specify whether the EXEC mask represents the valid mask */
5793 args->valid_mask = 0;
5794
5795 /* Specify whether this is the last export */
5796 args->done = 0;
5797
5798 /* Specify the target we are exporting */
5799 args->target = target;
5800
5801 args->compr = false;
5802 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5803 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5804 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5805 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5806
5807 if (!values)
5808 return;
5809
5810 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5811 LLVMValueRef val[4];
5812 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5813 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5814 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5815 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5816
5817 switch(col_format) {
5818 case V_028714_SPI_SHADER_ZERO:
5819 args->enabled_channels = 0; /* writemask */
5820 args->target = V_008DFC_SQ_EXP_NULL;
5821 break;
5822
5823 case V_028714_SPI_SHADER_32_R:
5824 args->enabled_channels = 1;
5825 args->out[0] = values[0];
5826 break;
5827
5828 case V_028714_SPI_SHADER_32_GR:
5829 args->enabled_channels = 0x3;
5830 args->out[0] = values[0];
5831 args->out[1] = values[1];
5832 break;
5833
5834 case V_028714_SPI_SHADER_32_AR:
5835 args->enabled_channels = 0x9;
5836 args->out[0] = values[0];
5837 args->out[3] = values[3];
5838 break;
5839
5840 case V_028714_SPI_SHADER_FP16_ABGR:
5841 args->compr = 1;
5842
5843 for (unsigned chan = 0; chan < 2; chan++) {
5844 LLVMValueRef pack_args[2] = {
5845 values[2 * chan],
5846 values[2 * chan + 1]
5847 };
5848 LLVMValueRef packed;
5849
5850 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5851 args->out[chan] = packed;
5852 }
5853 break;
5854
5855 case V_028714_SPI_SHADER_UNORM16_ABGR:
5856 for (unsigned chan = 0; chan < 4; chan++) {
5857 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5858 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5859 LLVMConstReal(ctx->ac.f32, 65535), "");
5860 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5861 LLVMConstReal(ctx->ac.f32, 0.5), "");
5862 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5863 ctx->ac.i32, "");
5864 }
5865
5866 args->compr = 1;
5867 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5868 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5869 break;
5870
5871 case V_028714_SPI_SHADER_SNORM16_ABGR:
5872 for (unsigned chan = 0; chan < 4; chan++) {
5873 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5874 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5875 LLVMConstReal(ctx->ac.f32, 32767), "");
5876
5877 /* If positive, add 0.5, else add -0.5. */
5878 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5879 LLVMBuildSelect(ctx->builder,
5880 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5881 val[chan], ctx->ac.f32_0, ""),
5882 LLVMConstReal(ctx->ac.f32, 0.5),
5883 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5884 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5885 }
5886
5887 args->compr = 1;
5888 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5889 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5890 break;
5891
5892 case V_028714_SPI_SHADER_UINT16_ABGR: {
5893 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5894 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5895 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5896
5897 for (unsigned chan = 0; chan < 4; chan++) {
5898 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5899 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5900 }
5901
5902 args->compr = 1;
5903 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5904 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5905 break;
5906 }
5907
5908 case V_028714_SPI_SHADER_SINT16_ABGR: {
5909 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5910 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5911 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5912 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5913 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5914 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5915
5916 /* Clamp. */
5917 for (unsigned chan = 0; chan < 4; chan++) {
5918 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5919 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5920 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5921 }
5922
5923 args->compr = 1;
5924 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5925 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5926 break;
5927 }
5928
5929 default:
5930 case V_028714_SPI_SHADER_32_ABGR:
5931 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5932 break;
5933 }
5934 } else
5935 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5936
5937 for (unsigned i = 0; i < 4; ++i)
5938 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5939 }
5940
5941 static void
5942 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5943 bool export_prim_id,
5944 struct ac_vs_output_info *outinfo)
5945 {
5946 uint32_t param_count = 0;
5947 unsigned target;
5948 unsigned pos_idx, num_pos_exports = 0;
5949 struct ac_export_args args, pos_args[4] = {};
5950 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5951 int i;
5952
5953 if (ctx->options->key.has_multiview_view_index) {
5954 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5955 if(!*tmp_out) {
5956 for(unsigned i = 0; i < 4; ++i)
5957 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5958 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5959 }
5960
5961 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5962 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5963 }
5964
5965 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5966 sizeof(outinfo->vs_output_param_offset));
5967
5968 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5969 LLVMValueRef slots[8];
5970 unsigned j;
5971
5972 if (outinfo->cull_dist_mask)
5973 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5974
5975 i = VARYING_SLOT_CLIP_DIST0;
5976 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5977 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5978 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5979
5980 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5981 slots[i] = LLVMGetUndef(ctx->ac.f32);
5982
5983 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5984 target = V_008DFC_SQ_EXP_POS + 3;
5985 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5986 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5987 &args, sizeof(args));
5988 }
5989
5990 target = V_008DFC_SQ_EXP_POS + 2;
5991 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5992 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5993 &args, sizeof(args));
5994
5995 }
5996
5997 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5998 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5999 for (unsigned j = 0; j < 4; j++)
6000 pos_values[j] = LLVMBuildLoad(ctx->builder,
6001 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
6002 }
6003 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6004
6005 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6006 outinfo->writes_pointsize = true;
6007 psize_value = LLVMBuildLoad(ctx->builder,
6008 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
6009 }
6010
6011 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6012 outinfo->writes_layer = true;
6013 layer_value = LLVMBuildLoad(ctx->builder,
6014 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
6015 }
6016
6017 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6018 outinfo->writes_viewport_index = true;
6019 viewport_index_value = LLVMBuildLoad(ctx->builder,
6020 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
6021 }
6022
6023 if (outinfo->writes_pointsize ||
6024 outinfo->writes_layer ||
6025 outinfo->writes_viewport_index) {
6026 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6027 (outinfo->writes_layer == true ? 4 : 0));
6028 pos_args[1].valid_mask = 0;
6029 pos_args[1].done = 0;
6030 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6031 pos_args[1].compr = 0;
6032 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6033 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6034 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6035 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6036
6037 if (outinfo->writes_pointsize == true)
6038 pos_args[1].out[0] = psize_value;
6039 if (outinfo->writes_layer == true)
6040 pos_args[1].out[2] = layer_value;
6041 if (outinfo->writes_viewport_index == true) {
6042 if (ctx->options->chip_class >= GFX9) {
6043 /* GFX9 has the layer in out.z[10:0] and the viewport
6044 * index in out.z[19:16].
6045 */
6046 LLVMValueRef v = viewport_index_value;
6047 v = ac_to_integer(&ctx->ac, v);
6048 v = LLVMBuildShl(ctx->builder, v,
6049 LLVMConstInt(ctx->ac.i32, 16, false),
6050 "");
6051 v = LLVMBuildOr(ctx->builder, v,
6052 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6053
6054 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6055 pos_args[1].enabled_channels |= 1 << 2;
6056 } else {
6057 pos_args[1].out[3] = viewport_index_value;
6058 pos_args[1].enabled_channels |= 1 << 3;
6059 }
6060 }
6061 }
6062 for (i = 0; i < 4; i++) {
6063 if (pos_args[i].out[0])
6064 num_pos_exports++;
6065 }
6066
6067 pos_idx = 0;
6068 for (i = 0; i < 4; i++) {
6069 if (!pos_args[i].out[0])
6070 continue;
6071
6072 /* Specify the target we are exporting */
6073 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6074 if (pos_idx == num_pos_exports)
6075 pos_args[i].done = 1;
6076 ac_build_export(&ctx->ac, &pos_args[i]);
6077 }
6078
6079 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6080 LLVMValueRef values[4];
6081 if (!(ctx->output_mask & (1ull << i)))
6082 continue;
6083
6084 for (unsigned j = 0; j < 4; j++)
6085 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6086 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6087
6088 if (i == VARYING_SLOT_LAYER) {
6089 target = V_008DFC_SQ_EXP_PARAM + param_count;
6090 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
6091 param_count++;
6092 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
6093 target = V_008DFC_SQ_EXP_PARAM + param_count;
6094 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6095 param_count++;
6096 } else if (i >= VARYING_SLOT_VAR0) {
6097 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
6098 target = V_008DFC_SQ_EXP_PARAM + param_count;
6099 outinfo->vs_output_param_offset[i] = param_count;
6100 param_count++;
6101 } else
6102 continue;
6103
6104 si_llvm_init_export_args(ctx, values, target, &args);
6105
6106 if (target >= V_008DFC_SQ_EXP_POS &&
6107 target <= (V_008DFC_SQ_EXP_POS + 3)) {
6108 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6109 &args, sizeof(args));
6110 } else {
6111 ac_build_export(&ctx->ac, &args);
6112 }
6113 }
6114
6115 if (export_prim_id) {
6116 LLVMValueRef values[4];
6117 target = V_008DFC_SQ_EXP_PARAM + param_count;
6118 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6119 param_count++;
6120
6121 values[0] = ctx->vs_prim_id;
6122 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6123 ctx->shader_info->vs.vgpr_comp_cnt);
6124 for (unsigned j = 1; j < 4; j++)
6125 values[j] = ctx->ac.f32_0;
6126 si_llvm_init_export_args(ctx, values, target, &args);
6127 ac_build_export(&ctx->ac, &args);
6128 outinfo->export_prim_id = true;
6129 }
6130
6131 outinfo->pos_exports = num_pos_exports;
6132 outinfo->param_exports = param_count;
6133 }
6134
6135 static void
6136 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6137 struct ac_es_output_info *outinfo)
6138 {
6139 int j;
6140 uint64_t max_output_written = 0;
6141 LLVMValueRef lds_base = NULL;
6142
6143 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6144 int param_index;
6145 int length = 4;
6146
6147 if (!(ctx->output_mask & (1ull << i)))
6148 continue;
6149
6150 if (i == VARYING_SLOT_CLIP_DIST0)
6151 length = ctx->num_output_clips + ctx->num_output_culls;
6152
6153 param_index = shader_io_get_unique_index(i);
6154
6155 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6156 }
6157
6158 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6159
6160 if (ctx->ac.chip_class >= GFX9) {
6161 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6162 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6163 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6164 LLVMConstInt(ctx->ac.i32, 24, false),
6165 LLVMConstInt(ctx->ac.i32, 4, false), false);
6166 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6167 LLVMBuildMul(ctx->ac.builder, wave_idx,
6168 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6169 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6170 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6171 }
6172
6173 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6174 LLVMValueRef dw_addr;
6175 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6176 int param_index;
6177 int length = 4;
6178
6179 if (!(ctx->output_mask & (1ull << i)))
6180 continue;
6181
6182 if (i == VARYING_SLOT_CLIP_DIST0)
6183 length = ctx->num_output_clips + ctx->num_output_culls;
6184
6185 param_index = shader_io_get_unique_index(i);
6186
6187 if (lds_base) {
6188 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6189 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6190 "");
6191 }
6192 for (j = 0; j < length; j++) {
6193 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6194 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6195
6196 if (ctx->ac.chip_class >= GFX9) {
6197 ac_lds_store(&ctx->ac, dw_addr,
6198 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6199 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6200 } else {
6201 ac_build_buffer_store_dword(&ctx->ac,
6202 ctx->esgs_ring,
6203 out_val, 1,
6204 NULL, ctx->es2gs_offset,
6205 (4 * param_index + j) * 4,
6206 1, 1, true, true);
6207 }
6208 }
6209 }
6210 }
6211
6212 static void
6213 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6214 {
6215 LLVMValueRef vertex_id = ctx->rel_auto_id;
6216 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6217 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6218 vertex_dw_stride, "");
6219
6220 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6221 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6222 int length = 4;
6223
6224 if (!(ctx->output_mask & (1ull << i)))
6225 continue;
6226
6227 if (i == VARYING_SLOT_CLIP_DIST0)
6228 length = ctx->num_output_clips + ctx->num_output_culls;
6229 int param = shader_io_get_unique_index(i);
6230 mark_tess_output(ctx, false, param);
6231 if (length > 4)
6232 mark_tess_output(ctx, false, param + 1);
6233 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6234 LLVMConstInt(ctx->ac.i32, param * 4, false),
6235 "");
6236 for (unsigned j = 0; j < length; j++) {
6237 ac_lds_store(&ctx->ac, dw_addr,
6238 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6239 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6240 }
6241 }
6242 }
6243
6244 struct ac_build_if_state
6245 {
6246 struct nir_to_llvm_context *ctx;
6247 LLVMValueRef condition;
6248 LLVMBasicBlockRef entry_block;
6249 LLVMBasicBlockRef true_block;
6250 LLVMBasicBlockRef false_block;
6251 LLVMBasicBlockRef merge_block;
6252 };
6253
6254 static LLVMBasicBlockRef
6255 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6256 {
6257 LLVMBasicBlockRef current_block;
6258 LLVMBasicBlockRef next_block;
6259 LLVMBasicBlockRef new_block;
6260
6261 /* get current basic block */
6262 current_block = LLVMGetInsertBlock(ctx->builder);
6263
6264 /* chqeck if there's another block after this one */
6265 next_block = LLVMGetNextBasicBlock(current_block);
6266 if (next_block) {
6267 /* insert the new block before the next block */
6268 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6269 }
6270 else {
6271 /* append new block after current block */
6272 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6273 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6274 }
6275 return new_block;
6276 }
6277
6278 static void
6279 ac_nir_build_if(struct ac_build_if_state *ifthen,
6280 struct nir_to_llvm_context *ctx,
6281 LLVMValueRef condition)
6282 {
6283 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6284
6285 memset(ifthen, 0, sizeof *ifthen);
6286 ifthen->ctx = ctx;
6287 ifthen->condition = condition;
6288 ifthen->entry_block = block;
6289
6290 /* create endif/merge basic block for the phi functions */
6291 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6292
6293 /* create/insert true_block before merge_block */
6294 ifthen->true_block =
6295 LLVMInsertBasicBlockInContext(ctx->context,
6296 ifthen->merge_block,
6297 "if-true-block");
6298
6299 /* successive code goes into the true block */
6300 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6301 }
6302
6303 /**
6304 * End a conditional.
6305 */
6306 static void
6307 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6308 {
6309 LLVMBuilderRef builder = ifthen->ctx->builder;
6310
6311 /* Insert branch to the merge block from current block */
6312 LLVMBuildBr(builder, ifthen->merge_block);
6313
6314 /*
6315 * Now patch in the various branch instructions.
6316 */
6317
6318 /* Insert the conditional branch instruction at the end of entry_block */
6319 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6320 if (ifthen->false_block) {
6321 /* we have an else clause */
6322 LLVMBuildCondBr(builder, ifthen->condition,
6323 ifthen->true_block, ifthen->false_block);
6324 }
6325 else {
6326 /* no else clause */
6327 LLVMBuildCondBr(builder, ifthen->condition,
6328 ifthen->true_block, ifthen->merge_block);
6329 }
6330
6331 /* Resume building code at end of the ifthen->merge_block */
6332 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6333 }
6334
6335 static void
6336 write_tess_factors(struct nir_to_llvm_context *ctx)
6337 {
6338 unsigned stride, outer_comps, inner_comps;
6339 struct ac_build_if_state if_ctx, inner_if_ctx;
6340 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6341 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6342 unsigned tess_inner_index, tess_outer_index;
6343 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6344 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6345 int i;
6346 emit_barrier(&ctx->ac, ctx->stage);
6347
6348 switch (ctx->options->key.tcs.primitive_mode) {
6349 case GL_ISOLINES:
6350 stride = 2;
6351 outer_comps = 2;
6352 inner_comps = 0;
6353 break;
6354 case GL_TRIANGLES:
6355 stride = 4;
6356 outer_comps = 3;
6357 inner_comps = 1;
6358 break;
6359 case GL_QUADS:
6360 stride = 6;
6361 outer_comps = 4;
6362 inner_comps = 2;
6363 break;
6364 default:
6365 return;
6366 }
6367
6368 ac_nir_build_if(&if_ctx, ctx,
6369 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6370 invocation_id, ctx->ac.i32_0, ""));
6371
6372 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6373 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6374
6375 mark_tess_output(ctx, true, tess_inner_index);
6376 mark_tess_output(ctx, true, tess_outer_index);
6377 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6378 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6379 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6380 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6381 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6382
6383 for (i = 0; i < 4; i++) {
6384 inner[i] = LLVMGetUndef(ctx->ac.i32);
6385 outer[i] = LLVMGetUndef(ctx->ac.i32);
6386 }
6387
6388 // LINES reverseal
6389 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6390 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6391 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6392 ctx->ac.i32_1, "");
6393 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6394 } else {
6395 for (i = 0; i < outer_comps; i++) {
6396 outer[i] = out[i] =
6397 ac_lds_load(&ctx->ac, lds_outer);
6398 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6399 ctx->ac.i32_1, "");
6400 }
6401 for (i = 0; i < inner_comps; i++) {
6402 inner[i] = out[outer_comps+i] =
6403 ac_lds_load(&ctx->ac, lds_inner);
6404 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6405 ctx->ac.i32_1, "");
6406 }
6407 }
6408
6409 /* Convert the outputs to vectors for stores. */
6410 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6411 vec1 = NULL;
6412
6413 if (stride > 4)
6414 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6415
6416
6417 buffer = ctx->hs_ring_tess_factor;
6418 tf_base = ctx->tess_factor_offset;
6419 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6420 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6421 unsigned tf_offset = 0;
6422
6423 if (ctx->options->chip_class <= VI) {
6424 ac_nir_build_if(&inner_if_ctx, ctx,
6425 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6426 rel_patch_id, ctx->ac.i32_0, ""));
6427
6428 /* Store the dynamic HS control word. */
6429 ac_build_buffer_store_dword(&ctx->ac, buffer,
6430 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6431 1, ctx->ac.i32_0, tf_base,
6432 0, 1, 0, true, false);
6433 tf_offset += 4;
6434
6435 ac_nir_build_endif(&inner_if_ctx);
6436 }
6437
6438 /* Store the tessellation factors. */
6439 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6440 MIN2(stride, 4), byteoffset, tf_base,
6441 tf_offset, 1, 0, true, false);
6442 if (vec1)
6443 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6444 stride - 4, byteoffset, tf_base,
6445 16 + tf_offset, 1, 0, true, false);
6446
6447 //store to offchip for TES to read - only if TES reads them
6448 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6449 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6450 LLVMValueRef tf_inner_offset;
6451 unsigned param_outer, param_inner;
6452
6453 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6454 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6455 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6456
6457 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6458 util_next_power_of_two(outer_comps));
6459
6460 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6461 outer_comps, tf_outer_offset,
6462 ctx->oc_lds, 0, 1, 0, true, false);
6463 if (inner_comps) {
6464 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6465 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6466 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6467
6468 inner_vec = inner_comps == 1 ? inner[0] :
6469 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6470 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6471 inner_comps, tf_inner_offset,
6472 ctx->oc_lds, 0, 1, 0, true, false);
6473 }
6474 }
6475 ac_nir_build_endif(&if_ctx);
6476 }
6477
6478 static void
6479 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6480 {
6481 write_tess_factors(ctx);
6482 }
6483
6484 static bool
6485 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6486 LLVMValueRef *color, unsigned param, bool is_last,
6487 struct ac_export_args *args)
6488 {
6489 /* Export */
6490 si_llvm_init_export_args(ctx, color, param,
6491 args);
6492
6493 if (is_last) {
6494 args->valid_mask = 1; /* whether the EXEC mask is valid */
6495 args->done = 1; /* DONE bit */
6496 } else if (!args->enabled_channels)
6497 return false; /* unnecessary NULL export */
6498
6499 return true;
6500 }
6501
6502 static void
6503 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6504 LLVMValueRef depth, LLVMValueRef stencil,
6505 LLVMValueRef samplemask)
6506 {
6507 struct ac_export_args args;
6508
6509 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6510
6511 ac_build_export(&ctx->ac, &args);
6512 }
6513
6514 static void
6515 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6516 {
6517 unsigned index = 0;
6518 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6519 struct ac_export_args color_args[8];
6520
6521 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6522 LLVMValueRef values[4];
6523
6524 if (!(ctx->output_mask & (1ull << i)))
6525 continue;
6526
6527 if (i == FRAG_RESULT_DEPTH) {
6528 ctx->shader_info->fs.writes_z = true;
6529 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6530 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6531 } else if (i == FRAG_RESULT_STENCIL) {
6532 ctx->shader_info->fs.writes_stencil = true;
6533 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6534 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6535 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6536 ctx->shader_info->fs.writes_sample_mask = true;
6537 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6538 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6539 } else {
6540 bool last = false;
6541 for (unsigned j = 0; j < 4; j++)
6542 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6543 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6544
6545 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6546 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6547
6548 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6549 if (ret)
6550 index++;
6551 }
6552 }
6553
6554 for (unsigned i = 0; i < index; i++)
6555 ac_build_export(&ctx->ac, &color_args[i]);
6556 if (depth || stencil || samplemask)
6557 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6558 else if (!index) {
6559 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6560 ac_build_export(&ctx->ac, &color_args[0]);
6561 }
6562 }
6563
6564 static void
6565 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6566 {
6567 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6568 }
6569
6570 static void
6571 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6572 LLVMValueRef *addrs)
6573 {
6574 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6575
6576 switch (ctx->stage) {
6577 case MESA_SHADER_VERTEX:
6578 if (ctx->options->key.vs.as_ls)
6579 handle_ls_outputs_post(ctx);
6580 else if (ctx->options->key.vs.as_es)
6581 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6582 else
6583 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6584 &ctx->shader_info->vs.outinfo);
6585 break;
6586 case MESA_SHADER_FRAGMENT:
6587 handle_fs_outputs_post(ctx);
6588 break;
6589 case MESA_SHADER_GEOMETRY:
6590 emit_gs_epilogue(ctx);
6591 break;
6592 case MESA_SHADER_TESS_CTRL:
6593 handle_tcs_outputs_post(ctx);
6594 break;
6595 case MESA_SHADER_TESS_EVAL:
6596 if (ctx->options->key.tes.as_es)
6597 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6598 else
6599 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6600 &ctx->shader_info->tes.outinfo);
6601 break;
6602 default:
6603 break;
6604 }
6605 }
6606
6607 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6608 {
6609 LLVMPassManagerRef passmgr;
6610 /* Create the pass manager */
6611 passmgr = LLVMCreateFunctionPassManagerForModule(
6612 ctx->module);
6613
6614 /* This pass should eliminate all the load and store instructions */
6615 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6616
6617 /* Add some optimization passes */
6618 LLVMAddScalarReplAggregatesPass(passmgr);
6619 LLVMAddLICMPass(passmgr);
6620 LLVMAddAggressiveDCEPass(passmgr);
6621 LLVMAddCFGSimplificationPass(passmgr);
6622 LLVMAddInstructionCombiningPass(passmgr);
6623
6624 /* Run the pass */
6625 LLVMInitializeFunctionPassManager(passmgr);
6626 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6627 LLVMFinalizeFunctionPassManager(passmgr);
6628
6629 LLVMDisposeBuilder(ctx->builder);
6630 LLVMDisposePassManager(passmgr);
6631 }
6632
6633 static void
6634 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6635 {
6636 struct ac_vs_output_info *outinfo;
6637
6638 switch (ctx->stage) {
6639 case MESA_SHADER_FRAGMENT:
6640 case MESA_SHADER_COMPUTE:
6641 case MESA_SHADER_TESS_CTRL:
6642 case MESA_SHADER_GEOMETRY:
6643 return;
6644 case MESA_SHADER_VERTEX:
6645 if (ctx->options->key.vs.as_ls ||
6646 ctx->options->key.vs.as_es)
6647 return;
6648 outinfo = &ctx->shader_info->vs.outinfo;
6649 break;
6650 case MESA_SHADER_TESS_EVAL:
6651 if (ctx->options->key.vs.as_es)
6652 return;
6653 outinfo = &ctx->shader_info->tes.outinfo;
6654 break;
6655 default:
6656 unreachable("Unhandled shader type");
6657 }
6658
6659 ac_optimize_vs_outputs(&ctx->ac,
6660 ctx->main_function,
6661 outinfo->vs_output_param_offset,
6662 VARYING_SLOT_MAX,
6663 &outinfo->param_exports);
6664 }
6665
6666 static void
6667 ac_setup_rings(struct nir_to_llvm_context *ctx)
6668 {
6669 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6670 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6671 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6672 }
6673
6674 if (ctx->is_gs_copy_shader) {
6675 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6676 }
6677 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6678 LLVMValueRef tmp;
6679 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6680 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6681
6682 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6683
6684 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6685 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6686 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6687 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6688 }
6689
6690 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6691 ctx->stage == MESA_SHADER_TESS_EVAL) {
6692 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6693 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6694 }
6695 }
6696
6697 static unsigned
6698 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6699 const struct nir_shader *nir)
6700 {
6701 switch (nir->info.stage) {
6702 case MESA_SHADER_TESS_CTRL:
6703 return chip_class >= CIK ? 128 : 64;
6704 case MESA_SHADER_GEOMETRY:
6705 return chip_class >= GFX9 ? 128 : 64;
6706 case MESA_SHADER_COMPUTE:
6707 break;
6708 default:
6709 return 0;
6710 }
6711
6712 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6713 nir->info.cs.local_size[1] *
6714 nir->info.cs.local_size[2];
6715 return max_workgroup_size;
6716 }
6717
6718 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6719 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6720 {
6721 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6722 LLVMConstInt(ctx->ac.i32, 8, false),
6723 LLVMConstInt(ctx->ac.i32, 8, false), false);
6724 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6725 ctx->ac.i32_0, "");
6726 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6727 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6728 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6729 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6730 }
6731
6732 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6733 {
6734 for(int i = 5; i >= 0; --i) {
6735 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6736 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6737 LLVMConstInt(ctx->ac.i32, 16, false), false);
6738 }
6739
6740 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6741 LLVMConstInt(ctx->ac.i32, 16, false),
6742 LLVMConstInt(ctx->ac.i32, 8, false), false);
6743 }
6744
6745 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6746 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6747 {
6748 struct ac_nir_context ctx = {};
6749 struct nir_function *func;
6750
6751 ctx.ac = *ac;
6752 ctx.abi = abi;
6753
6754 ctx.nctx = nctx;
6755 if (nctx)
6756 nctx->nir = &ctx;
6757
6758 ctx.stage = nir->info.stage;
6759
6760 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6761
6762 nir_foreach_variable(variable, &nir->outputs)
6763 handle_shader_output_decl(&ctx, nir, variable);
6764
6765 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6766 _mesa_key_pointer_equal);
6767 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6768 _mesa_key_pointer_equal);
6769 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6770 _mesa_key_pointer_equal);
6771
6772 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6773
6774 setup_locals(&ctx, func);
6775
6776 if (nir->info.stage == MESA_SHADER_COMPUTE)
6777 setup_shared(&ctx, nir);
6778
6779 visit_cf_list(&ctx, &func->impl->body);
6780 phi_post_pass(&ctx);
6781
6782 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6783 ctx.outputs);
6784
6785 free(ctx.locals);
6786 ralloc_free(ctx.defs);
6787 ralloc_free(ctx.phis);
6788 ralloc_free(ctx.vars);
6789
6790 if (nctx)
6791 nctx->nir = NULL;
6792 }
6793
6794 static
6795 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6796 struct nir_shader *const *shaders,
6797 int shader_count,
6798 struct ac_shader_variant_info *shader_info,
6799 const struct ac_nir_compiler_options *options)
6800 {
6801 struct nir_to_llvm_context ctx = {0};
6802 unsigned i;
6803 ctx.options = options;
6804 ctx.shader_info = shader_info;
6805 ctx.context = LLVMContextCreate();
6806 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6807
6808 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6809 options->family);
6810 ctx.ac.module = ctx.module;
6811 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6812
6813 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6814 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6815 LLVMSetDataLayout(ctx.module, data_layout_str);
6816 LLVMDisposeTargetData(data_layout);
6817 LLVMDisposeMessage(data_layout_str);
6818
6819 enum ac_float_mode float_mode =
6820 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6821 AC_FLOAT_MODE_DEFAULT;
6822
6823 ctx.builder = ac_create_builder(ctx.context, float_mode);
6824 ctx.ac.builder = ctx.builder;
6825
6826 memset(shader_info, 0, sizeof(*shader_info));
6827
6828 for(int i = 0; i < shader_count; ++i)
6829 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6830
6831 for (i = 0; i < AC_UD_MAX_SETS; i++)
6832 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6833 for (i = 0; i < AC_UD_MAX_UD; i++)
6834 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6835
6836 ctx.max_workgroup_size = 0;
6837 for (int i = 0; i < shader_count; ++i) {
6838 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6839 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6840 shaders[i]));
6841 }
6842
6843 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6844 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6845
6846 ctx.abi.inputs = &ctx.inputs[0];
6847 ctx.abi.emit_outputs = handle_shader_outputs_post;
6848 ctx.abi.emit_vertex = visit_emit_vertex;
6849 ctx.abi.load_ubo = radv_load_ubo;
6850 ctx.abi.load_ssbo = radv_load_ssbo;
6851 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6852 ctx.abi.clamp_shadow_reference = false;
6853
6854 if (shader_count >= 2)
6855 ac_init_exec_full_mask(&ctx.ac);
6856
6857 if (ctx.ac.chip_class == GFX9 &&
6858 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6859 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6860
6861 for(int i = 0; i < shader_count; ++i) {
6862 ctx.stage = shaders[i]->info.stage;
6863 ctx.output_mask = 0;
6864 ctx.tess_outputs_written = 0;
6865 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6866 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6867
6868 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6869 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6870 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6871 ctx.abi.load_inputs = load_gs_input;
6872 ctx.abi.emit_primitive = visit_end_primitive;
6873 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6874 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6875 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6876 ctx.abi.load_tess_varyings = load_tcs_varyings;
6877 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6878 ctx.abi.store_tcs_outputs = store_tcs_output;
6879 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6880 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6881 ctx.abi.load_tess_varyings = load_tes_input;
6882 ctx.abi.load_tess_coord = load_tess_coord;
6883 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6884 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6885 if (shader_info->info.vs.needs_instance_id) {
6886 if (ctx.options->key.vs.as_ls) {
6887 ctx.shader_info->vs.vgpr_comp_cnt =
6888 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6889 } else {
6890 ctx.shader_info->vs.vgpr_comp_cnt =
6891 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6892 }
6893 }
6894 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6895 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6896 }
6897
6898 if (i)
6899 emit_barrier(&ctx.ac, ctx.stage);
6900
6901 ac_setup_rings(&ctx);
6902
6903 LLVMBasicBlockRef merge_block;
6904 if (shader_count >= 2) {
6905 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6906 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6907 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6908
6909 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6910 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6911 LLVMConstInt(ctx.ac.i32, 8, false), false);
6912 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6913 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6914 thread_id, count, "");
6915 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6916
6917 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6918 }
6919
6920 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6921 handle_fs_inputs(&ctx, shaders[i]);
6922 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6923 handle_vs_inputs(&ctx, shaders[i]);
6924 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6925 prepare_gs_input_vgprs(&ctx);
6926
6927 nir_foreach_variable(variable, &shaders[i]->outputs)
6928 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6929
6930 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6931
6932 if (shader_count >= 2) {
6933 LLVMBuildBr(ctx.ac.builder, merge_block);
6934 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6935 }
6936
6937 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6938 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6939 shaders[i]->info.cull_distance_array_size > 4;
6940 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6941 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6942 shaders[i]->info.gs.vertices_out;
6943 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6944 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6945 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6946 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6947 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6948 }
6949 }
6950
6951 LLVMBuildRetVoid(ctx.builder);
6952
6953 if (options->dump_preoptir)
6954 ac_dump_module(ctx.module);
6955
6956 ac_llvm_finalize_module(&ctx);
6957
6958 if (shader_count == 1)
6959 ac_nir_eliminate_const_vs_outputs(&ctx);
6960
6961 return ctx.module;
6962 }
6963
6964 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6965 {
6966 unsigned *retval = (unsigned *)context;
6967 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6968 char *description = LLVMGetDiagInfoDescription(di);
6969
6970 if (severity == LLVMDSError) {
6971 *retval = 1;
6972 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6973 description);
6974 }
6975
6976 LLVMDisposeMessage(description);
6977 }
6978
6979 static unsigned ac_llvm_compile(LLVMModuleRef M,
6980 struct ac_shader_binary *binary,
6981 LLVMTargetMachineRef tm)
6982 {
6983 unsigned retval = 0;
6984 char *err;
6985 LLVMContextRef llvm_ctx;
6986 LLVMMemoryBufferRef out_buffer;
6987 unsigned buffer_size;
6988 const char *buffer_data;
6989 LLVMBool mem_err;
6990
6991 /* Setup Diagnostic Handler*/
6992 llvm_ctx = LLVMGetModuleContext(M);
6993
6994 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6995 &retval);
6996
6997 /* Compile IR*/
6998 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6999 &err, &out_buffer);
7000
7001 /* Process Errors/Warnings */
7002 if (mem_err) {
7003 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7004 free(err);
7005 retval = 1;
7006 goto out;
7007 }
7008
7009 /* Extract Shader Code*/
7010 buffer_size = LLVMGetBufferSize(out_buffer);
7011 buffer_data = LLVMGetBufferStart(out_buffer);
7012
7013 ac_elf_read(buffer_data, buffer_size, binary);
7014
7015 /* Clean up */
7016 LLVMDisposeMemoryBuffer(out_buffer);
7017
7018 out:
7019 return retval;
7020 }
7021
7022 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7023 LLVMModuleRef llvm_module,
7024 struct ac_shader_binary *binary,
7025 struct ac_shader_config *config,
7026 struct ac_shader_variant_info *shader_info,
7027 gl_shader_stage stage,
7028 bool dump_shader, bool supports_spill)
7029 {
7030 if (dump_shader)
7031 ac_dump_module(llvm_module);
7032
7033 memset(binary, 0, sizeof(*binary));
7034 int v = ac_llvm_compile(llvm_module, binary, tm);
7035 if (v) {
7036 fprintf(stderr, "compile failed\n");
7037 }
7038
7039 if (dump_shader)
7040 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7041
7042 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7043
7044 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7045 LLVMDisposeModule(llvm_module);
7046 LLVMContextDispose(ctx);
7047
7048 if (stage == MESA_SHADER_FRAGMENT) {
7049 shader_info->num_input_vgprs = 0;
7050 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7051 shader_info->num_input_vgprs += 2;
7052 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7053 shader_info->num_input_vgprs += 2;
7054 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7055 shader_info->num_input_vgprs += 2;
7056 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7057 shader_info->num_input_vgprs += 3;
7058 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7059 shader_info->num_input_vgprs += 2;
7060 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7061 shader_info->num_input_vgprs += 2;
7062 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7063 shader_info->num_input_vgprs += 2;
7064 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7065 shader_info->num_input_vgprs += 1;
7066 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7067 shader_info->num_input_vgprs += 1;
7068 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7069 shader_info->num_input_vgprs += 1;
7070 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7071 shader_info->num_input_vgprs += 1;
7072 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7073 shader_info->num_input_vgprs += 1;
7074 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7075 shader_info->num_input_vgprs += 1;
7076 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7077 shader_info->num_input_vgprs += 1;
7078 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7079 shader_info->num_input_vgprs += 1;
7080 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7081 shader_info->num_input_vgprs += 1;
7082 }
7083 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7084
7085 /* +3 for scratch wave offset and VCC */
7086 config->num_sgprs = MAX2(config->num_sgprs,
7087 shader_info->num_input_sgprs + 3);
7088
7089 /* Enable 64-bit and 16-bit denormals, because there is no performance
7090 * cost.
7091 *
7092 * If denormals are enabled, all floating-point output modifiers are
7093 * ignored.
7094 *
7095 * Don't enable denormals for 32-bit floats, because:
7096 * - Floating-point output modifiers would be ignored by the hw.
7097 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7098 * have to stop using those.
7099 * - SI & CI would be very slow.
7100 */
7101 config->float_mode |= V_00B028_FP_64_DENORMS;
7102 }
7103
7104 static void
7105 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7106 {
7107 switch (nir->info.stage) {
7108 case MESA_SHADER_COMPUTE:
7109 for (int i = 0; i < 3; ++i)
7110 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7111 break;
7112 case MESA_SHADER_FRAGMENT:
7113 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7114 break;
7115 case MESA_SHADER_GEOMETRY:
7116 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7117 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7118 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7119 shader_info->gs.invocations = nir->info.gs.invocations;
7120 break;
7121 case MESA_SHADER_TESS_EVAL:
7122 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7123 shader_info->tes.spacing = nir->info.tess.spacing;
7124 shader_info->tes.ccw = nir->info.tess.ccw;
7125 shader_info->tes.point_mode = nir->info.tess.point_mode;
7126 shader_info->tes.as_es = options->key.tes.as_es;
7127 break;
7128 case MESA_SHADER_TESS_CTRL:
7129 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7130 break;
7131 case MESA_SHADER_VERTEX:
7132 shader_info->vs.as_es = options->key.vs.as_es;
7133 shader_info->vs.as_ls = options->key.vs.as_ls;
7134 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7135 if (options->key.vs.as_ls)
7136 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7137 break;
7138 default:
7139 break;
7140 }
7141 }
7142
7143 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7144 struct ac_shader_binary *binary,
7145 struct ac_shader_config *config,
7146 struct ac_shader_variant_info *shader_info,
7147 struct nir_shader *const *nir,
7148 int nir_count,
7149 const struct ac_nir_compiler_options *options,
7150 bool dump_shader)
7151 {
7152
7153 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7154 options);
7155
7156 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7157 for (int i = 0; i < nir_count; ++i)
7158 ac_fill_shader_info(shader_info, nir[i], options);
7159
7160 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7161 if (options->chip_class == GFX9) {
7162 if (nir_count == 2 &&
7163 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7164 shader_info->gs.es_type = nir[0]->info.stage;
7165 }
7166 }
7167 }
7168
7169 static void
7170 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7171 {
7172 LLVMValueRef args[9];
7173 args[0] = ctx->gsvs_ring;
7174 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7175 args[3] = ctx->ac.i32_0;
7176 args[4] = ctx->ac.i32_1; /* OFFEN */
7177 args[5] = ctx->ac.i32_0; /* IDXEN */
7178 args[6] = ctx->ac.i32_1; /* GLC */
7179 args[7] = ctx->ac.i32_1; /* SLC */
7180 args[8] = ctx->ac.i32_0; /* TFE */
7181
7182 int idx = 0;
7183
7184 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7185 int length = 4;
7186 int slot = idx;
7187 int slot_inc = 1;
7188 if (!(ctx->output_mask & (1ull << i)))
7189 continue;
7190
7191 if (i == VARYING_SLOT_CLIP_DIST0) {
7192 /* unpack clip and cull from a single set of slots */
7193 length = ctx->num_output_clips + ctx->num_output_culls;
7194 if (length > 4)
7195 slot_inc = 2;
7196 }
7197
7198 for (unsigned j = 0; j < length; j++) {
7199 LLVMValueRef value;
7200 args[2] = LLVMConstInt(ctx->ac.i32,
7201 (slot * 4 + j) *
7202 ctx->gs_max_out_vertices * 16 * 4, false);
7203
7204 value = ac_build_intrinsic(&ctx->ac,
7205 "llvm.SI.buffer.load.dword.i32.i32",
7206 ctx->ac.i32, args, 9,
7207 AC_FUNC_ATTR_READONLY |
7208 AC_FUNC_ATTR_LEGACY);
7209
7210 LLVMBuildStore(ctx->builder,
7211 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7212 }
7213 idx += slot_inc;
7214 }
7215 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7216 }
7217
7218 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7219 struct nir_shader *geom_shader,
7220 struct ac_shader_binary *binary,
7221 struct ac_shader_config *config,
7222 struct ac_shader_variant_info *shader_info,
7223 const struct ac_nir_compiler_options *options,
7224 bool dump_shader)
7225 {
7226 struct nir_to_llvm_context ctx = {0};
7227 ctx.context = LLVMContextCreate();
7228 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7229 ctx.options = options;
7230 ctx.shader_info = shader_info;
7231
7232 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7233 options->family);
7234 ctx.ac.module = ctx.module;
7235
7236 ctx.is_gs_copy_shader = true;
7237 LLVMSetTarget(ctx.module, "amdgcn--");
7238
7239 enum ac_float_mode float_mode =
7240 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7241 AC_FLOAT_MODE_DEFAULT;
7242
7243 ctx.builder = ac_create_builder(ctx.context, float_mode);
7244 ctx.ac.builder = ctx.builder;
7245 ctx.stage = MESA_SHADER_VERTEX;
7246
7247 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7248
7249 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7250 ac_setup_rings(&ctx);
7251
7252 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7253 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7254
7255 struct ac_nir_context nir_ctx = {};
7256 nir_ctx.ac = ctx.ac;
7257 nir_ctx.abi = &ctx.abi;
7258
7259 nir_ctx.nctx = &ctx;
7260 ctx.nir = &nir_ctx;
7261
7262 nir_foreach_variable(variable, &geom_shader->outputs) {
7263 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7264 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7265 }
7266
7267 ac_gs_copy_shader_emit(&ctx);
7268
7269 ctx.nir = NULL;
7270
7271 LLVMBuildRetVoid(ctx.builder);
7272
7273 ac_llvm_finalize_module(&ctx);
7274
7275 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7276 MESA_SHADER_VERTEX,
7277 dump_shader, options->supports_spill);
7278 }