2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
52 struct nir_to_llvm_context
;
54 struct ac_nir_context
{
55 struct ac_llvm_context ac
;
56 struct ac_shader_abi
*abi
;
58 gl_shader_stage stage
;
60 struct hash_table
*defs
;
61 struct hash_table
*phis
;
62 struct hash_table
*vars
;
64 LLVMValueRef main_function
;
65 LLVMBasicBlockRef continue_block
;
66 LLVMBasicBlockRef break_block
;
68 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
73 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
76 struct nir_to_llvm_context
{
77 struct ac_llvm_context ac
;
78 const struct ac_nir_compiler_options
*options
;
79 struct ac_shader_variant_info
*shader_info
;
80 struct ac_shader_abi abi
;
81 struct ac_nir_context
*nir
;
83 unsigned max_workgroup_size
;
84 LLVMContextRef context
;
86 LLVMBuilderRef builder
;
87 LLVMValueRef main_function
;
89 struct hash_table
*defs
;
90 struct hash_table
*phis
;
92 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
93 LLVMValueRef ring_offsets
;
94 LLVMValueRef push_constants
;
95 LLVMValueRef view_index
;
96 LLVMValueRef num_work_groups
;
97 LLVMValueRef workgroup_ids
[3];
98 LLVMValueRef local_invocation_ids
;
101 LLVMValueRef vertex_buffers
;
102 LLVMValueRef rel_auto_id
;
103 LLVMValueRef vs_prim_id
;
104 LLVMValueRef ls_out_layout
;
105 LLVMValueRef es2gs_offset
;
107 LLVMValueRef tcs_offchip_layout
;
108 LLVMValueRef tcs_out_offsets
;
109 LLVMValueRef tcs_out_layout
;
110 LLVMValueRef tcs_in_layout
;
112 LLVMValueRef merged_wave_info
;
113 LLVMValueRef tess_factor_offset
;
114 LLVMValueRef tes_rel_patch_id
;
118 LLVMValueRef gsvs_ring_stride
;
119 LLVMValueRef gsvs_num_entries
;
120 LLVMValueRef gs2vs_offset
;
121 LLVMValueRef gs_wave_id
;
122 LLVMValueRef gs_vtx_offset
[6];
124 LLVMValueRef esgs_ring
;
125 LLVMValueRef gsvs_ring
;
126 LLVMValueRef hs_ring_tess_offchip
;
127 LLVMValueRef hs_ring_tess_factor
;
129 LLVMValueRef prim_mask
;
130 LLVMValueRef sample_pos_offset
;
131 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
132 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
134 gl_shader_stage stage
;
136 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
139 uint64_t output_mask
;
140 uint8_t num_output_clips
;
141 uint8_t num_output_culls
;
143 bool is_gs_copy_shader
;
144 LLVMValueRef gs_next_vertex
;
145 unsigned gs_max_out_vertices
;
147 unsigned tes_primitive_mode
;
148 uint64_t tess_outputs_written
;
149 uint64_t tess_patch_outputs_written
;
151 uint32_t tcs_patch_outputs_read
;
152 uint64_t tcs_outputs_read
;
155 static inline struct nir_to_llvm_context
*
156 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
158 struct nir_to_llvm_context
*ctx
= NULL
;
159 return container_of(abi
, ctx
, abi
);
163 nir2llvmtype(struct ac_nir_context
*ctx
,
164 const struct glsl_type
*type
)
166 switch (glsl_get_base_type(glsl_without_array(type
))) {
170 case GLSL_TYPE_UINT64
:
171 case GLSL_TYPE_INT64
:
173 case GLSL_TYPE_DOUBLE
:
175 case GLSL_TYPE_FLOAT
:
178 assert(!"Unsupported type in nir2llvmtype()");
184 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
185 const nir_deref_var
*deref
,
186 enum ac_descriptor_type desc_type
,
187 const nir_tex_instr
*instr
,
188 bool image
, bool write
);
190 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
192 return (index
* 4) + chan
;
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
197 /* handle patch indices separate */
198 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
200 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
202 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
203 return 2 + (slot
- VARYING_SLOT_PATCH0
);
205 if (slot
== VARYING_SLOT_POS
)
207 if (slot
== VARYING_SLOT_PSIZ
)
209 if (slot
== VARYING_SLOT_CLIP_DIST0
)
211 /* 3 is reserved for clip dist as well */
212 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
213 return 4 + (slot
- VARYING_SLOT_VAR0
);
214 unreachable("illegal slot in get unique index\n");
217 static void set_llvm_calling_convention(LLVMValueRef func
,
218 gl_shader_stage stage
)
220 enum radeon_llvm_calling_convention calling_conv
;
223 case MESA_SHADER_VERTEX
:
224 case MESA_SHADER_TESS_EVAL
:
225 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
227 case MESA_SHADER_GEOMETRY
:
228 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
230 case MESA_SHADER_TESS_CTRL
:
231 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
233 case MESA_SHADER_FRAGMENT
:
234 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
236 case MESA_SHADER_COMPUTE
:
237 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
240 unreachable("Unhandle shader type");
243 LLVMSetFunctionCallConv(func
, calling_conv
);
248 LLVMTypeRef types
[MAX_ARGS
];
249 LLVMValueRef
*assign
[MAX_ARGS
];
250 unsigned array_params_mask
;
253 uint8_t num_sgprs_used
;
254 uint8_t num_vgprs_used
;
257 enum ac_arg_regfile
{
263 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
264 LLVMValueRef
*param_ptr
)
266 assert(info
->count
< MAX_ARGS
);
268 info
->assign
[info
->count
] = param_ptr
;
269 info
->types
[info
->count
] = type
;
272 if (regfile
== ARG_SGPR
) {
273 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
276 assert(regfile
== ARG_VGPR
);
277 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
282 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
284 info
->array_params_mask
|= (1 << info
->count
);
285 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
288 static void assign_arguments(LLVMValueRef main_function
,
289 struct arg_info
*info
)
292 for (i
= 0; i
< info
->count
; i
++) {
294 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
299 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
300 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
301 unsigned num_return_elems
,
302 struct arg_info
*args
,
303 unsigned max_workgroup_size
,
306 LLVMTypeRef main_function_type
, ret_type
;
307 LLVMBasicBlockRef main_function_body
;
309 if (num_return_elems
)
310 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
311 num_return_elems
, true);
313 ret_type
= LLVMVoidTypeInContext(ctx
);
315 /* Setup the function */
317 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
318 LLVMValueRef main_function
=
319 LLVMAddFunction(module
, "main", main_function_type
);
321 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
322 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
324 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
325 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
326 if (args
->array_params_mask
& (1 << i
)) {
327 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
328 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
329 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
332 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
336 if (max_workgroup_size
) {
337 ac_llvm_add_target_dep_function_attr(main_function
,
338 "amdgpu-max-work-group-size",
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function
,
344 "less-precise-fpmad",
346 LLVMAddTargetDependentFunctionAttr(main_function
,
349 LLVMAddTargetDependentFunctionAttr(main_function
,
352 LLVMAddTargetDependentFunctionAttr(main_function
,
356 return main_function
;
359 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
361 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
365 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
367 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
368 type
= LLVMGetElementType(type
);
370 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
371 return LLVMGetIntTypeWidth(type
);
373 if (type
== ctx
->f16
)
375 if (type
== ctx
->f32
)
377 if (type
== ctx
->f64
)
380 unreachable("Unhandled type kind in get_elem_bits");
383 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
384 LLVMValueRef param
, unsigned rshift
,
387 LLVMValueRef value
= param
;
389 value
= LLVMBuildLShr(ctx
->builder
, value
,
390 LLVMConstInt(ctx
->i32
, rshift
, false), "");
392 if (rshift
+ bitwidth
< 32) {
393 unsigned mask
= (1 << bitwidth
) - 1;
394 value
= LLVMBuildAnd(ctx
->builder
, value
,
395 LLVMConstInt(ctx
->i32
, mask
, false), "");
400 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
402 switch (ctx
->stage
) {
403 case MESA_SHADER_TESS_CTRL
:
404 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
405 case MESA_SHADER_TESS_EVAL
:
406 return ctx
->tes_rel_patch_id
;
409 unreachable("Illegal stage");
413 /* Tessellation shaders pass outputs to the next shader using LDS.
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
434 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
436 if (ctx
->stage
== MESA_SHADER_VERTEX
)
437 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
438 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
439 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
447 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
449 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
455 return LLVMBuildMul(ctx
->builder
,
456 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
457 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
463 return LLVMBuildMul(ctx
->builder
,
464 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
465 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
471 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
472 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
474 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
480 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
481 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
482 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
484 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
485 LLVMBuildMul(ctx
->builder
, patch_stride
,
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
493 LLVMValueRef patch0_patch_data_offset
=
494 get_tcs_out_patch0_patch_data_offset(ctx
);
495 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
496 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
498 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
499 LLVMBuildMul(ctx
->builder
, patch_stride
,
505 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
506 uint32_t indirect_offset
)
508 ud_info
->sgpr_idx
= *sgpr_idx
;
509 ud_info
->num_sgprs
= num_sgprs
;
510 ud_info
->indirect
= indirect_offset
> 0;
511 ud_info
->indirect_offset
= indirect_offset
;
512 *sgpr_idx
+= num_sgprs
;
516 set_loc_shader(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
519 struct ac_userdata_info
*ud_info
=
520 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
523 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
527 set_loc_desc(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
528 uint32_t indirect_offset
)
530 struct ac_userdata_info
*ud_info
=
531 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
534 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
537 struct user_sgpr_info
{
538 bool need_ring_offsets
;
540 bool indirect_all_descriptor_sets
;
543 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
544 gl_shader_stage stage
,
545 struct user_sgpr_info
*user_sgpr_info
)
547 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage
== MESA_SHADER_GEOMETRY
||
551 stage
== MESA_SHADER_VERTEX
||
552 stage
== MESA_SHADER_TESS_CTRL
||
553 stage
== MESA_SHADER_TESS_EVAL
||
554 ctx
->is_gs_copy_shader
)
555 user_sgpr_info
->need_ring_offsets
= true;
557 if (stage
== MESA_SHADER_FRAGMENT
&&
558 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
559 user_sgpr_info
->need_ring_offsets
= true;
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
563 user_sgpr_info
->sgpr_count
+= 2;
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
568 case MESA_SHADER_COMPUTE
:
569 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
570 user_sgpr_info
->sgpr_count
+= 3;
572 case MESA_SHADER_FRAGMENT
:
573 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
575 case MESA_SHADER_VERTEX
:
576 if (!ctx
->is_gs_copy_shader
) {
577 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
578 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
579 user_sgpr_info
->sgpr_count
+= 3;
581 user_sgpr_info
->sgpr_count
+= 2;
584 if (ctx
->options
->key
.vs
.as_ls
)
585 user_sgpr_info
->sgpr_count
++;
587 case MESA_SHADER_TESS_CTRL
:
588 user_sgpr_info
->sgpr_count
+= 4;
590 case MESA_SHADER_TESS_EVAL
:
591 user_sgpr_info
->sgpr_count
+= 1;
593 case MESA_SHADER_GEOMETRY
:
594 user_sgpr_info
->sgpr_count
+= 2;
600 if (ctx
->shader_info
->info
.loads_push_constants
)
601 user_sgpr_info
->sgpr_count
+= 2;
603 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
604 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
606 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
607 user_sgpr_info
->sgpr_count
+= 2;
608 user_sgpr_info
->indirect_all_descriptor_sets
= true;
610 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
615 declare_global_input_sgprs(struct nir_to_llvm_context
*ctx
,
616 gl_shader_stage stage
,
617 bool has_previous_stage
,
618 gl_shader_stage previous_stage
,
619 const struct user_sgpr_info
*user_sgpr_info
,
620 struct arg_info
*args
,
621 LLVMValueRef
*desc_sets
)
623 LLVMTypeRef type
= const_array(ctx
->ac
.i8
, 1024 * 1024);
624 unsigned num_sets
= ctx
->options
->layout
?
625 ctx
->options
->layout
->num_sets
: 0;
626 unsigned stage_mask
= 1 << stage
;
628 if (has_previous_stage
)
629 stage_mask
|= 1 << previous_stage
;
631 /* 1 for each descriptor set */
632 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
633 for (unsigned i
= 0; i
< num_sets
; ++i
) {
634 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
635 add_array_arg(args
, type
,
636 &ctx
->descriptor_sets
[i
]);
640 add_array_arg(args
, const_array(type
, 32), desc_sets
);
643 if (ctx
->shader_info
->info
.loads_push_constants
) {
644 /* 1 for push constants and dynamic descriptors */
645 add_array_arg(args
, type
, &ctx
->push_constants
);
650 declare_vs_specific_input_sgprs(struct nir_to_llvm_context
*ctx
,
651 gl_shader_stage stage
,
652 bool has_previous_stage
,
653 gl_shader_stage previous_stage
,
654 struct arg_info
*args
)
656 if (!ctx
->is_gs_copy_shader
&&
657 (stage
== MESA_SHADER_VERTEX
||
658 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
659 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
660 add_arg(args
, ARG_SGPR
, const_array(ctx
->ac
.v4i32
, 16),
661 &ctx
->vertex_buffers
);
663 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
664 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
665 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
666 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
672 declare_vs_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
674 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
675 if (!ctx
->is_gs_copy_shader
) {
676 if (ctx
->options
->key
.vs
.as_ls
) {
677 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
680 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
681 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
683 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
688 declare_tes_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
690 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
691 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
692 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
693 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
697 set_global_input_locs(struct nir_to_llvm_context
*ctx
, gl_shader_stage stage
,
698 bool has_previous_stage
, gl_shader_stage previous_stage
,
699 const struct user_sgpr_info
*user_sgpr_info
,
700 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
702 unsigned num_sets
= ctx
->options
->layout
?
703 ctx
->options
->layout
->num_sets
: 0;
704 unsigned stage_mask
= 1 << stage
;
706 if (has_previous_stage
)
707 stage_mask
|= 1 << previous_stage
;
709 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
710 for (unsigned i
= 0; i
< num_sets
; ++i
) {
711 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
712 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
714 ctx
->descriptor_sets
[i
] = NULL
;
717 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
720 for (unsigned i
= 0; i
< num_sets
; ++i
) {
721 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
722 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
723 ctx
->descriptor_sets
[i
] =
724 ac_build_load_to_sgpr(&ctx
->ac
,
726 LLVMConstInt(ctx
->ac
.i32
, i
, false));
729 ctx
->descriptor_sets
[i
] = NULL
;
731 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
734 if (ctx
->shader_info
->info
.loads_push_constants
) {
735 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
740 set_vs_specific_input_locs(struct nir_to_llvm_context
*ctx
,
741 gl_shader_stage stage
, bool has_previous_stage
,
742 gl_shader_stage previous_stage
,
743 uint8_t *user_sgpr_idx
)
745 if (!ctx
->is_gs_copy_shader
&&
746 (stage
== MESA_SHADER_VERTEX
||
747 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
748 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
749 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
754 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
757 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
758 user_sgpr_idx
, vs_num
);
762 static void create_function(struct nir_to_llvm_context
*ctx
,
763 gl_shader_stage stage
,
764 bool has_previous_stage
,
765 gl_shader_stage previous_stage
)
767 uint8_t user_sgpr_idx
;
768 struct user_sgpr_info user_sgpr_info
;
769 struct arg_info args
= {};
770 LLVMValueRef desc_sets
;
772 allocate_user_sgprs(ctx
, stage
, &user_sgpr_info
);
774 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
775 add_arg(&args
, ARG_SGPR
, const_array(ctx
->ac
.v4i32
, 16),
780 case MESA_SHADER_COMPUTE
:
781 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
782 previous_stage
, &user_sgpr_info
,
785 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
786 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
787 &ctx
->num_work_groups
);
790 for (int i
= 0; i
< 3; i
++) {
791 ctx
->workgroup_ids
[i
] = NULL
;
792 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
793 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
794 &ctx
->workgroup_ids
[i
]);
798 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
799 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tg_size
);
800 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
801 &ctx
->local_invocation_ids
);
803 case MESA_SHADER_VERTEX
:
804 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
805 previous_stage
, &user_sgpr_info
,
807 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
808 previous_stage
, &args
);
810 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
811 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
812 if (ctx
->options
->key
.vs
.as_es
)
813 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
815 else if (ctx
->options
->key
.vs
.as_ls
)
816 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
817 &ctx
->ls_out_layout
);
819 declare_vs_input_vgprs(ctx
, &args
);
821 case MESA_SHADER_TESS_CTRL
:
822 if (has_previous_stage
) {
823 // First 6 system regs
824 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
825 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
826 &ctx
->merged_wave_info
);
827 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
828 &ctx
->tess_factor_offset
);
830 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
831 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
832 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
834 declare_global_input_sgprs(ctx
, stage
,
837 &user_sgpr_info
, &args
,
839 declare_vs_specific_input_sgprs(ctx
, stage
,
841 previous_stage
, &args
);
843 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
844 &ctx
->ls_out_layout
);
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->tcs_offchip_layout
);
848 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
849 &ctx
->tcs_out_offsets
);
850 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
851 &ctx
->tcs_out_layout
);
852 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
853 &ctx
->tcs_in_layout
);
854 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
855 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
858 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
859 &ctx
->abi
.tcs_patch_id
);
860 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
861 &ctx
->abi
.tcs_rel_ids
);
863 declare_vs_input_vgprs(ctx
, &args
);
865 declare_global_input_sgprs(ctx
, stage
,
868 &user_sgpr_info
, &args
,
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->tcs_offchip_layout
);
873 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
874 &ctx
->tcs_out_offsets
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tcs_out_layout
);
877 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
878 &ctx
->tcs_in_layout
);
879 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
880 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
883 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
884 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
885 &ctx
->tess_factor_offset
);
886 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
887 &ctx
->abi
.tcs_patch_id
);
888 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
889 &ctx
->abi
.tcs_rel_ids
);
892 case MESA_SHADER_TESS_EVAL
:
893 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
894 previous_stage
, &user_sgpr_info
,
897 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
898 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
899 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
901 if (ctx
->options
->key
.tes
.as_es
) {
902 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
903 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
904 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
907 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
908 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
910 declare_tes_input_vgprs(ctx
, &args
);
912 case MESA_SHADER_GEOMETRY
:
913 if (has_previous_stage
) {
914 // First 6 system regs
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
917 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
918 &ctx
->merged_wave_info
);
919 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
921 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
922 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
923 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
925 declare_global_input_sgprs(ctx
, stage
,
928 &user_sgpr_info
, &args
,
931 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
932 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
933 &ctx
->tcs_offchip_layout
);
935 declare_vs_specific_input_sgprs(ctx
, stage
,
941 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
942 &ctx
->gsvs_ring_stride
);
943 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
944 &ctx
->gsvs_num_entries
);
945 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
946 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
949 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
950 &ctx
->gs_vtx_offset
[0]);
951 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
952 &ctx
->gs_vtx_offset
[2]);
953 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
954 &ctx
->abi
.gs_prim_id
);
955 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
956 &ctx
->abi
.gs_invocation_id
);
957 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
958 &ctx
->gs_vtx_offset
[4]);
960 if (previous_stage
== MESA_SHADER_VERTEX
) {
961 declare_vs_input_vgprs(ctx
, &args
);
963 declare_tes_input_vgprs(ctx
, &args
);
966 declare_global_input_sgprs(ctx
, stage
,
969 &user_sgpr_info
, &args
,
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
973 &ctx
->gsvs_ring_stride
);
974 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
975 &ctx
->gsvs_num_entries
);
976 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
977 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
980 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
981 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->gs_vtx_offset
[0]);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->gs_vtx_offset
[1]);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->abi
.gs_prim_id
);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
989 &ctx
->gs_vtx_offset
[2]);
990 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
991 &ctx
->gs_vtx_offset
[3]);
992 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
993 &ctx
->gs_vtx_offset
[4]);
994 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
995 &ctx
->gs_vtx_offset
[5]);
996 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
997 &ctx
->abi
.gs_invocation_id
);
1000 case MESA_SHADER_FRAGMENT
:
1001 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1002 previous_stage
, &user_sgpr_info
,
1005 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
1006 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1007 &ctx
->sample_pos_offset
);
1009 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->prim_mask
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1018 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1019 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1020 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1021 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1022 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1023 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1024 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1025 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1028 unreachable("Shader stage not implemented");
1031 ctx
->main_function
= create_llvm_function(
1032 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
1033 ctx
->max_workgroup_size
,
1034 ctx
->options
->unsafe_math
);
1035 set_llvm_calling_convention(ctx
->main_function
, stage
);
1038 ctx
->shader_info
->num_input_vgprs
= 0;
1039 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1041 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1043 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1044 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1046 assign_arguments(ctx
->main_function
, &args
);
1050 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1051 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1053 if (ctx
->options
->supports_spill
) {
1054 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1055 LLVMPointerType(ctx
->ac
.i8
, CONST_ADDR_SPACE
),
1056 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1057 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
1058 const_array(ctx
->ac
.v4i32
, 16), "");
1062 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1063 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1064 if (has_previous_stage
)
1067 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1068 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1071 case MESA_SHADER_COMPUTE
:
1072 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1073 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1077 case MESA_SHADER_VERTEX
:
1078 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1079 previous_stage
, &user_sgpr_idx
);
1080 if (ctx
->view_index
)
1081 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1082 if (ctx
->options
->key
.vs
.as_ls
) {
1083 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1086 if (ctx
->options
->key
.vs
.as_ls
)
1087 ac_declare_lds_as_pointer(&ctx
->ac
);
1089 case MESA_SHADER_TESS_CTRL
:
1090 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1091 previous_stage
, &user_sgpr_idx
);
1092 if (has_previous_stage
)
1093 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1095 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1096 if (ctx
->view_index
)
1097 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1098 ac_declare_lds_as_pointer(&ctx
->ac
);
1100 case MESA_SHADER_TESS_EVAL
:
1101 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1102 if (ctx
->view_index
)
1103 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1105 case MESA_SHADER_GEOMETRY
:
1106 if (has_previous_stage
) {
1107 if (previous_stage
== MESA_SHADER_VERTEX
)
1108 set_vs_specific_input_locs(ctx
, stage
,
1113 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1116 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1118 if (ctx
->view_index
)
1119 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1120 if (has_previous_stage
)
1121 ac_declare_lds_as_pointer(&ctx
->ac
);
1123 case MESA_SHADER_FRAGMENT
:
1124 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1125 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1130 unreachable("Shader stage not implemented");
1133 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1136 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1137 LLVMValueRef value
, unsigned count
)
1139 unsigned num_components
= ac_get_llvm_num_components(value
);
1140 if (count
== num_components
)
1143 LLVMValueRef masks
[] = {
1144 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1145 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1148 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1151 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1152 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1156 build_store_values_extended(struct ac_llvm_context
*ac
,
1157 LLVMValueRef
*values
,
1158 unsigned value_count
,
1159 unsigned value_stride
,
1162 LLVMBuilderRef builder
= ac
->builder
;
1165 for (i
= 0; i
< value_count
; i
++) {
1166 LLVMValueRef ptr
= values
[i
* value_stride
];
1167 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1168 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1169 LLVMBuildStore(builder
, value
, ptr
);
1173 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1174 const nir_ssa_def
*def
)
1176 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1177 if (def
->num_components
> 1) {
1178 type
= LLVMVectorType(type
, def
->num_components
);
1183 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1186 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1187 return (LLVMValueRef
)entry
->data
;
1191 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1192 const struct nir_block
*b
)
1194 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1195 return (LLVMBasicBlockRef
)entry
->data
;
1198 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1200 unsigned num_components
)
1202 LLVMValueRef value
= get_src(ctx
, src
.src
);
1203 bool need_swizzle
= false;
1206 LLVMTypeRef type
= LLVMTypeOf(value
);
1207 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1208 ? LLVMGetVectorSize(type
)
1211 for (unsigned i
= 0; i
< num_components
; ++i
) {
1212 assert(src
.swizzle
[i
] < src_components
);
1213 if (src
.swizzle
[i
] != i
)
1214 need_swizzle
= true;
1217 if (need_swizzle
|| num_components
!= src_components
) {
1218 LLVMValueRef masks
[] = {
1219 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1220 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1221 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1222 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1224 if (src_components
> 1 && num_components
== 1) {
1225 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1227 } else if (src_components
== 1 && num_components
> 1) {
1228 LLVMValueRef values
[] = {value
, value
, value
, value
};
1229 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1231 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1232 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1236 assert(!src
.negate
);
1241 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1242 LLVMIntPredicate pred
, LLVMValueRef src0
,
1245 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1246 return LLVMBuildSelect(ctx
->builder
, result
,
1247 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1251 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1252 LLVMRealPredicate pred
, LLVMValueRef src0
,
1255 LLVMValueRef result
;
1256 src0
= ac_to_float(ctx
, src0
);
1257 src1
= ac_to_float(ctx
, src1
);
1258 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1259 return LLVMBuildSelect(ctx
->builder
, result
,
1260 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1264 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1266 LLVMTypeRef result_type
,
1270 LLVMValueRef params
[] = {
1271 ac_to_float(ctx
, src0
),
1274 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1275 get_elem_bits(ctx
, result_type
));
1276 assert(length
< sizeof(name
));
1277 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1280 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1282 LLVMTypeRef result_type
,
1283 LLVMValueRef src0
, LLVMValueRef src1
)
1286 LLVMValueRef params
[] = {
1287 ac_to_float(ctx
, src0
),
1288 ac_to_float(ctx
, src1
),
1291 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1292 get_elem_bits(ctx
, result_type
));
1293 assert(length
< sizeof(name
));
1294 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1297 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1299 LLVMTypeRef result_type
,
1300 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1303 LLVMValueRef params
[] = {
1304 ac_to_float(ctx
, src0
),
1305 ac_to_float(ctx
, src1
),
1306 ac_to_float(ctx
, src2
),
1309 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1310 get_elem_bits(ctx
, result_type
));
1311 assert(length
< sizeof(name
));
1312 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1315 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1316 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1318 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1320 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1323 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1324 LLVMIntPredicate pred
,
1325 LLVMValueRef src0
, LLVMValueRef src1
)
1327 return LLVMBuildSelect(ctx
->builder
,
1328 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1333 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1336 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1337 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1340 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1343 LLVMValueRef cmp
, val
;
1345 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, ctx
->f32_0
, "");
1346 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->f32_1
, src0
, "");
1347 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, ctx
->f32_0
, "");
1348 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(ctx
->f32
, -1.0), "");
1352 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1355 LLVMValueRef cmp
, val
;
1357 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, ctx
->i32_0
, "");
1358 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->i32_1
, src0
, "");
1359 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, ctx
->i32_0
, "");
1360 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(ctx
->i32
, -1, true), "");
1364 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1367 const char *intr
= "llvm.floor.f32";
1368 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1369 LLVMValueRef params
[] = {
1372 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1373 ctx
->f32
, params
, 1,
1374 AC_FUNC_ATTR_READNONE
);
1375 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1378 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1380 LLVMValueRef src0
, LLVMValueRef src1
)
1382 LLVMTypeRef ret_type
;
1383 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1385 LLVMValueRef params
[] = { src0
, src1
};
1386 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1389 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1390 params
, 2, AC_FUNC_ATTR_READNONE
);
1392 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1393 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1397 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1400 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1403 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1406 src0
= ac_to_float(ctx
, src0
);
1407 return LLVMBuildSExt(ctx
->builder
,
1408 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1412 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1415 return LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1418 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1421 return LLVMBuildSExt(ctx
->builder
,
1422 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1426 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1429 LLVMValueRef result
;
1430 LLVMValueRef cond
= NULL
;
1432 src0
= ac_to_float(&ctx
->ac
, src0
);
1433 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1435 if (ctx
->options
->chip_class
>= VI
) {
1436 LLVMValueRef args
[2];
1437 /* Check if the result is a denormal - and flush to 0 if so. */
1439 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1440 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1443 /* need to convert back up to f32 */
1444 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1446 if (ctx
->options
->chip_class
>= VI
)
1447 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1450 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1451 * so compare the result and flush to 0 if it's smaller.
1453 LLVMValueRef temp
, cond2
;
1454 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1455 ctx
->ac
.f32
, result
);
1456 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1457 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1459 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1460 temp
, ctx
->ac
.f32_0
, "");
1461 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1462 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1467 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1468 LLVMValueRef src0
, LLVMValueRef src1
)
1470 LLVMValueRef dst64
, result
;
1471 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1472 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1474 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1475 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1476 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1480 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1481 LLVMValueRef src0
, LLVMValueRef src1
)
1483 LLVMValueRef dst64
, result
;
1484 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1485 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1487 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1488 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1489 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1493 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1495 const LLVMValueRef srcs
[3])
1497 LLVMValueRef result
;
1498 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1500 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1501 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1505 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1506 LLVMValueRef src0
, LLVMValueRef src1
,
1507 LLVMValueRef src2
, LLVMValueRef src3
)
1509 LLVMValueRef bfi_args
[3], result
;
1511 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1512 LLVMBuildSub(ctx
->builder
,
1513 LLVMBuildShl(ctx
->builder
,
1518 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1521 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1524 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1525 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1527 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1528 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1529 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1531 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1535 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1538 LLVMValueRef comp
[2];
1540 src0
= ac_to_float(ctx
, src0
);
1541 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1542 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1544 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1547 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1550 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1551 LLVMValueRef temps
[2], result
, val
;
1554 for (i
= 0; i
< 2; i
++) {
1555 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1556 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1557 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1558 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1561 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1563 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1568 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1574 LLVMValueRef result
;
1576 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1577 mask
= AC_TID_MASK_LEFT
;
1578 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1579 mask
= AC_TID_MASK_TOP
;
1581 mask
= AC_TID_MASK_TOP_LEFT
;
1583 /* for DDX we want to next X pixel, DDY next Y pixel. */
1584 if (op
== nir_op_fddx_fine
||
1585 op
== nir_op_fddx_coarse
||
1591 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1596 * this takes an I,J coordinate pair,
1597 * and works out the X and Y derivatives.
1598 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1600 static LLVMValueRef
emit_ddxy_interp(
1601 struct ac_nir_context
*ctx
,
1602 LLVMValueRef interp_ij
)
1604 LLVMValueRef result
[4], a
;
1607 for (i
= 0; i
< 2; i
++) {
1608 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1609 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1610 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1611 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1613 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1616 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1618 LLVMValueRef src
[4], result
= NULL
;
1619 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1620 unsigned src_components
;
1621 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1623 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1624 switch (instr
->op
) {
1630 case nir_op_pack_half_2x16
:
1633 case nir_op_unpack_half_2x16
:
1637 src_components
= num_components
;
1640 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1641 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1643 switch (instr
->op
) {
1649 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1650 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1653 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1656 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1659 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1662 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1663 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1664 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1667 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1668 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1669 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1672 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1675 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1678 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1681 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1684 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1685 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1686 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1687 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1688 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1689 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1690 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1693 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1694 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1695 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1698 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1701 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1704 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1707 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1708 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1709 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1712 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1713 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1714 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1717 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1718 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, src
[0]);
1721 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1724 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1727 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1730 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1731 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1732 LLVMTypeOf(src
[0]), ""),
1736 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1737 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1738 LLVMTypeOf(src
[0]), ""),
1742 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1743 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1744 LLVMTypeOf(src
[0]), ""),
1748 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1751 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1754 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1757 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1760 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1763 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1766 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1769 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1772 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1775 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1778 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1779 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1782 result
= emit_iabs(&ctx
->ac
, src
[0]);
1785 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1788 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1791 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1794 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1797 result
= emit_isign(&ctx
->ac
, src
[0]);
1800 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1801 result
= emit_fsign(&ctx
->ac
, src
[0]);
1804 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1805 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1808 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1809 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1812 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1813 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1815 case nir_op_fround_even
:
1816 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1817 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1820 result
= emit_ffract(&ctx
->ac
, src
[0]);
1823 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1824 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1827 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1828 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1831 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1832 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1835 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1836 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1839 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1840 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1843 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1844 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1845 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, result
);
1848 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1849 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1852 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1853 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1854 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1855 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1856 ac_to_float_type(&ctx
->ac
, def_type
),
1860 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1861 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1862 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1863 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1864 ac_to_float_type(&ctx
->ac
, def_type
),
1868 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1869 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1871 case nir_op_ibitfield_extract
:
1872 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1874 case nir_op_ubitfield_extract
:
1875 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1877 case nir_op_bitfield_insert
:
1878 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1880 case nir_op_bitfield_reverse
:
1881 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1883 case nir_op_bit_count
:
1884 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1889 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1890 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1891 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1895 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1896 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1900 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1901 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1905 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1906 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1910 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1911 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1914 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1915 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1918 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1922 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1923 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1924 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1926 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1930 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1931 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1932 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1934 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1937 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1939 case nir_op_find_lsb
:
1940 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1941 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1943 case nir_op_ufind_msb
:
1944 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1945 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1947 case nir_op_ifind_msb
:
1948 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1949 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1951 case nir_op_uadd_carry
:
1952 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1953 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1954 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1956 case nir_op_usub_borrow
:
1957 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1958 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1959 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1962 result
= emit_b2f(&ctx
->ac
, src
[0]);
1965 result
= emit_f2b(&ctx
->ac
, src
[0]);
1968 result
= emit_b2i(&ctx
->ac
, src
[0]);
1971 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1972 result
= emit_i2b(&ctx
->ac
, src
[0]);
1974 case nir_op_fquantize2f16
:
1975 result
= emit_f2f16(ctx
->nctx
, src
[0]);
1977 case nir_op_umul_high
:
1978 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1979 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1980 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1982 case nir_op_imul_high
:
1983 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1984 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1985 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1987 case nir_op_pack_half_2x16
:
1988 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1990 case nir_op_unpack_half_2x16
:
1991 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1995 case nir_op_fddx_fine
:
1996 case nir_op_fddy_fine
:
1997 case nir_op_fddx_coarse
:
1998 case nir_op_fddy_coarse
:
1999 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2002 case nir_op_unpack_64_2x32_split_x
: {
2003 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2004 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2007 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2012 case nir_op_unpack_64_2x32_split_y
: {
2013 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2014 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2017 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2022 case nir_op_pack_64_2x32_split
: {
2023 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2024 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2025 src
[0], ctx
->ac
.i32_0
, "");
2026 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2027 src
[1], ctx
->ac
.i32_1
, "");
2028 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2033 fprintf(stderr
, "Unknown NIR alu instr: ");
2034 nir_print_instr(&instr
->instr
, stderr
);
2035 fprintf(stderr
, "\n");
2040 assert(instr
->dest
.dest
.is_ssa
);
2041 result
= ac_to_integer(&ctx
->ac
, result
);
2042 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2047 static void visit_load_const(struct ac_nir_context
*ctx
,
2048 const nir_load_const_instr
*instr
)
2050 LLVMValueRef values
[4], value
= NULL
;
2051 LLVMTypeRef element_type
=
2052 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2054 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2055 switch (instr
->def
.bit_size
) {
2057 values
[i
] = LLVMConstInt(element_type
,
2058 instr
->value
.u32
[i
], false);
2061 values
[i
] = LLVMConstInt(element_type
,
2062 instr
->value
.u64
[i
], false);
2066 "unsupported nir load_const bit_size: %d\n",
2067 instr
->def
.bit_size
);
2071 if (instr
->def
.num_components
> 1) {
2072 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2076 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2079 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2082 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2083 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2084 LLVMPointerType(type
, addr_space
), "");
2088 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2091 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2092 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2095 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2096 /* On VI, the descriptor contains the size in bytes,
2097 * but TXQ must return the size in elements.
2098 * The stride is always non-zero for resources using TXQ.
2100 LLVMValueRef stride
=
2101 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2103 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2104 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2105 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2106 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2108 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2114 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2117 static void build_int_type_name(
2119 char *buf
, unsigned bufsize
)
2121 assert(bufsize
>= 6);
2123 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2124 snprintf(buf
, bufsize
, "v%ui32",
2125 LLVMGetVectorSize(type
));
2130 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2131 struct ac_image_args
*args
,
2132 const nir_tex_instr
*instr
)
2134 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2135 LLVMValueRef coord
= args
->addr
;
2136 LLVMValueRef half_texel
[2];
2137 LLVMValueRef compare_cube_wa
= NULL
;
2138 LLVMValueRef result
;
2140 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2144 struct ac_image_args txq_args
= { 0 };
2146 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2147 txq_args
.opcode
= ac_image_get_resinfo
;
2148 txq_args
.dmask
= 0xf;
2149 txq_args
.addr
= ctx
->i32_0
;
2150 txq_args
.resource
= args
->resource
;
2151 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2153 for (c
= 0; c
< 2; c
++) {
2154 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2155 LLVMConstInt(ctx
->i32
, c
, false), "");
2156 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2157 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2158 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2159 LLVMConstReal(ctx
->f32
, -0.5), "");
2163 LLVMValueRef orig_coords
= args
->addr
;
2165 for (c
= 0; c
< 2; c
++) {
2167 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2168 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2169 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2170 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2171 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2172 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2177 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2178 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2179 * workaround by sampling using a scaled type and converting.
2180 * This is taken from amdgpu-pro shaders.
2182 /* NOTE this produces some ugly code compared to amdgpu-pro,
2183 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2184 * and then reads them back. -pro generates two selects,
2185 * one s_cmp for the descriptor rewriting
2186 * one v_cmp for the coordinate and result changes.
2188 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2189 LLVMValueRef tmp
, tmp2
;
2191 /* workaround 8/8/8/8 uint/sint cube gather bug */
2192 /* first detect it then change to a scaled read and f2i */
2193 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2196 /* extract the DATA_FORMAT */
2197 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2198 LLVMConstInt(ctx
->i32
, 6, false), false);
2200 /* is the DATA_FORMAT == 8_8_8_8 */
2201 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2203 if (stype
== GLSL_TYPE_UINT
)
2204 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2205 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2206 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2208 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2209 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2210 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2212 /* replace the NUM FORMAT in the descriptor */
2213 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2214 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2216 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2218 /* don't modify the coordinates for this case */
2219 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2222 result
= ac_build_image_opcode(ctx
, args
);
2224 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2225 LLVMValueRef tmp
, tmp2
;
2227 /* if the cube workaround is in place, f2i the result. */
2228 for (c
= 0; c
< 4; c
++) {
2229 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2230 if (stype
== GLSL_TYPE_UINT
)
2231 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2233 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2234 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2235 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2236 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2237 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2238 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2244 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2245 const nir_tex_instr
*instr
,
2247 struct ac_image_args
*args
)
2249 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2250 return ac_build_buffer_load_format(&ctx
->ac
,
2257 args
->opcode
= ac_image_sample
;
2258 args
->compare
= instr
->is_shadow
;
2260 switch (instr
->op
) {
2262 case nir_texop_txf_ms
:
2263 case nir_texop_samples_identical
:
2264 args
->opcode
= lod_is_zero
||
2265 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2266 ac_image_load
: ac_image_load_mip
;
2267 args
->compare
= false;
2268 args
->offset
= false;
2275 args
->level_zero
= true;
2280 case nir_texop_query_levels
:
2281 args
->opcode
= ac_image_get_resinfo
;
2284 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2285 args
->level_zero
= true;
2291 args
->opcode
= ac_image_gather4
;
2292 args
->level_zero
= true;
2295 args
->opcode
= ac_image_get_lod
;
2296 args
->compare
= false;
2297 args
->offset
= false;
2303 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2304 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2305 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2306 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2309 return ac_build_image_opcode(&ctx
->ac
, args
);
2312 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2313 nir_intrinsic_instr
*instr
)
2315 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2316 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2317 unsigned binding
= nir_intrinsic_binding(instr
);
2318 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2319 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2320 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2321 unsigned base_offset
= layout
->binding
[binding
].offset
;
2322 LLVMValueRef offset
, stride
;
2324 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2325 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2326 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2327 layout
->binding
[binding
].dynamic_offset_offset
;
2328 desc_ptr
= ctx
->push_constants
;
2329 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2330 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2332 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2334 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2335 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2336 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2338 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2339 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2340 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2345 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2346 nir_intrinsic_instr
*instr
)
2348 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2349 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2351 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2352 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2356 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2357 nir_intrinsic_instr
*instr
)
2359 LLVMValueRef ptr
, addr
;
2361 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2362 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2364 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2365 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2367 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2370 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2371 const nir_intrinsic_instr
*instr
)
2373 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2375 return get_buffer_size(ctx
, LLVMBuildLoad(ctx
->ac
.builder
, ptr
, ""), false);
2377 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2378 nir_intrinsic_instr
*instr
)
2380 const char *store_name
;
2381 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2382 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2383 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2384 int components_32bit
= elem_size_mult
* instr
->num_components
;
2385 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2386 LLVMValueRef base_data
, base_offset
;
2387 LLVMValueRef params
[6];
2389 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2390 get_src(ctx
, instr
->src
[1]), true);
2391 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2392 params
[4] = ctx
->ac
.i1false
; /* glc */
2393 params
[5] = ctx
->ac
.i1false
; /* slc */
2395 if (components_32bit
> 1)
2396 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2398 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2399 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2400 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2402 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2406 LLVMValueRef offset
;
2408 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2410 /* Due to an LLVM limitation, split 3-element writes
2411 * into a 2-element and a 1-element write. */
2413 writemask
|= 1 << (start
+ 2);
2417 start
*= elem_size_mult
;
2418 count
*= elem_size_mult
;
2421 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2426 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2428 } else if (count
== 2) {
2429 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2430 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2431 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, LLVMGetUndef(ctx
->ac
.v2f32
), tmp
,
2434 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2435 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
+ 1, false), "");
2436 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, data
, tmp
,
2438 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2442 if (ac_get_llvm_num_components(base_data
) > 1)
2443 data
= LLVMBuildExtractElement(ctx
->ac
.builder
, base_data
,
2444 LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2447 store_name
= "llvm.amdgcn.buffer.store.f32";
2450 offset
= base_offset
;
2452 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2456 ac_build_intrinsic(&ctx
->ac
, store_name
,
2457 ctx
->ac
.voidt
, params
, 6, 0);
2461 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2462 const nir_intrinsic_instr
*instr
)
2465 LLVMValueRef params
[6];
2468 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2469 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2471 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2472 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2473 get_src(ctx
, instr
->src
[0]),
2475 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2476 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2477 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2479 switch (instr
->intrinsic
) {
2480 case nir_intrinsic_ssbo_atomic_add
:
2481 name
= "llvm.amdgcn.buffer.atomic.add";
2483 case nir_intrinsic_ssbo_atomic_imin
:
2484 name
= "llvm.amdgcn.buffer.atomic.smin";
2486 case nir_intrinsic_ssbo_atomic_umin
:
2487 name
= "llvm.amdgcn.buffer.atomic.umin";
2489 case nir_intrinsic_ssbo_atomic_imax
:
2490 name
= "llvm.amdgcn.buffer.atomic.smax";
2492 case nir_intrinsic_ssbo_atomic_umax
:
2493 name
= "llvm.amdgcn.buffer.atomic.umax";
2495 case nir_intrinsic_ssbo_atomic_and
:
2496 name
= "llvm.amdgcn.buffer.atomic.and";
2498 case nir_intrinsic_ssbo_atomic_or
:
2499 name
= "llvm.amdgcn.buffer.atomic.or";
2501 case nir_intrinsic_ssbo_atomic_xor
:
2502 name
= "llvm.amdgcn.buffer.atomic.xor";
2504 case nir_intrinsic_ssbo_atomic_exchange
:
2505 name
= "llvm.amdgcn.buffer.atomic.swap";
2507 case nir_intrinsic_ssbo_atomic_comp_swap
:
2508 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2514 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2517 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2518 const nir_intrinsic_instr
*instr
)
2520 LLVMValueRef results
[2];
2521 int load_components
;
2522 int num_components
= instr
->num_components
;
2523 if (instr
->dest
.ssa
.bit_size
== 64)
2524 num_components
*= 2;
2526 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2527 load_components
= MIN2(num_components
- i
, 4);
2528 const char *load_name
;
2529 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2530 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2531 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2533 if (load_components
== 3)
2534 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2535 else if (load_components
> 1)
2536 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2538 if (load_components
>= 3)
2539 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2540 else if (load_components
== 2)
2541 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2542 else if (load_components
== 1)
2543 load_name
= "llvm.amdgcn.buffer.load.f32";
2545 unreachable("unhandled number of components");
2547 LLVMValueRef params
[] = {
2548 ctx
->abi
->load_ssbo(ctx
->abi
,
2549 get_src(ctx
, instr
->src
[0]),
2557 results
[i
] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2562 LLVMValueRef ret
= results
[0];
2563 if (num_components
> 4 || num_components
== 3) {
2564 LLVMValueRef masks
[] = {
2565 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2566 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2567 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2568 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2571 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2572 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2573 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2576 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2577 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2580 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2581 const nir_intrinsic_instr
*instr
)
2584 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2585 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2586 int num_components
= instr
->num_components
;
2588 if (ctx
->abi
->load_ubo
)
2589 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2591 if (instr
->dest
.ssa
.bit_size
== 64)
2592 num_components
*= 2;
2594 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2595 NULL
, 0, false, false, true, true);
2597 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2598 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2602 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2603 bool vs_in
, unsigned *vertex_index_out
,
2604 LLVMValueRef
*vertex_index_ref
,
2605 unsigned *const_out
, LLVMValueRef
*indir_out
)
2607 unsigned const_offset
= 0;
2608 nir_deref
*tail
= &deref
->deref
;
2609 LLVMValueRef offset
= NULL
;
2611 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2613 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2614 if (vertex_index_out
)
2615 *vertex_index_out
= deref_array
->base_offset
;
2617 if (vertex_index_ref
) {
2618 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2619 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2620 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2622 *vertex_index_ref
= vtx
;
2626 if (deref
->var
->data
.compact
) {
2627 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2628 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2629 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2630 /* We always lower indirect dereferences for "compact" array vars. */
2631 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2633 const_offset
= deref_array
->base_offset
;
2637 while (tail
->child
!= NULL
) {
2638 const struct glsl_type
*parent_type
= tail
->type
;
2641 if (tail
->deref_type
== nir_deref_type_array
) {
2642 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2643 LLVMValueRef index
, stride
, local_offset
;
2644 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2646 const_offset
+= size
* deref_array
->base_offset
;
2647 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2650 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2651 index
= get_src(ctx
, deref_array
->indirect
);
2652 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2653 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2656 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2658 offset
= local_offset
;
2659 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2660 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2662 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2663 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2664 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2667 unreachable("unsupported deref type");
2671 if (const_offset
&& offset
)
2672 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2673 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2676 *const_out
= const_offset
;
2677 *indir_out
= offset
;
2681 /* The offchip buffer layout for TCS->TES is
2683 * - attribute 0 of patch 0 vertex 0
2684 * - attribute 0 of patch 0 vertex 1
2685 * - attribute 0 of patch 0 vertex 2
2687 * - attribute 0 of patch 1 vertex 0
2688 * - attribute 0 of patch 1 vertex 1
2690 * - attribute 1 of patch 0 vertex 0
2691 * - attribute 1 of patch 0 vertex 1
2693 * - per patch attribute 0 of patch 0
2694 * - per patch attribute 0 of patch 1
2697 * Note that every attribute has 4 components.
2699 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2700 LLVMValueRef vertex_index
,
2701 LLVMValueRef param_index
)
2703 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2704 LLVMValueRef param_stride
, constant16
;
2705 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2707 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2708 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2709 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2712 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2714 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2715 vertices_per_patch
, "");
2717 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2720 param_stride
= total_vertices
;
2722 base_addr
= rel_patch_id
;
2723 param_stride
= num_patches
;
2726 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2727 LLVMBuildMul(ctx
->builder
, param_index
,
2728 param_stride
, ""), "");
2730 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2732 if (!vertex_index
) {
2733 LLVMValueRef patch_data_offset
=
2734 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2736 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2737 patch_data_offset
, "");
2742 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2744 unsigned const_index
,
2746 LLVMValueRef vertex_index
,
2747 LLVMValueRef indir_index
)
2749 LLVMValueRef param_index
;
2752 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2755 if (const_index
&& !is_compact
)
2756 param
+= const_index
;
2757 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2759 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2763 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2764 bool is_patch
, uint32_t param
)
2768 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2770 ctx
->tess_outputs_written
|= (1ull << param
);
2774 get_dw_address(struct nir_to_llvm_context
*ctx
,
2775 LLVMValueRef dw_addr
,
2777 unsigned const_index
,
2778 bool compact_const_index
,
2779 LLVMValueRef vertex_index
,
2780 LLVMValueRef stride
,
2781 LLVMValueRef indir_index
)
2786 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2787 LLVMBuildMul(ctx
->builder
,
2793 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2794 LLVMBuildMul(ctx
->builder
, indir_index
,
2795 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2796 else if (const_index
&& !compact_const_index
)
2797 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2798 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2800 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2801 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2803 if (const_index
&& compact_const_index
)
2804 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2805 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2810 load_tcs_input(struct ac_shader_abi
*abi
,
2811 LLVMValueRef vertex_index
,
2812 LLVMValueRef indir_index
,
2813 unsigned const_index
,
2815 unsigned driver_location
,
2817 unsigned num_components
,
2821 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2822 LLVMValueRef dw_addr
, stride
;
2823 LLVMValueRef value
[4], result
;
2824 unsigned param
= shader_io_get_unique_index(location
);
2826 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2827 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2828 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2831 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2832 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2833 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2836 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2841 load_tcs_output(struct nir_to_llvm_context
*ctx
,
2842 nir_intrinsic_instr
*instr
)
2844 LLVMValueRef dw_addr
;
2845 LLVMValueRef stride
= NULL
;
2846 LLVMValueRef value
[4], result
;
2847 LLVMValueRef vertex_index
= NULL
;
2848 LLVMValueRef indir_index
= NULL
;
2849 unsigned const_index
= 0;
2851 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2852 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2853 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2854 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2855 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2856 &const_index
, &indir_index
);
2858 if (!instr
->variables
[0]->var
->data
.patch
) {
2859 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2860 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2862 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2865 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2868 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2869 for (unsigned i
= comp
; i
< instr
->num_components
+ comp
; i
++) {
2870 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2871 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2874 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, instr
->num_components
, comp
);
2875 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2880 store_tcs_output(struct ac_shader_abi
*abi
,
2881 LLVMValueRef vertex_index
,
2882 LLVMValueRef param_index
,
2883 unsigned const_index
,
2885 unsigned driver_location
,
2892 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2893 LLVMValueRef dw_addr
;
2894 LLVMValueRef stride
= NULL
;
2895 LLVMValueRef buf_addr
= NULL
;
2897 bool store_lds
= true;
2900 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2903 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2907 param
= shader_io_get_unique_index(location
);
2908 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2909 is_compact
&& const_index
> 3) {
2915 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2916 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2918 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2921 mark_tess_output(ctx
, is_patch
, param
);
2923 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2925 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2926 vertex_index
, param_index
);
2928 bool is_tess_factor
= false;
2929 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2930 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2931 is_tess_factor
= true;
2933 unsigned base
= is_compact
? const_index
: 0;
2934 for (unsigned chan
= 0; chan
< 8; chan
++) {
2935 if (!(writemask
& (1 << chan
)))
2937 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2939 if (store_lds
|| is_tess_factor
)
2940 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2942 if (!is_tess_factor
&& writemask
!= 0xF)
2943 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2944 buf_addr
, ctx
->oc_lds
,
2945 4 * (base
+ chan
), 1, 0, true, false);
2947 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2951 if (writemask
== 0xF) {
2952 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2953 buf_addr
, ctx
->oc_lds
,
2954 (base
* 4), 1, 0, true, false);
2959 load_tes_input(struct ac_shader_abi
*abi
,
2960 LLVMValueRef vertex_index
,
2961 LLVMValueRef param_index
,
2962 unsigned const_index
,
2964 unsigned driver_location
,
2966 unsigned num_components
,
2970 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2971 LLVMValueRef buf_addr
;
2972 LLVMValueRef result
;
2973 unsigned param
= shader_io_get_unique_index(location
);
2975 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
2980 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2981 is_compact
, vertex_index
, param_index
);
2983 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
2984 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
2986 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
2987 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2988 result
= trim_vector(&ctx
->ac
, result
, num_components
);
2993 load_gs_input(struct ac_shader_abi
*abi
,
2995 unsigned driver_location
,
2997 unsigned num_components
,
2998 unsigned vertex_index
,
2999 unsigned const_index
,
3002 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3003 LLVMValueRef vtx_offset
;
3004 LLVMValueRef args
[9];
3005 unsigned param
, vtx_offset_param
;
3006 LLVMValueRef value
[4], result
;
3008 vtx_offset_param
= vertex_index
;
3009 assert(vtx_offset_param
< 6);
3010 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3011 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3013 param
= shader_io_get_unique_index(location
);
3015 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3016 if (ctx
->ac
.chip_class
>= GFX9
) {
3017 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3018 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3019 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3020 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3022 args
[0] = ctx
->esgs_ring
;
3023 args
[1] = vtx_offset
;
3024 args
[2] = LLVMConstInt(ctx
->ac
.i32
, (param
* 4 + i
+ const_index
) * 256, false);
3025 args
[3] = ctx
->ac
.i32_0
;
3026 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
3027 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
3028 args
[6] = ctx
->ac
.i32_1
; /* GLC */
3029 args
[7] = ctx
->ac
.i32_0
; /* SLC */
3030 args
[8] = ctx
->ac
.i32_0
; /* TFE */
3032 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
3033 ctx
->ac
.i32
, args
, 9,
3034 AC_FUNC_ATTR_READONLY
|
3035 AC_FUNC_ATTR_LEGACY
);
3038 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3044 build_gep_for_deref(struct ac_nir_context
*ctx
,
3045 nir_deref_var
*deref
)
3047 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3048 assert(entry
->data
);
3049 LLVMValueRef val
= entry
->data
;
3050 nir_deref
*tail
= deref
->deref
.child
;
3051 while (tail
!= NULL
) {
3052 LLVMValueRef offset
;
3053 switch (tail
->deref_type
) {
3054 case nir_deref_type_array
: {
3055 nir_deref_array
*array
= nir_deref_as_array(tail
);
3056 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3057 if (array
->deref_array_type
==
3058 nir_deref_array_type_indirect
) {
3059 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3066 case nir_deref_type_struct
: {
3067 nir_deref_struct
*deref_struct
=
3068 nir_deref_as_struct(tail
);
3069 offset
= LLVMConstInt(ctx
->ac
.i32
,
3070 deref_struct
->index
, 0);
3074 unreachable("bad deref type");
3076 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3082 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3083 nir_intrinsic_instr
*instr
)
3085 LLVMValueRef values
[8];
3086 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3087 int ve
= instr
->dest
.ssa
.num_components
;
3088 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3089 LLVMValueRef indir_index
;
3091 unsigned const_index
;
3092 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3093 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3094 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3095 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3096 &const_index
, &indir_index
);
3098 if (instr
->dest
.ssa
.bit_size
== 64)
3101 switch (instr
->variables
[0]->var
->data
.mode
) {
3102 case nir_var_shader_in
:
3103 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3104 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3105 LLVMValueRef result
;
3106 LLVMValueRef vertex_index
= NULL
;
3107 LLVMValueRef indir_index
= NULL
;
3108 unsigned const_index
= 0;
3109 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3110 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3111 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3112 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3114 get_deref_offset(ctx
, instr
->variables
[0],
3115 false, NULL
, is_patch
? NULL
: &vertex_index
,
3116 &const_index
, &indir_index
);
3118 result
= ctx
->abi
->load_tess_inputs(ctx
->abi
, vertex_index
, indir_index
,
3119 const_index
, location
, driver_location
,
3120 instr
->variables
[0]->var
->data
.location_frac
,
3121 instr
->num_components
,
3122 is_patch
, is_compact
);
3123 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3126 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3127 LLVMValueRef indir_index
;
3128 unsigned const_index
, vertex_index
;
3129 get_deref_offset(ctx
, instr
->variables
[0],
3130 false, &vertex_index
, NULL
,
3131 &const_index
, &indir_index
);
3132 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3133 instr
->variables
[0]->var
->data
.driver_location
,
3134 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3135 vertex_index
, const_index
,
3136 nir2llvmtype(ctx
, instr
->variables
[0]->var
->type
));
3139 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3141 unsigned count
= glsl_count_attribute_slots(
3142 instr
->variables
[0]->var
->type
,
3143 ctx
->stage
== MESA_SHADER_VERTEX
);
3145 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3146 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3147 stride
, false, true);
3149 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3153 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3157 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3159 unsigned count
= glsl_count_attribute_slots(
3160 instr
->variables
[0]->var
->type
, false);
3162 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3163 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3164 stride
, true, true);
3166 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3170 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3174 case nir_var_shared
: {
3175 LLVMValueRef address
= build_gep_for_deref(ctx
,
3176 instr
->variables
[0]);
3177 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3178 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3179 get_def_type(ctx
, &instr
->dest
.ssa
),
3182 case nir_var_shader_out
:
3183 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3184 return load_tcs_output(ctx
->nctx
, instr
);
3186 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3188 unsigned count
= glsl_count_attribute_slots(
3189 instr
->variables
[0]->var
->type
, false);
3191 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3192 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3193 stride
, true, true);
3195 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3199 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3200 ctx
->outputs
[idx
+ chan
+ const_index
* stride
],
3206 unreachable("unhandle variable mode");
3208 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3209 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3213 visit_store_var(struct ac_nir_context
*ctx
,
3214 nir_intrinsic_instr
*instr
)
3216 LLVMValueRef temp_ptr
, value
;
3217 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3218 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3219 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3220 int writemask
= instr
->const_index
[0] << comp
;
3221 LLVMValueRef indir_index
;
3222 unsigned const_index
;
3223 get_deref_offset(ctx
, instr
->variables
[0], false,
3224 NULL
, NULL
, &const_index
, &indir_index
);
3226 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3227 int old_writemask
= writemask
;
3229 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3230 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3234 for (unsigned chan
= 0; chan
< 4; chan
++) {
3235 if (old_writemask
& (1 << chan
))
3236 writemask
|= 3u << (2 * chan
);
3240 switch (instr
->variables
[0]->var
->data
.mode
) {
3241 case nir_var_shader_out
:
3243 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3244 LLVMValueRef vertex_index
= NULL
;
3245 LLVMValueRef indir_index
= NULL
;
3246 unsigned const_index
= 0;
3247 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3248 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3249 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3250 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3251 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3253 get_deref_offset(ctx
, instr
->variables
[0],
3254 false, NULL
, is_patch
? NULL
: &vertex_index
,
3255 &const_index
, &indir_index
);
3257 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3258 const_index
, location
, driver_location
,
3259 src
, comp
, is_patch
, is_compact
, writemask
);
3263 for (unsigned chan
= 0; chan
< 8; chan
++) {
3265 if (!(writemask
& (1 << chan
)))
3268 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3270 if (instr
->variables
[0]->var
->data
.compact
)
3273 unsigned count
= glsl_count_attribute_slots(
3274 instr
->variables
[0]->var
->type
, false);
3276 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3277 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3278 stride
, true, true);
3280 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3281 value
, indir_index
, "");
3282 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3283 count
, stride
, tmp_vec
);
3286 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3288 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3293 for (unsigned chan
= 0; chan
< 8; chan
++) {
3294 if (!(writemask
& (1 << chan
)))
3297 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3299 unsigned count
= glsl_count_attribute_slots(
3300 instr
->variables
[0]->var
->type
, false);
3302 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3303 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3306 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3307 value
, indir_index
, "");
3308 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3311 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3313 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3317 case nir_var_shared
: {
3318 int writemask
= instr
->const_index
[0];
3319 LLVMValueRef address
= build_gep_for_deref(ctx
,
3320 instr
->variables
[0]);
3321 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3322 unsigned components
=
3323 glsl_get_vector_elements(
3324 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3325 if (writemask
== (1 << components
) - 1) {
3326 val
= LLVMBuildBitCast(
3327 ctx
->ac
.builder
, val
,
3328 LLVMGetElementType(LLVMTypeOf(address
)), "");
3329 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3331 for (unsigned chan
= 0; chan
< 4; chan
++) {
3332 if (!(writemask
& (1 << chan
)))
3335 LLVMBuildStructGEP(ctx
->ac
.builder
,
3337 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3339 src
= LLVMBuildBitCast(
3340 ctx
->ac
.builder
, src
,
3341 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3342 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3352 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3355 case GLSL_SAMPLER_DIM_BUF
:
3357 case GLSL_SAMPLER_DIM_1D
:
3358 return array
? 2 : 1;
3359 case GLSL_SAMPLER_DIM_2D
:
3360 return array
? 3 : 2;
3361 case GLSL_SAMPLER_DIM_MS
:
3362 return array
? 4 : 3;
3363 case GLSL_SAMPLER_DIM_3D
:
3364 case GLSL_SAMPLER_DIM_CUBE
:
3366 case GLSL_SAMPLER_DIM_RECT
:
3367 case GLSL_SAMPLER_DIM_SUBPASS
:
3369 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3379 /* Adjust the sample index according to FMASK.
3381 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3382 * which is the identity mapping. Each nibble says which physical sample
3383 * should be fetched to get that sample.
3385 * For example, 0x11111100 means there are only 2 samples stored and
3386 * the second sample covers 3/4 of the pixel. When reading samples 0
3387 * and 1, return physical sample 0 (determined by the first two 0s
3388 * in FMASK), otherwise return physical sample 1.
3390 * The sample index should be adjusted as follows:
3391 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3393 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3394 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3395 LLVMValueRef coord_z
,
3396 LLVMValueRef sample_index
,
3397 LLVMValueRef fmask_desc_ptr
)
3399 LLVMValueRef fmask_load_address
[4];
3402 fmask_load_address
[0] = coord_x
;
3403 fmask_load_address
[1] = coord_y
;
3405 fmask_load_address
[2] = coord_z
;
3406 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3409 struct ac_image_args args
= {0};
3411 args
.opcode
= ac_image_load
;
3412 args
.da
= coord_z
? true : false;
3413 args
.resource
= fmask_desc_ptr
;
3415 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3417 res
= ac_build_image_opcode(ctx
, &args
);
3419 res
= ac_to_integer(ctx
, res
);
3420 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3421 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3423 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3427 LLVMValueRef sample_index4
=
3428 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3429 LLVMValueRef shifted_fmask
=
3430 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3431 LLVMValueRef final_sample
=
3432 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3434 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3435 * resource descriptor is 0 (invalid),
3437 LLVMValueRef fmask_desc
=
3438 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3441 LLVMValueRef fmask_word1
=
3442 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3445 LLVMValueRef word1_is_nonzero
=
3446 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3447 fmask_word1
, ctx
->i32_0
, "");
3449 /* Replace the MSAA sample index. */
3451 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3452 final_sample
, sample_index
, "");
3453 return sample_index
;
3456 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3457 const nir_intrinsic_instr
*instr
)
3459 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3460 if(instr
->variables
[0]->deref
.child
)
3461 type
= instr
->variables
[0]->deref
.child
->type
;
3463 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3464 LLVMValueRef coords
[4];
3465 LLVMValueRef masks
[] = {
3466 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3467 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3470 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3473 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3474 bool is_array
= glsl_sampler_type_is_array(type
);
3475 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3476 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3477 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3478 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3479 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3480 count
= image_type_to_components_count(dim
, is_array
);
3483 LLVMValueRef fmask_load_address
[3];
3486 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3487 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3489 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3491 fmask_load_address
[2] = NULL
;
3493 for (chan
= 0; chan
< 2; ++chan
)
3494 fmask_load_address
[chan
] =
3495 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3496 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3497 ctx
->ac
.i32
, ""), "");
3498 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3500 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3501 fmask_load_address
[0],
3502 fmask_load_address
[1],
3503 fmask_load_address
[2],
3505 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3507 if (count
== 1 && !gfx9_1d
) {
3508 if (instr
->src
[0].ssa
->num_components
)
3509 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3516 for (chan
= 0; chan
< count
; ++chan
) {
3517 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3520 for (chan
= 0; chan
< 2; ++chan
)
3521 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3522 ctx
->ac
.i32
, ""), "");
3523 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3529 coords
[2] = coords
[1];
3530 coords
[1] = ctx
->ac
.i32_0
;
3532 coords
[1] = ctx
->ac
.i32_0
;
3537 coords
[count
] = sample_index
;
3542 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3545 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3550 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3551 const nir_intrinsic_instr
*instr
)
3553 LLVMValueRef params
[7];
3555 char intrinsic_name
[64];
3556 const nir_variable
*var
= instr
->variables
[0]->var
;
3557 const struct glsl_type
*type
= var
->type
;
3559 if(instr
->variables
[0]->deref
.child
)
3560 type
= instr
->variables
[0]->deref
.child
->type
;
3562 type
= glsl_without_array(type
);
3563 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3564 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3565 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3566 ctx
->ac
.i32_0
, ""); /* vindex */
3567 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3568 params
[3] = ctx
->ac
.i1false
; /* glc */
3569 params
[4] = ctx
->ac
.i1false
; /* slc */
3570 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3573 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3574 res
= ac_to_integer(&ctx
->ac
, res
);
3576 bool is_da
= glsl_sampler_type_is_array(type
) ||
3577 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3578 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS
||
3579 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS_MS
;
3580 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3581 LLVMValueRef glc
= ctx
->ac
.i1false
;
3582 LLVMValueRef slc
= ctx
->ac
.i1false
;
3584 params
[0] = get_image_coords(ctx
, instr
);
3585 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3586 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3587 if (HAVE_LLVM
<= 0x0309) {
3588 params
[3] = ctx
->ac
.i1false
; /* r128 */
3593 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3600 ac_get_image_intr_name("llvm.amdgcn.image.load",
3601 ctx
->ac
.v4f32
, /* vdata */
3602 LLVMTypeOf(params
[0]), /* coords */
3603 LLVMTypeOf(params
[1]), /* rsrc */
3604 intrinsic_name
, sizeof(intrinsic_name
));
3606 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3607 params
, 7, AC_FUNC_ATTR_READONLY
);
3609 return ac_to_integer(&ctx
->ac
, res
);
3612 static void visit_image_store(struct ac_nir_context
*ctx
,
3613 nir_intrinsic_instr
*instr
)
3615 LLVMValueRef params
[8];
3616 char intrinsic_name
[64];
3617 const nir_variable
*var
= instr
->variables
[0]->var
;
3618 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3619 LLVMValueRef glc
= ctx
->ac
.i1false
;
3620 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3622 glc
= ctx
->ac
.i1true
;
3624 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3625 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3626 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3627 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3628 ctx
->ac
.i32_0
, ""); /* vindex */
3629 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3630 params
[4] = glc
; /* glc */
3631 params
[5] = ctx
->ac
.i1false
; /* slc */
3632 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3635 bool is_da
= glsl_sampler_type_is_array(type
) ||
3636 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3637 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3638 LLVMValueRef slc
= ctx
->ac
.i1false
;
3640 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3641 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3642 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3643 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3644 if (HAVE_LLVM
<= 0x0309) {
3645 params
[4] = ctx
->ac
.i1false
; /* r128 */
3650 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3657 ac_get_image_intr_name("llvm.amdgcn.image.store",
3658 LLVMTypeOf(params
[0]), /* vdata */
3659 LLVMTypeOf(params
[1]), /* coords */
3660 LLVMTypeOf(params
[2]), /* rsrc */
3661 intrinsic_name
, sizeof(intrinsic_name
));
3663 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3669 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3670 const nir_intrinsic_instr
*instr
)
3672 LLVMValueRef params
[7];
3673 int param_count
= 0;
3674 const nir_variable
*var
= instr
->variables
[0]->var
;
3676 const char *atomic_name
;
3677 char intrinsic_name
[41];
3678 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3679 MAYBE_UNUSED
int length
;
3681 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3683 switch (instr
->intrinsic
) {
3684 case nir_intrinsic_image_atomic_add
:
3685 atomic_name
= "add";
3687 case nir_intrinsic_image_atomic_min
:
3688 atomic_name
= is_unsigned
? "umin" : "smin";
3690 case nir_intrinsic_image_atomic_max
:
3691 atomic_name
= is_unsigned
? "umax" : "smax";
3693 case nir_intrinsic_image_atomic_and
:
3694 atomic_name
= "and";
3696 case nir_intrinsic_image_atomic_or
:
3699 case nir_intrinsic_image_atomic_xor
:
3700 atomic_name
= "xor";
3702 case nir_intrinsic_image_atomic_exchange
:
3703 atomic_name
= "swap";
3705 case nir_intrinsic_image_atomic_comp_swap
:
3706 atomic_name
= "cmpswap";
3712 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3713 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3714 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3716 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3717 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3719 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3720 ctx
->ac
.i32_0
, ""); /* vindex */
3721 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3722 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3724 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3725 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3727 char coords_type
[8];
3729 bool da
= glsl_sampler_type_is_array(type
) ||
3730 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3732 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3733 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3735 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3736 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3737 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3739 build_int_type_name(LLVMTypeOf(coords
),
3740 coords_type
, sizeof(coords_type
));
3742 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3743 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3746 assert(length
< sizeof(intrinsic_name
));
3747 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3750 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3751 const nir_intrinsic_instr
*instr
)
3754 const nir_variable
*var
= instr
->variables
[0]->var
;
3755 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3756 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3757 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
;
3758 if(instr
->variables
[0]->deref
.child
)
3759 type
= instr
->variables
[0]->deref
.child
->type
;
3761 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3762 return get_buffer_size(ctx
,
3763 get_sampler_desc(ctx
, instr
->variables
[0],
3764 AC_DESC_BUFFER
, NULL
, true, false), true);
3766 struct ac_image_args args
= { 0 };
3770 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3771 args
.opcode
= ac_image_get_resinfo
;
3772 args
.addr
= ctx
->ac
.i32_0
;
3774 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3776 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3778 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3779 glsl_sampler_type_is_array(type
)) {
3780 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3781 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3782 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3783 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3785 if (ctx
->ac
.chip_class
>= GFX9
&&
3786 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3787 glsl_sampler_type_is_array(type
)) {
3788 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3789 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3796 #define NOOP_WAITCNT 0xf7f
3797 #define LGKM_CNT 0x07f
3798 #define VM_CNT 0xf70
3800 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3801 const nir_intrinsic_instr
*instr
)
3803 unsigned waitcnt
= NOOP_WAITCNT
;
3805 switch (instr
->intrinsic
) {
3806 case nir_intrinsic_memory_barrier
:
3807 case nir_intrinsic_group_memory_barrier
:
3808 waitcnt
&= VM_CNT
& LGKM_CNT
;
3810 case nir_intrinsic_memory_barrier_atomic_counter
:
3811 case nir_intrinsic_memory_barrier_buffer
:
3812 case nir_intrinsic_memory_barrier_image
:
3815 case nir_intrinsic_memory_barrier_shared
:
3816 waitcnt
&= LGKM_CNT
;
3821 if (waitcnt
!= NOOP_WAITCNT
)
3822 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3825 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3827 /* SI only (thanks to a hw bug workaround):
3828 * The real barrier instruction isn’t needed, because an entire patch
3829 * always fits into a single wave.
3831 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3832 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3835 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3836 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3839 static void emit_discard_if(struct ac_nir_context
*ctx
,
3840 const nir_intrinsic_instr
*instr
)
3844 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3845 get_src(ctx
, instr
->src
[0]),
3847 ac_build_kill_if_false(&ctx
->ac
, cond
);
3851 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3853 LLVMValueRef result
;
3854 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3855 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3856 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3858 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3861 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3862 const nir_intrinsic_instr
*instr
)
3864 LLVMValueRef ptr
, result
;
3865 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3866 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3868 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3869 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3870 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3872 LLVMAtomicOrderingSequentiallyConsistent
,
3873 LLVMAtomicOrderingSequentiallyConsistent
,
3876 LLVMAtomicRMWBinOp op
;
3877 switch (instr
->intrinsic
) {
3878 case nir_intrinsic_var_atomic_add
:
3879 op
= LLVMAtomicRMWBinOpAdd
;
3881 case nir_intrinsic_var_atomic_umin
:
3882 op
= LLVMAtomicRMWBinOpUMin
;
3884 case nir_intrinsic_var_atomic_umax
:
3885 op
= LLVMAtomicRMWBinOpUMax
;
3887 case nir_intrinsic_var_atomic_imin
:
3888 op
= LLVMAtomicRMWBinOpMin
;
3890 case nir_intrinsic_var_atomic_imax
:
3891 op
= LLVMAtomicRMWBinOpMax
;
3893 case nir_intrinsic_var_atomic_and
:
3894 op
= LLVMAtomicRMWBinOpAnd
;
3896 case nir_intrinsic_var_atomic_or
:
3897 op
= LLVMAtomicRMWBinOpOr
;
3899 case nir_intrinsic_var_atomic_xor
:
3900 op
= LLVMAtomicRMWBinOpXor
;
3902 case nir_intrinsic_var_atomic_exchange
:
3903 op
= LLVMAtomicRMWBinOpXchg
;
3909 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3910 LLVMAtomicOrderingSequentiallyConsistent
,
3916 #define INTERP_CENTER 0
3917 #define INTERP_CENTROID 1
3918 #define INTERP_SAMPLE 2
3920 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
3921 enum glsl_interp_mode interp
, unsigned location
)
3924 case INTERP_MODE_FLAT
:
3927 case INTERP_MODE_SMOOTH
:
3928 case INTERP_MODE_NONE
:
3929 if (location
== INTERP_CENTER
)
3930 return ctx
->persp_center
;
3931 else if (location
== INTERP_CENTROID
)
3932 return ctx
->persp_centroid
;
3933 else if (location
== INTERP_SAMPLE
)
3934 return ctx
->persp_sample
;
3936 case INTERP_MODE_NOPERSPECTIVE
:
3937 if (location
== INTERP_CENTER
)
3938 return ctx
->linear_center
;
3939 else if (location
== INTERP_CENTROID
)
3940 return ctx
->linear_centroid
;
3941 else if (location
== INTERP_SAMPLE
)
3942 return ctx
->linear_sample
;
3948 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
3949 LLVMValueRef sample_id
)
3951 LLVMValueRef result
;
3952 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
3954 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
3955 const_array(ctx
->ac
.v2f32
, 64), "");
3957 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
3958 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
3963 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
3965 LLVMValueRef values
[2];
3967 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
3968 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
3969 return ac_build_gather_values(&ctx
->ac
, values
, 2);
3972 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
3973 const nir_intrinsic_instr
*instr
)
3975 LLVMValueRef result
[4];
3976 LLVMValueRef interp_param
, attr_number
;
3979 LLVMValueRef src_c0
= NULL
;
3980 LLVMValueRef src_c1
= NULL
;
3981 LLVMValueRef src0
= NULL
;
3982 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
3983 switch (instr
->intrinsic
) {
3984 case nir_intrinsic_interp_var_at_centroid
:
3985 location
= INTERP_CENTROID
;
3987 case nir_intrinsic_interp_var_at_sample
:
3988 case nir_intrinsic_interp_var_at_offset
:
3989 location
= INTERP_CENTER
;
3990 src0
= get_src(ctx
->nir
, instr
->src
[0]);
3996 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
3997 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_0
, ""));
3998 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_1
, ""));
3999 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4000 LLVMValueRef sample_position
;
4001 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4003 /* fetch sample ID */
4004 sample_position
= load_sample_position(ctx
, src0
);
4006 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_0
, "");
4007 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
4008 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_1
, "");
4009 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
4011 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4012 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4014 if (location
== INTERP_CENTER
) {
4015 LLVMValueRef ij_out
[2];
4016 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
4019 * take the I then J parameters, and the DDX/Y for it, and
4020 * calculate the IJ inputs for the interpolator.
4021 * temp1 = ddx * offset/sample.x + I;
4022 * interp_param.I = ddy * offset/sample.y + temp1;
4023 * temp1 = ddx * offset/sample.x + J;
4024 * interp_param.J = ddy * offset/sample.y + temp1;
4026 for (unsigned i
= 0; i
< 2; i
++) {
4027 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4028 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4029 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
4030 ddxy_out
, ix_ll
, "");
4031 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
4032 ddxy_out
, iy_ll
, "");
4033 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
4034 interp_param
, ix_ll
, "");
4035 LLVMValueRef temp1
, temp2
;
4037 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
4040 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
4041 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
4043 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
4044 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
4046 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
4047 temp2
, ctx
->ac
.i32
, "");
4049 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4053 for (chan
= 0; chan
< 4; chan
++) {
4054 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4057 interp_param
= LLVMBuildBitCast(ctx
->builder
,
4058 interp_param
, ctx
->ac
.v2f32
, "");
4059 LLVMValueRef i
= LLVMBuildExtractElement(
4060 ctx
->builder
, interp_param
, ctx
->ac
.i32_0
, "");
4061 LLVMValueRef j
= LLVMBuildExtractElement(
4062 ctx
->builder
, interp_param
, ctx
->ac
.i32_1
, "");
4064 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4065 llvm_chan
, attr_number
,
4066 ctx
->prim_mask
, i
, j
);
4068 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4069 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4070 llvm_chan
, attr_number
,
4074 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4075 instr
->variables
[0]->var
->data
.location_frac
);
4079 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4081 LLVMValueRef gs_next_vertex
;
4082 LLVMValueRef can_emit
;
4084 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4086 /* Write vertex attribute values to GSVS ring */
4087 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4088 ctx
->gs_next_vertex
,
4091 /* If this thread has already emitted the declared maximum number of
4092 * vertices, kill it: excessive vertex emissions are not supposed to
4093 * have any effect, and GS threads have no externally observable
4094 * effects other than emitting vertices.
4096 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4097 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4098 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4100 /* loop num outputs */
4102 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4103 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4108 if (!(ctx
->output_mask
& (1ull << i
)))
4111 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4112 /* pack clip and cull into a single set of slots */
4113 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4117 for (unsigned j
= 0; j
< length
; j
++) {
4118 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4120 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4121 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4122 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4124 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4126 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4128 voffset
, ctx
->gs2vs_offset
, 0,
4134 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4136 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4138 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4142 visit_end_primitive(struct nir_to_llvm_context
*ctx
,
4143 const nir_intrinsic_instr
*instr
)
4145 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4149 load_tess_coord(struct ac_shader_abi
*abi
, LLVMTypeRef type
,
4150 unsigned num_components
)
4152 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4154 LLVMValueRef coord
[4] = {
4161 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4162 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4163 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4165 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, num_components
);
4166 return LLVMBuildBitCast(ctx
->builder
, result
, type
, "");
4170 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4172 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4173 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4176 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4177 nir_intrinsic_instr
*instr
)
4179 LLVMValueRef result
= NULL
;
4181 switch (instr
->intrinsic
) {
4182 case nir_intrinsic_load_work_group_id
: {
4183 LLVMValueRef values
[3];
4185 for (int i
= 0; i
< 3; i
++) {
4186 values
[i
] = ctx
->nctx
->workgroup_ids
[i
] ?
4187 ctx
->nctx
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4190 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4193 case nir_intrinsic_load_base_vertex
: {
4194 result
= ctx
->abi
->base_vertex
;
4197 case nir_intrinsic_load_vertex_id_zero_base
: {
4198 result
= ctx
->abi
->vertex_id
;
4201 case nir_intrinsic_load_local_invocation_id
: {
4202 result
= ctx
->nctx
->local_invocation_ids
;
4205 case nir_intrinsic_load_base_instance
:
4206 result
= ctx
->abi
->start_instance
;
4208 case nir_intrinsic_load_draw_id
:
4209 result
= ctx
->abi
->draw_id
;
4211 case nir_intrinsic_load_view_index
:
4212 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4214 case nir_intrinsic_load_invocation_id
:
4215 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4216 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4218 result
= ctx
->abi
->gs_invocation_id
;
4220 case nir_intrinsic_load_primitive_id
:
4221 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4222 result
= ctx
->abi
->gs_prim_id
;
4223 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4224 result
= ctx
->abi
->tcs_patch_id
;
4225 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4226 result
= ctx
->abi
->tes_patch_id
;
4228 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4230 case nir_intrinsic_load_sample_id
:
4231 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4233 case nir_intrinsic_load_sample_pos
:
4234 result
= load_sample_pos(ctx
);
4236 case nir_intrinsic_load_sample_mask_in
:
4237 result
= ctx
->abi
->sample_coverage
;
4239 case nir_intrinsic_load_frag_coord
: {
4240 LLVMValueRef values
[4] = {
4241 ctx
->abi
->frag_pos
[0],
4242 ctx
->abi
->frag_pos
[1],
4243 ctx
->abi
->frag_pos
[2],
4244 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4246 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4249 case nir_intrinsic_load_front_face
:
4250 result
= ctx
->abi
->front_face
;
4252 case nir_intrinsic_load_instance_id
:
4253 result
= ctx
->abi
->instance_id
;
4255 case nir_intrinsic_load_num_work_groups
:
4256 result
= ctx
->nctx
->num_work_groups
;
4258 case nir_intrinsic_load_local_invocation_index
:
4259 result
= visit_load_local_invocation_index(ctx
->nctx
);
4261 case nir_intrinsic_load_push_constant
:
4262 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4264 case nir_intrinsic_vulkan_resource_index
:
4265 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4267 case nir_intrinsic_vulkan_resource_reindex
:
4268 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4270 case nir_intrinsic_store_ssbo
:
4271 visit_store_ssbo(ctx
, instr
);
4273 case nir_intrinsic_load_ssbo
:
4274 result
= visit_load_buffer(ctx
, instr
);
4276 case nir_intrinsic_ssbo_atomic_add
:
4277 case nir_intrinsic_ssbo_atomic_imin
:
4278 case nir_intrinsic_ssbo_atomic_umin
:
4279 case nir_intrinsic_ssbo_atomic_imax
:
4280 case nir_intrinsic_ssbo_atomic_umax
:
4281 case nir_intrinsic_ssbo_atomic_and
:
4282 case nir_intrinsic_ssbo_atomic_or
:
4283 case nir_intrinsic_ssbo_atomic_xor
:
4284 case nir_intrinsic_ssbo_atomic_exchange
:
4285 case nir_intrinsic_ssbo_atomic_comp_swap
:
4286 result
= visit_atomic_ssbo(ctx
, instr
);
4288 case nir_intrinsic_load_ubo
:
4289 result
= visit_load_ubo_buffer(ctx
, instr
);
4291 case nir_intrinsic_get_buffer_size
:
4292 result
= visit_get_buffer_size(ctx
, instr
);
4294 case nir_intrinsic_load_var
:
4295 result
= visit_load_var(ctx
, instr
);
4297 case nir_intrinsic_store_var
:
4298 visit_store_var(ctx
, instr
);
4300 case nir_intrinsic_image_load
:
4301 result
= visit_image_load(ctx
, instr
);
4303 case nir_intrinsic_image_store
:
4304 visit_image_store(ctx
, instr
);
4306 case nir_intrinsic_image_atomic_add
:
4307 case nir_intrinsic_image_atomic_min
:
4308 case nir_intrinsic_image_atomic_max
:
4309 case nir_intrinsic_image_atomic_and
:
4310 case nir_intrinsic_image_atomic_or
:
4311 case nir_intrinsic_image_atomic_xor
:
4312 case nir_intrinsic_image_atomic_exchange
:
4313 case nir_intrinsic_image_atomic_comp_swap
:
4314 result
= visit_image_atomic(ctx
, instr
);
4316 case nir_intrinsic_image_size
:
4317 result
= visit_image_size(ctx
, instr
);
4319 case nir_intrinsic_discard
:
4320 ac_build_intrinsic(&ctx
->ac
, "llvm.AMDGPU.kilp",
4321 LLVMVoidTypeInContext(ctx
->ac
.context
),
4322 NULL
, 0, AC_FUNC_ATTR_LEGACY
);
4324 case nir_intrinsic_discard_if
:
4325 emit_discard_if(ctx
, instr
);
4327 case nir_intrinsic_memory_barrier
:
4328 case nir_intrinsic_group_memory_barrier
:
4329 case nir_intrinsic_memory_barrier_atomic_counter
:
4330 case nir_intrinsic_memory_barrier_buffer
:
4331 case nir_intrinsic_memory_barrier_image
:
4332 case nir_intrinsic_memory_barrier_shared
:
4333 emit_membar(ctx
->nctx
, instr
);
4335 case nir_intrinsic_barrier
:
4336 emit_barrier(&ctx
->ac
, ctx
->stage
);
4338 case nir_intrinsic_var_atomic_add
:
4339 case nir_intrinsic_var_atomic_imin
:
4340 case nir_intrinsic_var_atomic_umin
:
4341 case nir_intrinsic_var_atomic_imax
:
4342 case nir_intrinsic_var_atomic_umax
:
4343 case nir_intrinsic_var_atomic_and
:
4344 case nir_intrinsic_var_atomic_or
:
4345 case nir_intrinsic_var_atomic_xor
:
4346 case nir_intrinsic_var_atomic_exchange
:
4347 case nir_intrinsic_var_atomic_comp_swap
:
4348 result
= visit_var_atomic(ctx
->nctx
, instr
);
4350 case nir_intrinsic_interp_var_at_centroid
:
4351 case nir_intrinsic_interp_var_at_sample
:
4352 case nir_intrinsic_interp_var_at_offset
:
4353 result
= visit_interp(ctx
->nctx
, instr
);
4355 case nir_intrinsic_emit_vertex
:
4356 assert(instr
->const_index
[0] == 0);
4357 ctx
->abi
->emit_vertex(ctx
->abi
, 0, ctx
->outputs
);
4359 case nir_intrinsic_end_primitive
:
4360 visit_end_primitive(ctx
->nctx
, instr
);
4362 case nir_intrinsic_load_tess_coord
: {
4363 LLVMTypeRef type
= ctx
->nctx
?
4364 get_def_type(ctx
->nctx
->nir
, &instr
->dest
.ssa
) :
4366 result
= ctx
->abi
->load_tess_coord(ctx
->abi
, type
, instr
->num_components
);
4369 case nir_intrinsic_load_tess_level_outer
:
4370 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4372 case nir_intrinsic_load_tess_level_inner
:
4373 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4375 case nir_intrinsic_load_patch_vertices_in
:
4376 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4379 fprintf(stderr
, "Unknown intrinsic: ");
4380 nir_print_instr(&instr
->instr
, stderr
);
4381 fprintf(stderr
, "\n");
4385 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4389 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4390 LLVMValueRef buffer_ptr
, bool write
)
4392 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4394 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4395 ctx
->shader_info
->fs
.writes_memory
= true;
4397 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4400 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4402 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4404 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4407 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4408 unsigned descriptor_set
,
4409 unsigned base_index
,
4410 unsigned constant_index
,
4412 enum ac_descriptor_type desc_type
,
4413 bool image
, bool write
)
4415 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4416 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4417 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4418 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4419 unsigned offset
= binding
->offset
;
4420 unsigned stride
= binding
->size
;
4422 LLVMBuilderRef builder
= ctx
->builder
;
4425 assert(base_index
< layout
->binding_count
);
4427 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4428 ctx
->shader_info
->fs
.writes_memory
= true;
4430 switch (desc_type
) {
4432 type
= ctx
->ac
.v8i32
;
4436 type
= ctx
->ac
.v8i32
;
4440 case AC_DESC_SAMPLER
:
4441 type
= ctx
->ac
.v4i32
;
4442 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4447 case AC_DESC_BUFFER
:
4448 type
= ctx
->ac
.v4i32
;
4452 unreachable("invalid desc_type\n");
4455 offset
+= constant_index
* stride
;
4457 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4458 (!index
|| binding
->immutable_samplers_equal
)) {
4459 if (binding
->immutable_samplers_equal
)
4462 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4464 LLVMValueRef constants
[] = {
4465 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4466 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4467 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4468 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4470 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4473 assert(stride
% type_size
== 0);
4476 index
= ctx
->ac
.i32_0
;
4478 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4480 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4481 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4483 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4486 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4487 const nir_deref_var
*deref
,
4488 enum ac_descriptor_type desc_type
,
4489 const nir_tex_instr
*tex_instr
,
4490 bool image
, bool write
)
4492 LLVMValueRef index
= NULL
;
4493 unsigned constant_index
= 0;
4494 unsigned descriptor_set
;
4495 unsigned base_index
;
4498 assert(tex_instr
&& !image
);
4500 base_index
= tex_instr
->sampler_index
;
4502 const nir_deref
*tail
= &deref
->deref
;
4503 while (tail
->child
) {
4504 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4505 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4510 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4512 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4513 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4515 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4516 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4521 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4524 constant_index
+= child
->base_offset
* array_size
;
4526 tail
= &child
->deref
;
4528 descriptor_set
= deref
->var
->data
.descriptor_set
;
4529 base_index
= deref
->var
->data
.binding
;
4532 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4535 constant_index
, index
,
4536 desc_type
, image
, write
);
4539 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4540 struct ac_image_args
*args
,
4541 const nir_tex_instr
*instr
,
4543 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4544 LLVMValueRef
*param
, unsigned count
,
4547 unsigned is_rect
= 0;
4548 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4550 if (op
== nir_texop_lod
)
4552 /* Pad to power of two vector */
4553 while (count
< util_next_power_of_two(count
))
4554 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4557 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4559 args
->addr
= param
[0];
4561 args
->resource
= res_ptr
;
4562 args
->sampler
= samp_ptr
;
4564 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4565 args
->addr
= param
[0];
4569 args
->dmask
= dmask
;
4570 args
->unorm
= is_rect
;
4574 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4577 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4578 * filtering manually. The driver sets img7 to a mask clearing
4579 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4580 * s_and_b32 samp0, samp0, img7
4583 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4585 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4586 LLVMValueRef res
, LLVMValueRef samp
)
4588 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4589 LLVMValueRef img7
, samp0
;
4591 if (ctx
->ac
.chip_class
>= VI
)
4594 img7
= LLVMBuildExtractElement(builder
, res
,
4595 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4596 samp0
= LLVMBuildExtractElement(builder
, samp
,
4597 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4598 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4599 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4600 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4603 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4604 nir_tex_instr
*instr
,
4605 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4606 LLVMValueRef
*fmask_ptr
)
4608 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4609 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4611 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4614 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4616 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4617 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4618 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4620 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4621 instr
->op
== nir_texop_samples_identical
))
4622 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4625 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4628 coord
= ac_to_float(ctx
, coord
);
4629 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4630 coord
= ac_to_integer(ctx
, coord
);
4634 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4636 LLVMValueRef result
= NULL
;
4637 struct ac_image_args args
= { 0 };
4638 unsigned dmask
= 0xf;
4639 LLVMValueRef address
[16];
4640 LLVMValueRef coords
[5];
4641 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4642 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4643 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4644 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4645 LLVMValueRef derivs
[6];
4646 unsigned chan
, count
= 0;
4647 unsigned const_src
= 0, num_deriv_comp
= 0;
4648 bool lod_is_zero
= false;
4650 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4652 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4653 switch (instr
->src
[i
].src_type
) {
4654 case nir_tex_src_coord
:
4655 coord
= get_src(ctx
, instr
->src
[i
].src
);
4657 case nir_tex_src_projector
:
4659 case nir_tex_src_comparator
:
4660 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4662 case nir_tex_src_offset
:
4663 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4666 case nir_tex_src_bias
:
4667 bias
= get_src(ctx
, instr
->src
[i
].src
);
4669 case nir_tex_src_lod
: {
4670 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4672 if (val
&& val
->i32
[0] == 0)
4674 lod
= get_src(ctx
, instr
->src
[i
].src
);
4677 case nir_tex_src_ms_index
:
4678 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4680 case nir_tex_src_ms_mcs
:
4682 case nir_tex_src_ddx
:
4683 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4684 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4686 case nir_tex_src_ddy
:
4687 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4689 case nir_tex_src_texture_offset
:
4690 case nir_tex_src_sampler_offset
:
4691 case nir_tex_src_plane
:
4697 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4698 result
= get_buffer_size(ctx
, res_ptr
, true);
4702 if (instr
->op
== nir_texop_texture_samples
) {
4703 LLVMValueRef res
, samples
, is_msaa
;
4704 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4705 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4706 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4707 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4708 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4709 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4710 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4711 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4712 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4714 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4715 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4716 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4717 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4718 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4720 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4727 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4728 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4730 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4731 LLVMValueRef offset
[3], pack
;
4732 for (chan
= 0; chan
< 3; ++chan
)
4733 offset
[chan
] = ctx
->ac
.i32_0
;
4736 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4737 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4738 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4739 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4741 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4742 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4744 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4745 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4746 address
[count
++] = pack
;
4749 /* pack LOD bias value */
4750 if (instr
->op
== nir_texop_txb
&& bias
) {
4751 address
[count
++] = bias
;
4754 /* Pack depth comparison value */
4755 if (instr
->is_shadow
&& comparator
) {
4756 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4757 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4759 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4760 * so the depth comparison value isn't clamped for Z16 and
4761 * Z24 anymore. Do it manually here.
4763 * It's unnecessary if the original texture format was
4764 * Z32_FLOAT, but we don't know that here.
4766 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4767 z
= ac_build_clamp(&ctx
->ac
, z
);
4769 address
[count
++] = z
;
4772 /* pack derivatives */
4774 int num_src_deriv_channels
, num_dest_deriv_channels
;
4775 switch (instr
->sampler_dim
) {
4776 case GLSL_SAMPLER_DIM_3D
:
4777 case GLSL_SAMPLER_DIM_CUBE
:
4779 num_src_deriv_channels
= 3;
4780 num_dest_deriv_channels
= 3;
4782 case GLSL_SAMPLER_DIM_2D
:
4784 num_src_deriv_channels
= 2;
4785 num_dest_deriv_channels
= 2;
4788 case GLSL_SAMPLER_DIM_1D
:
4789 num_src_deriv_channels
= 1;
4790 if (ctx
->ac
.chip_class
>= GFX9
) {
4791 num_dest_deriv_channels
= 2;
4794 num_dest_deriv_channels
= 1;
4800 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4801 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4802 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4804 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4805 derivs
[i
] = ctx
->ac
.f32_0
;
4806 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4810 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4811 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4812 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4813 if (instr
->coord_components
== 3)
4814 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4815 ac_prepare_cube_coords(&ctx
->ac
,
4816 instr
->op
== nir_texop_txd
, instr
->is_array
,
4817 instr
->op
== nir_texop_lod
, coords
, derivs
);
4823 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4824 address
[count
++] = derivs
[i
];
4827 /* Pack texture coordinates */
4829 address
[count
++] = coords
[0];
4830 if (instr
->coord_components
> 1) {
4831 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4832 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4834 address
[count
++] = coords
[1];
4836 if (instr
->coord_components
> 2) {
4837 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4838 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4839 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4840 instr
->op
!= nir_texop_txf
) {
4841 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4843 address
[count
++] = coords
[2];
4846 if (ctx
->ac
.chip_class
>= GFX9
) {
4847 LLVMValueRef filler
;
4848 if (instr
->op
== nir_texop_txf
)
4849 filler
= ctx
->ac
.i32_0
;
4851 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4853 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4854 /* No nir_texop_lod, because it does not take a slice
4855 * even with array textures. */
4856 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4857 address
[count
] = address
[count
- 1];
4858 address
[count
- 1] = filler
;
4861 address
[count
++] = filler
;
4867 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
4868 instr
->op
== nir_texop_txf
)) {
4869 address
[count
++] = lod
;
4870 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
4871 address
[count
++] = sample_index
;
4872 } else if(instr
->op
== nir_texop_txs
) {
4875 address
[count
++] = lod
;
4877 address
[count
++] = ctx
->ac
.i32_0
;
4880 for (chan
= 0; chan
< count
; chan
++) {
4881 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4882 address
[chan
], ctx
->ac
.i32
, "");
4885 if (instr
->op
== nir_texop_samples_identical
) {
4886 LLVMValueRef txf_address
[4];
4887 struct ac_image_args txf_args
= { 0 };
4888 unsigned txf_count
= count
;
4889 memcpy(txf_address
, address
, sizeof(txf_address
));
4891 if (!instr
->is_array
)
4892 txf_address
[2] = ctx
->ac
.i32_0
;
4893 txf_address
[3] = ctx
->ac
.i32_0
;
4895 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
4897 txf_address
, txf_count
, 0xf);
4899 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
4901 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4902 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
4906 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
4907 instr
->op
!= nir_texop_txs
) {
4908 unsigned sample_chan
= instr
->is_array
? 3 : 2;
4909 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
4912 instr
->is_array
? address
[2] : NULL
,
4913 address
[sample_chan
],
4917 if (offsets
&& instr
->op
== nir_texop_txf
) {
4918 nir_const_value
*const_offset
=
4919 nir_src_as_const_value(instr
->src
[const_src
].src
);
4920 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
4921 assert(const_offset
);
4922 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
4923 if (num_offsets
> 2)
4924 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
4925 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
4926 if (num_offsets
> 1)
4927 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
4928 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
4929 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
4930 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
4934 /* TODO TG4 support */
4935 if (instr
->op
== nir_texop_tg4
) {
4936 if (instr
->is_shadow
)
4939 dmask
= 1 << instr
->component
;
4941 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
4942 res_ptr
, samp_ptr
, address
, count
, dmask
);
4944 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
4946 if (instr
->op
== nir_texop_query_levels
)
4947 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4948 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
4949 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
4950 instr
->op
!= nir_texop_tg4
)
4951 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4952 else if (instr
->op
== nir_texop_txs
&&
4953 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4955 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4956 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
4957 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4958 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
4959 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
4960 } else if (ctx
->ac
.chip_class
>= GFX9
&&
4961 instr
->op
== nir_texop_txs
&&
4962 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
4964 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4965 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4966 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
4968 } else if (instr
->dest
.ssa
.num_components
!= 4)
4969 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
4973 assert(instr
->dest
.is_ssa
);
4974 result
= ac_to_integer(&ctx
->ac
, result
);
4975 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4980 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
4982 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
4983 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
4985 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4986 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
4989 static void visit_post_phi(struct ac_nir_context
*ctx
,
4990 nir_phi_instr
*instr
,
4991 LLVMValueRef llvm_phi
)
4993 nir_foreach_phi_src(src
, instr
) {
4994 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
4995 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
4997 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5001 static void phi_post_pass(struct ac_nir_context
*ctx
)
5003 struct hash_entry
*entry
;
5004 hash_table_foreach(ctx
->phis
, entry
) {
5005 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5006 (LLVMValueRef
)entry
->data
);
5011 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5012 const nir_ssa_undef_instr
*instr
)
5014 unsigned num_components
= instr
->def
.num_components
;
5017 if (num_components
== 1)
5018 undef
= LLVMGetUndef(ctx
->ac
.i32
);
5020 undef
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, num_components
));
5022 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5025 static void visit_jump(struct ac_nir_context
*ctx
,
5026 const nir_jump_instr
*instr
)
5028 switch (instr
->type
) {
5029 case nir_jump_break
:
5030 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5031 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5033 case nir_jump_continue
:
5034 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5035 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5038 fprintf(stderr
, "Unknown NIR jump instr: ");
5039 nir_print_instr(&instr
->instr
, stderr
);
5040 fprintf(stderr
, "\n");
5045 static void visit_cf_list(struct ac_nir_context
*ctx
,
5046 struct exec_list
*list
);
5048 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5050 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5051 nir_foreach_instr(instr
, block
)
5053 switch (instr
->type
) {
5054 case nir_instr_type_alu
:
5055 visit_alu(ctx
, nir_instr_as_alu(instr
));
5057 case nir_instr_type_load_const
:
5058 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5060 case nir_instr_type_intrinsic
:
5061 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5063 case nir_instr_type_tex
:
5064 visit_tex(ctx
, nir_instr_as_tex(instr
));
5066 case nir_instr_type_phi
:
5067 visit_phi(ctx
, nir_instr_as_phi(instr
));
5069 case nir_instr_type_ssa_undef
:
5070 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5072 case nir_instr_type_jump
:
5073 visit_jump(ctx
, nir_instr_as_jump(instr
));
5076 fprintf(stderr
, "Unknown NIR instr type: ");
5077 nir_print_instr(instr
, stderr
);
5078 fprintf(stderr
, "\n");
5083 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5086 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5088 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5090 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5091 LLVMBasicBlockRef merge_block
=
5092 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5093 LLVMBasicBlockRef if_block
=
5094 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5095 LLVMBasicBlockRef else_block
= merge_block
;
5096 if (!exec_list_is_empty(&if_stmt
->else_list
))
5097 else_block
= LLVMAppendBasicBlockInContext(
5098 ctx
->ac
.context
, fn
, "");
5100 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5102 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5104 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5105 visit_cf_list(ctx
, &if_stmt
->then_list
);
5106 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5107 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5109 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5110 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5111 visit_cf_list(ctx
, &if_stmt
->else_list
);
5112 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5113 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5116 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5119 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5121 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5122 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5123 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5125 ctx
->continue_block
=
5126 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5128 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5130 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5131 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5132 visit_cf_list(ctx
, &loop
->body
);
5134 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5135 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5136 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5138 ctx
->continue_block
= continue_parent
;
5139 ctx
->break_block
= break_parent
;
5142 static void visit_cf_list(struct ac_nir_context
*ctx
,
5143 struct exec_list
*list
)
5145 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5147 switch (node
->type
) {
5148 case nir_cf_node_block
:
5149 visit_block(ctx
, nir_cf_node_as_block(node
));
5152 case nir_cf_node_if
:
5153 visit_if(ctx
, nir_cf_node_as_if(node
));
5156 case nir_cf_node_loop
:
5157 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5167 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5168 struct nir_variable
*variable
)
5170 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5171 LLVMValueRef t_offset
;
5172 LLVMValueRef t_list
;
5174 LLVMValueRef buffer_index
;
5175 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5176 int idx
= variable
->data
.location
;
5177 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5179 variable
->data
.driver_location
= idx
* 4;
5181 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << index
)) {
5182 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5183 ctx
->abi
.start_instance
, "");
5184 if (ctx
->options
->key
.vs
.as_ls
) {
5185 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5186 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5188 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5189 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5192 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5193 ctx
->abi
.base_vertex
, "");
5195 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5196 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5198 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5200 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5205 for (unsigned chan
= 0; chan
< 4; chan
++) {
5206 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5207 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5208 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5209 input
, llvm_chan
, ""));
5214 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5216 LLVMValueRef interp_param
,
5217 LLVMValueRef prim_mask
,
5218 LLVMValueRef result
[4])
5220 LLVMValueRef attr_number
;
5223 bool interp
= interp_param
!= NULL
;
5225 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5227 /* fs.constant returns the param from the middle vertex, so it's not
5228 * really useful for flat shading. It's meant to be used for custom
5229 * interpolation (but the intrinsic can't fetch from the other two
5232 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5233 * to do the right thing. The only reason we use fs.constant is that
5234 * fs.interp cannot be used on integers, because they can be equal
5238 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5241 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5243 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5247 for (chan
= 0; chan
< 4; chan
++) {
5248 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5251 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5256 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5257 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5266 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5267 struct nir_variable
*variable
)
5269 int idx
= variable
->data
.location
;
5270 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5271 LLVMValueRef interp
;
5273 variable
->data
.driver_location
= idx
* 4;
5274 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5276 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5277 unsigned interp_type
;
5278 if (variable
->data
.sample
) {
5279 interp_type
= INTERP_SAMPLE
;
5280 ctx
->shader_info
->info
.ps
.force_persample
= true;
5281 } else if (variable
->data
.centroid
)
5282 interp_type
= INTERP_CENTROID
;
5284 interp_type
= INTERP_CENTER
;
5286 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5290 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5291 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5296 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5297 struct nir_shader
*nir
) {
5298 nir_foreach_variable(variable
, &nir
->inputs
)
5299 handle_vs_input_decl(ctx
, variable
);
5303 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5304 struct nir_shader
*nir
)
5306 if (!ctx
->options
->key
.fs
.multisample
)
5309 bool uses_center
= false;
5310 bool uses_centroid
= false;
5311 nir_foreach_variable(variable
, &nir
->inputs
) {
5312 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5313 variable
->data
.sample
)
5316 if (variable
->data
.centroid
)
5317 uses_centroid
= true;
5322 if (uses_center
&& uses_centroid
) {
5323 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5324 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5325 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5330 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5331 struct nir_shader
*nir
)
5333 prepare_interp_optimize(ctx
, nir
);
5335 nir_foreach_variable(variable
, &nir
->inputs
)
5336 handle_fs_input_decl(ctx
, variable
);
5340 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5341 ctx
->shader_info
->info
.needs_multiview_view_index
)
5342 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5344 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5345 LLVMValueRef interp_param
;
5346 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5348 if (!(ctx
->input_mask
& (1ull << i
)))
5351 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5352 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5353 interp_param
= *inputs
;
5354 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5358 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5360 } else if (i
== VARYING_SLOT_POS
) {
5361 for(int i
= 0; i
< 3; ++i
)
5362 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5364 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5365 ctx
->abi
.frag_pos
[3]);
5368 ctx
->shader_info
->fs
.num_interp
= index
;
5369 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5370 ctx
->shader_info
->fs
.has_pcoord
= true;
5371 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5372 ctx
->shader_info
->fs
.prim_id_input
= true;
5373 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5374 ctx
->shader_info
->fs
.layer_input
= true;
5375 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5377 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5378 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5382 ac_build_alloca(struct ac_llvm_context
*ac
,
5386 LLVMBuilderRef builder
= ac
->builder
;
5387 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5388 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5389 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5390 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5391 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5395 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5397 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5400 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5401 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5403 LLVMDisposeBuilder(first_builder
);
5408 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5412 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5413 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5418 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5419 struct nir_variable
*variable
,
5420 struct nir_shader
*shader
,
5421 gl_shader_stage stage
)
5423 int idx
= variable
->data
.location
+ variable
->data
.index
;
5424 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5425 uint64_t mask_attribs
;
5427 variable
->data
.driver_location
= idx
* 4;
5429 /* tess ctrl has it's own load/store paths for outputs */
5430 if (stage
== MESA_SHADER_TESS_CTRL
)
5433 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5434 if (stage
== MESA_SHADER_VERTEX
||
5435 stage
== MESA_SHADER_TESS_EVAL
||
5436 stage
== MESA_SHADER_GEOMETRY
) {
5437 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5438 int length
= shader
->info
.clip_distance_array_size
+
5439 shader
->info
.cull_distance_array_size
;
5440 if (stage
== MESA_SHADER_VERTEX
) {
5441 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5442 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5444 if (stage
== MESA_SHADER_TESS_EVAL
) {
5445 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5446 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5453 mask_attribs
= 1ull << idx
;
5457 ctx
->output_mask
|= mask_attribs
;
5461 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5462 struct nir_shader
*nir
,
5463 struct nir_variable
*variable
)
5465 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5466 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5468 /* tess ctrl has it's own load/store paths for outputs */
5469 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5472 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5473 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5474 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5475 int idx
= variable
->data
.location
+ variable
->data
.index
;
5476 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5477 int length
= nir
->info
.clip_distance_array_size
+
5478 nir
->info
.cull_distance_array_size
;
5487 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5488 for (unsigned chan
= 0; chan
< 4; chan
++) {
5489 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5490 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5496 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5497 enum glsl_base_type type
)
5501 case GLSL_TYPE_UINT
:
5502 case GLSL_TYPE_BOOL
:
5503 case GLSL_TYPE_SUBROUTINE
:
5505 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5507 case GLSL_TYPE_INT64
:
5508 case GLSL_TYPE_UINT64
:
5510 case GLSL_TYPE_DOUBLE
:
5513 unreachable("unknown GLSL type");
5518 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5519 const struct glsl_type
*type
)
5521 if (glsl_type_is_scalar(type
)) {
5522 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5525 if (glsl_type_is_vector(type
)) {
5526 return LLVMVectorType(
5527 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5528 glsl_get_vector_elements(type
));
5531 if (glsl_type_is_matrix(type
)) {
5532 return LLVMArrayType(
5533 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5534 glsl_get_matrix_columns(type
));
5537 if (glsl_type_is_array(type
)) {
5538 return LLVMArrayType(
5539 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5540 glsl_get_length(type
));
5543 assert(glsl_type_is_struct(type
));
5545 LLVMTypeRef member_types
[glsl_get_length(type
)];
5547 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5549 glsl_to_llvm_type(ctx
,
5550 glsl_get_struct_field(type
, i
));
5553 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5554 glsl_get_length(type
), false);
5558 setup_locals(struct ac_nir_context
*ctx
,
5559 struct nir_function
*func
)
5562 ctx
->num_locals
= 0;
5563 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5564 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5565 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5566 variable
->data
.location_frac
= 0;
5567 ctx
->num_locals
+= attrib_count
;
5569 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5573 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5574 for (j
= 0; j
< 4; j
++) {
5575 ctx
->locals
[i
* 4 + j
] =
5576 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5582 setup_shared(struct ac_nir_context
*ctx
,
5583 struct nir_shader
*nir
)
5585 nir_foreach_variable(variable
, &nir
->shared
) {
5586 LLVMValueRef shared
=
5587 LLVMAddGlobalInAddressSpace(
5588 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5589 variable
->name
? variable
->name
: "",
5591 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5596 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5598 v
= ac_to_float(ctx
, v
);
5599 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5600 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5604 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5605 LLVMValueRef src0
, LLVMValueRef src1
)
5607 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5608 LLVMValueRef comp
[2];
5610 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5611 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5612 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5613 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5616 /* Initialize arguments for the shader export intrinsic */
5618 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5619 LLVMValueRef
*values
,
5621 struct ac_export_args
*args
)
5623 /* Default is 0xf. Adjusted below depending on the format. */
5624 args
->enabled_channels
= 0xf;
5626 /* Specify whether the EXEC mask represents the valid mask */
5627 args
->valid_mask
= 0;
5629 /* Specify whether this is the last export */
5632 /* Specify the target we are exporting */
5633 args
->target
= target
;
5635 args
->compr
= false;
5636 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5637 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5638 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5639 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5644 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5645 LLVMValueRef val
[4];
5646 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5647 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5648 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5649 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5651 switch(col_format
) {
5652 case V_028714_SPI_SHADER_ZERO
:
5653 args
->enabled_channels
= 0; /* writemask */
5654 args
->target
= V_008DFC_SQ_EXP_NULL
;
5657 case V_028714_SPI_SHADER_32_R
:
5658 args
->enabled_channels
= 1;
5659 args
->out
[0] = values
[0];
5662 case V_028714_SPI_SHADER_32_GR
:
5663 args
->enabled_channels
= 0x3;
5664 args
->out
[0] = values
[0];
5665 args
->out
[1] = values
[1];
5668 case V_028714_SPI_SHADER_32_AR
:
5669 args
->enabled_channels
= 0x9;
5670 args
->out
[0] = values
[0];
5671 args
->out
[3] = values
[3];
5674 case V_028714_SPI_SHADER_FP16_ABGR
:
5677 for (unsigned chan
= 0; chan
< 2; chan
++) {
5678 LLVMValueRef pack_args
[2] = {
5680 values
[2 * chan
+ 1]
5682 LLVMValueRef packed
;
5684 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5685 args
->out
[chan
] = packed
;
5689 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5690 for (unsigned chan
= 0; chan
< 4; chan
++) {
5691 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5692 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5693 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5694 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5695 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5696 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5701 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5702 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5705 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5706 for (unsigned chan
= 0; chan
< 4; chan
++) {
5707 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5708 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5709 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5711 /* If positive, add 0.5, else add -0.5. */
5712 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5713 LLVMBuildSelect(ctx
->builder
,
5714 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5715 val
[chan
], ctx
->ac
.f32_0
, ""),
5716 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5717 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5718 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5722 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5723 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5726 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5727 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5728 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5729 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5731 for (unsigned chan
= 0; chan
< 4; chan
++) {
5732 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5733 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5737 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5738 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5742 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5743 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5744 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5745 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5746 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5747 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5748 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5751 for (unsigned chan
= 0; chan
< 4; chan
++) {
5752 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5753 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5754 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5758 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5759 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5764 case V_028714_SPI_SHADER_32_ABGR
:
5765 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5769 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5771 for (unsigned i
= 0; i
< 4; ++i
)
5772 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5776 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5777 bool export_prim_id
,
5778 struct ac_vs_output_info
*outinfo
)
5780 uint32_t param_count
= 0;
5782 unsigned pos_idx
, num_pos_exports
= 0;
5783 struct ac_export_args args
, pos_args
[4] = {};
5784 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5787 if (ctx
->options
->key
.has_multiview_view_index
) {
5788 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5790 for(unsigned i
= 0; i
< 4; ++i
)
5791 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5792 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5795 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5796 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5799 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5800 sizeof(outinfo
->vs_output_param_offset
));
5802 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5803 LLVMValueRef slots
[8];
5806 if (outinfo
->cull_dist_mask
)
5807 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5809 i
= VARYING_SLOT_CLIP_DIST0
;
5810 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5811 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5812 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5814 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5815 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5817 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5818 target
= V_008DFC_SQ_EXP_POS
+ 3;
5819 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5820 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5821 &args
, sizeof(args
));
5824 target
= V_008DFC_SQ_EXP_POS
+ 2;
5825 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5826 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5827 &args
, sizeof(args
));
5831 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5832 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5833 for (unsigned j
= 0; j
< 4; j
++)
5834 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5835 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5837 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5839 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5840 outinfo
->writes_pointsize
= true;
5841 psize_value
= LLVMBuildLoad(ctx
->builder
,
5842 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5845 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5846 outinfo
->writes_layer
= true;
5847 layer_value
= LLVMBuildLoad(ctx
->builder
,
5848 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5851 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5852 outinfo
->writes_viewport_index
= true;
5853 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5854 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5857 if (outinfo
->writes_pointsize
||
5858 outinfo
->writes_layer
||
5859 outinfo
->writes_viewport_index
) {
5860 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5861 (outinfo
->writes_layer
== true ? 4 : 0));
5862 pos_args
[1].valid_mask
= 0;
5863 pos_args
[1].done
= 0;
5864 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5865 pos_args
[1].compr
= 0;
5866 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
5867 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
5868 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
5869 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
5871 if (outinfo
->writes_pointsize
== true)
5872 pos_args
[1].out
[0] = psize_value
;
5873 if (outinfo
->writes_layer
== true)
5874 pos_args
[1].out
[2] = layer_value
;
5875 if (outinfo
->writes_viewport_index
== true) {
5876 if (ctx
->options
->chip_class
>= GFX9
) {
5877 /* GFX9 has the layer in out.z[10:0] and the viewport
5878 * index in out.z[19:16].
5880 LLVMValueRef v
= viewport_index_value
;
5881 v
= ac_to_integer(&ctx
->ac
, v
);
5882 v
= LLVMBuildShl(ctx
->builder
, v
,
5883 LLVMConstInt(ctx
->ac
.i32
, 16, false),
5885 v
= LLVMBuildOr(ctx
->builder
, v
,
5886 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
5888 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
5889 pos_args
[1].enabled_channels
|= 1 << 2;
5891 pos_args
[1].out
[3] = viewport_index_value
;
5892 pos_args
[1].enabled_channels
|= 1 << 3;
5896 for (i
= 0; i
< 4; i
++) {
5897 if (pos_args
[i
].out
[0])
5902 for (i
= 0; i
< 4; i
++) {
5903 if (!pos_args
[i
].out
[0])
5906 /* Specify the target we are exporting */
5907 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5908 if (pos_idx
== num_pos_exports
)
5909 pos_args
[i
].done
= 1;
5910 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
5913 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5914 LLVMValueRef values
[4];
5915 if (!(ctx
->output_mask
& (1ull << i
)))
5918 for (unsigned j
= 0; j
< 4; j
++)
5919 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5920 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5922 if (i
== VARYING_SLOT_LAYER
) {
5923 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5924 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
5926 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
5927 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5928 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5930 } else if (i
>= VARYING_SLOT_VAR0
) {
5931 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
5932 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5933 outinfo
->vs_output_param_offset
[i
] = param_count
;
5938 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5940 if (target
>= V_008DFC_SQ_EXP_POS
&&
5941 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
5942 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5943 &args
, sizeof(args
));
5945 ac_build_export(&ctx
->ac
, &args
);
5949 if (export_prim_id
) {
5950 LLVMValueRef values
[4];
5951 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5952 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5955 values
[0] = ctx
->vs_prim_id
;
5956 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
5957 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5958 for (unsigned j
= 1; j
< 4; j
++)
5959 values
[j
] = ctx
->ac
.f32_0
;
5960 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5961 ac_build_export(&ctx
->ac
, &args
);
5962 outinfo
->export_prim_id
= true;
5965 outinfo
->pos_exports
= num_pos_exports
;
5966 outinfo
->param_exports
= param_count
;
5970 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
5971 struct ac_es_output_info
*outinfo
)
5974 uint64_t max_output_written
= 0;
5975 LLVMValueRef lds_base
= NULL
;
5977 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5981 if (!(ctx
->output_mask
& (1ull << i
)))
5984 if (i
== VARYING_SLOT_CLIP_DIST0
)
5985 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5987 param_index
= shader_io_get_unique_index(i
);
5989 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
5992 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
5994 if (ctx
->ac
.chip_class
>= GFX9
) {
5995 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
5996 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
5997 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
5998 LLVMConstInt(ctx
->ac
.i32
, 24, false),
5999 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6000 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6001 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6002 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6003 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6004 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6007 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6008 LLVMValueRef dw_addr
;
6009 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6013 if (!(ctx
->output_mask
& (1ull << i
)))
6016 if (i
== VARYING_SLOT_CLIP_DIST0
)
6017 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6019 param_index
= shader_io_get_unique_index(i
);
6022 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6023 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6026 for (j
= 0; j
< length
; j
++) {
6027 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
6028 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
6030 if (ctx
->ac
.chip_class
>= GFX9
) {
6031 ac_lds_store(&ctx
->ac
, dw_addr
,
6032 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6033 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6035 ac_build_buffer_store_dword(&ctx
->ac
,
6038 NULL
, ctx
->es2gs_offset
,
6039 (4 * param_index
+ j
) * 4,
6047 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
6049 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6050 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6051 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
6052 vertex_dw_stride
, "");
6054 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6055 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6058 if (!(ctx
->output_mask
& (1ull << i
)))
6061 if (i
== VARYING_SLOT_CLIP_DIST0
)
6062 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6063 int param
= shader_io_get_unique_index(i
);
6064 mark_tess_output(ctx
, false, param
);
6066 mark_tess_output(ctx
, false, param
+ 1);
6067 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
6068 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6070 for (unsigned j
= 0; j
< length
; j
++) {
6071 ac_lds_store(&ctx
->ac
, dw_addr
,
6072 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6073 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6078 struct ac_build_if_state
6080 struct nir_to_llvm_context
*ctx
;
6081 LLVMValueRef condition
;
6082 LLVMBasicBlockRef entry_block
;
6083 LLVMBasicBlockRef true_block
;
6084 LLVMBasicBlockRef false_block
;
6085 LLVMBasicBlockRef merge_block
;
6088 static LLVMBasicBlockRef
6089 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
6091 LLVMBasicBlockRef current_block
;
6092 LLVMBasicBlockRef next_block
;
6093 LLVMBasicBlockRef new_block
;
6095 /* get current basic block */
6096 current_block
= LLVMGetInsertBlock(ctx
->builder
);
6098 /* chqeck if there's another block after this one */
6099 next_block
= LLVMGetNextBasicBlock(current_block
);
6101 /* insert the new block before the next block */
6102 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6105 /* append new block after current block */
6106 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6107 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6113 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6114 struct nir_to_llvm_context
*ctx
,
6115 LLVMValueRef condition
)
6117 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6119 memset(ifthen
, 0, sizeof *ifthen
);
6121 ifthen
->condition
= condition
;
6122 ifthen
->entry_block
= block
;
6124 /* create endif/merge basic block for the phi functions */
6125 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6127 /* create/insert true_block before merge_block */
6128 ifthen
->true_block
=
6129 LLVMInsertBasicBlockInContext(ctx
->context
,
6130 ifthen
->merge_block
,
6133 /* successive code goes into the true block */
6134 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6138 * End a conditional.
6141 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6143 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6145 /* Insert branch to the merge block from current block */
6146 LLVMBuildBr(builder
, ifthen
->merge_block
);
6149 * Now patch in the various branch instructions.
6152 /* Insert the conditional branch instruction at the end of entry_block */
6153 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6154 if (ifthen
->false_block
) {
6155 /* we have an else clause */
6156 LLVMBuildCondBr(builder
, ifthen
->condition
,
6157 ifthen
->true_block
, ifthen
->false_block
);
6160 /* no else clause */
6161 LLVMBuildCondBr(builder
, ifthen
->condition
,
6162 ifthen
->true_block
, ifthen
->merge_block
);
6165 /* Resume building code at end of the ifthen->merge_block */
6166 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6170 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6172 unsigned stride
, outer_comps
, inner_comps
;
6173 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6174 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6175 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6176 unsigned tess_inner_index
, tess_outer_index
;
6177 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6178 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6180 emit_barrier(&ctx
->ac
, ctx
->stage
);
6182 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6202 ac_nir_build_if(&if_ctx
, ctx
,
6203 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6204 invocation_id
, ctx
->ac
.i32_0
, ""));
6206 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6207 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6209 mark_tess_output(ctx
, true, tess_inner_index
);
6210 mark_tess_output(ctx
, true, tess_outer_index
);
6211 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6212 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6213 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6214 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6215 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6217 for (i
= 0; i
< 4; i
++) {
6218 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6219 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6223 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6224 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6225 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6227 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6229 for (i
= 0; i
< outer_comps
; i
++) {
6231 ac_lds_load(&ctx
->ac
, lds_outer
);
6232 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6235 for (i
= 0; i
< inner_comps
; i
++) {
6236 inner
[i
] = out
[outer_comps
+i
] =
6237 ac_lds_load(&ctx
->ac
, lds_inner
);
6238 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6243 /* Convert the outputs to vectors for stores. */
6244 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6248 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6251 buffer
= ctx
->hs_ring_tess_factor
;
6252 tf_base
= ctx
->tess_factor_offset
;
6253 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6254 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6255 unsigned tf_offset
= 0;
6257 if (ctx
->options
->chip_class
<= VI
) {
6258 ac_nir_build_if(&inner_if_ctx
, ctx
,
6259 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6260 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6262 /* Store the dynamic HS control word. */
6263 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6264 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6265 1, ctx
->ac
.i32_0
, tf_base
,
6266 0, 1, 0, true, false);
6269 ac_nir_build_endif(&inner_if_ctx
);
6272 /* Store the tessellation factors. */
6273 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6274 MIN2(stride
, 4), byteoffset
, tf_base
,
6275 tf_offset
, 1, 0, true, false);
6277 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6278 stride
- 4, byteoffset
, tf_base
,
6279 16 + tf_offset
, 1, 0, true, false);
6281 //store to offchip for TES to read - only if TES reads them
6282 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6283 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6284 LLVMValueRef tf_inner_offset
;
6285 unsigned param_outer
, param_inner
;
6287 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6288 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6289 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6291 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6292 util_next_power_of_two(outer_comps
));
6294 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6295 outer_comps
, tf_outer_offset
,
6296 ctx
->oc_lds
, 0, 1, 0, true, false);
6298 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6299 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6300 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6302 inner_vec
= inner_comps
== 1 ? inner
[0] :
6303 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6304 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6305 inner_comps
, tf_inner_offset
,
6306 ctx
->oc_lds
, 0, 1, 0, true, false);
6309 ac_nir_build_endif(&if_ctx
);
6313 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6315 write_tess_factors(ctx
);
6319 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6320 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6321 struct ac_export_args
*args
)
6324 si_llvm_init_export_args(ctx
, color
, param
,
6328 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6329 args
->done
= 1; /* DONE bit */
6330 } else if (!args
->enabled_channels
)
6331 return false; /* unnecessary NULL export */
6337 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6338 LLVMValueRef depth
, LLVMValueRef stencil
,
6339 LLVMValueRef samplemask
)
6341 struct ac_export_args args
;
6343 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6345 ac_build_export(&ctx
->ac
, &args
);
6349 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6352 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6353 struct ac_export_args color_args
[8];
6355 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6356 LLVMValueRef values
[4];
6358 if (!(ctx
->output_mask
& (1ull << i
)))
6361 if (i
== FRAG_RESULT_DEPTH
) {
6362 ctx
->shader_info
->fs
.writes_z
= true;
6363 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6364 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6365 } else if (i
== FRAG_RESULT_STENCIL
) {
6366 ctx
->shader_info
->fs
.writes_stencil
= true;
6367 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6368 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6369 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6370 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6371 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6372 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6375 for (unsigned j
= 0; j
< 4; j
++)
6376 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6377 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6379 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6380 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6382 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6388 for (unsigned i
= 0; i
< index
; i
++)
6389 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6390 if (depth
|| stencil
|| samplemask
)
6391 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6393 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6394 ac_build_export(&ctx
->ac
, &color_args
[0]);
6397 ctx
->shader_info
->fs
.output_mask
= index
? ((1ull << index
) - 1) : 0;
6401 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6403 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6407 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6408 LLVMValueRef
*addrs
)
6410 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6412 switch (ctx
->stage
) {
6413 case MESA_SHADER_VERTEX
:
6414 if (ctx
->options
->key
.vs
.as_ls
)
6415 handle_ls_outputs_post(ctx
);
6416 else if (ctx
->options
->key
.vs
.as_es
)
6417 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6419 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6420 &ctx
->shader_info
->vs
.outinfo
);
6422 case MESA_SHADER_FRAGMENT
:
6423 handle_fs_outputs_post(ctx
);
6425 case MESA_SHADER_GEOMETRY
:
6426 emit_gs_epilogue(ctx
);
6428 case MESA_SHADER_TESS_CTRL
:
6429 handle_tcs_outputs_post(ctx
);
6431 case MESA_SHADER_TESS_EVAL
:
6432 if (ctx
->options
->key
.tes
.as_es
)
6433 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6435 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6436 &ctx
->shader_info
->tes
.outinfo
);
6443 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6445 LLVMPassManagerRef passmgr
;
6446 /* Create the pass manager */
6447 passmgr
= LLVMCreateFunctionPassManagerForModule(
6450 /* This pass should eliminate all the load and store instructions */
6451 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6453 /* Add some optimization passes */
6454 LLVMAddScalarReplAggregatesPass(passmgr
);
6455 LLVMAddLICMPass(passmgr
);
6456 LLVMAddAggressiveDCEPass(passmgr
);
6457 LLVMAddCFGSimplificationPass(passmgr
);
6458 LLVMAddInstructionCombiningPass(passmgr
);
6461 LLVMInitializeFunctionPassManager(passmgr
);
6462 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6463 LLVMFinalizeFunctionPassManager(passmgr
);
6465 LLVMDisposeBuilder(ctx
->builder
);
6466 LLVMDisposePassManager(passmgr
);
6470 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6472 struct ac_vs_output_info
*outinfo
;
6474 switch (ctx
->stage
) {
6475 case MESA_SHADER_FRAGMENT
:
6476 case MESA_SHADER_COMPUTE
:
6477 case MESA_SHADER_TESS_CTRL
:
6478 case MESA_SHADER_GEOMETRY
:
6480 case MESA_SHADER_VERTEX
:
6481 if (ctx
->options
->key
.vs
.as_ls
||
6482 ctx
->options
->key
.vs
.as_es
)
6484 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6486 case MESA_SHADER_TESS_EVAL
:
6487 if (ctx
->options
->key
.vs
.as_es
)
6489 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6492 unreachable("Unhandled shader type");
6495 ac_optimize_vs_outputs(&ctx
->ac
,
6497 outinfo
->vs_output_param_offset
,
6499 &outinfo
->param_exports
);
6503 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6505 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6506 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6507 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6510 if (ctx
->is_gs_copy_shader
) {
6511 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6513 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6515 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6516 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6518 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6520 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6521 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6522 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6523 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6526 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6527 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6528 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6529 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6534 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6535 const struct nir_shader
*nir
)
6537 switch (nir
->info
.stage
) {
6538 case MESA_SHADER_TESS_CTRL
:
6539 return chip_class
>= CIK
? 128 : 64;
6540 case MESA_SHADER_GEOMETRY
:
6541 return chip_class
>= GFX9
? 128 : 64;
6542 case MESA_SHADER_COMPUTE
:
6548 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6549 nir
->info
.cs
.local_size
[1] *
6550 nir
->info
.cs
.local_size
[2];
6551 return max_workgroup_size
;
6554 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6555 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6557 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6558 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6559 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6560 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6562 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6563 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6564 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6565 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6568 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6570 for(int i
= 5; i
>= 0; --i
) {
6571 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6572 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6573 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6576 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6577 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6578 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6581 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6582 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6584 struct ac_nir_context ctx
= {};
6585 struct nir_function
*func
;
6594 ctx
.stage
= nir
->info
.stage
;
6596 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6598 nir_foreach_variable(variable
, &nir
->outputs
)
6599 handle_shader_output_decl(&ctx
, nir
, variable
);
6601 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6602 _mesa_key_pointer_equal
);
6603 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6604 _mesa_key_pointer_equal
);
6605 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6606 _mesa_key_pointer_equal
);
6608 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6610 setup_locals(&ctx
, func
);
6612 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6613 setup_shared(&ctx
, nir
);
6615 visit_cf_list(&ctx
, &func
->impl
->body
);
6616 phi_post_pass(&ctx
);
6618 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6622 ralloc_free(ctx
.defs
);
6623 ralloc_free(ctx
.phis
);
6624 ralloc_free(ctx
.vars
);
6631 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6632 struct nir_shader
*const *shaders
,
6634 struct ac_shader_variant_info
*shader_info
,
6635 const struct ac_nir_compiler_options
*options
)
6637 struct nir_to_llvm_context ctx
= {0};
6639 ctx
.options
= options
;
6640 ctx
.shader_info
= shader_info
;
6641 ctx
.context
= LLVMContextCreate();
6642 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6644 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6646 ctx
.ac
.module
= ctx
.module
;
6647 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6649 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6650 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6651 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6652 LLVMDisposeTargetData(data_layout
);
6653 LLVMDisposeMessage(data_layout_str
);
6655 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6656 ctx
.ac
.builder
= ctx
.builder
;
6658 memset(shader_info
, 0, sizeof(*shader_info
));
6660 for(int i
= 0; i
< shader_count
; ++i
)
6661 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6663 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6664 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6665 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6666 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6668 ctx
.max_workgroup_size
= 0;
6669 for (int i
= 0; i
< shader_count
; ++i
) {
6670 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6671 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6675 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6676 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6678 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6679 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6680 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6681 ctx
.abi
.load_ubo
= radv_load_ubo
;
6682 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6683 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6684 ctx
.abi
.clamp_shadow_reference
= false;
6686 if (shader_count
>= 2)
6687 ac_init_exec_full_mask(&ctx
.ac
);
6689 if (ctx
.ac
.chip_class
== GFX9
&&
6690 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6691 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6693 for(int i
= 0; i
< shader_count
; ++i
) {
6694 ctx
.stage
= shaders
[i
]->info
.stage
;
6695 ctx
.output_mask
= 0;
6696 ctx
.tess_outputs_written
= 0;
6697 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6698 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6700 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6701 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6702 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6703 ctx
.abi
.load_inputs
= load_gs_input
;
6704 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6705 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6706 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6707 ctx
.abi
.load_tess_inputs
= load_tcs_input
;
6708 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6709 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6710 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6711 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6712 ctx
.abi
.load_tess_inputs
= load_tes_input
;
6713 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6714 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6715 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6716 if (shader_info
->info
.vs
.needs_instance_id
) {
6717 if (ctx
.ac
.chip_class
== GFX9
&&
6718 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6719 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6720 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6722 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6723 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6726 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6727 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6731 emit_barrier(&ctx
.ac
, ctx
.stage
);
6733 ac_setup_rings(&ctx
);
6735 LLVMBasicBlockRef merge_block
;
6736 if (shader_count
>= 2) {
6737 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6738 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6739 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6741 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6742 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6743 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6744 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6745 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6746 thread_id
, count
, "");
6747 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6749 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6752 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6753 handle_fs_inputs(&ctx
, shaders
[i
]);
6754 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6755 handle_vs_inputs(&ctx
, shaders
[i
]);
6756 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6757 prepare_gs_input_vgprs(&ctx
);
6759 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6760 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6762 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6764 if (shader_count
>= 2) {
6765 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6766 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6769 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6770 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6771 shaders
[i
]->info
.cull_distance_array_size
> 4;
6772 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6773 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6774 shaders
[i
]->info
.gs
.vertices_out
;
6775 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6776 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6777 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6778 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6779 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6783 LLVMBuildRetVoid(ctx
.builder
);
6785 ac_llvm_finalize_module(&ctx
);
6787 if (shader_count
== 1)
6788 ac_nir_eliminate_const_vs_outputs(&ctx
);
6793 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6795 unsigned *retval
= (unsigned *)context
;
6796 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6797 char *description
= LLVMGetDiagInfoDescription(di
);
6799 if (severity
== LLVMDSError
) {
6801 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6805 LLVMDisposeMessage(description
);
6808 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6809 struct ac_shader_binary
*binary
,
6810 LLVMTargetMachineRef tm
)
6812 unsigned retval
= 0;
6814 LLVMContextRef llvm_ctx
;
6815 LLVMMemoryBufferRef out_buffer
;
6816 unsigned buffer_size
;
6817 const char *buffer_data
;
6820 /* Setup Diagnostic Handler*/
6821 llvm_ctx
= LLVMGetModuleContext(M
);
6823 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6827 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6830 /* Process Errors/Warnings */
6832 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6838 /* Extract Shader Code*/
6839 buffer_size
= LLVMGetBufferSize(out_buffer
);
6840 buffer_data
= LLVMGetBufferStart(out_buffer
);
6842 ac_elf_read(buffer_data
, buffer_size
, binary
);
6845 LLVMDisposeMemoryBuffer(out_buffer
);
6851 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6852 LLVMModuleRef llvm_module
,
6853 struct ac_shader_binary
*binary
,
6854 struct ac_shader_config
*config
,
6855 struct ac_shader_variant_info
*shader_info
,
6856 gl_shader_stage stage
,
6857 bool dump_shader
, bool supports_spill
)
6860 ac_dump_module(llvm_module
);
6862 memset(binary
, 0, sizeof(*binary
));
6863 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6865 fprintf(stderr
, "compile failed\n");
6869 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6871 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6873 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6874 LLVMDisposeModule(llvm_module
);
6875 LLVMContextDispose(ctx
);
6877 if (stage
== MESA_SHADER_FRAGMENT
) {
6878 shader_info
->num_input_vgprs
= 0;
6879 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6880 shader_info
->num_input_vgprs
+= 2;
6881 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6882 shader_info
->num_input_vgprs
+= 2;
6883 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6884 shader_info
->num_input_vgprs
+= 2;
6885 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6886 shader_info
->num_input_vgprs
+= 3;
6887 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6888 shader_info
->num_input_vgprs
+= 2;
6889 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6890 shader_info
->num_input_vgprs
+= 2;
6891 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6892 shader_info
->num_input_vgprs
+= 2;
6893 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6894 shader_info
->num_input_vgprs
+= 1;
6895 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6896 shader_info
->num_input_vgprs
+= 1;
6897 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6898 shader_info
->num_input_vgprs
+= 1;
6899 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6900 shader_info
->num_input_vgprs
+= 1;
6901 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6902 shader_info
->num_input_vgprs
+= 1;
6903 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6904 shader_info
->num_input_vgprs
+= 1;
6905 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6906 shader_info
->num_input_vgprs
+= 1;
6907 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6908 shader_info
->num_input_vgprs
+= 1;
6909 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
6910 shader_info
->num_input_vgprs
+= 1;
6912 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
6914 /* +3 for scratch wave offset and VCC */
6915 config
->num_sgprs
= MAX2(config
->num_sgprs
,
6916 shader_info
->num_input_sgprs
+ 3);
6918 /* Enable 64-bit and 16-bit denormals, because there is no performance
6921 * If denormals are enabled, all floating-point output modifiers are
6924 * Don't enable denormals for 32-bit floats, because:
6925 * - Floating-point output modifiers would be ignored by the hw.
6926 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6927 * have to stop using those.
6928 * - SI & CI would be very slow.
6930 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
6934 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
6936 switch (nir
->info
.stage
) {
6937 case MESA_SHADER_COMPUTE
:
6938 for (int i
= 0; i
< 3; ++i
)
6939 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
6941 case MESA_SHADER_FRAGMENT
:
6942 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
6944 case MESA_SHADER_GEOMETRY
:
6945 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
6946 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
6947 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
6948 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
6950 case MESA_SHADER_TESS_EVAL
:
6951 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
6952 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
6953 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
6954 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
6955 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
6957 case MESA_SHADER_TESS_CTRL
:
6958 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
6960 case MESA_SHADER_VERTEX
:
6961 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
6962 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
6963 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6964 if (options
->key
.vs
.as_ls
)
6965 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
6972 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
6973 struct ac_shader_binary
*binary
,
6974 struct ac_shader_config
*config
,
6975 struct ac_shader_variant_info
*shader_info
,
6976 struct nir_shader
*const *nir
,
6978 const struct ac_nir_compiler_options
*options
,
6982 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
6985 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
6986 for (int i
= 0; i
< nir_count
; ++i
)
6987 ac_fill_shader_info(shader_info
, nir
[i
], options
);
6989 /* Determine the ES type (VS or TES) for the GS on GFX9. */
6990 if (options
->chip_class
== GFX9
) {
6991 if (nir_count
== 2 &&
6992 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6993 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
6999 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
7001 LLVMValueRef args
[9];
7002 args
[0] = ctx
->gsvs_ring
;
7003 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7004 args
[3] = ctx
->ac
.i32_0
;
7005 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
7006 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
7007 args
[6] = ctx
->ac
.i32_1
; /* GLC */
7008 args
[7] = ctx
->ac
.i32_1
; /* SLC */
7009 args
[8] = ctx
->ac
.i32_0
; /* TFE */
7013 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
7017 if (!(ctx
->output_mask
& (1ull << i
)))
7020 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7021 /* unpack clip and cull from a single set of slots */
7022 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7027 for (unsigned j
= 0; j
< length
; j
++) {
7029 args
[2] = LLVMConstInt(ctx
->ac
.i32
,
7031 ctx
->gs_max_out_vertices
* 16 * 4, false);
7033 value
= ac_build_intrinsic(&ctx
->ac
,
7034 "llvm.SI.buffer.load.dword.i32.i32",
7035 ctx
->ac
.i32
, args
, 9,
7036 AC_FUNC_ATTR_READONLY
|
7037 AC_FUNC_ATTR_LEGACY
);
7039 LLVMBuildStore(ctx
->builder
,
7040 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7044 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7047 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7048 struct nir_shader
*geom_shader
,
7049 struct ac_shader_binary
*binary
,
7050 struct ac_shader_config
*config
,
7051 struct ac_shader_variant_info
*shader_info
,
7052 const struct ac_nir_compiler_options
*options
,
7055 struct nir_to_llvm_context ctx
= {0};
7056 ctx
.context
= LLVMContextCreate();
7057 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7058 ctx
.options
= options
;
7059 ctx
.shader_info
= shader_info
;
7061 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7063 ctx
.ac
.module
= ctx
.module
;
7065 ctx
.is_gs_copy_shader
= true;
7066 LLVMSetTarget(ctx
.module
, "amdgcn--");
7068 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
7069 ctx
.ac
.builder
= ctx
.builder
;
7070 ctx
.stage
= MESA_SHADER_VERTEX
;
7072 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7074 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7075 ac_setup_rings(&ctx
);
7077 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7078 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7080 struct ac_nir_context nir_ctx
= {};
7081 nir_ctx
.ac
= ctx
.ac
;
7082 nir_ctx
.abi
= &ctx
.abi
;
7084 nir_ctx
.nctx
= &ctx
;
7087 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7088 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7089 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7092 ac_gs_copy_shader_emit(&ctx
);
7096 LLVMBuildRetVoid(ctx
.builder
);
7098 ac_llvm_finalize_module(&ctx
);
7100 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
7102 dump_shader
, options
->supports_spill
);