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ac/radeonsi: add local_invocation_ids to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 struct hash_table *defs;
87 struct hash_table *phis;
88
89 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
90 LLVMValueRef ring_offsets;
91 LLVMValueRef push_constants;
92 LLVMValueRef view_index;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef tg_size;
95
96 LLVMValueRef vertex_buffers;
97 LLVMValueRef rel_auto_id;
98 LLVMValueRef vs_prim_id;
99 LLVMValueRef ls_out_layout;
100 LLVMValueRef es2gs_offset;
101
102 LLVMValueRef tcs_offchip_layout;
103 LLVMValueRef tcs_out_offsets;
104 LLVMValueRef tcs_out_layout;
105 LLVMValueRef tcs_in_layout;
106 LLVMValueRef oc_lds;
107 LLVMValueRef merged_wave_info;
108 LLVMValueRef tess_factor_offset;
109 LLVMValueRef tes_rel_patch_id;
110 LLVMValueRef tes_u;
111 LLVMValueRef tes_v;
112
113 LLVMValueRef gsvs_ring_stride;
114 LLVMValueRef gsvs_num_entries;
115 LLVMValueRef gs2vs_offset;
116 LLVMValueRef gs_wave_id;
117 LLVMValueRef gs_vtx_offset[6];
118
119 LLVMValueRef esgs_ring;
120 LLVMValueRef gsvs_ring;
121 LLVMValueRef hs_ring_tess_offchip;
122 LLVMValueRef hs_ring_tess_factor;
123
124 LLVMValueRef sample_pos_offset;
125 LLVMValueRef persp_sample, persp_center, persp_centroid;
126 LLVMValueRef linear_sample, linear_center, linear_centroid;
127
128 gl_shader_stage stage;
129
130 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
131
132 uint64_t input_mask;
133 uint64_t output_mask;
134 uint8_t num_output_clips;
135 uint8_t num_output_culls;
136
137 bool is_gs_copy_shader;
138 LLVMValueRef gs_next_vertex;
139 unsigned gs_max_out_vertices;
140
141 unsigned tes_primitive_mode;
142 uint64_t tess_outputs_written;
143 uint64_t tess_patch_outputs_written;
144
145 uint32_t tcs_patch_outputs_read;
146 uint64_t tcs_outputs_read;
147 };
148
149 static inline struct nir_to_llvm_context *
150 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
151 {
152 struct nir_to_llvm_context *ctx = NULL;
153 return container_of(abi, ctx, abi);
154 }
155
156 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
157 const nir_deref_var *deref,
158 enum ac_descriptor_type desc_type,
159 const nir_tex_instr *instr,
160 bool image, bool write);
161
162 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
163 {
164 return (index * 4) + chan;
165 }
166
167 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
168 {
169 /* handle patch indices separate */
170 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
171 return 0;
172 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
173 return 1;
174 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
175 return 2 + (slot - VARYING_SLOT_PATCH0);
176
177 if (slot == VARYING_SLOT_POS)
178 return 0;
179 if (slot == VARYING_SLOT_PSIZ)
180 return 1;
181 if (slot == VARYING_SLOT_CLIP_DIST0)
182 return 2;
183 /* 3 is reserved for clip dist as well */
184 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
185 return 4 + (slot - VARYING_SLOT_VAR0);
186 unreachable("illegal slot in get unique index\n");
187 }
188
189 static void set_llvm_calling_convention(LLVMValueRef func,
190 gl_shader_stage stage)
191 {
192 enum radeon_llvm_calling_convention calling_conv;
193
194 switch (stage) {
195 case MESA_SHADER_VERTEX:
196 case MESA_SHADER_TESS_EVAL:
197 calling_conv = RADEON_LLVM_AMDGPU_VS;
198 break;
199 case MESA_SHADER_GEOMETRY:
200 calling_conv = RADEON_LLVM_AMDGPU_GS;
201 break;
202 case MESA_SHADER_TESS_CTRL:
203 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
204 break;
205 case MESA_SHADER_FRAGMENT:
206 calling_conv = RADEON_LLVM_AMDGPU_PS;
207 break;
208 case MESA_SHADER_COMPUTE:
209 calling_conv = RADEON_LLVM_AMDGPU_CS;
210 break;
211 default:
212 unreachable("Unhandle shader type");
213 }
214
215 LLVMSetFunctionCallConv(func, calling_conv);
216 }
217
218 #define MAX_ARGS 23
219 struct arg_info {
220 LLVMTypeRef types[MAX_ARGS];
221 LLVMValueRef *assign[MAX_ARGS];
222 unsigned array_params_mask;
223 uint8_t count;
224 uint8_t sgpr_count;
225 uint8_t num_sgprs_used;
226 uint8_t num_vgprs_used;
227 };
228
229 enum ac_arg_regfile {
230 ARG_SGPR,
231 ARG_VGPR,
232 };
233
234 static void
235 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
236 LLVMValueRef *param_ptr)
237 {
238 assert(info->count < MAX_ARGS);
239
240 info->assign[info->count] = param_ptr;
241 info->types[info->count] = type;
242 info->count++;
243
244 if (regfile == ARG_SGPR) {
245 info->num_sgprs_used += ac_get_type_size(type) / 4;
246 info->sgpr_count++;
247 } else {
248 assert(regfile == ARG_VGPR);
249 info->num_vgprs_used += ac_get_type_size(type) / 4;
250 }
251 }
252
253 static inline void
254 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
255 {
256 info->array_params_mask |= (1 << info->count);
257 add_arg(info, ARG_SGPR, type, param_ptr);
258 }
259
260 static void assign_arguments(LLVMValueRef main_function,
261 struct arg_info *info)
262 {
263 unsigned i;
264 for (i = 0; i < info->count; i++) {
265 if (info->assign[i])
266 *info->assign[i] = LLVMGetParam(main_function, i);
267 }
268 }
269
270 static LLVMValueRef
271 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
272 LLVMBuilderRef builder, LLVMTypeRef *return_types,
273 unsigned num_return_elems,
274 struct arg_info *args,
275 unsigned max_workgroup_size,
276 bool unsafe_math)
277 {
278 LLVMTypeRef main_function_type, ret_type;
279 LLVMBasicBlockRef main_function_body;
280
281 if (num_return_elems)
282 ret_type = LLVMStructTypeInContext(ctx, return_types,
283 num_return_elems, true);
284 else
285 ret_type = LLVMVoidTypeInContext(ctx);
286
287 /* Setup the function */
288 main_function_type =
289 LLVMFunctionType(ret_type, args->types, args->count, 0);
290 LLVMValueRef main_function =
291 LLVMAddFunction(module, "main", main_function_type);
292 main_function_body =
293 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
294 LLVMPositionBuilderAtEnd(builder, main_function_body);
295
296 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
297 for (unsigned i = 0; i < args->sgpr_count; ++i) {
298 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
299
300 if (args->array_params_mask & (1 << i)) {
301 LLVMValueRef P = LLVMGetParam(main_function, i);
302 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
303 ac_add_attr_dereferenceable(P, UINT64_MAX);
304 }
305 }
306
307 if (max_workgroup_size) {
308 ac_llvm_add_target_dep_function_attr(main_function,
309 "amdgpu-max-work-group-size",
310 max_workgroup_size);
311 }
312 if (unsafe_math) {
313 /* These were copied from some LLVM test. */
314 LLVMAddTargetDependentFunctionAttr(main_function,
315 "less-precise-fpmad",
316 "true");
317 LLVMAddTargetDependentFunctionAttr(main_function,
318 "no-infs-fp-math",
319 "true");
320 LLVMAddTargetDependentFunctionAttr(main_function,
321 "no-nans-fp-math",
322 "true");
323 LLVMAddTargetDependentFunctionAttr(main_function,
324 "unsafe-fp-math",
325 "true");
326 LLVMAddTargetDependentFunctionAttr(main_function,
327 "no-signed-zeros-fp-math",
328 "true");
329 }
330 return main_function;
331 }
332
333 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
334 {
335 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
336 type = LLVMGetElementType(type);
337
338 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
339 return LLVMGetIntTypeWidth(type);
340
341 if (type == ctx->f16)
342 return 16;
343 if (type == ctx->f32)
344 return 32;
345 if (type == ctx->f64)
346 return 64;
347
348 unreachable("Unhandled type kind in get_elem_bits");
349 }
350
351 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
352 LLVMValueRef param, unsigned rshift,
353 unsigned bitwidth)
354 {
355 LLVMValueRef value = param;
356 if (rshift)
357 value = LLVMBuildLShr(ctx->builder, value,
358 LLVMConstInt(ctx->i32, rshift, false), "");
359
360 if (rshift + bitwidth < 32) {
361 unsigned mask = (1 << bitwidth) - 1;
362 value = LLVMBuildAnd(ctx->builder, value,
363 LLVMConstInt(ctx->i32, mask, false), "");
364 }
365 return value;
366 }
367
368 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
369 {
370 switch (ctx->stage) {
371 case MESA_SHADER_TESS_CTRL:
372 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
373 case MESA_SHADER_TESS_EVAL:
374 return ctx->tes_rel_patch_id;
375 break;
376 default:
377 unreachable("Illegal stage");
378 }
379 }
380
381 /* Tessellation shaders pass outputs to the next shader using LDS.
382 *
383 * LS outputs = TCS inputs
384 * TCS outputs = TES inputs
385 *
386 * The LDS layout is:
387 * - TCS inputs for patch 0
388 * - TCS inputs for patch 1
389 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
390 * - ...
391 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
392 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
393 * - TCS outputs for patch 1
394 * - Per-patch TCS outputs for patch 1
395 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
396 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
397 * - ...
398 *
399 * All three shaders VS(LS), TCS, TES share the same LDS space.
400 */
401 static LLVMValueRef
402 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
403 {
404 if (ctx->stage == MESA_SHADER_VERTEX)
405 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
406 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
407 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
408 else {
409 assert(0);
410 return NULL;
411 }
412 }
413
414 static LLVMValueRef
415 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
416 {
417 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
418 }
419
420 static LLVMValueRef
421 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
422 {
423 return LLVMBuildMul(ctx->builder,
424 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
425 LLVMConstInt(ctx->ac.i32, 4, false), "");
426 }
427
428 static LLVMValueRef
429 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
430 {
431 return LLVMBuildMul(ctx->builder,
432 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
433 LLVMConstInt(ctx->ac.i32, 4, false), "");
434 }
435
436 static LLVMValueRef
437 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
438 {
439 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
440 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
441
442 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
443 }
444
445 static LLVMValueRef
446 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
447 {
448 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
449 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
450 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
451
452 return LLVMBuildAdd(ctx->builder, patch0_offset,
453 LLVMBuildMul(ctx->builder, patch_stride,
454 rel_patch_id, ""),
455 "");
456 }
457
458 static LLVMValueRef
459 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
460 {
461 LLVMValueRef patch0_patch_data_offset =
462 get_tcs_out_patch0_patch_data_offset(ctx);
463 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
464 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
465
466 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
467 LLVMBuildMul(ctx->builder, patch_stride,
468 rel_patch_id, ""),
469 "");
470 }
471
472 static void
473 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
474 uint32_t indirect_offset)
475 {
476 ud_info->sgpr_idx = *sgpr_idx;
477 ud_info->num_sgprs = num_sgprs;
478 ud_info->indirect = indirect_offset > 0;
479 ud_info->indirect_offset = indirect_offset;
480 *sgpr_idx += num_sgprs;
481 }
482
483 static void
484 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
485 uint8_t num_sgprs)
486 {
487 struct ac_userdata_info *ud_info =
488 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
489 assert(ud_info);
490
491 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
492 }
493
494 static void
495 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
496 uint32_t indirect_offset)
497 {
498 struct ac_userdata_info *ud_info =
499 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
500 assert(ud_info);
501
502 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
503 }
504
505 struct user_sgpr_info {
506 bool need_ring_offsets;
507 uint8_t sgpr_count;
508 bool indirect_all_descriptor_sets;
509 };
510
511 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
512 gl_shader_stage stage)
513 {
514 switch (stage) {
515 case MESA_SHADER_VERTEX:
516 if (ctx->shader_info->info.needs_multiview_view_index ||
517 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
518 return true;
519 break;
520 case MESA_SHADER_TESS_EVAL:
521 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
522 return true;
523 break;
524 case MESA_SHADER_GEOMETRY:
525 case MESA_SHADER_TESS_CTRL:
526 if (ctx->shader_info->info.needs_multiview_view_index)
527 return true;
528 break;
529 default:
530 break;
531 }
532 return false;
533 }
534
535 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
536 gl_shader_stage stage,
537 bool needs_view_index,
538 struct user_sgpr_info *user_sgpr_info)
539 {
540 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
541
542 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
543 if (stage == MESA_SHADER_GEOMETRY ||
544 stage == MESA_SHADER_VERTEX ||
545 stage == MESA_SHADER_TESS_CTRL ||
546 stage == MESA_SHADER_TESS_EVAL ||
547 ctx->is_gs_copy_shader)
548 user_sgpr_info->need_ring_offsets = true;
549
550 if (stage == MESA_SHADER_FRAGMENT &&
551 ctx->shader_info->info.ps.needs_sample_positions)
552 user_sgpr_info->need_ring_offsets = true;
553
554 /* 2 user sgprs will nearly always be allocated for scratch/rings */
555 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
556 user_sgpr_info->sgpr_count += 2;
557 }
558
559 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
560 switch (stage) {
561 case MESA_SHADER_COMPUTE:
562 if (ctx->shader_info->info.cs.uses_grid_size)
563 user_sgpr_info->sgpr_count += 3;
564 break;
565 case MESA_SHADER_FRAGMENT:
566 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
567 break;
568 case MESA_SHADER_VERTEX:
569 if (!ctx->is_gs_copy_shader) {
570 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
571 if (ctx->shader_info->info.vs.needs_draw_id) {
572 user_sgpr_info->sgpr_count += 3;
573 } else {
574 user_sgpr_info->sgpr_count += 2;
575 }
576 }
577 if (ctx->options->key.vs.as_ls)
578 user_sgpr_info->sgpr_count++;
579 break;
580 case MESA_SHADER_TESS_CTRL:
581 user_sgpr_info->sgpr_count += 4;
582 break;
583 case MESA_SHADER_TESS_EVAL:
584 user_sgpr_info->sgpr_count += 1;
585 break;
586 case MESA_SHADER_GEOMETRY:
587 user_sgpr_info->sgpr_count += 2;
588 break;
589 default:
590 break;
591 }
592
593 if (needs_view_index)
594 user_sgpr_info->sgpr_count++;
595
596 if (ctx->shader_info->info.loads_push_constants)
597 user_sgpr_info->sgpr_count += 2;
598
599 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
600 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
601
602 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
603 user_sgpr_info->sgpr_count += 2;
604 user_sgpr_info->indirect_all_descriptor_sets = true;
605 } else {
606 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
607 }
608 }
609
610 static void
611 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
612 gl_shader_stage stage,
613 bool has_previous_stage,
614 gl_shader_stage previous_stage,
615 const struct user_sgpr_info *user_sgpr_info,
616 struct arg_info *args,
617 LLVMValueRef *desc_sets)
618 {
619 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
620 unsigned num_sets = ctx->options->layout ?
621 ctx->options->layout->num_sets : 0;
622 unsigned stage_mask = 1 << stage;
623
624 if (has_previous_stage)
625 stage_mask |= 1 << previous_stage;
626
627 /* 1 for each descriptor set */
628 if (!user_sgpr_info->indirect_all_descriptor_sets) {
629 for (unsigned i = 0; i < num_sets; ++i) {
630 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
631 add_array_arg(args, type,
632 &ctx->descriptor_sets[i]);
633 }
634 }
635 } else {
636 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
637 }
638
639 if (ctx->shader_info->info.loads_push_constants) {
640 /* 1 for push constants and dynamic descriptors */
641 add_array_arg(args, type, &ctx->push_constants);
642 }
643 }
644
645 static void
646 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
647 gl_shader_stage stage,
648 bool has_previous_stage,
649 gl_shader_stage previous_stage,
650 struct arg_info *args)
651 {
652 if (!ctx->is_gs_copy_shader &&
653 (stage == MESA_SHADER_VERTEX ||
654 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
655 if (ctx->shader_info->info.vs.has_vertex_buffers) {
656 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
657 &ctx->vertex_buffers);
658 }
659 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
660 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
661 if (ctx->shader_info->info.vs.needs_draw_id) {
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
663 }
664 }
665 }
666
667 static void
668 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
669 {
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
671 if (!ctx->is_gs_copy_shader) {
672 if (ctx->options->key.vs.as_ls) {
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
675 } else {
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
678 }
679 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
680 }
681 }
682
683 static void
684 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
685 {
686 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
687 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
688 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
689 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
690 }
691
692 static void
693 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
694 bool has_previous_stage, gl_shader_stage previous_stage,
695 const struct user_sgpr_info *user_sgpr_info,
696 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
697 {
698 unsigned num_sets = ctx->options->layout ?
699 ctx->options->layout->num_sets : 0;
700 unsigned stage_mask = 1 << stage;
701
702 if (has_previous_stage)
703 stage_mask |= 1 << previous_stage;
704
705 if (!user_sgpr_info->indirect_all_descriptor_sets) {
706 for (unsigned i = 0; i < num_sets; ++i) {
707 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
708 set_loc_desc(ctx, i, user_sgpr_idx, 0);
709 } else
710 ctx->descriptor_sets[i] = NULL;
711 }
712 } else {
713 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
714 user_sgpr_idx, 2);
715
716 for (unsigned i = 0; i < num_sets; ++i) {
717 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
718 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
719 ctx->descriptor_sets[i] =
720 ac_build_load_to_sgpr(&ctx->ac,
721 desc_sets,
722 LLVMConstInt(ctx->ac.i32, i, false));
723
724 } else
725 ctx->descriptor_sets[i] = NULL;
726 }
727 ctx->shader_info->need_indirect_descriptor_sets = true;
728 }
729
730 if (ctx->shader_info->info.loads_push_constants) {
731 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
732 }
733 }
734
735 static void
736 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
737 gl_shader_stage stage, bool has_previous_stage,
738 gl_shader_stage previous_stage,
739 uint8_t *user_sgpr_idx)
740 {
741 if (!ctx->is_gs_copy_shader &&
742 (stage == MESA_SHADER_VERTEX ||
743 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
744 if (ctx->shader_info->info.vs.has_vertex_buffers) {
745 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
746 user_sgpr_idx, 2);
747 }
748
749 unsigned vs_num = 2;
750 if (ctx->shader_info->info.vs.needs_draw_id)
751 vs_num++;
752
753 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
754 user_sgpr_idx, vs_num);
755 }
756 }
757
758 static void create_function(struct nir_to_llvm_context *ctx,
759 gl_shader_stage stage,
760 bool has_previous_stage,
761 gl_shader_stage previous_stage)
762 {
763 uint8_t user_sgpr_idx;
764 struct user_sgpr_info user_sgpr_info;
765 struct arg_info args = {};
766 LLVMValueRef desc_sets;
767 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
768 allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
769
770 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
771 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
772 &ctx->ring_offsets);
773 }
774
775 switch (stage) {
776 case MESA_SHADER_COMPUTE:
777 declare_global_input_sgprs(ctx, stage, has_previous_stage,
778 previous_stage, &user_sgpr_info,
779 &args, &desc_sets);
780
781 if (ctx->shader_info->info.cs.uses_grid_size) {
782 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
783 &ctx->num_work_groups);
784 }
785
786 for (int i = 0; i < 3; i++) {
787 ctx->abi.workgroup_ids[i] = NULL;
788 if (ctx->shader_info->info.cs.uses_block_id[i]) {
789 add_arg(&args, ARG_SGPR, ctx->ac.i32,
790 &ctx->abi.workgroup_ids[i]);
791 }
792 }
793
794 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
795 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
796 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
797 &ctx->abi.local_invocation_ids);
798 break;
799 case MESA_SHADER_VERTEX:
800 declare_global_input_sgprs(ctx, stage, has_previous_stage,
801 previous_stage, &user_sgpr_info,
802 &args, &desc_sets);
803 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
804 previous_stage, &args);
805
806 if (needs_view_index)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
808 if (ctx->options->key.vs.as_es)
809 add_arg(&args, ARG_SGPR, ctx->ac.i32,
810 &ctx->es2gs_offset);
811 else if (ctx->options->key.vs.as_ls)
812 add_arg(&args, ARG_SGPR, ctx->ac.i32,
813 &ctx->ls_out_layout);
814
815 declare_vs_input_vgprs(ctx, &args);
816 break;
817 case MESA_SHADER_TESS_CTRL:
818 if (has_previous_stage) {
819 // First 6 system regs
820 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->merged_wave_info);
823 add_arg(&args, ARG_SGPR, ctx->ac.i32,
824 &ctx->tess_factor_offset);
825
826 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
827 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
829
830 declare_global_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage,
833 &user_sgpr_info, &args,
834 &desc_sets);
835 declare_vs_specific_input_sgprs(ctx, stage,
836 has_previous_stage,
837 previous_stage, &args);
838
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->ls_out_layout);
841
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_offchip_layout);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_offsets);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_out_layout);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_in_layout);
850 if (needs_view_index)
851 add_arg(&args, ARG_SGPR, ctx->ac.i32,
852 &ctx->view_index);
853
854 add_arg(&args, ARG_VGPR, ctx->ac.i32,
855 &ctx->abi.tcs_patch_id);
856 add_arg(&args, ARG_VGPR, ctx->ac.i32,
857 &ctx->abi.tcs_rel_ids);
858
859 declare_vs_input_vgprs(ctx, &args);
860 } else {
861 declare_global_input_sgprs(ctx, stage,
862 has_previous_stage,
863 previous_stage,
864 &user_sgpr_info, &args,
865 &desc_sets);
866
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_offchip_layout);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_offsets);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_out_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_in_layout);
875 if (needs_view_index)
876 add_arg(&args, ARG_SGPR, ctx->ac.i32,
877 &ctx->view_index);
878
879 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->tess_factor_offset);
882 add_arg(&args, ARG_VGPR, ctx->ac.i32,
883 &ctx->abi.tcs_patch_id);
884 add_arg(&args, ARG_VGPR, ctx->ac.i32,
885 &ctx->abi.tcs_rel_ids);
886 }
887 break;
888 case MESA_SHADER_TESS_EVAL:
889 declare_global_input_sgprs(ctx, stage, has_previous_stage,
890 previous_stage, &user_sgpr_info,
891 &args, &desc_sets);
892
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
894 if (needs_view_index)
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
896
897 if (ctx->options->key.tes.as_es) {
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->es2gs_offset);
902 } else {
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
905 }
906 declare_tes_input_vgprs(ctx, &args);
907 break;
908 case MESA_SHADER_GEOMETRY:
909 if (has_previous_stage) {
910 // First 6 system regs
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->gs2vs_offset);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->merged_wave_info);
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
916
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
918 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
920
921 declare_global_input_sgprs(ctx, stage,
922 has_previous_stage,
923 previous_stage,
924 &user_sgpr_info, &args,
925 &desc_sets);
926
927 if (previous_stage == MESA_SHADER_TESS_EVAL) {
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->tcs_offchip_layout);
930 } else {
931 declare_vs_specific_input_sgprs(ctx, stage,
932 has_previous_stage,
933 previous_stage,
934 &args);
935 }
936
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->gsvs_ring_stride);
939 add_arg(&args, ARG_SGPR, ctx->ac.i32,
940 &ctx->gsvs_num_entries);
941 if (needs_view_index)
942 add_arg(&args, ARG_SGPR, ctx->ac.i32,
943 &ctx->view_index);
944
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[0]);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->gs_vtx_offset[2]);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->abi.gs_prim_id);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->abi.gs_invocation_id);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->gs_vtx_offset[4]);
955
956 if (previous_stage == MESA_SHADER_VERTEX) {
957 declare_vs_input_vgprs(ctx, &args);
958 } else {
959 declare_tes_input_vgprs(ctx, &args);
960 }
961 } else {
962 declare_global_input_sgprs(ctx, stage,
963 has_previous_stage,
964 previous_stage,
965 &user_sgpr_info, &args,
966 &desc_sets);
967
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->gsvs_ring_stride);
970 add_arg(&args, ARG_SGPR, ctx->ac.i32,
971 &ctx->gsvs_num_entries);
972 if (needs_view_index)
973 add_arg(&args, ARG_SGPR, ctx->ac.i32,
974 &ctx->view_index);
975
976 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
977 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[0]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[1]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->abi.gs_prim_id);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[2]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[3]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[4]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[5]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->abi.gs_invocation_id);
994 }
995 break;
996 case MESA_SHADER_FRAGMENT:
997 declare_global_input_sgprs(ctx, stage, has_previous_stage,
998 previous_stage, &user_sgpr_info,
999 &args, &desc_sets);
1000
1001 if (ctx->shader_info->info.ps.needs_sample_positions)
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1003 &ctx->sample_pos_offset);
1004
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1020 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1022 break;
1023 default:
1024 unreachable("Shader stage not implemented");
1025 }
1026
1027 ctx->main_function = create_llvm_function(
1028 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1029 ctx->max_workgroup_size,
1030 ctx->options->unsafe_math);
1031 set_llvm_calling_convention(ctx->main_function, stage);
1032
1033
1034 ctx->shader_info->num_input_vgprs = 0;
1035 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1036
1037 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1038
1039 if (ctx->stage != MESA_SHADER_FRAGMENT)
1040 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1041
1042 assign_arguments(ctx->main_function, &args);
1043
1044 user_sgpr_idx = 0;
1045
1046 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1047 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1048 &user_sgpr_idx, 2);
1049 if (ctx->options->supports_spill) {
1050 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1051 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1052 NULL, 0, AC_FUNC_ATTR_READNONE);
1053 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1054 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1055 }
1056 }
1057
1058 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1059 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1060 if (has_previous_stage)
1061 user_sgpr_idx = 0;
1062
1063 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1064 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1065
1066 switch (stage) {
1067 case MESA_SHADER_COMPUTE:
1068 if (ctx->shader_info->info.cs.uses_grid_size) {
1069 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1070 &user_sgpr_idx, 3);
1071 }
1072 break;
1073 case MESA_SHADER_VERTEX:
1074 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1075 previous_stage, &user_sgpr_idx);
1076 if (ctx->view_index)
1077 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1078 if (ctx->options->key.vs.as_ls) {
1079 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1080 &user_sgpr_idx, 1);
1081 }
1082 if (ctx->options->key.vs.as_ls)
1083 ac_declare_lds_as_pointer(&ctx->ac);
1084 break;
1085 case MESA_SHADER_TESS_CTRL:
1086 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1087 previous_stage, &user_sgpr_idx);
1088 if (has_previous_stage)
1089 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1090 &user_sgpr_idx, 1);
1091 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1092 if (ctx->view_index)
1093 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1094 ac_declare_lds_as_pointer(&ctx->ac);
1095 break;
1096 case MESA_SHADER_TESS_EVAL:
1097 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1098 if (ctx->view_index)
1099 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1100 break;
1101 case MESA_SHADER_GEOMETRY:
1102 if (has_previous_stage) {
1103 if (previous_stage == MESA_SHADER_VERTEX)
1104 set_vs_specific_input_locs(ctx, stage,
1105 has_previous_stage,
1106 previous_stage,
1107 &user_sgpr_idx);
1108 else
1109 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1110 &user_sgpr_idx, 1);
1111 }
1112 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1113 &user_sgpr_idx, 2);
1114 if (ctx->view_index)
1115 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1116 if (has_previous_stage)
1117 ac_declare_lds_as_pointer(&ctx->ac);
1118 break;
1119 case MESA_SHADER_FRAGMENT:
1120 if (ctx->shader_info->info.ps.needs_sample_positions) {
1121 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1122 &user_sgpr_idx, 1);
1123 }
1124 break;
1125 default:
1126 unreachable("Shader stage not implemented");
1127 }
1128
1129 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1130 }
1131
1132 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1133 LLVMValueRef value, unsigned count)
1134 {
1135 unsigned num_components = ac_get_llvm_num_components(value);
1136 if (count == num_components)
1137 return value;
1138
1139 LLVMValueRef masks[] = {
1140 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1141 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1142
1143 if (count == 1)
1144 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1145 "");
1146
1147 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1148 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1149 }
1150
1151 static void
1152 build_store_values_extended(struct ac_llvm_context *ac,
1153 LLVMValueRef *values,
1154 unsigned value_count,
1155 unsigned value_stride,
1156 LLVMValueRef vec)
1157 {
1158 LLVMBuilderRef builder = ac->builder;
1159 unsigned i;
1160
1161 for (i = 0; i < value_count; i++) {
1162 LLVMValueRef ptr = values[i * value_stride];
1163 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1164 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1165 LLVMBuildStore(builder, value, ptr);
1166 }
1167 }
1168
1169 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1170 const nir_ssa_def *def)
1171 {
1172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1173 if (def->num_components > 1) {
1174 type = LLVMVectorType(type, def->num_components);
1175 }
1176 return type;
1177 }
1178
1179 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1180 {
1181 assert(src.is_ssa);
1182 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1183 return (LLVMValueRef)entry->data;
1184 }
1185
1186
1187 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1188 const struct nir_block *b)
1189 {
1190 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1191 return (LLVMBasicBlockRef)entry->data;
1192 }
1193
1194 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1195 nir_alu_src src,
1196 unsigned num_components)
1197 {
1198 LLVMValueRef value = get_src(ctx, src.src);
1199 bool need_swizzle = false;
1200
1201 assert(value);
1202 LLVMTypeRef type = LLVMTypeOf(value);
1203 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1204 ? LLVMGetVectorSize(type)
1205 : 1;
1206
1207 for (unsigned i = 0; i < num_components; ++i) {
1208 assert(src.swizzle[i] < src_components);
1209 if (src.swizzle[i] != i)
1210 need_swizzle = true;
1211 }
1212
1213 if (need_swizzle || num_components != src_components) {
1214 LLVMValueRef masks[] = {
1215 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1216 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1219
1220 if (src_components > 1 && num_components == 1) {
1221 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1222 masks[0], "");
1223 } else if (src_components == 1 && num_components > 1) {
1224 LLVMValueRef values[] = {value, value, value, value};
1225 value = ac_build_gather_values(&ctx->ac, values, num_components);
1226 } else {
1227 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1228 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1229 swizzle, "");
1230 }
1231 }
1232 assert(!src.negate);
1233 assert(!src.abs);
1234 return value;
1235 }
1236
1237 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1238 LLVMIntPredicate pred, LLVMValueRef src0,
1239 LLVMValueRef src1)
1240 {
1241 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1242 return LLVMBuildSelect(ctx->builder, result,
1243 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1244 ctx->i32_0, "");
1245 }
1246
1247 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1248 LLVMRealPredicate pred, LLVMValueRef src0,
1249 LLVMValueRef src1)
1250 {
1251 LLVMValueRef result;
1252 src0 = ac_to_float(ctx, src0);
1253 src1 = ac_to_float(ctx, src1);
1254 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1255 return LLVMBuildSelect(ctx->builder, result,
1256 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1257 ctx->i32_0, "");
1258 }
1259
1260 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1261 const char *intrin,
1262 LLVMTypeRef result_type,
1263 LLVMValueRef src0)
1264 {
1265 char name[64];
1266 LLVMValueRef params[] = {
1267 ac_to_float(ctx, src0),
1268 };
1269
1270 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1271 get_elem_bits(ctx, result_type));
1272 assert(length < sizeof(name));
1273 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1274 }
1275
1276 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1277 const char *intrin,
1278 LLVMTypeRef result_type,
1279 LLVMValueRef src0, LLVMValueRef src1)
1280 {
1281 char name[64];
1282 LLVMValueRef params[] = {
1283 ac_to_float(ctx, src0),
1284 ac_to_float(ctx, src1),
1285 };
1286
1287 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1288 get_elem_bits(ctx, result_type));
1289 assert(length < sizeof(name));
1290 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1291 }
1292
1293 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1294 const char *intrin,
1295 LLVMTypeRef result_type,
1296 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1297 {
1298 char name[64];
1299 LLVMValueRef params[] = {
1300 ac_to_float(ctx, src0),
1301 ac_to_float(ctx, src1),
1302 ac_to_float(ctx, src2),
1303 };
1304
1305 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1306 get_elem_bits(ctx, result_type));
1307 assert(length < sizeof(name));
1308 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1309 }
1310
1311 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1312 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1313 {
1314 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1315 ctx->i32_0, "");
1316 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1317 }
1318
1319 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1320 LLVMIntPredicate pred,
1321 LLVMValueRef src0, LLVMValueRef src1)
1322 {
1323 return LLVMBuildSelect(ctx->builder,
1324 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1325 src0,
1326 src1, "");
1327
1328 }
1329 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1330 LLVMValueRef src0)
1331 {
1332 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1333 LLVMBuildNeg(ctx->builder, src0, ""));
1334 }
1335
1336 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1337 LLVMValueRef src0,
1338 unsigned bitsize)
1339 {
1340 LLVMValueRef cmp, val, zero, one;
1341 LLVMTypeRef type;
1342
1343 if (bitsize == 32) {
1344 type = ctx->f32;
1345 zero = ctx->f32_0;
1346 one = ctx->f32_1;
1347 } else {
1348 type = ctx->f64;
1349 zero = ctx->f64_0;
1350 one = ctx->f64_1;
1351 }
1352
1353 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1354 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1355 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1356 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1357 return val;
1358 }
1359
1360 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1361 LLVMValueRef src0, unsigned bitsize)
1362 {
1363 LLVMValueRef cmp, val, zero, one;
1364 LLVMTypeRef type;
1365
1366 if (bitsize == 32) {
1367 type = ctx->i32;
1368 zero = ctx->i32_0;
1369 one = ctx->i32_1;
1370 } else {
1371 type = ctx->i64;
1372 zero = ctx->i64_0;
1373 one = ctx->i64_1;
1374 }
1375
1376 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1377 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1378 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1379 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1380 return val;
1381 }
1382
1383 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1384 LLVMValueRef src0, unsigned bitsize)
1385 {
1386 LLVMTypeRef type;
1387 char *intr;
1388
1389 if (bitsize == 32) {
1390 intr = "llvm.floor.f32";
1391 type = ctx->f32;
1392 } else {
1393 intr = "llvm.floor.f64";
1394 type = ctx->f64;
1395 }
1396
1397 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1398 LLVMValueRef params[] = {
1399 fsrc0,
1400 };
1401 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1402 AC_FUNC_ATTR_READNONE);
1403 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1404 }
1405
1406 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1407 const char *intrin,
1408 LLVMValueRef src0, LLVMValueRef src1)
1409 {
1410 LLVMTypeRef ret_type;
1411 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1412 LLVMValueRef res;
1413 LLVMValueRef params[] = { src0, src1 };
1414 ret_type = LLVMStructTypeInContext(ctx->context, types,
1415 2, true);
1416
1417 res = ac_build_intrinsic(ctx, intrin, ret_type,
1418 params, 2, AC_FUNC_ATTR_READNONE);
1419
1420 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1421 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1422 return res;
1423 }
1424
1425 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1429 }
1430
1431 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1432 LLVMValueRef src0)
1433 {
1434 src0 = ac_to_float(ctx, src0);
1435 return LLVMBuildSExt(ctx->builder,
1436 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1437 ctx->i32, "");
1438 }
1439
1440 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0,
1442 unsigned bitsize)
1443 {
1444 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1445
1446 if (bitsize == 32)
1447 return result;
1448
1449 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1450 }
1451
1452 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1453 LLVMValueRef src0)
1454 {
1455 return LLVMBuildSExt(ctx->builder,
1456 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1457 ctx->i32, "");
1458 }
1459
1460 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1461 LLVMValueRef src0)
1462 {
1463 LLVMValueRef result;
1464 LLVMValueRef cond = NULL;
1465
1466 src0 = ac_to_float(&ctx->ac, src0);
1467 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1468
1469 if (ctx->options->chip_class >= VI) {
1470 LLVMValueRef args[2];
1471 /* Check if the result is a denormal - and flush to 0 if so. */
1472 args[0] = result;
1473 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1474 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1475 }
1476
1477 /* need to convert back up to f32 */
1478 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1479
1480 if (ctx->options->chip_class >= VI)
1481 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1482 else {
1483 /* for SI/CIK */
1484 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1485 * so compare the result and flush to 0 if it's smaller.
1486 */
1487 LLVMValueRef temp, cond2;
1488 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1489 ctx->ac.f32, result);
1490 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1491 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1492 temp, "");
1493 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1494 temp, ctx->ac.f32_0, "");
1495 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1496 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1497 }
1498 return result;
1499 }
1500
1501 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1502 LLVMValueRef src0, LLVMValueRef src1)
1503 {
1504 LLVMValueRef dst64, result;
1505 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1506 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1507
1508 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1509 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1510 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1511 return result;
1512 }
1513
1514 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1515 LLVMValueRef src0, LLVMValueRef src1)
1516 {
1517 LLVMValueRef dst64, result;
1518 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1519 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1520
1521 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1522 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1523 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1524 return result;
1525 }
1526
1527 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1528 bool is_signed,
1529 const LLVMValueRef srcs[3])
1530 {
1531 LLVMValueRef result;
1532 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1533
1534 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1535 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1536 return result;
1537 }
1538
1539 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1540 LLVMValueRef src0, LLVMValueRef src1,
1541 LLVMValueRef src2, LLVMValueRef src3)
1542 {
1543 LLVMValueRef bfi_args[3], result;
1544
1545 bfi_args[0] = LLVMBuildShl(ctx->builder,
1546 LLVMBuildSub(ctx->builder,
1547 LLVMBuildShl(ctx->builder,
1548 ctx->i32_1,
1549 src3, ""),
1550 ctx->i32_1, ""),
1551 src2, "");
1552 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1553 bfi_args[2] = src0;
1554
1555 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1556
1557 /* Calculate:
1558 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1559 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1560 */
1561 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1562 LLVMBuildAnd(ctx->builder, bfi_args[0],
1563 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1564
1565 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1566 return result;
1567 }
1568
1569 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1570 LLVMValueRef src0)
1571 {
1572 LLVMValueRef comp[2];
1573
1574 src0 = ac_to_float(ctx, src0);
1575 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1576 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1577
1578 return ac_build_cvt_pkrtz_f16(ctx, comp);
1579 }
1580
1581 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1582 LLVMValueRef src0)
1583 {
1584 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1585 LLVMValueRef temps[2], result, val;
1586 int i;
1587
1588 for (i = 0; i < 2; i++) {
1589 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1590 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1591 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1592 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1593 }
1594
1595 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1596 ctx->i32_0, "");
1597 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1598 ctx->i32_1, "");
1599 return result;
1600 }
1601
1602 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1603 nir_op op,
1604 LLVMValueRef src0)
1605 {
1606 unsigned mask;
1607 int idx;
1608 LLVMValueRef result;
1609
1610 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1611 mask = AC_TID_MASK_LEFT;
1612 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1613 mask = AC_TID_MASK_TOP;
1614 else
1615 mask = AC_TID_MASK_TOP_LEFT;
1616
1617 /* for DDX we want to next X pixel, DDY next Y pixel. */
1618 if (op == nir_op_fddx_fine ||
1619 op == nir_op_fddx_coarse ||
1620 op == nir_op_fddx)
1621 idx = 1;
1622 else
1623 idx = 2;
1624
1625 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1626 return result;
1627 }
1628
1629 /*
1630 * this takes an I,J coordinate pair,
1631 * and works out the X and Y derivatives.
1632 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1633 */
1634 static LLVMValueRef emit_ddxy_interp(
1635 struct ac_nir_context *ctx,
1636 LLVMValueRef interp_ij)
1637 {
1638 LLVMValueRef result[4], a;
1639 unsigned i;
1640
1641 for (i = 0; i < 2; i++) {
1642 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1643 LLVMConstInt(ctx->ac.i32, i, false), "");
1644 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1645 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1646 }
1647 return ac_build_gather_values(&ctx->ac, result, 4);
1648 }
1649
1650 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1651 {
1652 LLVMValueRef src[4], result = NULL;
1653 unsigned num_components = instr->dest.dest.ssa.num_components;
1654 unsigned src_components;
1655 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1656
1657 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1658 switch (instr->op) {
1659 case nir_op_vec2:
1660 case nir_op_vec3:
1661 case nir_op_vec4:
1662 src_components = 1;
1663 break;
1664 case nir_op_pack_half_2x16:
1665 src_components = 2;
1666 break;
1667 case nir_op_unpack_half_2x16:
1668 src_components = 1;
1669 break;
1670 default:
1671 src_components = num_components;
1672 break;
1673 }
1674 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1675 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1676
1677 switch (instr->op) {
1678 case nir_op_fmov:
1679 case nir_op_imov:
1680 result = src[0];
1681 break;
1682 case nir_op_fneg:
1683 src[0] = ac_to_float(&ctx->ac, src[0]);
1684 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1685 break;
1686 case nir_op_ineg:
1687 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1688 break;
1689 case nir_op_inot:
1690 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1691 break;
1692 case nir_op_iadd:
1693 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fadd:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_fsub:
1701 src[0] = ac_to_float(&ctx->ac, src[0]);
1702 src[1] = ac_to_float(&ctx->ac, src[1]);
1703 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1704 break;
1705 case nir_op_isub:
1706 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_imul:
1709 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_imod:
1712 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1713 break;
1714 case nir_op_umod:
1715 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1716 break;
1717 case nir_op_fmod:
1718 src[0] = ac_to_float(&ctx->ac, src[0]);
1719 src[1] = ac_to_float(&ctx->ac, src[1]);
1720 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1722 ac_to_float_type(&ctx->ac, def_type), result);
1723 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1724 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1725 break;
1726 case nir_op_frem:
1727 src[0] = ac_to_float(&ctx->ac, src[0]);
1728 src[1] = ac_to_float(&ctx->ac, src[1]);
1729 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1730 break;
1731 case nir_op_irem:
1732 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1733 break;
1734 case nir_op_idiv:
1735 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1736 break;
1737 case nir_op_udiv:
1738 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_fmul:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 src[1] = ac_to_float(&ctx->ac, src[1]);
1743 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_frcp:
1746 src[0] = ac_to_float(&ctx->ac, src[0]);
1747 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1748 src[0]);
1749 break;
1750 case nir_op_iand:
1751 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_ior:
1754 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1755 break;
1756 case nir_op_ixor:
1757 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1758 break;
1759 case nir_op_ishl:
1760 result = LLVMBuildShl(ctx->ac.builder, src[0],
1761 LLVMBuildZExt(ctx->ac.builder, src[1],
1762 LLVMTypeOf(src[0]), ""),
1763 "");
1764 break;
1765 case nir_op_ishr:
1766 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1767 LLVMBuildZExt(ctx->ac.builder, src[1],
1768 LLVMTypeOf(src[0]), ""),
1769 "");
1770 break;
1771 case nir_op_ushr:
1772 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1773 LLVMBuildZExt(ctx->ac.builder, src[1],
1774 LLVMTypeOf(src[0]), ""),
1775 "");
1776 break;
1777 case nir_op_ilt:
1778 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1779 break;
1780 case nir_op_ine:
1781 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1782 break;
1783 case nir_op_ieq:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1785 break;
1786 case nir_op_ige:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1788 break;
1789 case nir_op_ult:
1790 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1791 break;
1792 case nir_op_uge:
1793 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1794 break;
1795 case nir_op_feq:
1796 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1797 break;
1798 case nir_op_fne:
1799 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1800 break;
1801 case nir_op_flt:
1802 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1803 break;
1804 case nir_op_fge:
1805 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1806 break;
1807 case nir_op_fabs:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1809 ac_to_float_type(&ctx->ac, def_type), src[0]);
1810 break;
1811 case nir_op_iabs:
1812 result = emit_iabs(&ctx->ac, src[0]);
1813 break;
1814 case nir_op_imax:
1815 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1816 break;
1817 case nir_op_imin:
1818 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1819 break;
1820 case nir_op_umax:
1821 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1822 break;
1823 case nir_op_umin:
1824 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1825 break;
1826 case nir_op_isign:
1827 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1828 break;
1829 case nir_op_fsign:
1830 src[0] = ac_to_float(&ctx->ac, src[0]);
1831 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1832 break;
1833 case nir_op_ffloor:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_ftrunc:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fceil:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_fround_even:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1847 ac_to_float_type(&ctx->ac, def_type),src[0]);
1848 break;
1849 case nir_op_ffract:
1850 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1851 break;
1852 case nir_op_fsin:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1854 ac_to_float_type(&ctx->ac, def_type), src[0]);
1855 break;
1856 case nir_op_fcos:
1857 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1858 ac_to_float_type(&ctx->ac, def_type), src[0]);
1859 break;
1860 case nir_op_fsqrt:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fexp2:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_flog2:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_frsq:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1876 result);
1877 break;
1878 case nir_op_fpow:
1879 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1880 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1881 break;
1882 case nir_op_fmax:
1883 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1884 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1885 if (ctx->ac.chip_class < GFX9 &&
1886 instr->dest.dest.ssa.bit_size == 32) {
1887 /* Only pre-GFX9 chips do not flush denorms. */
1888 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1889 ac_to_float_type(&ctx->ac, def_type),
1890 result);
1891 }
1892 break;
1893 case nir_op_fmin:
1894 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1895 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1896 if (ctx->ac.chip_class < GFX9 &&
1897 instr->dest.dest.ssa.bit_size == 32) {
1898 /* Only pre-GFX9 chips do not flush denorms. */
1899 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1900 ac_to_float_type(&ctx->ac, def_type),
1901 result);
1902 }
1903 break;
1904 case nir_op_ffma:
1905 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1906 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1907 break;
1908 case nir_op_ibitfield_extract:
1909 result = emit_bitfield_extract(&ctx->ac, true, src);
1910 break;
1911 case nir_op_ubitfield_extract:
1912 result = emit_bitfield_extract(&ctx->ac, false, src);
1913 break;
1914 case nir_op_bitfield_insert:
1915 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1916 break;
1917 case nir_op_bitfield_reverse:
1918 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1919 break;
1920 case nir_op_bit_count:
1921 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1922 break;
1923 case nir_op_vec2:
1924 case nir_op_vec3:
1925 case nir_op_vec4:
1926 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1927 src[i] = ac_to_integer(&ctx->ac, src[i]);
1928 result = ac_build_gather_values(&ctx->ac, src, num_components);
1929 break;
1930 case nir_op_f2i32:
1931 case nir_op_f2i64:
1932 src[0] = ac_to_float(&ctx->ac, src[0]);
1933 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1934 break;
1935 case nir_op_f2u32:
1936 case nir_op_f2u64:
1937 src[0] = ac_to_float(&ctx->ac, src[0]);
1938 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1939 break;
1940 case nir_op_i2f32:
1941 case nir_op_i2f64:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1944 break;
1945 case nir_op_u2f32:
1946 case nir_op_u2f64:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1949 break;
1950 case nir_op_f2f64:
1951 src[0] = ac_to_float(&ctx->ac, src[0]);
1952 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_f2f32:
1955 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1956 break;
1957 case nir_op_u2u32:
1958 case nir_op_u2u64:
1959 src[0] = ac_to_integer(&ctx->ac, src[0]);
1960 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1961 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1962 else
1963 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1964 break;
1965 case nir_op_i2i32:
1966 case nir_op_i2i64:
1967 src[0] = ac_to_integer(&ctx->ac, src[0]);
1968 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1969 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1970 else
1971 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1972 break;
1973 case nir_op_bcsel:
1974 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1975 break;
1976 case nir_op_find_lsb:
1977 src[0] = ac_to_integer(&ctx->ac, src[0]);
1978 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1979 break;
1980 case nir_op_ufind_msb:
1981 src[0] = ac_to_integer(&ctx->ac, src[0]);
1982 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1983 break;
1984 case nir_op_ifind_msb:
1985 src[0] = ac_to_integer(&ctx->ac, src[0]);
1986 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1987 break;
1988 case nir_op_uadd_carry:
1989 src[0] = ac_to_integer(&ctx->ac, src[0]);
1990 src[1] = ac_to_integer(&ctx->ac, src[1]);
1991 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1992 break;
1993 case nir_op_usub_borrow:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1997 break;
1998 case nir_op_b2f:
1999 result = emit_b2f(&ctx->ac, src[0]);
2000 break;
2001 case nir_op_f2b:
2002 result = emit_f2b(&ctx->ac, src[0]);
2003 break;
2004 case nir_op_b2i:
2005 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2006 break;
2007 case nir_op_i2b:
2008 src[0] = ac_to_integer(&ctx->ac, src[0]);
2009 result = emit_i2b(&ctx->ac, src[0]);
2010 break;
2011 case nir_op_fquantize2f16:
2012 result = emit_f2f16(ctx->nctx, src[0]);
2013 break;
2014 case nir_op_umul_high:
2015 src[0] = ac_to_integer(&ctx->ac, src[0]);
2016 src[1] = ac_to_integer(&ctx->ac, src[1]);
2017 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2018 break;
2019 case nir_op_imul_high:
2020 src[0] = ac_to_integer(&ctx->ac, src[0]);
2021 src[1] = ac_to_integer(&ctx->ac, src[1]);
2022 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2023 break;
2024 case nir_op_pack_half_2x16:
2025 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2026 break;
2027 case nir_op_unpack_half_2x16:
2028 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2029 break;
2030 case nir_op_fddx:
2031 case nir_op_fddy:
2032 case nir_op_fddx_fine:
2033 case nir_op_fddy_fine:
2034 case nir_op_fddx_coarse:
2035 case nir_op_fddy_coarse:
2036 result = emit_ddxy(ctx, instr->op, src[0]);
2037 break;
2038
2039 case nir_op_unpack_64_2x32_split_x: {
2040 assert(instr->src[0].src.ssa->num_components == 1);
2041 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2042 ctx->ac.v2i32,
2043 "");
2044 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2045 ctx->ac.i32_0, "");
2046 break;
2047 }
2048
2049 case nir_op_unpack_64_2x32_split_y: {
2050 assert(instr->src[0].src.ssa->num_components == 1);
2051 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2052 ctx->ac.v2i32,
2053 "");
2054 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2055 ctx->ac.i32_1, "");
2056 break;
2057 }
2058
2059 case nir_op_pack_64_2x32_split: {
2060 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2061 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2062 src[0], ctx->ac.i32_0, "");
2063 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2064 src[1], ctx->ac.i32_1, "");
2065 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2066 break;
2067 }
2068
2069 default:
2070 fprintf(stderr, "Unknown NIR alu instr: ");
2071 nir_print_instr(&instr->instr, stderr);
2072 fprintf(stderr, "\n");
2073 abort();
2074 }
2075
2076 if (result) {
2077 assert(instr->dest.dest.is_ssa);
2078 result = ac_to_integer(&ctx->ac, result);
2079 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2080 result);
2081 }
2082 }
2083
2084 static void visit_load_const(struct ac_nir_context *ctx,
2085 const nir_load_const_instr *instr)
2086 {
2087 LLVMValueRef values[4], value = NULL;
2088 LLVMTypeRef element_type =
2089 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2090
2091 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2092 switch (instr->def.bit_size) {
2093 case 32:
2094 values[i] = LLVMConstInt(element_type,
2095 instr->value.u32[i], false);
2096 break;
2097 case 64:
2098 values[i] = LLVMConstInt(element_type,
2099 instr->value.u64[i], false);
2100 break;
2101 default:
2102 fprintf(stderr,
2103 "unsupported nir load_const bit_size: %d\n",
2104 instr->def.bit_size);
2105 abort();
2106 }
2107 }
2108 if (instr->def.num_components > 1) {
2109 value = LLVMConstVector(values, instr->def.num_components);
2110 } else
2111 value = values[0];
2112
2113 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2114 }
2115
2116 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2117 LLVMTypeRef type)
2118 {
2119 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2120 return LLVMBuildBitCast(ctx->builder, ptr,
2121 LLVMPointerType(type, addr_space), "");
2122 }
2123
2124 static LLVMValueRef
2125 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2126 {
2127 LLVMValueRef size =
2128 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2129 LLVMConstInt(ctx->ac.i32, 2, false), "");
2130
2131 /* VI only */
2132 if (ctx->ac.chip_class == VI && in_elements) {
2133 /* On VI, the descriptor contains the size in bytes,
2134 * but TXQ must return the size in elements.
2135 * The stride is always non-zero for resources using TXQ.
2136 */
2137 LLVMValueRef stride =
2138 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2139 ctx->ac.i32_1, "");
2140 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2141 LLVMConstInt(ctx->ac.i32, 16, false), "");
2142 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2143 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2144
2145 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2146 }
2147 return size;
2148 }
2149
2150 /**
2151 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2152 * intrinsic names).
2153 */
2154 static void build_int_type_name(
2155 LLVMTypeRef type,
2156 char *buf, unsigned bufsize)
2157 {
2158 assert(bufsize >= 6);
2159
2160 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2161 snprintf(buf, bufsize, "v%ui32",
2162 LLVMGetVectorSize(type));
2163 else
2164 strcpy(buf, "i32");
2165 }
2166
2167 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2168 struct ac_image_args *args,
2169 const nir_tex_instr *instr)
2170 {
2171 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2172 LLVMValueRef coord = args->addr;
2173 LLVMValueRef half_texel[2];
2174 LLVMValueRef compare_cube_wa = NULL;
2175 LLVMValueRef result;
2176 int c;
2177 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2178
2179 //TODO Rect
2180 {
2181 struct ac_image_args txq_args = { 0 };
2182
2183 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2184 txq_args.opcode = ac_image_get_resinfo;
2185 txq_args.dmask = 0xf;
2186 txq_args.addr = ctx->i32_0;
2187 txq_args.resource = args->resource;
2188 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2189
2190 for (c = 0; c < 2; c++) {
2191 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2192 LLVMConstInt(ctx->i32, c, false), "");
2193 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2194 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2195 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2196 LLVMConstReal(ctx->f32, -0.5), "");
2197 }
2198 }
2199
2200 LLVMValueRef orig_coords = args->addr;
2201
2202 for (c = 0; c < 2; c++) {
2203 LLVMValueRef tmp;
2204 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2205 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2206 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2207 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2208 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2209 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2210 }
2211
2212
2213 /*
2214 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2215 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2216 * workaround by sampling using a scaled type and converting.
2217 * This is taken from amdgpu-pro shaders.
2218 */
2219 /* NOTE this produces some ugly code compared to amdgpu-pro,
2220 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2221 * and then reads them back. -pro generates two selects,
2222 * one s_cmp for the descriptor rewriting
2223 * one v_cmp for the coordinate and result changes.
2224 */
2225 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2226 LLVMValueRef tmp, tmp2;
2227
2228 /* workaround 8/8/8/8 uint/sint cube gather bug */
2229 /* first detect it then change to a scaled read and f2i */
2230 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2231 tmp2 = tmp;
2232
2233 /* extract the DATA_FORMAT */
2234 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2235 LLVMConstInt(ctx->i32, 6, false), false);
2236
2237 /* is the DATA_FORMAT == 8_8_8_8 */
2238 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2239
2240 if (stype == GLSL_TYPE_UINT)
2241 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2242 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2243 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2244 else
2245 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2246 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2247 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2248
2249 /* replace the NUM FORMAT in the descriptor */
2250 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2251 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2252
2253 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2254
2255 /* don't modify the coordinates for this case */
2256 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2257 }
2258 args->addr = coord;
2259 result = ac_build_image_opcode(ctx, args);
2260
2261 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2262 LLVMValueRef tmp, tmp2;
2263
2264 /* if the cube workaround is in place, f2i the result. */
2265 for (c = 0; c < 4; c++) {
2266 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2267 if (stype == GLSL_TYPE_UINT)
2268 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2269 else
2270 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2271 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2272 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2273 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2274 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2275 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2276 }
2277 }
2278 return result;
2279 }
2280
2281 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2282 const nir_tex_instr *instr,
2283 bool lod_is_zero,
2284 struct ac_image_args *args)
2285 {
2286 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2287 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2288
2289 return ac_build_buffer_load_format(&ctx->ac,
2290 args->resource,
2291 args->addr,
2292 ctx->ac.i32_0,
2293 util_last_bit(mask),
2294 false, true);
2295 }
2296
2297 args->opcode = ac_image_sample;
2298 args->compare = instr->is_shadow;
2299
2300 switch (instr->op) {
2301 case nir_texop_txf:
2302 case nir_texop_txf_ms:
2303 case nir_texop_samples_identical:
2304 args->opcode = lod_is_zero ||
2305 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2306 ac_image_load : ac_image_load_mip;
2307 args->compare = false;
2308 args->offset = false;
2309 break;
2310 case nir_texop_txb:
2311 args->bias = true;
2312 break;
2313 case nir_texop_txl:
2314 if (lod_is_zero)
2315 args->level_zero = true;
2316 else
2317 args->lod = true;
2318 break;
2319 case nir_texop_txs:
2320 case nir_texop_query_levels:
2321 args->opcode = ac_image_get_resinfo;
2322 break;
2323 case nir_texop_tex:
2324 if (ctx->stage != MESA_SHADER_FRAGMENT)
2325 args->level_zero = true;
2326 break;
2327 case nir_texop_txd:
2328 args->deriv = true;
2329 break;
2330 case nir_texop_tg4:
2331 args->opcode = ac_image_gather4;
2332 args->level_zero = true;
2333 break;
2334 case nir_texop_lod:
2335 args->opcode = ac_image_get_lod;
2336 args->compare = false;
2337 args->offset = false;
2338 break;
2339 default:
2340 break;
2341 }
2342
2343 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2344 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2345 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2346 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2347 }
2348 }
2349 return ac_build_image_opcode(&ctx->ac, args);
2350 }
2351
2352 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2353 nir_intrinsic_instr *instr)
2354 {
2355 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2356 unsigned desc_set = nir_intrinsic_desc_set(instr);
2357 unsigned binding = nir_intrinsic_binding(instr);
2358 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2359 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2360 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2361 unsigned base_offset = layout->binding[binding].offset;
2362 LLVMValueRef offset, stride;
2363
2364 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2365 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2366 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2367 layout->binding[binding].dynamic_offset_offset;
2368 desc_ptr = ctx->push_constants;
2369 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2370 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2371 } else
2372 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2373
2374 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2375 index = LLVMBuildMul(ctx->builder, index, stride, "");
2376 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2377
2378 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2379 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2380 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2381
2382 return desc_ptr;
2383 }
2384
2385 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2389 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2390
2391 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2392 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2393 return result;
2394 }
2395
2396 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2397 nir_intrinsic_instr *instr)
2398 {
2399 LLVMValueRef ptr, addr;
2400
2401 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2402 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2403
2404 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2405 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2406
2407 return LLVMBuildLoad(ctx->builder, ptr, "");
2408 }
2409
2410 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2411 const nir_intrinsic_instr *instr)
2412 {
2413 LLVMValueRef index = get_src(ctx, instr->src[0]);
2414
2415 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2416 }
2417
2418 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2419 {
2420 uint32_t new_mask = 0;
2421 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2422 if (mask & (1u << i))
2423 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2424 return new_mask;
2425 }
2426
2427 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2428 unsigned start, unsigned count)
2429 {
2430 LLVMTypeRef type = LLVMTypeOf(src);
2431
2432 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2433 assert(start == 0);
2434 assert(count == 1);
2435 return src;
2436 }
2437
2438 unsigned src_elements = LLVMGetVectorSize(type);
2439 assert(start < src_elements);
2440 assert(start + count <= src_elements);
2441
2442 if (start == 0 && count == src_elements)
2443 return src;
2444
2445 if (count == 1)
2446 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2447
2448 assert(count <= 8);
2449 LLVMValueRef indices[8];
2450 for (unsigned i = 0; i < count; ++i)
2451 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2452
2453 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2454 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2455 }
2456
2457 static void visit_store_ssbo(struct ac_nir_context *ctx,
2458 nir_intrinsic_instr *instr)
2459 {
2460 const char *store_name;
2461 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2462 LLVMTypeRef data_type = ctx->ac.f32;
2463 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2464 int components_32bit = elem_size_mult * instr->num_components;
2465 unsigned writemask = nir_intrinsic_write_mask(instr);
2466 LLVMValueRef base_data, base_offset;
2467 LLVMValueRef params[6];
2468
2469 params[1] = ctx->abi->load_ssbo(ctx->abi,
2470 get_src(ctx, instr->src[1]), true);
2471 params[2] = ctx->ac.i32_0; /* vindex */
2472 params[4] = ctx->ac.i1false; /* glc */
2473 params[5] = ctx->ac.i1false; /* slc */
2474
2475 if (components_32bit > 1)
2476 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2477
2478 writemask = widen_mask(writemask, elem_size_mult);
2479
2480 base_data = ac_to_float(&ctx->ac, src_data);
2481 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2482 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2483 data_type, "");
2484 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2485 while (writemask) {
2486 int start, count;
2487 LLVMValueRef data;
2488 LLVMValueRef offset;
2489
2490 u_bit_scan_consecutive_range(&writemask, &start, &count);
2491
2492 /* Due to an LLVM limitation, split 3-element writes
2493 * into a 2-element and a 1-element write. */
2494 if (count == 3) {
2495 writemask |= 1 << (start + 2);
2496 count = 2;
2497 }
2498
2499 if (count > 4) {
2500 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2501 count = 4;
2502 }
2503
2504 if (count == 4) {
2505 store_name = "llvm.amdgcn.buffer.store.v4f32";
2506 } else if (count == 2) {
2507 store_name = "llvm.amdgcn.buffer.store.v2f32";
2508
2509 } else {
2510 assert(count == 1);
2511 store_name = "llvm.amdgcn.buffer.store.f32";
2512 }
2513 data = extract_vector_range(&ctx->ac, base_data, start, count);
2514
2515 offset = base_offset;
2516 if (start != 0) {
2517 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2518 }
2519 params[0] = data;
2520 params[3] = offset;
2521 ac_build_intrinsic(&ctx->ac, store_name,
2522 ctx->ac.voidt, params, 6, 0);
2523 }
2524 }
2525
2526 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2527 const nir_intrinsic_instr *instr)
2528 {
2529 const char *name;
2530 LLVMValueRef params[6];
2531 int arg_count = 0;
2532
2533 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2534 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2535 }
2536 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2537 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2538 get_src(ctx, instr->src[0]),
2539 true);
2540 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2541 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2542 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2543
2544 switch (instr->intrinsic) {
2545 case nir_intrinsic_ssbo_atomic_add:
2546 name = "llvm.amdgcn.buffer.atomic.add";
2547 break;
2548 case nir_intrinsic_ssbo_atomic_imin:
2549 name = "llvm.amdgcn.buffer.atomic.smin";
2550 break;
2551 case nir_intrinsic_ssbo_atomic_umin:
2552 name = "llvm.amdgcn.buffer.atomic.umin";
2553 break;
2554 case nir_intrinsic_ssbo_atomic_imax:
2555 name = "llvm.amdgcn.buffer.atomic.smax";
2556 break;
2557 case nir_intrinsic_ssbo_atomic_umax:
2558 name = "llvm.amdgcn.buffer.atomic.umax";
2559 break;
2560 case nir_intrinsic_ssbo_atomic_and:
2561 name = "llvm.amdgcn.buffer.atomic.and";
2562 break;
2563 case nir_intrinsic_ssbo_atomic_or:
2564 name = "llvm.amdgcn.buffer.atomic.or";
2565 break;
2566 case nir_intrinsic_ssbo_atomic_xor:
2567 name = "llvm.amdgcn.buffer.atomic.xor";
2568 break;
2569 case nir_intrinsic_ssbo_atomic_exchange:
2570 name = "llvm.amdgcn.buffer.atomic.swap";
2571 break;
2572 case nir_intrinsic_ssbo_atomic_comp_swap:
2573 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2574 break;
2575 default:
2576 abort();
2577 }
2578
2579 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2580 }
2581
2582 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2583 const nir_intrinsic_instr *instr)
2584 {
2585 LLVMValueRef results[2];
2586 int load_components;
2587 int num_components = instr->num_components;
2588 if (instr->dest.ssa.bit_size == 64)
2589 num_components *= 2;
2590
2591 for (int i = 0; i < num_components; i += load_components) {
2592 load_components = MIN2(num_components - i, 4);
2593 const char *load_name;
2594 LLVMTypeRef data_type = ctx->ac.f32;
2595 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2596 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2597
2598 if (load_components == 3)
2599 data_type = LLVMVectorType(ctx->ac.f32, 4);
2600 else if (load_components > 1)
2601 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2602
2603 if (load_components >= 3)
2604 load_name = "llvm.amdgcn.buffer.load.v4f32";
2605 else if (load_components == 2)
2606 load_name = "llvm.amdgcn.buffer.load.v2f32";
2607 else if (load_components == 1)
2608 load_name = "llvm.amdgcn.buffer.load.f32";
2609 else
2610 unreachable("unhandled number of components");
2611
2612 LLVMValueRef params[] = {
2613 ctx->abi->load_ssbo(ctx->abi,
2614 get_src(ctx, instr->src[0]),
2615 false),
2616 ctx->ac.i32_0,
2617 offset,
2618 ctx->ac.i1false,
2619 ctx->ac.i1false,
2620 };
2621
2622 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2623 }
2624
2625 assume(results[0]);
2626 LLVMValueRef ret = results[0];
2627 if (num_components > 4 || num_components == 3) {
2628 LLVMValueRef masks[] = {
2629 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2630 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2631 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2632 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2633 };
2634
2635 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2636 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2637 results[num_components > 4 ? 1 : 0], swizzle, "");
2638 }
2639
2640 return LLVMBuildBitCast(ctx->ac.builder, ret,
2641 get_def_type(ctx, &instr->dest.ssa), "");
2642 }
2643
2644 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2645 const nir_intrinsic_instr *instr)
2646 {
2647 LLVMValueRef ret;
2648 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2649 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2650 int num_components = instr->num_components;
2651
2652 if (ctx->abi->load_ubo)
2653 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2654
2655 if (instr->dest.ssa.bit_size == 64)
2656 num_components *= 2;
2657
2658 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2659 NULL, 0, false, false, true, true);
2660 ret = trim_vector(&ctx->ac, ret, num_components);
2661 return LLVMBuildBitCast(ctx->ac.builder, ret,
2662 get_def_type(ctx, &instr->dest.ssa), "");
2663 }
2664
2665 static void
2666 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2667 bool vs_in, unsigned *vertex_index_out,
2668 LLVMValueRef *vertex_index_ref,
2669 unsigned *const_out, LLVMValueRef *indir_out)
2670 {
2671 unsigned const_offset = 0;
2672 nir_deref *tail = &deref->deref;
2673 LLVMValueRef offset = NULL;
2674
2675 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2676 tail = tail->child;
2677 nir_deref_array *deref_array = nir_deref_as_array(tail);
2678 if (vertex_index_out)
2679 *vertex_index_out = deref_array->base_offset;
2680
2681 if (vertex_index_ref) {
2682 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2683 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2684 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2685 }
2686 *vertex_index_ref = vtx;
2687 }
2688 }
2689
2690 if (deref->var->data.compact) {
2691 assert(tail->child->deref_type == nir_deref_type_array);
2692 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2693 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2694 /* We always lower indirect dereferences for "compact" array vars. */
2695 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2696
2697 const_offset = deref_array->base_offset;
2698 goto out;
2699 }
2700
2701 while (tail->child != NULL) {
2702 const struct glsl_type *parent_type = tail->type;
2703 tail = tail->child;
2704
2705 if (tail->deref_type == nir_deref_type_array) {
2706 nir_deref_array *deref_array = nir_deref_as_array(tail);
2707 LLVMValueRef index, stride, local_offset;
2708 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2709
2710 const_offset += size * deref_array->base_offset;
2711 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2712 continue;
2713
2714 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2715 index = get_src(ctx, deref_array->indirect);
2716 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2717 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2718
2719 if (offset)
2720 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2721 else
2722 offset = local_offset;
2723 } else if (tail->deref_type == nir_deref_type_struct) {
2724 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2725
2726 for (unsigned i = 0; i < deref_struct->index; i++) {
2727 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2728 const_offset += glsl_count_attribute_slots(ft, vs_in);
2729 }
2730 } else
2731 unreachable("unsupported deref type");
2732
2733 }
2734 out:
2735 if (const_offset && offset)
2736 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2737 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2738 "");
2739
2740 *const_out = const_offset;
2741 *indir_out = offset;
2742 }
2743
2744
2745 /* The offchip buffer layout for TCS->TES is
2746 *
2747 * - attribute 0 of patch 0 vertex 0
2748 * - attribute 0 of patch 0 vertex 1
2749 * - attribute 0 of patch 0 vertex 2
2750 * ...
2751 * - attribute 0 of patch 1 vertex 0
2752 * - attribute 0 of patch 1 vertex 1
2753 * ...
2754 * - attribute 1 of patch 0 vertex 0
2755 * - attribute 1 of patch 0 vertex 1
2756 * ...
2757 * - per patch attribute 0 of patch 0
2758 * - per patch attribute 0 of patch 1
2759 * ...
2760 *
2761 * Note that every attribute has 4 components.
2762 */
2763 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2764 LLVMValueRef vertex_index,
2765 LLVMValueRef param_index)
2766 {
2767 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2768 LLVMValueRef param_stride, constant16;
2769 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2770
2771 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2772 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2773 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2774 num_patches, "");
2775
2776 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2777 if (vertex_index) {
2778 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2779 vertices_per_patch, "");
2780
2781 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2782 vertex_index, "");
2783
2784 param_stride = total_vertices;
2785 } else {
2786 base_addr = rel_patch_id;
2787 param_stride = num_patches;
2788 }
2789
2790 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2791 LLVMBuildMul(ctx->builder, param_index,
2792 param_stride, ""), "");
2793
2794 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2795
2796 if (!vertex_index) {
2797 LLVMValueRef patch_data_offset =
2798 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2799
2800 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2801 patch_data_offset, "");
2802 }
2803 return base_addr;
2804 }
2805
2806 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2807 unsigned param,
2808 unsigned const_index,
2809 bool is_compact,
2810 LLVMValueRef vertex_index,
2811 LLVMValueRef indir_index)
2812 {
2813 LLVMValueRef param_index;
2814
2815 if (indir_index)
2816 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2817 indir_index, "");
2818 else {
2819 if (const_index && !is_compact)
2820 param += const_index;
2821 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2822 }
2823 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2824 }
2825
2826 static void
2827 mark_tess_output(struct nir_to_llvm_context *ctx,
2828 bool is_patch, uint32_t param)
2829
2830 {
2831 if (is_patch) {
2832 ctx->tess_patch_outputs_written |= (1ull << param);
2833 } else
2834 ctx->tess_outputs_written |= (1ull << param);
2835 }
2836
2837 static LLVMValueRef
2838 get_dw_address(struct nir_to_llvm_context *ctx,
2839 LLVMValueRef dw_addr,
2840 unsigned param,
2841 unsigned const_index,
2842 bool compact_const_index,
2843 LLVMValueRef vertex_index,
2844 LLVMValueRef stride,
2845 LLVMValueRef indir_index)
2846
2847 {
2848
2849 if (vertex_index) {
2850 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2851 LLVMBuildMul(ctx->builder,
2852 vertex_index,
2853 stride, ""), "");
2854 }
2855
2856 if (indir_index)
2857 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2858 LLVMBuildMul(ctx->builder, indir_index,
2859 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2860 else if (const_index && !compact_const_index)
2861 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2862 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2863
2864 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2865 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2866
2867 if (const_index && compact_const_index)
2868 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2869 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2870 return dw_addr;
2871 }
2872
2873 static LLVMValueRef
2874 load_tcs_varyings(struct ac_shader_abi *abi,
2875 LLVMValueRef vertex_index,
2876 LLVMValueRef indir_index,
2877 unsigned const_index,
2878 unsigned location,
2879 unsigned driver_location,
2880 unsigned component,
2881 unsigned num_components,
2882 bool is_patch,
2883 bool is_compact,
2884 bool load_input)
2885 {
2886 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2887 LLVMValueRef dw_addr, stride;
2888 LLVMValueRef value[4], result;
2889 unsigned param = shader_io_get_unique_index(location);
2890
2891 if (load_input) {
2892 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2893 dw_addr = get_tcs_in_current_patch_offset(ctx);
2894 } else {
2895 if (!is_patch) {
2896 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2897 dw_addr = get_tcs_out_current_patch_offset(ctx);
2898 } else {
2899 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2900 stride = NULL;
2901 }
2902 }
2903
2904 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2905 indir_index);
2906
2907 for (unsigned i = 0; i < num_components + component; i++) {
2908 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2909 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2910 ctx->ac.i32_1, "");
2911 }
2912 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2913 return result;
2914 }
2915
2916 static void
2917 store_tcs_output(struct ac_shader_abi *abi,
2918 LLVMValueRef vertex_index,
2919 LLVMValueRef param_index,
2920 unsigned const_index,
2921 unsigned location,
2922 unsigned driver_location,
2923 LLVMValueRef src,
2924 unsigned component,
2925 bool is_patch,
2926 bool is_compact,
2927 unsigned writemask)
2928 {
2929 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2930 LLVMValueRef dw_addr;
2931 LLVMValueRef stride = NULL;
2932 LLVMValueRef buf_addr = NULL;
2933 unsigned param;
2934 bool store_lds = true;
2935
2936 if (is_patch) {
2937 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2938 store_lds = false;
2939 } else {
2940 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2941 store_lds = false;
2942 }
2943
2944 param = shader_io_get_unique_index(location);
2945 if (location == VARYING_SLOT_CLIP_DIST0 &&
2946 is_compact && const_index > 3) {
2947 const_index -= 3;
2948 param++;
2949 }
2950
2951 if (!is_patch) {
2952 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2953 dw_addr = get_tcs_out_current_patch_offset(ctx);
2954 } else {
2955 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2956 }
2957
2958 mark_tess_output(ctx, is_patch, param);
2959
2960 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2961 param_index);
2962 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2963 vertex_index, param_index);
2964
2965 bool is_tess_factor = false;
2966 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2967 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2968 is_tess_factor = true;
2969
2970 unsigned base = is_compact ? const_index : 0;
2971 for (unsigned chan = 0; chan < 8; chan++) {
2972 if (!(writemask & (1 << chan)))
2973 continue;
2974 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2975
2976 if (store_lds || is_tess_factor) {
2977 LLVMValueRef dw_addr_chan =
2978 LLVMBuildAdd(ctx->builder, dw_addr,
2979 LLVMConstInt(ctx->ac.i32, chan, false), "");
2980 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2981 }
2982
2983 if (!is_tess_factor && writemask != 0xF)
2984 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2985 buf_addr, ctx->oc_lds,
2986 4 * (base + chan), 1, 0, true, false);
2987 }
2988
2989 if (writemask == 0xF) {
2990 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2991 buf_addr, ctx->oc_lds,
2992 (base * 4), 1, 0, true, false);
2993 }
2994 }
2995
2996 static LLVMValueRef
2997 load_tes_input(struct ac_shader_abi *abi,
2998 LLVMValueRef vertex_index,
2999 LLVMValueRef param_index,
3000 unsigned const_index,
3001 unsigned location,
3002 unsigned driver_location,
3003 unsigned component,
3004 unsigned num_components,
3005 bool is_patch,
3006 bool is_compact,
3007 bool load_input)
3008 {
3009 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3010 LLVMValueRef buf_addr;
3011 LLVMValueRef result;
3012 unsigned param = shader_io_get_unique_index(location);
3013
3014 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3015 const_index -= 3;
3016 param++;
3017 }
3018
3019 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3020 is_compact, vertex_index, param_index);
3021
3022 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3023 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3024
3025 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3026 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3027 result = trim_vector(&ctx->ac, result, num_components);
3028 return result;
3029 }
3030
3031 static LLVMValueRef
3032 load_gs_input(struct ac_shader_abi *abi,
3033 unsigned location,
3034 unsigned driver_location,
3035 unsigned component,
3036 unsigned num_components,
3037 unsigned vertex_index,
3038 unsigned const_index,
3039 LLVMTypeRef type)
3040 {
3041 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3042 LLVMValueRef vtx_offset;
3043 unsigned param, vtx_offset_param;
3044 LLVMValueRef value[4], result;
3045
3046 vtx_offset_param = vertex_index;
3047 assert(vtx_offset_param < 6);
3048 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3049 LLVMConstInt(ctx->ac.i32, 4, false), "");
3050
3051 param = shader_io_get_unique_index(location);
3052
3053 for (unsigned i = component; i < num_components + component; i++) {
3054 if (ctx->ac.chip_class >= GFX9) {
3055 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3056 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3057 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3058 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3059 } else {
3060 LLVMValueRef soffset =
3061 LLVMConstInt(ctx->ac.i32,
3062 (param * 4 + i + const_index) * 256,
3063 false);
3064
3065 value[i] = ac_build_buffer_load(&ctx->ac,
3066 ctx->esgs_ring, 1,
3067 ctx->ac.i32_0,
3068 vtx_offset, soffset,
3069 0, 1, 0, true, false);
3070
3071 value[i] = LLVMBuildBitCast(ctx->builder, value[i],
3072 type, "");
3073 }
3074 }
3075 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3076 result = ac_to_integer(&ctx->ac, result);
3077 return result;
3078 }
3079
3080 static LLVMValueRef
3081 build_gep_for_deref(struct ac_nir_context *ctx,
3082 nir_deref_var *deref)
3083 {
3084 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3085 assert(entry->data);
3086 LLVMValueRef val = entry->data;
3087 nir_deref *tail = deref->deref.child;
3088 while (tail != NULL) {
3089 LLVMValueRef offset;
3090 switch (tail->deref_type) {
3091 case nir_deref_type_array: {
3092 nir_deref_array *array = nir_deref_as_array(tail);
3093 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3094 if (array->deref_array_type ==
3095 nir_deref_array_type_indirect) {
3096 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3097 get_src(ctx,
3098 array->indirect),
3099 "");
3100 }
3101 break;
3102 }
3103 case nir_deref_type_struct: {
3104 nir_deref_struct *deref_struct =
3105 nir_deref_as_struct(tail);
3106 offset = LLVMConstInt(ctx->ac.i32,
3107 deref_struct->index, 0);
3108 break;
3109 }
3110 default:
3111 unreachable("bad deref type");
3112 }
3113 val = ac_build_gep0(&ctx->ac, val, offset);
3114 tail = tail->child;
3115 }
3116 return val;
3117 }
3118
3119 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3120 nir_intrinsic_instr *instr,
3121 bool load_inputs)
3122 {
3123 LLVMValueRef result;
3124 LLVMValueRef vertex_index = NULL;
3125 LLVMValueRef indir_index = NULL;
3126 unsigned const_index = 0;
3127 unsigned location = instr->variables[0]->var->data.location;
3128 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3129 const bool is_patch = instr->variables[0]->var->data.patch;
3130 const bool is_compact = instr->variables[0]->var->data.compact;
3131
3132 get_deref_offset(ctx, instr->variables[0],
3133 false, NULL, is_patch ? NULL : &vertex_index,
3134 &const_index, &indir_index);
3135
3136 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3137 const_index, location, driver_location,
3138 instr->variables[0]->var->data.location_frac,
3139 instr->num_components,
3140 is_patch, is_compact, load_inputs);
3141 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3142 }
3143
3144 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3145 nir_intrinsic_instr *instr)
3146 {
3147 LLVMValueRef values[8];
3148 int idx = instr->variables[0]->var->data.driver_location;
3149 int ve = instr->dest.ssa.num_components;
3150 unsigned comp = instr->variables[0]->var->data.location_frac;
3151 LLVMValueRef indir_index;
3152 LLVMValueRef ret;
3153 unsigned const_index;
3154 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3155 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3156 instr->variables[0]->var->data.mode == nir_var_shader_in;
3157 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3158 &const_index, &indir_index);
3159
3160 if (instr->dest.ssa.bit_size == 64)
3161 ve *= 2;
3162
3163 switch (instr->variables[0]->var->data.mode) {
3164 case nir_var_shader_in:
3165 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3166 ctx->stage == MESA_SHADER_TESS_EVAL) {
3167 return load_tess_varyings(ctx, instr, true);
3168 }
3169
3170 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3171 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3172 LLVMValueRef indir_index;
3173 unsigned const_index, vertex_index;
3174 get_deref_offset(ctx, instr->variables[0],
3175 false, &vertex_index, NULL,
3176 &const_index, &indir_index);
3177
3178 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3179 instr->variables[0]->var->data.driver_location,
3180 instr->variables[0]->var->data.location_frac, ve,
3181 vertex_index, const_index, type);
3182 }
3183
3184 for (unsigned chan = comp; chan < ve + comp; chan++) {
3185 if (indir_index) {
3186 unsigned count = glsl_count_attribute_slots(
3187 instr->variables[0]->var->type,
3188 ctx->stage == MESA_SHADER_VERTEX);
3189 count -= chan / 4;
3190 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3191 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3192 stride, false, true);
3193
3194 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3195 tmp_vec,
3196 indir_index, "");
3197 } else
3198 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3199 }
3200 break;
3201 case nir_var_local:
3202 for (unsigned chan = 0; chan < ve; chan++) {
3203 if (indir_index) {
3204 unsigned count = glsl_count_attribute_slots(
3205 instr->variables[0]->var->type, false);
3206 count -= chan / 4;
3207 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3208 &ctx->ac, ctx->locals + idx + chan, count,
3209 stride, true, true);
3210
3211 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3212 tmp_vec,
3213 indir_index, "");
3214 } else {
3215 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3216 }
3217 }
3218 break;
3219 case nir_var_shared: {
3220 LLVMValueRef address = build_gep_for_deref(ctx,
3221 instr->variables[0]);
3222 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3223 return LLVMBuildBitCast(ctx->ac.builder, val,
3224 get_def_type(ctx, &instr->dest.ssa),
3225 "");
3226 }
3227 case nir_var_shader_out:
3228 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3229 return load_tess_varyings(ctx, instr, false);
3230 }
3231
3232 for (unsigned chan = comp; chan < ve + comp; chan++) {
3233 if (indir_index) {
3234 unsigned count = glsl_count_attribute_slots(
3235 instr->variables[0]->var->type, false);
3236 count -= chan / 4;
3237 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3238 &ctx->ac, ctx->outputs + idx + chan, count,
3239 stride, true, true);
3240
3241 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3242 tmp_vec,
3243 indir_index, "");
3244 } else {
3245 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3246 ctx->outputs[idx + chan + const_index * stride],
3247 "");
3248 }
3249 }
3250 break;
3251 default:
3252 unreachable("unhandle variable mode");
3253 }
3254 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3255 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3256 }
3257
3258 static void
3259 visit_store_var(struct ac_nir_context *ctx,
3260 nir_intrinsic_instr *instr)
3261 {
3262 LLVMValueRef temp_ptr, value;
3263 int idx = instr->variables[0]->var->data.driver_location;
3264 unsigned comp = instr->variables[0]->var->data.location_frac;
3265 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3266 int writemask = instr->const_index[0] << comp;
3267 LLVMValueRef indir_index;
3268 unsigned const_index;
3269 get_deref_offset(ctx, instr->variables[0], false,
3270 NULL, NULL, &const_index, &indir_index);
3271
3272 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3273
3274 src = LLVMBuildBitCast(ctx->ac.builder, src,
3275 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3276 "");
3277
3278 writemask = widen_mask(writemask, 2);
3279 }
3280
3281 switch (instr->variables[0]->var->data.mode) {
3282 case nir_var_shader_out:
3283
3284 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3285 LLVMValueRef vertex_index = NULL;
3286 LLVMValueRef indir_index = NULL;
3287 unsigned const_index = 0;
3288 const unsigned location = instr->variables[0]->var->data.location;
3289 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3290 const unsigned comp = instr->variables[0]->var->data.location_frac;
3291 const bool is_patch = instr->variables[0]->var->data.patch;
3292 const bool is_compact = instr->variables[0]->var->data.compact;
3293
3294 get_deref_offset(ctx, instr->variables[0],
3295 false, NULL, is_patch ? NULL : &vertex_index,
3296 &const_index, &indir_index);
3297
3298 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3299 const_index, location, driver_location,
3300 src, comp, is_patch, is_compact, writemask);
3301 return;
3302 }
3303
3304 for (unsigned chan = 0; chan < 8; chan++) {
3305 int stride = 4;
3306 if (!(writemask & (1 << chan)))
3307 continue;
3308
3309 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3310
3311 if (instr->variables[0]->var->data.compact)
3312 stride = 1;
3313 if (indir_index) {
3314 unsigned count = glsl_count_attribute_slots(
3315 instr->variables[0]->var->type, false);
3316 count -= chan / 4;
3317 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3318 &ctx->ac, ctx->outputs + idx + chan, count,
3319 stride, true, true);
3320
3321 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3322 value, indir_index, "");
3323 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3324 count, stride, tmp_vec);
3325
3326 } else {
3327 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3328
3329 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3330 }
3331 }
3332 break;
3333 case nir_var_local:
3334 for (unsigned chan = 0; chan < 8; chan++) {
3335 if (!(writemask & (1 << chan)))
3336 continue;
3337
3338 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3339 if (indir_index) {
3340 unsigned count = glsl_count_attribute_slots(
3341 instr->variables[0]->var->type, false);
3342 count -= chan / 4;
3343 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3344 &ctx->ac, ctx->locals + idx + chan, count,
3345 4, true, true);
3346
3347 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3348 value, indir_index, "");
3349 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3350 count, 4, tmp_vec);
3351 } else {
3352 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3353
3354 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3355 }
3356 }
3357 break;
3358 case nir_var_shared: {
3359 int writemask = instr->const_index[0];
3360 LLVMValueRef address = build_gep_for_deref(ctx,
3361 instr->variables[0]);
3362 LLVMValueRef val = get_src(ctx, instr->src[0]);
3363 unsigned components =
3364 glsl_get_vector_elements(
3365 nir_deref_tail(&instr->variables[0]->deref)->type);
3366 if (writemask == (1 << components) - 1) {
3367 val = LLVMBuildBitCast(
3368 ctx->ac.builder, val,
3369 LLVMGetElementType(LLVMTypeOf(address)), "");
3370 LLVMBuildStore(ctx->ac.builder, val, address);
3371 } else {
3372 for (unsigned chan = 0; chan < 4; chan++) {
3373 if (!(writemask & (1 << chan)))
3374 continue;
3375 LLVMValueRef ptr =
3376 LLVMBuildStructGEP(ctx->ac.builder,
3377 address, chan, "");
3378 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3379 chan);
3380 src = LLVMBuildBitCast(
3381 ctx->ac.builder, src,
3382 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3383 LLVMBuildStore(ctx->ac.builder, src, ptr);
3384 }
3385 }
3386 break;
3387 }
3388 default:
3389 break;
3390 }
3391 }
3392
3393 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3394 {
3395 switch (dim) {
3396 case GLSL_SAMPLER_DIM_BUF:
3397 return 1;
3398 case GLSL_SAMPLER_DIM_1D:
3399 return array ? 2 : 1;
3400 case GLSL_SAMPLER_DIM_2D:
3401 return array ? 3 : 2;
3402 case GLSL_SAMPLER_DIM_MS:
3403 return array ? 4 : 3;
3404 case GLSL_SAMPLER_DIM_3D:
3405 case GLSL_SAMPLER_DIM_CUBE:
3406 return 3;
3407 case GLSL_SAMPLER_DIM_RECT:
3408 case GLSL_SAMPLER_DIM_SUBPASS:
3409 return 2;
3410 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3411 return 3;
3412 default:
3413 break;
3414 }
3415 return 0;
3416 }
3417
3418
3419
3420 /* Adjust the sample index according to FMASK.
3421 *
3422 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3423 * which is the identity mapping. Each nibble says which physical sample
3424 * should be fetched to get that sample.
3425 *
3426 * For example, 0x11111100 means there are only 2 samples stored and
3427 * the second sample covers 3/4 of the pixel. When reading samples 0
3428 * and 1, return physical sample 0 (determined by the first two 0s
3429 * in FMASK), otherwise return physical sample 1.
3430 *
3431 * The sample index should be adjusted as follows:
3432 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3433 */
3434 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3435 LLVMValueRef coord_x, LLVMValueRef coord_y,
3436 LLVMValueRef coord_z,
3437 LLVMValueRef sample_index,
3438 LLVMValueRef fmask_desc_ptr)
3439 {
3440 LLVMValueRef fmask_load_address[4];
3441 LLVMValueRef res;
3442
3443 fmask_load_address[0] = coord_x;
3444 fmask_load_address[1] = coord_y;
3445 if (coord_z) {
3446 fmask_load_address[2] = coord_z;
3447 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3448 }
3449
3450 struct ac_image_args args = {0};
3451
3452 args.opcode = ac_image_load;
3453 args.da = coord_z ? true : false;
3454 args.resource = fmask_desc_ptr;
3455 args.dmask = 0xf;
3456 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3457
3458 res = ac_build_image_opcode(ctx, &args);
3459
3460 res = ac_to_integer(ctx, res);
3461 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3462 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3463
3464 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3465 res,
3466 ctx->i32_0, "");
3467
3468 LLVMValueRef sample_index4 =
3469 LLVMBuildMul(ctx->builder, sample_index, four, "");
3470 LLVMValueRef shifted_fmask =
3471 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3472 LLVMValueRef final_sample =
3473 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3474
3475 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3476 * resource descriptor is 0 (invalid),
3477 */
3478 LLVMValueRef fmask_desc =
3479 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3480 ctx->v8i32, "");
3481
3482 LLVMValueRef fmask_word1 =
3483 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3484 ctx->i32_1, "");
3485
3486 LLVMValueRef word1_is_nonzero =
3487 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3488 fmask_word1, ctx->i32_0, "");
3489
3490 /* Replace the MSAA sample index. */
3491 sample_index =
3492 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3493 final_sample, sample_index, "");
3494 return sample_index;
3495 }
3496
3497 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3498 const nir_intrinsic_instr *instr)
3499 {
3500 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3501
3502 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3503 LLVMValueRef coords[4];
3504 LLVMValueRef masks[] = {
3505 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3506 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3507 };
3508 LLVMValueRef res;
3509 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3510
3511 int count;
3512 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3513 bool is_array = glsl_sampler_type_is_array(type);
3514 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3515 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3516 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3517 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3518 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3519 count = image_type_to_components_count(dim, is_array);
3520
3521 if (is_ms) {
3522 LLVMValueRef fmask_load_address[3];
3523 int chan;
3524
3525 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3526 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3527 if (is_array)
3528 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3529 else
3530 fmask_load_address[2] = NULL;
3531 if (add_frag_pos) {
3532 for (chan = 0; chan < 2; ++chan)
3533 fmask_load_address[chan] =
3534 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3535 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3536 ctx->ac.i32, ""), "");
3537 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3538 }
3539 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3540 fmask_load_address[0],
3541 fmask_load_address[1],
3542 fmask_load_address[2],
3543 sample_index,
3544 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3545 }
3546 if (count == 1 && !gfx9_1d) {
3547 if (instr->src[0].ssa->num_components)
3548 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3549 else
3550 res = src0;
3551 } else {
3552 int chan;
3553 if (is_ms)
3554 count--;
3555 for (chan = 0; chan < count; ++chan) {
3556 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3557 }
3558 if (add_frag_pos) {
3559 for (chan = 0; chan < 2; ++chan)
3560 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3561 ctx->ac.i32, ""), "");
3562 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3563 count++;
3564 }
3565
3566 if (gfx9_1d) {
3567 if (is_array) {
3568 coords[2] = coords[1];
3569 coords[1] = ctx->ac.i32_0;
3570 } else
3571 coords[1] = ctx->ac.i32_0;
3572 count++;
3573 }
3574
3575 if (is_ms) {
3576 coords[count] = sample_index;
3577 count++;
3578 }
3579
3580 if (count == 3) {
3581 coords[3] = LLVMGetUndef(ctx->ac.i32);
3582 count = 4;
3583 }
3584 res = ac_build_gather_values(&ctx->ac, coords, count);
3585 }
3586 return res;
3587 }
3588
3589 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3590 const nir_intrinsic_instr *instr)
3591 {
3592 LLVMValueRef params[7];
3593 LLVMValueRef res;
3594 char intrinsic_name[64];
3595 const nir_variable *var = instr->variables[0]->var;
3596 const struct glsl_type *type = var->type;
3597
3598 if(instr->variables[0]->deref.child)
3599 type = instr->variables[0]->deref.child->type;
3600
3601 type = glsl_without_array(type);
3602
3603 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3604 if (dim == GLSL_SAMPLER_DIM_BUF) {
3605 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3606 unsigned num_channels = util_last_bit(mask);
3607 LLVMValueRef rsrc, vindex;
3608
3609 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3610 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3611 ctx->ac.i32_0, "");
3612
3613 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3614 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3615 ctx->ac.i32_0, num_channels,
3616 false, false);
3617 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3618
3619 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3620 res = ac_to_integer(&ctx->ac, res);
3621 } else {
3622 bool is_da = glsl_sampler_type_is_array(type) ||
3623 dim == GLSL_SAMPLER_DIM_CUBE ||
3624 dim == GLSL_SAMPLER_DIM_3D ||
3625 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3627 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3628 LLVMValueRef glc = ctx->ac.i1false;
3629 LLVMValueRef slc = ctx->ac.i1false;
3630
3631 params[0] = get_image_coords(ctx, instr);
3632 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3633 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3634 params[3] = glc;
3635 params[4] = slc;
3636 params[5] = ctx->ac.i1false;
3637 params[6] = da;
3638
3639 ac_get_image_intr_name("llvm.amdgcn.image.load",
3640 ctx->ac.v4f32, /* vdata */
3641 LLVMTypeOf(params[0]), /* coords */
3642 LLVMTypeOf(params[1]), /* rsrc */
3643 intrinsic_name, sizeof(intrinsic_name));
3644
3645 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3646 params, 7, AC_FUNC_ATTR_READONLY);
3647 }
3648 return ac_to_integer(&ctx->ac, res);
3649 }
3650
3651 static void visit_image_store(struct ac_nir_context *ctx,
3652 nir_intrinsic_instr *instr)
3653 {
3654 LLVMValueRef params[8];
3655 char intrinsic_name[64];
3656 const nir_variable *var = instr->variables[0]->var;
3657 const struct glsl_type *type = glsl_without_array(var->type);
3658 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3659 LLVMValueRef glc = ctx->ac.i1false;
3660 bool force_glc = ctx->ac.chip_class == SI;
3661 if (force_glc)
3662 glc = ctx->ac.i1true;
3663
3664 if (dim == GLSL_SAMPLER_DIM_BUF) {
3665 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3666 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3667 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3668 ctx->ac.i32_0, ""); /* vindex */
3669 params[3] = ctx->ac.i32_0; /* voffset */
3670 params[4] = glc; /* glc */
3671 params[5] = ctx->ac.i1false; /* slc */
3672 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3673 params, 6, 0);
3674 } else {
3675 bool is_da = glsl_sampler_type_is_array(type) ||
3676 dim == GLSL_SAMPLER_DIM_CUBE ||
3677 dim == GLSL_SAMPLER_DIM_3D;
3678 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3679 LLVMValueRef slc = ctx->ac.i1false;
3680
3681 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3682 params[1] = get_image_coords(ctx, instr); /* coords */
3683 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3684 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3685 params[4] = glc;
3686 params[5] = slc;
3687 params[6] = ctx->ac.i1false;
3688 params[7] = da;
3689
3690 ac_get_image_intr_name("llvm.amdgcn.image.store",
3691 LLVMTypeOf(params[0]), /* vdata */
3692 LLVMTypeOf(params[1]), /* coords */
3693 LLVMTypeOf(params[2]), /* rsrc */
3694 intrinsic_name, sizeof(intrinsic_name));
3695
3696 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3697 params, 8, 0);
3698 }
3699
3700 }
3701
3702 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3703 const nir_intrinsic_instr *instr)
3704 {
3705 LLVMValueRef params[7];
3706 int param_count = 0;
3707 const nir_variable *var = instr->variables[0]->var;
3708
3709 const char *atomic_name;
3710 char intrinsic_name[41];
3711 const struct glsl_type *type = glsl_without_array(var->type);
3712 MAYBE_UNUSED int length;
3713
3714 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3715
3716 switch (instr->intrinsic) {
3717 case nir_intrinsic_image_atomic_add:
3718 atomic_name = "add";
3719 break;
3720 case nir_intrinsic_image_atomic_min:
3721 atomic_name = is_unsigned ? "umin" : "smin";
3722 break;
3723 case nir_intrinsic_image_atomic_max:
3724 atomic_name = is_unsigned ? "umax" : "smax";
3725 break;
3726 case nir_intrinsic_image_atomic_and:
3727 atomic_name = "and";
3728 break;
3729 case nir_intrinsic_image_atomic_or:
3730 atomic_name = "or";
3731 break;
3732 case nir_intrinsic_image_atomic_xor:
3733 atomic_name = "xor";
3734 break;
3735 case nir_intrinsic_image_atomic_exchange:
3736 atomic_name = "swap";
3737 break;
3738 case nir_intrinsic_image_atomic_comp_swap:
3739 atomic_name = "cmpswap";
3740 break;
3741 default:
3742 abort();
3743 }
3744
3745 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3746 params[param_count++] = get_src(ctx, instr->src[3]);
3747 params[param_count++] = get_src(ctx, instr->src[2]);
3748
3749 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3750 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3751 NULL, true, true);
3752 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3753 ctx->ac.i32_0, ""); /* vindex */
3754 params[param_count++] = ctx->ac.i32_0; /* voffset */
3755 params[param_count++] = ctx->ac.i1false; /* slc */
3756
3757 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3758 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3759 } else {
3760 char coords_type[8];
3761
3762 bool da = glsl_sampler_type_is_array(type) ||
3763 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3764
3765 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3766 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3767 NULL, true, true);
3768 params[param_count++] = ctx->ac.i1false; /* r128 */
3769 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3770 params[param_count++] = ctx->ac.i1false; /* slc */
3771
3772 build_int_type_name(LLVMTypeOf(coords),
3773 coords_type, sizeof(coords_type));
3774
3775 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3776 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3777 }
3778
3779 assert(length < sizeof(intrinsic_name));
3780 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3781 }
3782
3783 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3784 const nir_intrinsic_instr *instr)
3785 {
3786 LLVMValueRef res;
3787 const nir_variable *var = instr->variables[0]->var;
3788 const struct glsl_type *type = instr->variables[0]->var->type;
3789 bool da = glsl_sampler_type_is_array(var->type) ||
3790 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3791 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3792 if(instr->variables[0]->deref.child)
3793 type = instr->variables[0]->deref.child->type;
3794
3795 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3796 return get_buffer_size(ctx,
3797 get_sampler_desc(ctx, instr->variables[0],
3798 AC_DESC_BUFFER, NULL, true, false), true);
3799
3800 struct ac_image_args args = { 0 };
3801
3802 args.da = da;
3803 args.dmask = 0xf;
3804 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3805 args.opcode = ac_image_get_resinfo;
3806 args.addr = ctx->ac.i32_0;
3807
3808 res = ac_build_image_opcode(&ctx->ac, &args);
3809
3810 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3811
3812 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3813 glsl_sampler_type_is_array(type)) {
3814 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3815 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3816 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3817 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3818 }
3819 if (ctx->ac.chip_class >= GFX9 &&
3820 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3821 glsl_sampler_type_is_array(type)) {
3822 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3823 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3824 ctx->ac.i32_1, "");
3825
3826 }
3827 return res;
3828 }
3829
3830 #define NOOP_WAITCNT 0xf7f
3831 #define LGKM_CNT 0x07f
3832 #define VM_CNT 0xf70
3833
3834 static void emit_membar(struct nir_to_llvm_context *ctx,
3835 const nir_intrinsic_instr *instr)
3836 {
3837 unsigned waitcnt = NOOP_WAITCNT;
3838
3839 switch (instr->intrinsic) {
3840 case nir_intrinsic_memory_barrier:
3841 case nir_intrinsic_group_memory_barrier:
3842 waitcnt &= VM_CNT & LGKM_CNT;
3843 break;
3844 case nir_intrinsic_memory_barrier_atomic_counter:
3845 case nir_intrinsic_memory_barrier_buffer:
3846 case nir_intrinsic_memory_barrier_image:
3847 waitcnt &= VM_CNT;
3848 break;
3849 case nir_intrinsic_memory_barrier_shared:
3850 waitcnt &= LGKM_CNT;
3851 break;
3852 default:
3853 break;
3854 }
3855 if (waitcnt != NOOP_WAITCNT)
3856 ac_build_waitcnt(&ctx->ac, waitcnt);
3857 }
3858
3859 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3860 {
3861 /* SI only (thanks to a hw bug workaround):
3862 * The real barrier instruction isn’t needed, because an entire patch
3863 * always fits into a single wave.
3864 */
3865 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3866 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3867 return;
3868 }
3869 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3870 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3871 }
3872
3873 static void emit_discard(struct ac_nir_context *ctx,
3874 const nir_intrinsic_instr *instr)
3875 {
3876 LLVMValueRef cond;
3877
3878 if (instr->intrinsic == nir_intrinsic_discard_if) {
3879 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3880 get_src(ctx, instr->src[0]),
3881 ctx->ac.i32_0, "");
3882 } else {
3883 assert(instr->intrinsic == nir_intrinsic_discard);
3884 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3885 }
3886
3887 ac_build_kill_if_false(&ctx->ac, cond);
3888 }
3889
3890 static LLVMValueRef
3891 visit_load_helper_invocation(struct ac_nir_context *ctx)
3892 {
3893 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3894 "llvm.amdgcn.ps.live",
3895 ctx->ac.i1, NULL, 0,
3896 AC_FUNC_ATTR_READNONE);
3897 result = LLVMBuildNot(ctx->ac.builder, result, "");
3898 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3899 }
3900
3901 static LLVMValueRef
3902 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3903 {
3904 LLVMValueRef result;
3905 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3906 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3907 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3908
3909 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3910 }
3911
3912 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3913 const nir_intrinsic_instr *instr)
3914 {
3915 LLVMValueRef ptr, result;
3916 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3917 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3918
3919 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3920 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3921 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3922 ptr, src, src1,
3923 LLVMAtomicOrderingSequentiallyConsistent,
3924 LLVMAtomicOrderingSequentiallyConsistent,
3925 false);
3926 } else {
3927 LLVMAtomicRMWBinOp op;
3928 switch (instr->intrinsic) {
3929 case nir_intrinsic_var_atomic_add:
3930 op = LLVMAtomicRMWBinOpAdd;
3931 break;
3932 case nir_intrinsic_var_atomic_umin:
3933 op = LLVMAtomicRMWBinOpUMin;
3934 break;
3935 case nir_intrinsic_var_atomic_umax:
3936 op = LLVMAtomicRMWBinOpUMax;
3937 break;
3938 case nir_intrinsic_var_atomic_imin:
3939 op = LLVMAtomicRMWBinOpMin;
3940 break;
3941 case nir_intrinsic_var_atomic_imax:
3942 op = LLVMAtomicRMWBinOpMax;
3943 break;
3944 case nir_intrinsic_var_atomic_and:
3945 op = LLVMAtomicRMWBinOpAnd;
3946 break;
3947 case nir_intrinsic_var_atomic_or:
3948 op = LLVMAtomicRMWBinOpOr;
3949 break;
3950 case nir_intrinsic_var_atomic_xor:
3951 op = LLVMAtomicRMWBinOpXor;
3952 break;
3953 case nir_intrinsic_var_atomic_exchange:
3954 op = LLVMAtomicRMWBinOpXchg;
3955 break;
3956 default:
3957 return NULL;
3958 }
3959
3960 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3961 LLVMAtomicOrderingSequentiallyConsistent,
3962 false);
3963 }
3964 return result;
3965 }
3966
3967 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3968 enum glsl_interp_mode interp, unsigned location)
3969 {
3970 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3971
3972 switch (interp) {
3973 case INTERP_MODE_FLAT:
3974 default:
3975 return NULL;
3976 case INTERP_MODE_SMOOTH:
3977 case INTERP_MODE_NONE:
3978 if (location == INTERP_CENTER)
3979 return ctx->persp_center;
3980 else if (location == INTERP_CENTROID)
3981 return ctx->persp_centroid;
3982 else if (location == INTERP_SAMPLE)
3983 return ctx->persp_sample;
3984 break;
3985 case INTERP_MODE_NOPERSPECTIVE:
3986 if (location == INTERP_CENTER)
3987 return ctx->linear_center;
3988 else if (location == INTERP_CENTROID)
3989 return ctx->linear_centroid;
3990 else if (location == INTERP_SAMPLE)
3991 return ctx->linear_sample;
3992 break;
3993 }
3994 return NULL;
3995 }
3996
3997 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
3998 LLVMValueRef sample_id)
3999 {
4000 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4001
4002 LLVMValueRef result;
4003 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4004
4005 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4006 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4007
4008 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4009 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4010
4011 return result;
4012 }
4013
4014 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4015 {
4016 LLVMValueRef values[2];
4017
4018 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4019 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4020 return ac_build_gather_values(&ctx->ac, values, 2);
4021 }
4022
4023 static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
4024 {
4025 uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? ctx->nctx->options->key.fs.log2_num_samples : ctx->nctx->options->key.fs.log2_ps_iter_samples;
4026
4027 /* The bit pattern matches that used by fixed function fragment
4028 * processing. */
4029 static const uint16_t ps_iter_masks[] = {
4030 0xffff, /* not used */
4031 0x5555,
4032 0x1111,
4033 0x0101,
4034 0x0001,
4035 };
4036 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4037
4038 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4039
4040 LLVMValueRef result, sample_id;
4041 sample_id = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4042 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4043 result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, "");
4044 return result;
4045 }
4046
4047 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4048 const nir_intrinsic_instr *instr)
4049 {
4050 LLVMValueRef result[4];
4051 LLVMValueRef interp_param, attr_number;
4052 unsigned location;
4053 unsigned chan;
4054 LLVMValueRef src_c0 = NULL;
4055 LLVMValueRef src_c1 = NULL;
4056 LLVMValueRef src0 = NULL;
4057 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4058 switch (instr->intrinsic) {
4059 case nir_intrinsic_interp_var_at_centroid:
4060 location = INTERP_CENTROID;
4061 break;
4062 case nir_intrinsic_interp_var_at_sample:
4063 case nir_intrinsic_interp_var_at_offset:
4064 location = INTERP_CENTER;
4065 src0 = get_src(ctx, instr->src[0]);
4066 break;
4067 default:
4068 break;
4069 }
4070
4071 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4072 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4073 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4074 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4075 LLVMValueRef sample_position;
4076 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4077
4078 /* fetch sample ID */
4079 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4080
4081 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4082 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4083 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4084 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4085 }
4086 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4087 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4088
4089 if (location == INTERP_CENTER) {
4090 LLVMValueRef ij_out[2];
4091 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4092
4093 /*
4094 * take the I then J parameters, and the DDX/Y for it, and
4095 * calculate the IJ inputs for the interpolator.
4096 * temp1 = ddx * offset/sample.x + I;
4097 * interp_param.I = ddy * offset/sample.y + temp1;
4098 * temp1 = ddx * offset/sample.x + J;
4099 * interp_param.J = ddy * offset/sample.y + temp1;
4100 */
4101 for (unsigned i = 0; i < 2; i++) {
4102 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4103 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4104 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4105 ddxy_out, ix_ll, "");
4106 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4107 ddxy_out, iy_ll, "");
4108 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4109 interp_param, ix_ll, "");
4110 LLVMValueRef temp1, temp2;
4111
4112 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4113 ctx->ac.f32, "");
4114
4115 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4116 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4117
4118 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4119 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4120
4121 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4122 temp2, ctx->ac.i32, "");
4123 }
4124 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4125
4126 }
4127
4128 for (chan = 0; chan < 4; chan++) {
4129 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4130
4131 if (interp_param) {
4132 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4133 interp_param, ctx->ac.v2f32, "");
4134 LLVMValueRef i = LLVMBuildExtractElement(
4135 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4136 LLVMValueRef j = LLVMBuildExtractElement(
4137 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4138
4139 result[chan] = ac_build_fs_interp(&ctx->ac,
4140 llvm_chan, attr_number,
4141 ctx->abi->prim_mask, i, j);
4142 } else {
4143 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4144 LLVMConstInt(ctx->ac.i32, 2, false),
4145 llvm_chan, attr_number,
4146 ctx->abi->prim_mask);
4147 }
4148 }
4149 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4150 instr->variables[0]->var->data.location_frac);
4151 }
4152
4153 static void
4154 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4155 {
4156 LLVMValueRef gs_next_vertex;
4157 LLVMValueRef can_emit;
4158 int idx;
4159 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4160
4161 assert(stream == 0);
4162
4163 /* Write vertex attribute values to GSVS ring */
4164 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4165 ctx->gs_next_vertex,
4166 "");
4167
4168 /* If this thread has already emitted the declared maximum number of
4169 * vertices, kill it: excessive vertex emissions are not supposed to
4170 * have any effect, and GS threads have no externally observable
4171 * effects other than emitting vertices.
4172 */
4173 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4174 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4175 ac_build_kill_if_false(&ctx->ac, can_emit);
4176
4177 /* loop num outputs */
4178 idx = 0;
4179 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4180 LLVMValueRef *out_ptr = &addrs[i * 4];
4181 int length = 4;
4182 int slot = idx;
4183 int slot_inc = 1;
4184
4185 if (!(ctx->output_mask & (1ull << i)))
4186 continue;
4187
4188 if (i == VARYING_SLOT_CLIP_DIST0) {
4189 /* pack clip and cull into a single set of slots */
4190 length = ctx->num_output_clips + ctx->num_output_culls;
4191 if (length > 4)
4192 slot_inc = 2;
4193 }
4194 for (unsigned j = 0; j < length; j++) {
4195 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4196 out_ptr[j], "");
4197 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4198 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4199 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4200
4201 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4202
4203 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4204 out_val, 1,
4205 voffset, ctx->gs2vs_offset, 0,
4206 1, 1, true, true);
4207 }
4208 idx += slot_inc;
4209 }
4210
4211 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4212 ctx->ac.i32_1, "");
4213 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4214
4215 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4216 }
4217
4218 static void
4219 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4220 {
4221 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4222 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4223 }
4224
4225 static LLVMValueRef
4226 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4227 unsigned num_components)
4228 {
4229 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4230
4231 LLVMValueRef coord[4] = {
4232 ctx->tes_u,
4233 ctx->tes_v,
4234 ctx->ac.f32_0,
4235 ctx->ac.f32_0,
4236 };
4237
4238 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4239 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4240 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4241
4242 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4243 return LLVMBuildBitCast(ctx->builder, result, type, "");
4244 }
4245
4246 static LLVMValueRef
4247 load_patch_vertices_in(struct ac_shader_abi *abi)
4248 {
4249 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4250 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4251 }
4252
4253 static void visit_intrinsic(struct ac_nir_context *ctx,
4254 nir_intrinsic_instr *instr)
4255 {
4256 LLVMValueRef result = NULL;
4257
4258 switch (instr->intrinsic) {
4259 case nir_intrinsic_ballot:
4260 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4261 break;
4262 case nir_intrinsic_read_invocation:
4263 case nir_intrinsic_read_first_invocation: {
4264 LLVMValueRef args[2];
4265
4266 /* Value */
4267 args[0] = get_src(ctx, instr->src[0]);
4268
4269 unsigned num_args;
4270 const char *intr_name;
4271 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4272 num_args = 2;
4273 intr_name = "llvm.amdgcn.readlane";
4274
4275 /* Invocation */
4276 args[1] = get_src(ctx, instr->src[1]);
4277 } else {
4278 num_args = 1;
4279 intr_name = "llvm.amdgcn.readfirstlane";
4280 }
4281
4282 /* We currently have no other way to prevent LLVM from lifting the icmp
4283 * calls to a dominating basic block.
4284 */
4285 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4286
4287 result = ac_build_intrinsic(&ctx->ac, intr_name,
4288 ctx->ac.i32, args, num_args,
4289 AC_FUNC_ATTR_READNONE |
4290 AC_FUNC_ATTR_CONVERGENT);
4291 break;
4292 }
4293 case nir_intrinsic_load_subgroup_invocation:
4294 result = ac_get_thread_id(&ctx->ac);
4295 break;
4296 case nir_intrinsic_load_work_group_id: {
4297 LLVMValueRef values[3];
4298
4299 for (int i = 0; i < 3; i++) {
4300 values[i] = ctx->abi->workgroup_ids[i] ?
4301 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4302 }
4303
4304 result = ac_build_gather_values(&ctx->ac, values, 3);
4305 break;
4306 }
4307 case nir_intrinsic_load_base_vertex: {
4308 result = ctx->abi->base_vertex;
4309 break;
4310 }
4311 case nir_intrinsic_load_vertex_id_zero_base: {
4312 result = ctx->abi->vertex_id;
4313 break;
4314 }
4315 case nir_intrinsic_load_local_invocation_id: {
4316 result = ctx->abi->local_invocation_ids;
4317 break;
4318 }
4319 case nir_intrinsic_load_base_instance:
4320 result = ctx->abi->start_instance;
4321 break;
4322 case nir_intrinsic_load_draw_id:
4323 result = ctx->abi->draw_id;
4324 break;
4325 case nir_intrinsic_load_view_index:
4326 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4327 break;
4328 case nir_intrinsic_load_invocation_id:
4329 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4330 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4331 else
4332 result = ctx->abi->gs_invocation_id;
4333 break;
4334 case nir_intrinsic_load_primitive_id:
4335 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4336 result = ctx->abi->gs_prim_id;
4337 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4338 result = ctx->abi->tcs_patch_id;
4339 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4340 result = ctx->abi->tes_patch_id;
4341 } else
4342 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4343 break;
4344 case nir_intrinsic_load_sample_id:
4345 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4346 break;
4347 case nir_intrinsic_load_sample_pos:
4348 result = load_sample_pos(ctx);
4349 break;
4350 case nir_intrinsic_load_sample_mask_in:
4351 if (ctx->nctx)
4352 result = load_sample_mask_in(ctx);
4353 else
4354 result = ctx->abi->sample_coverage;
4355 break;
4356 case nir_intrinsic_load_frag_coord: {
4357 LLVMValueRef values[4] = {
4358 ctx->abi->frag_pos[0],
4359 ctx->abi->frag_pos[1],
4360 ctx->abi->frag_pos[2],
4361 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4362 };
4363 result = ac_build_gather_values(&ctx->ac, values, 4);
4364 break;
4365 }
4366 case nir_intrinsic_load_front_face:
4367 result = ctx->abi->front_face;
4368 break;
4369 case nir_intrinsic_load_helper_invocation:
4370 result = visit_load_helper_invocation(ctx);
4371 break;
4372 case nir_intrinsic_load_instance_id:
4373 result = ctx->abi->instance_id;
4374 break;
4375 case nir_intrinsic_load_num_work_groups:
4376 result = ctx->nctx->num_work_groups;
4377 break;
4378 case nir_intrinsic_load_local_invocation_index:
4379 result = visit_load_local_invocation_index(ctx->nctx);
4380 break;
4381 case nir_intrinsic_load_push_constant:
4382 result = visit_load_push_constant(ctx->nctx, instr);
4383 break;
4384 case nir_intrinsic_vulkan_resource_index:
4385 result = visit_vulkan_resource_index(ctx->nctx, instr);
4386 break;
4387 case nir_intrinsic_vulkan_resource_reindex:
4388 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4389 break;
4390 case nir_intrinsic_store_ssbo:
4391 visit_store_ssbo(ctx, instr);
4392 break;
4393 case nir_intrinsic_load_ssbo:
4394 result = visit_load_buffer(ctx, instr);
4395 break;
4396 case nir_intrinsic_ssbo_atomic_add:
4397 case nir_intrinsic_ssbo_atomic_imin:
4398 case nir_intrinsic_ssbo_atomic_umin:
4399 case nir_intrinsic_ssbo_atomic_imax:
4400 case nir_intrinsic_ssbo_atomic_umax:
4401 case nir_intrinsic_ssbo_atomic_and:
4402 case nir_intrinsic_ssbo_atomic_or:
4403 case nir_intrinsic_ssbo_atomic_xor:
4404 case nir_intrinsic_ssbo_atomic_exchange:
4405 case nir_intrinsic_ssbo_atomic_comp_swap:
4406 result = visit_atomic_ssbo(ctx, instr);
4407 break;
4408 case nir_intrinsic_load_ubo:
4409 result = visit_load_ubo_buffer(ctx, instr);
4410 break;
4411 case nir_intrinsic_get_buffer_size:
4412 result = visit_get_buffer_size(ctx, instr);
4413 break;
4414 case nir_intrinsic_load_var:
4415 result = visit_load_var(ctx, instr);
4416 break;
4417 case nir_intrinsic_store_var:
4418 visit_store_var(ctx, instr);
4419 break;
4420 case nir_intrinsic_image_load:
4421 result = visit_image_load(ctx, instr);
4422 break;
4423 case nir_intrinsic_image_store:
4424 visit_image_store(ctx, instr);
4425 break;
4426 case nir_intrinsic_image_atomic_add:
4427 case nir_intrinsic_image_atomic_min:
4428 case nir_intrinsic_image_atomic_max:
4429 case nir_intrinsic_image_atomic_and:
4430 case nir_intrinsic_image_atomic_or:
4431 case nir_intrinsic_image_atomic_xor:
4432 case nir_intrinsic_image_atomic_exchange:
4433 case nir_intrinsic_image_atomic_comp_swap:
4434 result = visit_image_atomic(ctx, instr);
4435 break;
4436 case nir_intrinsic_image_size:
4437 result = visit_image_size(ctx, instr);
4438 break;
4439 case nir_intrinsic_discard:
4440 case nir_intrinsic_discard_if:
4441 emit_discard(ctx, instr);
4442 break;
4443 case nir_intrinsic_memory_barrier:
4444 case nir_intrinsic_group_memory_barrier:
4445 case nir_intrinsic_memory_barrier_atomic_counter:
4446 case nir_intrinsic_memory_barrier_buffer:
4447 case nir_intrinsic_memory_barrier_image:
4448 case nir_intrinsic_memory_barrier_shared:
4449 emit_membar(ctx->nctx, instr);
4450 break;
4451 case nir_intrinsic_barrier:
4452 emit_barrier(&ctx->ac, ctx->stage);
4453 break;
4454 case nir_intrinsic_var_atomic_add:
4455 case nir_intrinsic_var_atomic_imin:
4456 case nir_intrinsic_var_atomic_umin:
4457 case nir_intrinsic_var_atomic_imax:
4458 case nir_intrinsic_var_atomic_umax:
4459 case nir_intrinsic_var_atomic_and:
4460 case nir_intrinsic_var_atomic_or:
4461 case nir_intrinsic_var_atomic_xor:
4462 case nir_intrinsic_var_atomic_exchange:
4463 case nir_intrinsic_var_atomic_comp_swap:
4464 result = visit_var_atomic(ctx->nctx, instr);
4465 break;
4466 case nir_intrinsic_interp_var_at_centroid:
4467 case nir_intrinsic_interp_var_at_sample:
4468 case nir_intrinsic_interp_var_at_offset:
4469 result = visit_interp(ctx, instr);
4470 break;
4471 case nir_intrinsic_emit_vertex:
4472 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4473 break;
4474 case nir_intrinsic_end_primitive:
4475 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4476 break;
4477 case nir_intrinsic_load_tess_coord: {
4478 LLVMTypeRef type = ctx->nctx ?
4479 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4480 NULL;
4481 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4482 break;
4483 }
4484 case nir_intrinsic_load_tess_level_outer:
4485 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4486 break;
4487 case nir_intrinsic_load_tess_level_inner:
4488 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4489 break;
4490 case nir_intrinsic_load_patch_vertices_in:
4491 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4492 break;
4493 case nir_intrinsic_vote_all: {
4494 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4495 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4496 break;
4497 }
4498 case nir_intrinsic_vote_any: {
4499 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4500 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4501 break;
4502 }
4503 case nir_intrinsic_vote_eq: {
4504 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4505 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4506 break;
4507 }
4508 default:
4509 fprintf(stderr, "Unknown intrinsic: ");
4510 nir_print_instr(&instr->instr, stderr);
4511 fprintf(stderr, "\n");
4512 break;
4513 }
4514 if (result) {
4515 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4516 }
4517 }
4518
4519 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4520 LLVMValueRef buffer_ptr, bool write)
4521 {
4522 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4523 LLVMValueRef result;
4524
4525 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4526
4527 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4528 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4529
4530 return result;
4531 }
4532
4533 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4534 {
4535 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4536 LLVMValueRef result;
4537
4538 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4539
4540 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4541 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4542
4543 return result;
4544 }
4545
4546 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4547 unsigned descriptor_set,
4548 unsigned base_index,
4549 unsigned constant_index,
4550 LLVMValueRef index,
4551 enum ac_descriptor_type desc_type,
4552 bool image, bool write)
4553 {
4554 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4555 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4556 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4557 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4558 unsigned offset = binding->offset;
4559 unsigned stride = binding->size;
4560 unsigned type_size;
4561 LLVMBuilderRef builder = ctx->builder;
4562 LLVMTypeRef type;
4563
4564 assert(base_index < layout->binding_count);
4565
4566 switch (desc_type) {
4567 case AC_DESC_IMAGE:
4568 type = ctx->ac.v8i32;
4569 type_size = 32;
4570 break;
4571 case AC_DESC_FMASK:
4572 type = ctx->ac.v8i32;
4573 offset += 32;
4574 type_size = 32;
4575 break;
4576 case AC_DESC_SAMPLER:
4577 type = ctx->ac.v4i32;
4578 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4579 offset += 64;
4580
4581 type_size = 16;
4582 break;
4583 case AC_DESC_BUFFER:
4584 type = ctx->ac.v4i32;
4585 type_size = 16;
4586 break;
4587 default:
4588 unreachable("invalid desc_type\n");
4589 }
4590
4591 offset += constant_index * stride;
4592
4593 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4594 (!index || binding->immutable_samplers_equal)) {
4595 if (binding->immutable_samplers_equal)
4596 constant_index = 0;
4597
4598 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4599
4600 LLVMValueRef constants[] = {
4601 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4602 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4603 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4604 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4605 };
4606 return ac_build_gather_values(&ctx->ac, constants, 4);
4607 }
4608
4609 assert(stride % type_size == 0);
4610
4611 if (!index)
4612 index = ctx->ac.i32_0;
4613
4614 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4615
4616 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4617 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4618
4619 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4620 }
4621
4622 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4623 const nir_deref_var *deref,
4624 enum ac_descriptor_type desc_type,
4625 const nir_tex_instr *tex_instr,
4626 bool image, bool write)
4627 {
4628 LLVMValueRef index = NULL;
4629 unsigned constant_index = 0;
4630 unsigned descriptor_set;
4631 unsigned base_index;
4632
4633 if (!deref) {
4634 assert(tex_instr && !image);
4635 descriptor_set = 0;
4636 base_index = tex_instr->sampler_index;
4637 } else {
4638 const nir_deref *tail = &deref->deref;
4639 while (tail->child) {
4640 const nir_deref_array *child = nir_deref_as_array(tail->child);
4641 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4642
4643 if (!array_size)
4644 array_size = 1;
4645
4646 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4647
4648 if (child->deref_array_type == nir_deref_array_type_indirect) {
4649 LLVMValueRef indirect = get_src(ctx, child->indirect);
4650
4651 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4652 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4653
4654 if (!index)
4655 index = indirect;
4656 else
4657 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4658 }
4659
4660 constant_index += child->base_offset * array_size;
4661
4662 tail = &child->deref;
4663 }
4664 descriptor_set = deref->var->data.descriptor_set;
4665 base_index = deref->var->data.binding;
4666 }
4667
4668 return ctx->abi->load_sampler_desc(ctx->abi,
4669 descriptor_set,
4670 base_index,
4671 constant_index, index,
4672 desc_type, image, write);
4673 }
4674
4675 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4676 struct ac_image_args *args,
4677 const nir_tex_instr *instr,
4678 nir_texop op,
4679 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4680 LLVMValueRef *param, unsigned count,
4681 unsigned dmask)
4682 {
4683 unsigned is_rect = 0;
4684 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4685
4686 if (op == nir_texop_lod)
4687 da = false;
4688 /* Pad to power of two vector */
4689 while (count < util_next_power_of_two(count))
4690 param[count++] = LLVMGetUndef(ctx->i32);
4691
4692 if (count > 1)
4693 args->addr = ac_build_gather_values(ctx, param, count);
4694 else
4695 args->addr = param[0];
4696
4697 args->resource = res_ptr;
4698 args->sampler = samp_ptr;
4699
4700 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4701 args->addr = param[0];
4702 return;
4703 }
4704
4705 args->dmask = dmask;
4706 args->unorm = is_rect;
4707 args->da = da;
4708 }
4709
4710 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4711 *
4712 * SI-CI:
4713 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4714 * filtering manually. The driver sets img7 to a mask clearing
4715 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4716 * s_and_b32 samp0, samp0, img7
4717 *
4718 * VI:
4719 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4720 */
4721 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4722 LLVMValueRef res, LLVMValueRef samp)
4723 {
4724 LLVMBuilderRef builder = ctx->ac.builder;
4725 LLVMValueRef img7, samp0;
4726
4727 if (ctx->ac.chip_class >= VI)
4728 return samp;
4729
4730 img7 = LLVMBuildExtractElement(builder, res,
4731 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4732 samp0 = LLVMBuildExtractElement(builder, samp,
4733 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4734 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4735 return LLVMBuildInsertElement(builder, samp, samp0,
4736 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4737 }
4738
4739 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4740 nir_tex_instr *instr,
4741 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4742 LLVMValueRef *fmask_ptr)
4743 {
4744 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4745 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4746 else
4747 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4748 if (samp_ptr) {
4749 if (instr->sampler)
4750 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4751 else
4752 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4753 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4754 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4755 }
4756 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4757 instr->op == nir_texop_samples_identical))
4758 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4759 }
4760
4761 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4762 LLVMValueRef coord)
4763 {
4764 coord = ac_to_float(ctx, coord);
4765 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4766 coord = ac_to_integer(ctx, coord);
4767 return coord;
4768 }
4769
4770 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4771 {
4772 LLVMValueRef result = NULL;
4773 struct ac_image_args args = { 0 };
4774 unsigned dmask = 0xf;
4775 LLVMValueRef address[16];
4776 LLVMValueRef coords[5];
4777 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4778 LLVMValueRef bias = NULL, offsets = NULL;
4779 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4780 LLVMValueRef ddx = NULL, ddy = NULL;
4781 LLVMValueRef derivs[6];
4782 unsigned chan, count = 0;
4783 unsigned const_src = 0, num_deriv_comp = 0;
4784 bool lod_is_zero = false;
4785
4786 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4787
4788 for (unsigned i = 0; i < instr->num_srcs; i++) {
4789 switch (instr->src[i].src_type) {
4790 case nir_tex_src_coord:
4791 coord = get_src(ctx, instr->src[i].src);
4792 break;
4793 case nir_tex_src_projector:
4794 break;
4795 case nir_tex_src_comparator:
4796 comparator = get_src(ctx, instr->src[i].src);
4797 break;
4798 case nir_tex_src_offset:
4799 offsets = get_src(ctx, instr->src[i].src);
4800 const_src = i;
4801 break;
4802 case nir_tex_src_bias:
4803 bias = get_src(ctx, instr->src[i].src);
4804 break;
4805 case nir_tex_src_lod: {
4806 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4807
4808 if (val && val->i32[0] == 0)
4809 lod_is_zero = true;
4810 lod = get_src(ctx, instr->src[i].src);
4811 break;
4812 }
4813 case nir_tex_src_ms_index:
4814 sample_index = get_src(ctx, instr->src[i].src);
4815 break;
4816 case nir_tex_src_ms_mcs:
4817 break;
4818 case nir_tex_src_ddx:
4819 ddx = get_src(ctx, instr->src[i].src);
4820 num_deriv_comp = instr->src[i].src.ssa->num_components;
4821 break;
4822 case nir_tex_src_ddy:
4823 ddy = get_src(ctx, instr->src[i].src);
4824 break;
4825 case nir_tex_src_texture_offset:
4826 case nir_tex_src_sampler_offset:
4827 case nir_tex_src_plane:
4828 default:
4829 break;
4830 }
4831 }
4832
4833 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4834 result = get_buffer_size(ctx, res_ptr, true);
4835 goto write_result;
4836 }
4837
4838 if (instr->op == nir_texop_texture_samples) {
4839 LLVMValueRef res, samples, is_msaa;
4840 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4841 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4842 LLVMConstInt(ctx->ac.i32, 3, false), "");
4843 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4844 LLVMConstInt(ctx->ac.i32, 28, false), "");
4845 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4846 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4847 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4848 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4849
4850 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4851 LLVMConstInt(ctx->ac.i32, 16, false), "");
4852 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4853 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4854 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4855 samples, "");
4856 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4857 ctx->ac.i32_1, "");
4858 result = samples;
4859 goto write_result;
4860 }
4861
4862 if (coord)
4863 for (chan = 0; chan < instr->coord_components; chan++)
4864 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4865
4866 if (offsets && instr->op != nir_texop_txf) {
4867 LLVMValueRef offset[3], pack;
4868 for (chan = 0; chan < 3; ++chan)
4869 offset[chan] = ctx->ac.i32_0;
4870
4871 args.offset = true;
4872 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4873 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4874 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4875 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4876 if (chan)
4877 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4878 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4879 }
4880 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4881 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4882 address[count++] = pack;
4883
4884 }
4885 /* pack LOD bias value */
4886 if (instr->op == nir_texop_txb && bias) {
4887 address[count++] = bias;
4888 }
4889
4890 /* Pack depth comparison value */
4891 if (instr->is_shadow && comparator) {
4892 LLVMValueRef z = ac_to_float(&ctx->ac,
4893 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4894
4895 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4896 * so the depth comparison value isn't clamped for Z16 and
4897 * Z24 anymore. Do it manually here.
4898 *
4899 * It's unnecessary if the original texture format was
4900 * Z32_FLOAT, but we don't know that here.
4901 */
4902 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4903 z = ac_build_clamp(&ctx->ac, z);
4904
4905 address[count++] = z;
4906 }
4907
4908 /* pack derivatives */
4909 if (ddx || ddy) {
4910 int num_src_deriv_channels, num_dest_deriv_channels;
4911 switch (instr->sampler_dim) {
4912 case GLSL_SAMPLER_DIM_3D:
4913 case GLSL_SAMPLER_DIM_CUBE:
4914 num_deriv_comp = 3;
4915 num_src_deriv_channels = 3;
4916 num_dest_deriv_channels = 3;
4917 break;
4918 case GLSL_SAMPLER_DIM_2D:
4919 default:
4920 num_src_deriv_channels = 2;
4921 num_dest_deriv_channels = 2;
4922 num_deriv_comp = 2;
4923 break;
4924 case GLSL_SAMPLER_DIM_1D:
4925 num_src_deriv_channels = 1;
4926 if (ctx->ac.chip_class >= GFX9) {
4927 num_dest_deriv_channels = 2;
4928 num_deriv_comp = 2;
4929 } else {
4930 num_dest_deriv_channels = 1;
4931 num_deriv_comp = 1;
4932 }
4933 break;
4934 }
4935
4936 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4937 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4938 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4939 }
4940 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4941 derivs[i] = ctx->ac.f32_0;
4942 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4943 }
4944 }
4945
4946 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4947 for (chan = 0; chan < instr->coord_components; chan++)
4948 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4949 if (instr->coord_components == 3)
4950 coords[3] = LLVMGetUndef(ctx->ac.f32);
4951 ac_prepare_cube_coords(&ctx->ac,
4952 instr->op == nir_texop_txd, instr->is_array,
4953 instr->op == nir_texop_lod, coords, derivs);
4954 if (num_deriv_comp)
4955 num_deriv_comp--;
4956 }
4957
4958 if (ddx || ddy) {
4959 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4960 address[count++] = derivs[i];
4961 }
4962
4963 /* Pack texture coordinates */
4964 if (coord) {
4965 address[count++] = coords[0];
4966 if (instr->coord_components > 1) {
4967 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4968 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4969 }
4970 address[count++] = coords[1];
4971 }
4972 if (instr->coord_components > 2) {
4973 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4974 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4975 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4976 instr->op != nir_texop_txf) {
4977 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4978 }
4979 address[count++] = coords[2];
4980 }
4981
4982 if (ctx->ac.chip_class >= GFX9) {
4983 LLVMValueRef filler;
4984 if (instr->op == nir_texop_txf)
4985 filler = ctx->ac.i32_0;
4986 else
4987 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4988
4989 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4990 /* No nir_texop_lod, because it does not take a slice
4991 * even with array textures. */
4992 if (instr->is_array && instr->op != nir_texop_lod ) {
4993 address[count] = address[count - 1];
4994 address[count - 1] = filler;
4995 count++;
4996 } else
4997 address[count++] = filler;
4998 }
4999 }
5000 }
5001
5002 /* Pack LOD */
5003 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5004 instr->op == nir_texop_txf)) {
5005 address[count++] = lod;
5006 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5007 address[count++] = sample_index;
5008 } else if(instr->op == nir_texop_txs) {
5009 count = 0;
5010 if (lod)
5011 address[count++] = lod;
5012 else
5013 address[count++] = ctx->ac.i32_0;
5014 }
5015
5016 for (chan = 0; chan < count; chan++) {
5017 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5018 address[chan], ctx->ac.i32, "");
5019 }
5020
5021 if (instr->op == nir_texop_samples_identical) {
5022 LLVMValueRef txf_address[4];
5023 struct ac_image_args txf_args = { 0 };
5024 unsigned txf_count = count;
5025 memcpy(txf_address, address, sizeof(txf_address));
5026
5027 if (!instr->is_array)
5028 txf_address[2] = ctx->ac.i32_0;
5029 txf_address[3] = ctx->ac.i32_0;
5030
5031 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5032 fmask_ptr, NULL,
5033 txf_address, txf_count, 0xf);
5034
5035 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5036
5037 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5038 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5039 goto write_result;
5040 }
5041
5042 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5043 instr->op != nir_texop_txs) {
5044 unsigned sample_chan = instr->is_array ? 3 : 2;
5045 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5046 address[0],
5047 address[1],
5048 instr->is_array ? address[2] : NULL,
5049 address[sample_chan],
5050 fmask_ptr);
5051 }
5052
5053 if (offsets && instr->op == nir_texop_txf) {
5054 nir_const_value *const_offset =
5055 nir_src_as_const_value(instr->src[const_src].src);
5056 int num_offsets = instr->src[const_src].src.ssa->num_components;
5057 assert(const_offset);
5058 num_offsets = MIN2(num_offsets, instr->coord_components);
5059 if (num_offsets > 2)
5060 address[2] = LLVMBuildAdd(ctx->ac.builder,
5061 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5062 if (num_offsets > 1)
5063 address[1] = LLVMBuildAdd(ctx->ac.builder,
5064 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5065 address[0] = LLVMBuildAdd(ctx->ac.builder,
5066 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5067
5068 }
5069
5070 /* TODO TG4 support */
5071 if (instr->op == nir_texop_tg4) {
5072 if (instr->is_shadow)
5073 dmask = 1;
5074 else
5075 dmask = 1 << instr->component;
5076 }
5077 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5078 res_ptr, samp_ptr, address, count, dmask);
5079
5080 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5081
5082 if (instr->op == nir_texop_query_levels)
5083 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5084 else if (instr->is_shadow && instr->is_new_style_shadow &&
5085 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5086 instr->op != nir_texop_tg4)
5087 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5088 else if (instr->op == nir_texop_txs &&
5089 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5090 instr->is_array) {
5091 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5092 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5093 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5094 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5095 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5096 } else if (ctx->ac.chip_class >= GFX9 &&
5097 instr->op == nir_texop_txs &&
5098 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5099 instr->is_array) {
5100 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5101 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5102 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5103 ctx->ac.i32_1, "");
5104 } else if (instr->dest.ssa.num_components != 4)
5105 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5106
5107 write_result:
5108 if (result) {
5109 assert(instr->dest.is_ssa);
5110 result = ac_to_integer(&ctx->ac, result);
5111 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5112 }
5113 }
5114
5115
5116 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5117 {
5118 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5119 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5120
5121 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5122 _mesa_hash_table_insert(ctx->phis, instr, result);
5123 }
5124
5125 static void visit_post_phi(struct ac_nir_context *ctx,
5126 nir_phi_instr *instr,
5127 LLVMValueRef llvm_phi)
5128 {
5129 nir_foreach_phi_src(src, instr) {
5130 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5131 LLVMValueRef llvm_src = get_src(ctx, src->src);
5132
5133 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5134 }
5135 }
5136
5137 static void phi_post_pass(struct ac_nir_context *ctx)
5138 {
5139 struct hash_entry *entry;
5140 hash_table_foreach(ctx->phis, entry) {
5141 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5142 (LLVMValueRef)entry->data);
5143 }
5144 }
5145
5146
5147 static void visit_ssa_undef(struct ac_nir_context *ctx,
5148 const nir_ssa_undef_instr *instr)
5149 {
5150 unsigned num_components = instr->def.num_components;
5151 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5152 LLVMValueRef undef;
5153
5154 if (num_components == 1)
5155 undef = LLVMGetUndef(type);
5156 else {
5157 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5158 }
5159 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5160 }
5161
5162 static void visit_jump(struct ac_nir_context *ctx,
5163 const nir_jump_instr *instr)
5164 {
5165 switch (instr->type) {
5166 case nir_jump_break:
5167 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5168 LLVMClearInsertionPosition(ctx->ac.builder);
5169 break;
5170 case nir_jump_continue:
5171 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5172 LLVMClearInsertionPosition(ctx->ac.builder);
5173 break;
5174 default:
5175 fprintf(stderr, "Unknown NIR jump instr: ");
5176 nir_print_instr(&instr->instr, stderr);
5177 fprintf(stderr, "\n");
5178 abort();
5179 }
5180 }
5181
5182 static void visit_cf_list(struct ac_nir_context *ctx,
5183 struct exec_list *list);
5184
5185 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5186 {
5187 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5188 nir_foreach_instr(instr, block)
5189 {
5190 switch (instr->type) {
5191 case nir_instr_type_alu:
5192 visit_alu(ctx, nir_instr_as_alu(instr));
5193 break;
5194 case nir_instr_type_load_const:
5195 visit_load_const(ctx, nir_instr_as_load_const(instr));
5196 break;
5197 case nir_instr_type_intrinsic:
5198 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5199 break;
5200 case nir_instr_type_tex:
5201 visit_tex(ctx, nir_instr_as_tex(instr));
5202 break;
5203 case nir_instr_type_phi:
5204 visit_phi(ctx, nir_instr_as_phi(instr));
5205 break;
5206 case nir_instr_type_ssa_undef:
5207 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5208 break;
5209 case nir_instr_type_jump:
5210 visit_jump(ctx, nir_instr_as_jump(instr));
5211 break;
5212 default:
5213 fprintf(stderr, "Unknown NIR instr type: ");
5214 nir_print_instr(instr, stderr);
5215 fprintf(stderr, "\n");
5216 abort();
5217 }
5218 }
5219
5220 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5221 }
5222
5223 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5224 {
5225 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5226
5227 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5228 LLVMBasicBlockRef merge_block =
5229 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5230 LLVMBasicBlockRef if_block =
5231 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5232 LLVMBasicBlockRef else_block = merge_block;
5233 if (!exec_list_is_empty(&if_stmt->else_list))
5234 else_block = LLVMAppendBasicBlockInContext(
5235 ctx->ac.context, fn, "");
5236
5237 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5238 ctx->ac.i32_0, "");
5239 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5240
5241 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5242 visit_cf_list(ctx, &if_stmt->then_list);
5243 if (LLVMGetInsertBlock(ctx->ac.builder))
5244 LLVMBuildBr(ctx->ac.builder, merge_block);
5245
5246 if (!exec_list_is_empty(&if_stmt->else_list)) {
5247 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5248 visit_cf_list(ctx, &if_stmt->else_list);
5249 if (LLVMGetInsertBlock(ctx->ac.builder))
5250 LLVMBuildBr(ctx->ac.builder, merge_block);
5251 }
5252
5253 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5254 }
5255
5256 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5257 {
5258 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5259 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5260 LLVMBasicBlockRef break_parent = ctx->break_block;
5261
5262 ctx->continue_block =
5263 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5264 ctx->break_block =
5265 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5266
5267 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5268 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5269 visit_cf_list(ctx, &loop->body);
5270
5271 if (LLVMGetInsertBlock(ctx->ac.builder))
5272 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5273 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5274
5275 ctx->continue_block = continue_parent;
5276 ctx->break_block = break_parent;
5277 }
5278
5279 static void visit_cf_list(struct ac_nir_context *ctx,
5280 struct exec_list *list)
5281 {
5282 foreach_list_typed(nir_cf_node, node, node, list)
5283 {
5284 switch (node->type) {
5285 case nir_cf_node_block:
5286 visit_block(ctx, nir_cf_node_as_block(node));
5287 break;
5288
5289 case nir_cf_node_if:
5290 visit_if(ctx, nir_cf_node_as_if(node));
5291 break;
5292
5293 case nir_cf_node_loop:
5294 visit_loop(ctx, nir_cf_node_as_loop(node));
5295 break;
5296
5297 default:
5298 assert(0);
5299 }
5300 }
5301 }
5302
5303 static void
5304 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5305 struct nir_variable *variable)
5306 {
5307 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5308 LLVMValueRef t_offset;
5309 LLVMValueRef t_list;
5310 LLVMValueRef input;
5311 LLVMValueRef buffer_index;
5312 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5313 int idx = variable->data.location;
5314 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5315
5316 variable->data.driver_location = idx * 4;
5317
5318 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5319 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5320 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5321 ctx->abi.start_instance, "");
5322 if (ctx->options->key.vs.as_ls) {
5323 ctx->shader_info->vs.vgpr_comp_cnt =
5324 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5325 } else {
5326 ctx->shader_info->vs.vgpr_comp_cnt =
5327 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5328 }
5329 } else
5330 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5331 ctx->abi.base_vertex, "");
5332 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5333
5334 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5335
5336 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5337 buffer_index,
5338 ctx->ac.i32_0,
5339 4, false, true);
5340
5341 for (unsigned chan = 0; chan < 4; chan++) {
5342 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5343 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5344 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5345 input, llvm_chan, ""));
5346 }
5347 }
5348 }
5349
5350 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5351 unsigned attr,
5352 LLVMValueRef interp_param,
5353 LLVMValueRef prim_mask,
5354 LLVMValueRef result[4])
5355 {
5356 LLVMValueRef attr_number;
5357 unsigned chan;
5358 LLVMValueRef i, j;
5359 bool interp = interp_param != NULL;
5360
5361 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5362
5363 /* fs.constant returns the param from the middle vertex, so it's not
5364 * really useful for flat shading. It's meant to be used for custom
5365 * interpolation (but the intrinsic can't fetch from the other two
5366 * vertices).
5367 *
5368 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5369 * to do the right thing. The only reason we use fs.constant is that
5370 * fs.interp cannot be used on integers, because they can be equal
5371 * to NaN.
5372 */
5373 if (interp) {
5374 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5375 ctx->ac.v2f32, "");
5376
5377 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5378 ctx->ac.i32_0, "");
5379 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5380 ctx->ac.i32_1, "");
5381 }
5382
5383 for (chan = 0; chan < 4; chan++) {
5384 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5385
5386 if (interp) {
5387 result[chan] = ac_build_fs_interp(&ctx->ac,
5388 llvm_chan,
5389 attr_number,
5390 prim_mask, i, j);
5391 } else {
5392 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5393 LLVMConstInt(ctx->ac.i32, 2, false),
5394 llvm_chan,
5395 attr_number,
5396 prim_mask);
5397 }
5398 }
5399 }
5400
5401 static void
5402 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5403 struct nir_variable *variable)
5404 {
5405 int idx = variable->data.location;
5406 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5407 LLVMValueRef interp;
5408
5409 variable->data.driver_location = idx * 4;
5410 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5411
5412 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5413 unsigned interp_type;
5414 if (variable->data.sample) {
5415 interp_type = INTERP_SAMPLE;
5416 ctx->shader_info->info.ps.force_persample = true;
5417 } else if (variable->data.centroid)
5418 interp_type = INTERP_CENTROID;
5419 else
5420 interp_type = INTERP_CENTER;
5421
5422 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5423 } else
5424 interp = NULL;
5425
5426 for (unsigned i = 0; i < attrib_count; ++i)
5427 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5428
5429 }
5430
5431 static void
5432 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5433 struct nir_shader *nir) {
5434 nir_foreach_variable(variable, &nir->inputs)
5435 handle_vs_input_decl(ctx, variable);
5436 }
5437
5438 static void
5439 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5440 struct nir_shader *nir)
5441 {
5442 if (!ctx->options->key.fs.multisample)
5443 return;
5444
5445 bool uses_center = false;
5446 bool uses_centroid = false;
5447 nir_foreach_variable(variable, &nir->inputs) {
5448 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5449 variable->data.sample)
5450 continue;
5451
5452 if (variable->data.centroid)
5453 uses_centroid = true;
5454 else
5455 uses_center = true;
5456 }
5457
5458 if (uses_center && uses_centroid) {
5459 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5460 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5461 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5462 }
5463 }
5464
5465 static void
5466 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5467 struct nir_shader *nir)
5468 {
5469 prepare_interp_optimize(ctx, nir);
5470
5471 nir_foreach_variable(variable, &nir->inputs)
5472 handle_fs_input_decl(ctx, variable);
5473
5474 unsigned index = 0;
5475
5476 if (ctx->shader_info->info.ps.uses_input_attachments ||
5477 ctx->shader_info->info.needs_multiview_view_index)
5478 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5479
5480 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5481 LLVMValueRef interp_param;
5482 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5483
5484 if (!(ctx->input_mask & (1ull << i)))
5485 continue;
5486
5487 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5488 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5489 interp_param = *inputs;
5490 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5491 inputs);
5492
5493 if (!interp_param)
5494 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5495 ++index;
5496 } else if (i == VARYING_SLOT_POS) {
5497 for(int i = 0; i < 3; ++i)
5498 inputs[i] = ctx->abi.frag_pos[i];
5499
5500 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5501 ctx->abi.frag_pos[3]);
5502 }
5503 }
5504 ctx->shader_info->fs.num_interp = index;
5505 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5506 ctx->shader_info->fs.has_pcoord = true;
5507 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5508 ctx->shader_info->fs.prim_id_input = true;
5509 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5510 ctx->shader_info->fs.layer_input = true;
5511 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5512
5513 if (ctx->shader_info->info.needs_multiview_view_index)
5514 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5515 }
5516
5517 static LLVMValueRef
5518 ac_build_alloca(struct ac_llvm_context *ac,
5519 LLVMTypeRef type,
5520 const char *name)
5521 {
5522 LLVMBuilderRef builder = ac->builder;
5523 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5524 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5525 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5526 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5527 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5528 LLVMValueRef res;
5529
5530 if (first_instr) {
5531 LLVMPositionBuilderBefore(first_builder, first_instr);
5532 } else {
5533 LLVMPositionBuilderAtEnd(first_builder, first_block);
5534 }
5535
5536 res = LLVMBuildAlloca(first_builder, type, name);
5537 LLVMBuildStore(builder, LLVMConstNull(type), res);
5538
5539 LLVMDisposeBuilder(first_builder);
5540
5541 return res;
5542 }
5543
5544 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5545 LLVMTypeRef type,
5546 const char *name)
5547 {
5548 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5549 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5550 return ptr;
5551 }
5552
5553 static void
5554 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5555 struct nir_variable *variable,
5556 struct nir_shader *shader,
5557 gl_shader_stage stage)
5558 {
5559 int idx = variable->data.location + variable->data.index;
5560 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5561 uint64_t mask_attribs;
5562
5563 variable->data.driver_location = idx * 4;
5564
5565 /* tess ctrl has it's own load/store paths for outputs */
5566 if (stage == MESA_SHADER_TESS_CTRL)
5567 return;
5568
5569 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5570 if (stage == MESA_SHADER_VERTEX ||
5571 stage == MESA_SHADER_TESS_EVAL ||
5572 stage == MESA_SHADER_GEOMETRY) {
5573 if (idx == VARYING_SLOT_CLIP_DIST0) {
5574 int length = shader->info.clip_distance_array_size +
5575 shader->info.cull_distance_array_size;
5576 if (stage == MESA_SHADER_VERTEX) {
5577 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5578 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5579 }
5580 if (stage == MESA_SHADER_TESS_EVAL) {
5581 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5582 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5583 }
5584
5585 if (length > 4)
5586 attrib_count = 2;
5587 else
5588 attrib_count = 1;
5589 mask_attribs = 1ull << idx;
5590 }
5591 }
5592
5593 ctx->output_mask |= mask_attribs;
5594 }
5595
5596 static void
5597 handle_shader_output_decl(struct ac_nir_context *ctx,
5598 struct nir_shader *nir,
5599 struct nir_variable *variable)
5600 {
5601 unsigned output_loc = variable->data.driver_location / 4;
5602 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5603
5604 /* tess ctrl has it's own load/store paths for outputs */
5605 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5606 return;
5607
5608 if (ctx->stage == MESA_SHADER_VERTEX ||
5609 ctx->stage == MESA_SHADER_TESS_EVAL ||
5610 ctx->stage == MESA_SHADER_GEOMETRY) {
5611 int idx = variable->data.location + variable->data.index;
5612 if (idx == VARYING_SLOT_CLIP_DIST0) {
5613 int length = nir->info.clip_distance_array_size +
5614 nir->info.cull_distance_array_size;
5615
5616 if (length > 4)
5617 attrib_count = 2;
5618 else
5619 attrib_count = 1;
5620 }
5621 }
5622
5623 for (unsigned i = 0; i < attrib_count; ++i) {
5624 for (unsigned chan = 0; chan < 4; chan++) {
5625 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5626 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5627 }
5628 }
5629 }
5630
5631 static LLVMTypeRef
5632 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5633 enum glsl_base_type type)
5634 {
5635 switch (type) {
5636 case GLSL_TYPE_INT:
5637 case GLSL_TYPE_UINT:
5638 case GLSL_TYPE_BOOL:
5639 case GLSL_TYPE_SUBROUTINE:
5640 return ctx->ac.i32;
5641 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5642 return ctx->ac.f32;
5643 case GLSL_TYPE_INT64:
5644 case GLSL_TYPE_UINT64:
5645 return ctx->ac.i64;
5646 case GLSL_TYPE_DOUBLE:
5647 return ctx->ac.f64;
5648 default:
5649 unreachable("unknown GLSL type");
5650 }
5651 }
5652
5653 static LLVMTypeRef
5654 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5655 const struct glsl_type *type)
5656 {
5657 if (glsl_type_is_scalar(type)) {
5658 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5659 }
5660
5661 if (glsl_type_is_vector(type)) {
5662 return LLVMVectorType(
5663 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5664 glsl_get_vector_elements(type));
5665 }
5666
5667 if (glsl_type_is_matrix(type)) {
5668 return LLVMArrayType(
5669 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5670 glsl_get_matrix_columns(type));
5671 }
5672
5673 if (glsl_type_is_array(type)) {
5674 return LLVMArrayType(
5675 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5676 glsl_get_length(type));
5677 }
5678
5679 assert(glsl_type_is_struct(type));
5680
5681 LLVMTypeRef member_types[glsl_get_length(type)];
5682
5683 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5684 member_types[i] =
5685 glsl_to_llvm_type(ctx,
5686 glsl_get_struct_field(type, i));
5687 }
5688
5689 return LLVMStructTypeInContext(ctx->context, member_types,
5690 glsl_get_length(type), false);
5691 }
5692
5693 static void
5694 setup_locals(struct ac_nir_context *ctx,
5695 struct nir_function *func)
5696 {
5697 int i, j;
5698 ctx->num_locals = 0;
5699 nir_foreach_variable(variable, &func->impl->locals) {
5700 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5701 variable->data.driver_location = ctx->num_locals * 4;
5702 variable->data.location_frac = 0;
5703 ctx->num_locals += attrib_count;
5704 }
5705 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5706 if (!ctx->locals)
5707 return;
5708
5709 for (i = 0; i < ctx->num_locals; i++) {
5710 for (j = 0; j < 4; j++) {
5711 ctx->locals[i * 4 + j] =
5712 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5713 }
5714 }
5715 }
5716
5717 static void
5718 setup_shared(struct ac_nir_context *ctx,
5719 struct nir_shader *nir)
5720 {
5721 nir_foreach_variable(variable, &nir->shared) {
5722 LLVMValueRef shared =
5723 LLVMAddGlobalInAddressSpace(
5724 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5725 variable->name ? variable->name : "",
5726 AC_LOCAL_ADDR_SPACE);
5727 _mesa_hash_table_insert(ctx->vars, variable, shared);
5728 }
5729 }
5730
5731 static LLVMValueRef
5732 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5733 {
5734 v = ac_to_float(ctx, v);
5735 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5736 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5737 }
5738
5739
5740 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5741 LLVMValueRef src0, LLVMValueRef src1)
5742 {
5743 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5744 LLVMValueRef comp[2];
5745
5746 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5747 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5748 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5749 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5750 }
5751
5752 /* Initialize arguments for the shader export intrinsic */
5753 static void
5754 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5755 LLVMValueRef *values,
5756 unsigned target,
5757 struct ac_export_args *args)
5758 {
5759 /* Default is 0xf. Adjusted below depending on the format. */
5760 args->enabled_channels = 0xf;
5761
5762 /* Specify whether the EXEC mask represents the valid mask */
5763 args->valid_mask = 0;
5764
5765 /* Specify whether this is the last export */
5766 args->done = 0;
5767
5768 /* Specify the target we are exporting */
5769 args->target = target;
5770
5771 args->compr = false;
5772 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5773 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5774 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5775 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5776
5777 if (!values)
5778 return;
5779
5780 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5781 LLVMValueRef val[4];
5782 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5783 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5784 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5785 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5786
5787 switch(col_format) {
5788 case V_028714_SPI_SHADER_ZERO:
5789 args->enabled_channels = 0; /* writemask */
5790 args->target = V_008DFC_SQ_EXP_NULL;
5791 break;
5792
5793 case V_028714_SPI_SHADER_32_R:
5794 args->enabled_channels = 1;
5795 args->out[0] = values[0];
5796 break;
5797
5798 case V_028714_SPI_SHADER_32_GR:
5799 args->enabled_channels = 0x3;
5800 args->out[0] = values[0];
5801 args->out[1] = values[1];
5802 break;
5803
5804 case V_028714_SPI_SHADER_32_AR:
5805 args->enabled_channels = 0x9;
5806 args->out[0] = values[0];
5807 args->out[3] = values[3];
5808 break;
5809
5810 case V_028714_SPI_SHADER_FP16_ABGR:
5811 args->compr = 1;
5812
5813 for (unsigned chan = 0; chan < 2; chan++) {
5814 LLVMValueRef pack_args[2] = {
5815 values[2 * chan],
5816 values[2 * chan + 1]
5817 };
5818 LLVMValueRef packed;
5819
5820 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5821 args->out[chan] = packed;
5822 }
5823 break;
5824
5825 case V_028714_SPI_SHADER_UNORM16_ABGR:
5826 for (unsigned chan = 0; chan < 4; chan++) {
5827 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5828 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5829 LLVMConstReal(ctx->ac.f32, 65535), "");
5830 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5831 LLVMConstReal(ctx->ac.f32, 0.5), "");
5832 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5833 ctx->ac.i32, "");
5834 }
5835
5836 args->compr = 1;
5837 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5838 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5839 break;
5840
5841 case V_028714_SPI_SHADER_SNORM16_ABGR:
5842 for (unsigned chan = 0; chan < 4; chan++) {
5843 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5844 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5845 LLVMConstReal(ctx->ac.f32, 32767), "");
5846
5847 /* If positive, add 0.5, else add -0.5. */
5848 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5849 LLVMBuildSelect(ctx->builder,
5850 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5851 val[chan], ctx->ac.f32_0, ""),
5852 LLVMConstReal(ctx->ac.f32, 0.5),
5853 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5854 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5855 }
5856
5857 args->compr = 1;
5858 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5859 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5860 break;
5861
5862 case V_028714_SPI_SHADER_UINT16_ABGR: {
5863 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5864 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5865 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5866
5867 for (unsigned chan = 0; chan < 4; chan++) {
5868 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5869 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5870 }
5871
5872 args->compr = 1;
5873 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5874 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5875 break;
5876 }
5877
5878 case V_028714_SPI_SHADER_SINT16_ABGR: {
5879 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5880 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5881 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5882 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5883 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5884 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5885
5886 /* Clamp. */
5887 for (unsigned chan = 0; chan < 4; chan++) {
5888 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5889 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5890 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5891 }
5892
5893 args->compr = 1;
5894 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5895 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5896 break;
5897 }
5898
5899 default:
5900 case V_028714_SPI_SHADER_32_ABGR:
5901 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5902 break;
5903 }
5904 } else
5905 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5906
5907 for (unsigned i = 0; i < 4; ++i)
5908 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5909 }
5910
5911 static void
5912 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5913 bool export_prim_id,
5914 struct ac_vs_output_info *outinfo)
5915 {
5916 uint32_t param_count = 0;
5917 unsigned target;
5918 unsigned pos_idx, num_pos_exports = 0;
5919 struct ac_export_args args, pos_args[4] = {};
5920 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5921 int i;
5922
5923 if (ctx->options->key.has_multiview_view_index) {
5924 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5925 if(!*tmp_out) {
5926 for(unsigned i = 0; i < 4; ++i)
5927 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5928 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5929 }
5930
5931 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5932 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5933 }
5934
5935 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5936 sizeof(outinfo->vs_output_param_offset));
5937
5938 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5939 LLVMValueRef slots[8];
5940 unsigned j;
5941
5942 if (outinfo->cull_dist_mask)
5943 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5944
5945 i = VARYING_SLOT_CLIP_DIST0;
5946 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5947 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5948 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5949
5950 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5951 slots[i] = LLVMGetUndef(ctx->ac.f32);
5952
5953 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5954 target = V_008DFC_SQ_EXP_POS + 3;
5955 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5956 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5957 &args, sizeof(args));
5958 }
5959
5960 target = V_008DFC_SQ_EXP_POS + 2;
5961 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5962 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5963 &args, sizeof(args));
5964
5965 }
5966
5967 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5968 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5969 for (unsigned j = 0; j < 4; j++)
5970 pos_values[j] = LLVMBuildLoad(ctx->builder,
5971 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5972 }
5973 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5974
5975 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5976 outinfo->writes_pointsize = true;
5977 psize_value = LLVMBuildLoad(ctx->builder,
5978 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5979 }
5980
5981 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5982 outinfo->writes_layer = true;
5983 layer_value = LLVMBuildLoad(ctx->builder,
5984 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5985 }
5986
5987 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5988 outinfo->writes_viewport_index = true;
5989 viewport_index_value = LLVMBuildLoad(ctx->builder,
5990 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5991 }
5992
5993 if (outinfo->writes_pointsize ||
5994 outinfo->writes_layer ||
5995 outinfo->writes_viewport_index) {
5996 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5997 (outinfo->writes_layer == true ? 4 : 0));
5998 pos_args[1].valid_mask = 0;
5999 pos_args[1].done = 0;
6000 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6001 pos_args[1].compr = 0;
6002 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6003 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6004 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6005 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6006
6007 if (outinfo->writes_pointsize == true)
6008 pos_args[1].out[0] = psize_value;
6009 if (outinfo->writes_layer == true)
6010 pos_args[1].out[2] = layer_value;
6011 if (outinfo->writes_viewport_index == true) {
6012 if (ctx->options->chip_class >= GFX9) {
6013 /* GFX9 has the layer in out.z[10:0] and the viewport
6014 * index in out.z[19:16].
6015 */
6016 LLVMValueRef v = viewport_index_value;
6017 v = ac_to_integer(&ctx->ac, v);
6018 v = LLVMBuildShl(ctx->builder, v,
6019 LLVMConstInt(ctx->ac.i32, 16, false),
6020 "");
6021 v = LLVMBuildOr(ctx->builder, v,
6022 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6023
6024 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6025 pos_args[1].enabled_channels |= 1 << 2;
6026 } else {
6027 pos_args[1].out[3] = viewport_index_value;
6028 pos_args[1].enabled_channels |= 1 << 3;
6029 }
6030 }
6031 }
6032 for (i = 0; i < 4; i++) {
6033 if (pos_args[i].out[0])
6034 num_pos_exports++;
6035 }
6036
6037 pos_idx = 0;
6038 for (i = 0; i < 4; i++) {
6039 if (!pos_args[i].out[0])
6040 continue;
6041
6042 /* Specify the target we are exporting */
6043 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6044 if (pos_idx == num_pos_exports)
6045 pos_args[i].done = 1;
6046 ac_build_export(&ctx->ac, &pos_args[i]);
6047 }
6048
6049 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6050 LLVMValueRef values[4];
6051 if (!(ctx->output_mask & (1ull << i)))
6052 continue;
6053
6054 for (unsigned j = 0; j < 4; j++)
6055 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6056 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6057
6058 if (i == VARYING_SLOT_LAYER) {
6059 target = V_008DFC_SQ_EXP_PARAM + param_count;
6060 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
6061 param_count++;
6062 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
6063 target = V_008DFC_SQ_EXP_PARAM + param_count;
6064 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6065 param_count++;
6066 } else if (i >= VARYING_SLOT_VAR0) {
6067 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
6068 target = V_008DFC_SQ_EXP_PARAM + param_count;
6069 outinfo->vs_output_param_offset[i] = param_count;
6070 param_count++;
6071 } else
6072 continue;
6073
6074 si_llvm_init_export_args(ctx, values, target, &args);
6075
6076 if (target >= V_008DFC_SQ_EXP_POS &&
6077 target <= (V_008DFC_SQ_EXP_POS + 3)) {
6078 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6079 &args, sizeof(args));
6080 } else {
6081 ac_build_export(&ctx->ac, &args);
6082 }
6083 }
6084
6085 if (export_prim_id) {
6086 LLVMValueRef values[4];
6087 target = V_008DFC_SQ_EXP_PARAM + param_count;
6088 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
6089 param_count++;
6090
6091 values[0] = ctx->vs_prim_id;
6092 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6093 ctx->shader_info->vs.vgpr_comp_cnt);
6094 for (unsigned j = 1; j < 4; j++)
6095 values[j] = ctx->ac.f32_0;
6096 si_llvm_init_export_args(ctx, values, target, &args);
6097 ac_build_export(&ctx->ac, &args);
6098 outinfo->export_prim_id = true;
6099 }
6100
6101 outinfo->pos_exports = num_pos_exports;
6102 outinfo->param_exports = param_count;
6103 }
6104
6105 static void
6106 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6107 struct ac_es_output_info *outinfo)
6108 {
6109 int j;
6110 uint64_t max_output_written = 0;
6111 LLVMValueRef lds_base = NULL;
6112
6113 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6114 int param_index;
6115 int length = 4;
6116
6117 if (!(ctx->output_mask & (1ull << i)))
6118 continue;
6119
6120 if (i == VARYING_SLOT_CLIP_DIST0)
6121 length = ctx->num_output_clips + ctx->num_output_culls;
6122
6123 param_index = shader_io_get_unique_index(i);
6124
6125 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6126 }
6127
6128 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6129
6130 if (ctx->ac.chip_class >= GFX9) {
6131 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6132 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6133 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6134 LLVMConstInt(ctx->ac.i32, 24, false),
6135 LLVMConstInt(ctx->ac.i32, 4, false), false);
6136 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6137 LLVMBuildMul(ctx->ac.builder, wave_idx,
6138 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6139 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6140 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6141 }
6142
6143 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6144 LLVMValueRef dw_addr;
6145 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6146 int param_index;
6147 int length = 4;
6148
6149 if (!(ctx->output_mask & (1ull << i)))
6150 continue;
6151
6152 if (i == VARYING_SLOT_CLIP_DIST0)
6153 length = ctx->num_output_clips + ctx->num_output_culls;
6154
6155 param_index = shader_io_get_unique_index(i);
6156
6157 if (lds_base) {
6158 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6159 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6160 "");
6161 }
6162 for (j = 0; j < length; j++) {
6163 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6164 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6165
6166 if (ctx->ac.chip_class >= GFX9) {
6167 ac_lds_store(&ctx->ac, dw_addr,
6168 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6169 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6170 } else {
6171 ac_build_buffer_store_dword(&ctx->ac,
6172 ctx->esgs_ring,
6173 out_val, 1,
6174 NULL, ctx->es2gs_offset,
6175 (4 * param_index + j) * 4,
6176 1, 1, true, true);
6177 }
6178 }
6179 }
6180 }
6181
6182 static void
6183 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6184 {
6185 LLVMValueRef vertex_id = ctx->rel_auto_id;
6186 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6187 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6188 vertex_dw_stride, "");
6189
6190 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6191 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6192 int length = 4;
6193
6194 if (!(ctx->output_mask & (1ull << i)))
6195 continue;
6196
6197 if (i == VARYING_SLOT_CLIP_DIST0)
6198 length = ctx->num_output_clips + ctx->num_output_culls;
6199 int param = shader_io_get_unique_index(i);
6200 mark_tess_output(ctx, false, param);
6201 if (length > 4)
6202 mark_tess_output(ctx, false, param + 1);
6203 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6204 LLVMConstInt(ctx->ac.i32, param * 4, false),
6205 "");
6206 for (unsigned j = 0; j < length; j++) {
6207 ac_lds_store(&ctx->ac, dw_addr,
6208 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6209 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6210 }
6211 }
6212 }
6213
6214 struct ac_build_if_state
6215 {
6216 struct nir_to_llvm_context *ctx;
6217 LLVMValueRef condition;
6218 LLVMBasicBlockRef entry_block;
6219 LLVMBasicBlockRef true_block;
6220 LLVMBasicBlockRef false_block;
6221 LLVMBasicBlockRef merge_block;
6222 };
6223
6224 static LLVMBasicBlockRef
6225 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6226 {
6227 LLVMBasicBlockRef current_block;
6228 LLVMBasicBlockRef next_block;
6229 LLVMBasicBlockRef new_block;
6230
6231 /* get current basic block */
6232 current_block = LLVMGetInsertBlock(ctx->builder);
6233
6234 /* chqeck if there's another block after this one */
6235 next_block = LLVMGetNextBasicBlock(current_block);
6236 if (next_block) {
6237 /* insert the new block before the next block */
6238 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6239 }
6240 else {
6241 /* append new block after current block */
6242 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6243 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6244 }
6245 return new_block;
6246 }
6247
6248 static void
6249 ac_nir_build_if(struct ac_build_if_state *ifthen,
6250 struct nir_to_llvm_context *ctx,
6251 LLVMValueRef condition)
6252 {
6253 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6254
6255 memset(ifthen, 0, sizeof *ifthen);
6256 ifthen->ctx = ctx;
6257 ifthen->condition = condition;
6258 ifthen->entry_block = block;
6259
6260 /* create endif/merge basic block for the phi functions */
6261 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6262
6263 /* create/insert true_block before merge_block */
6264 ifthen->true_block =
6265 LLVMInsertBasicBlockInContext(ctx->context,
6266 ifthen->merge_block,
6267 "if-true-block");
6268
6269 /* successive code goes into the true block */
6270 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6271 }
6272
6273 /**
6274 * End a conditional.
6275 */
6276 static void
6277 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6278 {
6279 LLVMBuilderRef builder = ifthen->ctx->builder;
6280
6281 /* Insert branch to the merge block from current block */
6282 LLVMBuildBr(builder, ifthen->merge_block);
6283
6284 /*
6285 * Now patch in the various branch instructions.
6286 */
6287
6288 /* Insert the conditional branch instruction at the end of entry_block */
6289 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6290 if (ifthen->false_block) {
6291 /* we have an else clause */
6292 LLVMBuildCondBr(builder, ifthen->condition,
6293 ifthen->true_block, ifthen->false_block);
6294 }
6295 else {
6296 /* no else clause */
6297 LLVMBuildCondBr(builder, ifthen->condition,
6298 ifthen->true_block, ifthen->merge_block);
6299 }
6300
6301 /* Resume building code at end of the ifthen->merge_block */
6302 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6303 }
6304
6305 static void
6306 write_tess_factors(struct nir_to_llvm_context *ctx)
6307 {
6308 unsigned stride, outer_comps, inner_comps;
6309 struct ac_build_if_state if_ctx, inner_if_ctx;
6310 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6311 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6312 unsigned tess_inner_index, tess_outer_index;
6313 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6314 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6315 int i;
6316 emit_barrier(&ctx->ac, ctx->stage);
6317
6318 switch (ctx->options->key.tcs.primitive_mode) {
6319 case GL_ISOLINES:
6320 stride = 2;
6321 outer_comps = 2;
6322 inner_comps = 0;
6323 break;
6324 case GL_TRIANGLES:
6325 stride = 4;
6326 outer_comps = 3;
6327 inner_comps = 1;
6328 break;
6329 case GL_QUADS:
6330 stride = 6;
6331 outer_comps = 4;
6332 inner_comps = 2;
6333 break;
6334 default:
6335 return;
6336 }
6337
6338 ac_nir_build_if(&if_ctx, ctx,
6339 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6340 invocation_id, ctx->ac.i32_0, ""));
6341
6342 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6343 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6344
6345 mark_tess_output(ctx, true, tess_inner_index);
6346 mark_tess_output(ctx, true, tess_outer_index);
6347 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6348 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6349 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6350 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6351 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6352
6353 for (i = 0; i < 4; i++) {
6354 inner[i] = LLVMGetUndef(ctx->ac.i32);
6355 outer[i] = LLVMGetUndef(ctx->ac.i32);
6356 }
6357
6358 // LINES reverseal
6359 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6360 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6361 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6362 ctx->ac.i32_1, "");
6363 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6364 } else {
6365 for (i = 0; i < outer_comps; i++) {
6366 outer[i] = out[i] =
6367 ac_lds_load(&ctx->ac, lds_outer);
6368 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6369 ctx->ac.i32_1, "");
6370 }
6371 for (i = 0; i < inner_comps; i++) {
6372 inner[i] = out[outer_comps+i] =
6373 ac_lds_load(&ctx->ac, lds_inner);
6374 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6375 ctx->ac.i32_1, "");
6376 }
6377 }
6378
6379 /* Convert the outputs to vectors for stores. */
6380 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6381 vec1 = NULL;
6382
6383 if (stride > 4)
6384 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6385
6386
6387 buffer = ctx->hs_ring_tess_factor;
6388 tf_base = ctx->tess_factor_offset;
6389 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6390 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6391 unsigned tf_offset = 0;
6392
6393 if (ctx->options->chip_class <= VI) {
6394 ac_nir_build_if(&inner_if_ctx, ctx,
6395 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6396 rel_patch_id, ctx->ac.i32_0, ""));
6397
6398 /* Store the dynamic HS control word. */
6399 ac_build_buffer_store_dword(&ctx->ac, buffer,
6400 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6401 1, ctx->ac.i32_0, tf_base,
6402 0, 1, 0, true, false);
6403 tf_offset += 4;
6404
6405 ac_nir_build_endif(&inner_if_ctx);
6406 }
6407
6408 /* Store the tessellation factors. */
6409 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6410 MIN2(stride, 4), byteoffset, tf_base,
6411 tf_offset, 1, 0, true, false);
6412 if (vec1)
6413 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6414 stride - 4, byteoffset, tf_base,
6415 16 + tf_offset, 1, 0, true, false);
6416
6417 //store to offchip for TES to read - only if TES reads them
6418 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6419 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6420 LLVMValueRef tf_inner_offset;
6421 unsigned param_outer, param_inner;
6422
6423 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6424 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6425 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6426
6427 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6428 util_next_power_of_two(outer_comps));
6429
6430 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6431 outer_comps, tf_outer_offset,
6432 ctx->oc_lds, 0, 1, 0, true, false);
6433 if (inner_comps) {
6434 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6435 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6436 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6437
6438 inner_vec = inner_comps == 1 ? inner[0] :
6439 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6440 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6441 inner_comps, tf_inner_offset,
6442 ctx->oc_lds, 0, 1, 0, true, false);
6443 }
6444 }
6445 ac_nir_build_endif(&if_ctx);
6446 }
6447
6448 static void
6449 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6450 {
6451 write_tess_factors(ctx);
6452 }
6453
6454 static bool
6455 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6456 LLVMValueRef *color, unsigned param, bool is_last,
6457 struct ac_export_args *args)
6458 {
6459 /* Export */
6460 si_llvm_init_export_args(ctx, color, param,
6461 args);
6462
6463 if (is_last) {
6464 args->valid_mask = 1; /* whether the EXEC mask is valid */
6465 args->done = 1; /* DONE bit */
6466 } else if (!args->enabled_channels)
6467 return false; /* unnecessary NULL export */
6468
6469 return true;
6470 }
6471
6472 static void
6473 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6474 LLVMValueRef depth, LLVMValueRef stencil,
6475 LLVMValueRef samplemask)
6476 {
6477 struct ac_export_args args;
6478
6479 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6480
6481 ac_build_export(&ctx->ac, &args);
6482 }
6483
6484 static void
6485 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6486 {
6487 unsigned index = 0;
6488 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6489 struct ac_export_args color_args[8];
6490
6491 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6492 LLVMValueRef values[4];
6493
6494 if (!(ctx->output_mask & (1ull << i)))
6495 continue;
6496
6497 if (i == FRAG_RESULT_DEPTH) {
6498 ctx->shader_info->fs.writes_z = true;
6499 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6500 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6501 } else if (i == FRAG_RESULT_STENCIL) {
6502 ctx->shader_info->fs.writes_stencil = true;
6503 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6504 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6505 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6506 ctx->shader_info->fs.writes_sample_mask = true;
6507 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6508 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6509 } else {
6510 bool last = false;
6511 for (unsigned j = 0; j < 4; j++)
6512 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6513 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6514
6515 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6516 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6517
6518 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6519 if (ret)
6520 index++;
6521 }
6522 }
6523
6524 for (unsigned i = 0; i < index; i++)
6525 ac_build_export(&ctx->ac, &color_args[i]);
6526 if (depth || stencil || samplemask)
6527 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6528 else if (!index) {
6529 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6530 ac_build_export(&ctx->ac, &color_args[0]);
6531 }
6532 }
6533
6534 static void
6535 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6536 {
6537 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6538 }
6539
6540 static void
6541 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6542 LLVMValueRef *addrs)
6543 {
6544 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6545
6546 switch (ctx->stage) {
6547 case MESA_SHADER_VERTEX:
6548 if (ctx->options->key.vs.as_ls)
6549 handle_ls_outputs_post(ctx);
6550 else if (ctx->options->key.vs.as_es)
6551 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6552 else
6553 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6554 &ctx->shader_info->vs.outinfo);
6555 break;
6556 case MESA_SHADER_FRAGMENT:
6557 handle_fs_outputs_post(ctx);
6558 break;
6559 case MESA_SHADER_GEOMETRY:
6560 emit_gs_epilogue(ctx);
6561 break;
6562 case MESA_SHADER_TESS_CTRL:
6563 handle_tcs_outputs_post(ctx);
6564 break;
6565 case MESA_SHADER_TESS_EVAL:
6566 if (ctx->options->key.tes.as_es)
6567 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6568 else
6569 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6570 &ctx->shader_info->tes.outinfo);
6571 break;
6572 default:
6573 break;
6574 }
6575 }
6576
6577 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6578 {
6579 LLVMPassManagerRef passmgr;
6580 /* Create the pass manager */
6581 passmgr = LLVMCreateFunctionPassManagerForModule(
6582 ctx->module);
6583
6584 /* This pass should eliminate all the load and store instructions */
6585 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6586
6587 /* Add some optimization passes */
6588 LLVMAddScalarReplAggregatesPass(passmgr);
6589 LLVMAddLICMPass(passmgr);
6590 LLVMAddAggressiveDCEPass(passmgr);
6591 LLVMAddCFGSimplificationPass(passmgr);
6592 LLVMAddInstructionCombiningPass(passmgr);
6593
6594 /* Run the pass */
6595 LLVMInitializeFunctionPassManager(passmgr);
6596 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6597 LLVMFinalizeFunctionPassManager(passmgr);
6598
6599 LLVMDisposeBuilder(ctx->builder);
6600 LLVMDisposePassManager(passmgr);
6601 }
6602
6603 static void
6604 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6605 {
6606 struct ac_vs_output_info *outinfo;
6607
6608 switch (ctx->stage) {
6609 case MESA_SHADER_FRAGMENT:
6610 case MESA_SHADER_COMPUTE:
6611 case MESA_SHADER_TESS_CTRL:
6612 case MESA_SHADER_GEOMETRY:
6613 return;
6614 case MESA_SHADER_VERTEX:
6615 if (ctx->options->key.vs.as_ls ||
6616 ctx->options->key.vs.as_es)
6617 return;
6618 outinfo = &ctx->shader_info->vs.outinfo;
6619 break;
6620 case MESA_SHADER_TESS_EVAL:
6621 if (ctx->options->key.vs.as_es)
6622 return;
6623 outinfo = &ctx->shader_info->tes.outinfo;
6624 break;
6625 default:
6626 unreachable("Unhandled shader type");
6627 }
6628
6629 ac_optimize_vs_outputs(&ctx->ac,
6630 ctx->main_function,
6631 outinfo->vs_output_param_offset,
6632 VARYING_SLOT_MAX,
6633 &outinfo->param_exports);
6634 }
6635
6636 static void
6637 ac_setup_rings(struct nir_to_llvm_context *ctx)
6638 {
6639 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6640 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6641 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6642 }
6643
6644 if (ctx->is_gs_copy_shader) {
6645 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6646 }
6647 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6648 LLVMValueRef tmp;
6649 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6650 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6651
6652 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6653
6654 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6655 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6656 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6657 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6658 }
6659
6660 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6661 ctx->stage == MESA_SHADER_TESS_EVAL) {
6662 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6663 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6664 }
6665 }
6666
6667 static unsigned
6668 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6669 const struct nir_shader *nir)
6670 {
6671 switch (nir->info.stage) {
6672 case MESA_SHADER_TESS_CTRL:
6673 return chip_class >= CIK ? 128 : 64;
6674 case MESA_SHADER_GEOMETRY:
6675 return chip_class >= GFX9 ? 128 : 64;
6676 case MESA_SHADER_COMPUTE:
6677 break;
6678 default:
6679 return 0;
6680 }
6681
6682 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6683 nir->info.cs.local_size[1] *
6684 nir->info.cs.local_size[2];
6685 return max_workgroup_size;
6686 }
6687
6688 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6689 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6690 {
6691 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6692 LLVMConstInt(ctx->ac.i32, 8, false),
6693 LLVMConstInt(ctx->ac.i32, 8, false), false);
6694 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6695 ctx->ac.i32_0, "");
6696 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6697 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6698 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6699 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6700 }
6701
6702 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6703 {
6704 for(int i = 5; i >= 0; --i) {
6705 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6706 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6707 LLVMConstInt(ctx->ac.i32, 16, false), false);
6708 }
6709
6710 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6711 LLVMConstInt(ctx->ac.i32, 16, false),
6712 LLVMConstInt(ctx->ac.i32, 8, false), false);
6713 }
6714
6715 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6716 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6717 {
6718 struct ac_nir_context ctx = {};
6719 struct nir_function *func;
6720
6721 ctx.ac = *ac;
6722 ctx.abi = abi;
6723
6724 ctx.nctx = nctx;
6725 if (nctx)
6726 nctx->nir = &ctx;
6727
6728 ctx.stage = nir->info.stage;
6729
6730 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6731
6732 nir_foreach_variable(variable, &nir->outputs)
6733 handle_shader_output_decl(&ctx, nir, variable);
6734
6735 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6736 _mesa_key_pointer_equal);
6737 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6738 _mesa_key_pointer_equal);
6739 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6740 _mesa_key_pointer_equal);
6741
6742 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6743
6744 setup_locals(&ctx, func);
6745
6746 if (nir->info.stage == MESA_SHADER_COMPUTE)
6747 setup_shared(&ctx, nir);
6748
6749 visit_cf_list(&ctx, &func->impl->body);
6750 phi_post_pass(&ctx);
6751
6752 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6753 ctx.outputs);
6754
6755 free(ctx.locals);
6756 ralloc_free(ctx.defs);
6757 ralloc_free(ctx.phis);
6758 ralloc_free(ctx.vars);
6759
6760 if (nctx)
6761 nctx->nir = NULL;
6762 }
6763
6764 static
6765 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6766 struct nir_shader *const *shaders,
6767 int shader_count,
6768 struct ac_shader_variant_info *shader_info,
6769 const struct ac_nir_compiler_options *options)
6770 {
6771 struct nir_to_llvm_context ctx = {0};
6772 unsigned i;
6773 ctx.options = options;
6774 ctx.shader_info = shader_info;
6775 ctx.context = LLVMContextCreate();
6776 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6777
6778 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6779 options->family);
6780 ctx.ac.module = ctx.module;
6781 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6782
6783 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6784 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6785 LLVMSetDataLayout(ctx.module, data_layout_str);
6786 LLVMDisposeTargetData(data_layout);
6787 LLVMDisposeMessage(data_layout_str);
6788
6789 enum ac_float_mode float_mode =
6790 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6791 AC_FLOAT_MODE_DEFAULT;
6792
6793 ctx.builder = ac_create_builder(ctx.context, float_mode);
6794 ctx.ac.builder = ctx.builder;
6795
6796 memset(shader_info, 0, sizeof(*shader_info));
6797
6798 for(int i = 0; i < shader_count; ++i)
6799 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6800
6801 for (i = 0; i < AC_UD_MAX_SETS; i++)
6802 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6803 for (i = 0; i < AC_UD_MAX_UD; i++)
6804 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6805
6806 ctx.max_workgroup_size = 0;
6807 for (int i = 0; i < shader_count; ++i) {
6808 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6809 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6810 shaders[i]));
6811 }
6812
6813 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6814 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6815
6816 ctx.abi.inputs = &ctx.inputs[0];
6817 ctx.abi.emit_outputs = handle_shader_outputs_post;
6818 ctx.abi.emit_vertex = visit_emit_vertex;
6819 ctx.abi.load_ubo = radv_load_ubo;
6820 ctx.abi.load_ssbo = radv_load_ssbo;
6821 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6822 ctx.abi.clamp_shadow_reference = false;
6823
6824 if (shader_count >= 2)
6825 ac_init_exec_full_mask(&ctx.ac);
6826
6827 if (ctx.ac.chip_class == GFX9 &&
6828 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6829 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6830
6831 for(int i = 0; i < shader_count; ++i) {
6832 ctx.stage = shaders[i]->info.stage;
6833 ctx.output_mask = 0;
6834 ctx.tess_outputs_written = 0;
6835 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6836 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6837
6838 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6839 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6840 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6841 ctx.abi.load_inputs = load_gs_input;
6842 ctx.abi.emit_primitive = visit_end_primitive;
6843 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6844 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6845 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6846 ctx.abi.load_tess_varyings = load_tcs_varyings;
6847 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6848 ctx.abi.store_tcs_outputs = store_tcs_output;
6849 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6850 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6851 ctx.abi.load_tess_varyings = load_tes_input;
6852 ctx.abi.load_tess_coord = load_tess_coord;
6853 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6854 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6855 if (shader_info->info.vs.needs_instance_id) {
6856 if (ctx.options->key.vs.as_ls) {
6857 ctx.shader_info->vs.vgpr_comp_cnt =
6858 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6859 } else {
6860 ctx.shader_info->vs.vgpr_comp_cnt =
6861 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6862 }
6863 }
6864 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6865 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6866 ctx.abi.lookup_interp_param = lookup_interp_param;
6867 ctx.abi.load_sample_position = load_sample_position;
6868 }
6869
6870 if (i)
6871 emit_barrier(&ctx.ac, ctx.stage);
6872
6873 ac_setup_rings(&ctx);
6874
6875 LLVMBasicBlockRef merge_block;
6876 if (shader_count >= 2) {
6877 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6878 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6879 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6880
6881 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6882 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6883 LLVMConstInt(ctx.ac.i32, 8, false), false);
6884 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6885 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6886 thread_id, count, "");
6887 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6888
6889 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6890 }
6891
6892 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6893 handle_fs_inputs(&ctx, shaders[i]);
6894 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6895 handle_vs_inputs(&ctx, shaders[i]);
6896 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6897 prepare_gs_input_vgprs(&ctx);
6898
6899 nir_foreach_variable(variable, &shaders[i]->outputs)
6900 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6901
6902 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6903
6904 if (shader_count >= 2) {
6905 LLVMBuildBr(ctx.ac.builder, merge_block);
6906 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6907 }
6908
6909 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6910 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6911 shaders[i]->info.cull_distance_array_size > 4;
6912 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6913 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6914 shaders[i]->info.gs.vertices_out;
6915 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6916 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6917 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6918 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6919 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6920 }
6921 }
6922
6923 LLVMBuildRetVoid(ctx.builder);
6924
6925 if (options->dump_preoptir)
6926 ac_dump_module(ctx.module);
6927
6928 ac_llvm_finalize_module(&ctx);
6929
6930 if (shader_count == 1)
6931 ac_nir_eliminate_const_vs_outputs(&ctx);
6932
6933 return ctx.module;
6934 }
6935
6936 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6937 {
6938 unsigned *retval = (unsigned *)context;
6939 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6940 char *description = LLVMGetDiagInfoDescription(di);
6941
6942 if (severity == LLVMDSError) {
6943 *retval = 1;
6944 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6945 description);
6946 }
6947
6948 LLVMDisposeMessage(description);
6949 }
6950
6951 static unsigned ac_llvm_compile(LLVMModuleRef M,
6952 struct ac_shader_binary *binary,
6953 LLVMTargetMachineRef tm)
6954 {
6955 unsigned retval = 0;
6956 char *err;
6957 LLVMContextRef llvm_ctx;
6958 LLVMMemoryBufferRef out_buffer;
6959 unsigned buffer_size;
6960 const char *buffer_data;
6961 LLVMBool mem_err;
6962
6963 /* Setup Diagnostic Handler*/
6964 llvm_ctx = LLVMGetModuleContext(M);
6965
6966 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6967 &retval);
6968
6969 /* Compile IR*/
6970 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6971 &err, &out_buffer);
6972
6973 /* Process Errors/Warnings */
6974 if (mem_err) {
6975 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6976 free(err);
6977 retval = 1;
6978 goto out;
6979 }
6980
6981 /* Extract Shader Code*/
6982 buffer_size = LLVMGetBufferSize(out_buffer);
6983 buffer_data = LLVMGetBufferStart(out_buffer);
6984
6985 ac_elf_read(buffer_data, buffer_size, binary);
6986
6987 /* Clean up */
6988 LLVMDisposeMemoryBuffer(out_buffer);
6989
6990 out:
6991 return retval;
6992 }
6993
6994 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6995 LLVMModuleRef llvm_module,
6996 struct ac_shader_binary *binary,
6997 struct ac_shader_config *config,
6998 struct ac_shader_variant_info *shader_info,
6999 gl_shader_stage stage,
7000 bool dump_shader, bool supports_spill)
7001 {
7002 if (dump_shader)
7003 ac_dump_module(llvm_module);
7004
7005 memset(binary, 0, sizeof(*binary));
7006 int v = ac_llvm_compile(llvm_module, binary, tm);
7007 if (v) {
7008 fprintf(stderr, "compile failed\n");
7009 }
7010
7011 if (dump_shader)
7012 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7013
7014 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7015
7016 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7017 LLVMDisposeModule(llvm_module);
7018 LLVMContextDispose(ctx);
7019
7020 if (stage == MESA_SHADER_FRAGMENT) {
7021 shader_info->num_input_vgprs = 0;
7022 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7023 shader_info->num_input_vgprs += 2;
7024 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7025 shader_info->num_input_vgprs += 2;
7026 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7027 shader_info->num_input_vgprs += 2;
7028 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7029 shader_info->num_input_vgprs += 3;
7030 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7031 shader_info->num_input_vgprs += 2;
7032 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7033 shader_info->num_input_vgprs += 2;
7034 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7035 shader_info->num_input_vgprs += 2;
7036 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7037 shader_info->num_input_vgprs += 1;
7038 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7039 shader_info->num_input_vgprs += 1;
7040 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7041 shader_info->num_input_vgprs += 1;
7042 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7043 shader_info->num_input_vgprs += 1;
7044 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7045 shader_info->num_input_vgprs += 1;
7046 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7047 shader_info->num_input_vgprs += 1;
7048 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7049 shader_info->num_input_vgprs += 1;
7050 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7051 shader_info->num_input_vgprs += 1;
7052 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7053 shader_info->num_input_vgprs += 1;
7054 }
7055 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7056
7057 /* +3 for scratch wave offset and VCC */
7058 config->num_sgprs = MAX2(config->num_sgprs,
7059 shader_info->num_input_sgprs + 3);
7060
7061 /* Enable 64-bit and 16-bit denormals, because there is no performance
7062 * cost.
7063 *
7064 * If denormals are enabled, all floating-point output modifiers are
7065 * ignored.
7066 *
7067 * Don't enable denormals for 32-bit floats, because:
7068 * - Floating-point output modifiers would be ignored by the hw.
7069 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7070 * have to stop using those.
7071 * - SI & CI would be very slow.
7072 */
7073 config->float_mode |= V_00B028_FP_64_DENORMS;
7074 }
7075
7076 static void
7077 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7078 {
7079 switch (nir->info.stage) {
7080 case MESA_SHADER_COMPUTE:
7081 for (int i = 0; i < 3; ++i)
7082 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7083 break;
7084 case MESA_SHADER_FRAGMENT:
7085 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7086 break;
7087 case MESA_SHADER_GEOMETRY:
7088 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7089 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7090 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7091 shader_info->gs.invocations = nir->info.gs.invocations;
7092 break;
7093 case MESA_SHADER_TESS_EVAL:
7094 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7095 shader_info->tes.spacing = nir->info.tess.spacing;
7096 shader_info->tes.ccw = nir->info.tess.ccw;
7097 shader_info->tes.point_mode = nir->info.tess.point_mode;
7098 shader_info->tes.as_es = options->key.tes.as_es;
7099 break;
7100 case MESA_SHADER_TESS_CTRL:
7101 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7102 break;
7103 case MESA_SHADER_VERTEX:
7104 shader_info->vs.as_es = options->key.vs.as_es;
7105 shader_info->vs.as_ls = options->key.vs.as_ls;
7106 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7107 if (options->key.vs.as_ls)
7108 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7109 break;
7110 default:
7111 break;
7112 }
7113 }
7114
7115 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7116 struct ac_shader_binary *binary,
7117 struct ac_shader_config *config,
7118 struct ac_shader_variant_info *shader_info,
7119 struct nir_shader *const *nir,
7120 int nir_count,
7121 const struct ac_nir_compiler_options *options,
7122 bool dump_shader)
7123 {
7124
7125 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7126 options);
7127
7128 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7129 for (int i = 0; i < nir_count; ++i)
7130 ac_fill_shader_info(shader_info, nir[i], options);
7131
7132 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7133 if (options->chip_class == GFX9) {
7134 if (nir_count == 2 &&
7135 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7136 shader_info->gs.es_type = nir[0]->info.stage;
7137 }
7138 }
7139 }
7140
7141 static void
7142 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7143 {
7144 LLVMValueRef vtx_offset =
7145 LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
7146 LLVMConstInt(ctx->ac.i32, 4, false), "");
7147 int idx = 0;
7148
7149 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7150 int length = 4;
7151 int slot = idx;
7152 int slot_inc = 1;
7153 if (!(ctx->output_mask & (1ull << i)))
7154 continue;
7155
7156 if (i == VARYING_SLOT_CLIP_DIST0) {
7157 /* unpack clip and cull from a single set of slots */
7158 length = ctx->num_output_clips + ctx->num_output_culls;
7159 if (length > 4)
7160 slot_inc = 2;
7161 }
7162
7163 for (unsigned j = 0; j < length; j++) {
7164 LLVMValueRef value, soffset;
7165
7166 soffset = LLVMConstInt(ctx->ac.i32,
7167 (slot * 4 + j) *
7168 ctx->gs_max_out_vertices * 16 * 4, false);
7169
7170 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7171 1, ctx->ac.i32_0,
7172 vtx_offset, soffset,
7173 0, 1, 1, true, false);
7174
7175 LLVMBuildStore(ctx->builder,
7176 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7177 }
7178 idx += slot_inc;
7179 }
7180 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7181 }
7182
7183 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7184 struct nir_shader *geom_shader,
7185 struct ac_shader_binary *binary,
7186 struct ac_shader_config *config,
7187 struct ac_shader_variant_info *shader_info,
7188 const struct ac_nir_compiler_options *options,
7189 bool dump_shader)
7190 {
7191 struct nir_to_llvm_context ctx = {0};
7192 ctx.context = LLVMContextCreate();
7193 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7194 ctx.options = options;
7195 ctx.shader_info = shader_info;
7196
7197 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7198 options->family);
7199 ctx.ac.module = ctx.module;
7200
7201 ctx.is_gs_copy_shader = true;
7202 LLVMSetTarget(ctx.module, "amdgcn--");
7203
7204 enum ac_float_mode float_mode =
7205 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7206 AC_FLOAT_MODE_DEFAULT;
7207
7208 ctx.builder = ac_create_builder(ctx.context, float_mode);
7209 ctx.ac.builder = ctx.builder;
7210 ctx.stage = MESA_SHADER_VERTEX;
7211
7212 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7213
7214 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7215 ac_setup_rings(&ctx);
7216
7217 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7218 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7219
7220 struct ac_nir_context nir_ctx = {};
7221 nir_ctx.ac = ctx.ac;
7222 nir_ctx.abi = &ctx.abi;
7223
7224 nir_ctx.nctx = &ctx;
7225 ctx.nir = &nir_ctx;
7226
7227 nir_foreach_variable(variable, &geom_shader->outputs) {
7228 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7229 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7230 }
7231
7232 ac_gs_copy_shader_emit(&ctx);
7233
7234 ctx.nir = NULL;
7235
7236 LLVMBuildRetVoid(ctx.builder);
7237
7238 ac_llvm_finalize_module(&ctx);
7239
7240 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7241 MESA_SHADER_VERTEX,
7242 dump_shader, options->supports_spill);
7243 }