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ac/nir: Handle loading data from compact arrays.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
547 struct user_sgpr_info *user_sgpr_info)
548 {
549 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
550
551 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
552 if (ctx->stage == MESA_SHADER_GEOMETRY ||
553 ctx->stage == MESA_SHADER_VERTEX ||
554 ctx->stage == MESA_SHADER_TESS_CTRL ||
555 ctx->stage == MESA_SHADER_TESS_EVAL ||
556 ctx->is_gs_copy_shader)
557 user_sgpr_info->need_ring_offsets = true;
558
559 if (ctx->stage == MESA_SHADER_FRAGMENT &&
560 ctx->shader_info->info.ps.needs_sample_positions)
561 user_sgpr_info->need_ring_offsets = true;
562
563 /* 2 user sgprs will nearly always be allocated for scratch/rings */
564 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
565 user_sgpr_info->sgpr_count += 2;
566 }
567
568 switch (ctx->stage) {
569 case MESA_SHADER_COMPUTE:
570 if (ctx->shader_info->info.cs.uses_grid_size)
571 user_sgpr_info->sgpr_count += 3;
572 break;
573 case MESA_SHADER_FRAGMENT:
574 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
575 break;
576 case MESA_SHADER_VERTEX:
577 if (!ctx->is_gs_copy_shader) {
578 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
579 if (ctx->shader_info->info.vs.needs_draw_id) {
580 user_sgpr_info->sgpr_count += 3;
581 } else {
582 user_sgpr_info->sgpr_count += 2;
583 }
584 }
585 if (ctx->options->key.vs.as_ls)
586 user_sgpr_info->sgpr_count++;
587 break;
588 case MESA_SHADER_TESS_CTRL:
589 user_sgpr_info->sgpr_count += 4;
590 break;
591 case MESA_SHADER_TESS_EVAL:
592 user_sgpr_info->sgpr_count += 1;
593 break;
594 case MESA_SHADER_GEOMETRY:
595 user_sgpr_info->sgpr_count += 2;
596 break;
597 default:
598 break;
599 }
600
601 if (ctx->shader_info->info.needs_push_constants)
602 user_sgpr_info->sgpr_count += 2;
603
604 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
605 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
606 user_sgpr_info->sgpr_count += 2;
607 user_sgpr_info->indirect_all_descriptor_sets = true;
608 } else {
609 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
610 }
611 }
612
613 static void
614 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
615 gl_shader_stage stage,
616 bool has_previous_stage,
617 gl_shader_stage previous_stage,
618 const struct user_sgpr_info *user_sgpr_info,
619 struct arg_info *args,
620 LLVMValueRef *desc_sets)
621 {
622 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
623 unsigned num_sets = ctx->options->layout ?
624 ctx->options->layout->num_sets : 0;
625 unsigned stage_mask = 1 << stage;
626
627 if (has_previous_stage)
628 stage_mask |= 1 << previous_stage;
629
630 /* 1 for each descriptor set */
631 if (!user_sgpr_info->indirect_all_descriptor_sets) {
632 for (unsigned i = 0; i < num_sets; ++i) {
633 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
634 add_array_arg(args, type,
635 &ctx->descriptor_sets[i]);
636 }
637 }
638 } else {
639 add_array_arg(args, const_array(type, 32), desc_sets);
640 }
641
642 if (ctx->shader_info->info.needs_push_constants) {
643 /* 1 for push constants and dynamic descriptors */
644 add_array_arg(args, type, &ctx->push_constants);
645 }
646 }
647
648 static void
649 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
650 gl_shader_stage stage,
651 bool has_previous_stage,
652 gl_shader_stage previous_stage,
653 struct arg_info *args)
654 {
655 if (!ctx->is_gs_copy_shader &&
656 (stage == MESA_SHADER_VERTEX ||
657 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
658 if (ctx->shader_info->info.vs.has_vertex_buffers) {
659 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
660 &ctx->vertex_buffers);
661 }
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
664 if (ctx->shader_info->info.vs.needs_draw_id) {
665 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
666 }
667 }
668 }
669
670 static void
671 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
672 {
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
674 if (!ctx->is_gs_copy_shader) {
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
678 }
679 }
680
681 static void
682 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
683 {
684 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
685 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
686 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
687 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
688 }
689
690 static void
691 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
692 bool has_previous_stage, gl_shader_stage previous_stage,
693 const struct user_sgpr_info *user_sgpr_info,
694 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
695 {
696 unsigned num_sets = ctx->options->layout ?
697 ctx->options->layout->num_sets : 0;
698 unsigned stage_mask = 1 << stage;
699
700 if (has_previous_stage)
701 stage_mask |= 1 << previous_stage;
702
703 if (!user_sgpr_info->indirect_all_descriptor_sets) {
704 for (unsigned i = 0; i < num_sets; ++i) {
705 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
706 set_loc_desc(ctx, i, user_sgpr_idx, 0);
707 } else
708 ctx->descriptor_sets[i] = NULL;
709 }
710 } else {
711 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
712 user_sgpr_idx, 2);
713
714 for (unsigned i = 0; i < num_sets; ++i) {
715 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
716 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
717 ctx->descriptor_sets[i] =
718 ac_build_load_to_sgpr(&ctx->ac,
719 desc_sets,
720 LLVMConstInt(ctx->ac.i32, i, false));
721
722 } else
723 ctx->descriptor_sets[i] = NULL;
724 }
725 ctx->shader_info->need_indirect_descriptor_sets = true;
726 }
727
728 if (ctx->shader_info->info.needs_push_constants) {
729 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
730 }
731 }
732
733 static void
734 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
735 gl_shader_stage stage, bool has_previous_stage,
736 gl_shader_stage previous_stage,
737 uint8_t *user_sgpr_idx)
738 {
739 if (!ctx->is_gs_copy_shader &&
740 (stage == MESA_SHADER_VERTEX ||
741 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
742 if (ctx->shader_info->info.vs.has_vertex_buffers) {
743 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
744 user_sgpr_idx, 2);
745 }
746
747 unsigned vs_num = 2;
748 if (ctx->shader_info->info.vs.needs_draw_id)
749 vs_num++;
750
751 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
752 user_sgpr_idx, vs_num);
753 }
754 }
755
756 static void create_function(struct nir_to_llvm_context *ctx,
757 gl_shader_stage stage,
758 bool has_previous_stage,
759 gl_shader_stage previous_stage)
760 {
761 uint8_t user_sgpr_idx;
762 struct user_sgpr_info user_sgpr_info;
763 struct arg_info args = {};
764 LLVMValueRef desc_sets;
765
766 allocate_user_sgprs(ctx, &user_sgpr_info);
767
768 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
769 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
770 &ctx->ring_offsets);
771 }
772
773 switch (stage) {
774 case MESA_SHADER_COMPUTE:
775 declare_global_input_sgprs(ctx, stage, has_previous_stage,
776 previous_stage, &user_sgpr_info,
777 &args, &desc_sets);
778
779 if (ctx->shader_info->info.cs.uses_grid_size) {
780 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
781 &ctx->num_work_groups);
782 }
783
784 for (int i = 0; i < 3; i++) {
785 ctx->workgroup_ids[i] = NULL;
786 if (ctx->shader_info->info.cs.uses_block_id[i]) {
787 add_arg(&args, ARG_SGPR, ctx->ac.i32,
788 &ctx->workgroup_ids[i]);
789 }
790 }
791
792 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
793 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
794 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
795 &ctx->local_invocation_ids);
796 break;
797 case MESA_SHADER_VERTEX:
798 declare_global_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &user_sgpr_info,
800 &args, &desc_sets);
801 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
802 previous_stage, &args);
803
804 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
806 if (ctx->options->key.vs.as_es)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->es2gs_offset);
809 else if (ctx->options->key.vs.as_ls)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->ls_out_layout);
812
813 declare_vs_input_vgprs(ctx, &args);
814 break;
815 case MESA_SHADER_TESS_CTRL:
816 if (has_previous_stage) {
817 // First 6 system regs
818 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->merged_wave_info);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->tess_factor_offset);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
825 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
826 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
827
828 declare_global_input_sgprs(ctx, stage,
829 has_previous_stage,
830 previous_stage,
831 &user_sgpr_info, &args,
832 &desc_sets);
833 declare_vs_specific_input_sgprs(ctx, stage,
834 has_previous_stage,
835 previous_stage, &args);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->ls_out_layout);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_offchip_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_out_offsets);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_in_layout);
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->view_index);
851
852 add_arg(&args, ARG_VGPR, ctx->ac.i32,
853 &ctx->tcs_patch_id);
854 add_arg(&args, ARG_VGPR, ctx->ac.i32,
855 &ctx->tcs_rel_ids);
856
857 declare_vs_input_vgprs(ctx, &args);
858 } else {
859 declare_global_input_sgprs(ctx, stage,
860 has_previous_stage,
861 previous_stage,
862 &user_sgpr_info, &args,
863 &desc_sets);
864
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_offchip_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_out_offsets);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_in_layout);
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->view_index);
876
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tess_factor_offset);
880 add_arg(&args, ARG_VGPR, ctx->ac.i32,
881 &ctx->tcs_patch_id);
882 add_arg(&args, ARG_VGPR, ctx->ac.i32,
883 &ctx->tcs_rel_ids);
884 }
885 break;
886 case MESA_SHADER_TESS_EVAL:
887 declare_global_input_sgprs(ctx, stage, has_previous_stage,
888 previous_stage, &user_sgpr_info,
889 &args, &desc_sets);
890
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
892 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
894
895 if (ctx->options->key.tes.as_es) {
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->es2gs_offset);
900 } else {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 }
904 declare_tes_input_vgprs(ctx, &args);
905 break;
906 case MESA_SHADER_GEOMETRY:
907 if (has_previous_stage) {
908 // First 6 system regs
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->gs2vs_offset);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->merged_wave_info);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
914
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918
919 declare_global_input_sgprs(ctx, stage,
920 has_previous_stage,
921 previous_stage,
922 &user_sgpr_info, &args,
923 &desc_sets);
924
925 if (previous_stage == MESA_SHADER_TESS_EVAL) {
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->tcs_offchip_layout);
928 } else {
929 declare_vs_specific_input_sgprs(ctx, stage,
930 has_previous_stage,
931 previous_stage,
932 &args);
933 }
934
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_ring_stride);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->gsvs_num_entries);
939 if (ctx->shader_info->info.needs_multiview_view_index)
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->view_index);
942
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[0]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[2]);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_prim_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->abi.gs_invocation_id);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[4]);
953
954 if (previous_stage == MESA_SHADER_VERTEX) {
955 declare_vs_input_vgprs(ctx, &args);
956 } else {
957 declare_tes_input_vgprs(ctx, &args);
958 }
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_ring_stride);
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->gsvs_num_entries);
970 if (ctx->shader_info->info.needs_multiview_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->view_index);
973
974 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
975 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[0]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[1]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_prim_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[2]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[3]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[5]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->abi.gs_invocation_id);
992 }
993 break;
994 case MESA_SHADER_FRAGMENT:
995 declare_global_input_sgprs(ctx, stage, has_previous_stage,
996 previous_stage, &user_sgpr_info,
997 &args, &desc_sets);
998
999 if (ctx->shader_info->info.ps.needs_sample_positions)
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1001 &ctx->sample_pos_offset);
1002
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1020 break;
1021 default:
1022 unreachable("Shader stage not implemented");
1023 }
1024
1025 ctx->main_function = create_llvm_function(
1026 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1027 ctx->max_workgroup_size,
1028 ctx->options->unsafe_math);
1029 set_llvm_calling_convention(ctx->main_function, stage);
1030
1031
1032 ctx->shader_info->num_input_vgprs = 0;
1033 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1034
1035 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1036
1037 if (ctx->stage != MESA_SHADER_FRAGMENT)
1038 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1039
1040 assign_arguments(ctx->main_function, &args);
1041
1042 user_sgpr_idx = 0;
1043
1044 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1045 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1046 &user_sgpr_idx, 2);
1047 if (ctx->options->supports_spill) {
1048 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1049 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1050 NULL, 0, AC_FUNC_ATTR_READNONE);
1051 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1052 const_array(ctx->ac.v4i32, 16), "");
1053 }
1054 }
1055
1056 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1057 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1058 if (has_previous_stage)
1059 user_sgpr_idx = 0;
1060
1061 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1062 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1063
1064 switch (stage) {
1065 case MESA_SHADER_COMPUTE:
1066 if (ctx->shader_info->info.cs.uses_grid_size) {
1067 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1068 &user_sgpr_idx, 3);
1069 }
1070 break;
1071 case MESA_SHADER_VERTEX:
1072 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1073 previous_stage, &user_sgpr_idx);
1074 if (ctx->view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 if (ctx->options->key.vs.as_ls) {
1077 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1078 &user_sgpr_idx, 1);
1079 }
1080 if (ctx->options->key.vs.as_ls)
1081 ac_declare_lds_as_pointer(&ctx->ac);
1082 break;
1083 case MESA_SHADER_TESS_CTRL:
1084 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1085 previous_stage, &user_sgpr_idx);
1086 if (has_previous_stage)
1087 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1088 &user_sgpr_idx, 1);
1089 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1090 if (ctx->view_index)
1091 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1092 ac_declare_lds_as_pointer(&ctx->ac);
1093 break;
1094 case MESA_SHADER_TESS_EVAL:
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 break;
1099 case MESA_SHADER_GEOMETRY:
1100 if (has_previous_stage) {
1101 if (previous_stage == MESA_SHADER_VERTEX)
1102 set_vs_specific_input_locs(ctx, stage,
1103 has_previous_stage,
1104 previous_stage,
1105 &user_sgpr_idx);
1106 else
1107 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1108 &user_sgpr_idx, 1);
1109 }
1110 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1111 &user_sgpr_idx, 2);
1112 if (ctx->view_index)
1113 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1114 if (has_previous_stage)
1115 ac_declare_lds_as_pointer(&ctx->ac);
1116 break;
1117 case MESA_SHADER_FRAGMENT:
1118 if (ctx->shader_info->info.ps.needs_sample_positions) {
1119 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1120 &user_sgpr_idx, 1);
1121 }
1122 break;
1123 default:
1124 unreachable("Shader stage not implemented");
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static int get_llvm_num_components(LLVMValueRef value)
1131 {
1132 LLVMTypeRef type = LLVMTypeOf(value);
1133 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1134 ? LLVMGetVectorSize(type)
1135 : 1;
1136 return num_components;
1137 }
1138
1139 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1140 LLVMValueRef value,
1141 int index)
1142 {
1143 int count = get_llvm_num_components(value);
1144
1145 if (count == 1)
1146 return value;
1147
1148 return LLVMBuildExtractElement(ac->builder, value,
1149 LLVMConstInt(ac->i32, index, false), "");
1150 }
1151
1152 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1153 LLVMValueRef value, unsigned count)
1154 {
1155 unsigned num_components = get_llvm_num_components(value);
1156 if (count == num_components)
1157 return value;
1158
1159 LLVMValueRef masks[] = {
1160 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1161 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1162
1163 if (count == 1)
1164 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1165 "");
1166
1167 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1168 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1169 }
1170
1171 static void
1172 build_store_values_extended(struct ac_llvm_context *ac,
1173 LLVMValueRef *values,
1174 unsigned value_count,
1175 unsigned value_stride,
1176 LLVMValueRef vec)
1177 {
1178 LLVMBuilderRef builder = ac->builder;
1179 unsigned i;
1180
1181 for (i = 0; i < value_count; i++) {
1182 LLVMValueRef ptr = values[i * value_stride];
1183 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1184 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1185 LLVMBuildStore(builder, value, ptr);
1186 }
1187 }
1188
1189 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1190 const nir_ssa_def *def)
1191 {
1192 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1193 if (def->num_components > 1) {
1194 type = LLVMVectorType(type, def->num_components);
1195 }
1196 return type;
1197 }
1198
1199 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1200 {
1201 assert(src.is_ssa);
1202 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1203 return (LLVMValueRef)entry->data;
1204 }
1205
1206
1207 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1208 const struct nir_block *b)
1209 {
1210 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1211 return (LLVMBasicBlockRef)entry->data;
1212 }
1213
1214 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1215 nir_alu_src src,
1216 unsigned num_components)
1217 {
1218 LLVMValueRef value = get_src(ctx, src.src);
1219 bool need_swizzle = false;
1220
1221 assert(value);
1222 LLVMTypeRef type = LLVMTypeOf(value);
1223 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1224 ? LLVMGetVectorSize(type)
1225 : 1;
1226
1227 for (unsigned i = 0; i < num_components; ++i) {
1228 assert(src.swizzle[i] < src_components);
1229 if (src.swizzle[i] != i)
1230 need_swizzle = true;
1231 }
1232
1233 if (need_swizzle || num_components != src_components) {
1234 LLVMValueRef masks[] = {
1235 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1236 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1237 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1238 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1239
1240 if (src_components > 1 && num_components == 1) {
1241 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1242 masks[0], "");
1243 } else if (src_components == 1 && num_components > 1) {
1244 LLVMValueRef values[] = {value, value, value, value};
1245 value = ac_build_gather_values(&ctx->ac, values, num_components);
1246 } else {
1247 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1248 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1249 swizzle, "");
1250 }
1251 }
1252 assert(!src.negate);
1253 assert(!src.abs);
1254 return value;
1255 }
1256
1257 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1258 LLVMIntPredicate pred, LLVMValueRef src0,
1259 LLVMValueRef src1)
1260 {
1261 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1262 return LLVMBuildSelect(ctx->builder, result,
1263 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1264 ctx->i32_0, "");
1265 }
1266
1267 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1268 LLVMRealPredicate pred, LLVMValueRef src0,
1269 LLVMValueRef src1)
1270 {
1271 LLVMValueRef result;
1272 src0 = ac_to_float(ctx, src0);
1273 src1 = ac_to_float(ctx, src1);
1274 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1275 return LLVMBuildSelect(ctx->builder, result,
1276 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1277 ctx->i32_0, "");
1278 }
1279
1280 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 };
1289
1290 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1291 get_elem_bits(ctx, result_type));
1292 assert(length < sizeof(name));
1293 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1294 }
1295
1296 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1297 const char *intrin,
1298 LLVMTypeRef result_type,
1299 LLVMValueRef src0, LLVMValueRef src1)
1300 {
1301 char name[64];
1302 LLVMValueRef params[] = {
1303 ac_to_float(ctx, src0),
1304 ac_to_float(ctx, src1),
1305 };
1306
1307 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1308 get_elem_bits(ctx, result_type));
1309 assert(length < sizeof(name));
1310 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1311 }
1312
1313 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1314 const char *intrin,
1315 LLVMTypeRef result_type,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 char name[64];
1319 LLVMValueRef params[] = {
1320 ac_to_float(ctx, src0),
1321 ac_to_float(ctx, src1),
1322 ac_to_float(ctx, src2),
1323 };
1324
1325 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1326 get_elem_bits(ctx, result_type));
1327 assert(length < sizeof(name));
1328 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1329 }
1330
1331 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1333 {
1334 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1335 ctx->i32_0, "");
1336 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1337 }
1338
1339 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1340 LLVMIntPredicate pred,
1341 LLVMValueRef src0, LLVMValueRef src1)
1342 {
1343 return LLVMBuildSelect(ctx->builder,
1344 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1345 src0,
1346 src1, "");
1347
1348 }
1349 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1350 LLVMValueRef src0)
1351 {
1352 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1353 LLVMBuildNeg(ctx->builder, src0, ""));
1354 }
1355
1356 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0)
1358 {
1359 LLVMValueRef cmp, val;
1360
1361 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1362 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1363 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1364 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1365 return val;
1366 }
1367
1368 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1369 LLVMValueRef src0)
1370 {
1371 LLVMValueRef cmp, val;
1372
1373 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1374 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1375 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1376 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1377 return val;
1378 }
1379
1380 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1381 LLVMValueRef src0)
1382 {
1383 const char *intr = "llvm.floor.f32";
1384 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1385 LLVMValueRef params[] = {
1386 fsrc0,
1387 };
1388 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1389 ctx->f32, params, 1,
1390 AC_FUNC_ATTR_READNONE);
1391 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1392 }
1393
1394 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1395 const char *intrin,
1396 LLVMValueRef src0, LLVMValueRef src1)
1397 {
1398 LLVMTypeRef ret_type;
1399 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1400 LLVMValueRef res;
1401 LLVMValueRef params[] = { src0, src1 };
1402 ret_type = LLVMStructTypeInContext(ctx->context, types,
1403 2, true);
1404
1405 res = ac_build_intrinsic(ctx, intrin, ret_type,
1406 params, 2, AC_FUNC_ATTR_READNONE);
1407
1408 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1409 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1410 return res;
1411 }
1412
1413 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1414 LLVMValueRef src0)
1415 {
1416 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1417 }
1418
1419 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 src0 = ac_to_float(ctx, src0);
1423 return LLVMBuildSExt(ctx->builder,
1424 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1425 ctx->i32, "");
1426 }
1427
1428 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1429 LLVMValueRef src0)
1430 {
1431 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1432 }
1433
1434 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildSExt(ctx->builder,
1438 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1439 ctx->i32, "");
1440 }
1441
1442 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1443 LLVMValueRef src0)
1444 {
1445 LLVMValueRef result;
1446 LLVMValueRef cond = NULL;
1447
1448 src0 = ac_to_float(&ctx->ac, src0);
1449 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1450
1451 if (ctx->options->chip_class >= VI) {
1452 LLVMValueRef args[2];
1453 /* Check if the result is a denormal - and flush to 0 if so. */
1454 args[0] = result;
1455 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1456 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1457 }
1458
1459 /* need to convert back up to f32 */
1460 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1461
1462 if (ctx->options->chip_class >= VI)
1463 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1464 else {
1465 /* for SI/CIK */
1466 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1467 * so compare the result and flush to 0 if it's smaller.
1468 */
1469 LLVMValueRef temp, cond2;
1470 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1471 ctx->ac.f32, result);
1472 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1473 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1474 temp, "");
1475 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1476 temp, ctx->ac.f32_0, "");
1477 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1478 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1479 }
1480 return result;
1481 }
1482
1483 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1484 LLVMValueRef src0, LLVMValueRef src1)
1485 {
1486 LLVMValueRef dst64, result;
1487 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1488 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1489
1490 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1491 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1492 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1510 bool is_signed,
1511 const LLVMValueRef srcs[3])
1512 {
1513 LLVMValueRef result;
1514 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1515
1516 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1517 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1522 LLVMValueRef src0, LLVMValueRef src1,
1523 LLVMValueRef src2, LLVMValueRef src3)
1524 {
1525 LLVMValueRef bfi_args[3], result;
1526
1527 bfi_args[0] = LLVMBuildShl(ctx->builder,
1528 LLVMBuildSub(ctx->builder,
1529 LLVMBuildShl(ctx->builder,
1530 ctx->i32_1,
1531 src3, ""),
1532 ctx->i32_1, ""),
1533 src2, "");
1534 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1535 bfi_args[2] = src0;
1536
1537 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1538
1539 /* Calculate:
1540 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1541 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1542 */
1543 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1544 LLVMBuildAnd(ctx->builder, bfi_args[0],
1545 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1546
1547 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1548 return result;
1549 }
1550
1551 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1552 LLVMValueRef src0)
1553 {
1554 LLVMValueRef comp[2];
1555
1556 src0 = ac_to_float(ctx, src0);
1557 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1558 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1559
1560 return ac_build_cvt_pkrtz_f16(ctx, comp);
1561 }
1562
1563 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0)
1565 {
1566 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1567 LLVMValueRef temps[2], result, val;
1568 int i;
1569
1570 for (i = 0; i < 2; i++) {
1571 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1572 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1573 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1574 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1575 }
1576
1577 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1578 ctx->i32_0, "");
1579 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1580 ctx->i32_1, "");
1581 return result;
1582 }
1583
1584 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1585 nir_op op,
1586 LLVMValueRef src0)
1587 {
1588 unsigned mask;
1589 int idx;
1590 LLVMValueRef result;
1591
1592 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1593 mask = AC_TID_MASK_LEFT;
1594 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1595 mask = AC_TID_MASK_TOP;
1596 else
1597 mask = AC_TID_MASK_TOP_LEFT;
1598
1599 /* for DDX we want to next X pixel, DDY next Y pixel. */
1600 if (op == nir_op_fddx_fine ||
1601 op == nir_op_fddx_coarse ||
1602 op == nir_op_fddx)
1603 idx = 1;
1604 else
1605 idx = 2;
1606
1607 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1608 return result;
1609 }
1610
1611 /*
1612 * this takes an I,J coordinate pair,
1613 * and works out the X and Y derivatives.
1614 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1615 */
1616 static LLVMValueRef emit_ddxy_interp(
1617 struct ac_nir_context *ctx,
1618 LLVMValueRef interp_ij)
1619 {
1620 LLVMValueRef result[4], a;
1621 unsigned i;
1622
1623 for (i = 0; i < 2; i++) {
1624 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1625 LLVMConstInt(ctx->ac.i32, i, false), "");
1626 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1627 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1628 }
1629 return ac_build_gather_values(&ctx->ac, result, 4);
1630 }
1631
1632 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1633 {
1634 LLVMValueRef src[4], result = NULL;
1635 unsigned num_components = instr->dest.dest.ssa.num_components;
1636 unsigned src_components;
1637 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1638
1639 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1640 switch (instr->op) {
1641 case nir_op_vec2:
1642 case nir_op_vec3:
1643 case nir_op_vec4:
1644 src_components = 1;
1645 break;
1646 case nir_op_pack_half_2x16:
1647 src_components = 2;
1648 break;
1649 case nir_op_unpack_half_2x16:
1650 src_components = 1;
1651 break;
1652 default:
1653 src_components = num_components;
1654 break;
1655 }
1656 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1657 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1658
1659 switch (instr->op) {
1660 case nir_op_fmov:
1661 case nir_op_imov:
1662 result = src[0];
1663 break;
1664 case nir_op_fneg:
1665 src[0] = ac_to_float(&ctx->ac, src[0]);
1666 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1667 break;
1668 case nir_op_ineg:
1669 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1670 break;
1671 case nir_op_inot:
1672 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1673 break;
1674 case nir_op_iadd:
1675 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_fadd:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 src[1] = ac_to_float(&ctx->ac, src[1]);
1680 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1681 break;
1682 case nir_op_fsub:
1683 src[0] = ac_to_float(&ctx->ac, src[0]);
1684 src[1] = ac_to_float(&ctx->ac, src[1]);
1685 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_isub:
1688 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_imul:
1691 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_imod:
1694 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_umod:
1697 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fmod:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1704 ac_to_float_type(&ctx->ac, def_type), result);
1705 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1706 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1707 break;
1708 case nir_op_frem:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_irem:
1714 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_idiv:
1717 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_udiv:
1720 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_fmul:
1723 src[0] = ac_to_float(&ctx->ac, src[0]);
1724 src[1] = ac_to_float(&ctx->ac, src[1]);
1725 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_fdiv:
1728 src[0] = ac_to_float(&ctx->ac, src[0]);
1729 src[1] = ac_to_float(&ctx->ac, src[1]);
1730 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1731 break;
1732 case nir_op_frcp:
1733 src[0] = ac_to_float(&ctx->ac, src[0]);
1734 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1735 break;
1736 case nir_op_iand:
1737 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_ior:
1740 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_ixor:
1743 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_ishl:
1746 result = LLVMBuildShl(ctx->ac.builder, src[0],
1747 LLVMBuildZExt(ctx->ac.builder, src[1],
1748 LLVMTypeOf(src[0]), ""),
1749 "");
1750 break;
1751 case nir_op_ishr:
1752 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1753 LLVMBuildZExt(ctx->ac.builder, src[1],
1754 LLVMTypeOf(src[0]), ""),
1755 "");
1756 break;
1757 case nir_op_ushr:
1758 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1759 LLVMBuildZExt(ctx->ac.builder, src[1],
1760 LLVMTypeOf(src[0]), ""),
1761 "");
1762 break;
1763 case nir_op_ilt:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1765 break;
1766 case nir_op_ine:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1768 break;
1769 case nir_op_ieq:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1771 break;
1772 case nir_op_ige:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1774 break;
1775 case nir_op_ult:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1777 break;
1778 case nir_op_uge:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1780 break;
1781 case nir_op_feq:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1783 break;
1784 case nir_op_fne:
1785 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1786 break;
1787 case nir_op_flt:
1788 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1789 break;
1790 case nir_op_fge:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1792 break;
1793 case nir_op_fabs:
1794 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1795 ac_to_float_type(&ctx->ac, def_type), src[0]);
1796 break;
1797 case nir_op_iabs:
1798 result = emit_iabs(&ctx->ac, src[0]);
1799 break;
1800 case nir_op_imax:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1802 break;
1803 case nir_op_imin:
1804 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1805 break;
1806 case nir_op_umax:
1807 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1808 break;
1809 case nir_op_umin:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1811 break;
1812 case nir_op_isign:
1813 result = emit_isign(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fsign:
1816 src[0] = ac_to_float(&ctx->ac, src[0]);
1817 result = emit_fsign(&ctx->ac, src[0]);
1818 break;
1819 case nir_op_ffloor:
1820 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1821 ac_to_float_type(&ctx->ac, def_type), src[0]);
1822 break;
1823 case nir_op_ftrunc:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fceil:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_fround_even:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1833 ac_to_float_type(&ctx->ac, def_type),src[0]);
1834 break;
1835 case nir_op_ffract:
1836 result = emit_ffract(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_fsin:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_fcos:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 break;
1846 case nir_op_fsqrt:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1848 ac_to_float_type(&ctx->ac, def_type), src[0]);
1849 break;
1850 case nir_op_fexp2:
1851 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1852 ac_to_float_type(&ctx->ac, def_type), src[0]);
1853 break;
1854 case nir_op_flog2:
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1856 ac_to_float_type(&ctx->ac, def_type), src[0]);
1857 break;
1858 case nir_op_frsq:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1862 break;
1863 case nir_op_fpow:
1864 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1865 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1866 break;
1867 case nir_op_fmax:
1868 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1869 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1870 if (instr->dest.dest.ssa.bit_size == 32)
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1872 ac_to_float_type(&ctx->ac, def_type),
1873 result);
1874 break;
1875 case nir_op_fmin:
1876 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1877 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1878 if (instr->dest.dest.ssa.bit_size == 32)
1879 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1880 ac_to_float_type(&ctx->ac, def_type),
1881 result);
1882 break;
1883 case nir_op_ffma:
1884 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1885 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1886 break;
1887 case nir_op_ibitfield_extract:
1888 result = emit_bitfield_extract(&ctx->ac, true, src);
1889 break;
1890 case nir_op_ubitfield_extract:
1891 result = emit_bitfield_extract(&ctx->ac, false, src);
1892 break;
1893 case nir_op_bitfield_insert:
1894 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1895 break;
1896 case nir_op_bitfield_reverse:
1897 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1898 break;
1899 case nir_op_bit_count:
1900 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1901 break;
1902 case nir_op_vec2:
1903 case nir_op_vec3:
1904 case nir_op_vec4:
1905 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1906 src[i] = ac_to_integer(&ctx->ac, src[i]);
1907 result = ac_build_gather_values(&ctx->ac, src, num_components);
1908 break;
1909 case nir_op_f2i32:
1910 case nir_op_f2i64:
1911 src[0] = ac_to_float(&ctx->ac, src[0]);
1912 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1913 break;
1914 case nir_op_f2u32:
1915 case nir_op_f2u64:
1916 src[0] = ac_to_float(&ctx->ac, src[0]);
1917 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2f32:
1920 case nir_op_i2f64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1923 break;
1924 case nir_op_u2f32:
1925 case nir_op_u2f64:
1926 src[0] = ac_to_integer(&ctx->ac, src[0]);
1927 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1928 break;
1929 case nir_op_f2f64:
1930 src[0] = ac_to_float(&ctx->ac, src[0]);
1931 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1932 break;
1933 case nir_op_f2f32:
1934 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1935 break;
1936 case nir_op_u2u32:
1937 case nir_op_u2u64:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1940 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1941 else
1942 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1943 break;
1944 case nir_op_i2i32:
1945 case nir_op_i2i64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1948 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1949 else
1950 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1951 break;
1952 case nir_op_bcsel:
1953 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1954 break;
1955 case nir_op_find_lsb:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1958 break;
1959 case nir_op_ufind_msb:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1962 break;
1963 case nir_op_ifind_msb:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1966 break;
1967 case nir_op_uadd_carry:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 src[1] = ac_to_integer(&ctx->ac, src[1]);
1970 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1971 break;
1972 case nir_op_usub_borrow:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 src[1] = ac_to_integer(&ctx->ac, src[1]);
1975 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1976 break;
1977 case nir_op_b2f:
1978 result = emit_b2f(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_f2b:
1981 result = emit_f2b(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_b2i:
1984 result = emit_b2i(&ctx->ac, src[0]);
1985 break;
1986 case nir_op_i2b:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = emit_i2b(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_fquantize2f16:
1991 result = emit_f2f16(ctx->nctx, src[0]);
1992 break;
1993 case nir_op_umul_high:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1997 break;
1998 case nir_op_imul_high:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 src[1] = ac_to_integer(&ctx->ac, src[1]);
2001 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2002 break;
2003 case nir_op_pack_half_2x16:
2004 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_unpack_half_2x16:
2007 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2008 break;
2009 case nir_op_fddx:
2010 case nir_op_fddy:
2011 case nir_op_fddx_fine:
2012 case nir_op_fddy_fine:
2013 case nir_op_fddx_coarse:
2014 case nir_op_fddy_coarse:
2015 result = emit_ddxy(ctx, instr->op, src[0]);
2016 break;
2017
2018 case nir_op_unpack_64_2x32_split_x: {
2019 assert(instr->src[0].src.ssa->num_components == 1);
2020 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2021 ctx->ac.v2i32,
2022 "");
2023 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2024 ctx->ac.i32_0, "");
2025 break;
2026 }
2027
2028 case nir_op_unpack_64_2x32_split_y: {
2029 assert(instr->src[0].src.ssa->num_components == 1);
2030 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2031 ctx->ac.v2i32,
2032 "");
2033 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2034 ctx->ac.i32_1, "");
2035 break;
2036 }
2037
2038 case nir_op_pack_64_2x32_split: {
2039 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2040 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2041 src[0], ctx->ac.i32_0, "");
2042 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2043 src[1], ctx->ac.i32_1, "");
2044 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2045 break;
2046 }
2047
2048 default:
2049 fprintf(stderr, "Unknown NIR alu instr: ");
2050 nir_print_instr(&instr->instr, stderr);
2051 fprintf(stderr, "\n");
2052 abort();
2053 }
2054
2055 if (result) {
2056 assert(instr->dest.dest.is_ssa);
2057 result = ac_to_integer(&ctx->ac, result);
2058 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2059 result);
2060 }
2061 }
2062
2063 static void visit_load_const(struct ac_nir_context *ctx,
2064 const nir_load_const_instr *instr)
2065 {
2066 LLVMValueRef values[4], value = NULL;
2067 LLVMTypeRef element_type =
2068 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2069
2070 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2071 switch (instr->def.bit_size) {
2072 case 32:
2073 values[i] = LLVMConstInt(element_type,
2074 instr->value.u32[i], false);
2075 break;
2076 case 64:
2077 values[i] = LLVMConstInt(element_type,
2078 instr->value.u64[i], false);
2079 break;
2080 default:
2081 fprintf(stderr,
2082 "unsupported nir load_const bit_size: %d\n",
2083 instr->def.bit_size);
2084 abort();
2085 }
2086 }
2087 if (instr->def.num_components > 1) {
2088 value = LLVMConstVector(values, instr->def.num_components);
2089 } else
2090 value = values[0];
2091
2092 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2093 }
2094
2095 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2096 LLVMTypeRef type)
2097 {
2098 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2099 return LLVMBuildBitCast(ctx->builder, ptr,
2100 LLVMPointerType(type, addr_space), "");
2101 }
2102
2103 static LLVMValueRef
2104 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2105 {
2106 LLVMValueRef size =
2107 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2108 LLVMConstInt(ctx->ac.i32, 2, false), "");
2109
2110 /* VI only */
2111 if (ctx->ac.chip_class == VI && in_elements) {
2112 /* On VI, the descriptor contains the size in bytes,
2113 * but TXQ must return the size in elements.
2114 * The stride is always non-zero for resources using TXQ.
2115 */
2116 LLVMValueRef stride =
2117 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2118 ctx->ac.i32_1, "");
2119 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2120 LLVMConstInt(ctx->ac.i32, 16, false), "");
2121 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2122 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2123
2124 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2125 }
2126 return size;
2127 }
2128
2129 /**
2130 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2131 * intrinsic names).
2132 */
2133 static void build_int_type_name(
2134 LLVMTypeRef type,
2135 char *buf, unsigned bufsize)
2136 {
2137 assert(bufsize >= 6);
2138
2139 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2140 snprintf(buf, bufsize, "v%ui32",
2141 LLVMGetVectorSize(type));
2142 else
2143 strcpy(buf, "i32");
2144 }
2145
2146 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2147 struct ac_image_args *args,
2148 const nir_tex_instr *instr)
2149 {
2150 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2151 LLVMValueRef coord = args->addr;
2152 LLVMValueRef half_texel[2];
2153 LLVMValueRef compare_cube_wa = NULL;
2154 LLVMValueRef result;
2155 int c;
2156 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2157
2158 //TODO Rect
2159 {
2160 struct ac_image_args txq_args = { 0 };
2161
2162 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2163 txq_args.opcode = ac_image_get_resinfo;
2164 txq_args.dmask = 0xf;
2165 txq_args.addr = ctx->i32_0;
2166 txq_args.resource = args->resource;
2167 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2168
2169 for (c = 0; c < 2; c++) {
2170 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2171 LLVMConstInt(ctx->i32, c, false), "");
2172 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2173 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2174 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2175 LLVMConstReal(ctx->f32, -0.5), "");
2176 }
2177 }
2178
2179 LLVMValueRef orig_coords = args->addr;
2180
2181 for (c = 0; c < 2; c++) {
2182 LLVMValueRef tmp;
2183 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2184 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2185 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2186 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2187 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2188 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2189 }
2190
2191
2192 /*
2193 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2194 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2195 * workaround by sampling using a scaled type and converting.
2196 * This is taken from amdgpu-pro shaders.
2197 */
2198 /* NOTE this produces some ugly code compared to amdgpu-pro,
2199 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2200 * and then reads them back. -pro generates two selects,
2201 * one s_cmp for the descriptor rewriting
2202 * one v_cmp for the coordinate and result changes.
2203 */
2204 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2205 LLVMValueRef tmp, tmp2;
2206
2207 /* workaround 8/8/8/8 uint/sint cube gather bug */
2208 /* first detect it then change to a scaled read and f2i */
2209 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2210 tmp2 = tmp;
2211
2212 /* extract the DATA_FORMAT */
2213 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2214 LLVMConstInt(ctx->i32, 6, false), false);
2215
2216 /* is the DATA_FORMAT == 8_8_8_8 */
2217 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2218
2219 if (stype == GLSL_TYPE_UINT)
2220 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2221 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2222 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2223 else
2224 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2225 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2226 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2227
2228 /* replace the NUM FORMAT in the descriptor */
2229 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2230 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2231
2232 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2233
2234 /* don't modify the coordinates for this case */
2235 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2236 }
2237 args->addr = coord;
2238 result = ac_build_image_opcode(ctx, args);
2239
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2241 LLVMValueRef tmp, tmp2;
2242
2243 /* if the cube workaround is in place, f2i the result. */
2244 for (c = 0; c < 4; c++) {
2245 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2246 if (stype == GLSL_TYPE_UINT)
2247 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2248 else
2249 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2250 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2251 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2252 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2253 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2254 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2255 }
2256 }
2257 return result;
2258 }
2259
2260 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2261 const nir_tex_instr *instr,
2262 bool lod_is_zero,
2263 struct ac_image_args *args)
2264 {
2265 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2266 return ac_build_buffer_load_format(&ctx->ac,
2267 args->resource,
2268 args->addr,
2269 ctx->ac.i32_0,
2270 true);
2271 }
2272
2273 args->opcode = ac_image_sample;
2274 args->compare = instr->is_shadow;
2275
2276 switch (instr->op) {
2277 case nir_texop_txf:
2278 case nir_texop_txf_ms:
2279 case nir_texop_samples_identical:
2280 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2281 args->compare = false;
2282 args->offset = false;
2283 break;
2284 case nir_texop_txb:
2285 args->bias = true;
2286 break;
2287 case nir_texop_txl:
2288 if (lod_is_zero)
2289 args->level_zero = true;
2290 else
2291 args->lod = true;
2292 break;
2293 case nir_texop_txs:
2294 case nir_texop_query_levels:
2295 args->opcode = ac_image_get_resinfo;
2296 break;
2297 case nir_texop_tex:
2298 if (ctx->stage != MESA_SHADER_FRAGMENT)
2299 args->level_zero = true;
2300 break;
2301 case nir_texop_txd:
2302 args->deriv = true;
2303 break;
2304 case nir_texop_tg4:
2305 args->opcode = ac_image_gather4;
2306 args->level_zero = true;
2307 break;
2308 case nir_texop_lod:
2309 args->opcode = ac_image_get_lod;
2310 args->compare = false;
2311 args->offset = false;
2312 break;
2313 default:
2314 break;
2315 }
2316
2317 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2318 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2319 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2320 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2321 }
2322 }
2323 return ac_build_image_opcode(&ctx->ac, args);
2324 }
2325
2326 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2327 nir_intrinsic_instr *instr)
2328 {
2329 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2330 unsigned desc_set = nir_intrinsic_desc_set(instr);
2331 unsigned binding = nir_intrinsic_binding(instr);
2332 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2333 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2334 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2335 unsigned base_offset = layout->binding[binding].offset;
2336 LLVMValueRef offset, stride;
2337
2338 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2339 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2340 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2341 layout->binding[binding].dynamic_offset_offset;
2342 desc_ptr = ctx->push_constants;
2343 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2344 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2345 } else
2346 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2347
2348 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2349 index = LLVMBuildMul(ctx->builder, index, stride, "");
2350 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2351
2352 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2353 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2354 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2355
2356 return desc_ptr;
2357 }
2358
2359 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2360 nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2363 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2364
2365 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2366 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2367 return result;
2368 }
2369
2370 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2371 nir_intrinsic_instr *instr)
2372 {
2373 LLVMValueRef ptr, addr;
2374
2375 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2376 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2377
2378 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2379 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2380
2381 return LLVMBuildLoad(ctx->builder, ptr, "");
2382 }
2383
2384 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2388
2389 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2390 }
2391 static void visit_store_ssbo(struct ac_nir_context *ctx,
2392 nir_intrinsic_instr *instr)
2393 {
2394 const char *store_name;
2395 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2396 LLVMTypeRef data_type = ctx->ac.f32;
2397 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2398 int components_32bit = elem_size_mult * instr->num_components;
2399 unsigned writemask = nir_intrinsic_write_mask(instr);
2400 LLVMValueRef base_data, base_offset;
2401 LLVMValueRef params[6];
2402
2403 params[1] = ctx->abi->load_ssbo(ctx->abi,
2404 get_src(ctx, instr->src[1]), true);
2405 params[2] = ctx->ac.i32_0; /* vindex */
2406 params[4] = ctx->ac.i1false; /* glc */
2407 params[5] = ctx->ac.i1false; /* slc */
2408
2409 if (components_32bit > 1)
2410 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2411
2412 base_data = ac_to_float(&ctx->ac, src_data);
2413 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2414 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2415 data_type, "");
2416 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2417 while (writemask) {
2418 int start, count;
2419 LLVMValueRef data;
2420 LLVMValueRef offset;
2421 LLVMValueRef tmp;
2422 u_bit_scan_consecutive_range(&writemask, &start, &count);
2423
2424 /* Due to an LLVM limitation, split 3-element writes
2425 * into a 2-element and a 1-element write. */
2426 if (count == 3) {
2427 writemask |= 1 << (start + 2);
2428 count = 2;
2429 }
2430
2431 start *= elem_size_mult;
2432 count *= elem_size_mult;
2433
2434 if (count > 4) {
2435 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2436 count = 4;
2437 }
2438
2439 if (count == 4) {
2440 store_name = "llvm.amdgcn.buffer.store.v4f32";
2441 data = base_data;
2442 } else if (count == 2) {
2443 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2444 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2445 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2446 ctx->ac.i32_0, "");
2447
2448 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2449 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2450 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2451 ctx->ac.i32_1, "");
2452 store_name = "llvm.amdgcn.buffer.store.v2f32";
2453
2454 } else {
2455 assert(count == 1);
2456 if (get_llvm_num_components(base_data) > 1)
2457 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2458 LLVMConstInt(ctx->ac.i32, start, false), "");
2459 else
2460 data = base_data;
2461 store_name = "llvm.amdgcn.buffer.store.f32";
2462 }
2463
2464 offset = base_offset;
2465 if (start != 0) {
2466 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2467 }
2468 params[0] = data;
2469 params[3] = offset;
2470 ac_build_intrinsic(&ctx->ac, store_name,
2471 ctx->ac.voidt, params, 6, 0);
2472 }
2473 }
2474
2475 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 const char *name;
2479 LLVMValueRef params[6];
2480 int arg_count = 0;
2481
2482 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2483 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2484 }
2485 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2486 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2487 get_src(ctx, instr->src[0]),
2488 true);
2489 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2490 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2491 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2492
2493 switch (instr->intrinsic) {
2494 case nir_intrinsic_ssbo_atomic_add:
2495 name = "llvm.amdgcn.buffer.atomic.add";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_imin:
2498 name = "llvm.amdgcn.buffer.atomic.smin";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_umin:
2501 name = "llvm.amdgcn.buffer.atomic.umin";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_imax:
2504 name = "llvm.amdgcn.buffer.atomic.smax";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_umax:
2507 name = "llvm.amdgcn.buffer.atomic.umax";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_and:
2510 name = "llvm.amdgcn.buffer.atomic.and";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_or:
2513 name = "llvm.amdgcn.buffer.atomic.or";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_xor:
2516 name = "llvm.amdgcn.buffer.atomic.xor";
2517 break;
2518 case nir_intrinsic_ssbo_atomic_exchange:
2519 name = "llvm.amdgcn.buffer.atomic.swap";
2520 break;
2521 case nir_intrinsic_ssbo_atomic_comp_swap:
2522 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2523 break;
2524 default:
2525 abort();
2526 }
2527
2528 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2529 }
2530
2531 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2532 const nir_intrinsic_instr *instr)
2533 {
2534 LLVMValueRef results[2];
2535 int load_components;
2536 int num_components = instr->num_components;
2537 if (instr->dest.ssa.bit_size == 64)
2538 num_components *= 2;
2539
2540 for (int i = 0; i < num_components; i += load_components) {
2541 load_components = MIN2(num_components - i, 4);
2542 const char *load_name;
2543 LLVMTypeRef data_type = ctx->ac.f32;
2544 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2545 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2546
2547 if (load_components == 3)
2548 data_type = LLVMVectorType(ctx->ac.f32, 4);
2549 else if (load_components > 1)
2550 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2551
2552 if (load_components >= 3)
2553 load_name = "llvm.amdgcn.buffer.load.v4f32";
2554 else if (load_components == 2)
2555 load_name = "llvm.amdgcn.buffer.load.v2f32";
2556 else if (load_components == 1)
2557 load_name = "llvm.amdgcn.buffer.load.f32";
2558 else
2559 unreachable("unhandled number of components");
2560
2561 LLVMValueRef params[] = {
2562 ctx->abi->load_ssbo(ctx->abi,
2563 get_src(ctx, instr->src[0]),
2564 false),
2565 ctx->ac.i32_0,
2566 offset,
2567 ctx->ac.i1false,
2568 ctx->ac.i1false,
2569 };
2570
2571 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2572
2573 }
2574
2575 assume(results[0]);
2576 LLVMValueRef ret = results[0];
2577 if (num_components > 4 || num_components == 3) {
2578 LLVMValueRef masks[] = {
2579 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2580 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2581 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2582 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2583 };
2584
2585 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2586 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2587 results[num_components > 4 ? 1 : 0], swizzle, "");
2588 }
2589
2590 return LLVMBuildBitCast(ctx->ac.builder, ret,
2591 get_def_type(ctx, &instr->dest.ssa), "");
2592 }
2593
2594 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2595 const nir_intrinsic_instr *instr)
2596 {
2597 LLVMValueRef results[8], ret;
2598 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2599 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2600 int num_components = instr->num_components;
2601
2602 if (ctx->abi->load_ubo)
2603 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2604
2605 if (instr->dest.ssa.bit_size == 64)
2606 num_components *= 2;
2607
2608 for (unsigned i = 0; i < num_components; ++i) {
2609 LLVMValueRef params[] = {
2610 rsrc,
2611 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2612 offset, "")
2613 };
2614 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2615 params, 2,
2616 AC_FUNC_ATTR_READNONE |
2617 AC_FUNC_ATTR_LEGACY);
2618 }
2619
2620
2621 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2622 return LLVMBuildBitCast(ctx->ac.builder, ret,
2623 get_def_type(ctx, &instr->dest.ssa), "");
2624 }
2625
2626 static void
2627 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2628 bool vs_in, unsigned *vertex_index_out,
2629 LLVMValueRef *vertex_index_ref,
2630 unsigned *const_out, LLVMValueRef *indir_out)
2631 {
2632 unsigned const_offset = 0;
2633 nir_deref *tail = &deref->deref;
2634 LLVMValueRef offset = NULL;
2635
2636 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2637 tail = tail->child;
2638 nir_deref_array *deref_array = nir_deref_as_array(tail);
2639 if (vertex_index_out)
2640 *vertex_index_out = deref_array->base_offset;
2641
2642 if (vertex_index_ref) {
2643 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2644 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2645 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2646 }
2647 *vertex_index_ref = vtx;
2648 }
2649 }
2650
2651 if (deref->var->data.compact) {
2652 assert(tail->child->deref_type == nir_deref_type_array);
2653 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2654 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2655 /* We always lower indirect dereferences for "compact" array vars. */
2656 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2657
2658 const_offset = deref_array->base_offset;
2659 goto out;
2660 }
2661
2662 while (tail->child != NULL) {
2663 const struct glsl_type *parent_type = tail->type;
2664 tail = tail->child;
2665
2666 if (tail->deref_type == nir_deref_type_array) {
2667 nir_deref_array *deref_array = nir_deref_as_array(tail);
2668 LLVMValueRef index, stride, local_offset;
2669 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2670
2671 const_offset += size * deref_array->base_offset;
2672 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2673 continue;
2674
2675 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2676 index = get_src(ctx, deref_array->indirect);
2677 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2678 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2679
2680 if (offset)
2681 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2682 else
2683 offset = local_offset;
2684 } else if (tail->deref_type == nir_deref_type_struct) {
2685 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2686
2687 for (unsigned i = 0; i < deref_struct->index; i++) {
2688 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2689 const_offset += glsl_count_attribute_slots(ft, vs_in);
2690 }
2691 } else
2692 unreachable("unsupported deref type");
2693
2694 }
2695 out:
2696 if (const_offset && offset)
2697 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2698 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2699 "");
2700
2701 *const_out = const_offset;
2702 *indir_out = offset;
2703 }
2704
2705
2706 /* The offchip buffer layout for TCS->TES is
2707 *
2708 * - attribute 0 of patch 0 vertex 0
2709 * - attribute 0 of patch 0 vertex 1
2710 * - attribute 0 of patch 0 vertex 2
2711 * ...
2712 * - attribute 0 of patch 1 vertex 0
2713 * - attribute 0 of patch 1 vertex 1
2714 * ...
2715 * - attribute 1 of patch 0 vertex 0
2716 * - attribute 1 of patch 0 vertex 1
2717 * ...
2718 * - per patch attribute 0 of patch 0
2719 * - per patch attribute 0 of patch 1
2720 * ...
2721 *
2722 * Note that every attribute has 4 components.
2723 */
2724 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2725 LLVMValueRef vertex_index,
2726 LLVMValueRef param_index)
2727 {
2728 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2729 LLVMValueRef param_stride, constant16;
2730 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2731
2732 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2733 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2734 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2735 num_patches, "");
2736
2737 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2738 if (vertex_index) {
2739 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2740 vertices_per_patch, "");
2741
2742 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2743 vertex_index, "");
2744
2745 param_stride = total_vertices;
2746 } else {
2747 base_addr = rel_patch_id;
2748 param_stride = num_patches;
2749 }
2750
2751 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2752 LLVMBuildMul(ctx->builder, param_index,
2753 param_stride, ""), "");
2754
2755 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2756
2757 if (!vertex_index) {
2758 LLVMValueRef patch_data_offset =
2759 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2760
2761 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2762 patch_data_offset, "");
2763 }
2764 return base_addr;
2765 }
2766
2767 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2768 unsigned param,
2769 unsigned const_index,
2770 bool is_compact,
2771 LLVMValueRef vertex_index,
2772 LLVMValueRef indir_index)
2773 {
2774 LLVMValueRef param_index;
2775
2776 if (indir_index)
2777 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2778 indir_index, "");
2779 else {
2780 if (const_index && !is_compact)
2781 param += const_index;
2782 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2783 }
2784 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2785 }
2786
2787 static void
2788 mark_tess_output(struct nir_to_llvm_context *ctx,
2789 bool is_patch, uint32_t param)
2790
2791 {
2792 if (is_patch) {
2793 ctx->tess_patch_outputs_written |= (1ull << param);
2794 } else
2795 ctx->tess_outputs_written |= (1ull << param);
2796 }
2797
2798 static LLVMValueRef
2799 get_dw_address(struct nir_to_llvm_context *ctx,
2800 LLVMValueRef dw_addr,
2801 unsigned param,
2802 unsigned const_index,
2803 bool compact_const_index,
2804 LLVMValueRef vertex_index,
2805 LLVMValueRef stride,
2806 LLVMValueRef indir_index)
2807
2808 {
2809
2810 if (vertex_index) {
2811 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2812 LLVMBuildMul(ctx->builder,
2813 vertex_index,
2814 stride, ""), "");
2815 }
2816
2817 if (indir_index)
2818 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2819 LLVMBuildMul(ctx->builder, indir_index,
2820 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2821 else if (const_index && !compact_const_index)
2822 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2823 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2824
2825 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2826 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2827
2828 if (const_index && compact_const_index)
2829 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2830 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2831 return dw_addr;
2832 }
2833
2834 static LLVMValueRef
2835 load_tcs_input(struct nir_to_llvm_context *ctx,
2836 nir_intrinsic_instr *instr)
2837 {
2838 LLVMValueRef dw_addr, stride;
2839 unsigned const_index;
2840 LLVMValueRef vertex_index;
2841 LLVMValueRef indir_index;
2842 unsigned param;
2843 LLVMValueRef value[4], result;
2844 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2845 const bool is_compact = instr->variables[0]->var->data.compact;
2846 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2847 get_deref_offset(ctx->nir, instr->variables[0],
2848 false, NULL, per_vertex ? &vertex_index : NULL,
2849 &const_index, &indir_index);
2850
2851 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2852 dw_addr = get_tcs_in_current_patch_offset(ctx);
2853 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2854 indir_index);
2855
2856 unsigned comp = instr->variables[0]->var->data.location_frac;
2857 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2858 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2859 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2860 ctx->ac.i32_1, "");
2861 }
2862 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2863 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2864 return result;
2865 }
2866
2867 static LLVMValueRef
2868 load_tcs_output(struct nir_to_llvm_context *ctx,
2869 nir_intrinsic_instr *instr)
2870 {
2871 LLVMValueRef dw_addr;
2872 LLVMValueRef stride = NULL;
2873 LLVMValueRef value[4], result;
2874 LLVMValueRef vertex_index = NULL;
2875 LLVMValueRef indir_index = NULL;
2876 unsigned const_index = 0;
2877 unsigned param;
2878 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2879 const bool is_compact = instr->variables[0]->var->data.compact;
2880 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2881 get_deref_offset(ctx->nir, instr->variables[0],
2882 false, NULL, per_vertex ? &vertex_index : NULL,
2883 &const_index, &indir_index);
2884
2885 if (!instr->variables[0]->var->data.patch) {
2886 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2887 dw_addr = get_tcs_out_current_patch_offset(ctx);
2888 } else {
2889 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2890 }
2891
2892 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2893 indir_index);
2894
2895 unsigned comp = instr->variables[0]->var->data.location_frac;
2896 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2897 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2898 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2899 ctx->ac.i32_1, "");
2900 }
2901 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2902 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2903 return result;
2904 }
2905
2906 static void
2907 store_tcs_output(struct nir_to_llvm_context *ctx,
2908 nir_intrinsic_instr *instr,
2909 LLVMValueRef src,
2910 unsigned writemask)
2911 {
2912 LLVMValueRef dw_addr;
2913 LLVMValueRef stride = NULL;
2914 LLVMValueRef buf_addr = NULL;
2915 LLVMValueRef vertex_index = NULL;
2916 LLVMValueRef indir_index = NULL;
2917 unsigned const_index = 0;
2918 unsigned param;
2919 const unsigned comp = instr->variables[0]->var->data.location_frac;
2920 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2921 const bool is_compact = instr->variables[0]->var->data.compact;
2922 bool store_lds = true;
2923
2924 if (instr->variables[0]->var->data.patch) {
2925 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2926 store_lds = false;
2927 } else {
2928 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2929 store_lds = false;
2930 }
2931 get_deref_offset(ctx->nir, instr->variables[0],
2932 false, NULL, per_vertex ? &vertex_index : NULL,
2933 &const_index, &indir_index);
2934
2935 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2936 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2937 is_compact && const_index > 3) {
2938 const_index -= 3;
2939 param++;
2940 }
2941
2942 if (!instr->variables[0]->var->data.patch) {
2943 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2944 dw_addr = get_tcs_out_current_patch_offset(ctx);
2945 } else {
2946 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2947 }
2948
2949 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2950
2951 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2952 indir_index);
2953 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2954 vertex_index, indir_index);
2955
2956 bool is_tess_factor = false;
2957 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2958 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2959 is_tess_factor = true;
2960
2961 unsigned base = is_compact ? const_index : 0;
2962 for (unsigned chan = 0; chan < 8; chan++) {
2963 if (!(writemask & (1 << chan)))
2964 continue;
2965 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2966
2967 if (store_lds || is_tess_factor)
2968 ac_lds_store(&ctx->ac, dw_addr, value);
2969
2970 if (!is_tess_factor && writemask != 0xF)
2971 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2972 buf_addr, ctx->oc_lds,
2973 4 * (base + chan), 1, 0, true, false);
2974
2975 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2976 ctx->ac.i32_1, "");
2977 }
2978
2979 if (writemask == 0xF) {
2980 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2981 buf_addr, ctx->oc_lds,
2982 (base * 4), 1, 0, true, false);
2983 }
2984 }
2985
2986 static LLVMValueRef
2987 load_tes_input(struct nir_to_llvm_context *ctx,
2988 const nir_intrinsic_instr *instr)
2989 {
2990 LLVMValueRef buf_addr;
2991 LLVMValueRef result;
2992 LLVMValueRef vertex_index = NULL;
2993 LLVMValueRef indir_index = NULL;
2994 unsigned const_index = 0;
2995 unsigned param;
2996 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2997 const bool is_compact = instr->variables[0]->var->data.compact;
2998
2999 get_deref_offset(ctx->nir, instr->variables[0],
3000 false, NULL, per_vertex ? &vertex_index : NULL,
3001 &const_index, &indir_index);
3002 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
3003 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
3004 is_compact && const_index > 3) {
3005 const_index -= 3;
3006 param++;
3007 }
3008
3009 unsigned comp = instr->variables[0]->var->data.location_frac;
3010 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3011 is_compact, vertex_index, indir_index);
3012
3013 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
3014 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3015
3016 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
3017 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3018 result = trim_vector(&ctx->ac, result, instr->num_components);
3019 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
3020 return result;
3021 }
3022
3023 static LLVMValueRef
3024 load_gs_input(struct ac_shader_abi *abi,
3025 unsigned location,
3026 unsigned driver_location,
3027 unsigned component,
3028 unsigned num_components,
3029 unsigned vertex_index,
3030 unsigned const_index,
3031 LLVMTypeRef type)
3032 {
3033 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3034 LLVMValueRef vtx_offset;
3035 LLVMValueRef args[9];
3036 unsigned param, vtx_offset_param;
3037 LLVMValueRef value[4], result;
3038
3039 vtx_offset_param = vertex_index;
3040 assert(vtx_offset_param < 6);
3041 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3042 LLVMConstInt(ctx->ac.i32, 4, false), "");
3043
3044 param = shader_io_get_unique_index(location);
3045
3046 for (unsigned i = component; i < num_components + component; i++) {
3047 if (ctx->ac.chip_class >= GFX9) {
3048 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3049 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3050 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3051 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3052 } else {
3053 args[0] = ctx->esgs_ring;
3054 args[1] = vtx_offset;
3055 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3056 args[3] = ctx->ac.i32_0;
3057 args[4] = ctx->ac.i32_1; /* OFFEN */
3058 args[5] = ctx->ac.i32_0; /* IDXEN */
3059 args[6] = ctx->ac.i32_1; /* GLC */
3060 args[7] = ctx->ac.i32_0; /* SLC */
3061 args[8] = ctx->ac.i32_0; /* TFE */
3062
3063 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3064 ctx->ac.i32, args, 9,
3065 AC_FUNC_ATTR_READONLY |
3066 AC_FUNC_ATTR_LEGACY);
3067 }
3068 }
3069 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3070
3071 return result;
3072 }
3073
3074 static LLVMValueRef
3075 build_gep_for_deref(struct ac_nir_context *ctx,
3076 nir_deref_var *deref)
3077 {
3078 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3079 assert(entry->data);
3080 LLVMValueRef val = entry->data;
3081 nir_deref *tail = deref->deref.child;
3082 while (tail != NULL) {
3083 LLVMValueRef offset;
3084 switch (tail->deref_type) {
3085 case nir_deref_type_array: {
3086 nir_deref_array *array = nir_deref_as_array(tail);
3087 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3088 if (array->deref_array_type ==
3089 nir_deref_array_type_indirect) {
3090 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3091 get_src(ctx,
3092 array->indirect),
3093 "");
3094 }
3095 break;
3096 }
3097 case nir_deref_type_struct: {
3098 nir_deref_struct *deref_struct =
3099 nir_deref_as_struct(tail);
3100 offset = LLVMConstInt(ctx->ac.i32,
3101 deref_struct->index, 0);
3102 break;
3103 }
3104 default:
3105 unreachable("bad deref type");
3106 }
3107 val = ac_build_gep0(&ctx->ac, val, offset);
3108 tail = tail->child;
3109 }
3110 return val;
3111 }
3112
3113 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3114 nir_intrinsic_instr *instr)
3115 {
3116 LLVMValueRef values[8];
3117 int idx = instr->variables[0]->var->data.driver_location;
3118 int ve = instr->dest.ssa.num_components;
3119 unsigned comp = instr->variables[0]->var->data.location_frac;
3120 LLVMValueRef indir_index;
3121 LLVMValueRef ret;
3122 unsigned const_index;
3123 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3124 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3125 instr->variables[0]->var->data.mode == nir_var_shader_in;
3126 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3127 &const_index, &indir_index);
3128
3129 if (instr->dest.ssa.bit_size == 64)
3130 ve *= 2;
3131
3132 switch (instr->variables[0]->var->data.mode) {
3133 case nir_var_shader_in:
3134 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3135 return load_tcs_input(ctx->nctx, instr);
3136 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3137 return load_tes_input(ctx->nctx, instr);
3138 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3139 LLVMValueRef indir_index;
3140 unsigned const_index, vertex_index;
3141 get_deref_offset(ctx, instr->variables[0],
3142 false, &vertex_index, NULL,
3143 &const_index, &indir_index);
3144 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3145 instr->variables[0]->var->data.driver_location,
3146 instr->variables[0]->var->data.location_frac, ve,
3147 vertex_index, const_index,
3148 nir2llvmtype(ctx, instr->variables[0]->var->type));
3149 }
3150
3151 for (unsigned chan = comp; chan < ve + comp; chan++) {
3152 if (indir_index) {
3153 unsigned count = glsl_count_attribute_slots(
3154 instr->variables[0]->var->type,
3155 ctx->stage == MESA_SHADER_VERTEX);
3156 count -= chan / 4;
3157 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3158 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3159 stride, false, true);
3160
3161 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3162 tmp_vec,
3163 indir_index, "");
3164 } else
3165 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3166 }
3167 break;
3168 case nir_var_local:
3169 for (unsigned chan = 0; chan < ve; chan++) {
3170 if (indir_index) {
3171 unsigned count = glsl_count_attribute_slots(
3172 instr->variables[0]->var->type, false);
3173 count -= chan / 4;
3174 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3175 &ctx->ac, ctx->locals + idx + chan, count,
3176 stride, true, true);
3177
3178 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3179 tmp_vec,
3180 indir_index, "");
3181 } else {
3182 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3183 }
3184 }
3185 break;
3186 case nir_var_shared: {
3187 LLVMValueRef address = build_gep_for_deref(ctx,
3188 instr->variables[0]);
3189 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3190 return LLVMBuildBitCast(ctx->ac.builder, val,
3191 get_def_type(ctx, &instr->dest.ssa),
3192 "");
3193 }
3194 case nir_var_shader_out:
3195 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3196 return load_tcs_output(ctx->nctx, instr);
3197
3198 for (unsigned chan = comp; chan < ve + comp; chan++) {
3199 if (indir_index) {
3200 unsigned count = glsl_count_attribute_slots(
3201 instr->variables[0]->var->type, false);
3202 count -= chan / 4;
3203 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3204 &ctx->ac, ctx->outputs + idx + chan, count,
3205 stride, true, true);
3206
3207 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3208 tmp_vec,
3209 indir_index, "");
3210 } else {
3211 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3212 ctx->outputs[idx + chan + const_index * stride],
3213 "");
3214 }
3215 }
3216 break;
3217 default:
3218 unreachable("unhandle variable mode");
3219 }
3220 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3221 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3222 }
3223
3224 static void
3225 visit_store_var(struct ac_nir_context *ctx,
3226 nir_intrinsic_instr *instr)
3227 {
3228 LLVMValueRef temp_ptr, value;
3229 int idx = instr->variables[0]->var->data.driver_location;
3230 unsigned comp = instr->variables[0]->var->data.location_frac;
3231 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3232 int writemask = instr->const_index[0] << comp;
3233 LLVMValueRef indir_index;
3234 unsigned const_index;
3235 get_deref_offset(ctx, instr->variables[0], false,
3236 NULL, NULL, &const_index, &indir_index);
3237
3238 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3239 int old_writemask = writemask;
3240
3241 src = LLVMBuildBitCast(ctx->ac.builder, src,
3242 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3243 "");
3244
3245 writemask = 0;
3246 for (unsigned chan = 0; chan < 4; chan++) {
3247 if (old_writemask & (1 << chan))
3248 writemask |= 3u << (2 * chan);
3249 }
3250 }
3251
3252 switch (instr->variables[0]->var->data.mode) {
3253 case nir_var_shader_out:
3254
3255 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3256 store_tcs_output(ctx->nctx, instr, src, writemask);
3257 return;
3258 }
3259
3260 for (unsigned chan = 0; chan < 8; chan++) {
3261 int stride = 4;
3262 if (!(writemask & (1 << chan)))
3263 continue;
3264
3265 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3266
3267 if (instr->variables[0]->var->data.compact)
3268 stride = 1;
3269 if (indir_index) {
3270 unsigned count = glsl_count_attribute_slots(
3271 instr->variables[0]->var->type, false);
3272 count -= chan / 4;
3273 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3274 &ctx->ac, ctx->outputs + idx + chan, count,
3275 stride, true, true);
3276
3277 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3278 value, indir_index, "");
3279 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3280 count, stride, tmp_vec);
3281
3282 } else {
3283 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3284
3285 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3286 }
3287 }
3288 break;
3289 case nir_var_local:
3290 for (unsigned chan = 0; chan < 8; chan++) {
3291 if (!(writemask & (1 << chan)))
3292 continue;
3293
3294 value = llvm_extract_elem(&ctx->ac, src, chan);
3295 if (indir_index) {
3296 unsigned count = glsl_count_attribute_slots(
3297 instr->variables[0]->var->type, false);
3298 count -= chan / 4;
3299 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3300 &ctx->ac, ctx->locals + idx + chan, count,
3301 4, true, true);
3302
3303 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3304 value, indir_index, "");
3305 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3306 count, 4, tmp_vec);
3307 } else {
3308 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3309
3310 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3311 }
3312 }
3313 break;
3314 case nir_var_shared: {
3315 int writemask = instr->const_index[0];
3316 LLVMValueRef address = build_gep_for_deref(ctx,
3317 instr->variables[0]);
3318 LLVMValueRef val = get_src(ctx, instr->src[0]);
3319 unsigned components =
3320 glsl_get_vector_elements(
3321 nir_deref_tail(&instr->variables[0]->deref)->type);
3322 if (writemask == (1 << components) - 1) {
3323 val = LLVMBuildBitCast(
3324 ctx->ac.builder, val,
3325 LLVMGetElementType(LLVMTypeOf(address)), "");
3326 LLVMBuildStore(ctx->ac.builder, val, address);
3327 } else {
3328 for (unsigned chan = 0; chan < 4; chan++) {
3329 if (!(writemask & (1 << chan)))
3330 continue;
3331 LLVMValueRef ptr =
3332 LLVMBuildStructGEP(ctx->ac.builder,
3333 address, chan, "");
3334 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3335 chan);
3336 src = LLVMBuildBitCast(
3337 ctx->ac.builder, src,
3338 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3339 LLVMBuildStore(ctx->ac.builder, src, ptr);
3340 }
3341 }
3342 break;
3343 }
3344 default:
3345 break;
3346 }
3347 }
3348
3349 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3350 {
3351 switch (dim) {
3352 case GLSL_SAMPLER_DIM_BUF:
3353 return 1;
3354 case GLSL_SAMPLER_DIM_1D:
3355 return array ? 2 : 1;
3356 case GLSL_SAMPLER_DIM_2D:
3357 return array ? 3 : 2;
3358 case GLSL_SAMPLER_DIM_MS:
3359 return array ? 4 : 3;
3360 case GLSL_SAMPLER_DIM_3D:
3361 case GLSL_SAMPLER_DIM_CUBE:
3362 return 3;
3363 case GLSL_SAMPLER_DIM_RECT:
3364 case GLSL_SAMPLER_DIM_SUBPASS:
3365 return 2;
3366 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3367 return 3;
3368 default:
3369 break;
3370 }
3371 return 0;
3372 }
3373
3374
3375
3376 /* Adjust the sample index according to FMASK.
3377 *
3378 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3379 * which is the identity mapping. Each nibble says which physical sample
3380 * should be fetched to get that sample.
3381 *
3382 * For example, 0x11111100 means there are only 2 samples stored and
3383 * the second sample covers 3/4 of the pixel. When reading samples 0
3384 * and 1, return physical sample 0 (determined by the first two 0s
3385 * in FMASK), otherwise return physical sample 1.
3386 *
3387 * The sample index should be adjusted as follows:
3388 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3389 */
3390 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3391 LLVMValueRef coord_x, LLVMValueRef coord_y,
3392 LLVMValueRef coord_z,
3393 LLVMValueRef sample_index,
3394 LLVMValueRef fmask_desc_ptr)
3395 {
3396 LLVMValueRef fmask_load_address[4];
3397 LLVMValueRef res;
3398
3399 fmask_load_address[0] = coord_x;
3400 fmask_load_address[1] = coord_y;
3401 if (coord_z) {
3402 fmask_load_address[2] = coord_z;
3403 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3404 }
3405
3406 struct ac_image_args args = {0};
3407
3408 args.opcode = ac_image_load;
3409 args.da = coord_z ? true : false;
3410 args.resource = fmask_desc_ptr;
3411 args.dmask = 0xf;
3412 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3413
3414 res = ac_build_image_opcode(ctx, &args);
3415
3416 res = ac_to_integer(ctx, res);
3417 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3418 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3419
3420 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3421 res,
3422 ctx->i32_0, "");
3423
3424 LLVMValueRef sample_index4 =
3425 LLVMBuildMul(ctx->builder, sample_index, four, "");
3426 LLVMValueRef shifted_fmask =
3427 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3428 LLVMValueRef final_sample =
3429 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3430
3431 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3432 * resource descriptor is 0 (invalid),
3433 */
3434 LLVMValueRef fmask_desc =
3435 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3436 ctx->v8i32, "");
3437
3438 LLVMValueRef fmask_word1 =
3439 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3440 ctx->i32_1, "");
3441
3442 LLVMValueRef word1_is_nonzero =
3443 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3444 fmask_word1, ctx->i32_0, "");
3445
3446 /* Replace the MSAA sample index. */
3447 sample_index =
3448 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3449 final_sample, sample_index, "");
3450 return sample_index;
3451 }
3452
3453 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3454 const nir_intrinsic_instr *instr)
3455 {
3456 const struct glsl_type *type = instr->variables[0]->var->type;
3457 if(instr->variables[0]->deref.child)
3458 type = instr->variables[0]->deref.child->type;
3459
3460 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3461 LLVMValueRef coords[4];
3462 LLVMValueRef masks[] = {
3463 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3464 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3465 };
3466 LLVMValueRef res;
3467 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3468
3469 int count;
3470 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3471 bool is_array = glsl_sampler_type_is_array(type);
3472 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3473 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3474 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3475 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3476 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3477 count = image_type_to_components_count(dim, is_array);
3478
3479 if (is_ms) {
3480 LLVMValueRef fmask_load_address[3];
3481 int chan;
3482
3483 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3484 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3485 if (is_array)
3486 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3487 else
3488 fmask_load_address[2] = NULL;
3489 if (add_frag_pos) {
3490 for (chan = 0; chan < 2; ++chan)
3491 fmask_load_address[chan] =
3492 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3493 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3494 ctx->ac.i32, ""), "");
3495 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3496 }
3497 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3498 fmask_load_address[0],
3499 fmask_load_address[1],
3500 fmask_load_address[2],
3501 sample_index,
3502 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3503 }
3504 if (count == 1 && !gfx9_1d) {
3505 if (instr->src[0].ssa->num_components)
3506 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3507 else
3508 res = src0;
3509 } else {
3510 int chan;
3511 if (is_ms)
3512 count--;
3513 for (chan = 0; chan < count; ++chan) {
3514 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3515 }
3516 if (add_frag_pos) {
3517 for (chan = 0; chan < 2; ++chan)
3518 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3519 ctx->ac.i32, ""), "");
3520 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3521 count++;
3522 }
3523
3524 if (gfx9_1d) {
3525 if (is_array) {
3526 coords[2] = coords[1];
3527 coords[1] = ctx->ac.i32_0;
3528 } else
3529 coords[1] = ctx->ac.i32_0;
3530 count++;
3531 }
3532
3533 if (is_ms) {
3534 coords[count] = sample_index;
3535 count++;
3536 }
3537
3538 if (count == 3) {
3539 coords[3] = LLVMGetUndef(ctx->ac.i32);
3540 count = 4;
3541 }
3542 res = ac_build_gather_values(&ctx->ac, coords, count);
3543 }
3544 return res;
3545 }
3546
3547 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3548 const nir_intrinsic_instr *instr)
3549 {
3550 LLVMValueRef params[7];
3551 LLVMValueRef res;
3552 char intrinsic_name[64];
3553 const nir_variable *var = instr->variables[0]->var;
3554 const struct glsl_type *type = var->type;
3555
3556 if(instr->variables[0]->deref.child)
3557 type = instr->variables[0]->deref.child->type;
3558
3559 type = glsl_without_array(type);
3560 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3561 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3562 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3563 ctx->ac.i32_0, ""); /* vindex */
3564 params[2] = ctx->ac.i32_0; /* voffset */
3565 params[3] = ctx->ac.i1false; /* glc */
3566 params[4] = ctx->ac.i1false; /* slc */
3567 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3568 params, 5, 0);
3569
3570 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3571 res = ac_to_integer(&ctx->ac, res);
3572 } else {
3573 bool is_da = glsl_sampler_type_is_array(type) ||
3574 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3575 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3576 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3577 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3578 LLVMValueRef glc = ctx->ac.i1false;
3579 LLVMValueRef slc = ctx->ac.i1false;
3580
3581 params[0] = get_image_coords(ctx, instr);
3582 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3583 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3584 if (HAVE_LLVM <= 0x0309) {
3585 params[3] = ctx->ac.i1false; /* r128 */
3586 params[4] = da;
3587 params[5] = glc;
3588 params[6] = slc;
3589 } else {
3590 LLVMValueRef lwe = ctx->ac.i1false;
3591 params[3] = glc;
3592 params[4] = slc;
3593 params[5] = lwe;
3594 params[6] = da;
3595 }
3596
3597 ac_get_image_intr_name("llvm.amdgcn.image.load",
3598 ctx->ac.v4f32, /* vdata */
3599 LLVMTypeOf(params[0]), /* coords */
3600 LLVMTypeOf(params[1]), /* rsrc */
3601 intrinsic_name, sizeof(intrinsic_name));
3602
3603 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3604 params, 7, AC_FUNC_ATTR_READONLY);
3605 }
3606 return ac_to_integer(&ctx->ac, res);
3607 }
3608
3609 static void visit_image_store(struct ac_nir_context *ctx,
3610 nir_intrinsic_instr *instr)
3611 {
3612 LLVMValueRef params[8];
3613 char intrinsic_name[64];
3614 const nir_variable *var = instr->variables[0]->var;
3615 const struct glsl_type *type = glsl_without_array(var->type);
3616 LLVMValueRef glc = ctx->ac.i1false;
3617 bool force_glc = ctx->ac.chip_class == SI;
3618 if (force_glc)
3619 glc = ctx->ac.i1true;
3620
3621 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3622 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3623 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3624 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3625 ctx->ac.i32_0, ""); /* vindex */
3626 params[3] = ctx->ac.i32_0; /* voffset */
3627 params[4] = glc; /* glc */
3628 params[5] = ctx->ac.i1false; /* slc */
3629 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3630 params, 6, 0);
3631 } else {
3632 bool is_da = glsl_sampler_type_is_array(type) ||
3633 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3634 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3635 LLVMValueRef slc = ctx->ac.i1false;
3636
3637 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3638 params[1] = get_image_coords(ctx, instr); /* coords */
3639 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3640 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3641 if (HAVE_LLVM <= 0x0309) {
3642 params[4] = ctx->ac.i1false; /* r128 */
3643 params[5] = da;
3644 params[6] = glc;
3645 params[7] = slc;
3646 } else {
3647 LLVMValueRef lwe = ctx->ac.i1false;
3648 params[4] = glc;
3649 params[5] = slc;
3650 params[6] = lwe;
3651 params[7] = da;
3652 }
3653
3654 ac_get_image_intr_name("llvm.amdgcn.image.store",
3655 LLVMTypeOf(params[0]), /* vdata */
3656 LLVMTypeOf(params[1]), /* coords */
3657 LLVMTypeOf(params[2]), /* rsrc */
3658 intrinsic_name, sizeof(intrinsic_name));
3659
3660 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3661 params, 8, 0);
3662 }
3663
3664 }
3665
3666 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3667 const nir_intrinsic_instr *instr)
3668 {
3669 LLVMValueRef params[7];
3670 int param_count = 0;
3671 const nir_variable *var = instr->variables[0]->var;
3672
3673 const char *atomic_name;
3674 char intrinsic_name[41];
3675 const struct glsl_type *type = glsl_without_array(var->type);
3676 MAYBE_UNUSED int length;
3677
3678 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3679
3680 switch (instr->intrinsic) {
3681 case nir_intrinsic_image_atomic_add:
3682 atomic_name = "add";
3683 break;
3684 case nir_intrinsic_image_atomic_min:
3685 atomic_name = is_unsigned ? "umin" : "smin";
3686 break;
3687 case nir_intrinsic_image_atomic_max:
3688 atomic_name = is_unsigned ? "umax" : "smax";
3689 break;
3690 case nir_intrinsic_image_atomic_and:
3691 atomic_name = "and";
3692 break;
3693 case nir_intrinsic_image_atomic_or:
3694 atomic_name = "or";
3695 break;
3696 case nir_intrinsic_image_atomic_xor:
3697 atomic_name = "xor";
3698 break;
3699 case nir_intrinsic_image_atomic_exchange:
3700 atomic_name = "swap";
3701 break;
3702 case nir_intrinsic_image_atomic_comp_swap:
3703 atomic_name = "cmpswap";
3704 break;
3705 default:
3706 abort();
3707 }
3708
3709 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3710 params[param_count++] = get_src(ctx, instr->src[3]);
3711 params[param_count++] = get_src(ctx, instr->src[2]);
3712
3713 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3714 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3715 NULL, true, true);
3716 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3717 ctx->ac.i32_0, ""); /* vindex */
3718 params[param_count++] = ctx->ac.i32_0; /* voffset */
3719 params[param_count++] = ctx->ac.i1false; /* slc */
3720
3721 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3722 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3723 } else {
3724 char coords_type[8];
3725
3726 bool da = glsl_sampler_type_is_array(type) ||
3727 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3728
3729 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3730 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3731 NULL, true, true);
3732 params[param_count++] = ctx->ac.i1false; /* r128 */
3733 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3734 params[param_count++] = ctx->ac.i1false; /* slc */
3735
3736 build_int_type_name(LLVMTypeOf(coords),
3737 coords_type, sizeof(coords_type));
3738
3739 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3740 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3741 }
3742
3743 assert(length < sizeof(intrinsic_name));
3744 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3745 }
3746
3747 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3748 const nir_intrinsic_instr *instr)
3749 {
3750 LLVMValueRef res;
3751 const nir_variable *var = instr->variables[0]->var;
3752 const struct glsl_type *type = instr->variables[0]->var->type;
3753 bool da = glsl_sampler_type_is_array(var->type) ||
3754 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3755 if(instr->variables[0]->deref.child)
3756 type = instr->variables[0]->deref.child->type;
3757
3758 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3759 return get_buffer_size(ctx,
3760 get_sampler_desc(ctx, instr->variables[0],
3761 AC_DESC_BUFFER, NULL, true, false), true);
3762
3763 struct ac_image_args args = { 0 };
3764
3765 args.da = da;
3766 args.dmask = 0xf;
3767 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3768 args.opcode = ac_image_get_resinfo;
3769 args.addr = ctx->ac.i32_0;
3770
3771 res = ac_build_image_opcode(&ctx->ac, &args);
3772
3773 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3774
3775 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3776 glsl_sampler_type_is_array(type)) {
3777 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3778 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3779 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3780 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3781 }
3782 if (ctx->ac.chip_class >= GFX9 &&
3783 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3784 glsl_sampler_type_is_array(type)) {
3785 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3786 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3787 ctx->ac.i32_1, "");
3788
3789 }
3790 return res;
3791 }
3792
3793 #define NOOP_WAITCNT 0xf7f
3794 #define LGKM_CNT 0x07f
3795 #define VM_CNT 0xf70
3796
3797 static void emit_membar(struct nir_to_llvm_context *ctx,
3798 const nir_intrinsic_instr *instr)
3799 {
3800 unsigned waitcnt = NOOP_WAITCNT;
3801
3802 switch (instr->intrinsic) {
3803 case nir_intrinsic_memory_barrier:
3804 case nir_intrinsic_group_memory_barrier:
3805 waitcnt &= VM_CNT & LGKM_CNT;
3806 break;
3807 case nir_intrinsic_memory_barrier_atomic_counter:
3808 case nir_intrinsic_memory_barrier_buffer:
3809 case nir_intrinsic_memory_barrier_image:
3810 waitcnt &= VM_CNT;
3811 break;
3812 case nir_intrinsic_memory_barrier_shared:
3813 waitcnt &= LGKM_CNT;
3814 break;
3815 default:
3816 break;
3817 }
3818 if (waitcnt != NOOP_WAITCNT)
3819 ac_build_waitcnt(&ctx->ac, waitcnt);
3820 }
3821
3822 static void emit_barrier(struct nir_to_llvm_context *ctx)
3823 {
3824 /* SI only (thanks to a hw bug workaround):
3825 * The real barrier instruction isn’t needed, because an entire patch
3826 * always fits into a single wave.
3827 */
3828 if (ctx->options->chip_class == SI &&
3829 ctx->stage == MESA_SHADER_TESS_CTRL) {
3830 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3831 return;
3832 }
3833 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3834 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3835 }
3836
3837 static void emit_discard_if(struct ac_nir_context *ctx,
3838 const nir_intrinsic_instr *instr)
3839 {
3840 LLVMValueRef cond;
3841
3842 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3843 get_src(ctx, instr->src[0]),
3844 ctx->ac.i32_0, "");
3845 ac_build_kill_if_false(&ctx->ac, cond);
3846 }
3847
3848 static LLVMValueRef
3849 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3850 {
3851 LLVMValueRef result;
3852 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3853 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3854 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3855
3856 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3857 }
3858
3859 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3860 const nir_intrinsic_instr *instr)
3861 {
3862 LLVMValueRef ptr, result;
3863 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3864 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3865
3866 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3867 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3868 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3869 ptr, src, src1,
3870 LLVMAtomicOrderingSequentiallyConsistent,
3871 LLVMAtomicOrderingSequentiallyConsistent,
3872 false);
3873 } else {
3874 LLVMAtomicRMWBinOp op;
3875 switch (instr->intrinsic) {
3876 case nir_intrinsic_var_atomic_add:
3877 op = LLVMAtomicRMWBinOpAdd;
3878 break;
3879 case nir_intrinsic_var_atomic_umin:
3880 op = LLVMAtomicRMWBinOpUMin;
3881 break;
3882 case nir_intrinsic_var_atomic_umax:
3883 op = LLVMAtomicRMWBinOpUMax;
3884 break;
3885 case nir_intrinsic_var_atomic_imin:
3886 op = LLVMAtomicRMWBinOpMin;
3887 break;
3888 case nir_intrinsic_var_atomic_imax:
3889 op = LLVMAtomicRMWBinOpMax;
3890 break;
3891 case nir_intrinsic_var_atomic_and:
3892 op = LLVMAtomicRMWBinOpAnd;
3893 break;
3894 case nir_intrinsic_var_atomic_or:
3895 op = LLVMAtomicRMWBinOpOr;
3896 break;
3897 case nir_intrinsic_var_atomic_xor:
3898 op = LLVMAtomicRMWBinOpXor;
3899 break;
3900 case nir_intrinsic_var_atomic_exchange:
3901 op = LLVMAtomicRMWBinOpXchg;
3902 break;
3903 default:
3904 return NULL;
3905 }
3906
3907 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3908 LLVMAtomicOrderingSequentiallyConsistent,
3909 false);
3910 }
3911 return result;
3912 }
3913
3914 #define INTERP_CENTER 0
3915 #define INTERP_CENTROID 1
3916 #define INTERP_SAMPLE 2
3917
3918 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3919 enum glsl_interp_mode interp, unsigned location)
3920 {
3921 switch (interp) {
3922 case INTERP_MODE_FLAT:
3923 default:
3924 return NULL;
3925 case INTERP_MODE_SMOOTH:
3926 case INTERP_MODE_NONE:
3927 if (location == INTERP_CENTER)
3928 return ctx->persp_center;
3929 else if (location == INTERP_CENTROID)
3930 return ctx->persp_centroid;
3931 else if (location == INTERP_SAMPLE)
3932 return ctx->persp_sample;
3933 break;
3934 case INTERP_MODE_NOPERSPECTIVE:
3935 if (location == INTERP_CENTER)
3936 return ctx->linear_center;
3937 else if (location == INTERP_CENTROID)
3938 return ctx->linear_centroid;
3939 else if (location == INTERP_SAMPLE)
3940 return ctx->linear_sample;
3941 break;
3942 }
3943 return NULL;
3944 }
3945
3946 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3947 LLVMValueRef sample_id)
3948 {
3949 LLVMValueRef result;
3950 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3951
3952 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3953 const_array(ctx->ac.v2f32, 64), "");
3954
3955 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3956 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3957
3958 return result;
3959 }
3960
3961 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3962 {
3963 LLVMValueRef values[2];
3964
3965 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3966 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3967 return ac_build_gather_values(&ctx->ac, values, 2);
3968 }
3969
3970 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3971 const nir_intrinsic_instr *instr)
3972 {
3973 LLVMValueRef result[4];
3974 LLVMValueRef interp_param, attr_number;
3975 unsigned location;
3976 unsigned chan;
3977 LLVMValueRef src_c0 = NULL;
3978 LLVMValueRef src_c1 = NULL;
3979 LLVMValueRef src0 = NULL;
3980 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3981 switch (instr->intrinsic) {
3982 case nir_intrinsic_interp_var_at_centroid:
3983 location = INTERP_CENTROID;
3984 break;
3985 case nir_intrinsic_interp_var_at_sample:
3986 case nir_intrinsic_interp_var_at_offset:
3987 location = INTERP_CENTER;
3988 src0 = get_src(ctx->nir, instr->src[0]);
3989 break;
3990 default:
3991 break;
3992 }
3993
3994 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3995 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3996 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3997 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3998 LLVMValueRef sample_position;
3999 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4000
4001 /* fetch sample ID */
4002 sample_position = load_sample_position(ctx, src0);
4003
4004 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4005 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4006 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4007 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4008 }
4009 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4010 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4011
4012 if (location == INTERP_CENTER) {
4013 LLVMValueRef ij_out[2];
4014 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4015
4016 /*
4017 * take the I then J parameters, and the DDX/Y for it, and
4018 * calculate the IJ inputs for the interpolator.
4019 * temp1 = ddx * offset/sample.x + I;
4020 * interp_param.I = ddy * offset/sample.y + temp1;
4021 * temp1 = ddx * offset/sample.x + J;
4022 * interp_param.J = ddy * offset/sample.y + temp1;
4023 */
4024 for (unsigned i = 0; i < 2; i++) {
4025 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4026 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4027 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4028 ddxy_out, ix_ll, "");
4029 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4030 ddxy_out, iy_ll, "");
4031 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4032 interp_param, ix_ll, "");
4033 LLVMValueRef temp1, temp2;
4034
4035 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4036 ctx->ac.f32, "");
4037
4038 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4039 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4040
4041 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4042 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4043
4044 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4045 temp2, ctx->ac.i32, "");
4046 }
4047 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4048
4049 }
4050
4051 for (chan = 0; chan < 4; chan++) {
4052 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4053
4054 if (interp_param) {
4055 interp_param = LLVMBuildBitCast(ctx->builder,
4056 interp_param, ctx->ac.v2f32, "");
4057 LLVMValueRef i = LLVMBuildExtractElement(
4058 ctx->builder, interp_param, ctx->ac.i32_0, "");
4059 LLVMValueRef j = LLVMBuildExtractElement(
4060 ctx->builder, interp_param, ctx->ac.i32_1, "");
4061
4062 result[chan] = ac_build_fs_interp(&ctx->ac,
4063 llvm_chan, attr_number,
4064 ctx->prim_mask, i, j);
4065 } else {
4066 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4067 LLVMConstInt(ctx->ac.i32, 2, false),
4068 llvm_chan, attr_number,
4069 ctx->prim_mask);
4070 }
4071 }
4072 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4073 instr->variables[0]->var->data.location_frac);
4074 }
4075
4076 static void
4077 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4078 {
4079 LLVMValueRef gs_next_vertex;
4080 LLVMValueRef can_emit;
4081 int idx;
4082 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4083
4084 /* Write vertex attribute values to GSVS ring */
4085 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4086 ctx->gs_next_vertex,
4087 "");
4088
4089 /* If this thread has already emitted the declared maximum number of
4090 * vertices, kill it: excessive vertex emissions are not supposed to
4091 * have any effect, and GS threads have no externally observable
4092 * effects other than emitting vertices.
4093 */
4094 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4095 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4096 ac_build_kill_if_false(&ctx->ac, can_emit);
4097
4098 /* loop num outputs */
4099 idx = 0;
4100 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4101 LLVMValueRef *out_ptr = &addrs[i * 4];
4102 int length = 4;
4103 int slot = idx;
4104 int slot_inc = 1;
4105
4106 if (!(ctx->output_mask & (1ull << i)))
4107 continue;
4108
4109 if (i == VARYING_SLOT_CLIP_DIST0) {
4110 /* pack clip and cull into a single set of slots */
4111 length = ctx->num_output_clips + ctx->num_output_culls;
4112 if (length > 4)
4113 slot_inc = 2;
4114 }
4115 for (unsigned j = 0; j < length; j++) {
4116 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4117 out_ptr[j], "");
4118 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4119 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4120 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4121
4122 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4123
4124 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4125 out_val, 1,
4126 voffset, ctx->gs2vs_offset, 0,
4127 1, 1, true, true);
4128 }
4129 idx += slot_inc;
4130 }
4131
4132 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4133 ctx->ac.i32_1, "");
4134 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4135
4136 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4137 }
4138
4139 static void
4140 visit_end_primitive(struct nir_to_llvm_context *ctx,
4141 const nir_intrinsic_instr *instr)
4142 {
4143 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4144 }
4145
4146 static LLVMValueRef
4147 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4148 const nir_intrinsic_instr *instr)
4149 {
4150 LLVMValueRef coord[4] = {
4151 ctx->tes_u,
4152 ctx->tes_v,
4153 ctx->ac.f32_0,
4154 ctx->ac.f32_0,
4155 };
4156
4157 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4158 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4159 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4160
4161 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4162 return LLVMBuildBitCast(ctx->builder, result,
4163 get_def_type(ctx->nir, &instr->dest.ssa), "");
4164 }
4165
4166 static void visit_intrinsic(struct ac_nir_context *ctx,
4167 nir_intrinsic_instr *instr)
4168 {
4169 LLVMValueRef result = NULL;
4170
4171 switch (instr->intrinsic) {
4172 case nir_intrinsic_load_work_group_id: {
4173 LLVMValueRef values[3];
4174
4175 for (int i = 0; i < 3; i++) {
4176 values[i] = ctx->nctx->workgroup_ids[i] ?
4177 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4178 }
4179
4180 result = ac_build_gather_values(&ctx->ac, values, 3);
4181 break;
4182 }
4183 case nir_intrinsic_load_base_vertex: {
4184 result = ctx->abi->base_vertex;
4185 break;
4186 }
4187 case nir_intrinsic_load_vertex_id_zero_base: {
4188 result = ctx->abi->vertex_id;
4189 break;
4190 }
4191 case nir_intrinsic_load_local_invocation_id: {
4192 result = ctx->nctx->local_invocation_ids;
4193 break;
4194 }
4195 case nir_intrinsic_load_base_instance:
4196 result = ctx->abi->start_instance;
4197 break;
4198 case nir_intrinsic_load_draw_id:
4199 result = ctx->abi->draw_id;
4200 break;
4201 case nir_intrinsic_load_view_index:
4202 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4203 break;
4204 case nir_intrinsic_load_invocation_id:
4205 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4206 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4207 else
4208 result = ctx->abi->gs_invocation_id;
4209 break;
4210 case nir_intrinsic_load_primitive_id:
4211 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4212 if (ctx->nctx)
4213 ctx->nctx->shader_info->gs.uses_prim_id = true;
4214 result = ctx->abi->gs_prim_id;
4215 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4216 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4217 result = ctx->nctx->tcs_patch_id;
4218 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4219 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4220 result = ctx->nctx->tes_patch_id;
4221 } else
4222 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4223 break;
4224 case nir_intrinsic_load_sample_id:
4225 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4226 break;
4227 case nir_intrinsic_load_sample_pos:
4228 result = load_sample_pos(ctx);
4229 break;
4230 case nir_intrinsic_load_sample_mask_in:
4231 result = ctx->abi->sample_coverage;
4232 break;
4233 case nir_intrinsic_load_frag_coord: {
4234 LLVMValueRef values[4] = {
4235 ctx->abi->frag_pos[0],
4236 ctx->abi->frag_pos[1],
4237 ctx->abi->frag_pos[2],
4238 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4239 };
4240 result = ac_build_gather_values(&ctx->ac, values, 4);
4241 break;
4242 }
4243 case nir_intrinsic_load_front_face:
4244 result = ctx->abi->front_face;
4245 break;
4246 case nir_intrinsic_load_instance_id:
4247 result = ctx->abi->instance_id;
4248 break;
4249 case nir_intrinsic_load_num_work_groups:
4250 result = ctx->nctx->num_work_groups;
4251 break;
4252 case nir_intrinsic_load_local_invocation_index:
4253 result = visit_load_local_invocation_index(ctx->nctx);
4254 break;
4255 case nir_intrinsic_load_push_constant:
4256 result = visit_load_push_constant(ctx->nctx, instr);
4257 break;
4258 case nir_intrinsic_vulkan_resource_index:
4259 result = visit_vulkan_resource_index(ctx->nctx, instr);
4260 break;
4261 case nir_intrinsic_vulkan_resource_reindex:
4262 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4263 break;
4264 case nir_intrinsic_store_ssbo:
4265 visit_store_ssbo(ctx, instr);
4266 break;
4267 case nir_intrinsic_load_ssbo:
4268 result = visit_load_buffer(ctx, instr);
4269 break;
4270 case nir_intrinsic_ssbo_atomic_add:
4271 case nir_intrinsic_ssbo_atomic_imin:
4272 case nir_intrinsic_ssbo_atomic_umin:
4273 case nir_intrinsic_ssbo_atomic_imax:
4274 case nir_intrinsic_ssbo_atomic_umax:
4275 case nir_intrinsic_ssbo_atomic_and:
4276 case nir_intrinsic_ssbo_atomic_or:
4277 case nir_intrinsic_ssbo_atomic_xor:
4278 case nir_intrinsic_ssbo_atomic_exchange:
4279 case nir_intrinsic_ssbo_atomic_comp_swap:
4280 result = visit_atomic_ssbo(ctx, instr);
4281 break;
4282 case nir_intrinsic_load_ubo:
4283 result = visit_load_ubo_buffer(ctx, instr);
4284 break;
4285 case nir_intrinsic_get_buffer_size:
4286 result = visit_get_buffer_size(ctx, instr);
4287 break;
4288 case nir_intrinsic_load_var:
4289 result = visit_load_var(ctx, instr);
4290 break;
4291 case nir_intrinsic_store_var:
4292 visit_store_var(ctx, instr);
4293 break;
4294 case nir_intrinsic_image_load:
4295 result = visit_image_load(ctx, instr);
4296 break;
4297 case nir_intrinsic_image_store:
4298 visit_image_store(ctx, instr);
4299 break;
4300 case nir_intrinsic_image_atomic_add:
4301 case nir_intrinsic_image_atomic_min:
4302 case nir_intrinsic_image_atomic_max:
4303 case nir_intrinsic_image_atomic_and:
4304 case nir_intrinsic_image_atomic_or:
4305 case nir_intrinsic_image_atomic_xor:
4306 case nir_intrinsic_image_atomic_exchange:
4307 case nir_intrinsic_image_atomic_comp_swap:
4308 result = visit_image_atomic(ctx, instr);
4309 break;
4310 case nir_intrinsic_image_size:
4311 result = visit_image_size(ctx, instr);
4312 break;
4313 case nir_intrinsic_discard:
4314 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4315 LLVMVoidTypeInContext(ctx->ac.context),
4316 NULL, 0, AC_FUNC_ATTR_LEGACY);
4317 break;
4318 case nir_intrinsic_discard_if:
4319 emit_discard_if(ctx, instr);
4320 break;
4321 case nir_intrinsic_memory_barrier:
4322 case nir_intrinsic_group_memory_barrier:
4323 case nir_intrinsic_memory_barrier_atomic_counter:
4324 case nir_intrinsic_memory_barrier_buffer:
4325 case nir_intrinsic_memory_barrier_image:
4326 case nir_intrinsic_memory_barrier_shared:
4327 emit_membar(ctx->nctx, instr);
4328 break;
4329 case nir_intrinsic_barrier:
4330 emit_barrier(ctx->nctx);
4331 break;
4332 case nir_intrinsic_var_atomic_add:
4333 case nir_intrinsic_var_atomic_imin:
4334 case nir_intrinsic_var_atomic_umin:
4335 case nir_intrinsic_var_atomic_imax:
4336 case nir_intrinsic_var_atomic_umax:
4337 case nir_intrinsic_var_atomic_and:
4338 case nir_intrinsic_var_atomic_or:
4339 case nir_intrinsic_var_atomic_xor:
4340 case nir_intrinsic_var_atomic_exchange:
4341 case nir_intrinsic_var_atomic_comp_swap:
4342 result = visit_var_atomic(ctx->nctx, instr);
4343 break;
4344 case nir_intrinsic_interp_var_at_centroid:
4345 case nir_intrinsic_interp_var_at_sample:
4346 case nir_intrinsic_interp_var_at_offset:
4347 result = visit_interp(ctx->nctx, instr);
4348 break;
4349 case nir_intrinsic_emit_vertex:
4350 assert(instr->const_index[0] == 0);
4351 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4352 break;
4353 case nir_intrinsic_end_primitive:
4354 visit_end_primitive(ctx->nctx, instr);
4355 break;
4356 case nir_intrinsic_load_tess_coord:
4357 result = visit_load_tess_coord(ctx->nctx, instr);
4358 break;
4359 case nir_intrinsic_load_patch_vertices_in:
4360 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4361 break;
4362 default:
4363 fprintf(stderr, "Unknown intrinsic: ");
4364 nir_print_instr(&instr->instr, stderr);
4365 fprintf(stderr, "\n");
4366 break;
4367 }
4368 if (result) {
4369 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4370 }
4371 }
4372
4373 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4374 LLVMValueRef buffer_ptr, bool write)
4375 {
4376 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4377
4378 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4379 ctx->shader_info->fs.writes_memory = true;
4380
4381 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4382 }
4383
4384 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4385 {
4386 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4387
4388 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4389 }
4390
4391 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4392 unsigned descriptor_set,
4393 unsigned base_index,
4394 unsigned constant_index,
4395 LLVMValueRef index,
4396 enum ac_descriptor_type desc_type,
4397 bool image, bool write)
4398 {
4399 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4400 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4401 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4402 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4403 unsigned offset = binding->offset;
4404 unsigned stride = binding->size;
4405 unsigned type_size;
4406 LLVMBuilderRef builder = ctx->builder;
4407 LLVMTypeRef type;
4408
4409 assert(base_index < layout->binding_count);
4410
4411 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4412 ctx->shader_info->fs.writes_memory = true;
4413
4414 switch (desc_type) {
4415 case AC_DESC_IMAGE:
4416 type = ctx->ac.v8i32;
4417 type_size = 32;
4418 break;
4419 case AC_DESC_FMASK:
4420 type = ctx->ac.v8i32;
4421 offset += 32;
4422 type_size = 32;
4423 break;
4424 case AC_DESC_SAMPLER:
4425 type = ctx->ac.v4i32;
4426 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4427 offset += 64;
4428
4429 type_size = 16;
4430 break;
4431 case AC_DESC_BUFFER:
4432 type = ctx->ac.v4i32;
4433 type_size = 16;
4434 break;
4435 default:
4436 unreachable("invalid desc_type\n");
4437 }
4438
4439 offset += constant_index * stride;
4440
4441 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4442 (!index || binding->immutable_samplers_equal)) {
4443 if (binding->immutable_samplers_equal)
4444 constant_index = 0;
4445
4446 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4447
4448 LLVMValueRef constants[] = {
4449 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4450 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4451 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4452 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4453 };
4454 return ac_build_gather_values(&ctx->ac, constants, 4);
4455 }
4456
4457 assert(stride % type_size == 0);
4458
4459 if (!index)
4460 index = ctx->ac.i32_0;
4461
4462 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4463
4464 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4465 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4466
4467 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4468 }
4469
4470 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4471 const nir_deref_var *deref,
4472 enum ac_descriptor_type desc_type,
4473 const nir_tex_instr *tex_instr,
4474 bool image, bool write)
4475 {
4476 LLVMValueRef index = NULL;
4477 unsigned constant_index = 0;
4478 unsigned descriptor_set;
4479 unsigned base_index;
4480
4481 if (!deref) {
4482 assert(tex_instr && !image);
4483 descriptor_set = 0;
4484 base_index = tex_instr->sampler_index;
4485 } else {
4486 const nir_deref *tail = &deref->deref;
4487 while (tail->child) {
4488 const nir_deref_array *child = nir_deref_as_array(tail->child);
4489 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4490
4491 if (!array_size)
4492 array_size = 1;
4493
4494 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4495
4496 if (child->deref_array_type == nir_deref_array_type_indirect) {
4497 LLVMValueRef indirect = get_src(ctx, child->indirect);
4498
4499 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4500 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4501
4502 if (!index)
4503 index = indirect;
4504 else
4505 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4506 }
4507
4508 constant_index += child->base_offset * array_size;
4509
4510 tail = &child->deref;
4511 }
4512 descriptor_set = deref->var->data.descriptor_set;
4513 base_index = deref->var->data.binding;
4514 }
4515
4516 return ctx->abi->load_sampler_desc(ctx->abi,
4517 descriptor_set,
4518 base_index,
4519 constant_index, index,
4520 desc_type, image, write);
4521 }
4522
4523 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4524 struct ac_image_args *args,
4525 const nir_tex_instr *instr,
4526 nir_texop op,
4527 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4528 LLVMValueRef *param, unsigned count,
4529 unsigned dmask)
4530 {
4531 unsigned is_rect = 0;
4532 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4533
4534 if (op == nir_texop_lod)
4535 da = false;
4536 /* Pad to power of two vector */
4537 while (count < util_next_power_of_two(count))
4538 param[count++] = LLVMGetUndef(ctx->i32);
4539
4540 if (count > 1)
4541 args->addr = ac_build_gather_values(ctx, param, count);
4542 else
4543 args->addr = param[0];
4544
4545 args->resource = res_ptr;
4546 args->sampler = samp_ptr;
4547
4548 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4549 args->addr = param[0];
4550 return;
4551 }
4552
4553 args->dmask = dmask;
4554 args->unorm = is_rect;
4555 args->da = da;
4556 }
4557
4558 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4559 *
4560 * SI-CI:
4561 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4562 * filtering manually. The driver sets img7 to a mask clearing
4563 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4564 * s_and_b32 samp0, samp0, img7
4565 *
4566 * VI:
4567 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4568 */
4569 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4570 LLVMValueRef res, LLVMValueRef samp)
4571 {
4572 LLVMBuilderRef builder = ctx->ac.builder;
4573 LLVMValueRef img7, samp0;
4574
4575 if (ctx->ac.chip_class >= VI)
4576 return samp;
4577
4578 img7 = LLVMBuildExtractElement(builder, res,
4579 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4580 samp0 = LLVMBuildExtractElement(builder, samp,
4581 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4582 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4583 return LLVMBuildInsertElement(builder, samp, samp0,
4584 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4585 }
4586
4587 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4588 nir_tex_instr *instr,
4589 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4590 LLVMValueRef *fmask_ptr)
4591 {
4592 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4593 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4594 else
4595 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4596 if (samp_ptr) {
4597 if (instr->sampler)
4598 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4599 else
4600 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4601 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4602 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4603 }
4604 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4605 instr->op == nir_texop_samples_identical))
4606 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4607 }
4608
4609 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4610 LLVMValueRef coord)
4611 {
4612 coord = ac_to_float(ctx, coord);
4613 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4614 coord = ac_to_integer(ctx, coord);
4615 return coord;
4616 }
4617
4618 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4619 {
4620 LLVMValueRef result = NULL;
4621 struct ac_image_args args = { 0 };
4622 unsigned dmask = 0xf;
4623 LLVMValueRef address[16];
4624 LLVMValueRef coords[5];
4625 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4626 LLVMValueRef bias = NULL, offsets = NULL;
4627 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4628 LLVMValueRef ddx = NULL, ddy = NULL;
4629 LLVMValueRef derivs[6];
4630 unsigned chan, count = 0;
4631 unsigned const_src = 0, num_deriv_comp = 0;
4632 bool lod_is_zero = false;
4633
4634 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4635
4636 for (unsigned i = 0; i < instr->num_srcs; i++) {
4637 switch (instr->src[i].src_type) {
4638 case nir_tex_src_coord:
4639 coord = get_src(ctx, instr->src[i].src);
4640 break;
4641 case nir_tex_src_projector:
4642 break;
4643 case nir_tex_src_comparator:
4644 comparator = get_src(ctx, instr->src[i].src);
4645 break;
4646 case nir_tex_src_offset:
4647 offsets = get_src(ctx, instr->src[i].src);
4648 const_src = i;
4649 break;
4650 case nir_tex_src_bias:
4651 bias = get_src(ctx, instr->src[i].src);
4652 break;
4653 case nir_tex_src_lod: {
4654 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4655
4656 if (val && val->i32[0] == 0)
4657 lod_is_zero = true;
4658 lod = get_src(ctx, instr->src[i].src);
4659 break;
4660 }
4661 case nir_tex_src_ms_index:
4662 sample_index = get_src(ctx, instr->src[i].src);
4663 break;
4664 case nir_tex_src_ms_mcs:
4665 break;
4666 case nir_tex_src_ddx:
4667 ddx = get_src(ctx, instr->src[i].src);
4668 num_deriv_comp = instr->src[i].src.ssa->num_components;
4669 break;
4670 case nir_tex_src_ddy:
4671 ddy = get_src(ctx, instr->src[i].src);
4672 break;
4673 case nir_tex_src_texture_offset:
4674 case nir_tex_src_sampler_offset:
4675 case nir_tex_src_plane:
4676 default:
4677 break;
4678 }
4679 }
4680
4681 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4682 result = get_buffer_size(ctx, res_ptr, true);
4683 goto write_result;
4684 }
4685
4686 if (instr->op == nir_texop_texture_samples) {
4687 LLVMValueRef res, samples, is_msaa;
4688 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4689 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4690 LLVMConstInt(ctx->ac.i32, 3, false), "");
4691 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4692 LLVMConstInt(ctx->ac.i32, 28, false), "");
4693 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4694 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4695 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4696 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4697
4698 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4699 LLVMConstInt(ctx->ac.i32, 16, false), "");
4700 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4701 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4702 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4703 samples, "");
4704 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4705 ctx->ac.i32_1, "");
4706 result = samples;
4707 goto write_result;
4708 }
4709
4710 if (coord)
4711 for (chan = 0; chan < instr->coord_components; chan++)
4712 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4713
4714 if (offsets && instr->op != nir_texop_txf) {
4715 LLVMValueRef offset[3], pack;
4716 for (chan = 0; chan < 3; ++chan)
4717 offset[chan] = ctx->ac.i32_0;
4718
4719 args.offset = true;
4720 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4721 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4722 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4723 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4724 if (chan)
4725 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4726 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4727 }
4728 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4729 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4730 address[count++] = pack;
4731
4732 }
4733 /* pack LOD bias value */
4734 if (instr->op == nir_texop_txb && bias) {
4735 address[count++] = bias;
4736 }
4737
4738 /* Pack depth comparison value */
4739 if (instr->is_shadow && comparator) {
4740 LLVMValueRef z = ac_to_float(&ctx->ac,
4741 llvm_extract_elem(&ctx->ac, comparator, 0));
4742
4743 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4744 * so the depth comparison value isn't clamped for Z16 and
4745 * Z24 anymore. Do it manually here.
4746 *
4747 * It's unnecessary if the original texture format was
4748 * Z32_FLOAT, but we don't know that here.
4749 */
4750 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4751 z = ac_build_clamp(&ctx->ac, z);
4752
4753 address[count++] = z;
4754 }
4755
4756 /* pack derivatives */
4757 if (ddx || ddy) {
4758 int num_src_deriv_channels, num_dest_deriv_channels;
4759 switch (instr->sampler_dim) {
4760 case GLSL_SAMPLER_DIM_3D:
4761 case GLSL_SAMPLER_DIM_CUBE:
4762 num_deriv_comp = 3;
4763 num_src_deriv_channels = 3;
4764 num_dest_deriv_channels = 3;
4765 break;
4766 case GLSL_SAMPLER_DIM_2D:
4767 default:
4768 num_src_deriv_channels = 2;
4769 num_dest_deriv_channels = 2;
4770 num_deriv_comp = 2;
4771 break;
4772 case GLSL_SAMPLER_DIM_1D:
4773 num_src_deriv_channels = 1;
4774 if (ctx->ac.chip_class >= GFX9) {
4775 num_dest_deriv_channels = 2;
4776 num_deriv_comp = 2;
4777 } else {
4778 num_dest_deriv_channels = 1;
4779 num_deriv_comp = 1;
4780 }
4781 break;
4782 }
4783
4784 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4785 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4786 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4787 }
4788 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4789 derivs[i] = ctx->ac.f32_0;
4790 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4791 }
4792 }
4793
4794 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4795 for (chan = 0; chan < instr->coord_components; chan++)
4796 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4797 if (instr->coord_components == 3)
4798 coords[3] = LLVMGetUndef(ctx->ac.f32);
4799 ac_prepare_cube_coords(&ctx->ac,
4800 instr->op == nir_texop_txd, instr->is_array,
4801 instr->op == nir_texop_lod, coords, derivs);
4802 if (num_deriv_comp)
4803 num_deriv_comp--;
4804 }
4805
4806 if (ddx || ddy) {
4807 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4808 address[count++] = derivs[i];
4809 }
4810
4811 /* Pack texture coordinates */
4812 if (coord) {
4813 address[count++] = coords[0];
4814 if (instr->coord_components > 1) {
4815 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4816 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4817 }
4818 address[count++] = coords[1];
4819 }
4820 if (instr->coord_components > 2) {
4821 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4822 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4823 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4824 instr->op != nir_texop_txf) {
4825 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4826 }
4827 address[count++] = coords[2];
4828 }
4829
4830 if (ctx->ac.chip_class >= GFX9) {
4831 LLVMValueRef filler;
4832 if (instr->op == nir_texop_txf)
4833 filler = ctx->ac.i32_0;
4834 else
4835 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4836
4837 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4838 /* No nir_texop_lod, because it does not take a slice
4839 * even with array textures. */
4840 if (instr->is_array && instr->op != nir_texop_lod ) {
4841 address[count] = address[count - 1];
4842 address[count - 1] = filler;
4843 count++;
4844 } else
4845 address[count++] = filler;
4846 }
4847 }
4848 }
4849
4850 /* Pack LOD */
4851 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4852 instr->op == nir_texop_txf)) {
4853 address[count++] = lod;
4854 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4855 address[count++] = sample_index;
4856 } else if(instr->op == nir_texop_txs) {
4857 count = 0;
4858 if (lod)
4859 address[count++] = lod;
4860 else
4861 address[count++] = ctx->ac.i32_0;
4862 }
4863
4864 for (chan = 0; chan < count; chan++) {
4865 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4866 address[chan], ctx->ac.i32, "");
4867 }
4868
4869 if (instr->op == nir_texop_samples_identical) {
4870 LLVMValueRef txf_address[4];
4871 struct ac_image_args txf_args = { 0 };
4872 unsigned txf_count = count;
4873 memcpy(txf_address, address, sizeof(txf_address));
4874
4875 if (!instr->is_array)
4876 txf_address[2] = ctx->ac.i32_0;
4877 txf_address[3] = ctx->ac.i32_0;
4878
4879 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4880 fmask_ptr, NULL,
4881 txf_address, txf_count, 0xf);
4882
4883 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4884
4885 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4886 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4887 goto write_result;
4888 }
4889
4890 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4891 instr->op != nir_texop_txs) {
4892 unsigned sample_chan = instr->is_array ? 3 : 2;
4893 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4894 address[0],
4895 address[1],
4896 instr->is_array ? address[2] : NULL,
4897 address[sample_chan],
4898 fmask_ptr);
4899 }
4900
4901 if (offsets && instr->op == nir_texop_txf) {
4902 nir_const_value *const_offset =
4903 nir_src_as_const_value(instr->src[const_src].src);
4904 int num_offsets = instr->src[const_src].src.ssa->num_components;
4905 assert(const_offset);
4906 num_offsets = MIN2(num_offsets, instr->coord_components);
4907 if (num_offsets > 2)
4908 address[2] = LLVMBuildAdd(ctx->ac.builder,
4909 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4910 if (num_offsets > 1)
4911 address[1] = LLVMBuildAdd(ctx->ac.builder,
4912 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4913 address[0] = LLVMBuildAdd(ctx->ac.builder,
4914 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4915
4916 }
4917
4918 /* TODO TG4 support */
4919 if (instr->op == nir_texop_tg4) {
4920 if (instr->is_shadow)
4921 dmask = 1;
4922 else
4923 dmask = 1 << instr->component;
4924 }
4925 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4926 res_ptr, samp_ptr, address, count, dmask);
4927
4928 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4929
4930 if (instr->op == nir_texop_query_levels)
4931 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4932 else if (instr->is_shadow && instr->is_new_style_shadow &&
4933 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4934 instr->op != nir_texop_tg4)
4935 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4936 else if (instr->op == nir_texop_txs &&
4937 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4938 instr->is_array) {
4939 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4940 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4941 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4942 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4943 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4944 } else if (ctx->ac.chip_class >= GFX9 &&
4945 instr->op == nir_texop_txs &&
4946 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4947 instr->is_array) {
4948 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4949 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4950 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4951 ctx->ac.i32_1, "");
4952 } else if (instr->dest.ssa.num_components != 4)
4953 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4954
4955 write_result:
4956 if (result) {
4957 assert(instr->dest.is_ssa);
4958 result = ac_to_integer(&ctx->ac, result);
4959 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4960 }
4961 }
4962
4963
4964 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4965 {
4966 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4967 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4968
4969 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4970 _mesa_hash_table_insert(ctx->phis, instr, result);
4971 }
4972
4973 static void visit_post_phi(struct ac_nir_context *ctx,
4974 nir_phi_instr *instr,
4975 LLVMValueRef llvm_phi)
4976 {
4977 nir_foreach_phi_src(src, instr) {
4978 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4979 LLVMValueRef llvm_src = get_src(ctx, src->src);
4980
4981 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4982 }
4983 }
4984
4985 static void phi_post_pass(struct ac_nir_context *ctx)
4986 {
4987 struct hash_entry *entry;
4988 hash_table_foreach(ctx->phis, entry) {
4989 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4990 (LLVMValueRef)entry->data);
4991 }
4992 }
4993
4994
4995 static void visit_ssa_undef(struct ac_nir_context *ctx,
4996 const nir_ssa_undef_instr *instr)
4997 {
4998 unsigned num_components = instr->def.num_components;
4999 LLVMValueRef undef;
5000
5001 if (num_components == 1)
5002 undef = LLVMGetUndef(ctx->ac.i32);
5003 else {
5004 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5005 }
5006 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5007 }
5008
5009 static void visit_jump(struct ac_nir_context *ctx,
5010 const nir_jump_instr *instr)
5011 {
5012 switch (instr->type) {
5013 case nir_jump_break:
5014 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5015 LLVMClearInsertionPosition(ctx->ac.builder);
5016 break;
5017 case nir_jump_continue:
5018 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5019 LLVMClearInsertionPosition(ctx->ac.builder);
5020 break;
5021 default:
5022 fprintf(stderr, "Unknown NIR jump instr: ");
5023 nir_print_instr(&instr->instr, stderr);
5024 fprintf(stderr, "\n");
5025 abort();
5026 }
5027 }
5028
5029 static void visit_cf_list(struct ac_nir_context *ctx,
5030 struct exec_list *list);
5031
5032 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5033 {
5034 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5035 nir_foreach_instr(instr, block)
5036 {
5037 switch (instr->type) {
5038 case nir_instr_type_alu:
5039 visit_alu(ctx, nir_instr_as_alu(instr));
5040 break;
5041 case nir_instr_type_load_const:
5042 visit_load_const(ctx, nir_instr_as_load_const(instr));
5043 break;
5044 case nir_instr_type_intrinsic:
5045 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5046 break;
5047 case nir_instr_type_tex:
5048 visit_tex(ctx, nir_instr_as_tex(instr));
5049 break;
5050 case nir_instr_type_phi:
5051 visit_phi(ctx, nir_instr_as_phi(instr));
5052 break;
5053 case nir_instr_type_ssa_undef:
5054 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5055 break;
5056 case nir_instr_type_jump:
5057 visit_jump(ctx, nir_instr_as_jump(instr));
5058 break;
5059 default:
5060 fprintf(stderr, "Unknown NIR instr type: ");
5061 nir_print_instr(instr, stderr);
5062 fprintf(stderr, "\n");
5063 abort();
5064 }
5065 }
5066
5067 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5068 }
5069
5070 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5071 {
5072 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5073
5074 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5075 LLVMBasicBlockRef merge_block =
5076 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5077 LLVMBasicBlockRef if_block =
5078 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5079 LLVMBasicBlockRef else_block = merge_block;
5080 if (!exec_list_is_empty(&if_stmt->else_list))
5081 else_block = LLVMAppendBasicBlockInContext(
5082 ctx->ac.context, fn, "");
5083
5084 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5085 ctx->ac.i32_0, "");
5086 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5087
5088 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5089 visit_cf_list(ctx, &if_stmt->then_list);
5090 if (LLVMGetInsertBlock(ctx->ac.builder))
5091 LLVMBuildBr(ctx->ac.builder, merge_block);
5092
5093 if (!exec_list_is_empty(&if_stmt->else_list)) {
5094 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5095 visit_cf_list(ctx, &if_stmt->else_list);
5096 if (LLVMGetInsertBlock(ctx->ac.builder))
5097 LLVMBuildBr(ctx->ac.builder, merge_block);
5098 }
5099
5100 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5101 }
5102
5103 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5104 {
5105 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5106 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5107 LLVMBasicBlockRef break_parent = ctx->break_block;
5108
5109 ctx->continue_block =
5110 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5111 ctx->break_block =
5112 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5113
5114 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5115 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5116 visit_cf_list(ctx, &loop->body);
5117
5118 if (LLVMGetInsertBlock(ctx->ac.builder))
5119 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5120 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5121
5122 ctx->continue_block = continue_parent;
5123 ctx->break_block = break_parent;
5124 }
5125
5126 static void visit_cf_list(struct ac_nir_context *ctx,
5127 struct exec_list *list)
5128 {
5129 foreach_list_typed(nir_cf_node, node, node, list)
5130 {
5131 switch (node->type) {
5132 case nir_cf_node_block:
5133 visit_block(ctx, nir_cf_node_as_block(node));
5134 break;
5135
5136 case nir_cf_node_if:
5137 visit_if(ctx, nir_cf_node_as_if(node));
5138 break;
5139
5140 case nir_cf_node_loop:
5141 visit_loop(ctx, nir_cf_node_as_loop(node));
5142 break;
5143
5144 default:
5145 assert(0);
5146 }
5147 }
5148 }
5149
5150 static void
5151 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5152 struct nir_variable *variable)
5153 {
5154 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5155 LLVMValueRef t_offset;
5156 LLVMValueRef t_list;
5157 LLVMValueRef input;
5158 LLVMValueRef buffer_index;
5159 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5160 int idx = variable->data.location;
5161 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5162
5163 variable->data.driver_location = idx * 4;
5164
5165 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5166 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5167 ctx->abi.start_instance, "");
5168 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5169 ctx->shader_info->vs.vgpr_comp_cnt);
5170 } else
5171 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5172 ctx->abi.base_vertex, "");
5173
5174 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5175 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5176
5177 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5178
5179 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5180 buffer_index,
5181 ctx->ac.i32_0,
5182 true);
5183
5184 for (unsigned chan = 0; chan < 4; chan++) {
5185 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5186 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5187 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5188 input, llvm_chan, ""));
5189 }
5190 }
5191 }
5192
5193 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5194 unsigned attr,
5195 LLVMValueRef interp_param,
5196 LLVMValueRef prim_mask,
5197 LLVMValueRef result[4])
5198 {
5199 LLVMValueRef attr_number;
5200 unsigned chan;
5201 LLVMValueRef i, j;
5202 bool interp = interp_param != NULL;
5203
5204 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5205
5206 /* fs.constant returns the param from the middle vertex, so it's not
5207 * really useful for flat shading. It's meant to be used for custom
5208 * interpolation (but the intrinsic can't fetch from the other two
5209 * vertices).
5210 *
5211 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5212 * to do the right thing. The only reason we use fs.constant is that
5213 * fs.interp cannot be used on integers, because they can be equal
5214 * to NaN.
5215 */
5216 if (interp) {
5217 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5218 ctx->ac.v2f32, "");
5219
5220 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5221 ctx->ac.i32_0, "");
5222 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5223 ctx->ac.i32_1, "");
5224 }
5225
5226 for (chan = 0; chan < 4; chan++) {
5227 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5228
5229 if (interp) {
5230 result[chan] = ac_build_fs_interp(&ctx->ac,
5231 llvm_chan,
5232 attr_number,
5233 prim_mask, i, j);
5234 } else {
5235 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5236 LLVMConstInt(ctx->ac.i32, 2, false),
5237 llvm_chan,
5238 attr_number,
5239 prim_mask);
5240 }
5241 }
5242 }
5243
5244 static void
5245 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5246 struct nir_variable *variable)
5247 {
5248 int idx = variable->data.location;
5249 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5250 LLVMValueRef interp;
5251
5252 variable->data.driver_location = idx * 4;
5253 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5254
5255 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5256 unsigned interp_type;
5257 if (variable->data.sample) {
5258 interp_type = INTERP_SAMPLE;
5259 ctx->shader_info->info.ps.force_persample = true;
5260 } else if (variable->data.centroid)
5261 interp_type = INTERP_CENTROID;
5262 else
5263 interp_type = INTERP_CENTER;
5264
5265 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5266 } else
5267 interp = NULL;
5268
5269 for (unsigned i = 0; i < attrib_count; ++i)
5270 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5271
5272 }
5273
5274 static void
5275 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5276 struct nir_shader *nir) {
5277 nir_foreach_variable(variable, &nir->inputs)
5278 handle_vs_input_decl(ctx, variable);
5279 }
5280
5281 static void
5282 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5283 struct nir_shader *nir)
5284 {
5285 if (!ctx->options->key.fs.multisample)
5286 return;
5287
5288 bool uses_center = false;
5289 bool uses_centroid = false;
5290 nir_foreach_variable(variable, &nir->inputs) {
5291 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5292 variable->data.sample)
5293 continue;
5294
5295 if (variable->data.centroid)
5296 uses_centroid = true;
5297 else
5298 uses_center = true;
5299 }
5300
5301 if (uses_center && uses_centroid) {
5302 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5303 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5304 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5305 }
5306 }
5307
5308 static void
5309 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5310 struct nir_shader *nir)
5311 {
5312 prepare_interp_optimize(ctx, nir);
5313
5314 nir_foreach_variable(variable, &nir->inputs)
5315 handle_fs_input_decl(ctx, variable);
5316
5317 unsigned index = 0;
5318
5319 if (ctx->shader_info->info.ps.uses_input_attachments ||
5320 ctx->shader_info->info.needs_multiview_view_index)
5321 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5322
5323 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5324 LLVMValueRef interp_param;
5325 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5326
5327 if (!(ctx->input_mask & (1ull << i)))
5328 continue;
5329
5330 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5331 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5332 interp_param = *inputs;
5333 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5334 inputs);
5335
5336 if (!interp_param)
5337 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5338 ++index;
5339 } else if (i == VARYING_SLOT_POS) {
5340 for(int i = 0; i < 3; ++i)
5341 inputs[i] = ctx->abi.frag_pos[i];
5342
5343 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5344 ctx->abi.frag_pos[3]);
5345 }
5346 }
5347 ctx->shader_info->fs.num_interp = index;
5348 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5349 ctx->shader_info->fs.has_pcoord = true;
5350 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5351 ctx->shader_info->fs.prim_id_input = true;
5352 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5353 ctx->shader_info->fs.layer_input = true;
5354 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5355
5356 if (ctx->shader_info->info.needs_multiview_view_index)
5357 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5358 }
5359
5360 static LLVMValueRef
5361 ac_build_alloca(struct ac_llvm_context *ac,
5362 LLVMTypeRef type,
5363 const char *name)
5364 {
5365 LLVMBuilderRef builder = ac->builder;
5366 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5367 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5368 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5369 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5370 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5371 LLVMValueRef res;
5372
5373 if (first_instr) {
5374 LLVMPositionBuilderBefore(first_builder, first_instr);
5375 } else {
5376 LLVMPositionBuilderAtEnd(first_builder, first_block);
5377 }
5378
5379 res = LLVMBuildAlloca(first_builder, type, name);
5380 LLVMBuildStore(builder, LLVMConstNull(type), res);
5381
5382 LLVMDisposeBuilder(first_builder);
5383
5384 return res;
5385 }
5386
5387 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5388 LLVMTypeRef type,
5389 const char *name)
5390 {
5391 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5392 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5393 return ptr;
5394 }
5395
5396 static void
5397 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5398 struct nir_variable *variable,
5399 struct nir_shader *shader,
5400 gl_shader_stage stage)
5401 {
5402 int idx = variable->data.location + variable->data.index;
5403 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5404 uint64_t mask_attribs;
5405
5406 variable->data.driver_location = idx * 4;
5407
5408 /* tess ctrl has it's own load/store paths for outputs */
5409 if (stage == MESA_SHADER_TESS_CTRL)
5410 return;
5411
5412 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5413 if (stage == MESA_SHADER_VERTEX ||
5414 stage == MESA_SHADER_TESS_EVAL ||
5415 stage == MESA_SHADER_GEOMETRY) {
5416 if (idx == VARYING_SLOT_CLIP_DIST0) {
5417 int length = shader->info.clip_distance_array_size +
5418 shader->info.cull_distance_array_size;
5419 if (stage == MESA_SHADER_VERTEX) {
5420 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5421 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5422 }
5423 if (stage == MESA_SHADER_TESS_EVAL) {
5424 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5425 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5426 }
5427
5428 if (length > 4)
5429 attrib_count = 2;
5430 else
5431 attrib_count = 1;
5432 mask_attribs = 1ull << idx;
5433 }
5434 }
5435
5436 ctx->output_mask |= mask_attribs;
5437 }
5438
5439 static void
5440 handle_shader_output_decl(struct ac_nir_context *ctx,
5441 struct nir_shader *nir,
5442 struct nir_variable *variable)
5443 {
5444 unsigned output_loc = variable->data.driver_location / 4;
5445 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5446
5447 /* tess ctrl has it's own load/store paths for outputs */
5448 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5449 return;
5450
5451 if (ctx->stage == MESA_SHADER_VERTEX ||
5452 ctx->stage == MESA_SHADER_TESS_EVAL ||
5453 ctx->stage == MESA_SHADER_GEOMETRY) {
5454 int idx = variable->data.location + variable->data.index;
5455 if (idx == VARYING_SLOT_CLIP_DIST0) {
5456 int length = nir->info.clip_distance_array_size +
5457 nir->info.cull_distance_array_size;
5458
5459 if (length > 4)
5460 attrib_count = 2;
5461 else
5462 attrib_count = 1;
5463 }
5464 }
5465
5466 for (unsigned i = 0; i < attrib_count; ++i) {
5467 for (unsigned chan = 0; chan < 4; chan++) {
5468 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5469 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5470 }
5471 }
5472 }
5473
5474 static LLVMTypeRef
5475 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5476 enum glsl_base_type type)
5477 {
5478 switch (type) {
5479 case GLSL_TYPE_INT:
5480 case GLSL_TYPE_UINT:
5481 case GLSL_TYPE_BOOL:
5482 case GLSL_TYPE_SUBROUTINE:
5483 return ctx->ac.i32;
5484 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5485 return ctx->ac.f32;
5486 case GLSL_TYPE_INT64:
5487 case GLSL_TYPE_UINT64:
5488 return ctx->ac.i64;
5489 case GLSL_TYPE_DOUBLE:
5490 return ctx->ac.f64;
5491 default:
5492 unreachable("unknown GLSL type");
5493 }
5494 }
5495
5496 static LLVMTypeRef
5497 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5498 const struct glsl_type *type)
5499 {
5500 if (glsl_type_is_scalar(type)) {
5501 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5502 }
5503
5504 if (glsl_type_is_vector(type)) {
5505 return LLVMVectorType(
5506 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5507 glsl_get_vector_elements(type));
5508 }
5509
5510 if (glsl_type_is_matrix(type)) {
5511 return LLVMArrayType(
5512 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5513 glsl_get_matrix_columns(type));
5514 }
5515
5516 if (glsl_type_is_array(type)) {
5517 return LLVMArrayType(
5518 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5519 glsl_get_length(type));
5520 }
5521
5522 assert(glsl_type_is_struct(type));
5523
5524 LLVMTypeRef member_types[glsl_get_length(type)];
5525
5526 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5527 member_types[i] =
5528 glsl_to_llvm_type(ctx,
5529 glsl_get_struct_field(type, i));
5530 }
5531
5532 return LLVMStructTypeInContext(ctx->context, member_types,
5533 glsl_get_length(type), false);
5534 }
5535
5536 static void
5537 setup_locals(struct ac_nir_context *ctx,
5538 struct nir_function *func)
5539 {
5540 int i, j;
5541 ctx->num_locals = 0;
5542 nir_foreach_variable(variable, &func->impl->locals) {
5543 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5544 variable->data.driver_location = ctx->num_locals * 4;
5545 ctx->num_locals += attrib_count;
5546 }
5547 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5548 if (!ctx->locals)
5549 return;
5550
5551 for (i = 0; i < ctx->num_locals; i++) {
5552 for (j = 0; j < 4; j++) {
5553 ctx->locals[i * 4 + j] =
5554 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5555 }
5556 }
5557 }
5558
5559 static void
5560 setup_shared(struct ac_nir_context *ctx,
5561 struct nir_shader *nir)
5562 {
5563 nir_foreach_variable(variable, &nir->shared) {
5564 LLVMValueRef shared =
5565 LLVMAddGlobalInAddressSpace(
5566 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5567 variable->name ? variable->name : "",
5568 LOCAL_ADDR_SPACE);
5569 _mesa_hash_table_insert(ctx->vars, variable, shared);
5570 }
5571 }
5572
5573 static LLVMValueRef
5574 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5575 {
5576 v = ac_to_float(ctx, v);
5577 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5578 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5579 }
5580
5581
5582 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5583 LLVMValueRef src0, LLVMValueRef src1)
5584 {
5585 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5586 LLVMValueRef comp[2];
5587
5588 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5589 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5590 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5591 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5592 }
5593
5594 /* Initialize arguments for the shader export intrinsic */
5595 static void
5596 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5597 LLVMValueRef *values,
5598 unsigned target,
5599 struct ac_export_args *args)
5600 {
5601 /* Default is 0xf. Adjusted below depending on the format. */
5602 args->enabled_channels = 0xf;
5603
5604 /* Specify whether the EXEC mask represents the valid mask */
5605 args->valid_mask = 0;
5606
5607 /* Specify whether this is the last export */
5608 args->done = 0;
5609
5610 /* Specify the target we are exporting */
5611 args->target = target;
5612
5613 args->compr = false;
5614 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5615 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5616 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5617 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5618
5619 if (!values)
5620 return;
5621
5622 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5623 LLVMValueRef val[4];
5624 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5625 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5626 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5627 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5628
5629 switch(col_format) {
5630 case V_028714_SPI_SHADER_ZERO:
5631 args->enabled_channels = 0; /* writemask */
5632 args->target = V_008DFC_SQ_EXP_NULL;
5633 break;
5634
5635 case V_028714_SPI_SHADER_32_R:
5636 args->enabled_channels = 1;
5637 args->out[0] = values[0];
5638 break;
5639
5640 case V_028714_SPI_SHADER_32_GR:
5641 args->enabled_channels = 0x3;
5642 args->out[0] = values[0];
5643 args->out[1] = values[1];
5644 break;
5645
5646 case V_028714_SPI_SHADER_32_AR:
5647 args->enabled_channels = 0x9;
5648 args->out[0] = values[0];
5649 args->out[3] = values[3];
5650 break;
5651
5652 case V_028714_SPI_SHADER_FP16_ABGR:
5653 args->compr = 1;
5654
5655 for (unsigned chan = 0; chan < 2; chan++) {
5656 LLVMValueRef pack_args[2] = {
5657 values[2 * chan],
5658 values[2 * chan + 1]
5659 };
5660 LLVMValueRef packed;
5661
5662 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5663 args->out[chan] = packed;
5664 }
5665 break;
5666
5667 case V_028714_SPI_SHADER_UNORM16_ABGR:
5668 for (unsigned chan = 0; chan < 4; chan++) {
5669 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5670 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5671 LLVMConstReal(ctx->ac.f32, 65535), "");
5672 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5673 LLVMConstReal(ctx->ac.f32, 0.5), "");
5674 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5675 ctx->ac.i32, "");
5676 }
5677
5678 args->compr = 1;
5679 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5680 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5681 break;
5682
5683 case V_028714_SPI_SHADER_SNORM16_ABGR:
5684 for (unsigned chan = 0; chan < 4; chan++) {
5685 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5686 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5687 LLVMConstReal(ctx->ac.f32, 32767), "");
5688
5689 /* If positive, add 0.5, else add -0.5. */
5690 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5691 LLVMBuildSelect(ctx->builder,
5692 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5693 val[chan], ctx->ac.f32_0, ""),
5694 LLVMConstReal(ctx->ac.f32, 0.5),
5695 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5696 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5697 }
5698
5699 args->compr = 1;
5700 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5701 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5702 break;
5703
5704 case V_028714_SPI_SHADER_UINT16_ABGR: {
5705 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5706 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5707 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5708
5709 for (unsigned chan = 0; chan < 4; chan++) {
5710 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5711 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5712 }
5713
5714 args->compr = 1;
5715 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5716 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5717 break;
5718 }
5719
5720 case V_028714_SPI_SHADER_SINT16_ABGR: {
5721 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5722 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5723 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5724 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5725 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5726 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5727
5728 /* Clamp. */
5729 for (unsigned chan = 0; chan < 4; chan++) {
5730 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5731 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5732 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5733 }
5734
5735 args->compr = 1;
5736 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5737 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5738 break;
5739 }
5740
5741 default:
5742 case V_028714_SPI_SHADER_32_ABGR:
5743 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5744 break;
5745 }
5746 } else
5747 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5748
5749 for (unsigned i = 0; i < 4; ++i)
5750 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5751 }
5752
5753 static void
5754 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5755 bool export_prim_id,
5756 struct ac_vs_output_info *outinfo)
5757 {
5758 uint32_t param_count = 0;
5759 unsigned target;
5760 unsigned pos_idx, num_pos_exports = 0;
5761 struct ac_export_args args, pos_args[4] = {};
5762 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5763 int i;
5764
5765 if (ctx->options->key.has_multiview_view_index) {
5766 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5767 if(!*tmp_out) {
5768 for(unsigned i = 0; i < 4; ++i)
5769 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5770 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5771 }
5772
5773 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5774 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5775 }
5776
5777 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5778 sizeof(outinfo->vs_output_param_offset));
5779
5780 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5781 LLVMValueRef slots[8];
5782 unsigned j;
5783
5784 if (outinfo->cull_dist_mask)
5785 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5786
5787 i = VARYING_SLOT_CLIP_DIST0;
5788 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5789 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5790 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5791
5792 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5793 slots[i] = LLVMGetUndef(ctx->ac.f32);
5794
5795 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5796 target = V_008DFC_SQ_EXP_POS + 3;
5797 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5798 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5799 &args, sizeof(args));
5800 }
5801
5802 target = V_008DFC_SQ_EXP_POS + 2;
5803 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5804 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5805 &args, sizeof(args));
5806
5807 }
5808
5809 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5810 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5811 for (unsigned j = 0; j < 4; j++)
5812 pos_values[j] = LLVMBuildLoad(ctx->builder,
5813 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5814 }
5815 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5816
5817 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5818 outinfo->writes_pointsize = true;
5819 psize_value = LLVMBuildLoad(ctx->builder,
5820 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5821 }
5822
5823 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5824 outinfo->writes_layer = true;
5825 layer_value = LLVMBuildLoad(ctx->builder,
5826 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5827 }
5828
5829 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5830 outinfo->writes_viewport_index = true;
5831 viewport_index_value = LLVMBuildLoad(ctx->builder,
5832 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5833 }
5834
5835 if (outinfo->writes_pointsize ||
5836 outinfo->writes_layer ||
5837 outinfo->writes_viewport_index) {
5838 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5839 (outinfo->writes_layer == true ? 4 : 0));
5840 pos_args[1].valid_mask = 0;
5841 pos_args[1].done = 0;
5842 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5843 pos_args[1].compr = 0;
5844 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5845 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5846 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5847 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5848
5849 if (outinfo->writes_pointsize == true)
5850 pos_args[1].out[0] = psize_value;
5851 if (outinfo->writes_layer == true)
5852 pos_args[1].out[2] = layer_value;
5853 if (outinfo->writes_viewport_index == true) {
5854 if (ctx->options->chip_class >= GFX9) {
5855 /* GFX9 has the layer in out.z[10:0] and the viewport
5856 * index in out.z[19:16].
5857 */
5858 LLVMValueRef v = viewport_index_value;
5859 v = ac_to_integer(&ctx->ac, v);
5860 v = LLVMBuildShl(ctx->builder, v,
5861 LLVMConstInt(ctx->ac.i32, 16, false),
5862 "");
5863 v = LLVMBuildOr(ctx->builder, v,
5864 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5865
5866 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5867 pos_args[1].enabled_channels |= 1 << 2;
5868 } else {
5869 pos_args[1].out[3] = viewport_index_value;
5870 pos_args[1].enabled_channels |= 1 << 3;
5871 }
5872 }
5873 }
5874 for (i = 0; i < 4; i++) {
5875 if (pos_args[i].out[0])
5876 num_pos_exports++;
5877 }
5878
5879 pos_idx = 0;
5880 for (i = 0; i < 4; i++) {
5881 if (!pos_args[i].out[0])
5882 continue;
5883
5884 /* Specify the target we are exporting */
5885 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5886 if (pos_idx == num_pos_exports)
5887 pos_args[i].done = 1;
5888 ac_build_export(&ctx->ac, &pos_args[i]);
5889 }
5890
5891 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5892 LLVMValueRef values[4];
5893 if (!(ctx->output_mask & (1ull << i)))
5894 continue;
5895
5896 for (unsigned j = 0; j < 4; j++)
5897 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5898 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5899
5900 if (i == VARYING_SLOT_LAYER) {
5901 target = V_008DFC_SQ_EXP_PARAM + param_count;
5902 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5903 param_count++;
5904 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5905 target = V_008DFC_SQ_EXP_PARAM + param_count;
5906 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5907 param_count++;
5908 } else if (i >= VARYING_SLOT_VAR0) {
5909 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5910 target = V_008DFC_SQ_EXP_PARAM + param_count;
5911 outinfo->vs_output_param_offset[i] = param_count;
5912 param_count++;
5913 } else
5914 continue;
5915
5916 si_llvm_init_export_args(ctx, values, target, &args);
5917
5918 if (target >= V_008DFC_SQ_EXP_POS &&
5919 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5920 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5921 &args, sizeof(args));
5922 } else {
5923 ac_build_export(&ctx->ac, &args);
5924 }
5925 }
5926
5927 if (export_prim_id) {
5928 LLVMValueRef values[4];
5929 target = V_008DFC_SQ_EXP_PARAM + param_count;
5930 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5931 param_count++;
5932
5933 values[0] = ctx->vs_prim_id;
5934 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5935 ctx->shader_info->vs.vgpr_comp_cnt);
5936 for (unsigned j = 1; j < 4; j++)
5937 values[j] = ctx->ac.f32_0;
5938 si_llvm_init_export_args(ctx, values, target, &args);
5939 ac_build_export(&ctx->ac, &args);
5940 outinfo->export_prim_id = true;
5941 }
5942
5943 outinfo->pos_exports = num_pos_exports;
5944 outinfo->param_exports = param_count;
5945 }
5946
5947 static void
5948 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5949 struct ac_es_output_info *outinfo)
5950 {
5951 int j;
5952 uint64_t max_output_written = 0;
5953 LLVMValueRef lds_base = NULL;
5954
5955 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5956 int param_index;
5957 int length = 4;
5958
5959 if (!(ctx->output_mask & (1ull << i)))
5960 continue;
5961
5962 if (i == VARYING_SLOT_CLIP_DIST0)
5963 length = ctx->num_output_clips + ctx->num_output_culls;
5964
5965 param_index = shader_io_get_unique_index(i);
5966
5967 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5968 }
5969
5970 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5971
5972 if (ctx->ac.chip_class >= GFX9) {
5973 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5974 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5975 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5976 LLVMConstInt(ctx->ac.i32, 24, false),
5977 LLVMConstInt(ctx->ac.i32, 4, false), false);
5978 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5979 LLVMBuildMul(ctx->ac.builder, wave_idx,
5980 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5981 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5982 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5983 }
5984
5985 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5986 LLVMValueRef dw_addr;
5987 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5988 int param_index;
5989 int length = 4;
5990
5991 if (!(ctx->output_mask & (1ull << i)))
5992 continue;
5993
5994 if (i == VARYING_SLOT_CLIP_DIST0)
5995 length = ctx->num_output_clips + ctx->num_output_culls;
5996
5997 param_index = shader_io_get_unique_index(i);
5998
5999 if (lds_base) {
6000 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6001 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6002 "");
6003 }
6004 for (j = 0; j < length; j++) {
6005 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6006 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6007
6008 if (ctx->ac.chip_class >= GFX9) {
6009 ac_lds_store(&ctx->ac, dw_addr,
6010 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6011 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6012 } else {
6013 ac_build_buffer_store_dword(&ctx->ac,
6014 ctx->esgs_ring,
6015 out_val, 1,
6016 NULL, ctx->es2gs_offset,
6017 (4 * param_index + j) * 4,
6018 1, 1, true, true);
6019 }
6020 }
6021 }
6022 }
6023
6024 static void
6025 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6026 {
6027 LLVMValueRef vertex_id = ctx->rel_auto_id;
6028 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6029 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6030 vertex_dw_stride, "");
6031
6032 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6033 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6034 int length = 4;
6035
6036 if (!(ctx->output_mask & (1ull << i)))
6037 continue;
6038
6039 if (i == VARYING_SLOT_CLIP_DIST0)
6040 length = ctx->num_output_clips + ctx->num_output_culls;
6041 int param = shader_io_get_unique_index(i);
6042 mark_tess_output(ctx, false, param);
6043 if (length > 4)
6044 mark_tess_output(ctx, false, param + 1);
6045 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6046 LLVMConstInt(ctx->ac.i32, param * 4, false),
6047 "");
6048 for (unsigned j = 0; j < length; j++) {
6049 ac_lds_store(&ctx->ac, dw_addr,
6050 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6051 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6052 }
6053 }
6054 }
6055
6056 struct ac_build_if_state
6057 {
6058 struct nir_to_llvm_context *ctx;
6059 LLVMValueRef condition;
6060 LLVMBasicBlockRef entry_block;
6061 LLVMBasicBlockRef true_block;
6062 LLVMBasicBlockRef false_block;
6063 LLVMBasicBlockRef merge_block;
6064 };
6065
6066 static LLVMBasicBlockRef
6067 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6068 {
6069 LLVMBasicBlockRef current_block;
6070 LLVMBasicBlockRef next_block;
6071 LLVMBasicBlockRef new_block;
6072
6073 /* get current basic block */
6074 current_block = LLVMGetInsertBlock(ctx->builder);
6075
6076 /* chqeck if there's another block after this one */
6077 next_block = LLVMGetNextBasicBlock(current_block);
6078 if (next_block) {
6079 /* insert the new block before the next block */
6080 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6081 }
6082 else {
6083 /* append new block after current block */
6084 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6085 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6086 }
6087 return new_block;
6088 }
6089
6090 static void
6091 ac_nir_build_if(struct ac_build_if_state *ifthen,
6092 struct nir_to_llvm_context *ctx,
6093 LLVMValueRef condition)
6094 {
6095 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6096
6097 memset(ifthen, 0, sizeof *ifthen);
6098 ifthen->ctx = ctx;
6099 ifthen->condition = condition;
6100 ifthen->entry_block = block;
6101
6102 /* create endif/merge basic block for the phi functions */
6103 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6104
6105 /* create/insert true_block before merge_block */
6106 ifthen->true_block =
6107 LLVMInsertBasicBlockInContext(ctx->context,
6108 ifthen->merge_block,
6109 "if-true-block");
6110
6111 /* successive code goes into the true block */
6112 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6113 }
6114
6115 /**
6116 * End a conditional.
6117 */
6118 static void
6119 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6120 {
6121 LLVMBuilderRef builder = ifthen->ctx->builder;
6122
6123 /* Insert branch to the merge block from current block */
6124 LLVMBuildBr(builder, ifthen->merge_block);
6125
6126 /*
6127 * Now patch in the various branch instructions.
6128 */
6129
6130 /* Insert the conditional branch instruction at the end of entry_block */
6131 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6132 if (ifthen->false_block) {
6133 /* we have an else clause */
6134 LLVMBuildCondBr(builder, ifthen->condition,
6135 ifthen->true_block, ifthen->false_block);
6136 }
6137 else {
6138 /* no else clause */
6139 LLVMBuildCondBr(builder, ifthen->condition,
6140 ifthen->true_block, ifthen->merge_block);
6141 }
6142
6143 /* Resume building code at end of the ifthen->merge_block */
6144 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6145 }
6146
6147 static void
6148 write_tess_factors(struct nir_to_llvm_context *ctx)
6149 {
6150 unsigned stride, outer_comps, inner_comps;
6151 struct ac_build_if_state if_ctx, inner_if_ctx;
6152 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6153 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6154 unsigned tess_inner_index, tess_outer_index;
6155 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6156 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6157 int i;
6158 emit_barrier(ctx);
6159
6160 switch (ctx->options->key.tcs.primitive_mode) {
6161 case GL_ISOLINES:
6162 stride = 2;
6163 outer_comps = 2;
6164 inner_comps = 0;
6165 break;
6166 case GL_TRIANGLES:
6167 stride = 4;
6168 outer_comps = 3;
6169 inner_comps = 1;
6170 break;
6171 case GL_QUADS:
6172 stride = 6;
6173 outer_comps = 4;
6174 inner_comps = 2;
6175 break;
6176 default:
6177 return;
6178 }
6179
6180 ac_nir_build_if(&if_ctx, ctx,
6181 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6182 invocation_id, ctx->ac.i32_0, ""));
6183
6184 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6185 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6186
6187 mark_tess_output(ctx, true, tess_inner_index);
6188 mark_tess_output(ctx, true, tess_outer_index);
6189 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6190 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6191 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6192 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6193 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6194
6195 for (i = 0; i < 4; i++) {
6196 inner[i] = LLVMGetUndef(ctx->ac.i32);
6197 outer[i] = LLVMGetUndef(ctx->ac.i32);
6198 }
6199
6200 // LINES reverseal
6201 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6202 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6203 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6204 ctx->ac.i32_1, "");
6205 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6206 } else {
6207 for (i = 0; i < outer_comps; i++) {
6208 outer[i] = out[i] =
6209 ac_lds_load(&ctx->ac, lds_outer);
6210 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6211 ctx->ac.i32_1, "");
6212 }
6213 for (i = 0; i < inner_comps; i++) {
6214 inner[i] = out[outer_comps+i] =
6215 ac_lds_load(&ctx->ac, lds_inner);
6216 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6217 ctx->ac.i32_1, "");
6218 }
6219 }
6220
6221 /* Convert the outputs to vectors for stores. */
6222 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6223 vec1 = NULL;
6224
6225 if (stride > 4)
6226 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6227
6228
6229 buffer = ctx->hs_ring_tess_factor;
6230 tf_base = ctx->tess_factor_offset;
6231 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6232 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6233 unsigned tf_offset = 0;
6234
6235 if (ctx->options->chip_class <= VI) {
6236 ac_nir_build_if(&inner_if_ctx, ctx,
6237 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6238 rel_patch_id, ctx->ac.i32_0, ""));
6239
6240 /* Store the dynamic HS control word. */
6241 ac_build_buffer_store_dword(&ctx->ac, buffer,
6242 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6243 1, ctx->ac.i32_0, tf_base,
6244 0, 1, 0, true, false);
6245 tf_offset += 4;
6246
6247 ac_nir_build_endif(&inner_if_ctx);
6248 }
6249
6250 /* Store the tessellation factors. */
6251 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6252 MIN2(stride, 4), byteoffset, tf_base,
6253 tf_offset, 1, 0, true, false);
6254 if (vec1)
6255 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6256 stride - 4, byteoffset, tf_base,
6257 16 + tf_offset, 1, 0, true, false);
6258
6259 //store to offchip for TES to read - only if TES reads them
6260 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6261 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6262 LLVMValueRef tf_inner_offset;
6263 unsigned param_outer, param_inner;
6264
6265 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6266 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6267 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6268
6269 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6270 util_next_power_of_two(outer_comps));
6271
6272 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6273 outer_comps, tf_outer_offset,
6274 ctx->oc_lds, 0, 1, 0, true, false);
6275 if (inner_comps) {
6276 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6277 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6278 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6279
6280 inner_vec = inner_comps == 1 ? inner[0] :
6281 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6282 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6283 inner_comps, tf_inner_offset,
6284 ctx->oc_lds, 0, 1, 0, true, false);
6285 }
6286 }
6287 ac_nir_build_endif(&if_ctx);
6288 }
6289
6290 static void
6291 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6292 {
6293 write_tess_factors(ctx);
6294 }
6295
6296 static bool
6297 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6298 LLVMValueRef *color, unsigned param, bool is_last,
6299 struct ac_export_args *args)
6300 {
6301 /* Export */
6302 si_llvm_init_export_args(ctx, color, param,
6303 args);
6304
6305 if (is_last) {
6306 args->valid_mask = 1; /* whether the EXEC mask is valid */
6307 args->done = 1; /* DONE bit */
6308 } else if (!args->enabled_channels)
6309 return false; /* unnecessary NULL export */
6310
6311 return true;
6312 }
6313
6314 static void
6315 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6316 LLVMValueRef depth, LLVMValueRef stencil,
6317 LLVMValueRef samplemask)
6318 {
6319 struct ac_export_args args;
6320
6321 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6322
6323 ac_build_export(&ctx->ac, &args);
6324 }
6325
6326 static void
6327 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6328 {
6329 unsigned index = 0;
6330 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6331 struct ac_export_args color_args[8];
6332
6333 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6334 LLVMValueRef values[4];
6335
6336 if (!(ctx->output_mask & (1ull << i)))
6337 continue;
6338
6339 if (i == FRAG_RESULT_DEPTH) {
6340 ctx->shader_info->fs.writes_z = true;
6341 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6342 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6343 } else if (i == FRAG_RESULT_STENCIL) {
6344 ctx->shader_info->fs.writes_stencil = true;
6345 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6346 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6347 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6348 ctx->shader_info->fs.writes_sample_mask = true;
6349 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6350 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6351 } else {
6352 bool last = false;
6353 for (unsigned j = 0; j < 4; j++)
6354 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6355 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6356
6357 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6358 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6359
6360 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6361 if (ret)
6362 index++;
6363 }
6364 }
6365
6366 for (unsigned i = 0; i < index; i++)
6367 ac_build_export(&ctx->ac, &color_args[i]);
6368 if (depth || stencil || samplemask)
6369 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6370 else if (!index) {
6371 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6372 ac_build_export(&ctx->ac, &color_args[0]);
6373 }
6374
6375 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6376 }
6377
6378 static void
6379 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6380 {
6381 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6382 }
6383
6384 static void
6385 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6386 LLVMValueRef *addrs)
6387 {
6388 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6389
6390 switch (ctx->stage) {
6391 case MESA_SHADER_VERTEX:
6392 if (ctx->options->key.vs.as_ls)
6393 handle_ls_outputs_post(ctx);
6394 else if (ctx->options->key.vs.as_es)
6395 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6396 else
6397 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6398 &ctx->shader_info->vs.outinfo);
6399 break;
6400 case MESA_SHADER_FRAGMENT:
6401 handle_fs_outputs_post(ctx);
6402 break;
6403 case MESA_SHADER_GEOMETRY:
6404 emit_gs_epilogue(ctx);
6405 break;
6406 case MESA_SHADER_TESS_CTRL:
6407 handle_tcs_outputs_post(ctx);
6408 break;
6409 case MESA_SHADER_TESS_EVAL:
6410 if (ctx->options->key.tes.as_es)
6411 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6412 else
6413 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6414 &ctx->shader_info->tes.outinfo);
6415 break;
6416 default:
6417 break;
6418 }
6419 }
6420
6421 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6422 {
6423 LLVMPassManagerRef passmgr;
6424 /* Create the pass manager */
6425 passmgr = LLVMCreateFunctionPassManagerForModule(
6426 ctx->module);
6427
6428 /* This pass should eliminate all the load and store instructions */
6429 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6430
6431 /* Add some optimization passes */
6432 LLVMAddScalarReplAggregatesPass(passmgr);
6433 LLVMAddLICMPass(passmgr);
6434 LLVMAddAggressiveDCEPass(passmgr);
6435 LLVMAddCFGSimplificationPass(passmgr);
6436 LLVMAddInstructionCombiningPass(passmgr);
6437
6438 /* Run the pass */
6439 LLVMInitializeFunctionPassManager(passmgr);
6440 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6441 LLVMFinalizeFunctionPassManager(passmgr);
6442
6443 LLVMDisposeBuilder(ctx->builder);
6444 LLVMDisposePassManager(passmgr);
6445 }
6446
6447 static void
6448 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6449 {
6450 struct ac_vs_output_info *outinfo;
6451
6452 switch (ctx->stage) {
6453 case MESA_SHADER_FRAGMENT:
6454 case MESA_SHADER_COMPUTE:
6455 case MESA_SHADER_TESS_CTRL:
6456 case MESA_SHADER_GEOMETRY:
6457 return;
6458 case MESA_SHADER_VERTEX:
6459 if (ctx->options->key.vs.as_ls ||
6460 ctx->options->key.vs.as_es)
6461 return;
6462 outinfo = &ctx->shader_info->vs.outinfo;
6463 break;
6464 case MESA_SHADER_TESS_EVAL:
6465 if (ctx->options->key.vs.as_es)
6466 return;
6467 outinfo = &ctx->shader_info->tes.outinfo;
6468 break;
6469 default:
6470 unreachable("Unhandled shader type");
6471 }
6472
6473 ac_optimize_vs_outputs(&ctx->ac,
6474 ctx->main_function,
6475 outinfo->vs_output_param_offset,
6476 VARYING_SLOT_MAX,
6477 &outinfo->param_exports);
6478 }
6479
6480 static void
6481 ac_setup_rings(struct nir_to_llvm_context *ctx)
6482 {
6483 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6484 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6485 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6486 }
6487
6488 if (ctx->is_gs_copy_shader) {
6489 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6490 }
6491 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6492 LLVMValueRef tmp;
6493 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6494 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6495
6496 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6497
6498 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6499 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6500 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6501 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6502 }
6503
6504 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6505 ctx->stage == MESA_SHADER_TESS_EVAL) {
6506 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6507 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6508 }
6509 }
6510
6511 static unsigned
6512 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6513 const struct nir_shader *nir)
6514 {
6515 switch (nir->info.stage) {
6516 case MESA_SHADER_TESS_CTRL:
6517 return chip_class >= CIK ? 128 : 64;
6518 case MESA_SHADER_GEOMETRY:
6519 return chip_class >= GFX9 ? 128 : 64;
6520 case MESA_SHADER_COMPUTE:
6521 break;
6522 default:
6523 return 0;
6524 }
6525
6526 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6527 nir->info.cs.local_size[1] *
6528 nir->info.cs.local_size[2];
6529 return max_workgroup_size;
6530 }
6531
6532 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6533 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6534 {
6535 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6536 LLVMConstInt(ctx->ac.i32, 8, false),
6537 LLVMConstInt(ctx->ac.i32, 8, false), false);
6538 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6539 ctx->ac.i32_0, "");
6540 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6541 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6542 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6543 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6544 }
6545
6546 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6547 {
6548 for(int i = 5; i >= 0; --i) {
6549 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6550 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6551 LLVMConstInt(ctx->ac.i32, 16, false), false);
6552 }
6553
6554 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6555 LLVMConstInt(ctx->ac.i32, 16, false),
6556 LLVMConstInt(ctx->ac.i32, 8, false), false);
6557 }
6558
6559 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6560 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6561 {
6562 struct ac_nir_context ctx = {};
6563 struct nir_function *func;
6564
6565 ctx.ac = *ac;
6566 ctx.abi = abi;
6567
6568 ctx.nctx = nctx;
6569 if (nctx)
6570 nctx->nir = &ctx;
6571
6572 ctx.stage = nir->info.stage;
6573
6574 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6575
6576 nir_foreach_variable(variable, &nir->outputs)
6577 handle_shader_output_decl(&ctx, nir, variable);
6578
6579 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6580 _mesa_key_pointer_equal);
6581 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6582 _mesa_key_pointer_equal);
6583 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6584 _mesa_key_pointer_equal);
6585
6586 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6587
6588 setup_locals(&ctx, func);
6589
6590 if (nir->info.stage == MESA_SHADER_COMPUTE)
6591 setup_shared(&ctx, nir);
6592
6593 visit_cf_list(&ctx, &func->impl->body);
6594 phi_post_pass(&ctx);
6595
6596 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6597 ctx.outputs);
6598
6599 free(ctx.locals);
6600 ralloc_free(ctx.defs);
6601 ralloc_free(ctx.phis);
6602 ralloc_free(ctx.vars);
6603
6604 if (nctx)
6605 nctx->nir = NULL;
6606 }
6607
6608 static
6609 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6610 struct nir_shader *const *shaders,
6611 int shader_count,
6612 struct ac_shader_variant_info *shader_info,
6613 const struct ac_nir_compiler_options *options)
6614 {
6615 struct nir_to_llvm_context ctx = {0};
6616 unsigned i;
6617 ctx.options = options;
6618 ctx.shader_info = shader_info;
6619 ctx.context = LLVMContextCreate();
6620 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6621
6622 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6623 options->family);
6624 ctx.ac.module = ctx.module;
6625 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6626
6627 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6628 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6629 LLVMSetDataLayout(ctx.module, data_layout_str);
6630 LLVMDisposeTargetData(data_layout);
6631 LLVMDisposeMessage(data_layout_str);
6632
6633 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6634 ctx.ac.builder = ctx.builder;
6635
6636 memset(shader_info, 0, sizeof(*shader_info));
6637
6638 for(int i = 0; i < shader_count; ++i)
6639 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6640
6641 for (i = 0; i < AC_UD_MAX_SETS; i++)
6642 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6643 for (i = 0; i < AC_UD_MAX_UD; i++)
6644 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6645
6646 ctx.max_workgroup_size = 0;
6647 for (int i = 0; i < shader_count; ++i) {
6648 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6649 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6650 shaders[i]));
6651 }
6652
6653 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6654 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6655
6656 ctx.abi.inputs = &ctx.inputs[0];
6657 ctx.abi.emit_outputs = handle_shader_outputs_post;
6658 ctx.abi.emit_vertex = visit_emit_vertex;
6659 ctx.abi.load_ubo = radv_load_ubo;
6660 ctx.abi.load_ssbo = radv_load_ssbo;
6661 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6662 ctx.abi.clamp_shadow_reference = false;
6663
6664 if (shader_count >= 2)
6665 ac_init_exec_full_mask(&ctx.ac);
6666
6667 if (ctx.ac.chip_class == GFX9 &&
6668 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6669 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6670
6671 for(int i = 0; i < shader_count; ++i) {
6672 ctx.stage = shaders[i]->info.stage;
6673 ctx.output_mask = 0;
6674 ctx.tess_outputs_written = 0;
6675 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6676 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6677
6678 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6679 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6680 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6681 ctx.abi.load_inputs = load_gs_input;
6682 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6683 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6684 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6685 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6686 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6687 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6688 if (shader_info->info.vs.needs_instance_id) {
6689 ctx.shader_info->vs.vgpr_comp_cnt =
6690 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6691 }
6692 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6693 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6694 }
6695
6696 if (i)
6697 emit_barrier(&ctx);
6698
6699 ac_setup_rings(&ctx);
6700
6701 LLVMBasicBlockRef merge_block;
6702 if (shader_count >= 2) {
6703 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6704 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6705 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6706
6707 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6708 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6709 LLVMConstInt(ctx.ac.i32, 8, false), false);
6710 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6711 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6712 thread_id, count, "");
6713 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6714
6715 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6716 }
6717
6718 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6719 handle_fs_inputs(&ctx, shaders[i]);
6720 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6721 handle_vs_inputs(&ctx, shaders[i]);
6722 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6723 prepare_gs_input_vgprs(&ctx);
6724
6725 nir_foreach_variable(variable, &shaders[i]->outputs)
6726 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6727
6728 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6729
6730 if (shader_count >= 2) {
6731 LLVMBuildBr(ctx.ac.builder, merge_block);
6732 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6733 }
6734
6735 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6736 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6737 shaders[i]->info.cull_distance_array_size > 4;
6738 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6739 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6740 shaders[i]->info.gs.vertices_out;
6741 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6742 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6743 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6744 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6745 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6746 }
6747 }
6748
6749 LLVMBuildRetVoid(ctx.builder);
6750
6751 ac_llvm_finalize_module(&ctx);
6752
6753 if (shader_count == 1)
6754 ac_nir_eliminate_const_vs_outputs(&ctx);
6755
6756 return ctx.module;
6757 }
6758
6759 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6760 {
6761 unsigned *retval = (unsigned *)context;
6762 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6763 char *description = LLVMGetDiagInfoDescription(di);
6764
6765 if (severity == LLVMDSError) {
6766 *retval = 1;
6767 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6768 description);
6769 }
6770
6771 LLVMDisposeMessage(description);
6772 }
6773
6774 static unsigned ac_llvm_compile(LLVMModuleRef M,
6775 struct ac_shader_binary *binary,
6776 LLVMTargetMachineRef tm)
6777 {
6778 unsigned retval = 0;
6779 char *err;
6780 LLVMContextRef llvm_ctx;
6781 LLVMMemoryBufferRef out_buffer;
6782 unsigned buffer_size;
6783 const char *buffer_data;
6784 LLVMBool mem_err;
6785
6786 /* Setup Diagnostic Handler*/
6787 llvm_ctx = LLVMGetModuleContext(M);
6788
6789 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6790 &retval);
6791
6792 /* Compile IR*/
6793 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6794 &err, &out_buffer);
6795
6796 /* Process Errors/Warnings */
6797 if (mem_err) {
6798 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6799 free(err);
6800 retval = 1;
6801 goto out;
6802 }
6803
6804 /* Extract Shader Code*/
6805 buffer_size = LLVMGetBufferSize(out_buffer);
6806 buffer_data = LLVMGetBufferStart(out_buffer);
6807
6808 ac_elf_read(buffer_data, buffer_size, binary);
6809
6810 /* Clean up */
6811 LLVMDisposeMemoryBuffer(out_buffer);
6812
6813 out:
6814 return retval;
6815 }
6816
6817 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6818 LLVMModuleRef llvm_module,
6819 struct ac_shader_binary *binary,
6820 struct ac_shader_config *config,
6821 struct ac_shader_variant_info *shader_info,
6822 gl_shader_stage stage,
6823 bool dump_shader, bool supports_spill)
6824 {
6825 if (dump_shader)
6826 ac_dump_module(llvm_module);
6827
6828 memset(binary, 0, sizeof(*binary));
6829 int v = ac_llvm_compile(llvm_module, binary, tm);
6830 if (v) {
6831 fprintf(stderr, "compile failed\n");
6832 }
6833
6834 if (dump_shader)
6835 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6836
6837 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6838
6839 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6840 LLVMDisposeModule(llvm_module);
6841 LLVMContextDispose(ctx);
6842
6843 if (stage == MESA_SHADER_FRAGMENT) {
6844 shader_info->num_input_vgprs = 0;
6845 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6846 shader_info->num_input_vgprs += 2;
6847 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6848 shader_info->num_input_vgprs += 2;
6849 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6850 shader_info->num_input_vgprs += 2;
6851 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6852 shader_info->num_input_vgprs += 3;
6853 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6854 shader_info->num_input_vgprs += 2;
6855 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6856 shader_info->num_input_vgprs += 2;
6857 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 2;
6859 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 1;
6861 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 1;
6863 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 1;
6865 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 1;
6867 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 1;
6869 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 1;
6871 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 1;
6873 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 1;
6875 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 1;
6877 }
6878 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6879
6880 /* +3 for scratch wave offset and VCC */
6881 config->num_sgprs = MAX2(config->num_sgprs,
6882 shader_info->num_input_sgprs + 3);
6883 }
6884
6885 static void
6886 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6887 {
6888 switch (nir->info.stage) {
6889 case MESA_SHADER_COMPUTE:
6890 for (int i = 0; i < 3; ++i)
6891 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6892 break;
6893 case MESA_SHADER_FRAGMENT:
6894 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6895 break;
6896 case MESA_SHADER_GEOMETRY:
6897 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6898 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6899 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6900 shader_info->gs.invocations = nir->info.gs.invocations;
6901 break;
6902 case MESA_SHADER_TESS_EVAL:
6903 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6904 shader_info->tes.spacing = nir->info.tess.spacing;
6905 shader_info->tes.ccw = nir->info.tess.ccw;
6906 shader_info->tes.point_mode = nir->info.tess.point_mode;
6907 shader_info->tes.as_es = options->key.tes.as_es;
6908 break;
6909 case MESA_SHADER_TESS_CTRL:
6910 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6911 break;
6912 case MESA_SHADER_VERTEX:
6913 shader_info->vs.as_es = options->key.vs.as_es;
6914 shader_info->vs.as_ls = options->key.vs.as_ls;
6915 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6916 if (options->key.vs.as_ls)
6917 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6918 break;
6919 default:
6920 break;
6921 }
6922 }
6923
6924 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6925 struct ac_shader_binary *binary,
6926 struct ac_shader_config *config,
6927 struct ac_shader_variant_info *shader_info,
6928 struct nir_shader *const *nir,
6929 int nir_count,
6930 const struct ac_nir_compiler_options *options,
6931 bool dump_shader)
6932 {
6933
6934 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6935 options);
6936
6937 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6938 for (int i = 0; i < nir_count; ++i)
6939 ac_fill_shader_info(shader_info, nir[i], options);
6940 }
6941
6942 static void
6943 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6944 {
6945 LLVMValueRef args[9];
6946 args[0] = ctx->gsvs_ring;
6947 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6948 args[3] = ctx->ac.i32_0;
6949 args[4] = ctx->ac.i32_1; /* OFFEN */
6950 args[5] = ctx->ac.i32_0; /* IDXEN */
6951 args[6] = ctx->ac.i32_1; /* GLC */
6952 args[7] = ctx->ac.i32_1; /* SLC */
6953 args[8] = ctx->ac.i32_0; /* TFE */
6954
6955 int idx = 0;
6956
6957 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6958 int length = 4;
6959 int slot = idx;
6960 int slot_inc = 1;
6961 if (!(ctx->output_mask & (1ull << i)))
6962 continue;
6963
6964 if (i == VARYING_SLOT_CLIP_DIST0) {
6965 /* unpack clip and cull from a single set of slots */
6966 length = ctx->num_output_clips + ctx->num_output_culls;
6967 if (length > 4)
6968 slot_inc = 2;
6969 }
6970
6971 for (unsigned j = 0; j < length; j++) {
6972 LLVMValueRef value;
6973 args[2] = LLVMConstInt(ctx->ac.i32,
6974 (slot * 4 + j) *
6975 ctx->gs_max_out_vertices * 16 * 4, false);
6976
6977 value = ac_build_intrinsic(&ctx->ac,
6978 "llvm.SI.buffer.load.dword.i32.i32",
6979 ctx->ac.i32, args, 9,
6980 AC_FUNC_ATTR_READONLY |
6981 AC_FUNC_ATTR_LEGACY);
6982
6983 LLVMBuildStore(ctx->builder,
6984 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6985 }
6986 idx += slot_inc;
6987 }
6988 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6989 }
6990
6991 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6992 struct nir_shader *geom_shader,
6993 struct ac_shader_binary *binary,
6994 struct ac_shader_config *config,
6995 struct ac_shader_variant_info *shader_info,
6996 const struct ac_nir_compiler_options *options,
6997 bool dump_shader)
6998 {
6999 struct nir_to_llvm_context ctx = {0};
7000 ctx.context = LLVMContextCreate();
7001 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7002 ctx.options = options;
7003 ctx.shader_info = shader_info;
7004
7005 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7006 options->family);
7007 ctx.ac.module = ctx.module;
7008
7009 ctx.is_gs_copy_shader = true;
7010 LLVMSetTarget(ctx.module, "amdgcn--");
7011
7012 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7013 ctx.ac.builder = ctx.builder;
7014 ctx.stage = MESA_SHADER_VERTEX;
7015
7016 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7017
7018 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7019 ac_setup_rings(&ctx);
7020
7021 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7022 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7023
7024 struct ac_nir_context nir_ctx = {};
7025 nir_ctx.ac = ctx.ac;
7026 nir_ctx.abi = &ctx.abi;
7027
7028 nir_ctx.nctx = &ctx;
7029 ctx.nir = &nir_ctx;
7030
7031 nir_foreach_variable(variable, &geom_shader->outputs) {
7032 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7033 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7034 }
7035
7036 ac_gs_copy_shader_emit(&ctx);
7037
7038 ctx.nir = NULL;
7039
7040 LLVMBuildRetVoid(ctx.builder);
7041
7042 ac_llvm_finalize_module(&ctx);
7043
7044 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7045 MESA_SHADER_VERTEX,
7046 dump_shader, options->supports_spill);
7047 }