2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
52 struct nir_to_llvm_context
;
54 struct ac_nir_context
{
55 struct ac_llvm_context ac
;
56 struct ac_shader_abi
*abi
;
58 gl_shader_stage stage
;
60 struct hash_table
*defs
;
61 struct hash_table
*phis
;
62 struct hash_table
*vars
;
64 LLVMValueRef main_function
;
65 LLVMBasicBlockRef continue_block
;
66 LLVMBasicBlockRef break_block
;
68 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
73 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
76 struct nir_to_llvm_context
{
77 struct ac_llvm_context ac
;
78 const struct ac_nir_compiler_options
*options
;
79 struct ac_shader_variant_info
*shader_info
;
80 struct ac_shader_abi abi
;
81 struct ac_nir_context
*nir
;
83 unsigned max_workgroup_size
;
84 LLVMContextRef context
;
86 LLVMBuilderRef builder
;
87 LLVMValueRef main_function
;
89 struct hash_table
*defs
;
90 struct hash_table
*phis
;
92 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
93 LLVMValueRef ring_offsets
;
94 LLVMValueRef push_constants
;
95 LLVMValueRef view_index
;
96 LLVMValueRef num_work_groups
;
97 LLVMValueRef workgroup_ids
[3];
98 LLVMValueRef local_invocation_ids
;
101 LLVMValueRef vertex_buffers
;
102 LLVMValueRef rel_auto_id
;
103 LLVMValueRef vs_prim_id
;
104 LLVMValueRef ls_out_layout
;
105 LLVMValueRef es2gs_offset
;
107 LLVMValueRef tcs_offchip_layout
;
108 LLVMValueRef tcs_out_offsets
;
109 LLVMValueRef tcs_out_layout
;
110 LLVMValueRef tcs_in_layout
;
112 LLVMValueRef merged_wave_info
;
113 LLVMValueRef tess_factor_offset
;
114 LLVMValueRef tes_rel_patch_id
;
118 LLVMValueRef gsvs_ring_stride
;
119 LLVMValueRef gsvs_num_entries
;
120 LLVMValueRef gs2vs_offset
;
121 LLVMValueRef gs_wave_id
;
122 LLVMValueRef gs_vtx_offset
[6];
124 LLVMValueRef esgs_ring
;
125 LLVMValueRef gsvs_ring
;
126 LLVMValueRef hs_ring_tess_offchip
;
127 LLVMValueRef hs_ring_tess_factor
;
129 LLVMValueRef prim_mask
;
130 LLVMValueRef sample_pos_offset
;
131 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
132 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
134 gl_shader_stage stage
;
136 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
139 uint64_t output_mask
;
140 uint8_t num_output_clips
;
141 uint8_t num_output_culls
;
143 bool is_gs_copy_shader
;
144 LLVMValueRef gs_next_vertex
;
145 unsigned gs_max_out_vertices
;
147 unsigned tes_primitive_mode
;
148 uint64_t tess_outputs_written
;
149 uint64_t tess_patch_outputs_written
;
151 uint32_t tcs_patch_outputs_read
;
152 uint64_t tcs_outputs_read
;
155 static inline struct nir_to_llvm_context
*
156 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
158 struct nir_to_llvm_context
*ctx
= NULL
;
159 return container_of(abi
, ctx
, abi
);
163 nir2llvmtype(struct ac_nir_context
*ctx
,
164 const struct glsl_type
*type
)
166 switch (glsl_get_base_type(glsl_without_array(type
))) {
170 case GLSL_TYPE_UINT64
:
171 case GLSL_TYPE_INT64
:
173 case GLSL_TYPE_DOUBLE
:
175 case GLSL_TYPE_FLOAT
:
178 assert(!"Unsupported type in nir2llvmtype()");
184 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
185 const nir_deref_var
*deref
,
186 enum ac_descriptor_type desc_type
,
187 const nir_tex_instr
*instr
,
188 bool image
, bool write
);
190 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
192 return (index
* 4) + chan
;
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
197 /* handle patch indices separate */
198 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
200 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
202 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
203 return 2 + (slot
- VARYING_SLOT_PATCH0
);
205 if (slot
== VARYING_SLOT_POS
)
207 if (slot
== VARYING_SLOT_PSIZ
)
209 if (slot
== VARYING_SLOT_CLIP_DIST0
)
211 /* 3 is reserved for clip dist as well */
212 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
213 return 4 + (slot
- VARYING_SLOT_VAR0
);
214 unreachable("illegal slot in get unique index\n");
217 static void set_llvm_calling_convention(LLVMValueRef func
,
218 gl_shader_stage stage
)
220 enum radeon_llvm_calling_convention calling_conv
;
223 case MESA_SHADER_VERTEX
:
224 case MESA_SHADER_TESS_EVAL
:
225 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
227 case MESA_SHADER_GEOMETRY
:
228 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
230 case MESA_SHADER_TESS_CTRL
:
231 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
233 case MESA_SHADER_FRAGMENT
:
234 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
236 case MESA_SHADER_COMPUTE
:
237 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
240 unreachable("Unhandle shader type");
243 LLVMSetFunctionCallConv(func
, calling_conv
);
248 LLVMTypeRef types
[MAX_ARGS
];
249 LLVMValueRef
*assign
[MAX_ARGS
];
250 unsigned array_params_mask
;
253 uint8_t num_sgprs_used
;
254 uint8_t num_vgprs_used
;
257 enum ac_arg_regfile
{
263 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
264 LLVMValueRef
*param_ptr
)
266 assert(info
->count
< MAX_ARGS
);
268 info
->assign
[info
->count
] = param_ptr
;
269 info
->types
[info
->count
] = type
;
272 if (regfile
== ARG_SGPR
) {
273 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
276 assert(regfile
== ARG_VGPR
);
277 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
282 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
284 info
->array_params_mask
|= (1 << info
->count
);
285 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
288 static void assign_arguments(LLVMValueRef main_function
,
289 struct arg_info
*info
)
292 for (i
= 0; i
< info
->count
; i
++) {
294 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
299 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
300 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
301 unsigned num_return_elems
,
302 struct arg_info
*args
,
303 unsigned max_workgroup_size
,
306 LLVMTypeRef main_function_type
, ret_type
;
307 LLVMBasicBlockRef main_function_body
;
309 if (num_return_elems
)
310 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
311 num_return_elems
, true);
313 ret_type
= LLVMVoidTypeInContext(ctx
);
315 /* Setup the function */
317 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
318 LLVMValueRef main_function
=
319 LLVMAddFunction(module
, "main", main_function_type
);
321 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
322 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
324 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
325 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
326 if (args
->array_params_mask
& (1 << i
)) {
327 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
328 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
329 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
332 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
336 if (max_workgroup_size
) {
337 ac_llvm_add_target_dep_function_attr(main_function
,
338 "amdgpu-max-work-group-size",
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function
,
344 "less-precise-fpmad",
346 LLVMAddTargetDependentFunctionAttr(main_function
,
349 LLVMAddTargetDependentFunctionAttr(main_function
,
352 LLVMAddTargetDependentFunctionAttr(main_function
,
356 return main_function
;
359 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
361 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
365 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
367 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
368 type
= LLVMGetElementType(type
);
370 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
371 return LLVMGetIntTypeWidth(type
);
373 if (type
== ctx
->f16
)
375 if (type
== ctx
->f32
)
377 if (type
== ctx
->f64
)
380 unreachable("Unhandled type kind in get_elem_bits");
383 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
384 LLVMValueRef param
, unsigned rshift
,
387 LLVMValueRef value
= param
;
389 value
= LLVMBuildLShr(ctx
->builder
, value
,
390 LLVMConstInt(ctx
->i32
, rshift
, false), "");
392 if (rshift
+ bitwidth
< 32) {
393 unsigned mask
= (1 << bitwidth
) - 1;
394 value
= LLVMBuildAnd(ctx
->builder
, value
,
395 LLVMConstInt(ctx
->i32
, mask
, false), "");
400 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
402 switch (ctx
->stage
) {
403 case MESA_SHADER_TESS_CTRL
:
404 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
405 case MESA_SHADER_TESS_EVAL
:
406 return ctx
->tes_rel_patch_id
;
409 unreachable("Illegal stage");
413 /* Tessellation shaders pass outputs to the next shader using LDS.
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
434 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
436 if (ctx
->stage
== MESA_SHADER_VERTEX
)
437 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
438 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
439 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
447 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
449 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
455 return LLVMBuildMul(ctx
->builder
,
456 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
457 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
463 return LLVMBuildMul(ctx
->builder
,
464 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
465 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
471 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
472 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
474 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
480 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
481 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
482 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
484 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
485 LLVMBuildMul(ctx
->builder
, patch_stride
,
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
493 LLVMValueRef patch0_patch_data_offset
=
494 get_tcs_out_patch0_patch_data_offset(ctx
);
495 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
496 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
498 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
499 LLVMBuildMul(ctx
->builder
, patch_stride
,
505 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
506 uint32_t indirect_offset
)
508 ud_info
->sgpr_idx
= *sgpr_idx
;
509 ud_info
->num_sgprs
= num_sgprs
;
510 ud_info
->indirect
= indirect_offset
> 0;
511 ud_info
->indirect_offset
= indirect_offset
;
512 *sgpr_idx
+= num_sgprs
;
516 set_loc_shader(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
519 struct ac_userdata_info
*ud_info
=
520 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
523 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
527 set_loc_desc(struct nir_to_llvm_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
528 uint32_t indirect_offset
)
530 struct ac_userdata_info
*ud_info
=
531 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
534 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
537 struct user_sgpr_info
{
538 bool need_ring_offsets
;
540 bool indirect_all_descriptor_sets
;
543 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
544 gl_shader_stage stage
,
545 struct user_sgpr_info
*user_sgpr_info
)
547 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage
== MESA_SHADER_GEOMETRY
||
551 stage
== MESA_SHADER_VERTEX
||
552 stage
== MESA_SHADER_TESS_CTRL
||
553 stage
== MESA_SHADER_TESS_EVAL
||
554 ctx
->is_gs_copy_shader
)
555 user_sgpr_info
->need_ring_offsets
= true;
557 if (stage
== MESA_SHADER_FRAGMENT
&&
558 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
559 user_sgpr_info
->need_ring_offsets
= true;
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
563 user_sgpr_info
->sgpr_count
+= 2;
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
568 case MESA_SHADER_COMPUTE
:
569 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
570 user_sgpr_info
->sgpr_count
+= 3;
572 case MESA_SHADER_FRAGMENT
:
573 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
575 case MESA_SHADER_VERTEX
:
576 if (!ctx
->is_gs_copy_shader
) {
577 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
578 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
579 user_sgpr_info
->sgpr_count
+= 3;
581 user_sgpr_info
->sgpr_count
+= 2;
584 if (ctx
->options
->key
.vs
.as_ls
)
585 user_sgpr_info
->sgpr_count
++;
587 case MESA_SHADER_TESS_CTRL
:
588 user_sgpr_info
->sgpr_count
+= 4;
590 case MESA_SHADER_TESS_EVAL
:
591 user_sgpr_info
->sgpr_count
+= 1;
593 case MESA_SHADER_GEOMETRY
:
594 user_sgpr_info
->sgpr_count
+= 2;
600 if (ctx
->shader_info
->info
.needs_push_constants
)
601 user_sgpr_info
->sgpr_count
+= 2;
603 uint32_t remaining_sgprs
= 16 - user_sgpr_info
->sgpr_count
;
604 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
605 user_sgpr_info
->sgpr_count
+= 2;
606 user_sgpr_info
->indirect_all_descriptor_sets
= true;
608 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
613 declare_global_input_sgprs(struct nir_to_llvm_context
*ctx
,
614 gl_shader_stage stage
,
615 bool has_previous_stage
,
616 gl_shader_stage previous_stage
,
617 const struct user_sgpr_info
*user_sgpr_info
,
618 struct arg_info
*args
,
619 LLVMValueRef
*desc_sets
)
621 LLVMTypeRef type
= const_array(ctx
->ac
.i8
, 1024 * 1024);
622 unsigned num_sets
= ctx
->options
->layout
?
623 ctx
->options
->layout
->num_sets
: 0;
624 unsigned stage_mask
= 1 << stage
;
626 if (has_previous_stage
)
627 stage_mask
|= 1 << previous_stage
;
629 /* 1 for each descriptor set */
630 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
631 for (unsigned i
= 0; i
< num_sets
; ++i
) {
632 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
633 add_array_arg(args
, type
,
634 &ctx
->descriptor_sets
[i
]);
638 add_array_arg(args
, const_array(type
, 32), desc_sets
);
641 if (ctx
->shader_info
->info
.needs_push_constants
) {
642 /* 1 for push constants and dynamic descriptors */
643 add_array_arg(args
, type
, &ctx
->push_constants
);
648 declare_vs_specific_input_sgprs(struct nir_to_llvm_context
*ctx
,
649 gl_shader_stage stage
,
650 bool has_previous_stage
,
651 gl_shader_stage previous_stage
,
652 struct arg_info
*args
)
654 if (!ctx
->is_gs_copy_shader
&&
655 (stage
== MESA_SHADER_VERTEX
||
656 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
657 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
658 add_arg(args
, ARG_SGPR
, const_array(ctx
->ac
.v4i32
, 16),
659 &ctx
->vertex_buffers
);
661 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
662 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
663 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
664 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
670 declare_vs_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
672 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
673 if (!ctx
->is_gs_copy_shader
) {
674 if (ctx
->options
->key
.vs
.as_ls
) {
675 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
676 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
679 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
681 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
686 declare_tes_input_vgprs(struct nir_to_llvm_context
*ctx
, struct arg_info
*args
)
688 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
689 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
690 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
691 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
695 set_global_input_locs(struct nir_to_llvm_context
*ctx
, gl_shader_stage stage
,
696 bool has_previous_stage
, gl_shader_stage previous_stage
,
697 const struct user_sgpr_info
*user_sgpr_info
,
698 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
700 unsigned num_sets
= ctx
->options
->layout
?
701 ctx
->options
->layout
->num_sets
: 0;
702 unsigned stage_mask
= 1 << stage
;
704 if (has_previous_stage
)
705 stage_mask
|= 1 << previous_stage
;
707 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
708 for (unsigned i
= 0; i
< num_sets
; ++i
) {
709 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
710 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
712 ctx
->descriptor_sets
[i
] = NULL
;
715 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
718 for (unsigned i
= 0; i
< num_sets
; ++i
) {
719 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
720 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
721 ctx
->descriptor_sets
[i
] =
722 ac_build_load_to_sgpr(&ctx
->ac
,
724 LLVMConstInt(ctx
->ac
.i32
, i
, false));
727 ctx
->descriptor_sets
[i
] = NULL
;
729 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
732 if (ctx
->shader_info
->info
.needs_push_constants
) {
733 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
738 set_vs_specific_input_locs(struct nir_to_llvm_context
*ctx
,
739 gl_shader_stage stage
, bool has_previous_stage
,
740 gl_shader_stage previous_stage
,
741 uint8_t *user_sgpr_idx
)
743 if (!ctx
->is_gs_copy_shader
&&
744 (stage
== MESA_SHADER_VERTEX
||
745 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
746 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
747 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
752 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
755 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
756 user_sgpr_idx
, vs_num
);
760 static void create_function(struct nir_to_llvm_context
*ctx
,
761 gl_shader_stage stage
,
762 bool has_previous_stage
,
763 gl_shader_stage previous_stage
)
765 uint8_t user_sgpr_idx
;
766 struct user_sgpr_info user_sgpr_info
;
767 struct arg_info args
= {};
768 LLVMValueRef desc_sets
;
770 allocate_user_sgprs(ctx
, stage
, &user_sgpr_info
);
772 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
773 add_arg(&args
, ARG_SGPR
, const_array(ctx
->ac
.v4i32
, 16),
778 case MESA_SHADER_COMPUTE
:
779 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
780 previous_stage
, &user_sgpr_info
,
783 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
784 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
785 &ctx
->num_work_groups
);
788 for (int i
= 0; i
< 3; i
++) {
789 ctx
->workgroup_ids
[i
] = NULL
;
790 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
791 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
792 &ctx
->workgroup_ids
[i
]);
796 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
797 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tg_size
);
798 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
799 &ctx
->local_invocation_ids
);
801 case MESA_SHADER_VERTEX
:
802 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
803 previous_stage
, &user_sgpr_info
,
805 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
806 previous_stage
, &args
);
808 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
809 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
810 if (ctx
->options
->key
.vs
.as_es
)
811 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
813 else if (ctx
->options
->key
.vs
.as_ls
)
814 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
815 &ctx
->ls_out_layout
);
817 declare_vs_input_vgprs(ctx
, &args
);
819 case MESA_SHADER_TESS_CTRL
:
820 if (has_previous_stage
) {
821 // First 6 system regs
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
823 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
824 &ctx
->merged_wave_info
);
825 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
826 &ctx
->tess_factor_offset
);
828 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
829 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
830 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
832 declare_global_input_sgprs(ctx
, stage
,
835 &user_sgpr_info
, &args
,
837 declare_vs_specific_input_sgprs(ctx
, stage
,
839 previous_stage
, &args
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
842 &ctx
->ls_out_layout
);
844 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
845 &ctx
->tcs_offchip_layout
);
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->tcs_out_offsets
);
848 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
849 &ctx
->tcs_out_layout
);
850 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
851 &ctx
->tcs_in_layout
);
852 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
853 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
856 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
857 &ctx
->abi
.tcs_patch_id
);
858 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
859 &ctx
->abi
.tcs_rel_ids
);
861 declare_vs_input_vgprs(ctx
, &args
);
863 declare_global_input_sgprs(ctx
, stage
,
866 &user_sgpr_info
, &args
,
869 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
870 &ctx
->tcs_offchip_layout
);
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->tcs_out_offsets
);
873 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
874 &ctx
->tcs_out_layout
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tcs_in_layout
);
877 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
878 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
881 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
882 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
883 &ctx
->tess_factor_offset
);
884 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
885 &ctx
->abi
.tcs_patch_id
);
886 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
887 &ctx
->abi
.tcs_rel_ids
);
890 case MESA_SHADER_TESS_EVAL
:
891 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
892 previous_stage
, &user_sgpr_info
,
895 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
896 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
897 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->view_index
);
899 if (ctx
->options
->key
.tes
.as_es
) {
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
901 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
902 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
905 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
906 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
908 declare_tes_input_vgprs(ctx
, &args
);
910 case MESA_SHADER_GEOMETRY
:
911 if (has_previous_stage
) {
912 // First 6 system regs
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
916 &ctx
->merged_wave_info
);
917 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
919 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
920 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
921 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
923 declare_global_input_sgprs(ctx
, stage
,
926 &user_sgpr_info
, &args
,
929 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
930 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
931 &ctx
->tcs_offchip_layout
);
933 declare_vs_specific_input_sgprs(ctx
, stage
,
939 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
940 &ctx
->gsvs_ring_stride
);
941 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
942 &ctx
->gsvs_num_entries
);
943 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
944 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
947 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
948 &ctx
->gs_vtx_offset
[0]);
949 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
950 &ctx
->gs_vtx_offset
[2]);
951 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
952 &ctx
->abi
.gs_prim_id
);
953 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
954 &ctx
->abi
.gs_invocation_id
);
955 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
956 &ctx
->gs_vtx_offset
[4]);
958 if (previous_stage
== MESA_SHADER_VERTEX
) {
959 declare_vs_input_vgprs(ctx
, &args
);
961 declare_tes_input_vgprs(ctx
, &args
);
964 declare_global_input_sgprs(ctx
, stage
,
967 &user_sgpr_info
, &args
,
970 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
971 &ctx
->gsvs_ring_stride
);
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
973 &ctx
->gsvs_num_entries
);
974 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
975 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
978 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
979 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
980 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
981 &ctx
->gs_vtx_offset
[0]);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->gs_vtx_offset
[1]);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->abi
.gs_prim_id
);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->gs_vtx_offset
[2]);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
989 &ctx
->gs_vtx_offset
[3]);
990 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
991 &ctx
->gs_vtx_offset
[4]);
992 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
993 &ctx
->gs_vtx_offset
[5]);
994 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
995 &ctx
->abi
.gs_invocation_id
);
998 case MESA_SHADER_FRAGMENT
:
999 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1000 previous_stage
, &user_sgpr_info
,
1003 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
1004 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1005 &ctx
->sample_pos_offset
);
1007 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->prim_mask
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1018 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1019 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1020 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1021 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1022 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1023 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1026 unreachable("Shader stage not implemented");
1029 ctx
->main_function
= create_llvm_function(
1030 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
1031 ctx
->max_workgroup_size
,
1032 ctx
->options
->unsafe_math
);
1033 set_llvm_calling_convention(ctx
->main_function
, stage
);
1036 ctx
->shader_info
->num_input_vgprs
= 0;
1037 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1039 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1041 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1042 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1044 assign_arguments(ctx
->main_function
, &args
);
1048 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1049 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1051 if (ctx
->options
->supports_spill
) {
1052 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1053 LLVMPointerType(ctx
->ac
.i8
, CONST_ADDR_SPACE
),
1054 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1055 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
1056 const_array(ctx
->ac
.v4i32
, 16), "");
1060 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1061 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1062 if (has_previous_stage
)
1065 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1066 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1069 case MESA_SHADER_COMPUTE
:
1070 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1071 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1075 case MESA_SHADER_VERTEX
:
1076 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1077 previous_stage
, &user_sgpr_idx
);
1078 if (ctx
->view_index
)
1079 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1080 if (ctx
->options
->key
.vs
.as_ls
) {
1081 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1084 if (ctx
->options
->key
.vs
.as_ls
)
1085 ac_declare_lds_as_pointer(&ctx
->ac
);
1087 case MESA_SHADER_TESS_CTRL
:
1088 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1089 previous_stage
, &user_sgpr_idx
);
1090 if (has_previous_stage
)
1091 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1093 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1094 if (ctx
->view_index
)
1095 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1096 ac_declare_lds_as_pointer(&ctx
->ac
);
1098 case MESA_SHADER_TESS_EVAL
:
1099 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1100 if (ctx
->view_index
)
1101 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1103 case MESA_SHADER_GEOMETRY
:
1104 if (has_previous_stage
) {
1105 if (previous_stage
== MESA_SHADER_VERTEX
)
1106 set_vs_specific_input_locs(ctx
, stage
,
1111 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1114 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1116 if (ctx
->view_index
)
1117 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1118 if (has_previous_stage
)
1119 ac_declare_lds_as_pointer(&ctx
->ac
);
1121 case MESA_SHADER_FRAGMENT
:
1122 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1123 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1128 unreachable("Shader stage not implemented");
1131 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1134 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1135 LLVMValueRef value
, unsigned count
)
1137 unsigned num_components
= ac_get_llvm_num_components(value
);
1138 if (count
== num_components
)
1141 LLVMValueRef masks
[] = {
1142 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1143 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1146 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1149 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1150 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1154 build_store_values_extended(struct ac_llvm_context
*ac
,
1155 LLVMValueRef
*values
,
1156 unsigned value_count
,
1157 unsigned value_stride
,
1160 LLVMBuilderRef builder
= ac
->builder
;
1163 for (i
= 0; i
< value_count
; i
++) {
1164 LLVMValueRef ptr
= values
[i
* value_stride
];
1165 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1166 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1167 LLVMBuildStore(builder
, value
, ptr
);
1171 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1172 const nir_ssa_def
*def
)
1174 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1175 if (def
->num_components
> 1) {
1176 type
= LLVMVectorType(type
, def
->num_components
);
1181 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1184 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1185 return (LLVMValueRef
)entry
->data
;
1189 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1190 const struct nir_block
*b
)
1192 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1193 return (LLVMBasicBlockRef
)entry
->data
;
1196 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1198 unsigned num_components
)
1200 LLVMValueRef value
= get_src(ctx
, src
.src
);
1201 bool need_swizzle
= false;
1204 LLVMTypeRef type
= LLVMTypeOf(value
);
1205 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1206 ? LLVMGetVectorSize(type
)
1209 for (unsigned i
= 0; i
< num_components
; ++i
) {
1210 assert(src
.swizzle
[i
] < src_components
);
1211 if (src
.swizzle
[i
] != i
)
1212 need_swizzle
= true;
1215 if (need_swizzle
|| num_components
!= src_components
) {
1216 LLVMValueRef masks
[] = {
1217 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1218 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1219 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1220 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1222 if (src_components
> 1 && num_components
== 1) {
1223 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1225 } else if (src_components
== 1 && num_components
> 1) {
1226 LLVMValueRef values
[] = {value
, value
, value
, value
};
1227 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1229 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1230 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1234 assert(!src
.negate
);
1239 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1240 LLVMIntPredicate pred
, LLVMValueRef src0
,
1243 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1244 return LLVMBuildSelect(ctx
->builder
, result
,
1245 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1249 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1250 LLVMRealPredicate pred
, LLVMValueRef src0
,
1253 LLVMValueRef result
;
1254 src0
= ac_to_float(ctx
, src0
);
1255 src1
= ac_to_float(ctx
, src1
);
1256 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1257 return LLVMBuildSelect(ctx
->builder
, result
,
1258 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1262 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1264 LLVMTypeRef result_type
,
1268 LLVMValueRef params
[] = {
1269 ac_to_float(ctx
, src0
),
1272 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1273 get_elem_bits(ctx
, result_type
));
1274 assert(length
< sizeof(name
));
1275 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1278 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1280 LLVMTypeRef result_type
,
1281 LLVMValueRef src0
, LLVMValueRef src1
)
1284 LLVMValueRef params
[] = {
1285 ac_to_float(ctx
, src0
),
1286 ac_to_float(ctx
, src1
),
1289 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1290 get_elem_bits(ctx
, result_type
));
1291 assert(length
< sizeof(name
));
1292 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1295 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1297 LLVMTypeRef result_type
,
1298 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1301 LLVMValueRef params
[] = {
1302 ac_to_float(ctx
, src0
),
1303 ac_to_float(ctx
, src1
),
1304 ac_to_float(ctx
, src2
),
1307 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1308 get_elem_bits(ctx
, result_type
));
1309 assert(length
< sizeof(name
));
1310 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1313 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1314 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1316 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1318 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1321 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1322 LLVMIntPredicate pred
,
1323 LLVMValueRef src0
, LLVMValueRef src1
)
1325 return LLVMBuildSelect(ctx
->builder
,
1326 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1331 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1334 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1335 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1338 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1341 LLVMValueRef cmp
, val
;
1343 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, ctx
->f32_0
, "");
1344 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->f32_1
, src0
, "");
1345 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, ctx
->f32_0
, "");
1346 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(ctx
->f32
, -1.0), "");
1350 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1353 LLVMValueRef cmp
, val
;
1355 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, ctx
->i32_0
, "");
1356 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->i32_1
, src0
, "");
1357 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, ctx
->i32_0
, "");
1358 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(ctx
->i32
, -1, true), "");
1362 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1365 const char *intr
= "llvm.floor.f32";
1366 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1367 LLVMValueRef params
[] = {
1370 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1371 ctx
->f32
, params
, 1,
1372 AC_FUNC_ATTR_READNONE
);
1373 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1376 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1378 LLVMValueRef src0
, LLVMValueRef src1
)
1380 LLVMTypeRef ret_type
;
1381 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1383 LLVMValueRef params
[] = { src0
, src1
};
1384 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1387 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1388 params
, 2, AC_FUNC_ATTR_READNONE
);
1390 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1391 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1395 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1398 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1401 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1404 src0
= ac_to_float(ctx
, src0
);
1405 return LLVMBuildSExt(ctx
->builder
,
1406 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1410 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1413 return LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1416 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1419 return LLVMBuildSExt(ctx
->builder
,
1420 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1424 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1427 LLVMValueRef result
;
1428 LLVMValueRef cond
= NULL
;
1430 src0
= ac_to_float(&ctx
->ac
, src0
);
1431 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1433 if (ctx
->options
->chip_class
>= VI
) {
1434 LLVMValueRef args
[2];
1435 /* Check if the result is a denormal - and flush to 0 if so. */
1437 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1438 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1441 /* need to convert back up to f32 */
1442 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1444 if (ctx
->options
->chip_class
>= VI
)
1445 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1448 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1449 * so compare the result and flush to 0 if it's smaller.
1451 LLVMValueRef temp
, cond2
;
1452 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1453 ctx
->ac
.f32
, result
);
1454 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1455 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1457 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1458 temp
, ctx
->ac
.f32_0
, "");
1459 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1460 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1465 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1466 LLVMValueRef src0
, LLVMValueRef src1
)
1468 LLVMValueRef dst64
, result
;
1469 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1470 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1472 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1473 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1474 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1478 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1479 LLVMValueRef src0
, LLVMValueRef src1
)
1481 LLVMValueRef dst64
, result
;
1482 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1483 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1485 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1486 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1487 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1491 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1493 const LLVMValueRef srcs
[3])
1495 LLVMValueRef result
;
1496 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1498 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1499 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1503 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1504 LLVMValueRef src0
, LLVMValueRef src1
,
1505 LLVMValueRef src2
, LLVMValueRef src3
)
1507 LLVMValueRef bfi_args
[3], result
;
1509 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1510 LLVMBuildSub(ctx
->builder
,
1511 LLVMBuildShl(ctx
->builder
,
1516 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1519 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1522 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1523 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1525 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1526 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1527 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1529 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1533 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1536 LLVMValueRef comp
[2];
1538 src0
= ac_to_float(ctx
, src0
);
1539 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1540 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1542 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1545 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1548 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1549 LLVMValueRef temps
[2], result
, val
;
1552 for (i
= 0; i
< 2; i
++) {
1553 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1554 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1555 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1556 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1559 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1561 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1566 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1572 LLVMValueRef result
;
1574 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1575 mask
= AC_TID_MASK_LEFT
;
1576 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1577 mask
= AC_TID_MASK_TOP
;
1579 mask
= AC_TID_MASK_TOP_LEFT
;
1581 /* for DDX we want to next X pixel, DDY next Y pixel. */
1582 if (op
== nir_op_fddx_fine
||
1583 op
== nir_op_fddx_coarse
||
1589 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1594 * this takes an I,J coordinate pair,
1595 * and works out the X and Y derivatives.
1596 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1598 static LLVMValueRef
emit_ddxy_interp(
1599 struct ac_nir_context
*ctx
,
1600 LLVMValueRef interp_ij
)
1602 LLVMValueRef result
[4], a
;
1605 for (i
= 0; i
< 2; i
++) {
1606 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1607 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1608 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1609 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1611 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1614 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1616 LLVMValueRef src
[4], result
= NULL
;
1617 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1618 unsigned src_components
;
1619 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1621 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1622 switch (instr
->op
) {
1628 case nir_op_pack_half_2x16
:
1631 case nir_op_unpack_half_2x16
:
1635 src_components
= num_components
;
1638 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1639 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1641 switch (instr
->op
) {
1647 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1648 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1651 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1654 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1657 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1660 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1661 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1662 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1665 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1666 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1667 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1670 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1673 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1676 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1679 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1682 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1683 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1684 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1685 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1686 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1687 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1688 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1691 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1692 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1693 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1696 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1699 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1702 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1705 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1706 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1707 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1710 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1711 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1712 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1715 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1716 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, src
[0]);
1719 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1722 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1725 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1728 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1729 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1730 LLVMTypeOf(src
[0]), ""),
1734 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1735 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1736 LLVMTypeOf(src
[0]), ""),
1740 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1741 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1742 LLVMTypeOf(src
[0]), ""),
1746 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1749 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1752 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1755 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1758 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1761 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1764 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1767 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1770 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1773 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1776 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1777 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1780 result
= emit_iabs(&ctx
->ac
, src
[0]);
1783 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1786 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1789 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1792 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1795 result
= emit_isign(&ctx
->ac
, src
[0]);
1798 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1799 result
= emit_fsign(&ctx
->ac
, src
[0]);
1802 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1803 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1806 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1807 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1810 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1811 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1813 case nir_op_fround_even
:
1814 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1815 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1818 result
= emit_ffract(&ctx
->ac
, src
[0]);
1821 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1822 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1825 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1826 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1829 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1830 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1833 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1834 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1837 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1838 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1841 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1842 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1843 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, result
);
1846 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1847 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1850 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1851 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1852 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1853 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1854 ac_to_float_type(&ctx
->ac
, def_type
),
1858 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1859 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1860 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1861 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1862 ac_to_float_type(&ctx
->ac
, def_type
),
1866 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1867 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1869 case nir_op_ibitfield_extract
:
1870 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1872 case nir_op_ubitfield_extract
:
1873 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1875 case nir_op_bitfield_insert
:
1876 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1878 case nir_op_bitfield_reverse
:
1879 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1881 case nir_op_bit_count
:
1882 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1887 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1888 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1889 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1893 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1894 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1898 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1899 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1903 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1904 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1908 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1909 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1912 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1913 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1916 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1920 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1921 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1922 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1924 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1928 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1929 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1930 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1932 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1935 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1937 case nir_op_find_lsb
:
1938 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1939 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1941 case nir_op_ufind_msb
:
1942 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1943 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1945 case nir_op_ifind_msb
:
1946 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1947 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1949 case nir_op_uadd_carry
:
1950 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1951 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1952 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1954 case nir_op_usub_borrow
:
1955 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1956 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1957 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1960 result
= emit_b2f(&ctx
->ac
, src
[0]);
1963 result
= emit_f2b(&ctx
->ac
, src
[0]);
1966 result
= emit_b2i(&ctx
->ac
, src
[0]);
1969 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1970 result
= emit_i2b(&ctx
->ac
, src
[0]);
1972 case nir_op_fquantize2f16
:
1973 result
= emit_f2f16(ctx
->nctx
, src
[0]);
1975 case nir_op_umul_high
:
1976 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1977 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1978 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1980 case nir_op_imul_high
:
1981 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1982 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1983 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1985 case nir_op_pack_half_2x16
:
1986 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1988 case nir_op_unpack_half_2x16
:
1989 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1993 case nir_op_fddx_fine
:
1994 case nir_op_fddy_fine
:
1995 case nir_op_fddx_coarse
:
1996 case nir_op_fddy_coarse
:
1997 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
2000 case nir_op_unpack_64_2x32_split_x
: {
2001 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2002 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2005 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2010 case nir_op_unpack_64_2x32_split_y
: {
2011 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
2012 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2015 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2020 case nir_op_pack_64_2x32_split
: {
2021 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2022 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2023 src
[0], ctx
->ac
.i32_0
, "");
2024 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2025 src
[1], ctx
->ac
.i32_1
, "");
2026 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2031 fprintf(stderr
, "Unknown NIR alu instr: ");
2032 nir_print_instr(&instr
->instr
, stderr
);
2033 fprintf(stderr
, "\n");
2038 assert(instr
->dest
.dest
.is_ssa
);
2039 result
= ac_to_integer(&ctx
->ac
, result
);
2040 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2045 static void visit_load_const(struct ac_nir_context
*ctx
,
2046 const nir_load_const_instr
*instr
)
2048 LLVMValueRef values
[4], value
= NULL
;
2049 LLVMTypeRef element_type
=
2050 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2052 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2053 switch (instr
->def
.bit_size
) {
2055 values
[i
] = LLVMConstInt(element_type
,
2056 instr
->value
.u32
[i
], false);
2059 values
[i
] = LLVMConstInt(element_type
,
2060 instr
->value
.u64
[i
], false);
2064 "unsupported nir load_const bit_size: %d\n",
2065 instr
->def
.bit_size
);
2069 if (instr
->def
.num_components
> 1) {
2070 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2074 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2077 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
2080 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2081 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2082 LLVMPointerType(type
, addr_space
), "");
2086 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2089 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2090 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2093 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2094 /* On VI, the descriptor contains the size in bytes,
2095 * but TXQ must return the size in elements.
2096 * The stride is always non-zero for resources using TXQ.
2098 LLVMValueRef stride
=
2099 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2101 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2102 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2103 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2104 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2106 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2112 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2115 static void build_int_type_name(
2117 char *buf
, unsigned bufsize
)
2119 assert(bufsize
>= 6);
2121 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2122 snprintf(buf
, bufsize
, "v%ui32",
2123 LLVMGetVectorSize(type
));
2128 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2129 struct ac_image_args
*args
,
2130 const nir_tex_instr
*instr
)
2132 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2133 LLVMValueRef coord
= args
->addr
;
2134 LLVMValueRef half_texel
[2];
2135 LLVMValueRef compare_cube_wa
= NULL
;
2136 LLVMValueRef result
;
2138 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2142 struct ac_image_args txq_args
= { 0 };
2144 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2145 txq_args
.opcode
= ac_image_get_resinfo
;
2146 txq_args
.dmask
= 0xf;
2147 txq_args
.addr
= ctx
->i32_0
;
2148 txq_args
.resource
= args
->resource
;
2149 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2151 for (c
= 0; c
< 2; c
++) {
2152 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2153 LLVMConstInt(ctx
->i32
, c
, false), "");
2154 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2155 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2156 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2157 LLVMConstReal(ctx
->f32
, -0.5), "");
2161 LLVMValueRef orig_coords
= args
->addr
;
2163 for (c
= 0; c
< 2; c
++) {
2165 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2166 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2167 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2168 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2169 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2170 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2175 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2176 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2177 * workaround by sampling using a scaled type and converting.
2178 * This is taken from amdgpu-pro shaders.
2180 /* NOTE this produces some ugly code compared to amdgpu-pro,
2181 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2182 * and then reads them back. -pro generates two selects,
2183 * one s_cmp for the descriptor rewriting
2184 * one v_cmp for the coordinate and result changes.
2186 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2187 LLVMValueRef tmp
, tmp2
;
2189 /* workaround 8/8/8/8 uint/sint cube gather bug */
2190 /* first detect it then change to a scaled read and f2i */
2191 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2194 /* extract the DATA_FORMAT */
2195 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2196 LLVMConstInt(ctx
->i32
, 6, false), false);
2198 /* is the DATA_FORMAT == 8_8_8_8 */
2199 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2201 if (stype
== GLSL_TYPE_UINT
)
2202 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2203 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2204 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2206 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2207 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2208 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2210 /* replace the NUM FORMAT in the descriptor */
2211 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2212 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2214 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2216 /* don't modify the coordinates for this case */
2217 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2220 result
= ac_build_image_opcode(ctx
, args
);
2222 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2223 LLVMValueRef tmp
, tmp2
;
2225 /* if the cube workaround is in place, f2i the result. */
2226 for (c
= 0; c
< 4; c
++) {
2227 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2228 if (stype
== GLSL_TYPE_UINT
)
2229 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2231 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2232 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2233 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2234 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2235 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2236 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2242 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2243 const nir_tex_instr
*instr
,
2245 struct ac_image_args
*args
)
2247 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2248 return ac_build_buffer_load_format(&ctx
->ac
,
2255 args
->opcode
= ac_image_sample
;
2256 args
->compare
= instr
->is_shadow
;
2258 switch (instr
->op
) {
2260 case nir_texop_txf_ms
:
2261 case nir_texop_samples_identical
:
2262 args
->opcode
= lod_is_zero
||
2263 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2264 ac_image_load
: ac_image_load_mip
;
2265 args
->compare
= false;
2266 args
->offset
= false;
2273 args
->level_zero
= true;
2278 case nir_texop_query_levels
:
2279 args
->opcode
= ac_image_get_resinfo
;
2282 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2283 args
->level_zero
= true;
2289 args
->opcode
= ac_image_gather4
;
2290 args
->level_zero
= true;
2293 args
->opcode
= ac_image_get_lod
;
2294 args
->compare
= false;
2295 args
->offset
= false;
2301 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2302 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2303 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2304 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2307 return ac_build_image_opcode(&ctx
->ac
, args
);
2310 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2311 nir_intrinsic_instr
*instr
)
2313 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2314 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2315 unsigned binding
= nir_intrinsic_binding(instr
);
2316 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2317 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2318 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2319 unsigned base_offset
= layout
->binding
[binding
].offset
;
2320 LLVMValueRef offset
, stride
;
2322 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2323 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2324 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2325 layout
->binding
[binding
].dynamic_offset_offset
;
2326 desc_ptr
= ctx
->push_constants
;
2327 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2328 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2330 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2332 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2333 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2334 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2336 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2337 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2338 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2343 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2344 nir_intrinsic_instr
*instr
)
2346 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2347 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2349 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2350 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2354 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2355 nir_intrinsic_instr
*instr
)
2357 LLVMValueRef ptr
, addr
;
2359 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2360 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2362 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2363 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2365 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2368 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2369 const nir_intrinsic_instr
*instr
)
2371 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2373 return get_buffer_size(ctx
, LLVMBuildLoad(ctx
->ac
.builder
, ptr
, ""), false);
2375 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2376 nir_intrinsic_instr
*instr
)
2378 const char *store_name
;
2379 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2380 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2381 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2382 int components_32bit
= elem_size_mult
* instr
->num_components
;
2383 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2384 LLVMValueRef base_data
, base_offset
;
2385 LLVMValueRef params
[6];
2387 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2388 get_src(ctx
, instr
->src
[1]), true);
2389 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2390 params
[4] = ctx
->ac
.i1false
; /* glc */
2391 params
[5] = ctx
->ac
.i1false
; /* slc */
2393 if (components_32bit
> 1)
2394 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2396 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2397 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2398 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2400 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2404 LLVMValueRef offset
;
2406 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2408 /* Due to an LLVM limitation, split 3-element writes
2409 * into a 2-element and a 1-element write. */
2411 writemask
|= 1 << (start
+ 2);
2415 start
*= elem_size_mult
;
2416 count
*= elem_size_mult
;
2419 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2424 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2426 } else if (count
== 2) {
2427 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2428 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2429 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, LLVMGetUndef(ctx
->ac
.v2f32
), tmp
,
2432 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2433 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
+ 1, false), "");
2434 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, data
, tmp
,
2436 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2440 if (ac_get_llvm_num_components(base_data
) > 1)
2441 data
= LLVMBuildExtractElement(ctx
->ac
.builder
, base_data
,
2442 LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2445 store_name
= "llvm.amdgcn.buffer.store.f32";
2448 offset
= base_offset
;
2450 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2454 ac_build_intrinsic(&ctx
->ac
, store_name
,
2455 ctx
->ac
.voidt
, params
, 6, 0);
2459 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2460 const nir_intrinsic_instr
*instr
)
2463 LLVMValueRef params
[6];
2466 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2467 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2469 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2470 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2471 get_src(ctx
, instr
->src
[0]),
2473 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2474 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2475 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2477 switch (instr
->intrinsic
) {
2478 case nir_intrinsic_ssbo_atomic_add
:
2479 name
= "llvm.amdgcn.buffer.atomic.add";
2481 case nir_intrinsic_ssbo_atomic_imin
:
2482 name
= "llvm.amdgcn.buffer.atomic.smin";
2484 case nir_intrinsic_ssbo_atomic_umin
:
2485 name
= "llvm.amdgcn.buffer.atomic.umin";
2487 case nir_intrinsic_ssbo_atomic_imax
:
2488 name
= "llvm.amdgcn.buffer.atomic.smax";
2490 case nir_intrinsic_ssbo_atomic_umax
:
2491 name
= "llvm.amdgcn.buffer.atomic.umax";
2493 case nir_intrinsic_ssbo_atomic_and
:
2494 name
= "llvm.amdgcn.buffer.atomic.and";
2496 case nir_intrinsic_ssbo_atomic_or
:
2497 name
= "llvm.amdgcn.buffer.atomic.or";
2499 case nir_intrinsic_ssbo_atomic_xor
:
2500 name
= "llvm.amdgcn.buffer.atomic.xor";
2502 case nir_intrinsic_ssbo_atomic_exchange
:
2503 name
= "llvm.amdgcn.buffer.atomic.swap";
2505 case nir_intrinsic_ssbo_atomic_comp_swap
:
2506 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2512 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2515 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2516 const nir_intrinsic_instr
*instr
)
2518 LLVMValueRef results
[2];
2519 int load_components
;
2520 int num_components
= instr
->num_components
;
2521 if (instr
->dest
.ssa
.bit_size
== 64)
2522 num_components
*= 2;
2524 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2525 load_components
= MIN2(num_components
- i
, 4);
2526 const char *load_name
;
2527 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2528 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2529 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2531 if (load_components
== 3)
2532 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2533 else if (load_components
> 1)
2534 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2536 if (load_components
>= 3)
2537 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2538 else if (load_components
== 2)
2539 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2540 else if (load_components
== 1)
2541 load_name
= "llvm.amdgcn.buffer.load.f32";
2543 unreachable("unhandled number of components");
2545 LLVMValueRef params
[] = {
2546 ctx
->abi
->load_ssbo(ctx
->abi
,
2547 get_src(ctx
, instr
->src
[0]),
2555 results
[i
] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2560 LLVMValueRef ret
= results
[0];
2561 if (num_components
> 4 || num_components
== 3) {
2562 LLVMValueRef masks
[] = {
2563 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2564 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2565 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2566 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2569 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2570 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2571 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2574 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2575 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2578 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2579 const nir_intrinsic_instr
*instr
)
2581 LLVMValueRef results
[8], ret
;
2582 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2583 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2584 int num_components
= instr
->num_components
;
2586 if (ctx
->abi
->load_ubo
)
2587 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2589 if (instr
->dest
.ssa
.bit_size
== 64)
2590 num_components
*= 2;
2592 for (unsigned i
= 0; i
< num_components
; ++i
) {
2593 LLVMValueRef params
[] = {
2595 LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, 4 * i
, 0),
2598 results
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.load.const.v4i32", ctx
->ac
.f32
,
2600 AC_FUNC_ATTR_READNONE
|
2601 AC_FUNC_ATTR_LEGACY
);
2605 ret
= ac_build_gather_values(&ctx
->ac
, results
, num_components
);
2606 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2607 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2611 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2612 bool vs_in
, unsigned *vertex_index_out
,
2613 LLVMValueRef
*vertex_index_ref
,
2614 unsigned *const_out
, LLVMValueRef
*indir_out
)
2616 unsigned const_offset
= 0;
2617 nir_deref
*tail
= &deref
->deref
;
2618 LLVMValueRef offset
= NULL
;
2620 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2622 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2623 if (vertex_index_out
)
2624 *vertex_index_out
= deref_array
->base_offset
;
2626 if (vertex_index_ref
) {
2627 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2628 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2629 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2631 *vertex_index_ref
= vtx
;
2635 if (deref
->var
->data
.compact
) {
2636 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2637 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2638 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2639 /* We always lower indirect dereferences for "compact" array vars. */
2640 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2642 const_offset
= deref_array
->base_offset
;
2646 while (tail
->child
!= NULL
) {
2647 const struct glsl_type
*parent_type
= tail
->type
;
2650 if (tail
->deref_type
== nir_deref_type_array
) {
2651 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2652 LLVMValueRef index
, stride
, local_offset
;
2653 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2655 const_offset
+= size
* deref_array
->base_offset
;
2656 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2659 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2660 index
= get_src(ctx
, deref_array
->indirect
);
2661 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2662 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2665 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2667 offset
= local_offset
;
2668 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2669 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2671 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2672 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2673 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2676 unreachable("unsupported deref type");
2680 if (const_offset
&& offset
)
2681 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2682 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2685 *const_out
= const_offset
;
2686 *indir_out
= offset
;
2690 /* The offchip buffer layout for TCS->TES is
2692 * - attribute 0 of patch 0 vertex 0
2693 * - attribute 0 of patch 0 vertex 1
2694 * - attribute 0 of patch 0 vertex 2
2696 * - attribute 0 of patch 1 vertex 0
2697 * - attribute 0 of patch 1 vertex 1
2699 * - attribute 1 of patch 0 vertex 0
2700 * - attribute 1 of patch 0 vertex 1
2702 * - per patch attribute 0 of patch 0
2703 * - per patch attribute 0 of patch 1
2706 * Note that every attribute has 4 components.
2708 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2709 LLVMValueRef vertex_index
,
2710 LLVMValueRef param_index
)
2712 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2713 LLVMValueRef param_stride
, constant16
;
2714 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2716 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2717 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2718 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2721 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2723 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2724 vertices_per_patch
, "");
2726 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2729 param_stride
= total_vertices
;
2731 base_addr
= rel_patch_id
;
2732 param_stride
= num_patches
;
2735 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2736 LLVMBuildMul(ctx
->builder
, param_index
,
2737 param_stride
, ""), "");
2739 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2741 if (!vertex_index
) {
2742 LLVMValueRef patch_data_offset
=
2743 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2745 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2746 patch_data_offset
, "");
2751 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2753 unsigned const_index
,
2755 LLVMValueRef vertex_index
,
2756 LLVMValueRef indir_index
)
2758 LLVMValueRef param_index
;
2761 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2764 if (const_index
&& !is_compact
)
2765 param
+= const_index
;
2766 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2768 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2772 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2773 bool is_patch
, uint32_t param
)
2777 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2779 ctx
->tess_outputs_written
|= (1ull << param
);
2783 get_dw_address(struct nir_to_llvm_context
*ctx
,
2784 LLVMValueRef dw_addr
,
2786 unsigned const_index
,
2787 bool compact_const_index
,
2788 LLVMValueRef vertex_index
,
2789 LLVMValueRef stride
,
2790 LLVMValueRef indir_index
)
2795 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2796 LLVMBuildMul(ctx
->builder
,
2802 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2803 LLVMBuildMul(ctx
->builder
, indir_index
,
2804 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2805 else if (const_index
&& !compact_const_index
)
2806 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2807 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2809 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2810 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2812 if (const_index
&& compact_const_index
)
2813 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2814 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2819 load_tcs_input(struct ac_shader_abi
*abi
,
2820 LLVMValueRef vertex_index
,
2821 LLVMValueRef indir_index
,
2822 unsigned const_index
,
2824 unsigned driver_location
,
2826 unsigned num_components
,
2830 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2831 LLVMValueRef dw_addr
, stride
;
2832 LLVMValueRef value
[4], result
;
2833 unsigned param
= shader_io_get_unique_index(location
);
2835 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2836 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2837 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2840 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2841 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2842 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2845 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2850 load_tcs_output(struct nir_to_llvm_context
*ctx
,
2851 nir_intrinsic_instr
*instr
)
2853 LLVMValueRef dw_addr
;
2854 LLVMValueRef stride
= NULL
;
2855 LLVMValueRef value
[4], result
;
2856 LLVMValueRef vertex_index
= NULL
;
2857 LLVMValueRef indir_index
= NULL
;
2858 unsigned const_index
= 0;
2860 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2861 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2862 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2863 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2864 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2865 &const_index
, &indir_index
);
2867 if (!instr
->variables
[0]->var
->data
.patch
) {
2868 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2869 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2871 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2874 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2877 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2878 for (unsigned i
= comp
; i
< instr
->num_components
+ comp
; i
++) {
2879 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2880 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2883 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, instr
->num_components
, comp
);
2884 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2889 store_tcs_output(struct ac_shader_abi
*abi
,
2890 LLVMValueRef vertex_index
,
2891 LLVMValueRef param_index
,
2892 unsigned const_index
,
2894 unsigned driver_location
,
2901 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2902 LLVMValueRef dw_addr
;
2903 LLVMValueRef stride
= NULL
;
2904 LLVMValueRef buf_addr
= NULL
;
2906 bool store_lds
= true;
2909 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2912 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2916 param
= shader_io_get_unique_index(location
);
2917 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2918 is_compact
&& const_index
> 3) {
2924 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2925 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2927 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2930 mark_tess_output(ctx
, is_patch
, param
);
2932 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2934 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2935 vertex_index
, param_index
);
2937 bool is_tess_factor
= false;
2938 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2939 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2940 is_tess_factor
= true;
2942 unsigned base
= is_compact
? const_index
: 0;
2943 for (unsigned chan
= 0; chan
< 8; chan
++) {
2944 if (!(writemask
& (1 << chan
)))
2946 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2948 if (store_lds
|| is_tess_factor
)
2949 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2951 if (!is_tess_factor
&& writemask
!= 0xF)
2952 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2953 buf_addr
, ctx
->oc_lds
,
2954 4 * (base
+ chan
), 1, 0, true, false);
2956 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2960 if (writemask
== 0xF) {
2961 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2962 buf_addr
, ctx
->oc_lds
,
2963 (base
* 4), 1, 0, true, false);
2968 load_tes_input(struct ac_shader_abi
*abi
,
2969 LLVMValueRef vertex_index
,
2970 LLVMValueRef param_index
,
2971 unsigned const_index
,
2973 unsigned driver_location
,
2975 unsigned num_components
,
2979 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2980 LLVMValueRef buf_addr
;
2981 LLVMValueRef result
;
2982 unsigned param
= shader_io_get_unique_index(location
);
2984 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
2989 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2990 is_compact
, vertex_index
, param_index
);
2992 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
2993 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
2995 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
2996 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2997 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3002 load_gs_input(struct ac_shader_abi
*abi
,
3004 unsigned driver_location
,
3006 unsigned num_components
,
3007 unsigned vertex_index
,
3008 unsigned const_index
,
3011 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3012 LLVMValueRef vtx_offset
;
3013 LLVMValueRef args
[9];
3014 unsigned param
, vtx_offset_param
;
3015 LLVMValueRef value
[4], result
;
3017 vtx_offset_param
= vertex_index
;
3018 assert(vtx_offset_param
< 6);
3019 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3020 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3022 param
= shader_io_get_unique_index(location
);
3024 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3025 if (ctx
->ac
.chip_class
>= GFX9
) {
3026 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3027 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3028 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3029 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3031 args
[0] = ctx
->esgs_ring
;
3032 args
[1] = vtx_offset
;
3033 args
[2] = LLVMConstInt(ctx
->ac
.i32
, (param
* 4 + i
+ const_index
) * 256, false);
3034 args
[3] = ctx
->ac
.i32_0
;
3035 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
3036 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
3037 args
[6] = ctx
->ac
.i32_1
; /* GLC */
3038 args
[7] = ctx
->ac
.i32_0
; /* SLC */
3039 args
[8] = ctx
->ac
.i32_0
; /* TFE */
3041 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
3042 ctx
->ac
.i32
, args
, 9,
3043 AC_FUNC_ATTR_READONLY
|
3044 AC_FUNC_ATTR_LEGACY
);
3047 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3053 build_gep_for_deref(struct ac_nir_context
*ctx
,
3054 nir_deref_var
*deref
)
3056 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3057 assert(entry
->data
);
3058 LLVMValueRef val
= entry
->data
;
3059 nir_deref
*tail
= deref
->deref
.child
;
3060 while (tail
!= NULL
) {
3061 LLVMValueRef offset
;
3062 switch (tail
->deref_type
) {
3063 case nir_deref_type_array
: {
3064 nir_deref_array
*array
= nir_deref_as_array(tail
);
3065 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3066 if (array
->deref_array_type
==
3067 nir_deref_array_type_indirect
) {
3068 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3075 case nir_deref_type_struct
: {
3076 nir_deref_struct
*deref_struct
=
3077 nir_deref_as_struct(tail
);
3078 offset
= LLVMConstInt(ctx
->ac
.i32
,
3079 deref_struct
->index
, 0);
3083 unreachable("bad deref type");
3085 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3091 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3092 nir_intrinsic_instr
*instr
)
3094 LLVMValueRef values
[8];
3095 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3096 int ve
= instr
->dest
.ssa
.num_components
;
3097 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3098 LLVMValueRef indir_index
;
3100 unsigned const_index
;
3101 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3102 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3103 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3104 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3105 &const_index
, &indir_index
);
3107 if (instr
->dest
.ssa
.bit_size
== 64)
3110 switch (instr
->variables
[0]->var
->data
.mode
) {
3111 case nir_var_shader_in
:
3112 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3113 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3114 LLVMValueRef result
;
3115 LLVMValueRef vertex_index
= NULL
;
3116 LLVMValueRef indir_index
= NULL
;
3117 unsigned const_index
= 0;
3118 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3119 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3120 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3121 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3123 get_deref_offset(ctx
, instr
->variables
[0],
3124 false, NULL
, is_patch
? NULL
: &vertex_index
,
3125 &const_index
, &indir_index
);
3127 result
= ctx
->abi
->load_tess_inputs(ctx
->abi
, vertex_index
, indir_index
,
3128 const_index
, location
, driver_location
,
3129 instr
->variables
[0]->var
->data
.location_frac
,
3130 instr
->num_components
,
3131 is_patch
, is_compact
);
3132 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3135 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3136 LLVMValueRef indir_index
;
3137 unsigned const_index
, vertex_index
;
3138 get_deref_offset(ctx
, instr
->variables
[0],
3139 false, &vertex_index
, NULL
,
3140 &const_index
, &indir_index
);
3141 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3142 instr
->variables
[0]->var
->data
.driver_location
,
3143 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3144 vertex_index
, const_index
,
3145 nir2llvmtype(ctx
, instr
->variables
[0]->var
->type
));
3148 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3150 unsigned count
= glsl_count_attribute_slots(
3151 instr
->variables
[0]->var
->type
,
3152 ctx
->stage
== MESA_SHADER_VERTEX
);
3154 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3155 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3156 stride
, false, true);
3158 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3162 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3166 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3168 unsigned count
= glsl_count_attribute_slots(
3169 instr
->variables
[0]->var
->type
, false);
3171 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3172 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3173 stride
, true, true);
3175 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3179 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3183 case nir_var_shared
: {
3184 LLVMValueRef address
= build_gep_for_deref(ctx
,
3185 instr
->variables
[0]);
3186 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3187 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3188 get_def_type(ctx
, &instr
->dest
.ssa
),
3191 case nir_var_shader_out
:
3192 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3193 return load_tcs_output(ctx
->nctx
, instr
);
3195 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3197 unsigned count
= glsl_count_attribute_slots(
3198 instr
->variables
[0]->var
->type
, false);
3200 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3201 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3202 stride
, true, true);
3204 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3208 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3209 ctx
->outputs
[idx
+ chan
+ const_index
* stride
],
3215 unreachable("unhandle variable mode");
3217 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3218 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3222 visit_store_var(struct ac_nir_context
*ctx
,
3223 nir_intrinsic_instr
*instr
)
3225 LLVMValueRef temp_ptr
, value
;
3226 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3227 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3228 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3229 int writemask
= instr
->const_index
[0] << comp
;
3230 LLVMValueRef indir_index
;
3231 unsigned const_index
;
3232 get_deref_offset(ctx
, instr
->variables
[0], false,
3233 NULL
, NULL
, &const_index
, &indir_index
);
3235 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3236 int old_writemask
= writemask
;
3238 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3239 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3243 for (unsigned chan
= 0; chan
< 4; chan
++) {
3244 if (old_writemask
& (1 << chan
))
3245 writemask
|= 3u << (2 * chan
);
3249 switch (instr
->variables
[0]->var
->data
.mode
) {
3250 case nir_var_shader_out
:
3252 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3253 LLVMValueRef vertex_index
= NULL
;
3254 LLVMValueRef indir_index
= NULL
;
3255 unsigned const_index
= 0;
3256 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3257 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3258 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3259 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3260 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3262 get_deref_offset(ctx
, instr
->variables
[0],
3263 false, NULL
, is_patch
? NULL
: &vertex_index
,
3264 &const_index
, &indir_index
);
3266 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3267 const_index
, location
, driver_location
,
3268 src
, comp
, is_patch
, is_compact
, writemask
);
3272 for (unsigned chan
= 0; chan
< 8; chan
++) {
3274 if (!(writemask
& (1 << chan
)))
3277 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3279 if (instr
->variables
[0]->var
->data
.compact
)
3282 unsigned count
= glsl_count_attribute_slots(
3283 instr
->variables
[0]->var
->type
, false);
3285 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3286 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3287 stride
, true, true);
3289 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3290 value
, indir_index
, "");
3291 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3292 count
, stride
, tmp_vec
);
3295 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3297 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3302 for (unsigned chan
= 0; chan
< 8; chan
++) {
3303 if (!(writemask
& (1 << chan
)))
3306 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3308 unsigned count
= glsl_count_attribute_slots(
3309 instr
->variables
[0]->var
->type
, false);
3311 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3312 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3315 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3316 value
, indir_index
, "");
3317 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3320 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3322 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3326 case nir_var_shared
: {
3327 int writemask
= instr
->const_index
[0];
3328 LLVMValueRef address
= build_gep_for_deref(ctx
,
3329 instr
->variables
[0]);
3330 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3331 unsigned components
=
3332 glsl_get_vector_elements(
3333 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3334 if (writemask
== (1 << components
) - 1) {
3335 val
= LLVMBuildBitCast(
3336 ctx
->ac
.builder
, val
,
3337 LLVMGetElementType(LLVMTypeOf(address
)), "");
3338 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3340 for (unsigned chan
= 0; chan
< 4; chan
++) {
3341 if (!(writemask
& (1 << chan
)))
3344 LLVMBuildStructGEP(ctx
->ac
.builder
,
3346 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3348 src
= LLVMBuildBitCast(
3349 ctx
->ac
.builder
, src
,
3350 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3351 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3361 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3364 case GLSL_SAMPLER_DIM_BUF
:
3366 case GLSL_SAMPLER_DIM_1D
:
3367 return array
? 2 : 1;
3368 case GLSL_SAMPLER_DIM_2D
:
3369 return array
? 3 : 2;
3370 case GLSL_SAMPLER_DIM_MS
:
3371 return array
? 4 : 3;
3372 case GLSL_SAMPLER_DIM_3D
:
3373 case GLSL_SAMPLER_DIM_CUBE
:
3375 case GLSL_SAMPLER_DIM_RECT
:
3376 case GLSL_SAMPLER_DIM_SUBPASS
:
3378 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3388 /* Adjust the sample index according to FMASK.
3390 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3391 * which is the identity mapping. Each nibble says which physical sample
3392 * should be fetched to get that sample.
3394 * For example, 0x11111100 means there are only 2 samples stored and
3395 * the second sample covers 3/4 of the pixel. When reading samples 0
3396 * and 1, return physical sample 0 (determined by the first two 0s
3397 * in FMASK), otherwise return physical sample 1.
3399 * The sample index should be adjusted as follows:
3400 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3402 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3403 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3404 LLVMValueRef coord_z
,
3405 LLVMValueRef sample_index
,
3406 LLVMValueRef fmask_desc_ptr
)
3408 LLVMValueRef fmask_load_address
[4];
3411 fmask_load_address
[0] = coord_x
;
3412 fmask_load_address
[1] = coord_y
;
3414 fmask_load_address
[2] = coord_z
;
3415 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3418 struct ac_image_args args
= {0};
3420 args
.opcode
= ac_image_load
;
3421 args
.da
= coord_z
? true : false;
3422 args
.resource
= fmask_desc_ptr
;
3424 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3426 res
= ac_build_image_opcode(ctx
, &args
);
3428 res
= ac_to_integer(ctx
, res
);
3429 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3430 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3432 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3436 LLVMValueRef sample_index4
=
3437 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3438 LLVMValueRef shifted_fmask
=
3439 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3440 LLVMValueRef final_sample
=
3441 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3443 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3444 * resource descriptor is 0 (invalid),
3446 LLVMValueRef fmask_desc
=
3447 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3450 LLVMValueRef fmask_word1
=
3451 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3454 LLVMValueRef word1_is_nonzero
=
3455 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3456 fmask_word1
, ctx
->i32_0
, "");
3458 /* Replace the MSAA sample index. */
3460 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3461 final_sample
, sample_index
, "");
3462 return sample_index
;
3465 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3466 const nir_intrinsic_instr
*instr
)
3468 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3469 if(instr
->variables
[0]->deref
.child
)
3470 type
= instr
->variables
[0]->deref
.child
->type
;
3472 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3473 LLVMValueRef coords
[4];
3474 LLVMValueRef masks
[] = {
3475 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3476 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3479 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3482 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3483 bool is_array
= glsl_sampler_type_is_array(type
);
3484 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3485 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3486 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3487 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3488 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3489 count
= image_type_to_components_count(dim
, is_array
);
3492 LLVMValueRef fmask_load_address
[3];
3495 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3496 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3498 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3500 fmask_load_address
[2] = NULL
;
3502 for (chan
= 0; chan
< 2; ++chan
)
3503 fmask_load_address
[chan
] =
3504 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3505 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3506 ctx
->ac
.i32
, ""), "");
3507 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3509 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3510 fmask_load_address
[0],
3511 fmask_load_address
[1],
3512 fmask_load_address
[2],
3514 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3516 if (count
== 1 && !gfx9_1d
) {
3517 if (instr
->src
[0].ssa
->num_components
)
3518 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3525 for (chan
= 0; chan
< count
; ++chan
) {
3526 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3529 for (chan
= 0; chan
< 2; ++chan
)
3530 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3531 ctx
->ac
.i32
, ""), "");
3532 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3538 coords
[2] = coords
[1];
3539 coords
[1] = ctx
->ac
.i32_0
;
3541 coords
[1] = ctx
->ac
.i32_0
;
3546 coords
[count
] = sample_index
;
3551 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3554 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3559 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3560 const nir_intrinsic_instr
*instr
)
3562 LLVMValueRef params
[7];
3564 char intrinsic_name
[64];
3565 const nir_variable
*var
= instr
->variables
[0]->var
;
3566 const struct glsl_type
*type
= var
->type
;
3568 if(instr
->variables
[0]->deref
.child
)
3569 type
= instr
->variables
[0]->deref
.child
->type
;
3571 type
= glsl_without_array(type
);
3572 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3573 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3574 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3575 ctx
->ac
.i32_0
, ""); /* vindex */
3576 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3577 params
[3] = ctx
->ac
.i1false
; /* glc */
3578 params
[4] = ctx
->ac
.i1false
; /* slc */
3579 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3582 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3583 res
= ac_to_integer(&ctx
->ac
, res
);
3585 bool is_da
= glsl_sampler_type_is_array(type
) ||
3586 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3587 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS
||
3588 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS_MS
;
3589 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3590 LLVMValueRef glc
= ctx
->ac
.i1false
;
3591 LLVMValueRef slc
= ctx
->ac
.i1false
;
3593 params
[0] = get_image_coords(ctx
, instr
);
3594 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3595 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3596 if (HAVE_LLVM
<= 0x0309) {
3597 params
[3] = ctx
->ac
.i1false
; /* r128 */
3602 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3609 ac_get_image_intr_name("llvm.amdgcn.image.load",
3610 ctx
->ac
.v4f32
, /* vdata */
3611 LLVMTypeOf(params
[0]), /* coords */
3612 LLVMTypeOf(params
[1]), /* rsrc */
3613 intrinsic_name
, sizeof(intrinsic_name
));
3615 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3616 params
, 7, AC_FUNC_ATTR_READONLY
);
3618 return ac_to_integer(&ctx
->ac
, res
);
3621 static void visit_image_store(struct ac_nir_context
*ctx
,
3622 nir_intrinsic_instr
*instr
)
3624 LLVMValueRef params
[8];
3625 char intrinsic_name
[64];
3626 const nir_variable
*var
= instr
->variables
[0]->var
;
3627 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3628 LLVMValueRef glc
= ctx
->ac
.i1false
;
3629 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3631 glc
= ctx
->ac
.i1true
;
3633 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3634 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3635 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3636 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3637 ctx
->ac
.i32_0
, ""); /* vindex */
3638 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3639 params
[4] = glc
; /* glc */
3640 params
[5] = ctx
->ac
.i1false
; /* slc */
3641 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3644 bool is_da
= glsl_sampler_type_is_array(type
) ||
3645 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3646 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3647 LLVMValueRef slc
= ctx
->ac
.i1false
;
3649 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3650 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3651 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3652 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3653 if (HAVE_LLVM
<= 0x0309) {
3654 params
[4] = ctx
->ac
.i1false
; /* r128 */
3659 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3666 ac_get_image_intr_name("llvm.amdgcn.image.store",
3667 LLVMTypeOf(params
[0]), /* vdata */
3668 LLVMTypeOf(params
[1]), /* coords */
3669 LLVMTypeOf(params
[2]), /* rsrc */
3670 intrinsic_name
, sizeof(intrinsic_name
));
3672 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3678 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3679 const nir_intrinsic_instr
*instr
)
3681 LLVMValueRef params
[7];
3682 int param_count
= 0;
3683 const nir_variable
*var
= instr
->variables
[0]->var
;
3685 const char *atomic_name
;
3686 char intrinsic_name
[41];
3687 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3688 MAYBE_UNUSED
int length
;
3690 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3692 switch (instr
->intrinsic
) {
3693 case nir_intrinsic_image_atomic_add
:
3694 atomic_name
= "add";
3696 case nir_intrinsic_image_atomic_min
:
3697 atomic_name
= is_unsigned
? "umin" : "smin";
3699 case nir_intrinsic_image_atomic_max
:
3700 atomic_name
= is_unsigned
? "umax" : "smax";
3702 case nir_intrinsic_image_atomic_and
:
3703 atomic_name
= "and";
3705 case nir_intrinsic_image_atomic_or
:
3708 case nir_intrinsic_image_atomic_xor
:
3709 atomic_name
= "xor";
3711 case nir_intrinsic_image_atomic_exchange
:
3712 atomic_name
= "swap";
3714 case nir_intrinsic_image_atomic_comp_swap
:
3715 atomic_name
= "cmpswap";
3721 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3722 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3723 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3725 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3726 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3728 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3729 ctx
->ac
.i32_0
, ""); /* vindex */
3730 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3731 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3733 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3734 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3736 char coords_type
[8];
3738 bool da
= glsl_sampler_type_is_array(type
) ||
3739 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3741 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3742 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3744 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3745 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3746 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3748 build_int_type_name(LLVMTypeOf(coords
),
3749 coords_type
, sizeof(coords_type
));
3751 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3752 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3755 assert(length
< sizeof(intrinsic_name
));
3756 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3759 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3760 const nir_intrinsic_instr
*instr
)
3763 const nir_variable
*var
= instr
->variables
[0]->var
;
3764 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3765 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3766 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
;
3767 if(instr
->variables
[0]->deref
.child
)
3768 type
= instr
->variables
[0]->deref
.child
->type
;
3770 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3771 return get_buffer_size(ctx
,
3772 get_sampler_desc(ctx
, instr
->variables
[0],
3773 AC_DESC_BUFFER
, NULL
, true, false), true);
3775 struct ac_image_args args
= { 0 };
3779 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3780 args
.opcode
= ac_image_get_resinfo
;
3781 args
.addr
= ctx
->ac
.i32_0
;
3783 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3785 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3787 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3788 glsl_sampler_type_is_array(type
)) {
3789 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3790 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3791 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3792 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3794 if (ctx
->ac
.chip_class
>= GFX9
&&
3795 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3796 glsl_sampler_type_is_array(type
)) {
3797 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3798 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3805 #define NOOP_WAITCNT 0xf7f
3806 #define LGKM_CNT 0x07f
3807 #define VM_CNT 0xf70
3809 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3810 const nir_intrinsic_instr
*instr
)
3812 unsigned waitcnt
= NOOP_WAITCNT
;
3814 switch (instr
->intrinsic
) {
3815 case nir_intrinsic_memory_barrier
:
3816 case nir_intrinsic_group_memory_barrier
:
3817 waitcnt
&= VM_CNT
& LGKM_CNT
;
3819 case nir_intrinsic_memory_barrier_atomic_counter
:
3820 case nir_intrinsic_memory_barrier_buffer
:
3821 case nir_intrinsic_memory_barrier_image
:
3824 case nir_intrinsic_memory_barrier_shared
:
3825 waitcnt
&= LGKM_CNT
;
3830 if (waitcnt
!= NOOP_WAITCNT
)
3831 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3834 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3836 /* SI only (thanks to a hw bug workaround):
3837 * The real barrier instruction isn’t needed, because an entire patch
3838 * always fits into a single wave.
3840 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3841 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3844 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3845 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3848 static void emit_discard_if(struct ac_nir_context
*ctx
,
3849 const nir_intrinsic_instr
*instr
)
3853 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3854 get_src(ctx
, instr
->src
[0]),
3856 ac_build_kill_if_false(&ctx
->ac
, cond
);
3860 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3862 LLVMValueRef result
;
3863 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3864 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3865 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3867 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3870 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3871 const nir_intrinsic_instr
*instr
)
3873 LLVMValueRef ptr
, result
;
3874 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3875 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3877 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3878 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3879 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3881 LLVMAtomicOrderingSequentiallyConsistent
,
3882 LLVMAtomicOrderingSequentiallyConsistent
,
3885 LLVMAtomicRMWBinOp op
;
3886 switch (instr
->intrinsic
) {
3887 case nir_intrinsic_var_atomic_add
:
3888 op
= LLVMAtomicRMWBinOpAdd
;
3890 case nir_intrinsic_var_atomic_umin
:
3891 op
= LLVMAtomicRMWBinOpUMin
;
3893 case nir_intrinsic_var_atomic_umax
:
3894 op
= LLVMAtomicRMWBinOpUMax
;
3896 case nir_intrinsic_var_atomic_imin
:
3897 op
= LLVMAtomicRMWBinOpMin
;
3899 case nir_intrinsic_var_atomic_imax
:
3900 op
= LLVMAtomicRMWBinOpMax
;
3902 case nir_intrinsic_var_atomic_and
:
3903 op
= LLVMAtomicRMWBinOpAnd
;
3905 case nir_intrinsic_var_atomic_or
:
3906 op
= LLVMAtomicRMWBinOpOr
;
3908 case nir_intrinsic_var_atomic_xor
:
3909 op
= LLVMAtomicRMWBinOpXor
;
3911 case nir_intrinsic_var_atomic_exchange
:
3912 op
= LLVMAtomicRMWBinOpXchg
;
3918 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3919 LLVMAtomicOrderingSequentiallyConsistent
,
3925 #define INTERP_CENTER 0
3926 #define INTERP_CENTROID 1
3927 #define INTERP_SAMPLE 2
3929 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
3930 enum glsl_interp_mode interp
, unsigned location
)
3933 case INTERP_MODE_FLAT
:
3936 case INTERP_MODE_SMOOTH
:
3937 case INTERP_MODE_NONE
:
3938 if (location
== INTERP_CENTER
)
3939 return ctx
->persp_center
;
3940 else if (location
== INTERP_CENTROID
)
3941 return ctx
->persp_centroid
;
3942 else if (location
== INTERP_SAMPLE
)
3943 return ctx
->persp_sample
;
3945 case INTERP_MODE_NOPERSPECTIVE
:
3946 if (location
== INTERP_CENTER
)
3947 return ctx
->linear_center
;
3948 else if (location
== INTERP_CENTROID
)
3949 return ctx
->linear_centroid
;
3950 else if (location
== INTERP_SAMPLE
)
3951 return ctx
->linear_sample
;
3957 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
3958 LLVMValueRef sample_id
)
3960 LLVMValueRef result
;
3961 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
3963 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
3964 const_array(ctx
->ac
.v2f32
, 64), "");
3966 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
3967 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
3972 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
3974 LLVMValueRef values
[2];
3976 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
3977 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
3978 return ac_build_gather_values(&ctx
->ac
, values
, 2);
3981 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
3982 const nir_intrinsic_instr
*instr
)
3984 LLVMValueRef result
[4];
3985 LLVMValueRef interp_param
, attr_number
;
3988 LLVMValueRef src_c0
= NULL
;
3989 LLVMValueRef src_c1
= NULL
;
3990 LLVMValueRef src0
= NULL
;
3991 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
3992 switch (instr
->intrinsic
) {
3993 case nir_intrinsic_interp_var_at_centroid
:
3994 location
= INTERP_CENTROID
;
3996 case nir_intrinsic_interp_var_at_sample
:
3997 case nir_intrinsic_interp_var_at_offset
:
3998 location
= INTERP_CENTER
;
3999 src0
= get_src(ctx
->nir
, instr
->src
[0]);
4005 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4006 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_0
, ""));
4007 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_1
, ""));
4008 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4009 LLVMValueRef sample_position
;
4010 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4012 /* fetch sample ID */
4013 sample_position
= load_sample_position(ctx
, src0
);
4015 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_0
, "");
4016 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
4017 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_1
, "");
4018 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
4020 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4021 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4023 if (location
== INTERP_CENTER
) {
4024 LLVMValueRef ij_out
[2];
4025 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
4028 * take the I then J parameters, and the DDX/Y for it, and
4029 * calculate the IJ inputs for the interpolator.
4030 * temp1 = ddx * offset/sample.x + I;
4031 * interp_param.I = ddy * offset/sample.y + temp1;
4032 * temp1 = ddx * offset/sample.x + J;
4033 * interp_param.J = ddy * offset/sample.y + temp1;
4035 for (unsigned i
= 0; i
< 2; i
++) {
4036 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4037 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4038 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
4039 ddxy_out
, ix_ll
, "");
4040 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
4041 ddxy_out
, iy_ll
, "");
4042 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
4043 interp_param
, ix_ll
, "");
4044 LLVMValueRef temp1
, temp2
;
4046 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
4049 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
4050 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
4052 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
4053 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
4055 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
4056 temp2
, ctx
->ac
.i32
, "");
4058 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4062 for (chan
= 0; chan
< 4; chan
++) {
4063 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4066 interp_param
= LLVMBuildBitCast(ctx
->builder
,
4067 interp_param
, ctx
->ac
.v2f32
, "");
4068 LLVMValueRef i
= LLVMBuildExtractElement(
4069 ctx
->builder
, interp_param
, ctx
->ac
.i32_0
, "");
4070 LLVMValueRef j
= LLVMBuildExtractElement(
4071 ctx
->builder
, interp_param
, ctx
->ac
.i32_1
, "");
4073 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4074 llvm_chan
, attr_number
,
4075 ctx
->prim_mask
, i
, j
);
4077 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4078 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4079 llvm_chan
, attr_number
,
4083 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4084 instr
->variables
[0]->var
->data
.location_frac
);
4088 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4090 LLVMValueRef gs_next_vertex
;
4091 LLVMValueRef can_emit
;
4093 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4095 /* Write vertex attribute values to GSVS ring */
4096 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
4097 ctx
->gs_next_vertex
,
4100 /* If this thread has already emitted the declared maximum number of
4101 * vertices, kill it: excessive vertex emissions are not supposed to
4102 * have any effect, and GS threads have no externally observable
4103 * effects other than emitting vertices.
4105 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
4106 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4107 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4109 /* loop num outputs */
4111 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
4112 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4117 if (!(ctx
->output_mask
& (1ull << i
)))
4120 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4121 /* pack clip and cull into a single set of slots */
4122 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4126 for (unsigned j
= 0; j
< length
; j
++) {
4127 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4129 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4130 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4131 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4133 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4135 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4137 voffset
, ctx
->gs2vs_offset
, 0,
4143 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4145 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4147 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4151 visit_end_primitive(struct nir_to_llvm_context
*ctx
,
4152 const nir_intrinsic_instr
*instr
)
4154 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4158 load_tess_coord(struct ac_shader_abi
*abi
, LLVMTypeRef type
,
4159 unsigned num_components
)
4161 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4163 LLVMValueRef coord
[4] = {
4170 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4171 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4172 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4174 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, num_components
);
4175 return LLVMBuildBitCast(ctx
->builder
, result
, type
, "");
4178 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4179 nir_intrinsic_instr
*instr
)
4181 LLVMValueRef result
= NULL
;
4183 switch (instr
->intrinsic
) {
4184 case nir_intrinsic_load_work_group_id
: {
4185 LLVMValueRef values
[3];
4187 for (int i
= 0; i
< 3; i
++) {
4188 values
[i
] = ctx
->nctx
->workgroup_ids
[i
] ?
4189 ctx
->nctx
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4192 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4195 case nir_intrinsic_load_base_vertex
: {
4196 result
= ctx
->abi
->base_vertex
;
4199 case nir_intrinsic_load_vertex_id_zero_base
: {
4200 result
= ctx
->abi
->vertex_id
;
4203 case nir_intrinsic_load_local_invocation_id
: {
4204 result
= ctx
->nctx
->local_invocation_ids
;
4207 case nir_intrinsic_load_base_instance
:
4208 result
= ctx
->abi
->start_instance
;
4210 case nir_intrinsic_load_draw_id
:
4211 result
= ctx
->abi
->draw_id
;
4213 case nir_intrinsic_load_view_index
:
4214 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4216 case nir_intrinsic_load_invocation_id
:
4217 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4218 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4220 result
= ctx
->abi
->gs_invocation_id
;
4222 case nir_intrinsic_load_primitive_id
:
4223 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4224 result
= ctx
->abi
->gs_prim_id
;
4225 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4226 result
= ctx
->abi
->tcs_patch_id
;
4227 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4228 result
= ctx
->abi
->tes_patch_id
;
4230 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4232 case nir_intrinsic_load_sample_id
:
4233 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4235 case nir_intrinsic_load_sample_pos
:
4236 result
= load_sample_pos(ctx
);
4238 case nir_intrinsic_load_sample_mask_in
:
4239 result
= ctx
->abi
->sample_coverage
;
4241 case nir_intrinsic_load_frag_coord
: {
4242 LLVMValueRef values
[4] = {
4243 ctx
->abi
->frag_pos
[0],
4244 ctx
->abi
->frag_pos
[1],
4245 ctx
->abi
->frag_pos
[2],
4246 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4248 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4251 case nir_intrinsic_load_front_face
:
4252 result
= ctx
->abi
->front_face
;
4254 case nir_intrinsic_load_instance_id
:
4255 result
= ctx
->abi
->instance_id
;
4257 case nir_intrinsic_load_num_work_groups
:
4258 result
= ctx
->nctx
->num_work_groups
;
4260 case nir_intrinsic_load_local_invocation_index
:
4261 result
= visit_load_local_invocation_index(ctx
->nctx
);
4263 case nir_intrinsic_load_push_constant
:
4264 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4266 case nir_intrinsic_vulkan_resource_index
:
4267 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4269 case nir_intrinsic_vulkan_resource_reindex
:
4270 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4272 case nir_intrinsic_store_ssbo
:
4273 visit_store_ssbo(ctx
, instr
);
4275 case nir_intrinsic_load_ssbo
:
4276 result
= visit_load_buffer(ctx
, instr
);
4278 case nir_intrinsic_ssbo_atomic_add
:
4279 case nir_intrinsic_ssbo_atomic_imin
:
4280 case nir_intrinsic_ssbo_atomic_umin
:
4281 case nir_intrinsic_ssbo_atomic_imax
:
4282 case nir_intrinsic_ssbo_atomic_umax
:
4283 case nir_intrinsic_ssbo_atomic_and
:
4284 case nir_intrinsic_ssbo_atomic_or
:
4285 case nir_intrinsic_ssbo_atomic_xor
:
4286 case nir_intrinsic_ssbo_atomic_exchange
:
4287 case nir_intrinsic_ssbo_atomic_comp_swap
:
4288 result
= visit_atomic_ssbo(ctx
, instr
);
4290 case nir_intrinsic_load_ubo
:
4291 result
= visit_load_ubo_buffer(ctx
, instr
);
4293 case nir_intrinsic_get_buffer_size
:
4294 result
= visit_get_buffer_size(ctx
, instr
);
4296 case nir_intrinsic_load_var
:
4297 result
= visit_load_var(ctx
, instr
);
4299 case nir_intrinsic_store_var
:
4300 visit_store_var(ctx
, instr
);
4302 case nir_intrinsic_image_load
:
4303 result
= visit_image_load(ctx
, instr
);
4305 case nir_intrinsic_image_store
:
4306 visit_image_store(ctx
, instr
);
4308 case nir_intrinsic_image_atomic_add
:
4309 case nir_intrinsic_image_atomic_min
:
4310 case nir_intrinsic_image_atomic_max
:
4311 case nir_intrinsic_image_atomic_and
:
4312 case nir_intrinsic_image_atomic_or
:
4313 case nir_intrinsic_image_atomic_xor
:
4314 case nir_intrinsic_image_atomic_exchange
:
4315 case nir_intrinsic_image_atomic_comp_swap
:
4316 result
= visit_image_atomic(ctx
, instr
);
4318 case nir_intrinsic_image_size
:
4319 result
= visit_image_size(ctx
, instr
);
4321 case nir_intrinsic_discard
:
4322 ac_build_intrinsic(&ctx
->ac
, "llvm.AMDGPU.kilp",
4323 LLVMVoidTypeInContext(ctx
->ac
.context
),
4324 NULL
, 0, AC_FUNC_ATTR_LEGACY
);
4326 case nir_intrinsic_discard_if
:
4327 emit_discard_if(ctx
, instr
);
4329 case nir_intrinsic_memory_barrier
:
4330 case nir_intrinsic_group_memory_barrier
:
4331 case nir_intrinsic_memory_barrier_atomic_counter
:
4332 case nir_intrinsic_memory_barrier_buffer
:
4333 case nir_intrinsic_memory_barrier_image
:
4334 case nir_intrinsic_memory_barrier_shared
:
4335 emit_membar(ctx
->nctx
, instr
);
4337 case nir_intrinsic_barrier
:
4338 emit_barrier(&ctx
->ac
, ctx
->stage
);
4340 case nir_intrinsic_var_atomic_add
:
4341 case nir_intrinsic_var_atomic_imin
:
4342 case nir_intrinsic_var_atomic_umin
:
4343 case nir_intrinsic_var_atomic_imax
:
4344 case nir_intrinsic_var_atomic_umax
:
4345 case nir_intrinsic_var_atomic_and
:
4346 case nir_intrinsic_var_atomic_or
:
4347 case nir_intrinsic_var_atomic_xor
:
4348 case nir_intrinsic_var_atomic_exchange
:
4349 case nir_intrinsic_var_atomic_comp_swap
:
4350 result
= visit_var_atomic(ctx
->nctx
, instr
);
4352 case nir_intrinsic_interp_var_at_centroid
:
4353 case nir_intrinsic_interp_var_at_sample
:
4354 case nir_intrinsic_interp_var_at_offset
:
4355 result
= visit_interp(ctx
->nctx
, instr
);
4357 case nir_intrinsic_emit_vertex
:
4358 assert(instr
->const_index
[0] == 0);
4359 ctx
->abi
->emit_vertex(ctx
->abi
, 0, ctx
->outputs
);
4361 case nir_intrinsic_end_primitive
:
4362 visit_end_primitive(ctx
->nctx
, instr
);
4364 case nir_intrinsic_load_tess_coord
: {
4365 LLVMTypeRef type
= ctx
->nctx
?
4366 get_def_type(ctx
->nctx
->nir
, &instr
->dest
.ssa
) :
4368 result
= ctx
->abi
->load_tess_coord(ctx
->abi
, type
, instr
->num_components
);
4371 case nir_intrinsic_load_tess_level_outer
:
4372 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4374 case nir_intrinsic_load_tess_level_inner
:
4375 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4377 case nir_intrinsic_load_patch_vertices_in
:
4378 result
= LLVMConstInt(ctx
->ac
.i32
, ctx
->nctx
->options
->key
.tcs
.input_vertices
, false);
4381 fprintf(stderr
, "Unknown intrinsic: ");
4382 nir_print_instr(&instr
->instr
, stderr
);
4383 fprintf(stderr
, "\n");
4387 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4391 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4392 LLVMValueRef buffer_ptr
, bool write
)
4394 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4396 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4397 ctx
->shader_info
->fs
.writes_memory
= true;
4399 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4402 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4404 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4406 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4409 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4410 unsigned descriptor_set
,
4411 unsigned base_index
,
4412 unsigned constant_index
,
4414 enum ac_descriptor_type desc_type
,
4415 bool image
, bool write
)
4417 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4418 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4419 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4420 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4421 unsigned offset
= binding
->offset
;
4422 unsigned stride
= binding
->size
;
4424 LLVMBuilderRef builder
= ctx
->builder
;
4427 assert(base_index
< layout
->binding_count
);
4429 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4430 ctx
->shader_info
->fs
.writes_memory
= true;
4432 switch (desc_type
) {
4434 type
= ctx
->ac
.v8i32
;
4438 type
= ctx
->ac
.v8i32
;
4442 case AC_DESC_SAMPLER
:
4443 type
= ctx
->ac
.v4i32
;
4444 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4449 case AC_DESC_BUFFER
:
4450 type
= ctx
->ac
.v4i32
;
4454 unreachable("invalid desc_type\n");
4457 offset
+= constant_index
* stride
;
4459 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4460 (!index
|| binding
->immutable_samplers_equal
)) {
4461 if (binding
->immutable_samplers_equal
)
4464 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4466 LLVMValueRef constants
[] = {
4467 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4468 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4469 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4470 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4472 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4475 assert(stride
% type_size
== 0);
4478 index
= ctx
->ac
.i32_0
;
4480 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4482 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4483 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4485 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4488 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4489 const nir_deref_var
*deref
,
4490 enum ac_descriptor_type desc_type
,
4491 const nir_tex_instr
*tex_instr
,
4492 bool image
, bool write
)
4494 LLVMValueRef index
= NULL
;
4495 unsigned constant_index
= 0;
4496 unsigned descriptor_set
;
4497 unsigned base_index
;
4500 assert(tex_instr
&& !image
);
4502 base_index
= tex_instr
->sampler_index
;
4504 const nir_deref
*tail
= &deref
->deref
;
4505 while (tail
->child
) {
4506 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4507 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4512 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4514 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4515 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4517 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4518 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4523 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4526 constant_index
+= child
->base_offset
* array_size
;
4528 tail
= &child
->deref
;
4530 descriptor_set
= deref
->var
->data
.descriptor_set
;
4531 base_index
= deref
->var
->data
.binding
;
4534 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4537 constant_index
, index
,
4538 desc_type
, image
, write
);
4541 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4542 struct ac_image_args
*args
,
4543 const nir_tex_instr
*instr
,
4545 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4546 LLVMValueRef
*param
, unsigned count
,
4549 unsigned is_rect
= 0;
4550 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4552 if (op
== nir_texop_lod
)
4554 /* Pad to power of two vector */
4555 while (count
< util_next_power_of_two(count
))
4556 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4559 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4561 args
->addr
= param
[0];
4563 args
->resource
= res_ptr
;
4564 args
->sampler
= samp_ptr
;
4566 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4567 args
->addr
= param
[0];
4571 args
->dmask
= dmask
;
4572 args
->unorm
= is_rect
;
4576 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4579 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4580 * filtering manually. The driver sets img7 to a mask clearing
4581 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4582 * s_and_b32 samp0, samp0, img7
4585 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4587 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4588 LLVMValueRef res
, LLVMValueRef samp
)
4590 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4591 LLVMValueRef img7
, samp0
;
4593 if (ctx
->ac
.chip_class
>= VI
)
4596 img7
= LLVMBuildExtractElement(builder
, res
,
4597 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4598 samp0
= LLVMBuildExtractElement(builder
, samp
,
4599 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4600 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4601 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4602 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4605 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4606 nir_tex_instr
*instr
,
4607 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4608 LLVMValueRef
*fmask_ptr
)
4610 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4611 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4613 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4616 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4618 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4619 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4620 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4622 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4623 instr
->op
== nir_texop_samples_identical
))
4624 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4627 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4630 coord
= ac_to_float(ctx
, coord
);
4631 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4632 coord
= ac_to_integer(ctx
, coord
);
4636 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4638 LLVMValueRef result
= NULL
;
4639 struct ac_image_args args
= { 0 };
4640 unsigned dmask
= 0xf;
4641 LLVMValueRef address
[16];
4642 LLVMValueRef coords
[5];
4643 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4644 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4645 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4646 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4647 LLVMValueRef derivs
[6];
4648 unsigned chan
, count
= 0;
4649 unsigned const_src
= 0, num_deriv_comp
= 0;
4650 bool lod_is_zero
= false;
4652 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4654 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4655 switch (instr
->src
[i
].src_type
) {
4656 case nir_tex_src_coord
:
4657 coord
= get_src(ctx
, instr
->src
[i
].src
);
4659 case nir_tex_src_projector
:
4661 case nir_tex_src_comparator
:
4662 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4664 case nir_tex_src_offset
:
4665 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4668 case nir_tex_src_bias
:
4669 bias
= get_src(ctx
, instr
->src
[i
].src
);
4671 case nir_tex_src_lod
: {
4672 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4674 if (val
&& val
->i32
[0] == 0)
4676 lod
= get_src(ctx
, instr
->src
[i
].src
);
4679 case nir_tex_src_ms_index
:
4680 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4682 case nir_tex_src_ms_mcs
:
4684 case nir_tex_src_ddx
:
4685 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4686 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4688 case nir_tex_src_ddy
:
4689 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4691 case nir_tex_src_texture_offset
:
4692 case nir_tex_src_sampler_offset
:
4693 case nir_tex_src_plane
:
4699 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4700 result
= get_buffer_size(ctx
, res_ptr
, true);
4704 if (instr
->op
== nir_texop_texture_samples
) {
4705 LLVMValueRef res
, samples
, is_msaa
;
4706 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4707 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4708 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4709 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4710 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4711 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4712 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4713 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4714 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4716 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4717 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4718 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4719 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4720 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4722 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4729 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4730 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4732 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4733 LLVMValueRef offset
[3], pack
;
4734 for (chan
= 0; chan
< 3; ++chan
)
4735 offset
[chan
] = ctx
->ac
.i32_0
;
4738 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4739 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4740 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4741 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4743 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4744 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4746 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4747 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4748 address
[count
++] = pack
;
4751 /* pack LOD bias value */
4752 if (instr
->op
== nir_texop_txb
&& bias
) {
4753 address
[count
++] = bias
;
4756 /* Pack depth comparison value */
4757 if (instr
->is_shadow
&& comparator
) {
4758 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4759 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4761 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4762 * so the depth comparison value isn't clamped for Z16 and
4763 * Z24 anymore. Do it manually here.
4765 * It's unnecessary if the original texture format was
4766 * Z32_FLOAT, but we don't know that here.
4768 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4769 z
= ac_build_clamp(&ctx
->ac
, z
);
4771 address
[count
++] = z
;
4774 /* pack derivatives */
4776 int num_src_deriv_channels
, num_dest_deriv_channels
;
4777 switch (instr
->sampler_dim
) {
4778 case GLSL_SAMPLER_DIM_3D
:
4779 case GLSL_SAMPLER_DIM_CUBE
:
4781 num_src_deriv_channels
= 3;
4782 num_dest_deriv_channels
= 3;
4784 case GLSL_SAMPLER_DIM_2D
:
4786 num_src_deriv_channels
= 2;
4787 num_dest_deriv_channels
= 2;
4790 case GLSL_SAMPLER_DIM_1D
:
4791 num_src_deriv_channels
= 1;
4792 if (ctx
->ac
.chip_class
>= GFX9
) {
4793 num_dest_deriv_channels
= 2;
4796 num_dest_deriv_channels
= 1;
4802 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4803 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4804 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4806 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4807 derivs
[i
] = ctx
->ac
.f32_0
;
4808 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4812 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4813 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4814 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4815 if (instr
->coord_components
== 3)
4816 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4817 ac_prepare_cube_coords(&ctx
->ac
,
4818 instr
->op
== nir_texop_txd
, instr
->is_array
,
4819 instr
->op
== nir_texop_lod
, coords
, derivs
);
4825 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4826 address
[count
++] = derivs
[i
];
4829 /* Pack texture coordinates */
4831 address
[count
++] = coords
[0];
4832 if (instr
->coord_components
> 1) {
4833 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4834 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4836 address
[count
++] = coords
[1];
4838 if (instr
->coord_components
> 2) {
4839 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4840 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4841 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4842 instr
->op
!= nir_texop_txf
) {
4843 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4845 address
[count
++] = coords
[2];
4848 if (ctx
->ac
.chip_class
>= GFX9
) {
4849 LLVMValueRef filler
;
4850 if (instr
->op
== nir_texop_txf
)
4851 filler
= ctx
->ac
.i32_0
;
4853 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4855 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4856 /* No nir_texop_lod, because it does not take a slice
4857 * even with array textures. */
4858 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4859 address
[count
] = address
[count
- 1];
4860 address
[count
- 1] = filler
;
4863 address
[count
++] = filler
;
4869 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
4870 instr
->op
== nir_texop_txf
)) {
4871 address
[count
++] = lod
;
4872 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
4873 address
[count
++] = sample_index
;
4874 } else if(instr
->op
== nir_texop_txs
) {
4877 address
[count
++] = lod
;
4879 address
[count
++] = ctx
->ac
.i32_0
;
4882 for (chan
= 0; chan
< count
; chan
++) {
4883 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4884 address
[chan
], ctx
->ac
.i32
, "");
4887 if (instr
->op
== nir_texop_samples_identical
) {
4888 LLVMValueRef txf_address
[4];
4889 struct ac_image_args txf_args
= { 0 };
4890 unsigned txf_count
= count
;
4891 memcpy(txf_address
, address
, sizeof(txf_address
));
4893 if (!instr
->is_array
)
4894 txf_address
[2] = ctx
->ac
.i32_0
;
4895 txf_address
[3] = ctx
->ac
.i32_0
;
4897 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
4899 txf_address
, txf_count
, 0xf);
4901 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
4903 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4904 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
4908 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
4909 instr
->op
!= nir_texop_txs
) {
4910 unsigned sample_chan
= instr
->is_array
? 3 : 2;
4911 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
4914 instr
->is_array
? address
[2] : NULL
,
4915 address
[sample_chan
],
4919 if (offsets
&& instr
->op
== nir_texop_txf
) {
4920 nir_const_value
*const_offset
=
4921 nir_src_as_const_value(instr
->src
[const_src
].src
);
4922 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
4923 assert(const_offset
);
4924 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
4925 if (num_offsets
> 2)
4926 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
4927 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
4928 if (num_offsets
> 1)
4929 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
4930 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
4931 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
4932 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
4936 /* TODO TG4 support */
4937 if (instr
->op
== nir_texop_tg4
) {
4938 if (instr
->is_shadow
)
4941 dmask
= 1 << instr
->component
;
4943 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
4944 res_ptr
, samp_ptr
, address
, count
, dmask
);
4946 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
4948 if (instr
->op
== nir_texop_query_levels
)
4949 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4950 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
4951 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
4952 instr
->op
!= nir_texop_tg4
)
4953 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4954 else if (instr
->op
== nir_texop_txs
&&
4955 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4957 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4958 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
4959 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4960 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
4961 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
4962 } else if (ctx
->ac
.chip_class
>= GFX9
&&
4963 instr
->op
== nir_texop_txs
&&
4964 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
4966 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4967 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4968 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
4970 } else if (instr
->dest
.ssa
.num_components
!= 4)
4971 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
4975 assert(instr
->dest
.is_ssa
);
4976 result
= ac_to_integer(&ctx
->ac
, result
);
4977 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4982 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
4984 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
4985 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
4987 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4988 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
4991 static void visit_post_phi(struct ac_nir_context
*ctx
,
4992 nir_phi_instr
*instr
,
4993 LLVMValueRef llvm_phi
)
4995 nir_foreach_phi_src(src
, instr
) {
4996 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
4997 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
4999 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5003 static void phi_post_pass(struct ac_nir_context
*ctx
)
5005 struct hash_entry
*entry
;
5006 hash_table_foreach(ctx
->phis
, entry
) {
5007 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5008 (LLVMValueRef
)entry
->data
);
5013 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5014 const nir_ssa_undef_instr
*instr
)
5016 unsigned num_components
= instr
->def
.num_components
;
5019 if (num_components
== 1)
5020 undef
= LLVMGetUndef(ctx
->ac
.i32
);
5022 undef
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, num_components
));
5024 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5027 static void visit_jump(struct ac_nir_context
*ctx
,
5028 const nir_jump_instr
*instr
)
5030 switch (instr
->type
) {
5031 case nir_jump_break
:
5032 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5033 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5035 case nir_jump_continue
:
5036 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5037 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5040 fprintf(stderr
, "Unknown NIR jump instr: ");
5041 nir_print_instr(&instr
->instr
, stderr
);
5042 fprintf(stderr
, "\n");
5047 static void visit_cf_list(struct ac_nir_context
*ctx
,
5048 struct exec_list
*list
);
5050 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5052 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5053 nir_foreach_instr(instr
, block
)
5055 switch (instr
->type
) {
5056 case nir_instr_type_alu
:
5057 visit_alu(ctx
, nir_instr_as_alu(instr
));
5059 case nir_instr_type_load_const
:
5060 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5062 case nir_instr_type_intrinsic
:
5063 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5065 case nir_instr_type_tex
:
5066 visit_tex(ctx
, nir_instr_as_tex(instr
));
5068 case nir_instr_type_phi
:
5069 visit_phi(ctx
, nir_instr_as_phi(instr
));
5071 case nir_instr_type_ssa_undef
:
5072 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5074 case nir_instr_type_jump
:
5075 visit_jump(ctx
, nir_instr_as_jump(instr
));
5078 fprintf(stderr
, "Unknown NIR instr type: ");
5079 nir_print_instr(instr
, stderr
);
5080 fprintf(stderr
, "\n");
5085 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5088 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5090 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5092 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5093 LLVMBasicBlockRef merge_block
=
5094 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5095 LLVMBasicBlockRef if_block
=
5096 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5097 LLVMBasicBlockRef else_block
= merge_block
;
5098 if (!exec_list_is_empty(&if_stmt
->else_list
))
5099 else_block
= LLVMAppendBasicBlockInContext(
5100 ctx
->ac
.context
, fn
, "");
5102 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5104 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5106 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5107 visit_cf_list(ctx
, &if_stmt
->then_list
);
5108 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5109 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5111 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5112 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5113 visit_cf_list(ctx
, &if_stmt
->else_list
);
5114 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5115 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5118 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5121 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5123 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5124 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5125 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5127 ctx
->continue_block
=
5128 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5130 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5132 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5133 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5134 visit_cf_list(ctx
, &loop
->body
);
5136 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5137 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5138 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5140 ctx
->continue_block
= continue_parent
;
5141 ctx
->break_block
= break_parent
;
5144 static void visit_cf_list(struct ac_nir_context
*ctx
,
5145 struct exec_list
*list
)
5147 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5149 switch (node
->type
) {
5150 case nir_cf_node_block
:
5151 visit_block(ctx
, nir_cf_node_as_block(node
));
5154 case nir_cf_node_if
:
5155 visit_if(ctx
, nir_cf_node_as_if(node
));
5158 case nir_cf_node_loop
:
5159 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5169 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5170 struct nir_variable
*variable
)
5172 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5173 LLVMValueRef t_offset
;
5174 LLVMValueRef t_list
;
5176 LLVMValueRef buffer_index
;
5177 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5178 int idx
= variable
->data
.location
;
5179 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5181 variable
->data
.driver_location
= idx
* 4;
5183 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << index
)) {
5184 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5185 ctx
->abi
.start_instance
, "");
5186 if (ctx
->options
->key
.vs
.as_ls
) {
5187 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5188 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5190 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5191 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5194 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5195 ctx
->abi
.base_vertex
, "");
5197 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5198 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5200 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5202 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5207 for (unsigned chan
= 0; chan
< 4; chan
++) {
5208 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5209 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5210 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5211 input
, llvm_chan
, ""));
5216 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5218 LLVMValueRef interp_param
,
5219 LLVMValueRef prim_mask
,
5220 LLVMValueRef result
[4])
5222 LLVMValueRef attr_number
;
5225 bool interp
= interp_param
!= NULL
;
5227 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5229 /* fs.constant returns the param from the middle vertex, so it's not
5230 * really useful for flat shading. It's meant to be used for custom
5231 * interpolation (but the intrinsic can't fetch from the other two
5234 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5235 * to do the right thing. The only reason we use fs.constant is that
5236 * fs.interp cannot be used on integers, because they can be equal
5240 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5243 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5245 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5249 for (chan
= 0; chan
< 4; chan
++) {
5250 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5253 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5258 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5259 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5268 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5269 struct nir_variable
*variable
)
5271 int idx
= variable
->data
.location
;
5272 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5273 LLVMValueRef interp
;
5275 variable
->data
.driver_location
= idx
* 4;
5276 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5278 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5279 unsigned interp_type
;
5280 if (variable
->data
.sample
) {
5281 interp_type
= INTERP_SAMPLE
;
5282 ctx
->shader_info
->info
.ps
.force_persample
= true;
5283 } else if (variable
->data
.centroid
)
5284 interp_type
= INTERP_CENTROID
;
5286 interp_type
= INTERP_CENTER
;
5288 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5292 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5293 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5298 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5299 struct nir_shader
*nir
) {
5300 nir_foreach_variable(variable
, &nir
->inputs
)
5301 handle_vs_input_decl(ctx
, variable
);
5305 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5306 struct nir_shader
*nir
)
5308 if (!ctx
->options
->key
.fs
.multisample
)
5311 bool uses_center
= false;
5312 bool uses_centroid
= false;
5313 nir_foreach_variable(variable
, &nir
->inputs
) {
5314 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5315 variable
->data
.sample
)
5318 if (variable
->data
.centroid
)
5319 uses_centroid
= true;
5324 if (uses_center
&& uses_centroid
) {
5325 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5326 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5327 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5332 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5333 struct nir_shader
*nir
)
5335 prepare_interp_optimize(ctx
, nir
);
5337 nir_foreach_variable(variable
, &nir
->inputs
)
5338 handle_fs_input_decl(ctx
, variable
);
5342 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5343 ctx
->shader_info
->info
.needs_multiview_view_index
)
5344 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5346 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5347 LLVMValueRef interp_param
;
5348 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5350 if (!(ctx
->input_mask
& (1ull << i
)))
5353 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5354 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5355 interp_param
= *inputs
;
5356 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5360 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5362 } else if (i
== VARYING_SLOT_POS
) {
5363 for(int i
= 0; i
< 3; ++i
)
5364 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5366 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5367 ctx
->abi
.frag_pos
[3]);
5370 ctx
->shader_info
->fs
.num_interp
= index
;
5371 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5372 ctx
->shader_info
->fs
.has_pcoord
= true;
5373 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5374 ctx
->shader_info
->fs
.prim_id_input
= true;
5375 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5376 ctx
->shader_info
->fs
.layer_input
= true;
5377 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5379 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5380 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5384 ac_build_alloca(struct ac_llvm_context
*ac
,
5388 LLVMBuilderRef builder
= ac
->builder
;
5389 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5390 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5391 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5392 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5393 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5397 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5399 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5402 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5403 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5405 LLVMDisposeBuilder(first_builder
);
5410 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5414 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5415 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5420 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5421 struct nir_variable
*variable
,
5422 struct nir_shader
*shader
,
5423 gl_shader_stage stage
)
5425 int idx
= variable
->data
.location
+ variable
->data
.index
;
5426 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5427 uint64_t mask_attribs
;
5429 variable
->data
.driver_location
= idx
* 4;
5431 /* tess ctrl has it's own load/store paths for outputs */
5432 if (stage
== MESA_SHADER_TESS_CTRL
)
5435 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5436 if (stage
== MESA_SHADER_VERTEX
||
5437 stage
== MESA_SHADER_TESS_EVAL
||
5438 stage
== MESA_SHADER_GEOMETRY
) {
5439 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5440 int length
= shader
->info
.clip_distance_array_size
+
5441 shader
->info
.cull_distance_array_size
;
5442 if (stage
== MESA_SHADER_VERTEX
) {
5443 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5444 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5446 if (stage
== MESA_SHADER_TESS_EVAL
) {
5447 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5448 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5455 mask_attribs
= 1ull << idx
;
5459 ctx
->output_mask
|= mask_attribs
;
5463 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5464 struct nir_shader
*nir
,
5465 struct nir_variable
*variable
)
5467 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5468 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5470 /* tess ctrl has it's own load/store paths for outputs */
5471 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5474 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5475 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5476 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5477 int idx
= variable
->data
.location
+ variable
->data
.index
;
5478 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5479 int length
= nir
->info
.clip_distance_array_size
+
5480 nir
->info
.cull_distance_array_size
;
5489 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5490 for (unsigned chan
= 0; chan
< 4; chan
++) {
5491 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5492 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5498 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5499 enum glsl_base_type type
)
5503 case GLSL_TYPE_UINT
:
5504 case GLSL_TYPE_BOOL
:
5505 case GLSL_TYPE_SUBROUTINE
:
5507 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5509 case GLSL_TYPE_INT64
:
5510 case GLSL_TYPE_UINT64
:
5512 case GLSL_TYPE_DOUBLE
:
5515 unreachable("unknown GLSL type");
5520 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5521 const struct glsl_type
*type
)
5523 if (glsl_type_is_scalar(type
)) {
5524 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5527 if (glsl_type_is_vector(type
)) {
5528 return LLVMVectorType(
5529 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5530 glsl_get_vector_elements(type
));
5533 if (glsl_type_is_matrix(type
)) {
5534 return LLVMArrayType(
5535 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5536 glsl_get_matrix_columns(type
));
5539 if (glsl_type_is_array(type
)) {
5540 return LLVMArrayType(
5541 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5542 glsl_get_length(type
));
5545 assert(glsl_type_is_struct(type
));
5547 LLVMTypeRef member_types
[glsl_get_length(type
)];
5549 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5551 glsl_to_llvm_type(ctx
,
5552 glsl_get_struct_field(type
, i
));
5555 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5556 glsl_get_length(type
), false);
5560 setup_locals(struct ac_nir_context
*ctx
,
5561 struct nir_function
*func
)
5564 ctx
->num_locals
= 0;
5565 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5566 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5567 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5568 ctx
->num_locals
+= attrib_count
;
5570 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5574 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5575 for (j
= 0; j
< 4; j
++) {
5576 ctx
->locals
[i
* 4 + j
] =
5577 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5583 setup_shared(struct ac_nir_context
*ctx
,
5584 struct nir_shader
*nir
)
5586 nir_foreach_variable(variable
, &nir
->shared
) {
5587 LLVMValueRef shared
=
5588 LLVMAddGlobalInAddressSpace(
5589 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5590 variable
->name
? variable
->name
: "",
5592 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5597 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5599 v
= ac_to_float(ctx
, v
);
5600 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5601 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5605 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5606 LLVMValueRef src0
, LLVMValueRef src1
)
5608 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5609 LLVMValueRef comp
[2];
5611 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5612 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5613 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5614 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5617 /* Initialize arguments for the shader export intrinsic */
5619 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5620 LLVMValueRef
*values
,
5622 struct ac_export_args
*args
)
5624 /* Default is 0xf. Adjusted below depending on the format. */
5625 args
->enabled_channels
= 0xf;
5627 /* Specify whether the EXEC mask represents the valid mask */
5628 args
->valid_mask
= 0;
5630 /* Specify whether this is the last export */
5633 /* Specify the target we are exporting */
5634 args
->target
= target
;
5636 args
->compr
= false;
5637 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5638 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5639 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5640 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5645 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5646 LLVMValueRef val
[4];
5647 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5648 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5649 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5650 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5652 switch(col_format
) {
5653 case V_028714_SPI_SHADER_ZERO
:
5654 args
->enabled_channels
= 0; /* writemask */
5655 args
->target
= V_008DFC_SQ_EXP_NULL
;
5658 case V_028714_SPI_SHADER_32_R
:
5659 args
->enabled_channels
= 1;
5660 args
->out
[0] = values
[0];
5663 case V_028714_SPI_SHADER_32_GR
:
5664 args
->enabled_channels
= 0x3;
5665 args
->out
[0] = values
[0];
5666 args
->out
[1] = values
[1];
5669 case V_028714_SPI_SHADER_32_AR
:
5670 args
->enabled_channels
= 0x9;
5671 args
->out
[0] = values
[0];
5672 args
->out
[3] = values
[3];
5675 case V_028714_SPI_SHADER_FP16_ABGR
:
5678 for (unsigned chan
= 0; chan
< 2; chan
++) {
5679 LLVMValueRef pack_args
[2] = {
5681 values
[2 * chan
+ 1]
5683 LLVMValueRef packed
;
5685 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5686 args
->out
[chan
] = packed
;
5690 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5691 for (unsigned chan
= 0; chan
< 4; chan
++) {
5692 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5693 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5694 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5695 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5696 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5697 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5702 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5703 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5706 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5707 for (unsigned chan
= 0; chan
< 4; chan
++) {
5708 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5709 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5710 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5712 /* If positive, add 0.5, else add -0.5. */
5713 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5714 LLVMBuildSelect(ctx
->builder
,
5715 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5716 val
[chan
], ctx
->ac
.f32_0
, ""),
5717 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5718 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5719 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5723 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5724 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5727 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5728 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5729 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5730 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5732 for (unsigned chan
= 0; chan
< 4; chan
++) {
5733 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5734 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5738 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5739 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5743 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5744 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5745 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5746 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5747 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5748 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5749 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5752 for (unsigned chan
= 0; chan
< 4; chan
++) {
5753 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5754 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5755 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5759 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5760 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5765 case V_028714_SPI_SHADER_32_ABGR
:
5766 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5770 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5772 for (unsigned i
= 0; i
< 4; ++i
)
5773 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5777 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5778 bool export_prim_id
,
5779 struct ac_vs_output_info
*outinfo
)
5781 uint32_t param_count
= 0;
5783 unsigned pos_idx
, num_pos_exports
= 0;
5784 struct ac_export_args args
, pos_args
[4] = {};
5785 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5788 if (ctx
->options
->key
.has_multiview_view_index
) {
5789 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5791 for(unsigned i
= 0; i
< 4; ++i
)
5792 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5793 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5796 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5797 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5800 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5801 sizeof(outinfo
->vs_output_param_offset
));
5803 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5804 LLVMValueRef slots
[8];
5807 if (outinfo
->cull_dist_mask
)
5808 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5810 i
= VARYING_SLOT_CLIP_DIST0
;
5811 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5812 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5813 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5815 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5816 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5818 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5819 target
= V_008DFC_SQ_EXP_POS
+ 3;
5820 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5821 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5822 &args
, sizeof(args
));
5825 target
= V_008DFC_SQ_EXP_POS
+ 2;
5826 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5827 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5828 &args
, sizeof(args
));
5832 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5833 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5834 for (unsigned j
= 0; j
< 4; j
++)
5835 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5836 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5838 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5840 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5841 outinfo
->writes_pointsize
= true;
5842 psize_value
= LLVMBuildLoad(ctx
->builder
,
5843 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5846 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5847 outinfo
->writes_layer
= true;
5848 layer_value
= LLVMBuildLoad(ctx
->builder
,
5849 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5852 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5853 outinfo
->writes_viewport_index
= true;
5854 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5855 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5858 if (outinfo
->writes_pointsize
||
5859 outinfo
->writes_layer
||
5860 outinfo
->writes_viewport_index
) {
5861 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5862 (outinfo
->writes_layer
== true ? 4 : 0));
5863 pos_args
[1].valid_mask
= 0;
5864 pos_args
[1].done
= 0;
5865 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5866 pos_args
[1].compr
= 0;
5867 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
5868 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
5869 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
5870 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
5872 if (outinfo
->writes_pointsize
== true)
5873 pos_args
[1].out
[0] = psize_value
;
5874 if (outinfo
->writes_layer
== true)
5875 pos_args
[1].out
[2] = layer_value
;
5876 if (outinfo
->writes_viewport_index
== true) {
5877 if (ctx
->options
->chip_class
>= GFX9
) {
5878 /* GFX9 has the layer in out.z[10:0] and the viewport
5879 * index in out.z[19:16].
5881 LLVMValueRef v
= viewport_index_value
;
5882 v
= ac_to_integer(&ctx
->ac
, v
);
5883 v
= LLVMBuildShl(ctx
->builder
, v
,
5884 LLVMConstInt(ctx
->ac
.i32
, 16, false),
5886 v
= LLVMBuildOr(ctx
->builder
, v
,
5887 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
5889 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
5890 pos_args
[1].enabled_channels
|= 1 << 2;
5892 pos_args
[1].out
[3] = viewport_index_value
;
5893 pos_args
[1].enabled_channels
|= 1 << 3;
5897 for (i
= 0; i
< 4; i
++) {
5898 if (pos_args
[i
].out
[0])
5903 for (i
= 0; i
< 4; i
++) {
5904 if (!pos_args
[i
].out
[0])
5907 /* Specify the target we are exporting */
5908 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5909 if (pos_idx
== num_pos_exports
)
5910 pos_args
[i
].done
= 1;
5911 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
5914 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5915 LLVMValueRef values
[4];
5916 if (!(ctx
->output_mask
& (1ull << i
)))
5919 for (unsigned j
= 0; j
< 4; j
++)
5920 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5921 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5923 if (i
== VARYING_SLOT_LAYER
) {
5924 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5925 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
5927 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
5928 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5929 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5931 } else if (i
>= VARYING_SLOT_VAR0
) {
5932 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
5933 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5934 outinfo
->vs_output_param_offset
[i
] = param_count
;
5939 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5941 if (target
>= V_008DFC_SQ_EXP_POS
&&
5942 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
5943 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5944 &args
, sizeof(args
));
5946 ac_build_export(&ctx
->ac
, &args
);
5950 if (export_prim_id
) {
5951 LLVMValueRef values
[4];
5952 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5953 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5956 values
[0] = ctx
->vs_prim_id
;
5957 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
5958 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5959 for (unsigned j
= 1; j
< 4; j
++)
5960 values
[j
] = ctx
->ac
.f32_0
;
5961 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5962 ac_build_export(&ctx
->ac
, &args
);
5963 outinfo
->export_prim_id
= true;
5966 outinfo
->pos_exports
= num_pos_exports
;
5967 outinfo
->param_exports
= param_count
;
5971 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
5972 struct ac_es_output_info
*outinfo
)
5975 uint64_t max_output_written
= 0;
5976 LLVMValueRef lds_base
= NULL
;
5978 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5982 if (!(ctx
->output_mask
& (1ull << i
)))
5985 if (i
== VARYING_SLOT_CLIP_DIST0
)
5986 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5988 param_index
= shader_io_get_unique_index(i
);
5990 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
5993 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
5995 if (ctx
->ac
.chip_class
>= GFX9
) {
5996 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
5997 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
5998 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
5999 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6000 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6001 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6002 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6003 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6004 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6005 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6008 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6009 LLVMValueRef dw_addr
;
6010 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6014 if (!(ctx
->output_mask
& (1ull << i
)))
6017 if (i
== VARYING_SLOT_CLIP_DIST0
)
6018 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6020 param_index
= shader_io_get_unique_index(i
);
6023 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6024 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6027 for (j
= 0; j
< length
; j
++) {
6028 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
6029 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
6031 if (ctx
->ac
.chip_class
>= GFX9
) {
6032 ac_lds_store(&ctx
->ac
, dw_addr
,
6033 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6034 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6036 ac_build_buffer_store_dword(&ctx
->ac
,
6039 NULL
, ctx
->es2gs_offset
,
6040 (4 * param_index
+ j
) * 4,
6048 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
6050 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6051 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6052 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
6053 vertex_dw_stride
, "");
6055 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6056 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
6059 if (!(ctx
->output_mask
& (1ull << i
)))
6062 if (i
== VARYING_SLOT_CLIP_DIST0
)
6063 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6064 int param
= shader_io_get_unique_index(i
);
6065 mark_tess_output(ctx
, false, param
);
6067 mark_tess_output(ctx
, false, param
+ 1);
6068 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
6069 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6071 for (unsigned j
= 0; j
< length
; j
++) {
6072 ac_lds_store(&ctx
->ac
, dw_addr
,
6073 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
6074 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6079 struct ac_build_if_state
6081 struct nir_to_llvm_context
*ctx
;
6082 LLVMValueRef condition
;
6083 LLVMBasicBlockRef entry_block
;
6084 LLVMBasicBlockRef true_block
;
6085 LLVMBasicBlockRef false_block
;
6086 LLVMBasicBlockRef merge_block
;
6089 static LLVMBasicBlockRef
6090 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
6092 LLVMBasicBlockRef current_block
;
6093 LLVMBasicBlockRef next_block
;
6094 LLVMBasicBlockRef new_block
;
6096 /* get current basic block */
6097 current_block
= LLVMGetInsertBlock(ctx
->builder
);
6099 /* chqeck if there's another block after this one */
6100 next_block
= LLVMGetNextBasicBlock(current_block
);
6102 /* insert the new block before the next block */
6103 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6106 /* append new block after current block */
6107 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6108 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6114 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6115 struct nir_to_llvm_context
*ctx
,
6116 LLVMValueRef condition
)
6118 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
6120 memset(ifthen
, 0, sizeof *ifthen
);
6122 ifthen
->condition
= condition
;
6123 ifthen
->entry_block
= block
;
6125 /* create endif/merge basic block for the phi functions */
6126 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6128 /* create/insert true_block before merge_block */
6129 ifthen
->true_block
=
6130 LLVMInsertBasicBlockInContext(ctx
->context
,
6131 ifthen
->merge_block
,
6134 /* successive code goes into the true block */
6135 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
6139 * End a conditional.
6142 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6144 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6146 /* Insert branch to the merge block from current block */
6147 LLVMBuildBr(builder
, ifthen
->merge_block
);
6150 * Now patch in the various branch instructions.
6153 /* Insert the conditional branch instruction at the end of entry_block */
6154 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6155 if (ifthen
->false_block
) {
6156 /* we have an else clause */
6157 LLVMBuildCondBr(builder
, ifthen
->condition
,
6158 ifthen
->true_block
, ifthen
->false_block
);
6161 /* no else clause */
6162 LLVMBuildCondBr(builder
, ifthen
->condition
,
6163 ifthen
->true_block
, ifthen
->merge_block
);
6166 /* Resume building code at end of the ifthen->merge_block */
6167 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6171 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6173 unsigned stride
, outer_comps
, inner_comps
;
6174 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6175 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6176 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6177 unsigned tess_inner_index
, tess_outer_index
;
6178 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6179 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6181 emit_barrier(&ctx
->ac
, ctx
->stage
);
6183 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6203 ac_nir_build_if(&if_ctx
, ctx
,
6204 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6205 invocation_id
, ctx
->ac
.i32_0
, ""));
6207 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6208 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6210 mark_tess_output(ctx
, true, tess_inner_index
);
6211 mark_tess_output(ctx
, true, tess_outer_index
);
6212 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6213 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6214 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6215 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6216 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6218 for (i
= 0; i
< 4; i
++) {
6219 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6220 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6224 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6225 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6226 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6228 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6230 for (i
= 0; i
< outer_comps
; i
++) {
6232 ac_lds_load(&ctx
->ac
, lds_outer
);
6233 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6236 for (i
= 0; i
< inner_comps
; i
++) {
6237 inner
[i
] = out
[outer_comps
+i
] =
6238 ac_lds_load(&ctx
->ac
, lds_inner
);
6239 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6244 /* Convert the outputs to vectors for stores. */
6245 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6249 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6252 buffer
= ctx
->hs_ring_tess_factor
;
6253 tf_base
= ctx
->tess_factor_offset
;
6254 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6255 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6256 unsigned tf_offset
= 0;
6258 if (ctx
->options
->chip_class
<= VI
) {
6259 ac_nir_build_if(&inner_if_ctx
, ctx
,
6260 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6261 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6263 /* Store the dynamic HS control word. */
6264 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6265 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6266 1, ctx
->ac
.i32_0
, tf_base
,
6267 0, 1, 0, true, false);
6270 ac_nir_build_endif(&inner_if_ctx
);
6273 /* Store the tessellation factors. */
6274 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6275 MIN2(stride
, 4), byteoffset
, tf_base
,
6276 tf_offset
, 1, 0, true, false);
6278 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6279 stride
- 4, byteoffset
, tf_base
,
6280 16 + tf_offset
, 1, 0, true, false);
6282 //store to offchip for TES to read - only if TES reads them
6283 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6284 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6285 LLVMValueRef tf_inner_offset
;
6286 unsigned param_outer
, param_inner
;
6288 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6289 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6290 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6292 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6293 util_next_power_of_two(outer_comps
));
6295 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6296 outer_comps
, tf_outer_offset
,
6297 ctx
->oc_lds
, 0, 1, 0, true, false);
6299 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6300 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6301 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6303 inner_vec
= inner_comps
== 1 ? inner
[0] :
6304 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6305 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6306 inner_comps
, tf_inner_offset
,
6307 ctx
->oc_lds
, 0, 1, 0, true, false);
6310 ac_nir_build_endif(&if_ctx
);
6314 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6316 write_tess_factors(ctx
);
6320 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6321 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6322 struct ac_export_args
*args
)
6325 si_llvm_init_export_args(ctx
, color
, param
,
6329 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6330 args
->done
= 1; /* DONE bit */
6331 } else if (!args
->enabled_channels
)
6332 return false; /* unnecessary NULL export */
6338 radv_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6339 LLVMValueRef depth
, LLVMValueRef stencil
,
6340 LLVMValueRef samplemask
)
6342 struct ac_export_args args
;
6344 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6346 ac_build_export(&ctx
->ac
, &args
);
6350 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6353 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6354 struct ac_export_args color_args
[8];
6356 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6357 LLVMValueRef values
[4];
6359 if (!(ctx
->output_mask
& (1ull << i
)))
6362 if (i
== FRAG_RESULT_DEPTH
) {
6363 ctx
->shader_info
->fs
.writes_z
= true;
6364 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6365 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6366 } else if (i
== FRAG_RESULT_STENCIL
) {
6367 ctx
->shader_info
->fs
.writes_stencil
= true;
6368 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6369 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6370 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6371 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6372 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6373 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6376 for (unsigned j
= 0; j
< 4; j
++)
6377 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6378 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6380 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6381 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6383 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6389 for (unsigned i
= 0; i
< index
; i
++)
6390 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6391 if (depth
|| stencil
|| samplemask
)
6392 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6394 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6395 ac_build_export(&ctx
->ac
, &color_args
[0]);
6398 ctx
->shader_info
->fs
.output_mask
= index
? ((1ull << index
) - 1) : 0;
6402 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6404 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6408 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6409 LLVMValueRef
*addrs
)
6411 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6413 switch (ctx
->stage
) {
6414 case MESA_SHADER_VERTEX
:
6415 if (ctx
->options
->key
.vs
.as_ls
)
6416 handle_ls_outputs_post(ctx
);
6417 else if (ctx
->options
->key
.vs
.as_es
)
6418 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6420 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6421 &ctx
->shader_info
->vs
.outinfo
);
6423 case MESA_SHADER_FRAGMENT
:
6424 handle_fs_outputs_post(ctx
);
6426 case MESA_SHADER_GEOMETRY
:
6427 emit_gs_epilogue(ctx
);
6429 case MESA_SHADER_TESS_CTRL
:
6430 handle_tcs_outputs_post(ctx
);
6432 case MESA_SHADER_TESS_EVAL
:
6433 if (ctx
->options
->key
.tes
.as_es
)
6434 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6436 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6437 &ctx
->shader_info
->tes
.outinfo
);
6444 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6446 LLVMPassManagerRef passmgr
;
6447 /* Create the pass manager */
6448 passmgr
= LLVMCreateFunctionPassManagerForModule(
6451 /* This pass should eliminate all the load and store instructions */
6452 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6454 /* Add some optimization passes */
6455 LLVMAddScalarReplAggregatesPass(passmgr
);
6456 LLVMAddLICMPass(passmgr
);
6457 LLVMAddAggressiveDCEPass(passmgr
);
6458 LLVMAddCFGSimplificationPass(passmgr
);
6459 LLVMAddInstructionCombiningPass(passmgr
);
6462 LLVMInitializeFunctionPassManager(passmgr
);
6463 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6464 LLVMFinalizeFunctionPassManager(passmgr
);
6466 LLVMDisposeBuilder(ctx
->builder
);
6467 LLVMDisposePassManager(passmgr
);
6471 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6473 struct ac_vs_output_info
*outinfo
;
6475 switch (ctx
->stage
) {
6476 case MESA_SHADER_FRAGMENT
:
6477 case MESA_SHADER_COMPUTE
:
6478 case MESA_SHADER_TESS_CTRL
:
6479 case MESA_SHADER_GEOMETRY
:
6481 case MESA_SHADER_VERTEX
:
6482 if (ctx
->options
->key
.vs
.as_ls
||
6483 ctx
->options
->key
.vs
.as_es
)
6485 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6487 case MESA_SHADER_TESS_EVAL
:
6488 if (ctx
->options
->key
.vs
.as_es
)
6490 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6493 unreachable("Unhandled shader type");
6496 ac_optimize_vs_outputs(&ctx
->ac
,
6498 outinfo
->vs_output_param_offset
,
6500 &outinfo
->param_exports
);
6504 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6506 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6507 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6508 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6511 if (ctx
->is_gs_copy_shader
) {
6512 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6514 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6516 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6517 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6519 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6521 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6522 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6523 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6524 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6527 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6528 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6529 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6530 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6535 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6536 const struct nir_shader
*nir
)
6538 switch (nir
->info
.stage
) {
6539 case MESA_SHADER_TESS_CTRL
:
6540 return chip_class
>= CIK
? 128 : 64;
6541 case MESA_SHADER_GEOMETRY
:
6542 return chip_class
>= GFX9
? 128 : 64;
6543 case MESA_SHADER_COMPUTE
:
6549 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6550 nir
->info
.cs
.local_size
[1] *
6551 nir
->info
.cs
.local_size
[2];
6552 return max_workgroup_size
;
6555 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6556 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6558 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6559 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6560 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6561 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6563 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6564 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6565 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6566 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6569 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6571 for(int i
= 5; i
>= 0; --i
) {
6572 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6573 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6574 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6577 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6578 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6579 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6582 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6583 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6585 struct ac_nir_context ctx
= {};
6586 struct nir_function
*func
;
6595 ctx
.stage
= nir
->info
.stage
;
6597 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6599 nir_foreach_variable(variable
, &nir
->outputs
)
6600 handle_shader_output_decl(&ctx
, nir
, variable
);
6602 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6603 _mesa_key_pointer_equal
);
6604 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6605 _mesa_key_pointer_equal
);
6606 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6607 _mesa_key_pointer_equal
);
6609 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6611 setup_locals(&ctx
, func
);
6613 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6614 setup_shared(&ctx
, nir
);
6616 visit_cf_list(&ctx
, &func
->impl
->body
);
6617 phi_post_pass(&ctx
);
6619 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6623 ralloc_free(ctx
.defs
);
6624 ralloc_free(ctx
.phis
);
6625 ralloc_free(ctx
.vars
);
6632 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6633 struct nir_shader
*const *shaders
,
6635 struct ac_shader_variant_info
*shader_info
,
6636 const struct ac_nir_compiler_options
*options
)
6638 struct nir_to_llvm_context ctx
= {0};
6640 ctx
.options
= options
;
6641 ctx
.shader_info
= shader_info
;
6642 ctx
.context
= LLVMContextCreate();
6643 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6645 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6647 ctx
.ac
.module
= ctx
.module
;
6648 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6650 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6651 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6652 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6653 LLVMDisposeTargetData(data_layout
);
6654 LLVMDisposeMessage(data_layout_str
);
6656 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6657 ctx
.ac
.builder
= ctx
.builder
;
6659 memset(shader_info
, 0, sizeof(*shader_info
));
6661 for(int i
= 0; i
< shader_count
; ++i
)
6662 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6664 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6665 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6666 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6667 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6669 ctx
.max_workgroup_size
= 0;
6670 for (int i
= 0; i
< shader_count
; ++i
) {
6671 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6672 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6676 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6677 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6679 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6680 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6681 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6682 ctx
.abi
.load_ubo
= radv_load_ubo
;
6683 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6684 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6685 ctx
.abi
.clamp_shadow_reference
= false;
6687 if (shader_count
>= 2)
6688 ac_init_exec_full_mask(&ctx
.ac
);
6690 if (ctx
.ac
.chip_class
== GFX9
&&
6691 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6692 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6694 for(int i
= 0; i
< shader_count
; ++i
) {
6695 ctx
.stage
= shaders
[i
]->info
.stage
;
6696 ctx
.output_mask
= 0;
6697 ctx
.tess_outputs_written
= 0;
6698 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6699 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6701 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6702 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6703 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6704 ctx
.abi
.load_inputs
= load_gs_input
;
6705 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6706 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6707 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6708 ctx
.abi
.load_tess_inputs
= load_tcs_input
;
6709 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6710 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6711 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6712 ctx
.abi
.load_tess_inputs
= load_tes_input
;
6713 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6714 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6715 if (shader_info
->info
.vs
.needs_instance_id
) {
6716 if (ctx
.ac
.chip_class
== GFX9
&&
6717 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6718 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6719 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6721 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6722 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6725 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6726 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6730 emit_barrier(&ctx
.ac
, ctx
.stage
);
6732 ac_setup_rings(&ctx
);
6734 LLVMBasicBlockRef merge_block
;
6735 if (shader_count
>= 2) {
6736 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6737 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6738 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6740 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6741 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6742 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6743 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6744 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6745 thread_id
, count
, "");
6746 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6748 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6751 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6752 handle_fs_inputs(&ctx
, shaders
[i
]);
6753 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6754 handle_vs_inputs(&ctx
, shaders
[i
]);
6755 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6756 prepare_gs_input_vgprs(&ctx
);
6758 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6759 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6761 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6763 if (shader_count
>= 2) {
6764 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6765 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6768 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6769 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6770 shaders
[i
]->info
.cull_distance_array_size
> 4;
6771 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6772 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6773 shaders
[i
]->info
.gs
.vertices_out
;
6774 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6775 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6776 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6777 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6778 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6782 LLVMBuildRetVoid(ctx
.builder
);
6784 ac_llvm_finalize_module(&ctx
);
6786 if (shader_count
== 1)
6787 ac_nir_eliminate_const_vs_outputs(&ctx
);
6792 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6794 unsigned *retval
= (unsigned *)context
;
6795 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6796 char *description
= LLVMGetDiagInfoDescription(di
);
6798 if (severity
== LLVMDSError
) {
6800 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6804 LLVMDisposeMessage(description
);
6807 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6808 struct ac_shader_binary
*binary
,
6809 LLVMTargetMachineRef tm
)
6811 unsigned retval
= 0;
6813 LLVMContextRef llvm_ctx
;
6814 LLVMMemoryBufferRef out_buffer
;
6815 unsigned buffer_size
;
6816 const char *buffer_data
;
6819 /* Setup Diagnostic Handler*/
6820 llvm_ctx
= LLVMGetModuleContext(M
);
6822 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6826 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6829 /* Process Errors/Warnings */
6831 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6837 /* Extract Shader Code*/
6838 buffer_size
= LLVMGetBufferSize(out_buffer
);
6839 buffer_data
= LLVMGetBufferStart(out_buffer
);
6841 ac_elf_read(buffer_data
, buffer_size
, binary
);
6844 LLVMDisposeMemoryBuffer(out_buffer
);
6850 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6851 LLVMModuleRef llvm_module
,
6852 struct ac_shader_binary
*binary
,
6853 struct ac_shader_config
*config
,
6854 struct ac_shader_variant_info
*shader_info
,
6855 gl_shader_stage stage
,
6856 bool dump_shader
, bool supports_spill
)
6859 ac_dump_module(llvm_module
);
6861 memset(binary
, 0, sizeof(*binary
));
6862 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6864 fprintf(stderr
, "compile failed\n");
6868 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6870 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6872 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6873 LLVMDisposeModule(llvm_module
);
6874 LLVMContextDispose(ctx
);
6876 if (stage
== MESA_SHADER_FRAGMENT
) {
6877 shader_info
->num_input_vgprs
= 0;
6878 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6879 shader_info
->num_input_vgprs
+= 2;
6880 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6881 shader_info
->num_input_vgprs
+= 2;
6882 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6883 shader_info
->num_input_vgprs
+= 2;
6884 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6885 shader_info
->num_input_vgprs
+= 3;
6886 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6887 shader_info
->num_input_vgprs
+= 2;
6888 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6889 shader_info
->num_input_vgprs
+= 2;
6890 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6891 shader_info
->num_input_vgprs
+= 2;
6892 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6893 shader_info
->num_input_vgprs
+= 1;
6894 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6895 shader_info
->num_input_vgprs
+= 1;
6896 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6897 shader_info
->num_input_vgprs
+= 1;
6898 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6899 shader_info
->num_input_vgprs
+= 1;
6900 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6901 shader_info
->num_input_vgprs
+= 1;
6902 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6903 shader_info
->num_input_vgprs
+= 1;
6904 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6905 shader_info
->num_input_vgprs
+= 1;
6906 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6907 shader_info
->num_input_vgprs
+= 1;
6908 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
6909 shader_info
->num_input_vgprs
+= 1;
6911 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
6913 /* +3 for scratch wave offset and VCC */
6914 config
->num_sgprs
= MAX2(config
->num_sgprs
,
6915 shader_info
->num_input_sgprs
+ 3);
6917 /* Enable 64-bit and 16-bit denormals, because there is no performance
6920 * If denormals are enabled, all floating-point output modifiers are
6923 * Don't enable denormals for 32-bit floats, because:
6924 * - Floating-point output modifiers would be ignored by the hw.
6925 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6926 * have to stop using those.
6927 * - SI & CI would be very slow.
6929 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
6933 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
6935 switch (nir
->info
.stage
) {
6936 case MESA_SHADER_COMPUTE
:
6937 for (int i
= 0; i
< 3; ++i
)
6938 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
6940 case MESA_SHADER_FRAGMENT
:
6941 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
6943 case MESA_SHADER_GEOMETRY
:
6944 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
6945 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
6946 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
6947 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
6949 case MESA_SHADER_TESS_EVAL
:
6950 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
6951 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
6952 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
6953 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
6954 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
6956 case MESA_SHADER_TESS_CTRL
:
6957 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
6959 case MESA_SHADER_VERTEX
:
6960 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
6961 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
6962 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6963 if (options
->key
.vs
.as_ls
)
6964 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
6971 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
6972 struct ac_shader_binary
*binary
,
6973 struct ac_shader_config
*config
,
6974 struct ac_shader_variant_info
*shader_info
,
6975 struct nir_shader
*const *nir
,
6977 const struct ac_nir_compiler_options
*options
,
6981 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
6984 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
6985 for (int i
= 0; i
< nir_count
; ++i
)
6986 ac_fill_shader_info(shader_info
, nir
[i
], options
);
6990 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
6992 LLVMValueRef args
[9];
6993 args
[0] = ctx
->gsvs_ring
;
6994 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
6995 args
[3] = ctx
->ac
.i32_0
;
6996 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
6997 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
6998 args
[6] = ctx
->ac
.i32_1
; /* GLC */
6999 args
[7] = ctx
->ac
.i32_1
; /* SLC */
7000 args
[8] = ctx
->ac
.i32_0
; /* TFE */
7004 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
7008 if (!(ctx
->output_mask
& (1ull << i
)))
7011 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7012 /* unpack clip and cull from a single set of slots */
7013 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7018 for (unsigned j
= 0; j
< length
; j
++) {
7020 args
[2] = LLVMConstInt(ctx
->ac
.i32
,
7022 ctx
->gs_max_out_vertices
* 16 * 4, false);
7024 value
= ac_build_intrinsic(&ctx
->ac
,
7025 "llvm.SI.buffer.load.dword.i32.i32",
7026 ctx
->ac
.i32
, args
, 9,
7027 AC_FUNC_ATTR_READONLY
|
7028 AC_FUNC_ATTR_LEGACY
);
7030 LLVMBuildStore(ctx
->builder
,
7031 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7035 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7038 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7039 struct nir_shader
*geom_shader
,
7040 struct ac_shader_binary
*binary
,
7041 struct ac_shader_config
*config
,
7042 struct ac_shader_variant_info
*shader_info
,
7043 const struct ac_nir_compiler_options
*options
,
7046 struct nir_to_llvm_context ctx
= {0};
7047 ctx
.context
= LLVMContextCreate();
7048 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7049 ctx
.options
= options
;
7050 ctx
.shader_info
= shader_info
;
7052 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7054 ctx
.ac
.module
= ctx
.module
;
7056 ctx
.is_gs_copy_shader
= true;
7057 LLVMSetTarget(ctx
.module
, "amdgcn--");
7059 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
7060 ctx
.ac
.builder
= ctx
.builder
;
7061 ctx
.stage
= MESA_SHADER_VERTEX
;
7063 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7065 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7066 ac_setup_rings(&ctx
);
7068 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7069 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7071 struct ac_nir_context nir_ctx
= {};
7072 nir_ctx
.ac
= ctx
.ac
;
7073 nir_ctx
.abi
= &ctx
.abi
;
7075 nir_ctx
.nctx
= &ctx
;
7078 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7079 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7080 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7083 ac_gs_copy_shader_emit(&ctx
);
7087 LLVMBuildRetVoid(ctx
.builder
);
7089 ac_llvm_finalize_module(&ctx
);
7091 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
7093 dump_shader
, options
->supports_spill
);