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ac/surface: sanity-check that we got a TC-compatible HTILE if requested
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "amdgpu_id.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void addrlib_family_rev_id(enum radeon_family family,
53 unsigned *addrlib_family,
54 unsigned *addrlib_revid)
55 {
56 switch (family) {
57 case CHIP_TAHITI:
58 *addrlib_family = FAMILY_SI;
59 *addrlib_revid = SI_TAHITI_P_A0;
60 break;
61 case CHIP_PITCAIRN:
62 *addrlib_family = FAMILY_SI;
63 *addrlib_revid = SI_PITCAIRN_PM_A0;
64 break;
65 case CHIP_VERDE:
66 *addrlib_family = FAMILY_SI;
67 *addrlib_revid = SI_CAPEVERDE_M_A0;
68 break;
69 case CHIP_OLAND:
70 *addrlib_family = FAMILY_SI;
71 *addrlib_revid = SI_OLAND_M_A0;
72 break;
73 case CHIP_HAINAN:
74 *addrlib_family = FAMILY_SI;
75 *addrlib_revid = SI_HAINAN_V_A0;
76 break;
77 case CHIP_BONAIRE:
78 *addrlib_family = FAMILY_CI;
79 *addrlib_revid = CI_BONAIRE_M_A0;
80 break;
81 case CHIP_KAVERI:
82 *addrlib_family = FAMILY_KV;
83 *addrlib_revid = KV_SPECTRE_A0;
84 break;
85 case CHIP_KABINI:
86 *addrlib_family = FAMILY_KV;
87 *addrlib_revid = KB_KALINDI_A0;
88 break;
89 case CHIP_HAWAII:
90 *addrlib_family = FAMILY_CI;
91 *addrlib_revid = CI_HAWAII_P_A0;
92 break;
93 case CHIP_MULLINS:
94 *addrlib_family = FAMILY_KV;
95 *addrlib_revid = ML_GODAVARI_A0;
96 break;
97 case CHIP_TONGA:
98 *addrlib_family = FAMILY_VI;
99 *addrlib_revid = VI_TONGA_P_A0;
100 break;
101 case CHIP_ICELAND:
102 *addrlib_family = FAMILY_VI;
103 *addrlib_revid = VI_ICELAND_M_A0;
104 break;
105 case CHIP_CARRIZO:
106 *addrlib_family = FAMILY_CZ;
107 *addrlib_revid = CARRIZO_A0;
108 break;
109 case CHIP_STONEY:
110 *addrlib_family = FAMILY_CZ;
111 *addrlib_revid = STONEY_A0;
112 break;
113 case CHIP_FIJI:
114 *addrlib_family = FAMILY_VI;
115 *addrlib_revid = VI_FIJI_P_A0;
116 break;
117 case CHIP_POLARIS10:
118 *addrlib_family = FAMILY_VI;
119 *addrlib_revid = VI_POLARIS10_P_A0;
120 break;
121 case CHIP_POLARIS11:
122 *addrlib_family = FAMILY_VI;
123 *addrlib_revid = VI_POLARIS11_M_A0;
124 break;
125 case CHIP_POLARIS12:
126 *addrlib_family = FAMILY_VI;
127 *addrlib_revid = VI_POLARIS12_V_A0;
128 break;
129 case CHIP_VEGA10:
130 *addrlib_family = FAMILY_AI;
131 *addrlib_revid = AI_VEGA10_P_A0;
132 break;
133 case CHIP_RAVEN:
134 *addrlib_family = FAMILY_RV;
135 *addrlib_revid = RAVEN_A0;
136 break;
137 default:
138 fprintf(stderr, "amdgpu: Unknown family.\n");
139 }
140 }
141
142 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
143 {
144 return malloc(pInput->sizeInBytes);
145 }
146
147 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
148 {
149 free(pInput->pVirtAddr);
150 return ADDR_OK;
151 }
152
153 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
154 const struct amdgpu_gpu_info *amdinfo,
155 uint64_t *max_alignment)
156 {
157 ADDR_CREATE_INPUT addrCreateInput = {0};
158 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
159 ADDR_REGISTER_VALUE regValue = {0};
160 ADDR_CREATE_FLAGS createFlags = {{0}};
161 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
162 ADDR_E_RETURNCODE addrRet;
163
164 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
165 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
166
167 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
168 createFlags.value = 0;
169
170 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
171 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
172 return NULL;
173
174 if (addrCreateInput.chipFamily >= FAMILY_AI) {
175 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
176 regValue.blockVarSizeLog2 = 0;
177 } else {
178 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
179 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
180
181 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
182 regValue.pTileConfig = amdinfo->gb_tile_mode;
183 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
184 if (addrCreateInput.chipFamily == FAMILY_SI) {
185 regValue.pMacroTileConfig = NULL;
186 regValue.noOfMacroEntries = 0;
187 } else {
188 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
189 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
190 }
191
192 createFlags.useTileIndex = 1;
193 createFlags.useHtileSliceAlign = 1;
194
195 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
196 }
197
198 addrCreateInput.callbacks.allocSysMem = allocSysMem;
199 addrCreateInput.callbacks.freeSysMem = freeSysMem;
200 addrCreateInput.callbacks.debugPrint = 0;
201 addrCreateInput.createFlags = createFlags;
202 addrCreateInput.regValue = regValue;
203
204 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
205 if (addrRet != ADDR_OK)
206 return NULL;
207
208 if (max_alignment) {
209 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
210 if (addrRet == ADDR_OK){
211 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
212 }
213 }
214 return addrCreateOutput.hLib;
215 }
216
217 static int surf_config_sanity(const struct ac_surf_config *config)
218 {
219 /* all dimension must be at least 1 ! */
220 if (!config->info.width || !config->info.height || !config->info.depth ||
221 !config->info.array_size || !config->info.levels)
222 return -EINVAL;
223
224 switch (config->info.samples) {
225 case 0:
226 case 1:
227 case 2:
228 case 4:
229 case 8:
230 break;
231 default:
232 return -EINVAL;
233 }
234
235 if (config->is_3d && config->info.array_size > 1)
236 return -EINVAL;
237 if (config->is_cube && config->info.depth > 1)
238 return -EINVAL;
239
240 return 0;
241 }
242
243 static int gfx6_compute_level(ADDR_HANDLE addrlib,
244 const struct ac_surf_config *config,
245 struct radeon_surf *surf, bool is_stencil,
246 unsigned level, bool compressed,
247 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
248 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
249 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
250 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
251 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
252 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
253 {
254 struct legacy_surf_level *surf_level;
255 ADDR_E_RETURNCODE ret;
256
257 AddrSurfInfoIn->mipLevel = level;
258 AddrSurfInfoIn->width = u_minify(config->info.width, level);
259 AddrSurfInfoIn->height = u_minify(config->info.height, level);
260
261 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
262 * because GFX9 needs linear alignment of 256 bytes.
263 */
264 if (config->info.levels == 1 &&
265 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
266 AddrSurfInfoIn->bpp) {
267 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
268
269 assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
270 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
271 }
272
273 if (config->is_3d)
274 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
275 else if (config->is_cube)
276 AddrSurfInfoIn->numSlices = 6;
277 else
278 AddrSurfInfoIn->numSlices = config->info.array_size;
279
280 if (level > 0) {
281 /* Set the base level pitch. This is needed for calculation
282 * of non-zero levels. */
283 if (is_stencil)
284 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
285 else
286 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
287
288 /* Convert blocks to pixels for compressed formats. */
289 if (compressed)
290 AddrSurfInfoIn->basePitch *= surf->blk_w;
291 }
292
293 ret = AddrComputeSurfaceInfo(addrlib,
294 AddrSurfInfoIn,
295 AddrSurfInfoOut);
296 if (ret != ADDR_OK) {
297 return ret;
298 }
299
300 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
301 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
302 surf_level->slice_size = AddrSurfInfoOut->sliceSize;
303 surf_level->nblk_x = AddrSurfInfoOut->pitch;
304 surf_level->nblk_y = AddrSurfInfoOut->height;
305
306 switch (AddrSurfInfoOut->tileMode) {
307 case ADDR_TM_LINEAR_ALIGNED:
308 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
309 break;
310 case ADDR_TM_1D_TILED_THIN1:
311 surf_level->mode = RADEON_SURF_MODE_1D;
312 break;
313 case ADDR_TM_2D_TILED_THIN1:
314 surf_level->mode = RADEON_SURF_MODE_2D;
315 break;
316 default:
317 assert(0);
318 }
319
320 if (is_stencil)
321 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
322 else
323 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
324
325 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
326
327 /* Clear DCC fields at the beginning. */
328 surf_level->dcc_offset = 0;
329
330 /* The previous level's flag tells us if we can use DCC for this level. */
331 if (AddrSurfInfoIn->flags.dccCompatible &&
332 (level == 0 || AddrDccOut->subLvlCompressible)) {
333 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
334 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
335 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
336 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
337 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
338
339 ret = AddrComputeDccInfo(addrlib,
340 AddrDccIn,
341 AddrDccOut);
342
343 if (ret == ADDR_OK) {
344 surf_level->dcc_offset = surf->dcc_size;
345 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
346 surf->num_dcc_levels = level + 1;
347 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
348 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
349 }
350 }
351
352 /* TC-compatible HTILE. */
353 if (!is_stencil &&
354 AddrSurfInfoIn->flags.depth &&
355 surf_level->mode == RADEON_SURF_MODE_2D &&
356 level == 0) {
357 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
358 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
359 AddrHtileIn->height = AddrSurfInfoOut->height;
360 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
361 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
362 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
363 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
364 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
365 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
366
367 ret = AddrComputeHtileInfo(addrlib,
368 AddrHtileIn,
369 AddrHtileOut);
370
371 if (ret == ADDR_OK) {
372 surf->htile_size = AddrHtileOut->htileBytes;
373 surf->htile_slice_size = AddrHtileOut->sliceSize;
374 surf->htile_alignment = AddrHtileOut->baseAlign;
375 }
376 }
377
378 return 0;
379 }
380
381 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
382 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
383
384 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
385 const struct radeon_info *info)
386 {
387 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
388
389 if (info->chip_class >= CIK)
390 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
391 else
392 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
393 }
394
395 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
396 {
397 unsigned index, tileb;
398
399 tileb = 8 * 8 * surf->bpe;
400 tileb = MIN2(surf->u.legacy.tile_split, tileb);
401
402 for (index = 0; tileb > 64; index++)
403 tileb >>= 1;
404
405 assert(index < 16);
406 return index;
407 }
408
409 /**
410 * This must be called after the first level is computed.
411 *
412 * Copy surface-global settings like pipe/bank config from level 0 surface
413 * computation, and compute tile swizzle.
414 */
415 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
416 const struct radeon_info *info,
417 const struct ac_surf_config *config,
418 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
419 struct radeon_surf *surf)
420 {
421 surf->surf_alignment = csio->baseAlign;
422 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
423 gfx6_set_micro_tile_mode(surf, info);
424
425 /* For 2D modes only. */
426 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
427 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
428 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
429 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
430 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
431 surf->u.legacy.num_banks = csio->pTileInfo->banks;
432 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
433 } else {
434 surf->u.legacy.macro_tile_index = 0;
435 }
436
437 /* Compute tile swizzle. */
438 /* TODO: fix tile swizzle with mipmapping for SI */
439 if ((info->chip_class >= CIK || config->info.levels == 1) &&
440 config->info.surf_index &&
441 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
442 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
443 (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
444 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
445 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
446
447 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
448 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
449
450 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
451 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
452 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
453 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
454 AddrBaseSwizzleIn.tileMode = csio->tileMode;
455
456 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
457 &AddrBaseSwizzleOut);
458 if (r != ADDR_OK)
459 return r;
460
461 assert(AddrBaseSwizzleOut.tileSwizzle <=
462 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
463 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
464 }
465 return 0;
466 }
467
468 /**
469 * Fill in the tiling information in \p surf based on the given surface config.
470 *
471 * The following fields of \p surf must be initialized by the caller:
472 * blk_w, blk_h, bpe, flags.
473 */
474 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
475 const struct radeon_info *info,
476 const struct ac_surf_config *config,
477 enum radeon_surf_mode mode,
478 struct radeon_surf *surf)
479 {
480 unsigned level;
481 bool compressed;
482 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
483 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
484 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
485 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
486 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
487 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
488 ADDR_TILEINFO AddrTileInfoIn = {0};
489 ADDR_TILEINFO AddrTileInfoOut = {0};
490 int r;
491
492 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
493 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
494 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
495 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
496 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
497 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
498 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
499
500 compressed = surf->blk_w == 4 && surf->blk_h == 4;
501
502 /* MSAA and FMASK require 2D tiling. */
503 if (config->info.samples > 1 ||
504 (surf->flags & RADEON_SURF_FMASK))
505 mode = RADEON_SURF_MODE_2D;
506
507 /* DB doesn't support linear layouts. */
508 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
509 mode < RADEON_SURF_MODE_1D)
510 mode = RADEON_SURF_MODE_1D;
511
512 /* Set the requested tiling mode. */
513 switch (mode) {
514 case RADEON_SURF_MODE_LINEAR_ALIGNED:
515 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
516 break;
517 case RADEON_SURF_MODE_1D:
518 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
519 break;
520 case RADEON_SURF_MODE_2D:
521 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
522 break;
523 default:
524 assert(0);
525 }
526
527 /* The format must be set correctly for the allocation of compressed
528 * textures to work. In other cases, setting the bpp is sufficient.
529 */
530 if (compressed) {
531 switch (surf->bpe) {
532 case 8:
533 AddrSurfInfoIn.format = ADDR_FMT_BC1;
534 break;
535 case 16:
536 AddrSurfInfoIn.format = ADDR_FMT_BC3;
537 break;
538 default:
539 assert(0);
540 }
541 }
542 else {
543 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
544 }
545
546 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
547 config->info.samples ? config->info.samples : 1;
548 AddrSurfInfoIn.tileIndex = -1;
549
550 /* Set the micro tile type. */
551 if (surf->flags & RADEON_SURF_SCANOUT)
552 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
553 else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
554 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
555 else
556 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
557
558 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
559 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
560 AddrSurfInfoIn.flags.cube = config->is_cube;
561 AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
562 AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
563 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
564 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
565
566 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
567 * requested, because TC-compatible HTILE requires 2D tiling.
568 */
569 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
570 !AddrSurfInfoIn.flags.fmask &&
571 config->info.samples <= 1 &&
572 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
573
574 /* DCC notes:
575 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
576 * with samples >= 4.
577 * - Mipmapped array textures have low performance (discovered by a closed
578 * driver team).
579 */
580 AddrSurfInfoIn.flags.dccCompatible =
581 info->chip_class >= VI &&
582 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
583 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
584 !compressed && AddrDccIn.numSamples <= 1 &&
585 ((config->info.array_size == 1 && config->info.depth == 1) ||
586 config->info.levels == 1);
587
588 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
589 AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
590
591 /* noStencil = 0 can result in a depth part that is incompatible with
592 * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
593 * this case, we may end up setting stencil_adjusted).
594 *
595 * TODO: update addrlib to a newer version, remove this, and
596 * use flags.matchStencilTileCfg = 1 as an alternative fix.
597 */
598 if (config->info.levels > 1)
599 AddrSurfInfoIn.flags.noStencil = 1;
600
601 /* Set preferred macrotile parameters. This is usually required
602 * for shared resources. This is for 2D tiling only. */
603 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
604 surf->u.legacy.bankw && surf->u.legacy.bankh &&
605 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
606 assert(!(surf->flags & RADEON_SURF_FMASK));
607
608 /* If any of these parameters are incorrect, the calculation
609 * will fail. */
610 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
611 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
612 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
613 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
614 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
615 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
616 AddrSurfInfoIn.flags.opt4Space = 0;
617 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
618
619 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
620 * the tile index, because we are expected to know it if
621 * we know the other parameters.
622 *
623 * This is something that can easily be fixed in Addrlib.
624 * For now, just figure it out here.
625 * Note that only 2D_TILE_THIN1 is handled here.
626 */
627 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
628 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
629
630 if (info->chip_class == SI) {
631 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
632 if (surf->bpe == 2)
633 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
634 else
635 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
636 } else {
637 if (surf->bpe == 1)
638 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
639 else if (surf->bpe == 2)
640 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
641 else if (surf->bpe == 4)
642 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
643 else
644 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
645 }
646 } else {
647 /* CIK - VI */
648 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
649 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
650 else
651 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
652
653 /* Addrlib doesn't set this if tileIndex is forced like above. */
654 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
655 }
656 }
657
658 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
659 surf->num_dcc_levels = 0;
660 surf->surf_size = 0;
661 surf->dcc_size = 0;
662 surf->dcc_alignment = 1;
663 surf->htile_size = 0;
664 surf->htile_slice_size = 0;
665 surf->htile_alignment = 1;
666
667 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
668 !(surf->flags & RADEON_SURF_ZBUFFER);
669
670 /* Calculate texture layout information. */
671 if (!only_stencil) {
672 for (level = 0; level < config->info.levels; level++) {
673 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
674 &AddrSurfInfoIn, &AddrSurfInfoOut,
675 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
676 if (r)
677 return r;
678
679 if (level > 0)
680 continue;
681
682 /* Check that we actually got a TC-compatible HTILE if
683 * we requested it (only for level 0, since we're not
684 * supporting HTILE on higher mip levels anyway). */
685 assert(AddrSurfInfoOut.tcCompatible ||
686 !AddrSurfInfoIn.flags.tcCompatible);
687
688 r = gfx6_surface_settings(addrlib, info, config,
689 &AddrSurfInfoOut, surf);
690 if (r)
691 return r;
692 }
693 }
694
695 /* Calculate texture layout information for stencil. */
696 if (surf->flags & RADEON_SURF_SBUFFER) {
697 AddrSurfInfoIn.bpp = 8;
698 AddrSurfInfoIn.flags.depth = 0;
699 AddrSurfInfoIn.flags.stencil = 1;
700 AddrSurfInfoIn.flags.tcCompatible = 0;
701 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
702 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
703
704 for (level = 0; level < config->info.levels; level++) {
705 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
706 &AddrSurfInfoIn, &AddrSurfInfoOut,
707 &AddrDccIn, &AddrDccOut,
708 NULL, NULL);
709 if (r)
710 return r;
711
712 /* DB uses the depth pitch for both stencil and depth. */
713 if (!only_stencil) {
714 if (surf->u.legacy.stencil_level[level].nblk_x !=
715 surf->u.legacy.level[level].nblk_x)
716 surf->u.legacy.stencil_adjusted = true;
717 } else {
718 surf->u.legacy.level[level].nblk_x =
719 surf->u.legacy.stencil_level[level].nblk_x;
720 }
721
722 if (level == 0) {
723 if (only_stencil) {
724 r = gfx6_surface_settings(addrlib, info, config,
725 &AddrSurfInfoOut, surf);
726 if (r)
727 return r;
728 }
729
730 /* For 2D modes only. */
731 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
732 surf->u.legacy.stencil_tile_split =
733 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
734 }
735 }
736 }
737 }
738
739 /* Recalculate the whole DCC miptree size including disabled levels.
740 * This is what addrlib does, but calling addrlib would be a lot more
741 * complicated.
742 */
743 if (surf->dcc_size && config->info.levels > 1) {
744 /* The smallest miplevels that are never compressed by DCC
745 * still read the DCC buffer via TC if the base level uses DCC,
746 * and for some reason the DCC buffer needs to be larger if
747 * the miptree uses non-zero tile_swizzle. Otherwise there are
748 * VM faults.
749 *
750 * "dcc_alignment * 4" was determined by trial and error.
751 */
752 surf->dcc_size = align64(surf->surf_size >> 8,
753 surf->dcc_alignment * 4);
754 }
755
756 /* Make sure HTILE covers the whole miptree, because the shader reads
757 * TC-compatible HTILE even for levels where it's disabled by DB.
758 */
759 if (surf->htile_size && config->info.levels > 1)
760 surf->htile_size *= 2;
761
762 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
763 return 0;
764 }
765
766 /* This is only called when expecting a tiled layout. */
767 static int
768 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
769 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
770 bool is_fmask, AddrSwizzleMode *swizzle_mode)
771 {
772 ADDR_E_RETURNCODE ret;
773 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
774 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
775
776 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
777 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
778
779 sin.flags = in->flags;
780 sin.resourceType = in->resourceType;
781 sin.format = in->format;
782 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
783 /* TODO: We could allow some of these: */
784 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
785 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
786 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
787 sin.bpp = in->bpp;
788 sin.width = in->width;
789 sin.height = in->height;
790 sin.numSlices = in->numSlices;
791 sin.numMipLevels = in->numMipLevels;
792 sin.numSamples = in->numSamples;
793 sin.numFrags = in->numFrags;
794
795 if (is_fmask) {
796 sin.flags.color = 0;
797 sin.flags.fmask = 1;
798 }
799
800 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
801 if (ret != ADDR_OK)
802 return ret;
803
804 *swizzle_mode = sout.swizzleMode;
805 return 0;
806 }
807
808 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
809 struct radeon_surf *surf, bool compressed,
810 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
811 {
812 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
813 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
814 ADDR_E_RETURNCODE ret;
815
816 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
817 out.pMipInfo = mip_info;
818
819 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
820 if (ret != ADDR_OK)
821 return ret;
822
823 if (in->flags.stencil) {
824 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
825 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
826 out.mipChainPitch - 1;
827 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
828 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
829 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
830 return 0;
831 }
832
833 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
834 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
835 out.mipChainPitch - 1;
836
837 /* CMASK fast clear uses these even if FMASK isn't allocated.
838 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
839 */
840 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
841 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
842
843 surf->u.gfx9.surf_slice_size = out.sliceSize;
844 surf->u.gfx9.surf_pitch = out.pitch;
845 surf->u.gfx9.surf_height = out.height;
846 surf->surf_size = out.surfSize;
847 surf->surf_alignment = out.baseAlign;
848
849 if (in->swizzleMode == ADDR_SW_LINEAR) {
850 for (unsigned i = 0; i < in->numMipLevels; i++)
851 surf->u.gfx9.offset[i] = mip_info[i].offset;
852 }
853
854 if (in->flags.depth) {
855 assert(in->swizzleMode != ADDR_SW_LINEAR);
856
857 /* HTILE */
858 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
859 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
860
861 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
862 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
863
864 hin.hTileFlags.pipeAligned = 1;
865 hin.hTileFlags.rbAligned = 1;
866 hin.depthFlags = in->flags;
867 hin.swizzleMode = in->swizzleMode;
868 hin.unalignedWidth = in->width;
869 hin.unalignedHeight = in->height;
870 hin.numSlices = in->numSlices;
871 hin.numMipLevels = in->numMipLevels;
872
873 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
874 if (ret != ADDR_OK)
875 return ret;
876
877 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
878 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
879 surf->htile_size = hout.htileBytes;
880 surf->htile_slice_size = hout.sliceSize;
881 surf->htile_alignment = hout.baseAlign;
882 } else {
883 /* DCC */
884 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
885 !(surf->flags & RADEON_SURF_SCANOUT) &&
886 !compressed &&
887 in->swizzleMode != ADDR_SW_LINEAR &&
888 /* TODO: We could support DCC with MSAA. */
889 in->numSamples == 1) {
890 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
891 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
892
893 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
894 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
895
896 din.dccKeyFlags.pipeAligned = 1;
897 din.dccKeyFlags.rbAligned = 1;
898 din.colorFlags = in->flags;
899 din.resourceType = in->resourceType;
900 din.swizzleMode = in->swizzleMode;
901 din.bpp = in->bpp;
902 din.unalignedWidth = in->width;
903 din.unalignedHeight = in->height;
904 din.numSlices = in->numSlices;
905 din.numFrags = in->numFrags;
906 din.numMipLevels = in->numMipLevels;
907 din.dataSurfaceSize = out.surfSize;
908
909 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
910 if (ret != ADDR_OK)
911 return ret;
912
913 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
914 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
915 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
916 surf->dcc_size = dout.dccRamSize;
917 surf->dcc_alignment = dout.dccRamBaseAlign;
918 surf->num_dcc_levels = in->numMipLevels;
919
920 /* Disable DCC for the smallest levels. It seems to be
921 * required for DCC readability between CB and shaders
922 * when TC L2 isn't flushed. This was guessed.
923 *
924 * Alternative solutions that also work but are worse:
925 * - Disable DCC.
926 * - Flush TC L2 after rendering.
927 */
928 for (unsigned i = 1; i < in->numMipLevels; i++) {
929 if (mip_info[i].pitch *
930 mip_info[i].height * surf->bpe < 1024) {
931 surf->num_dcc_levels = i;
932 break;
933 }
934 }
935 }
936
937 /* FMASK */
938 if (in->numSamples > 1) {
939 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
940 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
941
942 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
943 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
944
945 ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
946 if (ret != ADDR_OK)
947 return ret;
948
949 fin.unalignedWidth = in->width;
950 fin.unalignedHeight = in->height;
951 fin.numSlices = in->numSlices;
952 fin.numSamples = in->numSamples;
953 fin.numFrags = in->numFrags;
954
955 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
956 if (ret != ADDR_OK)
957 return ret;
958
959 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
960 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
961 surf->u.gfx9.fmask_size = fout.fmaskBytes;
962 surf->u.gfx9.fmask_alignment = fout.baseAlign;
963 }
964
965 /* CMASK */
966 if (in->swizzleMode != ADDR_SW_LINEAR) {
967 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
968 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
969
970 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
971 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
972
973 cin.cMaskFlags.pipeAligned = 1;
974 cin.cMaskFlags.rbAligned = 1;
975 cin.colorFlags = in->flags;
976 cin.resourceType = in->resourceType;
977 cin.unalignedWidth = in->width;
978 cin.unalignedHeight = in->height;
979 cin.numSlices = in->numSlices;
980
981 if (in->numSamples > 1)
982 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
983 else
984 cin.swizzleMode = in->swizzleMode;
985
986 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
987 if (ret != ADDR_OK)
988 return ret;
989
990 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
991 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
992 surf->u.gfx9.cmask_size = cout.cmaskBytes;
993 surf->u.gfx9.cmask_alignment = cout.baseAlign;
994 }
995 }
996
997 return 0;
998 }
999
1000 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1001 const struct ac_surf_config *config,
1002 enum radeon_surf_mode mode,
1003 struct radeon_surf *surf)
1004 {
1005 bool compressed;
1006 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1007 int r;
1008
1009 assert(!(surf->flags & RADEON_SURF_FMASK));
1010
1011 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1012
1013 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1014
1015 /* The format must be set correctly for the allocation of compressed
1016 * textures to work. In other cases, setting the bpp is sufficient. */
1017 if (compressed) {
1018 switch (surf->bpe) {
1019 case 8:
1020 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1021 break;
1022 case 16:
1023 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1024 break;
1025 default:
1026 assert(0);
1027 }
1028 } else {
1029 AddrSurfInfoIn.bpp = surf->bpe * 8;
1030 }
1031
1032 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1033 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1034 AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
1035 /* flags.texture currently refers to TC-compatible HTILE */
1036 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1037 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1038 AddrSurfInfoIn.flags.opt4space = 1;
1039
1040 AddrSurfInfoIn.numMipLevels = config->info.levels;
1041 AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1042 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1043
1044 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1045 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1046 * must sample 1D textures as 2D. */
1047 if (config->is_3d)
1048 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1049 else
1050 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1051
1052 AddrSurfInfoIn.width = config->info.width;
1053 AddrSurfInfoIn.height = config->info.height;
1054
1055 if (config->is_3d)
1056 AddrSurfInfoIn.numSlices = config->info.depth;
1057 else if (config->is_cube)
1058 AddrSurfInfoIn.numSlices = 6;
1059 else
1060 AddrSurfInfoIn.numSlices = config->info.array_size;
1061
1062 switch (mode) {
1063 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1064 assert(config->info.samples <= 1);
1065 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1066 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1067 break;
1068
1069 case RADEON_SURF_MODE_1D:
1070 case RADEON_SURF_MODE_2D:
1071 if (surf->flags & RADEON_SURF_IMPORTED) {
1072 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1073 break;
1074 }
1075
1076 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
1077 &AddrSurfInfoIn.swizzleMode);
1078 if (r)
1079 return r;
1080 break;
1081
1082 default:
1083 assert(0);
1084 }
1085
1086 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1087 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1088
1089 surf->num_dcc_levels = 0;
1090 surf->surf_size = 0;
1091 surf->dcc_size = 0;
1092 surf->htile_size = 0;
1093 surf->htile_slice_size = 0;
1094 surf->u.gfx9.surf_offset = 0;
1095 surf->u.gfx9.stencil_offset = 0;
1096 surf->u.gfx9.fmask_size = 0;
1097 surf->u.gfx9.cmask_size = 0;
1098
1099 /* Calculate texture layout information. */
1100 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1101 if (r)
1102 return r;
1103
1104 /* Calculate texture layout information for stencil. */
1105 if (surf->flags & RADEON_SURF_SBUFFER) {
1106 AddrSurfInfoIn.bpp = 8;
1107 AddrSurfInfoIn.flags.depth = 0;
1108 AddrSurfInfoIn.flags.stencil = 1;
1109
1110 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1111 if (r)
1112 return r;
1113 }
1114
1115 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1116
1117 switch (surf->u.gfx9.surf.swizzle_mode) {
1118 /* S = standard. */
1119 case ADDR_SW_256B_S:
1120 case ADDR_SW_4KB_S:
1121 case ADDR_SW_64KB_S:
1122 case ADDR_SW_VAR_S:
1123 case ADDR_SW_64KB_S_T:
1124 case ADDR_SW_4KB_S_X:
1125 case ADDR_SW_64KB_S_X:
1126 case ADDR_SW_VAR_S_X:
1127 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1128 break;
1129
1130 /* D = display. */
1131 case ADDR_SW_LINEAR:
1132 case ADDR_SW_256B_D:
1133 case ADDR_SW_4KB_D:
1134 case ADDR_SW_64KB_D:
1135 case ADDR_SW_VAR_D:
1136 case ADDR_SW_64KB_D_T:
1137 case ADDR_SW_4KB_D_X:
1138 case ADDR_SW_64KB_D_X:
1139 case ADDR_SW_VAR_D_X:
1140 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1141 break;
1142
1143 /* R = rotated. */
1144 case ADDR_SW_256B_R:
1145 case ADDR_SW_4KB_R:
1146 case ADDR_SW_64KB_R:
1147 case ADDR_SW_VAR_R:
1148 case ADDR_SW_64KB_R_T:
1149 case ADDR_SW_4KB_R_X:
1150 case ADDR_SW_64KB_R_X:
1151 case ADDR_SW_VAR_R_X:
1152 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1153 break;
1154
1155 /* Z = depth. */
1156 case ADDR_SW_4KB_Z:
1157 case ADDR_SW_64KB_Z:
1158 case ADDR_SW_VAR_Z:
1159 case ADDR_SW_64KB_Z_T:
1160 case ADDR_SW_4KB_Z_X:
1161 case ADDR_SW_64KB_Z_X:
1162 case ADDR_SW_VAR_Z_X:
1163 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1164 break;
1165
1166 default:
1167 assert(0);
1168 }
1169
1170 return 0;
1171 }
1172
1173 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1174 const struct ac_surf_config *config,
1175 enum radeon_surf_mode mode,
1176 struct radeon_surf *surf)
1177 {
1178 int r;
1179
1180 r = surf_config_sanity(config);
1181 if (r)
1182 return r;
1183
1184 if (info->chip_class >= GFX9)
1185 return gfx9_compute_surface(addrlib, config, mode, surf);
1186 else
1187 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1188 }