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ac/surface: add a wrapper structure to hold ADDR_HANDLE
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35 #include "sid.h"
36
37 #include <errno.h>
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <amdgpu.h>
41 #include "drm-uapi/amdgpu_drm.h"
42
43 #include "addrlib/inc/addrinterface.h"
44
45 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
46 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
47 #endif
48
49 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
50 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
51 #endif
52
53 struct ac_addrlib {
54 ADDR_HANDLE handle;
55 };
56
57 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
58 {
59 return malloc(pInput->sizeInBytes);
60 }
61
62 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
63 {
64 free(pInput->pVirtAddr);
65 return ADDR_OK;
66 }
67
68 struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info,
69 const struct amdgpu_gpu_info *amdinfo,
70 uint64_t *max_alignment)
71 {
72 ADDR_CREATE_INPUT addrCreateInput = {0};
73 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
74 ADDR_REGISTER_VALUE regValue = {0};
75 ADDR_CREATE_FLAGS createFlags = {{0}};
76 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
77 ADDR_E_RETURNCODE addrRet;
78
79 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
80 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
81
82 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
83 createFlags.value = 0;
84
85 addrCreateInput.chipFamily = info->family_id;
86 addrCreateInput.chipRevision = info->chip_external_rev;
87
88 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
89 return NULL;
90
91 if (addrCreateInput.chipFamily >= FAMILY_AI) {
92 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
93 } else {
94 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
95 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
96
97 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
98 regValue.pTileConfig = amdinfo->gb_tile_mode;
99 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
100 if (addrCreateInput.chipFamily == FAMILY_SI) {
101 regValue.pMacroTileConfig = NULL;
102 regValue.noOfMacroEntries = 0;
103 } else {
104 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
105 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
106 }
107
108 createFlags.useTileIndex = 1;
109 createFlags.useHtileSliceAlign = 1;
110
111 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
112 }
113
114 addrCreateInput.callbacks.allocSysMem = allocSysMem;
115 addrCreateInput.callbacks.freeSysMem = freeSysMem;
116 addrCreateInput.callbacks.debugPrint = 0;
117 addrCreateInput.createFlags = createFlags;
118 addrCreateInput.regValue = regValue;
119
120 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
121 if (addrRet != ADDR_OK)
122 return NULL;
123
124 if (max_alignment) {
125 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
126 if (addrRet == ADDR_OK){
127 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
128 }
129 }
130
131 struct ac_addrlib *addrlib = calloc(1, sizeof(struct ac_addrlib));
132 if (!addrlib) {
133 AddrDestroy(addrCreateOutput.hLib);
134 return NULL;
135 }
136
137 addrlib->handle = addrCreateOutput.hLib;
138 return addrlib;
139 }
140
141 void ac_addrlib_destroy(struct ac_addrlib *addrlib)
142 {
143 AddrDestroy(addrlib->handle);
144 free(addrlib);
145 }
146
147 static int surf_config_sanity(const struct ac_surf_config *config,
148 unsigned flags)
149 {
150 /* FMASK is allocated together with the color surface and can't be
151 * allocated separately.
152 */
153 assert(!(flags & RADEON_SURF_FMASK));
154 if (flags & RADEON_SURF_FMASK)
155 return -EINVAL;
156
157 /* all dimension must be at least 1 ! */
158 if (!config->info.width || !config->info.height || !config->info.depth ||
159 !config->info.array_size || !config->info.levels)
160 return -EINVAL;
161
162 switch (config->info.samples) {
163 case 0:
164 case 1:
165 case 2:
166 case 4:
167 case 8:
168 break;
169 case 16:
170 if (flags & RADEON_SURF_Z_OR_SBUFFER)
171 return -EINVAL;
172 break;
173 default:
174 return -EINVAL;
175 }
176
177 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
178 switch (config->info.storage_samples) {
179 case 0:
180 case 1:
181 case 2:
182 case 4:
183 case 8:
184 break;
185 default:
186 return -EINVAL;
187 }
188 }
189
190 if (config->is_3d && config->info.array_size > 1)
191 return -EINVAL;
192 if (config->is_cube && config->info.depth > 1)
193 return -EINVAL;
194
195 return 0;
196 }
197
198 static int gfx6_compute_level(ADDR_HANDLE addrlib,
199 const struct ac_surf_config *config,
200 struct radeon_surf *surf, bool is_stencil,
201 unsigned level, bool compressed,
202 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
203 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
204 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
205 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
206 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
207 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
208 {
209 struct legacy_surf_level *surf_level;
210 ADDR_E_RETURNCODE ret;
211
212 AddrSurfInfoIn->mipLevel = level;
213 AddrSurfInfoIn->width = u_minify(config->info.width, level);
214 AddrSurfInfoIn->height = u_minify(config->info.height, level);
215
216 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
217 * because GFX9 needs linear alignment of 256 bytes.
218 */
219 if (config->info.levels == 1 &&
220 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
221 AddrSurfInfoIn->bpp &&
222 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
223 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
224
225 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
226 }
227
228 /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
229 * true for r32g32b32 formats. */
230 if (AddrSurfInfoIn->bpp == 96) {
231 assert(config->info.levels == 1);
232 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
233
234 /* The least common multiple of 64 bytes and 12 bytes/pixel is
235 * 192 bytes, or 16 pixels. */
236 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
237 }
238
239 if (config->is_3d)
240 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
241 else if (config->is_cube)
242 AddrSurfInfoIn->numSlices = 6;
243 else
244 AddrSurfInfoIn->numSlices = config->info.array_size;
245
246 if (level > 0) {
247 /* Set the base level pitch. This is needed for calculation
248 * of non-zero levels. */
249 if (is_stencil)
250 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
251 else
252 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
253
254 /* Convert blocks to pixels for compressed formats. */
255 if (compressed)
256 AddrSurfInfoIn->basePitch *= surf->blk_w;
257 }
258
259 ret = AddrComputeSurfaceInfo(addrlib,
260 AddrSurfInfoIn,
261 AddrSurfInfoOut);
262 if (ret != ADDR_OK) {
263 return ret;
264 }
265
266 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
267 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
268 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
269 surf_level->nblk_x = AddrSurfInfoOut->pitch;
270 surf_level->nblk_y = AddrSurfInfoOut->height;
271
272 switch (AddrSurfInfoOut->tileMode) {
273 case ADDR_TM_LINEAR_ALIGNED:
274 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
275 break;
276 case ADDR_TM_1D_TILED_THIN1:
277 surf_level->mode = RADEON_SURF_MODE_1D;
278 break;
279 case ADDR_TM_2D_TILED_THIN1:
280 surf_level->mode = RADEON_SURF_MODE_2D;
281 break;
282 default:
283 assert(0);
284 }
285
286 if (is_stencil)
287 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
288 else
289 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
290
291 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
292
293 /* Clear DCC fields at the beginning. */
294 surf_level->dcc_offset = 0;
295
296 /* The previous level's flag tells us if we can use DCC for this level. */
297 if (AddrSurfInfoIn->flags.dccCompatible &&
298 (level == 0 || AddrDccOut->subLvlCompressible)) {
299 bool prev_level_clearable = level == 0 ||
300 AddrDccOut->dccRamSizeAligned;
301
302 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
303 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
304 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
305 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
306 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
307
308 ret = AddrComputeDccInfo(addrlib,
309 AddrDccIn,
310 AddrDccOut);
311
312 if (ret == ADDR_OK) {
313 surf_level->dcc_offset = surf->dcc_size;
314 surf->num_dcc_levels = level + 1;
315 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
316 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
317
318 /* If the DCC size of a subresource (1 mip level or 1 slice)
319 * is not aligned, the DCC memory layout is not contiguous for
320 * that subresource, which means we can't use fast clear.
321 *
322 * We only do fast clears for whole mipmap levels. If we did
323 * per-slice fast clears, the same restriction would apply.
324 * (i.e. only compute the slice size and see if it's aligned)
325 *
326 * The last level can be non-contiguous and still be clearable
327 * if it's interleaved with the next level that doesn't exist.
328 */
329 if (AddrDccOut->dccRamSizeAligned ||
330 (prev_level_clearable && level == config->info.levels - 1))
331 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
332 else
333 surf_level->dcc_fast_clear_size = 0;
334
335 /* Compute the DCC slice size because addrlib doesn't
336 * provide this info. As DCC memory is linear (each
337 * slice is the same size) it's easy to compute.
338 */
339 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
340
341 /* For arrays, we have to compute the DCC info again
342 * with one slice size to get a correct fast clear
343 * size.
344 */
345 if (config->info.array_size > 1) {
346 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
347 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
348 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
349 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
350 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
351
352 ret = AddrComputeDccInfo(addrlib,
353 AddrDccIn, AddrDccOut);
354 if (ret == ADDR_OK) {
355 /* If the DCC memory isn't properly
356 * aligned, the data are interleaved
357 * accross slices.
358 */
359 if (AddrDccOut->dccRamSizeAligned)
360 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
361 else
362 surf_level->dcc_slice_fast_clear_size = 0;
363 }
364
365 if (surf->flags & RADEON_SURF_CONTIGUOUS_DCC_LAYERS &&
366 surf->dcc_slice_size != surf_level->dcc_slice_fast_clear_size) {
367 surf->dcc_size = 0;
368 surf->num_dcc_levels = 0;
369 AddrDccOut->subLvlCompressible = false;
370 }
371 } else {
372 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
373 }
374 }
375 }
376
377 /* HTILE. */
378 if (!is_stencil &&
379 AddrSurfInfoIn->flags.depth &&
380 surf_level->mode == RADEON_SURF_MODE_2D &&
381 level == 0 &&
382 !(surf->flags & RADEON_SURF_NO_HTILE)) {
383 AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
384 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
385 AddrHtileIn->height = AddrSurfInfoOut->height;
386 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
387 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
388 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
389 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
390 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
391 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
392
393 ret = AddrComputeHtileInfo(addrlib,
394 AddrHtileIn,
395 AddrHtileOut);
396
397 if (ret == ADDR_OK) {
398 surf->htile_size = AddrHtileOut->htileBytes;
399 surf->htile_slice_size = AddrHtileOut->sliceSize;
400 surf->htile_alignment = AddrHtileOut->baseAlign;
401 }
402 }
403
404 return 0;
405 }
406
407 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
408 const struct radeon_info *info)
409 {
410 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
411
412 if (info->chip_class >= GFX7)
413 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
414 else
415 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
416 }
417
418 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
419 {
420 unsigned index, tileb;
421
422 tileb = 8 * 8 * surf->bpe;
423 tileb = MIN2(surf->u.legacy.tile_split, tileb);
424
425 for (index = 0; tileb > 64; index++)
426 tileb >>= 1;
427
428 assert(index < 16);
429 return index;
430 }
431
432 static bool get_display_flag(const struct ac_surf_config *config,
433 const struct radeon_surf *surf)
434 {
435 unsigned num_channels = config->info.num_channels;
436 unsigned bpe = surf->bpe;
437
438 if (!config->is_3d &&
439 !config->is_cube &&
440 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
441 surf->flags & RADEON_SURF_SCANOUT &&
442 config->info.samples <= 1 &&
443 surf->blk_w <= 2 && surf->blk_h == 1) {
444 /* subsampled */
445 if (surf->blk_w == 2 && surf->blk_h == 1)
446 return true;
447
448 if (/* RGBA8 or RGBA16F */
449 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
450 /* R5G6B5 or R5G5B5A1 */
451 (bpe == 2 && num_channels >= 3) ||
452 /* C8 palette */
453 (bpe == 1 && num_channels == 1))
454 return true;
455 }
456 return false;
457 }
458
459 /**
460 * This must be called after the first level is computed.
461 *
462 * Copy surface-global settings like pipe/bank config from level 0 surface
463 * computation, and compute tile swizzle.
464 */
465 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
466 const struct radeon_info *info,
467 const struct ac_surf_config *config,
468 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
469 struct radeon_surf *surf)
470 {
471 surf->surf_alignment = csio->baseAlign;
472 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
473 gfx6_set_micro_tile_mode(surf, info);
474
475 /* For 2D modes only. */
476 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
477 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
478 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
479 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
480 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
481 surf->u.legacy.num_banks = csio->pTileInfo->banks;
482 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
483 } else {
484 surf->u.legacy.macro_tile_index = 0;
485 }
486
487 /* Compute tile swizzle. */
488 /* TODO: fix tile swizzle with mipmapping for GFX6 */
489 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
490 config->info.surf_index &&
491 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
492 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
493 !get_display_flag(config, surf)) {
494 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
495 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
496
497 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
498 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
499
500 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
501 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
502 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
503 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
504 AddrBaseSwizzleIn.tileMode = csio->tileMode;
505
506 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
507 &AddrBaseSwizzleOut);
508 if (r != ADDR_OK)
509 return r;
510
511 assert(AddrBaseSwizzleOut.tileSwizzle <=
512 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
513 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
514 }
515 return 0;
516 }
517
518 static void ac_compute_cmask(const struct radeon_info *info,
519 const struct ac_surf_config *config,
520 struct radeon_surf *surf)
521 {
522 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
523 unsigned num_pipes = info->num_tile_pipes;
524 unsigned cl_width, cl_height;
525
526 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER || surf->is_linear ||
527 (config->info.samples >= 2 && !surf->fmask_size))
528 return;
529
530 assert(info->chip_class <= GFX8);
531
532 switch (num_pipes) {
533 case 2:
534 cl_width = 32;
535 cl_height = 16;
536 break;
537 case 4:
538 cl_width = 32;
539 cl_height = 32;
540 break;
541 case 8:
542 cl_width = 64;
543 cl_height = 32;
544 break;
545 case 16: /* Hawaii */
546 cl_width = 64;
547 cl_height = 64;
548 break;
549 default:
550 assert(0);
551 return;
552 }
553
554 unsigned base_align = num_pipes * pipe_interleave_bytes;
555
556 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
557 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
558 unsigned slice_elements = (width * height) / (8*8);
559
560 /* Each element of CMASK is a nibble. */
561 unsigned slice_bytes = slice_elements / 2;
562
563 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
564 if (surf->u.legacy.cmask_slice_tile_max)
565 surf->u.legacy.cmask_slice_tile_max -= 1;
566
567 unsigned num_layers;
568 if (config->is_3d)
569 num_layers = config->info.depth;
570 else if (config->is_cube)
571 num_layers = 6;
572 else
573 num_layers = config->info.array_size;
574
575 surf->cmask_alignment = MAX2(256, base_align);
576 surf->cmask_slice_size = align(slice_bytes, base_align);
577 surf->cmask_size = surf->cmask_slice_size * num_layers;
578 }
579
580 /**
581 * Fill in the tiling information in \p surf based on the given surface config.
582 *
583 * The following fields of \p surf must be initialized by the caller:
584 * blk_w, blk_h, bpe, flags.
585 */
586 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
587 const struct radeon_info *info,
588 const struct ac_surf_config *config,
589 enum radeon_surf_mode mode,
590 struct radeon_surf *surf)
591 {
592 unsigned level;
593 bool compressed;
594 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
595 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
596 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
597 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
598 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
599 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
600 ADDR_TILEINFO AddrTileInfoIn = {0};
601 ADDR_TILEINFO AddrTileInfoOut = {0};
602 int r;
603
604 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
605 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
606 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
607 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
608 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
609 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
610 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
611
612 compressed = surf->blk_w == 4 && surf->blk_h == 4;
613
614 /* MSAA requires 2D tiling. */
615 if (config->info.samples > 1)
616 mode = RADEON_SURF_MODE_2D;
617
618 /* DB doesn't support linear layouts. */
619 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
620 mode < RADEON_SURF_MODE_1D)
621 mode = RADEON_SURF_MODE_1D;
622
623 /* Set the requested tiling mode. */
624 switch (mode) {
625 case RADEON_SURF_MODE_LINEAR_ALIGNED:
626 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
627 break;
628 case RADEON_SURF_MODE_1D:
629 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
630 break;
631 case RADEON_SURF_MODE_2D:
632 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
633 break;
634 default:
635 assert(0);
636 }
637
638 /* The format must be set correctly for the allocation of compressed
639 * textures to work. In other cases, setting the bpp is sufficient.
640 */
641 if (compressed) {
642 switch (surf->bpe) {
643 case 8:
644 AddrSurfInfoIn.format = ADDR_FMT_BC1;
645 break;
646 case 16:
647 AddrSurfInfoIn.format = ADDR_FMT_BC3;
648 break;
649 default:
650 assert(0);
651 }
652 }
653 else {
654 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
655 }
656
657 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
658 MAX2(1, config->info.samples);
659 AddrSurfInfoIn.tileIndex = -1;
660
661 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
662 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
663 MAX2(1, config->info.storage_samples);
664 }
665
666 /* Set the micro tile type. */
667 if (surf->flags & RADEON_SURF_SCANOUT)
668 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
669 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
670 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
671 else
672 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
673
674 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
675 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
676 AddrSurfInfoIn.flags.cube = config->is_cube;
677 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
678 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
679 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
680
681 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
682 * requested, because TC-compatible HTILE requires 2D tiling.
683 */
684 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
685 !AddrSurfInfoIn.flags.fmask &&
686 config->info.samples <= 1 &&
687 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
688
689 /* DCC notes:
690 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
691 * with samples >= 4.
692 * - Mipmapped array textures have low performance (discovered by a closed
693 * driver team).
694 */
695 AddrSurfInfoIn.flags.dccCompatible =
696 info->chip_class >= GFX8 &&
697 info->has_graphics && /* disable DCC on compute-only chips */
698 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
699 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
700 !compressed &&
701 ((config->info.array_size == 1 && config->info.depth == 1) ||
702 config->info.levels == 1);
703
704 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
705 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
706
707 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
708 * for Z and stencil. This can cause a number of problems which we work
709 * around here:
710 *
711 * - a depth part that is incompatible with mipmapped texturing
712 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
713 * incorrect tiling applied to the stencil part, stencil buffer
714 * memory accesses that go out of bounds) even without mipmapping
715 *
716 * Some piglit tests that are prone to different types of related
717 * failures:
718 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
719 * ./bin/framebuffer-blit-levels {draw,read} stencil
720 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
721 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
722 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
723 */
724 int stencil_tile_idx = -1;
725
726 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
727 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
728 /* Compute stencilTileIdx that is compatible with the (depth)
729 * tileIdx. This degrades the depth surface if necessary to
730 * ensure that a matching stencilTileIdx exists. */
731 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
732
733 /* Keep the depth mip-tail compatible with texturing. */
734 AddrSurfInfoIn.flags.noStencil = 1;
735 }
736
737 /* Set preferred macrotile parameters. This is usually required
738 * for shared resources. This is for 2D tiling only. */
739 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
740 surf->u.legacy.bankw && surf->u.legacy.bankh &&
741 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
742 /* If any of these parameters are incorrect, the calculation
743 * will fail. */
744 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
745 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
746 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
747 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
748 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
749 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
750 AddrSurfInfoIn.flags.opt4Space = 0;
751 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
752
753 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
754 * the tile index, because we are expected to know it if
755 * we know the other parameters.
756 *
757 * This is something that can easily be fixed in Addrlib.
758 * For now, just figure it out here.
759 * Note that only 2D_TILE_THIN1 is handled here.
760 */
761 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
762 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
763
764 if (info->chip_class == GFX6) {
765 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
766 if (surf->bpe == 2)
767 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
768 else
769 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
770 } else {
771 if (surf->bpe == 1)
772 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
773 else if (surf->bpe == 2)
774 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
775 else if (surf->bpe == 4)
776 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
777 else
778 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
779 }
780 } else {
781 /* GFX7 - GFX8 */
782 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
783 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
784 else
785 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
786
787 /* Addrlib doesn't set this if tileIndex is forced like above. */
788 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
789 }
790 }
791
792 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
793 surf->num_dcc_levels = 0;
794 surf->surf_size = 0;
795 surf->dcc_size = 0;
796 surf->dcc_alignment = 1;
797 surf->htile_size = 0;
798 surf->htile_slice_size = 0;
799 surf->htile_alignment = 1;
800
801 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
802 !(surf->flags & RADEON_SURF_ZBUFFER);
803
804 /* Calculate texture layout information. */
805 if (!only_stencil) {
806 for (level = 0; level < config->info.levels; level++) {
807 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
808 &AddrSurfInfoIn, &AddrSurfInfoOut,
809 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
810 if (r)
811 return r;
812
813 if (level > 0)
814 continue;
815
816 if (!AddrSurfInfoOut.tcCompatible) {
817 AddrSurfInfoIn.flags.tcCompatible = 0;
818 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
819 }
820
821 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
822 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
823 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
824 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
825
826 assert(stencil_tile_idx >= 0);
827 }
828
829 r = gfx6_surface_settings(addrlib, info, config,
830 &AddrSurfInfoOut, surf);
831 if (r)
832 return r;
833 }
834 }
835
836 /* Calculate texture layout information for stencil. */
837 if (surf->flags & RADEON_SURF_SBUFFER) {
838 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
839 AddrSurfInfoIn.bpp = 8;
840 AddrSurfInfoIn.flags.depth = 0;
841 AddrSurfInfoIn.flags.stencil = 1;
842 AddrSurfInfoIn.flags.tcCompatible = 0;
843 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
844 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
845
846 for (level = 0; level < config->info.levels; level++) {
847 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
848 &AddrSurfInfoIn, &AddrSurfInfoOut,
849 &AddrDccIn, &AddrDccOut,
850 NULL, NULL);
851 if (r)
852 return r;
853
854 /* DB uses the depth pitch for both stencil and depth. */
855 if (!only_stencil) {
856 if (surf->u.legacy.stencil_level[level].nblk_x !=
857 surf->u.legacy.level[level].nblk_x)
858 surf->u.legacy.stencil_adjusted = true;
859 } else {
860 surf->u.legacy.level[level].nblk_x =
861 surf->u.legacy.stencil_level[level].nblk_x;
862 }
863
864 if (level == 0) {
865 if (only_stencil) {
866 r = gfx6_surface_settings(addrlib, info, config,
867 &AddrSurfInfoOut, surf);
868 if (r)
869 return r;
870 }
871
872 /* For 2D modes only. */
873 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
874 surf->u.legacy.stencil_tile_split =
875 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
876 }
877 }
878 }
879 }
880
881 /* Compute FMASK. */
882 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
883 info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
884 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
885 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
886 ADDR_TILEINFO fmask_tile_info = {};
887
888 fin.size = sizeof(fin);
889 fout.size = sizeof(fout);
890
891 fin.tileMode = AddrSurfInfoOut.tileMode;
892 fin.pitch = AddrSurfInfoOut.pitch;
893 fin.height = config->info.height;
894 fin.numSlices = AddrSurfInfoIn.numSlices;
895 fin.numSamples = AddrSurfInfoIn.numSamples;
896 fin.numFrags = AddrSurfInfoIn.numFrags;
897 fin.tileIndex = -1;
898 fout.pTileInfo = &fmask_tile_info;
899
900 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
901 if (r)
902 return r;
903
904 surf->fmask_size = fout.fmaskBytes;
905 surf->fmask_alignment = fout.baseAlign;
906 surf->fmask_tile_swizzle = 0;
907
908 surf->u.legacy.fmask.slice_tile_max =
909 (fout.pitch * fout.height) / 64;
910 if (surf->u.legacy.fmask.slice_tile_max)
911 surf->u.legacy.fmask.slice_tile_max -= 1;
912
913 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
914 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
915 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
916 surf->u.legacy.fmask.slice_size = fout.sliceSize;
917
918 /* Compute tile swizzle for FMASK. */
919 if (config->info.fmask_surf_index &&
920 !(surf->flags & RADEON_SURF_SHAREABLE)) {
921 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
922 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
923
924 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
925 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
926
927 /* This counter starts from 1 instead of 0. */
928 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
929 xin.tileIndex = fout.tileIndex;
930 xin.macroModeIndex = fout.macroModeIndex;
931 xin.pTileInfo = fout.pTileInfo;
932 xin.tileMode = fin.tileMode;
933
934 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
935 if (r != ADDR_OK)
936 return r;
937
938 assert(xout.tileSwizzle <=
939 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
940 surf->fmask_tile_swizzle = xout.tileSwizzle;
941 }
942 }
943
944 /* Recalculate the whole DCC miptree size including disabled levels.
945 * This is what addrlib does, but calling addrlib would be a lot more
946 * complicated.
947 */
948 if (surf->dcc_size && config->info.levels > 1) {
949 /* The smallest miplevels that are never compressed by DCC
950 * still read the DCC buffer via TC if the base level uses DCC,
951 * and for some reason the DCC buffer needs to be larger if
952 * the miptree uses non-zero tile_swizzle. Otherwise there are
953 * VM faults.
954 *
955 * "dcc_alignment * 4" was determined by trial and error.
956 */
957 surf->dcc_size = align64(surf->surf_size >> 8,
958 surf->dcc_alignment * 4);
959 }
960
961 /* Make sure HTILE covers the whole miptree, because the shader reads
962 * TC-compatible HTILE even for levels where it's disabled by DB.
963 */
964 if (surf->htile_size && config->info.levels > 1 &&
965 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
966 /* MSAA can't occur with levels > 1, so ignore the sample count. */
967 const unsigned total_pixels = surf->surf_size / surf->bpe;
968 const unsigned htile_block_size = 8 * 8;
969 const unsigned htile_element_size = 4;
970
971 surf->htile_size = (total_pixels / htile_block_size) *
972 htile_element_size;
973 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
974 } else if (!surf->htile_size) {
975 /* Unset this if HTILE is not present. */
976 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
977 }
978
979 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
980 surf->is_displayable = surf->is_linear ||
981 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
982 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
983
984 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
985 * used at the same time. This case is not currently expected to occur
986 * because we don't use rotated. Enforce this restriction on all chips
987 * to facilitate testing.
988 */
989 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
990 assert(!"rotate micro tile mode is unsupported");
991 return ADDR_ERROR;
992 }
993
994 ac_compute_cmask(info, config, surf);
995 return 0;
996 }
997
998 /* This is only called when expecting a tiled layout. */
999 static int
1000 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
1001 struct radeon_surf *surf,
1002 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
1003 bool is_fmask, AddrSwizzleMode *swizzle_mode)
1004 {
1005 ADDR_E_RETURNCODE ret;
1006 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
1007 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
1008
1009 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
1010 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
1011
1012 sin.flags = in->flags;
1013 sin.resourceType = in->resourceType;
1014 sin.format = in->format;
1015 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
1016 /* TODO: We could allow some of these: */
1017 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
1018 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
1019 sin.bpp = in->bpp;
1020 sin.width = in->width;
1021 sin.height = in->height;
1022 sin.numSlices = in->numSlices;
1023 sin.numMipLevels = in->numMipLevels;
1024 sin.numSamples = in->numSamples;
1025 sin.numFrags = in->numFrags;
1026
1027 if (is_fmask) {
1028 sin.flags.display = 0;
1029 sin.flags.color = 0;
1030 sin.flags.fmask = 1;
1031 }
1032
1033 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1034 sin.forbiddenBlock.linear = 1;
1035
1036 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1037 sin.preferredSwSet.sw_D = 1;
1038 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
1039 sin.preferredSwSet.sw_S = 1;
1040 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1041 sin.preferredSwSet.sw_Z = 1;
1042 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
1043 sin.preferredSwSet.sw_R = 1;
1044 }
1045
1046 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1047 if (ret != ADDR_OK)
1048 return ret;
1049
1050 *swizzle_mode = sout.swizzleMode;
1051 return 0;
1052 }
1053
1054 static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
1055 {
1056 if (info->chip_class >= GFX10)
1057 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1058
1059 return sw_mode != ADDR_SW_LINEAR;
1060 }
1061
1062 ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info,
1063 const struct radeon_surf *surf)
1064 {
1065 if (info->chip_class <= GFX9) {
1066 /* Only independent 64B blocks are supported. */
1067 return surf->u.gfx9.dcc.independent_64B_blocks &&
1068 !surf->u.gfx9.dcc.independent_128B_blocks &&
1069 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
1070 }
1071
1072 if (info->family == CHIP_NAVI10) {
1073 /* Only independent 128B blocks are supported. */
1074 return !surf->u.gfx9.dcc.independent_64B_blocks &&
1075 surf->u.gfx9.dcc.independent_128B_blocks &&
1076 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1077 }
1078
1079 if (info->family == CHIP_NAVI12 ||
1080 info->family == CHIP_NAVI14) {
1081 /* Either 64B or 128B can be used, but not both.
1082 * If 64B is used, DCC image stores are unsupported.
1083 */
1084 return surf->u.gfx9.dcc.independent_64B_blocks !=
1085 surf->u.gfx9.dcc.independent_128B_blocks &&
1086 (!surf->u.gfx9.dcc.independent_64B_blocks ||
1087 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) &&
1088 (!surf->u.gfx9.dcc.independent_128B_blocks ||
1089 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
1090 }
1091
1092 /* 128B is recommended, but 64B can be set too if needed for 4K by DCN.
1093 * Since there is no reason to ever disable 128B, require it.
1094 * DCC image stores are always supported.
1095 */
1096 return surf->u.gfx9.dcc.independent_128B_blocks &&
1097 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1098 }
1099
1100 static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
1101 const struct ac_surf_config *config,
1102 const struct radeon_surf *surf,
1103 bool rb_aligned, bool pipe_aligned)
1104 {
1105 if (!info->use_display_dcc_unaligned &&
1106 !info->use_display_dcc_with_retile_blit)
1107 return false;
1108
1109 /* 16bpp and 64bpp are more complicated, so they are disallowed for now. */
1110 if (surf->bpe != 4)
1111 return false;
1112
1113 /* Handle unaligned DCC. */
1114 if (info->use_display_dcc_unaligned &&
1115 (rb_aligned || pipe_aligned))
1116 return false;
1117
1118 switch (info->chip_class) {
1119 case GFX9:
1120 /* There are more constraints, but we always set
1121 * INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B,
1122 * which always works.
1123 */
1124 assert(surf->u.gfx9.dcc.independent_64B_blocks &&
1125 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1126 return true;
1127 case GFX10:
1128 case GFX10_3:
1129 /* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
1130 if (info->chip_class == GFX10 &&
1131 surf->u.gfx9.dcc.independent_128B_blocks)
1132 return false;
1133
1134 /* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1. */
1135 return ((config->info.width <= 2560 &&
1136 config->info.height <= 2560) ||
1137 (surf->u.gfx9.dcc.independent_64B_blocks &&
1138 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
1139 default:
1140 unreachable("unhandled chip");
1141 return false;
1142 }
1143 }
1144
1145 static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
1146 const struct radeon_info *info,
1147 const struct ac_surf_config *config,
1148 struct radeon_surf *surf, bool compressed,
1149 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1150 {
1151 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1152 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1153 ADDR_E_RETURNCODE ret;
1154
1155 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1156 out.pMipInfo = mip_info;
1157
1158 ret = Addr2ComputeSurfaceInfo(addrlib->handle, in, &out);
1159 if (ret != ADDR_OK)
1160 return ret;
1161
1162 if (in->flags.stencil) {
1163 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1164 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1165 out.mipChainPitch - 1;
1166 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1167 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1168 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1169 return 0;
1170 }
1171
1172 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1173 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1174 out.mipChainPitch - 1;
1175
1176 /* CMASK fast clear uses these even if FMASK isn't allocated.
1177 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1178 */
1179 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1180 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1181
1182 surf->u.gfx9.surf_slice_size = out.sliceSize;
1183 surf->u.gfx9.surf_pitch = out.pitch;
1184 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch &&
1185 surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR) {
1186 /* Adjust surf_pitch to be in elements units,
1187 * not in pixels */
1188 surf->u.gfx9.surf_pitch =
1189 align(surf->u.gfx9.surf_pitch / surf->blk_w, 256 / surf->bpe);
1190 surf->u.gfx9.surf.epitch = MAX2(surf->u.gfx9.surf.epitch,
1191 surf->u.gfx9.surf_pitch * surf->blk_w - 1);
1192 }
1193 surf->u.gfx9.surf_height = out.height;
1194 surf->surf_size = out.surfSize;
1195 surf->surf_alignment = out.baseAlign;
1196
1197 if (in->swizzleMode == ADDR_SW_LINEAR) {
1198 for (unsigned i = 0; i < in->numMipLevels; i++) {
1199 surf->u.gfx9.offset[i] = mip_info[i].offset;
1200 surf->u.gfx9.pitch[i] = mip_info[i].pitch;
1201 }
1202 }
1203
1204 if (in->flags.depth) {
1205 assert(in->swizzleMode != ADDR_SW_LINEAR);
1206
1207 if (surf->flags & RADEON_SURF_NO_HTILE)
1208 return 0;
1209
1210 /* HTILE */
1211 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1212 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1213
1214 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1215 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1216
1217 assert(in->flags.metaPipeUnaligned == 0);
1218 assert(in->flags.metaRbUnaligned == 0);
1219
1220 hin.hTileFlags.pipeAligned = 1;
1221 hin.hTileFlags.rbAligned = 1;
1222 hin.depthFlags = in->flags;
1223 hin.swizzleMode = in->swizzleMode;
1224 hin.unalignedWidth = in->width;
1225 hin.unalignedHeight = in->height;
1226 hin.numSlices = in->numSlices;
1227 hin.numMipLevels = in->numMipLevels;
1228 hin.firstMipIdInTail = out.firstMipIdInTail;
1229
1230 ret = Addr2ComputeHtileInfo(addrlib->handle, &hin, &hout);
1231 if (ret != ADDR_OK)
1232 return ret;
1233
1234 surf->htile_size = hout.htileBytes;
1235 surf->htile_slice_size = hout.sliceSize;
1236 surf->htile_alignment = hout.baseAlign;
1237 return 0;
1238 }
1239
1240 {
1241 /* Compute tile swizzle for the color surface.
1242 * All *_X and *_T modes can use the swizzle.
1243 */
1244 if (config->info.surf_index &&
1245 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1246 !out.mipChainInTail &&
1247 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1248 !in->flags.display) {
1249 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1250 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1251
1252 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1253 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1254
1255 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1256 xin.flags = in->flags;
1257 xin.swizzleMode = in->swizzleMode;
1258 xin.resourceType = in->resourceType;
1259 xin.format = in->format;
1260 xin.numSamples = in->numSamples;
1261 xin.numFrags = in->numFrags;
1262
1263 ret = Addr2ComputePipeBankXor(addrlib->handle, &xin, &xout);
1264 if (ret != ADDR_OK)
1265 return ret;
1266
1267 assert(xout.pipeBankXor <=
1268 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1269 surf->tile_swizzle = xout.pipeBankXor;
1270 }
1271
1272 /* DCC */
1273 if (info->has_graphics &&
1274 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1275 !compressed &&
1276 is_dcc_supported_by_CB(info, in->swizzleMode) &&
1277 (!in->flags.display ||
1278 is_dcc_supported_by_DCN(info, config, surf,
1279 !in->flags.metaRbUnaligned,
1280 !in->flags.metaPipeUnaligned))) {
1281 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1282 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1283 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1284
1285 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1286 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1287 dout.pMipInfo = meta_mip_info;
1288
1289 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1290 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1291 din.colorFlags = in->flags;
1292 din.resourceType = in->resourceType;
1293 din.swizzleMode = in->swizzleMode;
1294 din.bpp = in->bpp;
1295 din.unalignedWidth = in->width;
1296 din.unalignedHeight = in->height;
1297 din.numSlices = in->numSlices;
1298 din.numFrags = in->numFrags;
1299 din.numMipLevels = in->numMipLevels;
1300 din.dataSurfaceSize = out.surfSize;
1301 din.firstMipIdInTail = out.firstMipIdInTail;
1302
1303 ret = Addr2ComputeDccInfo(addrlib->handle, &din, &dout);
1304 if (ret != ADDR_OK)
1305 return ret;
1306
1307 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1308 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1309 surf->u.gfx9.dcc_block_width = dout.compressBlkWidth;
1310 surf->u.gfx9.dcc_block_height = dout.compressBlkHeight;
1311 surf->u.gfx9.dcc_block_depth = dout.compressBlkDepth;
1312 surf->dcc_size = dout.dccRamSize;
1313 surf->dcc_alignment = dout.dccRamBaseAlign;
1314 surf->num_dcc_levels = in->numMipLevels;
1315
1316 /* Disable DCC for levels that are in the mip tail.
1317 *
1318 * There are two issues that this is intended to
1319 * address:
1320 *
1321 * 1. Multiple mip levels may share a cache line. This
1322 * can lead to corruption when switching between
1323 * rendering to different mip levels because the
1324 * RBs don't maintain coherency.
1325 *
1326 * 2. Texturing with metadata after rendering sometimes
1327 * fails with corruption, probably for a similar
1328 * reason.
1329 *
1330 * Working around these issues for all levels in the
1331 * mip tail may be overly conservative, but it's what
1332 * Vulkan does.
1333 *
1334 * Alternative solutions that also work but are worse:
1335 * - Disable DCC entirely.
1336 * - Flush TC L2 after rendering.
1337 */
1338 for (unsigned i = 0; i < in->numMipLevels; i++) {
1339 if (meta_mip_info[i].inMiptail) {
1340 surf->num_dcc_levels = i;
1341 break;
1342 }
1343 }
1344
1345 if (!surf->num_dcc_levels)
1346 surf->dcc_size = 0;
1347
1348 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1349 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1350 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1351
1352 /* Compute displayable DCC. */
1353 if (in->flags.display &&
1354 surf->num_dcc_levels &&
1355 info->use_display_dcc_with_retile_blit) {
1356 /* Compute displayable DCC info. */
1357 din.dccKeyFlags.pipeAligned = 0;
1358 din.dccKeyFlags.rbAligned = 0;
1359
1360 assert(din.numSlices == 1);
1361 assert(din.numMipLevels == 1);
1362 assert(din.numFrags == 1);
1363 assert(surf->tile_swizzle == 0);
1364 assert(surf->u.gfx9.dcc.pipe_aligned ||
1365 surf->u.gfx9.dcc.rb_aligned);
1366
1367 ret = Addr2ComputeDccInfo(addrlib->handle, &din, &dout);
1368 if (ret != ADDR_OK)
1369 return ret;
1370
1371 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1372 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1373 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1374 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1375
1376 surf->u.gfx9.dcc_retile_use_uint16 =
1377 surf->u.gfx9.display_dcc_size <= UINT16_MAX + 1 &&
1378 surf->dcc_size <= UINT16_MAX + 1;
1379 surf->u.gfx9.dcc_retile_num_elements =
1380 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1381 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1382 /* Align the size to 4 (for the compute shader). */
1383 surf->u.gfx9.dcc_retile_num_elements =
1384 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1385
1386 if (!(surf->flags & RADEON_SURF_IMPORTED)) {
1387 /* Compute address mapping from non-displayable to displayable DCC. */
1388 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1389 addrin.size = sizeof(addrin);
1390 addrin.swizzleMode = din.swizzleMode;
1391 addrin.resourceType = din.resourceType;
1392 addrin.bpp = din.bpp;
1393 addrin.numSlices = 1;
1394 addrin.numMipLevels = 1;
1395 addrin.numFrags = 1;
1396 addrin.pitch = dout.pitch;
1397 addrin.height = dout.height;
1398 addrin.compressBlkWidth = dout.compressBlkWidth;
1399 addrin.compressBlkHeight = dout.compressBlkHeight;
1400 addrin.compressBlkDepth = dout.compressBlkDepth;
1401 addrin.metaBlkWidth = dout.metaBlkWidth;
1402 addrin.metaBlkHeight = dout.metaBlkHeight;
1403 addrin.metaBlkDepth = dout.metaBlkDepth;
1404 addrin.dccRamSliceSize = dout.dccRamSliceSize;
1405
1406 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1407 addrout.size = sizeof(addrout);
1408
1409 surf->u.gfx9.dcc_retile_map =
1410 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1411 if (!surf->u.gfx9.dcc_retile_map)
1412 return ADDR_OUTOFMEMORY;
1413
1414 unsigned index = 0;
1415
1416 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1417 addrin.y = y;
1418
1419 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1420 addrin.x = x;
1421
1422 /* Compute src DCC address */
1423 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1424 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1425 addrout.addr = 0;
1426
1427 ret = Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout);
1428 if (ret != ADDR_OK)
1429 return ret;
1430
1431 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1432
1433 /* Compute dst DCC address */
1434 addrin.dccKeyFlags.pipeAligned = 0;
1435 addrin.dccKeyFlags.rbAligned = 0;
1436 addrout.addr = 0;
1437
1438 ret = Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout);
1439 if (ret != ADDR_OK)
1440 return ret;
1441
1442 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1443
1444 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1445 index++;
1446 }
1447 }
1448 /* Fill the remaining pairs with the last one (for the compute shader). */
1449 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1450 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1451 }
1452 }
1453 }
1454
1455 /* FMASK */
1456 if (in->numSamples > 1 && info->has_graphics &&
1457 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1458 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1459 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1460
1461 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1462 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1463
1464 ret = gfx9_get_preferred_swizzle_mode(addrlib->handle, surf, in,
1465 true, &fin.swizzleMode);
1466 if (ret != ADDR_OK)
1467 return ret;
1468
1469 fin.unalignedWidth = in->width;
1470 fin.unalignedHeight = in->height;
1471 fin.numSlices = in->numSlices;
1472 fin.numSamples = in->numSamples;
1473 fin.numFrags = in->numFrags;
1474
1475 ret = Addr2ComputeFmaskInfo(addrlib->handle, &fin, &fout);
1476 if (ret != ADDR_OK)
1477 return ret;
1478
1479 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1480 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1481 surf->fmask_size = fout.fmaskBytes;
1482 surf->fmask_alignment = fout.baseAlign;
1483
1484 /* Compute tile swizzle for the FMASK surface. */
1485 if (config->info.fmask_surf_index &&
1486 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1487 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1488 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1489 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1490
1491 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1492 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1493
1494 /* This counter starts from 1 instead of 0. */
1495 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1496 xin.flags = in->flags;
1497 xin.swizzleMode = fin.swizzleMode;
1498 xin.resourceType = in->resourceType;
1499 xin.format = in->format;
1500 xin.numSamples = in->numSamples;
1501 xin.numFrags = in->numFrags;
1502
1503 ret = Addr2ComputePipeBankXor(addrlib->handle, &xin, &xout);
1504 if (ret != ADDR_OK)
1505 return ret;
1506
1507 assert(xout.pipeBankXor <=
1508 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1509 surf->fmask_tile_swizzle = xout.pipeBankXor;
1510 }
1511 }
1512
1513 /* CMASK -- on GFX10 only for FMASK */
1514 if (in->swizzleMode != ADDR_SW_LINEAR &&
1515 in->resourceType == ADDR_RSRC_TEX_2D &&
1516 ((info->chip_class <= GFX9 &&
1517 in->numSamples == 1 &&
1518 in->flags.metaPipeUnaligned == 0 &&
1519 in->flags.metaRbUnaligned == 0) ||
1520 (surf->fmask_size && in->numSamples >= 2))) {
1521 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1522 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1523
1524 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1525 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1526
1527 assert(in->flags.metaPipeUnaligned == 0);
1528 assert(in->flags.metaRbUnaligned == 0);
1529
1530 cin.cMaskFlags.pipeAligned = 1;
1531 cin.cMaskFlags.rbAligned = 1;
1532 cin.colorFlags = in->flags;
1533 cin.resourceType = in->resourceType;
1534 cin.unalignedWidth = in->width;
1535 cin.unalignedHeight = in->height;
1536 cin.numSlices = in->numSlices;
1537
1538 if (in->numSamples > 1)
1539 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1540 else
1541 cin.swizzleMode = in->swizzleMode;
1542
1543 ret = Addr2ComputeCmaskInfo(addrlib->handle, &cin, &cout);
1544 if (ret != ADDR_OK)
1545 return ret;
1546
1547 surf->cmask_size = cout.cmaskBytes;
1548 surf->cmask_alignment = cout.baseAlign;
1549 }
1550 }
1551
1552 return 0;
1553 }
1554
1555 static int gfx9_compute_surface(struct ac_addrlib *addrlib,
1556 const struct radeon_info *info,
1557 const struct ac_surf_config *config,
1558 enum radeon_surf_mode mode,
1559 struct radeon_surf *surf)
1560 {
1561 bool compressed;
1562 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1563 int r;
1564
1565 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1566
1567 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1568
1569 /* The format must be set correctly for the allocation of compressed
1570 * textures to work. In other cases, setting the bpp is sufficient. */
1571 if (compressed) {
1572 switch (surf->bpe) {
1573 case 8:
1574 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1575 break;
1576 case 16:
1577 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1578 break;
1579 default:
1580 assert(0);
1581 }
1582 } else {
1583 switch (surf->bpe) {
1584 case 1:
1585 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1586 AddrSurfInfoIn.format = ADDR_FMT_8;
1587 break;
1588 case 2:
1589 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1590 !(surf->flags & RADEON_SURF_SBUFFER));
1591 AddrSurfInfoIn.format = ADDR_FMT_16;
1592 break;
1593 case 4:
1594 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1595 !(surf->flags & RADEON_SURF_SBUFFER));
1596 AddrSurfInfoIn.format = ADDR_FMT_32;
1597 break;
1598 case 8:
1599 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1600 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1601 break;
1602 case 12:
1603 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1604 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1605 break;
1606 case 16:
1607 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1608 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1609 break;
1610 default:
1611 assert(0);
1612 }
1613 AddrSurfInfoIn.bpp = surf->bpe * 8;
1614 }
1615
1616 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1617 AddrSurfInfoIn.flags.color = is_color_surface &&
1618 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1619 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1620 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1621 /* flags.texture currently refers to TC-compatible HTILE */
1622 AddrSurfInfoIn.flags.texture = is_color_surface ||
1623 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1624 AddrSurfInfoIn.flags.opt4space = 1;
1625
1626 AddrSurfInfoIn.numMipLevels = config->info.levels;
1627 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1628 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1629
1630 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1631 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1632
1633 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1634 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1635 * must sample 1D textures as 2D. */
1636 if (config->is_3d)
1637 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1638 else if (info->chip_class != GFX9 && config->is_1d)
1639 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1640 else
1641 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1642
1643 AddrSurfInfoIn.width = config->info.width;
1644 AddrSurfInfoIn.height = config->info.height;
1645
1646 if (config->is_3d)
1647 AddrSurfInfoIn.numSlices = config->info.depth;
1648 else if (config->is_cube)
1649 AddrSurfInfoIn.numSlices = 6;
1650 else
1651 AddrSurfInfoIn.numSlices = config->info.array_size;
1652
1653 /* This is propagated to DCC. It must be 0 for HTILE and CMASK. */
1654 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1655 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1656
1657 /* Optimal values for the L2 cache. */
1658 if (info->chip_class == GFX9) {
1659 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1660 surf->u.gfx9.dcc.independent_128B_blocks = 0;
1661 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1662 } else if (info->chip_class >= GFX10) {
1663 surf->u.gfx9.dcc.independent_64B_blocks = 0;
1664 surf->u.gfx9.dcc.independent_128B_blocks = 1;
1665 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
1666 }
1667
1668 if (AddrSurfInfoIn.flags.display) {
1669 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1670 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1671 *
1672 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1673 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1674 * after rendering, so PIPE_ALIGNED=1 is recommended.
1675 */
1676 if (info->use_display_dcc_unaligned) {
1677 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1678 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1679 }
1680
1681 /* Adjust DCC settings to meet DCN requirements. */
1682 if (info->use_display_dcc_unaligned ||
1683 info->use_display_dcc_with_retile_blit) {
1684 /* Only Navi12/14 support independent 64B blocks in L2,
1685 * but without DCC image stores.
1686 */
1687 if (info->family == CHIP_NAVI12 ||
1688 info->family == CHIP_NAVI14) {
1689 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1690 surf->u.gfx9.dcc.independent_128B_blocks = 0;
1691 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1692 }
1693
1694 if (info->chip_class >= GFX10_3) {
1695 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1696 surf->u.gfx9.dcc.independent_128B_blocks = 1;
1697 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1698 }
1699 }
1700 }
1701
1702 switch (mode) {
1703 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1704 assert(config->info.samples <= 1);
1705 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1706 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1707 break;
1708
1709 case RADEON_SURF_MODE_1D:
1710 case RADEON_SURF_MODE_2D:
1711 if (surf->flags & RADEON_SURF_IMPORTED ||
1712 (info->chip_class >= GFX10 &&
1713 surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1714 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1715 break;
1716 }
1717
1718 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, surf, &AddrSurfInfoIn,
1719 false, &AddrSurfInfoIn.swizzleMode);
1720 if (r)
1721 return r;
1722 break;
1723
1724 default:
1725 assert(0);
1726 }
1727
1728 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1729 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1730
1731 surf->num_dcc_levels = 0;
1732 surf->surf_size = 0;
1733 surf->fmask_size = 0;
1734 surf->dcc_size = 0;
1735 surf->htile_size = 0;
1736 surf->htile_slice_size = 0;
1737 surf->u.gfx9.surf_offset = 0;
1738 surf->u.gfx9.stencil_offset = 0;
1739 surf->cmask_size = 0;
1740 surf->u.gfx9.dcc_retile_use_uint16 = false;
1741 surf->u.gfx9.dcc_retile_num_elements = 0;
1742 surf->u.gfx9.dcc_retile_map = NULL;
1743
1744 /* Calculate texture layout information. */
1745 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1746 &AddrSurfInfoIn);
1747 if (r)
1748 goto error;
1749
1750 /* Calculate texture layout information for stencil. */
1751 if (surf->flags & RADEON_SURF_SBUFFER) {
1752 AddrSurfInfoIn.flags.stencil = 1;
1753 AddrSurfInfoIn.bpp = 8;
1754 AddrSurfInfoIn.format = ADDR_FMT_8;
1755
1756 if (!AddrSurfInfoIn.flags.depth) {
1757 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, surf, &AddrSurfInfoIn,
1758 false, &AddrSurfInfoIn.swizzleMode);
1759 if (r)
1760 goto error;
1761 } else
1762 AddrSurfInfoIn.flags.depth = 0;
1763
1764 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1765 &AddrSurfInfoIn);
1766 if (r)
1767 goto error;
1768 }
1769
1770 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1771
1772 /* Query whether the surface is displayable. */
1773 /* This is only useful for surfaces that are allocated without SCANOUT. */
1774 bool displayable = false;
1775 if (!config->is_3d && !config->is_cube) {
1776 r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.surf.swizzle_mode,
1777 surf->bpe * 8, &displayable);
1778 if (r)
1779 goto error;
1780
1781 /* Display needs unaligned DCC. */
1782 if (surf->num_dcc_levels &&
1783 !is_dcc_supported_by_DCN(info, config, surf,
1784 surf->u.gfx9.dcc.rb_aligned,
1785 surf->u.gfx9.dcc.pipe_aligned))
1786 displayable = false;
1787 }
1788 surf->is_displayable = displayable;
1789
1790 /* Validate that we allocated a displayable surface if requested. */
1791 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
1792
1793 /* Validate that DCC is set up correctly. */
1794 if (surf->num_dcc_levels) {
1795 assert(is_dcc_supported_by_L2(info, surf));
1796 if (AddrSurfInfoIn.flags.color)
1797 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.surf.swizzle_mode));
1798 if (AddrSurfInfoIn.flags.display) {
1799 assert(is_dcc_supported_by_DCN(info, config, surf,
1800 surf->u.gfx9.dcc.rb_aligned,
1801 surf->u.gfx9.dcc.pipe_aligned));
1802 }
1803 }
1804
1805 if (info->has_graphics &&
1806 !compressed &&
1807 !config->is_3d &&
1808 config->info.levels == 1 &&
1809 AddrSurfInfoIn.flags.color &&
1810 !surf->is_linear &&
1811 surf->surf_alignment >= 64 * 1024 && /* 64KB tiling */
1812 !(surf->flags & (RADEON_SURF_DISABLE_DCC |
1813 RADEON_SURF_FORCE_SWIZZLE_MODE |
1814 RADEON_SURF_FORCE_MICRO_TILE_MODE))) {
1815 /* Validate that DCC is enabled if DCN can do it. */
1816 if ((info->use_display_dcc_unaligned ||
1817 info->use_display_dcc_with_retile_blit) &&
1818 AddrSurfInfoIn.flags.display &&
1819 surf->bpe == 4) {
1820 assert(surf->num_dcc_levels);
1821 }
1822
1823 /* Validate that non-scanout DCC is always enabled. */
1824 if (!AddrSurfInfoIn.flags.display)
1825 assert(surf->num_dcc_levels);
1826 }
1827
1828 if (!surf->htile_size) {
1829 /* Unset this if HTILE is not present. */
1830 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
1831 }
1832
1833 switch (surf->u.gfx9.surf.swizzle_mode) {
1834 /* S = standard. */
1835 case ADDR_SW_256B_S:
1836 case ADDR_SW_4KB_S:
1837 case ADDR_SW_64KB_S:
1838 case ADDR_SW_64KB_S_T:
1839 case ADDR_SW_4KB_S_X:
1840 case ADDR_SW_64KB_S_X:
1841 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
1842 break;
1843
1844 /* D = display. */
1845 case ADDR_SW_LINEAR:
1846 case ADDR_SW_256B_D:
1847 case ADDR_SW_4KB_D:
1848 case ADDR_SW_64KB_D:
1849 case ADDR_SW_64KB_D_T:
1850 case ADDR_SW_4KB_D_X:
1851 case ADDR_SW_64KB_D_X:
1852 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1853 break;
1854
1855 /* R = rotated (gfx9), render target (gfx10). */
1856 case ADDR_SW_256B_R:
1857 case ADDR_SW_4KB_R:
1858 case ADDR_SW_64KB_R:
1859 case ADDR_SW_64KB_R_T:
1860 case ADDR_SW_4KB_R_X:
1861 case ADDR_SW_64KB_R_X:
1862 case ADDR_SW_VAR_R_X:
1863 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1864 * used at the same time. We currently do not use rotated
1865 * in gfx9.
1866 */
1867 assert(info->chip_class >= GFX10 ||
1868 !"rotate micro tile mode is unsupported");
1869 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
1870 break;
1871
1872 /* Z = depth. */
1873 case ADDR_SW_4KB_Z:
1874 case ADDR_SW_64KB_Z:
1875 case ADDR_SW_64KB_Z_T:
1876 case ADDR_SW_4KB_Z_X:
1877 case ADDR_SW_64KB_Z_X:
1878 case ADDR_SW_VAR_Z_X:
1879 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1880 break;
1881
1882 default:
1883 assert(0);
1884 }
1885
1886 return 0;
1887
1888 error:
1889 free(surf->u.gfx9.dcc_retile_map);
1890 surf->u.gfx9.dcc_retile_map = NULL;
1891 return r;
1892 }
1893
1894 int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info,
1895 const struct ac_surf_config *config,
1896 enum radeon_surf_mode mode,
1897 struct radeon_surf *surf)
1898 {
1899 int r;
1900
1901 r = surf_config_sanity(config, surf->flags);
1902 if (r)
1903 return r;
1904
1905 if (info->chip_class >= GFX9)
1906 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
1907 else
1908 r = gfx6_compute_surface(addrlib->handle, info, config, mode, surf);
1909
1910 if (r)
1911 return r;
1912
1913 /* Determine the memory layout of multiple allocations in one buffer. */
1914 surf->total_size = surf->surf_size;
1915 surf->alignment = surf->surf_alignment;
1916
1917 if (surf->htile_size) {
1918 surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
1919 surf->total_size = surf->htile_offset + surf->htile_size;
1920 surf->alignment = MAX2(surf->alignment, surf->htile_alignment);
1921 }
1922
1923 if (surf->fmask_size) {
1924 assert(config->info.samples >= 2);
1925 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
1926 surf->total_size = surf->fmask_offset + surf->fmask_size;
1927 surf->alignment = MAX2(surf->alignment, surf->fmask_alignment);
1928 }
1929
1930 /* Single-sample CMASK is in a separate buffer. */
1931 if (surf->cmask_size && config->info.samples >= 2) {
1932 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
1933 surf->total_size = surf->cmask_offset + surf->cmask_size;
1934 surf->alignment = MAX2(surf->alignment, surf->cmask_alignment);
1935 }
1936
1937 if (surf->is_displayable)
1938 surf->flags |= RADEON_SURF_SCANOUT;
1939
1940 if (surf->dcc_size &&
1941 /* dcc_size is computed on GFX9+ only if it's displayable. */
1942 (info->chip_class >= GFX9 || !get_display_flag(config, surf))) {
1943 /* It's better when displayable DCC is immediately after
1944 * the image due to hw-specific reasons.
1945 */
1946 if (info->chip_class >= GFX9 &&
1947 surf->u.gfx9.dcc_retile_num_elements) {
1948 /* Add space for the displayable DCC buffer. */
1949 surf->display_dcc_offset =
1950 align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
1951 surf->total_size = surf->display_dcc_offset +
1952 surf->u.gfx9.display_dcc_size;
1953
1954 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1955 surf->dcc_retile_map_offset =
1956 align64(surf->total_size, info->tcc_cache_line_size);
1957
1958 if (surf->u.gfx9.dcc_retile_use_uint16) {
1959 surf->total_size = surf->dcc_retile_map_offset +
1960 surf->u.gfx9.dcc_retile_num_elements * 2;
1961 } else {
1962 surf->total_size = surf->dcc_retile_map_offset +
1963 surf->u.gfx9.dcc_retile_num_elements * 4;
1964 }
1965 }
1966
1967 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
1968 surf->total_size = surf->dcc_offset + surf->dcc_size;
1969 surf->alignment = MAX2(surf->alignment, surf->dcc_alignment);
1970 }
1971
1972 return 0;
1973 }
1974
1975 /* This is meant to be used for disabling DCC. */
1976 void ac_surface_zero_dcc_fields(struct radeon_surf *surf)
1977 {
1978 surf->dcc_offset = 0;
1979 surf->display_dcc_offset = 0;
1980 surf->dcc_retile_map_offset = 0;
1981 }
1982
1983 static unsigned eg_tile_split(unsigned tile_split)
1984 {
1985 switch (tile_split) {
1986 case 0: tile_split = 64; break;
1987 case 1: tile_split = 128; break;
1988 case 2: tile_split = 256; break;
1989 case 3: tile_split = 512; break;
1990 default:
1991 case 4: tile_split = 1024; break;
1992 case 5: tile_split = 2048; break;
1993 case 6: tile_split = 4096; break;
1994 }
1995 return tile_split;
1996 }
1997
1998 static unsigned eg_tile_split_rev(unsigned eg_tile_split)
1999 {
2000 switch (eg_tile_split) {
2001 case 64: return 0;
2002 case 128: return 1;
2003 case 256: return 2;
2004 case 512: return 3;
2005 default:
2006 case 1024: return 4;
2007 case 2048: return 5;
2008 case 4096: return 6;
2009 }
2010 }
2011
2012 #define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_SHIFT 45
2013 #define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_MASK 0x3
2014
2015 /* This should be called before ac_compute_surface. */
2016 void ac_surface_set_bo_metadata(const struct radeon_info *info,
2017 struct radeon_surf *surf, uint64_t tiling_flags,
2018 enum radeon_surf_mode *mode)
2019 {
2020 bool scanout;
2021
2022 if (info->chip_class >= GFX9) {
2023 surf->u.gfx9.surf.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2024 surf->u.gfx9.dcc.independent_64B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B);
2025 surf->u.gfx9.dcc.independent_128B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_128B);
2026 surf->u.gfx9.dcc.max_compressed_block_size = AMDGPU_TILING_GET(tiling_flags, DCC_MAX_COMPRESSED_BLOCK_SIZE);
2027 surf->u.gfx9.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
2028 scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT);
2029 *mode = surf->u.gfx9.surf.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED;
2030 } else {
2031 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2032 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2033 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2034 surf->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
2035 surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2036 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2037 scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
2038
2039 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
2040 *mode = RADEON_SURF_MODE_2D;
2041 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
2042 *mode = RADEON_SURF_MODE_1D;
2043 else
2044 *mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
2045 }
2046
2047 if (scanout)
2048 surf->flags |= RADEON_SURF_SCANOUT;
2049 else
2050 surf->flags &= ~RADEON_SURF_SCANOUT;
2051 }
2052
2053 void ac_surface_get_bo_metadata(const struct radeon_info *info,
2054 struct radeon_surf *surf, uint64_t *tiling_flags)
2055 {
2056 *tiling_flags = 0;
2057
2058 if (info->chip_class >= GFX9) {
2059 uint64_t dcc_offset = 0;
2060
2061 if (surf->dcc_offset) {
2062 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset
2063 : surf->dcc_offset;
2064 assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24));
2065 }
2066
2067 *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.surf.swizzle_mode);
2068 *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8);
2069 *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.display_dcc_pitch_max);
2070 *tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.dcc.independent_64B_blocks);
2071 *tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.dcc.independent_128B_blocks);
2072 *tiling_flags |= AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, surf->u.gfx9.dcc.max_compressed_block_size);
2073 *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0);
2074 } else {
2075 if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D)
2076 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
2077 else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D)
2078 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
2079 else
2080 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
2081
2082 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config);
2083 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw));
2084 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh));
2085 if (surf->u.legacy.tile_split)
2086 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(surf->u.legacy.tile_split));
2087 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea));
2088 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks)-1);
2089
2090 if (surf->flags & RADEON_SURF_SCANOUT)
2091 *tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
2092 else
2093 *tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
2094 }
2095 }
2096
2097 static uint32_t ac_get_umd_metadata_word1(const struct radeon_info *info)
2098 {
2099 return (ATI_VENDOR_ID << 16) | info->pci_id;
2100 }
2101
2102 /* This should be called after ac_compute_surface. */
2103 bool ac_surface_set_umd_metadata(const struct radeon_info *info,
2104 struct radeon_surf *surf,
2105 unsigned num_storage_samples,
2106 unsigned num_mipmap_levels,
2107 unsigned size_metadata,
2108 uint32_t metadata[64])
2109 {
2110 uint32_t *desc = &metadata[2];
2111 uint64_t offset;
2112
2113 if (info->chip_class >= GFX9)
2114 offset = surf->u.gfx9.surf_offset;
2115 else
2116 offset = surf->u.legacy.level[0].offset;
2117
2118 if (offset || /* Non-zero planes ignore metadata. */
2119 size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */
2120 metadata[0] == 0 || /* invalid version number */
2121 metadata[1] != ac_get_umd_metadata_word1(info)) /* invalid PCI ID */ {
2122 /* Disable DCC because it might not be enabled. */
2123 ac_surface_zero_dcc_fields(surf);
2124
2125 /* Don't report an error if the texture comes from an incompatible driver,
2126 * but this might not work.
2127 */
2128 return true;
2129 }
2130
2131 /* Validate that sample counts and the number of mipmap levels match. */
2132 unsigned desc_last_level = G_008F1C_LAST_LEVEL(desc[3]);
2133 unsigned type = G_008F1C_TYPE(desc[3]);
2134
2135 if (type == V_008F1C_SQ_RSRC_IMG_2D_MSAA || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2136 unsigned log_samples = util_logbase2(MAX2(1, num_storage_samples));
2137
2138 if (desc_last_level != log_samples) {
2139 fprintf(stderr,
2140 "amdgpu: invalid MSAA texture import, "
2141 "metadata has log2(samples) = %u, the caller set %u\n",
2142 desc_last_level, log_samples);
2143 return false;
2144 }
2145 } else {
2146 if (desc_last_level != num_mipmap_levels - 1) {
2147 fprintf(stderr,
2148 "amdgpu: invalid mipmapped texture import, "
2149 "metadata has last_level = %u, the caller set %u\n",
2150 desc_last_level, num_mipmap_levels - 1);
2151 return false;
2152 }
2153 }
2154
2155 if (info->chip_class >= GFX8 && G_008F28_COMPRESSION_EN(desc[6])) {
2156 /* Read DCC information. */
2157 switch (info->chip_class) {
2158 case GFX8:
2159 surf->dcc_offset = (uint64_t)desc[7] << 8;
2160 break;
2161
2162 case GFX9:
2163 surf->dcc_offset =
2164 ((uint64_t)desc[7] << 8) | ((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40);
2165 surf->u.gfx9.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]);
2166 surf->u.gfx9.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]);
2167
2168 /* If DCC is unaligned, this can only be a displayable image. */
2169 if (!surf->u.gfx9.dcc.pipe_aligned && !surf->u.gfx9.dcc.rb_aligned)
2170 assert(surf->is_displayable);
2171 break;
2172
2173 case GFX10:
2174 case GFX10_3:
2175 surf->dcc_offset =
2176 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | ((uint64_t)desc[7] << 16);
2177 surf->u.gfx9.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
2178 break;
2179
2180 default:
2181 assert(0);
2182 return false;
2183 }
2184 } else {
2185 /* Disable DCC. dcc_offset is always set by texture_from_handle
2186 * and must be cleared here.
2187 */
2188 ac_surface_zero_dcc_fields(surf);
2189 }
2190
2191 return true;
2192 }
2193
2194 void ac_surface_get_umd_metadata(const struct radeon_info *info,
2195 struct radeon_surf *surf,
2196 unsigned num_mipmap_levels,
2197 uint32_t desc[8],
2198 unsigned *size_metadata, uint32_t metadata[64])
2199 {
2200 /* Clear the base address and set the relative DCC offset. */
2201 desc[0] = 0;
2202 desc[1] &= C_008F14_BASE_ADDRESS_HI;
2203
2204 switch (info->chip_class) {
2205 case GFX6:
2206 case GFX7:
2207 break;
2208 case GFX8:
2209 desc[7] = surf->dcc_offset >> 8;
2210 break;
2211 case GFX9:
2212 desc[7] = surf->dcc_offset >> 8;
2213 desc[5] &= C_008F24_META_DATA_ADDRESS;
2214 desc[5] |= S_008F24_META_DATA_ADDRESS(surf->dcc_offset >> 40);
2215 break;
2216 case GFX10:
2217 case GFX10_3:
2218 desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
2219 desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->dcc_offset >> 8);
2220 desc[7] = surf->dcc_offset >> 16;
2221 break;
2222 default:
2223 assert(0);
2224 }
2225
2226 /* Metadata image format format version 1:
2227 * [0] = 1 (metadata format identifier)
2228 * [1] = (VENDOR_ID << 16) | PCI_ID
2229 * [2:9] = image descriptor for the whole resource
2230 * [2] is always 0, because the base address is cleared
2231 * [9] is the DCC offset bits [39:8] from the beginning of
2232 * the buffer
2233 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
2234 */
2235
2236 metadata[0] = 1; /* metadata image format version 1 */
2237
2238 /* Tiling modes are ambiguous without a PCI ID. */
2239 metadata[1] = ac_get_umd_metadata_word1(info);
2240
2241 /* Dwords [2:9] contain the image descriptor. */
2242 memcpy(&metadata[2], desc, 8 * 4);
2243 *size_metadata = 10 * 4;
2244
2245 /* Dwords [10:..] contain the mipmap level offsets. */
2246 if (info->chip_class <= GFX8) {
2247 for (unsigned i = 0; i < num_mipmap_levels; i++)
2248 metadata[10 + i] = surf->u.legacy.level[i].offset >> 8;
2249
2250 *size_metadata += num_mipmap_levels * 4;
2251 }
2252 }
2253
2254 void ac_surface_override_offset_stride(const struct radeon_info *info,
2255 struct radeon_surf *surf,
2256 unsigned num_mipmap_levels,
2257 uint64_t offset, unsigned pitch)
2258 {
2259 if (info->chip_class >= GFX9) {
2260 if (pitch) {
2261 surf->u.gfx9.surf_pitch = pitch;
2262 if (num_mipmap_levels == 1)
2263 surf->u.gfx9.surf.epitch = pitch - 1;
2264 surf->u.gfx9.surf_slice_size =
2265 (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
2266 }
2267 surf->u.gfx9.surf_offset = offset;
2268 if (surf->u.gfx9.stencil_offset)
2269 surf->u.gfx9.stencil_offset += offset;
2270 } else {
2271 if (pitch) {
2272 surf->u.legacy.level[0].nblk_x = pitch;
2273 surf->u.legacy.level[0].slice_size_dw =
2274 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
2275 }
2276
2277 if (offset) {
2278 for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
2279 surf->u.legacy.level[i].offset += offset;
2280 }
2281 }
2282
2283 if (surf->htile_offset)
2284 surf->htile_offset += offset;
2285 if (surf->fmask_offset)
2286 surf->fmask_offset += offset;
2287 if (surf->cmask_offset)
2288 surf->cmask_offset += offset;
2289 if (surf->dcc_offset)
2290 surf->dcc_offset += offset;
2291 if (surf->display_dcc_offset)
2292 surf->display_dcc_offset += offset;
2293 if (surf->dcc_retile_map_offset)
2294 surf->dcc_retile_map_offset += offset;
2295 }