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radv: clear FMASK layers instead of the whole buffer on GFX8
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 regValue.blockVarSizeLog2 = 0;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 if (config->is_3d)
211 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
212 else if (config->is_cube)
213 AddrSurfInfoIn->numSlices = 6;
214 else
215 AddrSurfInfoIn->numSlices = config->info.array_size;
216
217 if (level > 0) {
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
220 if (is_stencil)
221 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
222 else
223 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
224
225 /* Convert blocks to pixels for compressed formats. */
226 if (compressed)
227 AddrSurfInfoIn->basePitch *= surf->blk_w;
228 }
229
230 ret = AddrComputeSurfaceInfo(addrlib,
231 AddrSurfInfoIn,
232 AddrSurfInfoOut);
233 if (ret != ADDR_OK) {
234 return ret;
235 }
236
237 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
238 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
239 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
240 surf_level->nblk_x = AddrSurfInfoOut->pitch;
241 surf_level->nblk_y = AddrSurfInfoOut->height;
242
243 switch (AddrSurfInfoOut->tileMode) {
244 case ADDR_TM_LINEAR_ALIGNED:
245 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
246 break;
247 case ADDR_TM_1D_TILED_THIN1:
248 surf_level->mode = RADEON_SURF_MODE_1D;
249 break;
250 case ADDR_TM_2D_TILED_THIN1:
251 surf_level->mode = RADEON_SURF_MODE_2D;
252 break;
253 default:
254 assert(0);
255 }
256
257 if (is_stencil)
258 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
259 else
260 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
261
262 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
263
264 /* Clear DCC fields at the beginning. */
265 surf_level->dcc_offset = 0;
266
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn->flags.dccCompatible &&
269 (level == 0 || AddrDccOut->subLvlCompressible)) {
270 bool prev_level_clearable = level == 0 ||
271 AddrDccOut->dccRamSizeAligned;
272
273 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
274 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
275 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
276 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
277 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
278
279 ret = AddrComputeDccInfo(addrlib,
280 AddrDccIn,
281 AddrDccOut);
282
283 if (ret == ADDR_OK) {
284 surf_level->dcc_offset = surf->dcc_size;
285 surf->num_dcc_levels = level + 1;
286 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
287 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
288
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
292 *
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
296 *
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
299 */
300 if (AddrDccOut->dccRamSizeAligned ||
301 (prev_level_clearable && level == config->info.levels - 1))
302 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
303 else
304 surf_level->dcc_fast_clear_size = 0;
305 }
306 }
307
308 /* TC-compatible HTILE. */
309 if (!is_stencil &&
310 AddrSurfInfoIn->flags.depth &&
311 surf_level->mode == RADEON_SURF_MODE_2D &&
312 level == 0) {
313 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
314 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
315 AddrHtileIn->height = AddrSurfInfoOut->height;
316 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
317 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
318 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
319 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
320 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
321 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
322
323 ret = AddrComputeHtileInfo(addrlib,
324 AddrHtileIn,
325 AddrHtileOut);
326
327 if (ret == ADDR_OK) {
328 surf->htile_size = AddrHtileOut->htileBytes;
329 surf->htile_slice_size = AddrHtileOut->sliceSize;
330 surf->htile_alignment = AddrHtileOut->baseAlign;
331 }
332 }
333
334 return 0;
335 }
336
337 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
338 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
339 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
340
341 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
342 const struct radeon_info *info)
343 {
344 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
345
346 if (info->chip_class >= GFX7)
347 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
348 else
349 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
350 }
351
352 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
353 {
354 unsigned index, tileb;
355
356 tileb = 8 * 8 * surf->bpe;
357 tileb = MIN2(surf->u.legacy.tile_split, tileb);
358
359 for (index = 0; tileb > 64; index++)
360 tileb >>= 1;
361
362 assert(index < 16);
363 return index;
364 }
365
366 static bool get_display_flag(const struct ac_surf_config *config,
367 const struct radeon_surf *surf)
368 {
369 unsigned num_channels = config->info.num_channels;
370 unsigned bpe = surf->bpe;
371
372 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
373 surf->flags & RADEON_SURF_SCANOUT &&
374 config->info.samples <= 1 &&
375 surf->blk_w <= 2 && surf->blk_h == 1) {
376 /* subsampled */
377 if (surf->blk_w == 2 && surf->blk_h == 1)
378 return true;
379
380 if (/* RGBA8 or RGBA16F */
381 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
382 /* R5G6B5 or R5G5B5A1 */
383 (bpe == 2 && num_channels >= 3) ||
384 /* C8 palette */
385 (bpe == 1 && num_channels == 1))
386 return true;
387 }
388 return false;
389 }
390
391 /**
392 * This must be called after the first level is computed.
393 *
394 * Copy surface-global settings like pipe/bank config from level 0 surface
395 * computation, and compute tile swizzle.
396 */
397 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
398 const struct radeon_info *info,
399 const struct ac_surf_config *config,
400 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
401 struct radeon_surf *surf)
402 {
403 surf->surf_alignment = csio->baseAlign;
404 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
405 gfx6_set_micro_tile_mode(surf, info);
406
407 /* For 2D modes only. */
408 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
409 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
410 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
411 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
412 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
413 surf->u.legacy.num_banks = csio->pTileInfo->banks;
414 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
415 } else {
416 surf->u.legacy.macro_tile_index = 0;
417 }
418
419 /* Compute tile swizzle. */
420 /* TODO: fix tile swizzle with mipmapping for GFX6 */
421 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
422 config->info.surf_index &&
423 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
424 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
425 !get_display_flag(config, surf)) {
426 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
427 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
428
429 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
430 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
431
432 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
433 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
434 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
435 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
436 AddrBaseSwizzleIn.tileMode = csio->tileMode;
437
438 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
439 &AddrBaseSwizzleOut);
440 if (r != ADDR_OK)
441 return r;
442
443 assert(AddrBaseSwizzleOut.tileSwizzle <=
444 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
445 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
446 }
447 return 0;
448 }
449
450 static void ac_compute_cmask(const struct radeon_info *info,
451 const struct ac_surf_config *config,
452 struct radeon_surf *surf)
453 {
454 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
455 unsigned num_pipes = info->num_tile_pipes;
456 unsigned cl_width, cl_height;
457
458 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
459 return;
460
461 assert(info->chip_class <= GFX8);
462
463 switch (num_pipes) {
464 case 2:
465 cl_width = 32;
466 cl_height = 16;
467 break;
468 case 4:
469 cl_width = 32;
470 cl_height = 32;
471 break;
472 case 8:
473 cl_width = 64;
474 cl_height = 32;
475 break;
476 case 16: /* Hawaii */
477 cl_width = 64;
478 cl_height = 64;
479 break;
480 default:
481 assert(0);
482 return;
483 }
484
485 unsigned base_align = num_pipes * pipe_interleave_bytes;
486
487 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
488 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
489 unsigned slice_elements = (width * height) / (8*8);
490
491 /* Each element of CMASK is a nibble. */
492 unsigned slice_bytes = slice_elements / 2;
493
494 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
495 if (surf->u.legacy.cmask_slice_tile_max)
496 surf->u.legacy.cmask_slice_tile_max -= 1;
497
498 unsigned num_layers;
499 if (config->is_3d)
500 num_layers = config->info.depth;
501 else if (config->is_cube)
502 num_layers = 6;
503 else
504 num_layers = config->info.array_size;
505
506 surf->cmask_alignment = MAX2(256, base_align);
507 surf->cmask_size = align(slice_bytes, base_align) * num_layers;
508 }
509
510 /**
511 * Fill in the tiling information in \p surf based on the given surface config.
512 *
513 * The following fields of \p surf must be initialized by the caller:
514 * blk_w, blk_h, bpe, flags.
515 */
516 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
517 const struct radeon_info *info,
518 const struct ac_surf_config *config,
519 enum radeon_surf_mode mode,
520 struct radeon_surf *surf)
521 {
522 unsigned level;
523 bool compressed;
524 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
525 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
526 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
527 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
528 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
529 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
530 ADDR_TILEINFO AddrTileInfoIn = {0};
531 ADDR_TILEINFO AddrTileInfoOut = {0};
532 int r;
533
534 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
535 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
536 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
537 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
538 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
539 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
540 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
541
542 compressed = surf->blk_w == 4 && surf->blk_h == 4;
543
544 /* MSAA requires 2D tiling. */
545 if (config->info.samples > 1)
546 mode = RADEON_SURF_MODE_2D;
547
548 /* DB doesn't support linear layouts. */
549 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
550 mode < RADEON_SURF_MODE_1D)
551 mode = RADEON_SURF_MODE_1D;
552
553 /* Set the requested tiling mode. */
554 switch (mode) {
555 case RADEON_SURF_MODE_LINEAR_ALIGNED:
556 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
557 break;
558 case RADEON_SURF_MODE_1D:
559 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
560 break;
561 case RADEON_SURF_MODE_2D:
562 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
563 break;
564 default:
565 assert(0);
566 }
567
568 /* The format must be set correctly for the allocation of compressed
569 * textures to work. In other cases, setting the bpp is sufficient.
570 */
571 if (compressed) {
572 switch (surf->bpe) {
573 case 8:
574 AddrSurfInfoIn.format = ADDR_FMT_BC1;
575 break;
576 case 16:
577 AddrSurfInfoIn.format = ADDR_FMT_BC3;
578 break;
579 default:
580 assert(0);
581 }
582 }
583 else {
584 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
585 }
586
587 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
588 MAX2(1, config->info.samples);
589 AddrSurfInfoIn.tileIndex = -1;
590
591 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
592 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
593 MAX2(1, config->info.storage_samples);
594 }
595
596 /* Set the micro tile type. */
597 if (surf->flags & RADEON_SURF_SCANOUT)
598 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
599 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
600 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
601 else
602 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
603
604 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
605 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
606 AddrSurfInfoIn.flags.cube = config->is_cube;
607 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
608 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
609 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
610
611 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
612 * requested, because TC-compatible HTILE requires 2D tiling.
613 */
614 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
615 !AddrSurfInfoIn.flags.fmask &&
616 config->info.samples <= 1 &&
617 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
618
619 /* DCC notes:
620 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
621 * with samples >= 4.
622 * - Mipmapped array textures have low performance (discovered by a closed
623 * driver team).
624 */
625 AddrSurfInfoIn.flags.dccCompatible =
626 info->chip_class >= GFX8 &&
627 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
628 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
629 !compressed &&
630 ((config->info.array_size == 1 && config->info.depth == 1) ||
631 config->info.levels == 1);
632
633 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
634 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
635
636 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
637 * for Z and stencil. This can cause a number of problems which we work
638 * around here:
639 *
640 * - a depth part that is incompatible with mipmapped texturing
641 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
642 * incorrect tiling applied to the stencil part, stencil buffer
643 * memory accesses that go out of bounds) even without mipmapping
644 *
645 * Some piglit tests that are prone to different types of related
646 * failures:
647 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
648 * ./bin/framebuffer-blit-levels {draw,read} stencil
649 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
650 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
651 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
652 */
653 int stencil_tile_idx = -1;
654
655 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
656 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
657 /* Compute stencilTileIdx that is compatible with the (depth)
658 * tileIdx. This degrades the depth surface if necessary to
659 * ensure that a matching stencilTileIdx exists. */
660 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
661
662 /* Keep the depth mip-tail compatible with texturing. */
663 AddrSurfInfoIn.flags.noStencil = 1;
664 }
665
666 /* Set preferred macrotile parameters. This is usually required
667 * for shared resources. This is for 2D tiling only. */
668 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
669 surf->u.legacy.bankw && surf->u.legacy.bankh &&
670 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
671 /* If any of these parameters are incorrect, the calculation
672 * will fail. */
673 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
674 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
675 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
676 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
677 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
678 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
679 AddrSurfInfoIn.flags.opt4Space = 0;
680 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
681
682 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
683 * the tile index, because we are expected to know it if
684 * we know the other parameters.
685 *
686 * This is something that can easily be fixed in Addrlib.
687 * For now, just figure it out here.
688 * Note that only 2D_TILE_THIN1 is handled here.
689 */
690 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
691 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
692
693 if (info->chip_class == GFX6) {
694 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
695 if (surf->bpe == 2)
696 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
697 else
698 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
699 } else {
700 if (surf->bpe == 1)
701 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
702 else if (surf->bpe == 2)
703 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
704 else if (surf->bpe == 4)
705 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
706 else
707 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
708 }
709 } else {
710 /* GFX7 - GFX8 */
711 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
712 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
713 else
714 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
715
716 /* Addrlib doesn't set this if tileIndex is forced like above. */
717 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
718 }
719 }
720
721 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
722 surf->num_dcc_levels = 0;
723 surf->surf_size = 0;
724 surf->dcc_size = 0;
725 surf->dcc_alignment = 1;
726 surf->htile_size = 0;
727 surf->htile_slice_size = 0;
728 surf->htile_alignment = 1;
729
730 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
731 !(surf->flags & RADEON_SURF_ZBUFFER);
732
733 /* Calculate texture layout information. */
734 if (!only_stencil) {
735 for (level = 0; level < config->info.levels; level++) {
736 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
737 &AddrSurfInfoIn, &AddrSurfInfoOut,
738 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
739 if (r)
740 return r;
741
742 if (level > 0)
743 continue;
744
745 /* Check that we actually got a TC-compatible HTILE if
746 * we requested it (only for level 0, since we're not
747 * supporting HTILE on higher mip levels anyway). */
748 assert(AddrSurfInfoOut.tcCompatible ||
749 !AddrSurfInfoIn.flags.tcCompatible ||
750 AddrSurfInfoIn.flags.matchStencilTileCfg);
751
752 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
753 if (!AddrSurfInfoOut.tcCompatible) {
754 AddrSurfInfoIn.flags.tcCompatible = 0;
755 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
756 }
757
758 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
759 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
760 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
761
762 assert(stencil_tile_idx >= 0);
763 }
764
765 r = gfx6_surface_settings(addrlib, info, config,
766 &AddrSurfInfoOut, surf);
767 if (r)
768 return r;
769 }
770 }
771
772 /* Calculate texture layout information for stencil. */
773 if (surf->flags & RADEON_SURF_SBUFFER) {
774 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
775 AddrSurfInfoIn.bpp = 8;
776 AddrSurfInfoIn.flags.depth = 0;
777 AddrSurfInfoIn.flags.stencil = 1;
778 AddrSurfInfoIn.flags.tcCompatible = 0;
779 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
780 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
781
782 for (level = 0; level < config->info.levels; level++) {
783 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
784 &AddrSurfInfoIn, &AddrSurfInfoOut,
785 &AddrDccIn, &AddrDccOut,
786 NULL, NULL);
787 if (r)
788 return r;
789
790 /* DB uses the depth pitch for both stencil and depth. */
791 if (!only_stencil) {
792 if (surf->u.legacy.stencil_level[level].nblk_x !=
793 surf->u.legacy.level[level].nblk_x)
794 surf->u.legacy.stencil_adjusted = true;
795 } else {
796 surf->u.legacy.level[level].nblk_x =
797 surf->u.legacy.stencil_level[level].nblk_x;
798 }
799
800 if (level == 0) {
801 if (only_stencil) {
802 r = gfx6_surface_settings(addrlib, info, config,
803 &AddrSurfInfoOut, surf);
804 if (r)
805 return r;
806 }
807
808 /* For 2D modes only. */
809 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
810 surf->u.legacy.stencil_tile_split =
811 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
812 }
813 }
814 }
815 }
816
817 /* Compute FMASK. */
818 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
819 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
820 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
821 ADDR_TILEINFO fmask_tile_info = {};
822
823 fin.size = sizeof(fin);
824 fout.size = sizeof(fout);
825
826 fin.tileMode = AddrSurfInfoOut.tileMode;
827 fin.pitch = AddrSurfInfoOut.pitch;
828 fin.height = config->info.height;
829 fin.numSlices = AddrSurfInfoIn.numSlices;
830 fin.numSamples = AddrSurfInfoIn.numSamples;
831 fin.numFrags = AddrSurfInfoIn.numFrags;
832 fin.tileIndex = -1;
833 fout.pTileInfo = &fmask_tile_info;
834
835 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
836 if (r)
837 return r;
838
839 surf->fmask_size = fout.fmaskBytes;
840 surf->fmask_alignment = fout.baseAlign;
841 surf->fmask_tile_swizzle = 0;
842
843 surf->u.legacy.fmask.slice_tile_max =
844 (fout.pitch * fout.height) / 64;
845 if (surf->u.legacy.fmask.slice_tile_max)
846 surf->u.legacy.fmask.slice_tile_max -= 1;
847
848 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
849 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
850 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
851 surf->u.legacy.fmask.slice_size = fout.sliceSize;
852
853 /* Compute tile swizzle for FMASK. */
854 if (config->info.fmask_surf_index &&
855 !(surf->flags & RADEON_SURF_SHAREABLE)) {
856 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
857 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
858
859 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
860 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
861
862 /* This counter starts from 1 instead of 0. */
863 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
864 xin.tileIndex = fout.tileIndex;
865 xin.macroModeIndex = fout.macroModeIndex;
866 xin.pTileInfo = fout.pTileInfo;
867 xin.tileMode = fin.tileMode;
868
869 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
870 if (r != ADDR_OK)
871 return r;
872
873 assert(xout.tileSwizzle <=
874 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
875 surf->fmask_tile_swizzle = xout.tileSwizzle;
876 }
877 }
878
879 /* Recalculate the whole DCC miptree size including disabled levels.
880 * This is what addrlib does, but calling addrlib would be a lot more
881 * complicated.
882 */
883 if (surf->dcc_size && config->info.levels > 1) {
884 /* The smallest miplevels that are never compressed by DCC
885 * still read the DCC buffer via TC if the base level uses DCC,
886 * and for some reason the DCC buffer needs to be larger if
887 * the miptree uses non-zero tile_swizzle. Otherwise there are
888 * VM faults.
889 *
890 * "dcc_alignment * 4" was determined by trial and error.
891 */
892 surf->dcc_size = align64(surf->surf_size >> 8,
893 surf->dcc_alignment * 4);
894 }
895
896 /* Make sure HTILE covers the whole miptree, because the shader reads
897 * TC-compatible HTILE even for levels where it's disabled by DB.
898 */
899 if (surf->htile_size && config->info.levels > 1 &&
900 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
901 /* MSAA can't occur with levels > 1, so ignore the sample count. */
902 const unsigned total_pixels = surf->surf_size / surf->bpe;
903 const unsigned htile_block_size = 8 * 8;
904 const unsigned htile_element_size = 4;
905
906 surf->htile_size = (total_pixels / htile_block_size) *
907 htile_element_size;
908 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
909 }
910
911 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
912 surf->is_displayable = surf->is_linear ||
913 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
914 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
915
916 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
917 * used at the same time. This case is not currently expected to occur
918 * because we don't use rotated. Enforce this restriction on all chips
919 * to facilitate testing.
920 */
921 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
922 assert(!"rotate micro tile mode is unsupported");
923 return ADDR_ERROR;
924 }
925
926 ac_compute_cmask(info, config, surf);
927 return 0;
928 }
929
930 /* This is only called when expecting a tiled layout. */
931 static int
932 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
933 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
934 bool is_fmask, AddrSwizzleMode *swizzle_mode)
935 {
936 ADDR_E_RETURNCODE ret;
937 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
938 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
939
940 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
941 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
942
943 sin.flags = in->flags;
944 sin.resourceType = in->resourceType;
945 sin.format = in->format;
946 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
947 /* TODO: We could allow some of these: */
948 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
949 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
950 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
951 sin.bpp = in->bpp;
952 sin.width = in->width;
953 sin.height = in->height;
954 sin.numSlices = in->numSlices;
955 sin.numMipLevels = in->numMipLevels;
956 sin.numSamples = in->numSamples;
957 sin.numFrags = in->numFrags;
958
959 if (is_fmask) {
960 sin.flags.display = 0;
961 sin.flags.color = 0;
962 sin.flags.fmask = 1;
963 }
964
965 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
966 if (ret != ADDR_OK)
967 return ret;
968
969 *swizzle_mode = sout.swizzleMode;
970 return 0;
971 }
972
973 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
974 const struct radeon_info *info,
975 const struct ac_surf_config *config,
976 struct radeon_surf *surf, bool compressed,
977 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
978 {
979 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
980 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
981 ADDR_E_RETURNCODE ret;
982
983 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
984 out.pMipInfo = mip_info;
985
986 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
987 if (ret != ADDR_OK)
988 return ret;
989
990 if (in->flags.stencil) {
991 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
992 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
993 out.mipChainPitch - 1;
994 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
995 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
996 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
997 return 0;
998 }
999
1000 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1001 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1002 out.mipChainPitch - 1;
1003
1004 /* CMASK fast clear uses these even if FMASK isn't allocated.
1005 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1006 */
1007 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1008 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1009
1010 surf->u.gfx9.surf_slice_size = out.sliceSize;
1011 surf->u.gfx9.surf_pitch = out.pitch;
1012 surf->u.gfx9.surf_height = out.height;
1013 surf->surf_size = out.surfSize;
1014 surf->surf_alignment = out.baseAlign;
1015
1016 if (in->swizzleMode == ADDR_SW_LINEAR) {
1017 for (unsigned i = 0; i < in->numMipLevels; i++)
1018 surf->u.gfx9.offset[i] = mip_info[i].offset;
1019 }
1020
1021 if (in->flags.depth) {
1022 assert(in->swizzleMode != ADDR_SW_LINEAR);
1023
1024 /* HTILE */
1025 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1026 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1027
1028 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1029 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1030
1031 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1032 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1033 hin.depthFlags = in->flags;
1034 hin.swizzleMode = in->swizzleMode;
1035 hin.unalignedWidth = in->width;
1036 hin.unalignedHeight = in->height;
1037 hin.numSlices = in->numSlices;
1038 hin.numMipLevels = in->numMipLevels;
1039 hin.firstMipIdInTail = out.firstMipIdInTail;
1040
1041 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1042 if (ret != ADDR_OK)
1043 return ret;
1044
1045 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1046 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1047 surf->htile_size = hout.htileBytes;
1048 surf->htile_slice_size = hout.sliceSize;
1049 surf->htile_alignment = hout.baseAlign;
1050 } else {
1051 /* Compute tile swizzle for the color surface.
1052 * All *_X and *_T modes can use the swizzle.
1053 */
1054 if (config->info.surf_index &&
1055 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1056 !out.mipChainInTail &&
1057 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1058 !in->flags.display) {
1059 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1060 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1061
1062 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1063 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1064
1065 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1066 xin.flags = in->flags;
1067 xin.swizzleMode = in->swizzleMode;
1068 xin.resourceType = in->resourceType;
1069 xin.format = in->format;
1070 xin.numSamples = in->numSamples;
1071 xin.numFrags = in->numFrags;
1072
1073 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1074 if (ret != ADDR_OK)
1075 return ret;
1076
1077 assert(xout.pipeBankXor <=
1078 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1079 surf->tile_swizzle = xout.pipeBankXor;
1080 }
1081
1082 /* DCC */
1083 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1084 !compressed &&
1085 in->swizzleMode != ADDR_SW_LINEAR) {
1086 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1087 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1088 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1089
1090 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1091 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1092 dout.pMipInfo = meta_mip_info;
1093
1094 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1095 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1096 din.colorFlags = in->flags;
1097 din.resourceType = in->resourceType;
1098 din.swizzleMode = in->swizzleMode;
1099 din.bpp = in->bpp;
1100 din.unalignedWidth = in->width;
1101 din.unalignedHeight = in->height;
1102 din.numSlices = in->numSlices;
1103 din.numFrags = in->numFrags;
1104 din.numMipLevels = in->numMipLevels;
1105 din.dataSurfaceSize = out.surfSize;
1106 din.firstMipIdInTail = out.firstMipIdInTail;
1107
1108 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1109 if (ret != ADDR_OK)
1110 return ret;
1111
1112 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1113 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1114 surf->dcc_size = dout.dccRamSize;
1115 surf->dcc_alignment = dout.dccRamBaseAlign;
1116 surf->num_dcc_levels = in->numMipLevels;
1117
1118 /* Disable DCC for levels that are in the mip tail.
1119 *
1120 * There are two issues that this is intended to
1121 * address:
1122 *
1123 * 1. Multiple mip levels may share a cache line. This
1124 * can lead to corruption when switching between
1125 * rendering to different mip levels because the
1126 * RBs don't maintain coherency.
1127 *
1128 * 2. Texturing with metadata after rendering sometimes
1129 * fails with corruption, probably for a similar
1130 * reason.
1131 *
1132 * Working around these issues for all levels in the
1133 * mip tail may be overly conservative, but it's what
1134 * Vulkan does.
1135 *
1136 * Alternative solutions that also work but are worse:
1137 * - Disable DCC entirely.
1138 * - Flush TC L2 after rendering.
1139 */
1140 for (unsigned i = 0; i < in->numMipLevels; i++) {
1141 if (meta_mip_info[i].inMiptail) {
1142 surf->num_dcc_levels = i;
1143 break;
1144 }
1145 }
1146
1147 if (!surf->num_dcc_levels)
1148 surf->dcc_size = 0;
1149
1150 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1151 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1152 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1153
1154 /* Compute displayable DCC. */
1155 if (in->flags.display &&
1156 surf->num_dcc_levels &&
1157 info->use_display_dcc_with_retile_blit) {
1158 /* Compute displayable DCC info. */
1159 din.dccKeyFlags.pipeAligned = 0;
1160 din.dccKeyFlags.rbAligned = 0;
1161
1162 assert(din.numSlices == 1);
1163 assert(din.numMipLevels == 1);
1164 assert(din.numFrags == 1);
1165 assert(surf->tile_swizzle == 0);
1166 assert(surf->u.gfx9.dcc.pipe_aligned ||
1167 surf->u.gfx9.dcc.rb_aligned);
1168
1169 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1170 if (ret != ADDR_OK)
1171 return ret;
1172
1173 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1174 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1175 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1176 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1177
1178 /* Compute address mapping from non-displayable to displayable DCC. */
1179 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1180 addrin.size = sizeof(addrin);
1181 addrin.colorFlags.color = 1;
1182 addrin.swizzleMode = din.swizzleMode;
1183 addrin.resourceType = din.resourceType;
1184 addrin.bpp = din.bpp;
1185 addrin.unalignedWidth = din.unalignedWidth;
1186 addrin.unalignedHeight = din.unalignedHeight;
1187 addrin.numSlices = 1;
1188 addrin.numMipLevels = 1;
1189 addrin.numFrags = 1;
1190
1191 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1192 addrout.size = sizeof(addrout);
1193
1194 surf->u.gfx9.dcc_retile_num_elements =
1195 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1196 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1197 /* Align the size to 4 (for the compute shader). */
1198 surf->u.gfx9.dcc_retile_num_elements =
1199 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1200
1201 surf->u.gfx9.dcc_retile_map =
1202 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1203 if (!surf->u.gfx9.dcc_retile_map)
1204 return ADDR_OUTOFMEMORY;
1205
1206 unsigned index = 0;
1207 surf->u.gfx9.dcc_retile_use_uint16 = true;
1208
1209 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1210 addrin.y = y;
1211
1212 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1213 addrin.x = x;
1214
1215 /* Compute src DCC address */
1216 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1217 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1218 addrout.addr = 0;
1219
1220 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1221 if (ret != ADDR_OK)
1222 return ret;
1223
1224 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1225 if (addrout.addr > USHRT_MAX)
1226 surf->u.gfx9.dcc_retile_use_uint16 = false;
1227
1228 /* Compute dst DCC address */
1229 addrin.dccKeyFlags.pipeAligned = 0;
1230 addrin.dccKeyFlags.rbAligned = 0;
1231 addrout.addr = 0;
1232
1233 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1234 if (ret != ADDR_OK)
1235 return ret;
1236
1237 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1238 if (addrout.addr > USHRT_MAX)
1239 surf->u.gfx9.dcc_retile_use_uint16 = false;
1240
1241 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1242 index++;
1243 }
1244 }
1245 /* Fill the remaining pairs with the last one (for the compute shader). */
1246 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1247 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1248 }
1249 }
1250
1251 /* FMASK */
1252 if (in->numSamples > 1) {
1253 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1254 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1255
1256 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1257 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1258
1259 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1260 true, &fin.swizzleMode);
1261 if (ret != ADDR_OK)
1262 return ret;
1263
1264 fin.unalignedWidth = in->width;
1265 fin.unalignedHeight = in->height;
1266 fin.numSlices = in->numSlices;
1267 fin.numSamples = in->numSamples;
1268 fin.numFrags = in->numFrags;
1269
1270 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1271 if (ret != ADDR_OK)
1272 return ret;
1273
1274 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1275 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1276 surf->fmask_size = fout.fmaskBytes;
1277 surf->fmask_alignment = fout.baseAlign;
1278
1279 /* Compute tile swizzle for the FMASK surface. */
1280 if (config->info.fmask_surf_index &&
1281 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1282 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1283 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1284 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1285
1286 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1287 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1288
1289 /* This counter starts from 1 instead of 0. */
1290 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1291 xin.flags = in->flags;
1292 xin.swizzleMode = fin.swizzleMode;
1293 xin.resourceType = in->resourceType;
1294 xin.format = in->format;
1295 xin.numSamples = in->numSamples;
1296 xin.numFrags = in->numFrags;
1297
1298 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1299 if (ret != ADDR_OK)
1300 return ret;
1301
1302 assert(xout.pipeBankXor <=
1303 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1304 surf->fmask_tile_swizzle = xout.pipeBankXor;
1305 }
1306 }
1307
1308 /* CMASK */
1309 if (in->swizzleMode != ADDR_SW_LINEAR) {
1310 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1311 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1312
1313 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1314 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1315
1316 if (in->numSamples > 1) {
1317 /* FMASK is always aligned. */
1318 cin.cMaskFlags.pipeAligned = 1;
1319 cin.cMaskFlags.rbAligned = 1;
1320 } else {
1321 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1322 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1323 }
1324 cin.colorFlags = in->flags;
1325 cin.resourceType = in->resourceType;
1326 cin.unalignedWidth = in->width;
1327 cin.unalignedHeight = in->height;
1328 cin.numSlices = in->numSlices;
1329
1330 if (in->numSamples > 1)
1331 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1332 else
1333 cin.swizzleMode = in->swizzleMode;
1334
1335 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1336 if (ret != ADDR_OK)
1337 return ret;
1338
1339 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1340 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1341 surf->cmask_size = cout.cmaskBytes;
1342 surf->cmask_alignment = cout.baseAlign;
1343 }
1344 }
1345
1346 return 0;
1347 }
1348
1349 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1350 const struct radeon_info *info,
1351 const struct ac_surf_config *config,
1352 enum radeon_surf_mode mode,
1353 struct radeon_surf *surf)
1354 {
1355 bool compressed;
1356 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1357 int r;
1358
1359 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1360
1361 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1362
1363 /* The format must be set correctly for the allocation of compressed
1364 * textures to work. In other cases, setting the bpp is sufficient. */
1365 if (compressed) {
1366 switch (surf->bpe) {
1367 case 8:
1368 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1369 break;
1370 case 16:
1371 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1372 break;
1373 default:
1374 assert(0);
1375 }
1376 } else {
1377 switch (surf->bpe) {
1378 case 1:
1379 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1380 AddrSurfInfoIn.format = ADDR_FMT_8;
1381 break;
1382 case 2:
1383 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1384 !(surf->flags & RADEON_SURF_SBUFFER));
1385 AddrSurfInfoIn.format = ADDR_FMT_16;
1386 break;
1387 case 4:
1388 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1389 !(surf->flags & RADEON_SURF_SBUFFER));
1390 AddrSurfInfoIn.format = ADDR_FMT_32;
1391 break;
1392 case 8:
1393 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1394 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1395 break;
1396 case 12:
1397 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1398 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1399 break;
1400 case 16:
1401 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1402 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1403 break;
1404 default:
1405 assert(0);
1406 }
1407 AddrSurfInfoIn.bpp = surf->bpe * 8;
1408 }
1409
1410 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1411 AddrSurfInfoIn.flags.color = is_color_surface &&
1412 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1413 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1414 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1415 /* flags.texture currently refers to TC-compatible HTILE */
1416 AddrSurfInfoIn.flags.texture = is_color_surface ||
1417 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1418 AddrSurfInfoIn.flags.opt4space = 1;
1419
1420 AddrSurfInfoIn.numMipLevels = config->info.levels;
1421 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1422 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1423
1424 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1425 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1426
1427 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1428 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1429 * must sample 1D textures as 2D. */
1430 if (config->is_3d)
1431 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1432 else
1433 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1434
1435 AddrSurfInfoIn.width = config->info.width;
1436 AddrSurfInfoIn.height = config->info.height;
1437
1438 if (config->is_3d)
1439 AddrSurfInfoIn.numSlices = config->info.depth;
1440 else if (config->is_cube)
1441 AddrSurfInfoIn.numSlices = 6;
1442 else
1443 AddrSurfInfoIn.numSlices = config->info.array_size;
1444
1445 /* This is propagated to HTILE/DCC/CMASK. */
1446 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1447 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1448
1449 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1450 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1451 *
1452 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1453 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1454 * after rendering, so PIPE_ALIGNED=1 is recommended.
1455 */
1456 if (info->use_display_dcc_unaligned && is_color_surface &&
1457 AddrSurfInfoIn.flags.display) {
1458 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1459 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1460 }
1461
1462 switch (mode) {
1463 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1464 assert(config->info.samples <= 1);
1465 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1466 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1467 break;
1468
1469 case RADEON_SURF_MODE_1D:
1470 case RADEON_SURF_MODE_2D:
1471 if (surf->flags & RADEON_SURF_IMPORTED) {
1472 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1473 break;
1474 }
1475
1476 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1477 false, &AddrSurfInfoIn.swizzleMode);
1478 if (r)
1479 return r;
1480 break;
1481
1482 default:
1483 assert(0);
1484 }
1485
1486 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1487 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1488
1489 surf->num_dcc_levels = 0;
1490 surf->surf_size = 0;
1491 surf->fmask_size = 0;
1492 surf->dcc_size = 0;
1493 surf->htile_size = 0;
1494 surf->htile_slice_size = 0;
1495 surf->u.gfx9.surf_offset = 0;
1496 surf->u.gfx9.stencil_offset = 0;
1497 surf->cmask_size = 0;
1498 surf->u.gfx9.dcc_retile_use_uint16 = false;
1499 surf->u.gfx9.dcc_retile_num_elements = 0;
1500 surf->u.gfx9.dcc_retile_map = NULL;
1501
1502 /* Calculate texture layout information. */
1503 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1504 &AddrSurfInfoIn);
1505 if (r)
1506 goto error;
1507
1508 /* Calculate texture layout information for stencil. */
1509 if (surf->flags & RADEON_SURF_SBUFFER) {
1510 AddrSurfInfoIn.flags.stencil = 1;
1511 AddrSurfInfoIn.bpp = 8;
1512 AddrSurfInfoIn.format = ADDR_FMT_8;
1513
1514 if (!AddrSurfInfoIn.flags.depth) {
1515 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1516 false, &AddrSurfInfoIn.swizzleMode);
1517 if (r)
1518 goto error;
1519 } else
1520 AddrSurfInfoIn.flags.depth = 0;
1521
1522 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1523 &AddrSurfInfoIn);
1524 if (r)
1525 goto error;
1526 }
1527
1528 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1529
1530 /* Query whether the surface is displayable. */
1531 bool displayable = false;
1532 if (!config->is_3d && !config->is_cube) {
1533 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1534 surf->bpe * 8, &displayable);
1535 if (r)
1536 goto error;
1537
1538 /* Display needs unaligned DCC. */
1539 if (info->use_display_dcc_unaligned &&
1540 surf->num_dcc_levels &&
1541 (surf->u.gfx9.dcc.pipe_aligned ||
1542 surf->u.gfx9.dcc.rb_aligned))
1543 displayable = false;
1544 }
1545 surf->is_displayable = displayable;
1546
1547 switch (surf->u.gfx9.surf.swizzle_mode) {
1548 /* S = standard. */
1549 case ADDR_SW_256B_S:
1550 case ADDR_SW_4KB_S:
1551 case ADDR_SW_64KB_S:
1552 case ADDR_SW_VAR_S:
1553 case ADDR_SW_64KB_S_T:
1554 case ADDR_SW_4KB_S_X:
1555 case ADDR_SW_64KB_S_X:
1556 case ADDR_SW_VAR_S_X:
1557 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1558 break;
1559
1560 /* D = display. */
1561 case ADDR_SW_LINEAR:
1562 case ADDR_SW_256B_D:
1563 case ADDR_SW_4KB_D:
1564 case ADDR_SW_64KB_D:
1565 case ADDR_SW_VAR_D:
1566 case ADDR_SW_64KB_D_T:
1567 case ADDR_SW_4KB_D_X:
1568 case ADDR_SW_64KB_D_X:
1569 case ADDR_SW_VAR_D_X:
1570 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1571 break;
1572
1573 /* R = rotated. */
1574 case ADDR_SW_256B_R:
1575 case ADDR_SW_4KB_R:
1576 case ADDR_SW_64KB_R:
1577 case ADDR_SW_VAR_R:
1578 case ADDR_SW_64KB_R_T:
1579 case ADDR_SW_4KB_R_X:
1580 case ADDR_SW_64KB_R_X:
1581 case ADDR_SW_VAR_R_X:
1582 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1583 * used at the same time. This case is not currently expected to occur
1584 * because we don't use rotated. Enforce this restriction on all chips
1585 * to facilitate testing.
1586 */
1587 assert(!"rotate micro tile mode is unsupported");
1588 r = ADDR_ERROR;
1589 goto error;
1590
1591 /* Z = depth. */
1592 case ADDR_SW_4KB_Z:
1593 case ADDR_SW_64KB_Z:
1594 case ADDR_SW_VAR_Z:
1595 case ADDR_SW_64KB_Z_T:
1596 case ADDR_SW_4KB_Z_X:
1597 case ADDR_SW_64KB_Z_X:
1598 case ADDR_SW_VAR_Z_X:
1599 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1600 break;
1601
1602 default:
1603 assert(0);
1604 }
1605
1606 return 0;
1607
1608 error:
1609 free(surf->u.gfx9.dcc_retile_map);
1610 surf->u.gfx9.dcc_retile_map = NULL;
1611 return r;
1612 }
1613
1614 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1615 const struct ac_surf_config *config,
1616 enum radeon_surf_mode mode,
1617 struct radeon_surf *surf)
1618 {
1619 int r;
1620
1621 r = surf_config_sanity(config, surf->flags);
1622 if (r)
1623 return r;
1624
1625 if (info->chip_class >= GFX9)
1626 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1627 else
1628 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1629 }