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ac/surface/gfx6: compute FMASK together with the color surface
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static unsigned get_first(unsigned x, unsigned y)
53 {
54 return x;
55 }
56
57 static void addrlib_family_rev_id(enum radeon_family family,
58 unsigned *addrlib_family,
59 unsigned *addrlib_revid)
60 {
61 switch (family) {
62 case CHIP_TAHITI:
63 *addrlib_family = FAMILY_SI;
64 *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
65 break;
66 case CHIP_PITCAIRN:
67 *addrlib_family = FAMILY_SI;
68 *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
69 break;
70 case CHIP_VERDE:
71 *addrlib_family = FAMILY_SI;
72 *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
73 break;
74 case CHIP_OLAND:
75 *addrlib_family = FAMILY_SI;
76 *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
77 break;
78 case CHIP_HAINAN:
79 *addrlib_family = FAMILY_SI;
80 *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
81 break;
82 case CHIP_BONAIRE:
83 *addrlib_family = FAMILY_CI;
84 *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
85 break;
86 case CHIP_KAVERI:
87 *addrlib_family = FAMILY_KV;
88 *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
89 break;
90 case CHIP_KABINI:
91 *addrlib_family = FAMILY_KV;
92 *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
93 break;
94 case CHIP_HAWAII:
95 *addrlib_family = FAMILY_CI;
96 *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
97 break;
98 case CHIP_MULLINS:
99 *addrlib_family = FAMILY_KV;
100 *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
101 break;
102 case CHIP_TONGA:
103 *addrlib_family = FAMILY_VI;
104 *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
105 break;
106 case CHIP_ICELAND:
107 *addrlib_family = FAMILY_VI;
108 *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
109 break;
110 case CHIP_CARRIZO:
111 *addrlib_family = FAMILY_CZ;
112 *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
113 break;
114 case CHIP_STONEY:
115 *addrlib_family = FAMILY_CZ;
116 *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
117 break;
118 case CHIP_FIJI:
119 *addrlib_family = FAMILY_VI;
120 *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
121 break;
122 case CHIP_POLARIS10:
123 *addrlib_family = FAMILY_VI;
124 *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
125 break;
126 case CHIP_POLARIS11:
127 *addrlib_family = FAMILY_VI;
128 *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
129 break;
130 case CHIP_POLARIS12:
131 *addrlib_family = FAMILY_VI;
132 *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
133 break;
134 case CHIP_VEGAM:
135 *addrlib_family = FAMILY_VI;
136 *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
137 break;
138 case CHIP_VEGA10:
139 *addrlib_family = FAMILY_AI;
140 *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
141 break;
142 case CHIP_VEGA12:
143 *addrlib_family = FAMILY_AI;
144 *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
145 break;
146 case CHIP_RAVEN:
147 *addrlib_family = FAMILY_RV;
148 *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
149 break;
150 default:
151 fprintf(stderr, "amdgpu: Unknown family.\n");
152 }
153 }
154
155 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
156 {
157 return malloc(pInput->sizeInBytes);
158 }
159
160 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
161 {
162 free(pInput->pVirtAddr);
163 return ADDR_OK;
164 }
165
166 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
167 const struct amdgpu_gpu_info *amdinfo,
168 uint64_t *max_alignment)
169 {
170 ADDR_CREATE_INPUT addrCreateInput = {0};
171 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
172 ADDR_REGISTER_VALUE regValue = {0};
173 ADDR_CREATE_FLAGS createFlags = {{0}};
174 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
175 ADDR_E_RETURNCODE addrRet;
176
177 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
178 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
179
180 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
181 createFlags.value = 0;
182
183 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
184 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
185 return NULL;
186
187 if (addrCreateInput.chipFamily >= FAMILY_AI) {
188 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
189 regValue.blockVarSizeLog2 = 0;
190 } else {
191 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
192 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
193
194 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
195 regValue.pTileConfig = amdinfo->gb_tile_mode;
196 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
197 if (addrCreateInput.chipFamily == FAMILY_SI) {
198 regValue.pMacroTileConfig = NULL;
199 regValue.noOfMacroEntries = 0;
200 } else {
201 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
202 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
203 }
204
205 createFlags.useTileIndex = 1;
206 createFlags.useHtileSliceAlign = 1;
207
208 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
209 }
210
211 addrCreateInput.callbacks.allocSysMem = allocSysMem;
212 addrCreateInput.callbacks.freeSysMem = freeSysMem;
213 addrCreateInput.callbacks.debugPrint = 0;
214 addrCreateInput.createFlags = createFlags;
215 addrCreateInput.regValue = regValue;
216
217 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
218 if (addrRet != ADDR_OK)
219 return NULL;
220
221 if (max_alignment) {
222 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
223 if (addrRet == ADDR_OK){
224 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
225 }
226 }
227 return addrCreateOutput.hLib;
228 }
229
230 static int surf_config_sanity(const struct ac_surf_config *config,
231 unsigned flags)
232 {
233 /* FMASK is allocated together with the color surface and can't be
234 * allocated separately.
235 */
236 assert(!(flags & RADEON_SURF_FMASK));
237 if (flags & RADEON_SURF_FMASK)
238 return -EINVAL;
239
240 /* all dimension must be at least 1 ! */
241 if (!config->info.width || !config->info.height || !config->info.depth ||
242 !config->info.array_size || !config->info.levels)
243 return -EINVAL;
244
245 switch (config->info.samples) {
246 case 0:
247 case 1:
248 case 2:
249 case 4:
250 case 8:
251 break;
252 default:
253 return -EINVAL;
254 }
255
256 if (config->is_3d && config->info.array_size > 1)
257 return -EINVAL;
258 if (config->is_cube && config->info.depth > 1)
259 return -EINVAL;
260
261 return 0;
262 }
263
264 static int gfx6_compute_level(ADDR_HANDLE addrlib,
265 const struct ac_surf_config *config,
266 struct radeon_surf *surf, bool is_stencil,
267 unsigned level, bool compressed,
268 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
269 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
270 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
271 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
272 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
273 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
274 {
275 struct legacy_surf_level *surf_level;
276 ADDR_E_RETURNCODE ret;
277
278 AddrSurfInfoIn->mipLevel = level;
279 AddrSurfInfoIn->width = u_minify(config->info.width, level);
280 AddrSurfInfoIn->height = u_minify(config->info.height, level);
281
282 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
283 * because GFX9 needs linear alignment of 256 bytes.
284 */
285 if (config->info.levels == 1 &&
286 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
287 AddrSurfInfoIn->bpp) {
288 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
289
290 assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
291 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
292 }
293
294 if (config->is_3d)
295 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
296 else if (config->is_cube)
297 AddrSurfInfoIn->numSlices = 6;
298 else
299 AddrSurfInfoIn->numSlices = config->info.array_size;
300
301 if (level > 0) {
302 /* Set the base level pitch. This is needed for calculation
303 * of non-zero levels. */
304 if (is_stencil)
305 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
306 else
307 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
308
309 /* Convert blocks to pixels for compressed formats. */
310 if (compressed)
311 AddrSurfInfoIn->basePitch *= surf->blk_w;
312 }
313
314 ret = AddrComputeSurfaceInfo(addrlib,
315 AddrSurfInfoIn,
316 AddrSurfInfoOut);
317 if (ret != ADDR_OK) {
318 return ret;
319 }
320
321 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
322 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
323 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
324 surf_level->nblk_x = AddrSurfInfoOut->pitch;
325 surf_level->nblk_y = AddrSurfInfoOut->height;
326
327 switch (AddrSurfInfoOut->tileMode) {
328 case ADDR_TM_LINEAR_ALIGNED:
329 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
330 break;
331 case ADDR_TM_1D_TILED_THIN1:
332 surf_level->mode = RADEON_SURF_MODE_1D;
333 break;
334 case ADDR_TM_2D_TILED_THIN1:
335 surf_level->mode = RADEON_SURF_MODE_2D;
336 break;
337 default:
338 assert(0);
339 }
340
341 if (is_stencil)
342 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
343 else
344 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
345
346 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
347
348 /* Clear DCC fields at the beginning. */
349 surf_level->dcc_offset = 0;
350
351 /* The previous level's flag tells us if we can use DCC for this level. */
352 if (AddrSurfInfoIn->flags.dccCompatible &&
353 (level == 0 || AddrDccOut->subLvlCompressible)) {
354 bool prev_level_clearable = level == 0 ||
355 AddrDccOut->dccRamSizeAligned;
356
357 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
358 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
359 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
360 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
361 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
362
363 ret = AddrComputeDccInfo(addrlib,
364 AddrDccIn,
365 AddrDccOut);
366
367 if (ret == ADDR_OK) {
368 surf_level->dcc_offset = surf->dcc_size;
369 surf->num_dcc_levels = level + 1;
370 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
371 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
372
373 /* If the DCC size of a subresource (1 mip level or 1 slice)
374 * is not aligned, the DCC memory layout is not contiguous for
375 * that subresource, which means we can't use fast clear.
376 *
377 * We only do fast clears for whole mipmap levels. If we did
378 * per-slice fast clears, the same restriction would apply.
379 * (i.e. only compute the slice size and see if it's aligned)
380 *
381 * The last level can be non-contiguous and still be clearable
382 * if it's interleaved with the next level that doesn't exist.
383 */
384 if (AddrDccOut->dccRamSizeAligned ||
385 (prev_level_clearable && level == config->info.levels - 1))
386 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
387 else
388 surf_level->dcc_fast_clear_size = 0;
389 }
390 }
391
392 /* TC-compatible HTILE. */
393 if (!is_stencil &&
394 AddrSurfInfoIn->flags.depth &&
395 surf_level->mode == RADEON_SURF_MODE_2D &&
396 level == 0) {
397 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
398 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
399 AddrHtileIn->height = AddrSurfInfoOut->height;
400 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
401 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
402 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
403 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
404 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
405 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
406
407 ret = AddrComputeHtileInfo(addrlib,
408 AddrHtileIn,
409 AddrHtileOut);
410
411 if (ret == ADDR_OK) {
412 surf->htile_size = AddrHtileOut->htileBytes;
413 surf->htile_slice_size = AddrHtileOut->sliceSize;
414 surf->htile_alignment = AddrHtileOut->baseAlign;
415 }
416 }
417
418 return 0;
419 }
420
421 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
422 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
423
424 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
425 const struct radeon_info *info)
426 {
427 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
428
429 if (info->chip_class >= CIK)
430 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
431 else
432 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
433 }
434
435 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
436 {
437 unsigned index, tileb;
438
439 tileb = 8 * 8 * surf->bpe;
440 tileb = MIN2(surf->u.legacy.tile_split, tileb);
441
442 for (index = 0; tileb > 64; index++)
443 tileb >>= 1;
444
445 assert(index < 16);
446 return index;
447 }
448
449 static bool get_display_flag(const struct ac_surf_config *config,
450 const struct radeon_surf *surf)
451 {
452 unsigned num_channels = config->info.num_channels;
453 unsigned bpe = surf->bpe;
454
455 if (surf->flags & RADEON_SURF_SCANOUT &&
456 config->info.samples <= 1 &&
457 surf->blk_w <= 2 && surf->blk_h == 1) {
458 /* subsampled */
459 if (surf->blk_w == 2 && surf->blk_h == 1)
460 return true;
461
462 if (/* RGBA8 or RGBA16F */
463 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
464 /* R5G6B5 or R5G5B5A1 */
465 (bpe == 2 && num_channels >= 3) ||
466 /* C8 palette */
467 (bpe == 1 && num_channels == 1))
468 return true;
469 }
470 return false;
471 }
472
473 /**
474 * This must be called after the first level is computed.
475 *
476 * Copy surface-global settings like pipe/bank config from level 0 surface
477 * computation, and compute tile swizzle.
478 */
479 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
480 const struct radeon_info *info,
481 const struct ac_surf_config *config,
482 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
483 struct radeon_surf *surf)
484 {
485 surf->surf_alignment = csio->baseAlign;
486 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
487 gfx6_set_micro_tile_mode(surf, info);
488
489 /* For 2D modes only. */
490 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
491 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
492 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
493 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
494 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
495 surf->u.legacy.num_banks = csio->pTileInfo->banks;
496 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
497 } else {
498 surf->u.legacy.macro_tile_index = 0;
499 }
500
501 /* Compute tile swizzle. */
502 /* TODO: fix tile swizzle with mipmapping for SI */
503 if ((info->chip_class >= CIK || config->info.levels == 1) &&
504 config->info.surf_index &&
505 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
506 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
507 !get_display_flag(config, surf)) {
508 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
509 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
510
511 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
512 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
513
514 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
515 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
516 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
517 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
518 AddrBaseSwizzleIn.tileMode = csio->tileMode;
519
520 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
521 &AddrBaseSwizzleOut);
522 if (r != ADDR_OK)
523 return r;
524
525 assert(AddrBaseSwizzleOut.tileSwizzle <=
526 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
527 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
528 }
529 return 0;
530 }
531
532 /**
533 * Fill in the tiling information in \p surf based on the given surface config.
534 *
535 * The following fields of \p surf must be initialized by the caller:
536 * blk_w, blk_h, bpe, flags.
537 */
538 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
539 const struct radeon_info *info,
540 const struct ac_surf_config *config,
541 enum radeon_surf_mode mode,
542 struct radeon_surf *surf)
543 {
544 unsigned level;
545 bool compressed;
546 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
547 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
548 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
549 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
550 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
551 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
552 ADDR_TILEINFO AddrTileInfoIn = {0};
553 ADDR_TILEINFO AddrTileInfoOut = {0};
554 int r;
555
556 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
557 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
558 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
559 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
560 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
561 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
562 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
563
564 compressed = surf->blk_w == 4 && surf->blk_h == 4;
565
566 /* MSAA requires 2D tiling. */
567 if (config->info.samples > 1)
568 mode = RADEON_SURF_MODE_2D;
569
570 /* DB doesn't support linear layouts. */
571 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
572 mode < RADEON_SURF_MODE_1D)
573 mode = RADEON_SURF_MODE_1D;
574
575 /* Set the requested tiling mode. */
576 switch (mode) {
577 case RADEON_SURF_MODE_LINEAR_ALIGNED:
578 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
579 break;
580 case RADEON_SURF_MODE_1D:
581 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
582 break;
583 case RADEON_SURF_MODE_2D:
584 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
585 break;
586 default:
587 assert(0);
588 }
589
590 /* The format must be set correctly for the allocation of compressed
591 * textures to work. In other cases, setting the bpp is sufficient.
592 */
593 if (compressed) {
594 switch (surf->bpe) {
595 case 8:
596 AddrSurfInfoIn.format = ADDR_FMT_BC1;
597 break;
598 case 16:
599 AddrSurfInfoIn.format = ADDR_FMT_BC3;
600 break;
601 default:
602 assert(0);
603 }
604 }
605 else {
606 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
607 }
608
609 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
610 config->info.samples ? config->info.samples : 1;
611 AddrSurfInfoIn.tileIndex = -1;
612
613 /* Set the micro tile type. */
614 if (surf->flags & RADEON_SURF_SCANOUT)
615 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
616 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
617 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
618 else
619 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
620
621 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
622 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
623 AddrSurfInfoIn.flags.cube = config->is_cube;
624 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
625 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
626 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
627
628 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
629 * requested, because TC-compatible HTILE requires 2D tiling.
630 */
631 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
632 !AddrSurfInfoIn.flags.fmask &&
633 config->info.samples <= 1 &&
634 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
635
636 /* DCC notes:
637 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
638 * with samples >= 4.
639 * - Mipmapped array textures have low performance (discovered by a closed
640 * driver team).
641 */
642 AddrSurfInfoIn.flags.dccCompatible =
643 info->chip_class >= VI &&
644 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
645 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
646 !compressed &&
647 ((config->info.array_size == 1 && config->info.depth == 1) ||
648 config->info.levels == 1);
649
650 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
651 AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
652
653 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
654 * for Z and stencil. This can cause a number of problems which we work
655 * around here:
656 *
657 * - a depth part that is incompatible with mipmapped texturing
658 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
659 * incorrect tiling applied to the stencil part, stencil buffer
660 * memory accesses that go out of bounds) even without mipmapping
661 *
662 * Some piglit tests that are prone to different types of related
663 * failures:
664 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
665 * ./bin/framebuffer-blit-levels {draw,read} stencil
666 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
667 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
668 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
669 */
670 int stencil_tile_idx = -1;
671
672 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
673 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
674 /* Compute stencilTileIdx that is compatible with the (depth)
675 * tileIdx. This degrades the depth surface if necessary to
676 * ensure that a matching stencilTileIdx exists. */
677 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
678
679 /* Keep the depth mip-tail compatible with texturing. */
680 AddrSurfInfoIn.flags.noStencil = 1;
681 }
682
683 /* Set preferred macrotile parameters. This is usually required
684 * for shared resources. This is for 2D tiling only. */
685 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
686 surf->u.legacy.bankw && surf->u.legacy.bankh &&
687 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
688 /* If any of these parameters are incorrect, the calculation
689 * will fail. */
690 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
691 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
692 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
693 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
694 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
695 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
696 AddrSurfInfoIn.flags.opt4Space = 0;
697 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
698
699 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
700 * the tile index, because we are expected to know it if
701 * we know the other parameters.
702 *
703 * This is something that can easily be fixed in Addrlib.
704 * For now, just figure it out here.
705 * Note that only 2D_TILE_THIN1 is handled here.
706 */
707 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
708 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
709
710 if (info->chip_class == SI) {
711 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
712 if (surf->bpe == 2)
713 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
714 else
715 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
716 } else {
717 if (surf->bpe == 1)
718 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
719 else if (surf->bpe == 2)
720 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
721 else if (surf->bpe == 4)
722 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
723 else
724 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
725 }
726 } else {
727 /* CIK - VI */
728 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
729 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
730 else
731 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
732
733 /* Addrlib doesn't set this if tileIndex is forced like above. */
734 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
735 }
736 }
737
738 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
739 surf->num_dcc_levels = 0;
740 surf->surf_size = 0;
741 surf->dcc_size = 0;
742 surf->dcc_alignment = 1;
743 surf->htile_size = 0;
744 surf->htile_slice_size = 0;
745 surf->htile_alignment = 1;
746
747 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
748 !(surf->flags & RADEON_SURF_ZBUFFER);
749
750 /* Calculate texture layout information. */
751 if (!only_stencil) {
752 for (level = 0; level < config->info.levels; level++) {
753 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
754 &AddrSurfInfoIn, &AddrSurfInfoOut,
755 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
756 if (r)
757 return r;
758
759 if (level > 0)
760 continue;
761
762 /* Check that we actually got a TC-compatible HTILE if
763 * we requested it (only for level 0, since we're not
764 * supporting HTILE on higher mip levels anyway). */
765 assert(AddrSurfInfoOut.tcCompatible ||
766 !AddrSurfInfoIn.flags.tcCompatible ||
767 AddrSurfInfoIn.flags.matchStencilTileCfg);
768
769 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
770 if (!AddrSurfInfoOut.tcCompatible) {
771 AddrSurfInfoIn.flags.tcCompatible = 0;
772 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
773 }
774
775 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
776 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
777 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
778
779 assert(stencil_tile_idx >= 0);
780 }
781
782 r = gfx6_surface_settings(addrlib, info, config,
783 &AddrSurfInfoOut, surf);
784 if (r)
785 return r;
786 }
787 }
788
789 /* Calculate texture layout information for stencil. */
790 if (surf->flags & RADEON_SURF_SBUFFER) {
791 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
792 AddrSurfInfoIn.bpp = 8;
793 AddrSurfInfoIn.flags.depth = 0;
794 AddrSurfInfoIn.flags.stencil = 1;
795 AddrSurfInfoIn.flags.tcCompatible = 0;
796 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
797 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
798
799 for (level = 0; level < config->info.levels; level++) {
800 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
801 &AddrSurfInfoIn, &AddrSurfInfoOut,
802 &AddrDccIn, &AddrDccOut,
803 NULL, NULL);
804 if (r)
805 return r;
806
807 /* DB uses the depth pitch for both stencil and depth. */
808 if (!only_stencil) {
809 if (surf->u.legacy.stencil_level[level].nblk_x !=
810 surf->u.legacy.level[level].nblk_x)
811 surf->u.legacy.stencil_adjusted = true;
812 } else {
813 surf->u.legacy.level[level].nblk_x =
814 surf->u.legacy.stencil_level[level].nblk_x;
815 }
816
817 if (level == 0) {
818 if (only_stencil) {
819 r = gfx6_surface_settings(addrlib, info, config,
820 &AddrSurfInfoOut, surf);
821 if (r)
822 return r;
823 }
824
825 /* For 2D modes only. */
826 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
827 surf->u.legacy.stencil_tile_split =
828 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
829 }
830 }
831 }
832 }
833
834 /* Compute FMASK. */
835 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
836 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
837 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
838 ADDR_TILEINFO fmask_tile_info = {};
839
840 fin.size = sizeof(fin);
841 fout.size = sizeof(fout);
842
843 fin.tileMode = AddrSurfInfoOut.tileMode;
844 fin.pitch = AddrSurfInfoOut.pitch;
845 fin.height = config->info.height;
846 fin.numSlices = AddrSurfInfoIn.numSlices;
847 fin.numSamples = AddrSurfInfoIn.numSamples;
848 fin.numFrags = AddrSurfInfoIn.numFrags;
849 fin.tileIndex = AddrSurfInfoOut.tileIndex;
850 fout.pTileInfo = &fmask_tile_info;
851
852 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
853 if (r)
854 return r;
855
856 surf->u.legacy.fmask.size = fout.fmaskBytes;
857 surf->u.legacy.fmask.alignment = fout.baseAlign;
858 surf->u.legacy.fmask.tile_swizzle = 0;
859
860 surf->u.legacy.fmask.slice_tile_max =
861 (fout.pitch * fout.height) / 64;
862 if (surf->u.legacy.fmask.slice_tile_max)
863 surf->u.legacy.fmask.slice_tile_max -= 1;
864
865 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
866 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
867 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
868
869 /* Compute tile swizzle for FMASK. */
870 if (config->info.fmask_surf_index &&
871 !(surf->flags & RADEON_SURF_SHAREABLE)) {
872 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
873 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
874
875 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
876 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
877
878 /* This counter starts from 1 instead of 0. */
879 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
880 xin.tileIndex = fout.tileIndex;
881 xin.macroModeIndex = fout.macroModeIndex;
882 xin.pTileInfo = fout.pTileInfo;
883 xin.tileMode = fin.tileMode;
884
885 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
886 if (r != ADDR_OK)
887 return r;
888
889 assert(xout.tileSwizzle <=
890 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
891 surf->u.legacy.fmask.tile_swizzle = xout.tileSwizzle;
892 }
893 }
894
895 /* Recalculate the whole DCC miptree size including disabled levels.
896 * This is what addrlib does, but calling addrlib would be a lot more
897 * complicated.
898 */
899 if (surf->dcc_size && config->info.levels > 1) {
900 /* The smallest miplevels that are never compressed by DCC
901 * still read the DCC buffer via TC if the base level uses DCC,
902 * and for some reason the DCC buffer needs to be larger if
903 * the miptree uses non-zero tile_swizzle. Otherwise there are
904 * VM faults.
905 *
906 * "dcc_alignment * 4" was determined by trial and error.
907 */
908 surf->dcc_size = align64(surf->surf_size >> 8,
909 surf->dcc_alignment * 4);
910 }
911
912 /* Make sure HTILE covers the whole miptree, because the shader reads
913 * TC-compatible HTILE even for levels where it's disabled by DB.
914 */
915 if (surf->htile_size && config->info.levels > 1)
916 surf->htile_size *= 2;
917
918 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
919 surf->is_displayable = surf->is_linear ||
920 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
921 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
922 return 0;
923 }
924
925 /* This is only called when expecting a tiled layout. */
926 static int
927 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
928 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
929 bool is_fmask, unsigned flags,
930 AddrSwizzleMode *swizzle_mode)
931 {
932 ADDR_E_RETURNCODE ret;
933 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
934 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
935
936 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
937 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
938
939 sin.flags = in->flags;
940 sin.resourceType = in->resourceType;
941 sin.format = in->format;
942 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
943 /* TODO: We could allow some of these: */
944 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
945 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
946 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
947 sin.bpp = in->bpp;
948 sin.width = in->width;
949 sin.height = in->height;
950 sin.numSlices = in->numSlices;
951 sin.numMipLevels = in->numMipLevels;
952 sin.numSamples = in->numSamples;
953 sin.numFrags = in->numFrags;
954
955 if (flags & RADEON_SURF_SCANOUT) {
956 sin.preferredSwSet.sw_D = 1;
957 /* Raven only allows S for displayable surfaces with < 64 bpp, so
958 * allow it as fallback */
959 sin.preferredSwSet.sw_S = 1;
960 } else if (in->flags.depth || in->flags.stencil || is_fmask)
961 sin.preferredSwSet.sw_Z = 1;
962 else
963 sin.preferredSwSet.sw_S = 1;
964
965 if (is_fmask) {
966 sin.flags.display = 0;
967 sin.flags.color = 0;
968 sin.flags.fmask = 1;
969 }
970
971 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
972 if (ret != ADDR_OK)
973 return ret;
974
975 *swizzle_mode = sout.swizzleMode;
976 return 0;
977 }
978
979 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
980 const struct ac_surf_config *config,
981 struct radeon_surf *surf, bool compressed,
982 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
983 {
984 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
985 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
986 ADDR_E_RETURNCODE ret;
987
988 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
989 out.pMipInfo = mip_info;
990
991 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
992 if (ret != ADDR_OK)
993 return ret;
994
995 if (in->flags.stencil) {
996 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
997 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
998 out.mipChainPitch - 1;
999 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1000 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1001 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1002 return 0;
1003 }
1004
1005 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1006 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1007 out.mipChainPitch - 1;
1008
1009 /* CMASK fast clear uses these even if FMASK isn't allocated.
1010 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1011 */
1012 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1013 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1014
1015 surf->u.gfx9.surf_slice_size = out.sliceSize;
1016 surf->u.gfx9.surf_pitch = out.pitch;
1017 surf->u.gfx9.surf_height = out.height;
1018 surf->surf_size = out.surfSize;
1019 surf->surf_alignment = out.baseAlign;
1020
1021 if (in->swizzleMode == ADDR_SW_LINEAR) {
1022 for (unsigned i = 0; i < in->numMipLevels; i++)
1023 surf->u.gfx9.offset[i] = mip_info[i].offset;
1024 }
1025
1026 if (in->flags.depth) {
1027 assert(in->swizzleMode != ADDR_SW_LINEAR);
1028
1029 /* HTILE */
1030 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1031 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1032
1033 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1034 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1035
1036 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1037 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1038 hin.depthFlags = in->flags;
1039 hin.swizzleMode = in->swizzleMode;
1040 hin.unalignedWidth = in->width;
1041 hin.unalignedHeight = in->height;
1042 hin.numSlices = in->numSlices;
1043 hin.numMipLevels = in->numMipLevels;
1044
1045 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1046 if (ret != ADDR_OK)
1047 return ret;
1048
1049 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1050 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1051 surf->htile_size = hout.htileBytes;
1052 surf->htile_slice_size = hout.sliceSize;
1053 surf->htile_alignment = hout.baseAlign;
1054 } else {
1055 /* Compute tile swizzle for the color surface.
1056 * All *_X and *_T modes can use the swizzle.
1057 */
1058 if (config->info.surf_index &&
1059 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1060 !out.mipChainInTail &&
1061 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1062 !in->flags.display) {
1063 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1064 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1065
1066 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1067 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1068
1069 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1070 xin.flags = in->flags;
1071 xin.swizzleMode = in->swizzleMode;
1072 xin.resourceType = in->resourceType;
1073 xin.format = in->format;
1074 xin.numSamples = in->numSamples;
1075 xin.numFrags = in->numFrags;
1076
1077 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1078 if (ret != ADDR_OK)
1079 return ret;
1080
1081 assert(xout.pipeBankXor <=
1082 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1083 surf->tile_swizzle = xout.pipeBankXor;
1084 }
1085
1086 /* DCC */
1087 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1088 !compressed &&
1089 in->swizzleMode != ADDR_SW_LINEAR) {
1090 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1091 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1092 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1093
1094 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1095 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1096 dout.pMipInfo = meta_mip_info;
1097
1098 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1099 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1100 din.colorFlags = in->flags;
1101 din.resourceType = in->resourceType;
1102 din.swizzleMode = in->swizzleMode;
1103 din.bpp = in->bpp;
1104 din.unalignedWidth = in->width;
1105 din.unalignedHeight = in->height;
1106 din.numSlices = in->numSlices;
1107 din.numFrags = in->numFrags;
1108 din.numMipLevels = in->numMipLevels;
1109 din.dataSurfaceSize = out.surfSize;
1110
1111 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1112 if (ret != ADDR_OK)
1113 return ret;
1114
1115 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1116 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1117 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
1118 surf->dcc_size = dout.dccRamSize;
1119 surf->dcc_alignment = dout.dccRamBaseAlign;
1120 surf->num_dcc_levels = in->numMipLevels;
1121
1122 /* Disable DCC for levels that are in the mip tail.
1123 *
1124 * There are two issues that this is intended to
1125 * address:
1126 *
1127 * 1. Multiple mip levels may share a cache line. This
1128 * can lead to corruption when switching between
1129 * rendering to different mip levels because the
1130 * RBs don't maintain coherency.
1131 *
1132 * 2. Texturing with metadata after rendering sometimes
1133 * fails with corruption, probably for a similar
1134 * reason.
1135 *
1136 * Working around these issues for all levels in the
1137 * mip tail may be overly conservative, but it's what
1138 * Vulkan does.
1139 *
1140 * Alternative solutions that also work but are worse:
1141 * - Disable DCC entirely.
1142 * - Flush TC L2 after rendering.
1143 */
1144 for (unsigned i = 0; i < in->numMipLevels; i++) {
1145 if (meta_mip_info[i].inMiptail) {
1146 surf->num_dcc_levels = i;
1147 break;
1148 }
1149 }
1150
1151 if (!surf->num_dcc_levels)
1152 surf->dcc_size = 0;
1153 }
1154
1155 /* FMASK */
1156 if (in->numSamples > 1) {
1157 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1158 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1159
1160 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1161 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1162
1163 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1164 true, surf->flags,
1165 &fin.swizzleMode);
1166 if (ret != ADDR_OK)
1167 return ret;
1168
1169 fin.unalignedWidth = in->width;
1170 fin.unalignedHeight = in->height;
1171 fin.numSlices = in->numSlices;
1172 fin.numSamples = in->numSamples;
1173 fin.numFrags = in->numFrags;
1174
1175 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1176 if (ret != ADDR_OK)
1177 return ret;
1178
1179 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1180 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1181 surf->u.gfx9.fmask_size = fout.fmaskBytes;
1182 surf->u.gfx9.fmask_alignment = fout.baseAlign;
1183
1184 /* Compute tile swizzle for the FMASK surface. */
1185 if (config->info.fmask_surf_index &&
1186 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1187 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1188 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1189 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1190
1191 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1192 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1193
1194 /* This counter starts from 1 instead of 0. */
1195 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1196 xin.flags = in->flags;
1197 xin.swizzleMode = in->swizzleMode;
1198 xin.resourceType = in->resourceType;
1199 xin.format = in->format;
1200 xin.numSamples = in->numSamples;
1201 xin.numFrags = in->numFrags;
1202
1203 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1204 if (ret != ADDR_OK)
1205 return ret;
1206
1207 assert(xout.pipeBankXor <=
1208 u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
1209 surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
1210 }
1211 }
1212
1213 /* CMASK */
1214 if (in->swizzleMode != ADDR_SW_LINEAR) {
1215 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1216 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1217
1218 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1219 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1220
1221 if (in->numSamples > 1) {
1222 /* FMASK is always aligned. */
1223 cin.cMaskFlags.pipeAligned = 1;
1224 cin.cMaskFlags.rbAligned = 1;
1225 } else {
1226 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1227 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1228 }
1229 cin.colorFlags = in->flags;
1230 cin.resourceType = in->resourceType;
1231 cin.unalignedWidth = in->width;
1232 cin.unalignedHeight = in->height;
1233 cin.numSlices = in->numSlices;
1234
1235 if (in->numSamples > 1)
1236 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1237 else
1238 cin.swizzleMode = in->swizzleMode;
1239
1240 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1241 if (ret != ADDR_OK)
1242 return ret;
1243
1244 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1245 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1246 surf->u.gfx9.cmask_size = cout.cmaskBytes;
1247 surf->u.gfx9.cmask_alignment = cout.baseAlign;
1248 }
1249 }
1250
1251 return 0;
1252 }
1253
1254 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1255 const struct radeon_info *info,
1256 const struct ac_surf_config *config,
1257 enum radeon_surf_mode mode,
1258 struct radeon_surf *surf)
1259 {
1260 bool compressed;
1261 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1262 int r;
1263
1264 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1265
1266 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1267
1268 /* The format must be set correctly for the allocation of compressed
1269 * textures to work. In other cases, setting the bpp is sufficient. */
1270 if (compressed) {
1271 switch (surf->bpe) {
1272 case 8:
1273 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1274 break;
1275 case 16:
1276 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1277 break;
1278 default:
1279 assert(0);
1280 }
1281 } else {
1282 switch (surf->bpe) {
1283 case 1:
1284 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1285 AddrSurfInfoIn.format = ADDR_FMT_8;
1286 break;
1287 case 2:
1288 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1289 !(surf->flags & RADEON_SURF_SBUFFER));
1290 AddrSurfInfoIn.format = ADDR_FMT_16;
1291 break;
1292 case 4:
1293 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1294 !(surf->flags & RADEON_SURF_SBUFFER));
1295 AddrSurfInfoIn.format = ADDR_FMT_32;
1296 break;
1297 case 8:
1298 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1299 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1300 break;
1301 case 16:
1302 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1303 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1304 break;
1305 default:
1306 assert(0);
1307 }
1308 AddrSurfInfoIn.bpp = surf->bpe * 8;
1309 }
1310
1311 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1312 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1313 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1314 /* flags.texture currently refers to TC-compatible HTILE */
1315 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1316 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1317 AddrSurfInfoIn.flags.opt4space = 1;
1318
1319 AddrSurfInfoIn.numMipLevels = config->info.levels;
1320 AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1321 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1322
1323 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1324 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1325 * must sample 1D textures as 2D. */
1326 if (config->is_3d)
1327 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1328 else
1329 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1330
1331 AddrSurfInfoIn.width = config->info.width;
1332 AddrSurfInfoIn.height = config->info.height;
1333
1334 if (config->is_3d)
1335 AddrSurfInfoIn.numSlices = config->info.depth;
1336 else if (config->is_cube)
1337 AddrSurfInfoIn.numSlices = 6;
1338 else
1339 AddrSurfInfoIn.numSlices = config->info.array_size;
1340
1341 /* This is propagated to HTILE/DCC/CMASK. */
1342 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1343 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1344
1345 switch (mode) {
1346 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1347 assert(config->info.samples <= 1);
1348 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1349 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1350 break;
1351
1352 case RADEON_SURF_MODE_1D:
1353 case RADEON_SURF_MODE_2D:
1354 if (surf->flags & RADEON_SURF_IMPORTED) {
1355 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1356 break;
1357 }
1358
1359 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1360 false, surf->flags,
1361 &AddrSurfInfoIn.swizzleMode);
1362 if (r)
1363 return r;
1364 break;
1365
1366 default:
1367 assert(0);
1368 }
1369
1370 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1371 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1372
1373 surf->num_dcc_levels = 0;
1374 surf->surf_size = 0;
1375 surf->dcc_size = 0;
1376 surf->htile_size = 0;
1377 surf->htile_slice_size = 0;
1378 surf->u.gfx9.surf_offset = 0;
1379 surf->u.gfx9.stencil_offset = 0;
1380 surf->u.gfx9.fmask_size = 0;
1381 surf->u.gfx9.cmask_size = 0;
1382
1383 /* Calculate texture layout information. */
1384 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1385 &AddrSurfInfoIn);
1386 if (r)
1387 return r;
1388
1389 /* Calculate texture layout information for stencil. */
1390 if (surf->flags & RADEON_SURF_SBUFFER) {
1391 AddrSurfInfoIn.flags.stencil = 1;
1392 AddrSurfInfoIn.bpp = 8;
1393 AddrSurfInfoIn.format = ADDR_FMT_8;
1394
1395 if (!AddrSurfInfoIn.flags.depth) {
1396 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1397 false, surf->flags,
1398 &AddrSurfInfoIn.swizzleMode);
1399 if (r)
1400 return r;
1401 } else
1402 AddrSurfInfoIn.flags.depth = 0;
1403
1404 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1405 &AddrSurfInfoIn);
1406 if (r)
1407 return r;
1408 }
1409
1410 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1411
1412 /* Query whether the surface is displayable. */
1413 bool displayable = false;
1414 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1415 surf->bpe * 8, &displayable);
1416 if (r)
1417 return r;
1418 surf->is_displayable = displayable;
1419
1420 switch (surf->u.gfx9.surf.swizzle_mode) {
1421 /* S = standard. */
1422 case ADDR_SW_256B_S:
1423 case ADDR_SW_4KB_S:
1424 case ADDR_SW_64KB_S:
1425 case ADDR_SW_VAR_S:
1426 case ADDR_SW_64KB_S_T:
1427 case ADDR_SW_4KB_S_X:
1428 case ADDR_SW_64KB_S_X:
1429 case ADDR_SW_VAR_S_X:
1430 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1431 break;
1432
1433 /* D = display. */
1434 case ADDR_SW_LINEAR:
1435 case ADDR_SW_256B_D:
1436 case ADDR_SW_4KB_D:
1437 case ADDR_SW_64KB_D:
1438 case ADDR_SW_VAR_D:
1439 case ADDR_SW_64KB_D_T:
1440 case ADDR_SW_4KB_D_X:
1441 case ADDR_SW_64KB_D_X:
1442 case ADDR_SW_VAR_D_X:
1443 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1444 break;
1445
1446 /* R = rotated. */
1447 case ADDR_SW_256B_R:
1448 case ADDR_SW_4KB_R:
1449 case ADDR_SW_64KB_R:
1450 case ADDR_SW_VAR_R:
1451 case ADDR_SW_64KB_R_T:
1452 case ADDR_SW_4KB_R_X:
1453 case ADDR_SW_64KB_R_X:
1454 case ADDR_SW_VAR_R_X:
1455 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1456 break;
1457
1458 /* Z = depth. */
1459 case ADDR_SW_4KB_Z:
1460 case ADDR_SW_64KB_Z:
1461 case ADDR_SW_VAR_Z:
1462 case ADDR_SW_64KB_Z_T:
1463 case ADDR_SW_4KB_Z_X:
1464 case ADDR_SW_64KB_Z_X:
1465 case ADDR_SW_VAR_Z_X:
1466 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1467 break;
1468
1469 default:
1470 assert(0);
1471 }
1472
1473 /* Temporary workaround to prevent VM faults and hangs. */
1474 if (info->family == CHIP_VEGA12)
1475 surf->u.gfx9.fmask_size *= 8;
1476
1477 return 0;
1478 }
1479
1480 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1481 const struct ac_surf_config *config,
1482 enum radeon_surf_mode mode,
1483 struct radeon_surf *surf)
1484 {
1485 int r;
1486
1487 r = surf_config_sanity(config, surf->flags);
1488 if (r)
1489 return r;
1490
1491 if (info->chip_class >= GFX9)
1492 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1493 else
1494 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1495 }