2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include <amdgpu_drm.h>
42 #include "addrlib/inc/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static unsigned get_first(unsigned x
, unsigned y
)
57 static void addrlib_family_rev_id(enum radeon_family family
,
58 unsigned *addrlib_family
,
59 unsigned *addrlib_revid
)
63 *addrlib_family
= FAMILY_SI
;
64 *addrlib_revid
= get_first(AMDGPU_TAHITI_RANGE
);
67 *addrlib_family
= FAMILY_SI
;
68 *addrlib_revid
= get_first(AMDGPU_PITCAIRN_RANGE
);
71 *addrlib_family
= FAMILY_SI
;
72 *addrlib_revid
= get_first(AMDGPU_CAPEVERDE_RANGE
);
75 *addrlib_family
= FAMILY_SI
;
76 *addrlib_revid
= get_first(AMDGPU_OLAND_RANGE
);
79 *addrlib_family
= FAMILY_SI
;
80 *addrlib_revid
= get_first(AMDGPU_HAINAN_RANGE
);
83 *addrlib_family
= FAMILY_CI
;
84 *addrlib_revid
= get_first(AMDGPU_BONAIRE_RANGE
);
87 *addrlib_family
= FAMILY_KV
;
88 *addrlib_revid
= get_first(AMDGPU_SPECTRE_RANGE
);
91 *addrlib_family
= FAMILY_KV
;
92 *addrlib_revid
= get_first(AMDGPU_KALINDI_RANGE
);
95 *addrlib_family
= FAMILY_CI
;
96 *addrlib_revid
= get_first(AMDGPU_HAWAII_RANGE
);
99 *addrlib_family
= FAMILY_VI
;
100 *addrlib_revid
= get_first(AMDGPU_TONGA_RANGE
);
103 *addrlib_family
= FAMILY_VI
;
104 *addrlib_revid
= get_first(AMDGPU_ICELAND_RANGE
);
107 *addrlib_family
= FAMILY_CZ
;
108 *addrlib_revid
= get_first(AMDGPU_CARRIZO_RANGE
);
111 *addrlib_family
= FAMILY_CZ
;
112 *addrlib_revid
= get_first(AMDGPU_STONEY_RANGE
);
115 *addrlib_family
= FAMILY_VI
;
116 *addrlib_revid
= get_first(AMDGPU_FIJI_RANGE
);
119 *addrlib_family
= FAMILY_VI
;
120 *addrlib_revid
= get_first(AMDGPU_POLARIS10_RANGE
);
123 *addrlib_family
= FAMILY_VI
;
124 *addrlib_revid
= get_first(AMDGPU_POLARIS11_RANGE
);
127 *addrlib_family
= FAMILY_VI
;
128 *addrlib_revid
= get_first(AMDGPU_POLARIS12_RANGE
);
131 *addrlib_family
= FAMILY_VI
;
132 *addrlib_revid
= get_first(AMDGPU_VEGAM_RANGE
);
135 *addrlib_family
= FAMILY_AI
;
136 *addrlib_revid
= get_first(AMDGPU_VEGA10_RANGE
);
139 *addrlib_family
= FAMILY_AI
;
140 *addrlib_revid
= get_first(AMDGPU_VEGA12_RANGE
);
143 *addrlib_family
= FAMILY_AI
;
144 *addrlib_revid
= get_first(AMDGPU_VEGA20_RANGE
);
147 *addrlib_family
= FAMILY_RV
;
148 *addrlib_revid
= get_first(AMDGPU_RAVEN_RANGE
);
151 *addrlib_family
= FAMILY_RV
;
152 *addrlib_revid
= get_first(AMDGPU_RAVEN2_RANGE
);
155 fprintf(stderr
, "amdgpu: Unknown family.\n");
159 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
161 return malloc(pInput
->sizeInBytes
);
164 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
166 free(pInput
->pVirtAddr
);
170 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
171 const struct amdgpu_gpu_info
*amdinfo
,
172 uint64_t *max_alignment
)
174 ADDR_CREATE_INPUT addrCreateInput
= {0};
175 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
176 ADDR_REGISTER_VALUE regValue
= {0};
177 ADDR_CREATE_FLAGS createFlags
= {{0}};
178 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
179 ADDR_E_RETURNCODE addrRet
;
181 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
182 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
184 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
185 createFlags
.value
= 0;
187 addrlib_family_rev_id(info
->family
, &addrCreateInput
.chipFamily
, &addrCreateInput
.chipRevision
);
188 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
191 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
192 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
193 regValue
.blockVarSizeLog2
= 0;
195 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
196 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
198 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
199 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
200 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
201 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
202 regValue
.pMacroTileConfig
= NULL
;
203 regValue
.noOfMacroEntries
= 0;
205 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
206 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
209 createFlags
.useTileIndex
= 1;
210 createFlags
.useHtileSliceAlign
= 1;
212 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
215 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
216 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
217 addrCreateInput
.callbacks
.debugPrint
= 0;
218 addrCreateInput
.createFlags
= createFlags
;
219 addrCreateInput
.regValue
= regValue
;
221 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
222 if (addrRet
!= ADDR_OK
)
226 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
227 if (addrRet
== ADDR_OK
){
228 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
231 return addrCreateOutput
.hLib
;
234 static int surf_config_sanity(const struct ac_surf_config
*config
,
237 /* FMASK is allocated together with the color surface and can't be
238 * allocated separately.
240 assert(!(flags
& RADEON_SURF_FMASK
));
241 if (flags
& RADEON_SURF_FMASK
)
244 /* all dimension must be at least 1 ! */
245 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
246 !config
->info
.array_size
|| !config
->info
.levels
)
249 switch (config
->info
.samples
) {
257 if (flags
& RADEON_SURF_Z_OR_SBUFFER
)
264 if (!(flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
265 switch (config
->info
.storage_samples
) {
277 if (config
->is_3d
&& config
->info
.array_size
> 1)
279 if (config
->is_cube
&& config
->info
.depth
> 1)
285 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
286 const struct ac_surf_config
*config
,
287 struct radeon_surf
*surf
, bool is_stencil
,
288 unsigned level
, bool compressed
,
289 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
290 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
291 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
292 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
293 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
294 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
296 struct legacy_surf_level
*surf_level
;
297 ADDR_E_RETURNCODE ret
;
299 AddrSurfInfoIn
->mipLevel
= level
;
300 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
301 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
303 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
304 * because GFX9 needs linear alignment of 256 bytes.
306 if (config
->info
.levels
== 1 &&
307 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
308 AddrSurfInfoIn
->bpp
&&
309 util_is_power_of_two_or_zero(AddrSurfInfoIn
->bpp
)) {
310 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
312 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
316 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
317 else if (config
->is_cube
)
318 AddrSurfInfoIn
->numSlices
= 6;
320 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
323 /* Set the base level pitch. This is needed for calculation
324 * of non-zero levels. */
326 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
328 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
330 /* Convert blocks to pixels for compressed formats. */
332 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
335 ret
= AddrComputeSurfaceInfo(addrlib
,
338 if (ret
!= ADDR_OK
) {
342 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
343 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
344 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
345 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
346 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
348 switch (AddrSurfInfoOut
->tileMode
) {
349 case ADDR_TM_LINEAR_ALIGNED
:
350 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
352 case ADDR_TM_1D_TILED_THIN1
:
353 surf_level
->mode
= RADEON_SURF_MODE_1D
;
355 case ADDR_TM_2D_TILED_THIN1
:
356 surf_level
->mode
= RADEON_SURF_MODE_2D
;
363 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
365 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
367 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
369 /* Clear DCC fields at the beginning. */
370 surf_level
->dcc_offset
= 0;
372 /* The previous level's flag tells us if we can use DCC for this level. */
373 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
374 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
375 bool prev_level_clearable
= level
== 0 ||
376 AddrDccOut
->dccRamSizeAligned
;
378 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
379 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
380 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
381 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
382 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
384 ret
= AddrComputeDccInfo(addrlib
,
388 if (ret
== ADDR_OK
) {
389 surf_level
->dcc_offset
= surf
->dcc_size
;
390 surf
->num_dcc_levels
= level
+ 1;
391 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
392 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
394 /* If the DCC size of a subresource (1 mip level or 1 slice)
395 * is not aligned, the DCC memory layout is not contiguous for
396 * that subresource, which means we can't use fast clear.
398 * We only do fast clears for whole mipmap levels. If we did
399 * per-slice fast clears, the same restriction would apply.
400 * (i.e. only compute the slice size and see if it's aligned)
402 * The last level can be non-contiguous and still be clearable
403 * if it's interleaved with the next level that doesn't exist.
405 if (AddrDccOut
->dccRamSizeAligned
||
406 (prev_level_clearable
&& level
== config
->info
.levels
- 1))
407 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
409 surf_level
->dcc_fast_clear_size
= 0;
413 /* TC-compatible HTILE. */
415 AddrSurfInfoIn
->flags
.depth
&&
416 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
418 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
419 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
420 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
421 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
422 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
423 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
424 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
425 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
426 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
428 ret
= AddrComputeHtileInfo(addrlib
,
432 if (ret
== ADDR_OK
) {
433 surf
->htile_size
= AddrHtileOut
->htileBytes
;
434 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
435 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
442 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
443 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
444 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
446 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
447 const struct radeon_info
*info
)
449 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
451 if (info
->chip_class
>= GFX7
)
452 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
454 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
457 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
459 unsigned index
, tileb
;
461 tileb
= 8 * 8 * surf
->bpe
;
462 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
464 for (index
= 0; tileb
> 64; index
++)
471 static bool get_display_flag(const struct ac_surf_config
*config
,
472 const struct radeon_surf
*surf
)
474 unsigned num_channels
= config
->info
.num_channels
;
475 unsigned bpe
= surf
->bpe
;
477 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
478 surf
->flags
& RADEON_SURF_SCANOUT
&&
479 config
->info
.samples
<= 1 &&
480 surf
->blk_w
<= 2 && surf
->blk_h
== 1) {
482 if (surf
->blk_w
== 2 && surf
->blk_h
== 1)
485 if (/* RGBA8 or RGBA16F */
486 (bpe
>= 4 && bpe
<= 8 && num_channels
== 4) ||
487 /* R5G6B5 or R5G5B5A1 */
488 (bpe
== 2 && num_channels
>= 3) ||
490 (bpe
== 1 && num_channels
== 1))
497 * This must be called after the first level is computed.
499 * Copy surface-global settings like pipe/bank config from level 0 surface
500 * computation, and compute tile swizzle.
502 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
503 const struct radeon_info
*info
,
504 const struct ac_surf_config
*config
,
505 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
506 struct radeon_surf
*surf
)
508 surf
->surf_alignment
= csio
->baseAlign
;
509 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
510 gfx6_set_micro_tile_mode(surf
, info
);
512 /* For 2D modes only. */
513 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
514 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
515 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
516 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
517 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
518 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
519 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
521 surf
->u
.legacy
.macro_tile_index
= 0;
524 /* Compute tile swizzle. */
525 /* TODO: fix tile swizzle with mipmapping for GFX6 */
526 if ((info
->chip_class
>= GFX7
|| config
->info
.levels
== 1) &&
527 config
->info
.surf_index
&&
528 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
529 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
530 !get_display_flag(config
, surf
)) {
531 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
532 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
534 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
535 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
537 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
538 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
539 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
540 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
541 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
543 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
544 &AddrBaseSwizzleOut
);
548 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
549 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
550 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
555 void ac_compute_cmask(const struct radeon_info
*info
,
556 const struct ac_surf_config
*config
,
557 struct radeon_surf
*surf
)
559 unsigned pipe_interleave_bytes
= info
->pipe_interleave_bytes
;
560 unsigned num_pipes
= info
->num_tile_pipes
;
561 unsigned cl_width
, cl_height
;
563 if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
566 assert(info
->chip_class
<= GFX8
);
581 case 16: /* Hawaii */
590 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
592 unsigned width
= align(surf
->u
.legacy
.level
[0].nblk_x
, cl_width
*8);
593 unsigned height
= align(surf
->u
.legacy
.level
[0].nblk_y
, cl_height
*8);
594 unsigned slice_elements
= (width
* height
) / (8*8);
596 /* Each element of CMASK is a nibble. */
597 unsigned slice_bytes
= slice_elements
/ 2;
599 surf
->u
.legacy
.cmask_slice_tile_max
= (width
* height
) / (128*128);
600 if (surf
->u
.legacy
.cmask_slice_tile_max
)
601 surf
->u
.legacy
.cmask_slice_tile_max
-= 1;
605 num_layers
= config
->info
.depth
;
606 else if (config
->is_cube
)
609 num_layers
= config
->info
.array_size
;
611 surf
->cmask_alignment
= MAX2(256, base_align
);
612 surf
->cmask_size
= align(slice_bytes
, base_align
) * num_layers
;
616 * Fill in the tiling information in \p surf based on the given surface config.
618 * The following fields of \p surf must be initialized by the caller:
619 * blk_w, blk_h, bpe, flags.
621 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
622 const struct radeon_info
*info
,
623 const struct ac_surf_config
*config
,
624 enum radeon_surf_mode mode
,
625 struct radeon_surf
*surf
)
629 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
630 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
631 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
632 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
633 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
634 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
635 ADDR_TILEINFO AddrTileInfoIn
= {0};
636 ADDR_TILEINFO AddrTileInfoOut
= {0};
639 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
640 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
641 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
642 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
643 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
644 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
645 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
647 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
649 /* MSAA requires 2D tiling. */
650 if (config
->info
.samples
> 1)
651 mode
= RADEON_SURF_MODE_2D
;
653 /* DB doesn't support linear layouts. */
654 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
655 mode
< RADEON_SURF_MODE_1D
)
656 mode
= RADEON_SURF_MODE_1D
;
658 /* Set the requested tiling mode. */
660 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
661 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
663 case RADEON_SURF_MODE_1D
:
664 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
666 case RADEON_SURF_MODE_2D
:
667 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
673 /* The format must be set correctly for the allocation of compressed
674 * textures to work. In other cases, setting the bpp is sufficient.
679 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
682 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
689 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
692 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
693 MAX2(1, config
->info
.samples
);
694 AddrSurfInfoIn
.tileIndex
= -1;
696 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
697 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numFrags
=
698 MAX2(1, config
->info
.storage_samples
);
701 /* Set the micro tile type. */
702 if (surf
->flags
& RADEON_SURF_SCANOUT
)
703 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
704 else if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
705 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
707 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
709 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
710 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
711 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
712 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
713 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
714 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
716 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
717 * requested, because TC-compatible HTILE requires 2D tiling.
719 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
720 !AddrSurfInfoIn
.flags
.fmask
&&
721 config
->info
.samples
<= 1 &&
722 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
725 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
727 * - Mipmapped array textures have low performance (discovered by a closed
730 AddrSurfInfoIn
.flags
.dccCompatible
=
731 info
->chip_class
>= GFX8
&&
732 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
733 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
735 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
736 config
->info
.levels
== 1);
738 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
739 AddrSurfInfoIn
.flags
.compressZ
= !!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
741 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
742 * for Z and stencil. This can cause a number of problems which we work
745 * - a depth part that is incompatible with mipmapped texturing
746 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
747 * incorrect tiling applied to the stencil part, stencil buffer
748 * memory accesses that go out of bounds) even without mipmapping
750 * Some piglit tests that are prone to different types of related
752 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
753 * ./bin/framebuffer-blit-levels {draw,read} stencil
754 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
755 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
756 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
758 int stencil_tile_idx
= -1;
760 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
761 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
762 /* Compute stencilTileIdx that is compatible with the (depth)
763 * tileIdx. This degrades the depth surface if necessary to
764 * ensure that a matching stencilTileIdx exists. */
765 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
767 /* Keep the depth mip-tail compatible with texturing. */
768 AddrSurfInfoIn
.flags
.noStencil
= 1;
771 /* Set preferred macrotile parameters. This is usually required
772 * for shared resources. This is for 2D tiling only. */
773 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
774 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
775 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
776 /* If any of these parameters are incorrect, the calculation
778 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
779 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
780 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
781 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
782 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
783 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
784 AddrSurfInfoIn
.flags
.opt4Space
= 0;
785 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
787 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
788 * the tile index, because we are expected to know it if
789 * we know the other parameters.
791 * This is something that can easily be fixed in Addrlib.
792 * For now, just figure it out here.
793 * Note that only 2D_TILE_THIN1 is handled here.
795 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
796 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
798 if (info
->chip_class
== GFX6
) {
799 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
801 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
803 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
806 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
807 else if (surf
->bpe
== 2)
808 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
809 else if (surf
->bpe
== 4)
810 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
812 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
816 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
817 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
819 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
821 /* Addrlib doesn't set this if tileIndex is forced like above. */
822 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
826 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
827 surf
->num_dcc_levels
= 0;
830 surf
->dcc_alignment
= 1;
831 surf
->htile_size
= 0;
832 surf
->htile_slice_size
= 0;
833 surf
->htile_alignment
= 1;
835 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
836 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
838 /* Calculate texture layout information. */
840 for (level
= 0; level
< config
->info
.levels
; level
++) {
841 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
842 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
843 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
850 /* Check that we actually got a TC-compatible HTILE if
851 * we requested it (only for level 0, since we're not
852 * supporting HTILE on higher mip levels anyway). */
853 assert(AddrSurfInfoOut
.tcCompatible
||
854 !AddrSurfInfoIn
.flags
.tcCompatible
||
855 AddrSurfInfoIn
.flags
.matchStencilTileCfg
);
857 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
858 if (!AddrSurfInfoOut
.tcCompatible
) {
859 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
860 surf
->flags
&= ~RADEON_SURF_TC_COMPATIBLE_HTILE
;
863 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
864 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
865 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
867 assert(stencil_tile_idx
>= 0);
870 r
= gfx6_surface_settings(addrlib
, info
, config
,
871 &AddrSurfInfoOut
, surf
);
877 /* Calculate texture layout information for stencil. */
878 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
879 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
880 AddrSurfInfoIn
.bpp
= 8;
881 AddrSurfInfoIn
.flags
.depth
= 0;
882 AddrSurfInfoIn
.flags
.stencil
= 1;
883 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
884 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
885 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
887 for (level
= 0; level
< config
->info
.levels
; level
++) {
888 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
889 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
890 &AddrDccIn
, &AddrDccOut
,
895 /* DB uses the depth pitch for both stencil and depth. */
897 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
898 surf
->u
.legacy
.level
[level
].nblk_x
)
899 surf
->u
.legacy
.stencil_adjusted
= true;
901 surf
->u
.legacy
.level
[level
].nblk_x
=
902 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
907 r
= gfx6_surface_settings(addrlib
, info
, config
,
908 &AddrSurfInfoOut
, surf
);
913 /* For 2D modes only. */
914 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
915 surf
->u
.legacy
.stencil_tile_split
=
916 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
923 if (config
->info
.samples
>= 2 && AddrSurfInfoIn
.flags
.color
) {
924 ADDR_COMPUTE_FMASK_INFO_INPUT fin
= {0};
925 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
926 ADDR_TILEINFO fmask_tile_info
= {};
928 fin
.size
= sizeof(fin
);
929 fout
.size
= sizeof(fout
);
931 fin
.tileMode
= AddrSurfInfoOut
.tileMode
;
932 fin
.pitch
= AddrSurfInfoOut
.pitch
;
933 fin
.height
= config
->info
.height
;
934 fin
.numSlices
= AddrSurfInfoIn
.numSlices
;
935 fin
.numSamples
= AddrSurfInfoIn
.numSamples
;
936 fin
.numFrags
= AddrSurfInfoIn
.numFrags
;
938 fout
.pTileInfo
= &fmask_tile_info
;
940 r
= AddrComputeFmaskInfo(addrlib
, &fin
, &fout
);
944 surf
->fmask_size
= fout
.fmaskBytes
;
945 surf
->fmask_alignment
= fout
.baseAlign
;
946 surf
->fmask_tile_swizzle
= 0;
948 surf
->u
.legacy
.fmask
.slice_tile_max
=
949 (fout
.pitch
* fout
.height
) / 64;
950 if (surf
->u
.legacy
.fmask
.slice_tile_max
)
951 surf
->u
.legacy
.fmask
.slice_tile_max
-= 1;
953 surf
->u
.legacy
.fmask
.tiling_index
= fout
.tileIndex
;
954 surf
->u
.legacy
.fmask
.bankh
= fout
.pTileInfo
->bankHeight
;
955 surf
->u
.legacy
.fmask
.pitch_in_pixels
= fout
.pitch
;
957 /* Compute tile swizzle for FMASK. */
958 if (config
->info
.fmask_surf_index
&&
959 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
960 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin
= {0};
961 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout
= {0};
963 xin
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
964 xout
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
966 /* This counter starts from 1 instead of 0. */
967 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
968 xin
.tileIndex
= fout
.tileIndex
;
969 xin
.macroModeIndex
= fout
.macroModeIndex
;
970 xin
.pTileInfo
= fout
.pTileInfo
;
971 xin
.tileMode
= fin
.tileMode
;
973 int r
= AddrComputeBaseSwizzle(addrlib
, &xin
, &xout
);
977 assert(xout
.tileSwizzle
<=
978 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
979 surf
->fmask_tile_swizzle
= xout
.tileSwizzle
;
983 /* Recalculate the whole DCC miptree size including disabled levels.
984 * This is what addrlib does, but calling addrlib would be a lot more
987 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
988 /* The smallest miplevels that are never compressed by DCC
989 * still read the DCC buffer via TC if the base level uses DCC,
990 * and for some reason the DCC buffer needs to be larger if
991 * the miptree uses non-zero tile_swizzle. Otherwise there are
994 * "dcc_alignment * 4" was determined by trial and error.
996 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
997 surf
->dcc_alignment
* 4);
1000 /* Make sure HTILE covers the whole miptree, because the shader reads
1001 * TC-compatible HTILE even for levels where it's disabled by DB.
1003 if (surf
->htile_size
&& config
->info
.levels
> 1 &&
1004 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) {
1005 /* MSAA can't occur with levels > 1, so ignore the sample count. */
1006 const unsigned total_pixels
= surf
->surf_size
/ surf
->bpe
;
1007 const unsigned htile_block_size
= 8 * 8;
1008 const unsigned htile_element_size
= 4;
1010 surf
->htile_size
= (total_pixels
/ htile_block_size
) *
1012 surf
->htile_size
= align(surf
->htile_size
, surf
->htile_alignment
);
1015 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
1016 surf
->is_displayable
= surf
->is_linear
||
1017 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
1018 surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
;
1020 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1021 * used at the same time. This case is not currently expected to occur
1022 * because we don't use rotated. Enforce this restriction on all chips
1023 * to facilitate testing.
1025 if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
) {
1026 assert(!"rotate micro tile mode is unsupported");
1030 ac_compute_cmask(info
, config
, surf
);
1034 /* This is only called when expecting a tiled layout. */
1036 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
1037 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
1038 bool is_fmask
, AddrSwizzleMode
*swizzle_mode
)
1040 ADDR_E_RETURNCODE ret
;
1041 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
1042 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
1044 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
1045 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
1047 sin
.flags
= in
->flags
;
1048 sin
.resourceType
= in
->resourceType
;
1049 sin
.format
= in
->format
;
1050 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
1051 /* TODO: We could allow some of these: */
1052 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
1053 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
1054 sin
.forbiddenBlock
.linear
= 1; /* don't allow linear swizzle modes */
1056 sin
.width
= in
->width
;
1057 sin
.height
= in
->height
;
1058 sin
.numSlices
= in
->numSlices
;
1059 sin
.numMipLevels
= in
->numMipLevels
;
1060 sin
.numSamples
= in
->numSamples
;
1061 sin
.numFrags
= in
->numFrags
;
1064 sin
.flags
.display
= 0;
1065 sin
.flags
.color
= 0;
1066 sin
.flags
.fmask
= 1;
1069 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
1073 *swizzle_mode
= sout
.swizzleMode
;
1077 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
1078 const struct radeon_info
*info
,
1079 const struct ac_surf_config
*config
,
1080 struct radeon_surf
*surf
, bool compressed
,
1081 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
1083 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1084 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
1085 ADDR_E_RETURNCODE ret
;
1087 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
1088 out
.pMipInfo
= mip_info
;
1090 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
1094 if (in
->flags
.stencil
) {
1095 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
1096 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1097 out
.mipChainPitch
- 1;
1098 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
1099 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
1100 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
1104 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
1105 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1106 out
.mipChainPitch
- 1;
1108 /* CMASK fast clear uses these even if FMASK isn't allocated.
1109 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1111 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
1112 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
1114 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
1115 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
1116 surf
->u
.gfx9
.surf_height
= out
.height
;
1117 surf
->surf_size
= out
.surfSize
;
1118 surf
->surf_alignment
= out
.baseAlign
;
1120 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
1121 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
1122 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
1125 if (in
->flags
.depth
) {
1126 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
1129 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
1130 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
1132 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
1133 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
1135 hin
.hTileFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1136 hin
.hTileFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1137 hin
.depthFlags
= in
->flags
;
1138 hin
.swizzleMode
= in
->swizzleMode
;
1139 hin
.unalignedWidth
= in
->width
;
1140 hin
.unalignedHeight
= in
->height
;
1141 hin
.numSlices
= in
->numSlices
;
1142 hin
.numMipLevels
= in
->numMipLevels
;
1143 hin
.firstMipIdInTail
= out
.firstMipIdInTail
;
1145 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
1149 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
1150 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
1151 surf
->htile_size
= hout
.htileBytes
;
1152 surf
->htile_slice_size
= hout
.sliceSize
;
1153 surf
->htile_alignment
= hout
.baseAlign
;
1155 /* Compute tile swizzle for the color surface.
1156 * All *_X and *_T modes can use the swizzle.
1158 if (config
->info
.surf_index
&&
1159 in
->swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1160 !out
.mipChainInTail
&&
1161 !(surf
->flags
& RADEON_SURF_SHAREABLE
) &&
1162 !in
->flags
.display
) {
1163 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1164 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1166 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1167 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1169 xin
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
1170 xin
.flags
= in
->flags
;
1171 xin
.swizzleMode
= in
->swizzleMode
;
1172 xin
.resourceType
= in
->resourceType
;
1173 xin
.format
= in
->format
;
1174 xin
.numSamples
= in
->numSamples
;
1175 xin
.numFrags
= in
->numFrags
;
1177 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1181 assert(xout
.pipeBankXor
<=
1182 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
1183 surf
->tile_swizzle
= xout
.pipeBankXor
;
1187 if (!(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
1189 in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1190 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
1191 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
1192 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1194 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
1195 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
1196 dout
.pMipInfo
= meta_mip_info
;
1198 din
.dccKeyFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1199 din
.dccKeyFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1200 din
.colorFlags
= in
->flags
;
1201 din
.resourceType
= in
->resourceType
;
1202 din
.swizzleMode
= in
->swizzleMode
;
1204 din
.unalignedWidth
= in
->width
;
1205 din
.unalignedHeight
= in
->height
;
1206 din
.numSlices
= in
->numSlices
;
1207 din
.numFrags
= in
->numFrags
;
1208 din
.numMipLevels
= in
->numMipLevels
;
1209 din
.dataSurfaceSize
= out
.surfSize
;
1210 din
.firstMipIdInTail
= out
.firstMipIdInTail
;
1212 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1216 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
1217 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
1218 surf
->dcc_size
= dout
.dccRamSize
;
1219 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
1220 surf
->num_dcc_levels
= in
->numMipLevels
;
1222 /* Disable DCC for levels that are in the mip tail.
1224 * There are two issues that this is intended to
1227 * 1. Multiple mip levels may share a cache line. This
1228 * can lead to corruption when switching between
1229 * rendering to different mip levels because the
1230 * RBs don't maintain coherency.
1232 * 2. Texturing with metadata after rendering sometimes
1233 * fails with corruption, probably for a similar
1236 * Working around these issues for all levels in the
1237 * mip tail may be overly conservative, but it's what
1240 * Alternative solutions that also work but are worse:
1241 * - Disable DCC entirely.
1242 * - Flush TC L2 after rendering.
1244 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1245 if (meta_mip_info
[i
].inMiptail
) {
1246 surf
->num_dcc_levels
= i
;
1251 if (!surf
->num_dcc_levels
)
1254 surf
->u
.gfx9
.display_dcc_size
= surf
->dcc_size
;
1255 surf
->u
.gfx9
.display_dcc_alignment
= surf
->dcc_alignment
;
1256 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1258 /* Compute displayable DCC. */
1259 if (in
->flags
.display
&&
1260 surf
->num_dcc_levels
&&
1261 info
->use_display_dcc_with_retile_blit
) {
1262 /* Compute displayable DCC info. */
1263 din
.dccKeyFlags
.pipeAligned
= 0;
1264 din
.dccKeyFlags
.rbAligned
= 0;
1266 assert(din
.numSlices
== 1);
1267 assert(din
.numMipLevels
== 1);
1268 assert(din
.numFrags
== 1);
1269 assert(surf
->tile_swizzle
== 0);
1270 assert(surf
->u
.gfx9
.dcc
.pipe_aligned
||
1271 surf
->u
.gfx9
.dcc
.rb_aligned
);
1273 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1277 surf
->u
.gfx9
.display_dcc_size
= dout
.dccRamSize
;
1278 surf
->u
.gfx9
.display_dcc_alignment
= dout
.dccRamBaseAlign
;
1279 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1280 assert(surf
->u
.gfx9
.display_dcc_size
<= surf
->dcc_size
);
1282 /* Compute address mapping from non-displayable to displayable DCC. */
1283 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin
= {};
1284 addrin
.size
= sizeof(addrin
);
1285 addrin
.colorFlags
.color
= 1;
1286 addrin
.swizzleMode
= din
.swizzleMode
;
1287 addrin
.resourceType
= din
.resourceType
;
1288 addrin
.bpp
= din
.bpp
;
1289 addrin
.unalignedWidth
= din
.unalignedWidth
;
1290 addrin
.unalignedHeight
= din
.unalignedHeight
;
1291 addrin
.numSlices
= 1;
1292 addrin
.numMipLevels
= 1;
1293 addrin
.numFrags
= 1;
1295 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout
= {};
1296 addrout
.size
= sizeof(addrout
);
1298 surf
->u
.gfx9
.dcc_retile_num_elements
=
1299 DIV_ROUND_UP(in
->width
, dout
.compressBlkWidth
) *
1300 DIV_ROUND_UP(in
->height
, dout
.compressBlkHeight
) * 2;
1301 /* Align the size to 4 (for the compute shader). */
1302 surf
->u
.gfx9
.dcc_retile_num_elements
=
1303 align(surf
->u
.gfx9
.dcc_retile_num_elements
, 4);
1305 surf
->u
.gfx9
.dcc_retile_map
=
1306 malloc(surf
->u
.gfx9
.dcc_retile_num_elements
* 4);
1307 if (!surf
->u
.gfx9
.dcc_retile_map
)
1308 return ADDR_OUTOFMEMORY
;
1311 surf
->u
.gfx9
.dcc_retile_use_uint16
= true;
1313 for (unsigned y
= 0; y
< in
->height
; y
+= dout
.compressBlkHeight
) {
1316 for (unsigned x
= 0; x
< in
->width
; x
+= dout
.compressBlkWidth
) {
1319 /* Compute src DCC address */
1320 addrin
.dccKeyFlags
.pipeAligned
= surf
->u
.gfx9
.dcc
.pipe_aligned
;
1321 addrin
.dccKeyFlags
.rbAligned
= surf
->u
.gfx9
.dcc
.rb_aligned
;
1324 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1328 surf
->u
.gfx9
.dcc_retile_map
[index
* 2] = addrout
.addr
;
1329 if (addrout
.addr
> USHRT_MAX
)
1330 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1332 /* Compute dst DCC address */
1333 addrin
.dccKeyFlags
.pipeAligned
= 0;
1334 addrin
.dccKeyFlags
.rbAligned
= 0;
1337 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1341 surf
->u
.gfx9
.dcc_retile_map
[index
* 2 + 1] = addrout
.addr
;
1342 if (addrout
.addr
> USHRT_MAX
)
1343 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1345 assert(index
* 2 + 1 < surf
->u
.gfx9
.dcc_retile_num_elements
);
1349 /* Fill the remaining pairs with the last one (for the compute shader). */
1350 for (unsigned i
= index
* 2; i
< surf
->u
.gfx9
.dcc_retile_num_elements
; i
++)
1351 surf
->u
.gfx9
.dcc_retile_map
[i
] = surf
->u
.gfx9
.dcc_retile_map
[i
- 2];
1356 if (in
->numSamples
> 1) {
1357 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
1358 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1360 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1361 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1363 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
,
1364 true, &fin
.swizzleMode
);
1368 fin
.unalignedWidth
= in
->width
;
1369 fin
.unalignedHeight
= in
->height
;
1370 fin
.numSlices
= in
->numSlices
;
1371 fin
.numSamples
= in
->numSamples
;
1372 fin
.numFrags
= in
->numFrags
;
1374 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1378 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1379 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1380 surf
->fmask_size
= fout
.fmaskBytes
;
1381 surf
->fmask_alignment
= fout
.baseAlign
;
1383 /* Compute tile swizzle for the FMASK surface. */
1384 if (config
->info
.fmask_surf_index
&&
1385 fin
.swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1386 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
1387 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1388 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1390 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1391 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1393 /* This counter starts from 1 instead of 0. */
1394 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
1395 xin
.flags
= in
->flags
;
1396 xin
.swizzleMode
= fin
.swizzleMode
;
1397 xin
.resourceType
= in
->resourceType
;
1398 xin
.format
= in
->format
;
1399 xin
.numSamples
= in
->numSamples
;
1400 xin
.numFrags
= in
->numFrags
;
1402 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1406 assert(xout
.pipeBankXor
<=
1407 u_bit_consecutive(0, sizeof(surf
->fmask_tile_swizzle
) * 8));
1408 surf
->fmask_tile_swizzle
= xout
.pipeBankXor
;
1413 if (in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1414 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1415 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1417 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1418 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1420 if (in
->numSamples
> 1) {
1421 /* FMASK is always aligned. */
1422 cin
.cMaskFlags
.pipeAligned
= 1;
1423 cin
.cMaskFlags
.rbAligned
= 1;
1425 cin
.cMaskFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1426 cin
.cMaskFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1428 cin
.colorFlags
= in
->flags
;
1429 cin
.resourceType
= in
->resourceType
;
1430 cin
.unalignedWidth
= in
->width
;
1431 cin
.unalignedHeight
= in
->height
;
1432 cin
.numSlices
= in
->numSlices
;
1434 if (in
->numSamples
> 1)
1435 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1437 cin
.swizzleMode
= in
->swizzleMode
;
1439 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1443 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1444 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1445 surf
->cmask_size
= cout
.cmaskBytes
;
1446 surf
->cmask_alignment
= cout
.baseAlign
;
1453 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1454 const struct radeon_info
*info
,
1455 const struct ac_surf_config
*config
,
1456 enum radeon_surf_mode mode
,
1457 struct radeon_surf
*surf
)
1460 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1463 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1465 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1467 /* The format must be set correctly for the allocation of compressed
1468 * textures to work. In other cases, setting the bpp is sufficient. */
1470 switch (surf
->bpe
) {
1472 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1475 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1481 switch (surf
->bpe
) {
1483 assert(!(surf
->flags
& RADEON_SURF_ZBUFFER
));
1484 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1487 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1488 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1489 AddrSurfInfoIn
.format
= ADDR_FMT_16
;
1492 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1493 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1494 AddrSurfInfoIn
.format
= ADDR_FMT_32
;
1497 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1498 AddrSurfInfoIn
.format
= ADDR_FMT_32_32
;
1501 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1502 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32
;
1505 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1506 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32_32
;
1511 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1514 bool is_color_surface
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
1515 AddrSurfInfoIn
.flags
.color
= is_color_surface
&&
1516 !(surf
->flags
& RADEON_SURF_NO_RENDER_TARGET
);
1517 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1518 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
1519 /* flags.texture currently refers to TC-compatible HTILE */
1520 AddrSurfInfoIn
.flags
.texture
= is_color_surface
||
1521 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1522 AddrSurfInfoIn
.flags
.opt4space
= 1;
1524 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1525 AddrSurfInfoIn
.numSamples
= MAX2(1, config
->info
.samples
);
1526 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1528 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
))
1529 AddrSurfInfoIn
.numFrags
= MAX2(1, config
->info
.storage_samples
);
1531 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1532 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1533 * must sample 1D textures as 2D. */
1535 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1537 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1539 AddrSurfInfoIn
.width
= config
->info
.width
;
1540 AddrSurfInfoIn
.height
= config
->info
.height
;
1543 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1544 else if (config
->is_cube
)
1545 AddrSurfInfoIn
.numSlices
= 6;
1547 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1549 /* This is propagated to HTILE/DCC/CMASK. */
1550 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 0;
1551 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 0;
1553 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1554 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1556 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1557 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1558 * after rendering, so PIPE_ALIGNED=1 is recommended.
1560 if (info
->use_display_dcc_unaligned
&& is_color_surface
&&
1561 AddrSurfInfoIn
.flags
.display
) {
1562 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 1;
1563 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 1;
1567 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1568 assert(config
->info
.samples
<= 1);
1569 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1570 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1573 case RADEON_SURF_MODE_1D
:
1574 case RADEON_SURF_MODE_2D
:
1575 if (surf
->flags
& RADEON_SURF_IMPORTED
) {
1576 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1580 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1581 false, &AddrSurfInfoIn
.swizzleMode
);
1590 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1591 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1593 surf
->num_dcc_levels
= 0;
1594 surf
->surf_size
= 0;
1595 surf
->fmask_size
= 0;
1597 surf
->htile_size
= 0;
1598 surf
->htile_slice_size
= 0;
1599 surf
->u
.gfx9
.surf_offset
= 0;
1600 surf
->u
.gfx9
.stencil_offset
= 0;
1601 surf
->cmask_size
= 0;
1602 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1603 surf
->u
.gfx9
.dcc_retile_num_elements
= 0;
1604 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1606 /* Calculate texture layout information. */
1607 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1612 /* Calculate texture layout information for stencil. */
1613 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1614 AddrSurfInfoIn
.flags
.stencil
= 1;
1615 AddrSurfInfoIn
.bpp
= 8;
1616 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1618 if (!AddrSurfInfoIn
.flags
.depth
) {
1619 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1620 false, &AddrSurfInfoIn
.swizzleMode
);
1624 AddrSurfInfoIn
.flags
.depth
= 0;
1626 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1632 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1634 /* Query whether the surface is displayable. */
1635 bool displayable
= false;
1636 if (!config
->is_3d
&& !config
->is_cube
) {
1637 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1638 surf
->bpe
* 8, &displayable
);
1642 /* Display needs unaligned DCC. */
1643 if (info
->use_display_dcc_unaligned
&&
1644 surf
->num_dcc_levels
&&
1645 (surf
->u
.gfx9
.dcc
.pipe_aligned
||
1646 surf
->u
.gfx9
.dcc
.rb_aligned
))
1647 displayable
= false;
1649 surf
->is_displayable
= displayable
;
1651 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1653 case ADDR_SW_256B_S
:
1655 case ADDR_SW_64KB_S
:
1657 case ADDR_SW_64KB_S_T
:
1658 case ADDR_SW_4KB_S_X
:
1659 case ADDR_SW_64KB_S_X
:
1660 case ADDR_SW_VAR_S_X
:
1661 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1665 case ADDR_SW_LINEAR
:
1666 case ADDR_SW_256B_D
:
1668 case ADDR_SW_64KB_D
:
1670 case ADDR_SW_64KB_D_T
:
1671 case ADDR_SW_4KB_D_X
:
1672 case ADDR_SW_64KB_D_X
:
1673 case ADDR_SW_VAR_D_X
:
1674 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1678 case ADDR_SW_256B_R
:
1680 case ADDR_SW_64KB_R
:
1682 case ADDR_SW_64KB_R_T
:
1683 case ADDR_SW_4KB_R_X
:
1684 case ADDR_SW_64KB_R_X
:
1685 case ADDR_SW_VAR_R_X
:
1686 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1687 * used at the same time. This case is not currently expected to occur
1688 * because we don't use rotated. Enforce this restriction on all chips
1689 * to facilitate testing.
1691 assert(!"rotate micro tile mode is unsupported");
1697 case ADDR_SW_64KB_Z
:
1699 case ADDR_SW_64KB_Z_T
:
1700 case ADDR_SW_4KB_Z_X
:
1701 case ADDR_SW_64KB_Z_X
:
1702 case ADDR_SW_VAR_Z_X
:
1703 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1713 free(surf
->u
.gfx9
.dcc_retile_map
);
1714 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1718 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1719 const struct ac_surf_config
*config
,
1720 enum radeon_surf_mode mode
,
1721 struct radeon_surf
*surf
)
1725 r
= surf_config_sanity(config
, surf
->flags
);
1729 if (info
->chip_class
>= GFX9
)
1730 return gfx9_compute_surface(addrlib
, info
, config
, mode
, surf
);
1732 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);