src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30
  31 #include "amd_family.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /* Forward declarations. */
  38 typedef void* ADDR_HANDLE;
  39
  40 struct amdgpu_gpu_info;
  41 struct radeon_info;
  42
  43 #define RADEON_SURF_MAX_LEVELS                  15
  44
  45 enum radeon_surf_mode {
  46     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  47     RADEON_SURF_MODE_1D = 2,
  48     RADEON_SURF_MODE_2D = 3,
  49 };
  50
  51 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  52 enum radeon_micro_mode {
  53     RADEON_MICRO_MODE_DISPLAY = 0,
  54     RADEON_MICRO_MODE_THIN = 1,
  55     RADEON_MICRO_MODE_DEPTH = 2,
  56     RADEON_MICRO_MODE_ROTATED = 3,
  57 };
  58
  59 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  60 #define RADEON_SURF_SCANOUT                     (1 << 16)
  61 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  62 #define RADEON_SURF_SBUFFER                     (1 << 18)
  63 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  64 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  65 #define RADEON_SURF_FMASK                       (1 << 21)
  66 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  67 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  68 #define RADEON_SURF_IMPORTED                    (1 << 24)
  69 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  70 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  71
  72 struct legacy_surf_level {
  73     uint64_t                    offset;
  74     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
  75     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
  76     uint32_t                    dcc_fast_clear_size;
  77     unsigned                    nblk_x:15;
  78     unsigned                    nblk_y:15;
  79     enum radeon_surf_mode       mode:2;
  80 };
  81
  82 struct legacy_surf_fmask {
  83     unsigned slice_tile_max; /* max 4M */
  84     uint8_t tiling_index;    /* max 31 */
  85     uint8_t bankh;           /* max 8 */
  86     uint16_t pitch_in_pixels;
  87 };
  88
  89 struct legacy_surf_layout {
  90     unsigned                    bankw:4;  /* max 8 */
  91     unsigned                    bankh:4;  /* max 8 */
  92     unsigned                    mtilea:4; /* max 8 */
  93     unsigned                    tile_split:13;         /* max 4K */
  94     unsigned                    stencil_tile_split:13; /* max 4K */
  95     unsigned                    pipe_config:5;      /* max 17 */
  96     unsigned                    num_banks:5;        /* max 16 */
  97     unsigned                    macro_tile_index:4; /* max 15 */
  98
  99     /* Whether the depth miptree or stencil miptree as used by the DB are
 100      * adjusted from their TC compatible form to ensure depth/stencil
 101      * compatibility. If either is true, the corresponding plane cannot be
 102      * sampled from.
 103      */
 104     unsigned                    depth_adjusted:1;
 105     unsigned                    stencil_adjusted:1;
 106
 107     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 108     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 109     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 110     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 111     struct legacy_surf_fmask    fmask;
 112     unsigned                    cmask_slice_tile_max;
 113 };
 114
 115 /* Same as addrlib - AddrResourceType. */
 116 enum gfx9_resource_type {
 117     RADEON_RESOURCE_1D = 0,
 118     RADEON_RESOURCE_2D,
 119     RADEON_RESOURCE_3D,
 120 };
 121
 122 struct gfx9_surf_flags {
 123     uint16_t                    swizzle_mode; /* tile mode */
 124     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 125 };
 126
 127 struct gfx9_surf_meta_flags {
 128     unsigned                    rb_aligned:1;   /* optimal for RBs */
 129     unsigned                    pipe_aligned:1; /* optimal for TC */
 130 };
 131
 132 struct gfx9_surf_layout {
 133     struct gfx9_surf_flags      surf;    /* color or depth surface */
 134     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 135     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 136
 137     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 138     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 139     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 140
 141     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 142     uint16_t                    surf_pitch; /* in blocks */
 143     uint16_t                    surf_height;
 144
 145     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 146     /* The size of the 2D plane containing all mipmap levels. */
 147     uint64_t                    surf_slice_size;
 148     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 149     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 150
 151     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 152
 153     uint64_t                    stencil_offset; /* separate stencil */
 154 };
 155
 156 struct radeon_surf {
 157     /* Format properties. */
 158     unsigned                    blk_w:4;
 159     unsigned                    blk_h:4;
 160     unsigned                    bpe:5;
 161     /* Number of mipmap levels where DCC is enabled starting from level 0.
 162      * Non-zero levels may be disabled due to alignment constraints, but not
 163      * the first level.
 164      */
 165     unsigned                    num_dcc_levels:4;
 166     unsigned                    is_linear:1;
 167     unsigned                    has_stencil:1;
 168     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
 169     unsigned                    is_displayable:1;
 170     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 171     unsigned                    micro_tile_mode:3;
 172     uint32_t                    flags;
 173
 174     /* These are return values. Some of them can be set by the caller, but
 175      * they will be treated as hints (e.g. bankw, bankh) and might be
 176      * changed by the calculator.
 177      */
 178
 179     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 180      * The value is the same for all mipmap levels. Supported tile modes:
 181      * - GFX6: Only macro tiling.
 182      * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
 183      *   tail.
 184      *
 185      * Only these surfaces are allowed to set it:
 186      * - color (if it doesn't have to be displayable)
 187      * - DCC (same tile swizzle as color)
 188      * - FMASK
 189      * - CMASK if it's TC-compatible or if the gen is GFX9
 190      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 191      */
 192     uint8_t                     tile_swizzle;
 193     uint8_t                     fmask_tile_swizzle;
 194
 195     uint64_t                    surf_size;
 196     uint64_t                    fmask_size;
 197     uint32_t                    surf_alignment;
 198     uint32_t                    fmask_alignment;
 199
 200     /* DCC and HTILE are very small. */
 201     uint32_t                    dcc_size;
 202     uint32_t                    dcc_alignment;
 203
 204     uint32_t                    htile_size;
 205     uint32_t                    htile_slice_size;
 206     uint32_t                    htile_alignment;
 207
 208     uint32_t                    cmask_size;
 209     uint32_t                    cmask_alignment;
 210
 211     union {
 212         /* R600-VI return values.
 213          *
 214          * Some of them can be set by the caller if certain parameters are
 215          * desirable. The allocator will try to obey them.
 216          */
 217         struct legacy_surf_layout legacy;
 218
 219         /* GFX9+ return values. */
 220         struct gfx9_surf_layout gfx9;
 221     } u;
 222 };
 223
 224 struct ac_surf_info {
 225         uint32_t width;
 226         uint32_t height;
 227         uint32_t depth;
 228         uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
 229         uint8_t color_samples; /* For color: color samples */
 230         uint8_t levels;
 231         uint8_t num_channels; /* heuristic for displayability */
 232         uint16_t array_size;
 233         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 234         uint32_t *fmask_surf_index;
 235 };
 236
 237 struct ac_surf_config {
 238         struct ac_surf_info info;
 239         unsigned is_3d : 1;
 240         unsigned is_cube : 1;
 241 };
 242
 243 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 244                                const struct amdgpu_gpu_info *amdinfo,
 245                                uint64_t *max_alignment);
 246
 247 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 248                        const struct ac_surf_config * config,
 249                        enum radeon_surf_mode mode,
 250                        struct radeon_surf *surf);
 251
 252 void ac_compute_cmask(const struct radeon_info *info,
 253                       const struct ac_surf_config *config,
 254                       struct radeon_surf *surf);
 255
 256 #ifdef __cplusplus
 257 }
 258 #endif
 259
 260 #endif /* AC_SURFACE_H */