src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30 #include <stdbool.h>
  31
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 /* Forward declarations. */
  39 typedef void* ADDR_HANDLE;
  40
  41 struct amdgpu_gpu_info;
  42 struct radeon_info;
  43
  44 #define RADEON_SURF_MAX_LEVELS                  15
  45
  46 enum radeon_surf_mode {
  47     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  48     RADEON_SURF_MODE_1D = 2,
  49     RADEON_SURF_MODE_2D = 3,
  50 };
  51
  52 /* This describes D/S/Z/R swizzle modes.
  53  * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order.
  54  */
  55 enum radeon_micro_mode {
  56     RADEON_MICRO_MODE_DISPLAY = 0,
  57     RADEON_MICRO_MODE_STANDARD = 1,
  58     RADEON_MICRO_MODE_DEPTH = 2,
  59     RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */
  60 };
  61
  62 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  63 #define RADEON_SURF_SCANOUT                     (1 << 16)
  64 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  65 #define RADEON_SURF_SBUFFER                     (1 << 18)
  66 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  67 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  68 #define RADEON_SURF_FMASK                       (1 << 21)
  69 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  70 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  71 #define RADEON_SURF_IMPORTED                    (1 << 24)
  72 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  73 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  74 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
  75 #define RADEON_SURF_FORCE_SWIZZLE_MODE          (1 << 28)
  76 #define RADEON_SURF_NO_FMASK                    (1 << 29)
  77 #define RADEON_SURF_NO_HTILE                    (1 << 30)
  78 #define RADEON_SURF_FORCE_MICRO_TILE_MODE       (1u << 31)
  79
  80 struct legacy_surf_level {
  81     uint64_t                    offset;
  82     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
  83     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
  84     uint32_t                    dcc_fast_clear_size;
  85     uint32_t                    dcc_slice_fast_clear_size;
  86     unsigned                    nblk_x:15;
  87     unsigned                    nblk_y:15;
  88     enum radeon_surf_mode       mode:2;
  89 };
  90
  91 struct legacy_surf_fmask {
  92     unsigned slice_tile_max; /* max 4M */
  93     uint8_t tiling_index;    /* max 31 */
  94     uint8_t bankh;           /* max 8 */
  95     uint16_t pitch_in_pixels;
  96     uint64_t slice_size;
  97 };
  98
  99 struct legacy_surf_layout {
 100     unsigned                    bankw:4;  /* max 8 */
 101     unsigned                    bankh:4;  /* max 8 */
 102     unsigned                    mtilea:4; /* max 8 */
 103     unsigned                    tile_split:13;         /* max 4K */
 104     unsigned                    stencil_tile_split:13; /* max 4K */
 105     unsigned                    pipe_config:5;      /* max 17 */
 106     unsigned                    num_banks:5;        /* max 16 */
 107     unsigned                    macro_tile_index:4; /* max 15 */
 108
 109     /* Whether the depth miptree or stencil miptree as used by the DB are
 110      * adjusted from their TC compatible form to ensure depth/stencil
 111      * compatibility. If either is true, the corresponding plane cannot be
 112      * sampled from.
 113      */
 114     unsigned                    depth_adjusted:1;
 115     unsigned                    stencil_adjusted:1;
 116
 117     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 118     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 119     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 120     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 121     struct legacy_surf_fmask    fmask;
 122     unsigned                    cmask_slice_tile_max;
 123 };
 124
 125 /* Same as addrlib - AddrResourceType. */
 126 enum gfx9_resource_type {
 127     RADEON_RESOURCE_1D = 0,
 128     RADEON_RESOURCE_2D,
 129     RADEON_RESOURCE_3D,
 130 };
 131
 132 struct gfx9_surf_flags {
 133     uint16_t                    swizzle_mode; /* tile mode */
 134     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 135 };
 136
 137 struct gfx9_surf_meta_flags {
 138     unsigned                    rb_aligned:1;   /* optimal for RBs */
 139     unsigned                    pipe_aligned:1; /* optimal for TC */
 140 };
 141
 142 struct gfx9_surf_layout {
 143     struct gfx9_surf_flags      surf;    /* color or depth surface */
 144     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 145     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 146
 147     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 148     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 149     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 150
 151     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 152     uint16_t                    surf_pitch; /* in blocks */
 153     uint16_t                    surf_height;
 154
 155     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 156     /* The size of the 2D plane containing all mipmap levels. */
 157     uint64_t                    surf_slice_size;
 158     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 159     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 160     /* Mipmap level pitch in elements. Only valid for LINEAR. */
 161     uint16_t                    pitch[RADEON_SURF_MAX_LEVELS];
 162
 163     uint64_t                    stencil_offset; /* separate stencil */
 164
 165     /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
 166      * The 3D engine doesn't support that layout except for chips with 1 RB.
 167      * All other chips must set rb_aligned=1.
 168      * A compute shader needs to convert from aligned DCC to unaligned.
 169      */
 170     uint32_t                    display_dcc_size;
 171     uint32_t                    display_dcc_alignment;
 172     uint16_t                    display_dcc_pitch_max;  /* (mip chain pitch - 1) */
 173     bool                        dcc_retile_use_uint16; /* if all values fit into uint16_t */
 174     uint32_t                    dcc_retile_num_elements;
 175     uint32_t                    *dcc_retile_map;
 176 };
 177
 178 struct radeon_surf {
 179     /* Format properties. */
 180     unsigned                    blk_w:4;
 181     unsigned                    blk_h:4;
 182     unsigned                    bpe:5;
 183     /* Number of mipmap levels where DCC is enabled starting from level 0.
 184      * Non-zero levels may be disabled due to alignment constraints, but not
 185      * the first level.
 186      */
 187     unsigned                    num_dcc_levels:4;
 188     unsigned                    is_linear:1;
 189     unsigned                    has_stencil:1;
 190     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
 191     unsigned                    is_displayable:1;
 192     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 193     unsigned                    micro_tile_mode:3;
 194     uint32_t                    flags;
 195
 196     /* These are return values. Some of them can be set by the caller, but
 197      * they will be treated as hints (e.g. bankw, bankh) and might be
 198      * changed by the calculator.
 199      */
 200
 201     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 202      * The value is the same for all mipmap levels. Supported tile modes:
 203      * - GFX6: Only macro tiling.
 204      * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
 205      *   tail.
 206      *
 207      * Only these surfaces are allowed to set it:
 208      * - color (if it doesn't have to be displayable)
 209      * - DCC (same tile swizzle as color)
 210      * - FMASK
 211      * - CMASK if it's TC-compatible or if the gen is GFX9
 212      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 213      */
 214     uint8_t                     tile_swizzle;
 215     uint8_t                     fmask_tile_swizzle;
 216
 217     uint64_t                    surf_size;
 218     uint64_t                    fmask_size;
 219     uint32_t                    surf_alignment;
 220     uint32_t                    fmask_alignment;
 221
 222     /* DCC and HTILE are very small. */
 223     uint32_t                    dcc_size;
 224     uint32_t                    dcc_slice_size;
 225     uint32_t                    dcc_alignment;
 226
 227     uint32_t                    htile_size;
 228     uint32_t                    htile_slice_size;
 229     uint32_t                    htile_alignment;
 230
 231     uint32_t                    cmask_size;
 232     uint32_t                    cmask_slice_size;
 233     uint32_t                    cmask_alignment;
 234
 235     /* All buffers combined. */
 236     uint64_t                    htile_offset;
 237     uint64_t                    fmask_offset;
 238     uint64_t                    cmask_offset;
 239     uint64_t                    dcc_offset;
 240     uint64_t                    display_dcc_offset;
 241     uint64_t                    dcc_retile_map_offset;
 242     uint64_t                    total_size;
 243
 244     union {
 245         /* Return values for GFX8 and older.
 246          *
 247          * Some of them can be set by the caller if certain parameters are
 248          * desirable. The allocator will try to obey them.
 249          */
 250         struct legacy_surf_layout legacy;
 251
 252         /* GFX9+ return values. */
 253         struct gfx9_surf_layout gfx9;
 254     } u;
 255 };
 256
 257 struct ac_surf_info {
 258         uint32_t width;
 259         uint32_t height;
 260         uint32_t depth;
 261         uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
 262         uint8_t storage_samples; /* For color: allocated samples */
 263         uint8_t levels;
 264         uint8_t num_channels; /* heuristic for displayability */
 265         uint16_t array_size;
 266         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 267         uint32_t *fmask_surf_index;
 268 };
 269
 270 struct ac_surf_config {
 271         struct ac_surf_info info;
 272         unsigned is_1d : 1;
 273         unsigned is_3d : 1;
 274         unsigned is_cube : 1;
 275 };
 276
 277 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 278                                const struct amdgpu_gpu_info *amdinfo,
 279                                uint64_t *max_alignment);
 280
 281 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 282                        const struct ac_surf_config * config,
 283                        enum radeon_surf_mode mode,
 284                        struct radeon_surf *surf);
 285
 286 #ifdef __cplusplus
 287 }
 288 #endif
 289
 290 #endif /* AC_SURFACE_H */