src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30
  31 #include "amd_family.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /* Forward declarations. */
  38 typedef void* ADDR_HANDLE;
  39
  40 struct amdgpu_gpu_info;
  41 struct radeon_info;
  42
  43 #define RADEON_SURF_MAX_LEVELS                  15
  44
  45 enum radeon_surf_mode {
  46     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  47     RADEON_SURF_MODE_1D = 2,
  48     RADEON_SURF_MODE_2D = 3,
  49 };
  50
  51 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  52 enum radeon_micro_mode {
  53     RADEON_MICRO_MODE_DISPLAY = 0,
  54     RADEON_MICRO_MODE_THIN = 1,
  55     RADEON_MICRO_MODE_DEPTH = 2,
  56     RADEON_MICRO_MODE_ROTATED = 3,
  57 };
  58
  59 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  60 #define RADEON_SURF_SCANOUT                     (1 << 16)
  61 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  62 #define RADEON_SURF_SBUFFER                     (1 << 18)
  63 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  64 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  65 #define RADEON_SURF_FMASK                       (1 << 21)
  66 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  67 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  68 #define RADEON_SURF_IMPORTED                    (1 << 24)
  69 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  70 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  71
  72 struct legacy_surf_level {
  73     uint64_t                    offset;
  74     uint64_t                    slice_size;
  75     uint64_t                    dcc_offset;
  76     uint64_t                    dcc_fast_clear_size;
  77     uint16_t                    nblk_x;
  78     uint16_t                    nblk_y;
  79     enum radeon_surf_mode       mode;
  80 };
  81
  82 struct legacy_surf_layout {
  83     unsigned                    bankw:4;  /* max 8 */
  84     unsigned                    bankh:4;  /* max 8 */
  85     unsigned                    mtilea:4; /* max 8 */
  86     unsigned                    tile_split:13;         /* max 4K */
  87     unsigned                    stencil_tile_split:13; /* max 4K */
  88     unsigned                    pipe_config:5;      /* max 17 */
  89     unsigned                    num_banks:5;        /* max 16 */
  90     unsigned                    macro_tile_index:4; /* max 15 */
  91
  92     /* Whether the depth miptree or stencil miptree as used by the DB are
  93      * adjusted from their TC compatible form to ensure depth/stencil
  94      * compatibility. If either is true, the corresponding plane cannot be
  95      * sampled from.
  96      */
  97     unsigned                    depth_adjusted:1;
  98     unsigned                    stencil_adjusted:1;
  99
 100     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 101     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 102     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 103     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 104 };
 105
 106 /* Same as addrlib - AddrResourceType. */
 107 enum gfx9_resource_type {
 108     RADEON_RESOURCE_1D = 0,
 109     RADEON_RESOURCE_2D,
 110     RADEON_RESOURCE_3D,
 111 };
 112
 113 struct gfx9_surf_flags {
 114     uint16_t                    swizzle_mode; /* tile mode */
 115     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 116 };
 117
 118 struct gfx9_surf_meta_flags {
 119     unsigned                    rb_aligned:1;   /* optimal for RBs */
 120     unsigned                    pipe_aligned:1; /* optimal for TC */
 121 };
 122
 123 struct gfx9_surf_layout {
 124     struct gfx9_surf_flags      surf;    /* color or depth surface */
 125     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 126     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 127
 128     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 129     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 130     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 131
 132     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 133     uint16_t                    surf_pitch; /* in blocks */
 134     uint16_t                    surf_height;
 135
 136     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 137     /* The size of the 2D plane containing all mipmap levels. */
 138     uint64_t                    surf_slice_size;
 139     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 140     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 141
 142     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 143
 144     uint64_t                    stencil_offset; /* separate stencil */
 145     uint64_t                    fmask_size;
 146     uint64_t                    cmask_size;
 147
 148     uint32_t                    fmask_alignment;
 149     uint32_t                    cmask_alignment;
 150 };
 151
 152 struct radeon_surf {
 153     /* Format properties. */
 154     unsigned                    blk_w:4;
 155     unsigned                    blk_h:4;
 156     unsigned                    bpe:5;
 157     /* Number of mipmap levels where DCC is enabled starting from level 0.
 158      * Non-zero levels may be disabled due to alignment constraints, but not
 159      * the first level.
 160      */
 161     unsigned                    num_dcc_levels:4;
 162     unsigned                    is_linear:1;
 163     unsigned                    has_stencil:1;
 164     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 165     unsigned                    micro_tile_mode:3;
 166     uint32_t                    flags;
 167
 168     /* These are return values. Some of them can be set by the caller, but
 169      * they will be treated as hints (e.g. bankw, bankh) and might be
 170      * changed by the calculator.
 171      */
 172
 173     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 174      * The value is the same for all mipmap levels. Supported tile modes:
 175      * - GFX6: Only macro tiling.
 176      * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
 177      *
 178      * Only these surfaces are allowed to set it:
 179      * - color (if it doesn't have to be displayable)
 180      * - DCC (same tile swizzle as color)
 181      * - FMASK
 182      * - CMASK if it's TC-compatible or if the gen is GFX9
 183      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 184      */
 185     uint8_t                     tile_swizzle;
 186
 187     uint64_t                    surf_size;
 188     uint64_t                    dcc_size;
 189     uint64_t                    htile_size;
 190
 191     uint32_t                    htile_slice_size;
 192
 193     uint32_t                    surf_alignment;
 194     uint32_t                    dcc_alignment;
 195     uint32_t                    htile_alignment;
 196
 197     union {
 198         /* R600-VI return values.
 199          *
 200          * Some of them can be set by the caller if certain parameters are
 201          * desirable. The allocator will try to obey them.
 202          */
 203         struct legacy_surf_layout legacy;
 204
 205         /* GFX9+ return values. */
 206         struct gfx9_surf_layout gfx9;
 207     } u;
 208 };
 209
 210 struct ac_surf_info {
 211         uint32_t width;
 212         uint32_t height;
 213         uint32_t depth;
 214         uint8_t samples;
 215         uint8_t levels;
 216         uint16_t array_size;
 217         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 218 };
 219
 220 struct ac_surf_config {
 221         struct ac_surf_info info;
 222         unsigned is_3d : 1;
 223         unsigned is_cube : 1;
 224 };
 225
 226 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 227                                const struct amdgpu_gpu_info *amdinfo,
 228                                uint64_t *max_alignment);
 229
 230 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 231                        const struct ac_surf_config * config,
 232                        enum radeon_surf_mode mode,
 233                        struct radeon_surf *surf);
 234
 235 #ifdef __cplusplus
 236 }
 237 #endif
 238
 239 #endif /* AC_SURFACE_H */