2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
31 #include "amd_family.h"
33 /* Forward declarations. */
34 typedef void* ADDR_HANDLE
;
36 struct amdgpu_gpu_info
;
39 #define RADEON_SURF_MAX_LEVELS 15
41 enum radeon_surf_mode
{
42 RADEON_SURF_MODE_LINEAR_ALIGNED
= 1,
43 RADEON_SURF_MODE_1D
= 2,
44 RADEON_SURF_MODE_2D
= 3,
47 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
48 enum radeon_micro_mode
{
49 RADEON_MICRO_MODE_DISPLAY
= 0,
50 RADEON_MICRO_MODE_THIN
= 1,
51 RADEON_MICRO_MODE_DEPTH
= 2,
52 RADEON_MICRO_MODE_ROTATED
= 3,
55 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
56 #define RADEON_SURF_SCANOUT (1 << 16)
57 #define RADEON_SURF_ZBUFFER (1 << 17)
58 #define RADEON_SURF_SBUFFER (1 << 18)
59 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
60 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
61 #define RADEON_SURF_FMASK (1 << 21)
62 #define RADEON_SURF_DISABLE_DCC (1 << 22)
63 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
64 #define RADEON_SURF_IMPORTED (1 << 24)
65 #define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
67 struct legacy_surf_level
{
71 uint64_t dcc_fast_clear_size
;
74 enum radeon_surf_mode mode
;
77 struct legacy_surf_layout
{
78 unsigned bankw
:4; /* max 8 */
79 unsigned bankh
:4; /* max 8 */
80 unsigned mtilea
:4; /* max 8 */
81 unsigned tile_split
:13; /* max 4K */
82 unsigned stencil_tile_split
:13; /* max 4K */
83 unsigned pipe_config
:5; /* max 17 */
84 unsigned num_banks
:5; /* max 16 */
85 unsigned macro_tile_index
:4; /* max 15 */
87 /* Whether the depth miptree or stencil miptree as used by the DB are
88 * adjusted from their TC compatible form to ensure depth/stencil
89 * compatibility. If either is true, the corresponding plane cannot be
92 unsigned depth_adjusted
:1;
93 unsigned stencil_adjusted
:1;
95 struct legacy_surf_level level
[RADEON_SURF_MAX_LEVELS
];
96 struct legacy_surf_level stencil_level
[RADEON_SURF_MAX_LEVELS
];
97 uint8_t tiling_index
[RADEON_SURF_MAX_LEVELS
];
98 uint8_t stencil_tiling_index
[RADEON_SURF_MAX_LEVELS
];
101 /* Same as addrlib - AddrResourceType. */
102 enum gfx9_resource_type
{
103 RADEON_RESOURCE_1D
= 0,
108 struct gfx9_surf_flags
{
109 uint16_t swizzle_mode
; /* tile mode */
110 uint16_t epitch
; /* (pitch - 1) or (height - 1) */
113 struct gfx9_surf_meta_flags
{
114 unsigned rb_aligned
:1; /* optimal for RBs */
115 unsigned pipe_aligned
:1; /* optimal for TC */
118 struct gfx9_surf_layout
{
119 struct gfx9_surf_flags surf
; /* color or depth surface */
120 struct gfx9_surf_flags fmask
; /* not added to surf_size */
121 struct gfx9_surf_flags stencil
; /* added to surf_size, use stencil_offset */
123 struct gfx9_surf_meta_flags dcc
; /* metadata of color */
124 struct gfx9_surf_meta_flags htile
; /* metadata of depth and stencil */
125 struct gfx9_surf_meta_flags cmask
; /* metadata of fmask */
127 enum gfx9_resource_type resource_type
; /* 1D, 2D or 3D */
128 uint64_t surf_offset
; /* 0 unless imported with an offset */
129 /* The size of the 2D plane containing all mipmap levels. */
130 uint64_t surf_slice_size
;
131 uint16_t surf_pitch
; /* in blocks */
132 uint16_t surf_height
;
133 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
134 uint32_t offset
[RADEON_SURF_MAX_LEVELS
];
136 uint16_t dcc_pitch_max
; /* (mip chain pitch - 1) */
138 uint64_t stencil_offset
; /* separate stencil */
142 uint32_t fmask_alignment
;
143 uint32_t cmask_alignment
;
147 /* Format properties. */
151 /* Number of mipmap levels where DCC is enabled starting from level 0.
152 * Non-zero levels may be disabled due to alignment constraints, but not
155 unsigned num_dcc_levels
:4;
156 unsigned is_linear
:1;
157 /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
158 unsigned micro_tile_mode
:3;
161 /* These are return values. Some of them can be set by the caller, but
162 * they will be treated as hints (e.g. bankw, bankh) and might be
163 * changed by the calculator.
169 uint32_t htile_slice_size
;
171 uint32_t surf_alignment
;
172 uint32_t dcc_alignment
;
173 uint32_t htile_alignment
;
176 /* R600-VI return values.
178 * Some of them can be set by the caller if certain parameters are
179 * desirable. The allocator will try to obey them.
181 struct legacy_surf_layout legacy
;
183 /* GFX9+ return values. */
184 struct gfx9_surf_layout gfx9
;
188 struct ac_surf_info
{
197 struct ac_surf_config
{
198 struct ac_surf_info info
;
200 unsigned is_cube
: 1;
203 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
204 const struct amdgpu_gpu_info
*amdinfo
);
206 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
207 const struct ac_surf_config
* config
,
208 enum radeon_surf_mode mode
,
209 struct radeon_surf
*surf
);
211 #endif /* AC_SURFACE_H */