src/amd/compiler/aco_builder_h.py

   1
   2 template = """\
   3 /*
   4  * Copyright (c) 2019 Valve Corporation
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  *
  25  * This file was generated by aco_builder_h.py
  26  */
  27
  28 #ifndef _ACO_BUILDER_
  29 #define _ACO_BUILDER_
  30
  31 #include "aco_ir.h"
  32 #include "util/u_math.h"
  33 #include "util/bitscan.h"
  34
  35 namespace aco {
  36 enum dpp_ctrl {
  37     _dpp_quad_perm = 0x000,
  38     _dpp_row_sl = 0x100,
  39     _dpp_row_sr = 0x110,
  40     _dpp_row_rr = 0x120,
  41     dpp_wf_sl1 = 0x130,
  42     dpp_wf_rl1 = 0x134,
  43     dpp_wf_sr1 = 0x138,
  44     dpp_wf_rr1 = 0x13C,
  45     dpp_row_mirror = 0x140,
  46     dpp_row_half_mirror = 0x141,
  47     dpp_row_bcast15 = 0x142,
  48     dpp_row_bcast31 = 0x143
  49 };
  50
  51 inline dpp_ctrl
  52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
  53 {
  54     assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
  55     return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
  56 }
  57
  58 inline dpp_ctrl
  59 dpp_row_sl(unsigned amount)
  60 {
  61     assert(amount > 0 && amount < 16);
  62     return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
  63 }
  64
  65 inline dpp_ctrl
  66 dpp_row_sr(unsigned amount)
  67 {
  68     assert(amount > 0 && amount < 16);
  69     return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
  70 }
  71
  72 inline unsigned
  73 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
  74 {
  75     assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
  76     return and_mask | (or_mask << 5) | (xor_mask << 10);
  77 }
  78
  79 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
  80
  81 class Builder {
  82 public:
  83    struct Result {
  84       Instruction *instr;
  85
  86       Result(Instruction *instr) : instr(instr) {}
  87
  88       operator Instruction *() const {
  89          return instr;
  90       }
  91
  92       operator Temp() const {
  93          return instr->definitions[0].getTemp();
  94       }
  95
  96       operator Operand() const {
  97          return Operand((Temp)*this);
  98       }
  99
 100       Definition& def(unsigned index) const {
 101          return instr->definitions[index];
 102       }
 103
 104       aco_ptr<Instruction> get_ptr() const {
 105         return aco_ptr<Instruction>(instr);
 106       }
 107    };
 108
 109    struct Op {
 110       Operand op;
 111       Op(Temp tmp) : op(tmp) {}
 112       Op(Operand op_) : op(op_) {}
 113       Op(Result res) : op((Temp)res) {}
 114    };
 115
 116    Program *program;
 117    bool use_iterator;
 118    union {
 119    bool forwards; //when use_iterator == true
 120    bool start; //when use_iterator == false
 121    };
 122    std::vector<aco_ptr<Instruction>> *instructions;
 123    std::vector<aco_ptr<Instruction>>::iterator it;
 124
 125    Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), instructions(NULL) {}
 126    Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), instructions(&block->instructions) {}
 127    Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), instructions(instrs) {}
 128
 129    void moveEnd(Block *block) {
 130       instructions = &block->instructions;
 131    }
 132
 133    void reset() {
 134       use_iterator = false;
 135       start = false;
 136       instructions = NULL;
 137    }
 138
 139    void reset(Block *block) {
 140       use_iterator = false;
 141       start = false;
 142       instructions = &block->instructions;
 143    }
 144
 145    void reset(std::vector<aco_ptr<Instruction>> *instrs) {
 146       use_iterator = false;
 147       start = false;
 148       instructions = instrs;
 149    }
 150
 151    Result insert(aco_ptr<Instruction> instr) {
 152       Instruction *instr_ptr = instr.get();
 153       if (instructions) {
 154          if (use_iterator) {
 155             it = instructions->emplace(it, std::move(instr));
 156             if (forwards)
 157                it = std::next(it);
 158          } else if (!start) {
 159             instructions->emplace_back(std::move(instr));
 160          } else {
 161             instructions->emplace(instructions->begin(), std::move(instr));
 162          }
 163       }
 164       return Result(instr_ptr);
 165    }
 166
 167    Result insert(Instruction* instr) {
 168       if (instructions) {
 169          if (use_iterator) {
 170             it = instructions->emplace(it, aco_ptr<Instruction>(instr));
 171             if (forwards)
 172                it = std::next(it);
 173          } else if (!start) {
 174             instructions->emplace_back(aco_ptr<Instruction>(instr));
 175          } else {
 176             instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
 177          }
 178       }
 179       return Result(instr);
 180    }
 181
 182    Temp tmp(RegClass rc) {
 183       return (Temp){program->allocateId(), rc};
 184    }
 185
 186    Temp tmp(RegType type, unsigned size) {
 187       return (Temp){program->allocateId(), RegClass(type, size)};
 188    }
 189
 190    Definition def(RegClass rc) {
 191       return Definition((Temp){program->allocateId(), rc});
 192    }
 193
 194    Definition def(RegType type, unsigned size) {
 195       return Definition((Temp){program->allocateId(), RegClass(type, size)});
 196    }
 197
 198    Definition def(RegClass rc, PhysReg reg) {
 199       return Definition(program->allocateId(), reg, rc);
 200    }
 201
 202 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
 203    Operand ${fixed}(Temp tmp) {
 204        Operand op(tmp);
 205        op.setFixed(aco::${fixed});
 206        return op;
 207    }
 208
 209    Definition ${fixed}(Definition def) {
 210        def.setFixed(aco::${fixed});
 211        return def;
 212    }
 213
 214    Definition hint_${fixed}(Definition def) {
 215        def.setHint(aco::${fixed});
 216        return def;
 217    }
 218
 219 % endfor
 220    /* hand-written helpers */
 221    Temp as_uniform(Op op)
 222    {
 223       assert(op.op.isTemp());
 224       if (op.op.getTemp().type() == RegType::vgpr)
 225          return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
 226       else
 227          return op.op.getTemp();
 228    }
 229
 230    Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
 231    {
 232       assert(tmp.type() == RegType::vgpr);
 233       if (imm == 0) {
 234          return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
 235       } else if (imm == 1) {
 236          return copy(dst, Operand(tmp));
 237       } else if (util_is_power_of_two_or_zero(imm)) {
 238          return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
 239       } else if (bits24) {
 240         return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
 241       } else {
 242         Temp imm_tmp = copy(def(v1), Operand(imm));
 243         return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
 244       }
 245    }
 246
 247    Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
 248    {
 249       return v_mul_imm(dst, tmp, imm, true);
 250    }
 251
 252    Result copy(Definition dst, Op op_) {
 253       Operand op = op_.op;
 254       if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
 255          uint32_t imm = op.constantValue();
 256          if (imm >= 0xffff8000 || imm <= 0x7fff) {
 257             return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
 258          } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
 259             uint32_t rev = util_bitreverse(imm);
 260             return dst.regClass() == v1 ?
 261                    vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
 262                    sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
 263          } else if (imm != 0) {
 264             unsigned start = (ffs(imm) - 1) & 0x1f;
 265             unsigned size = util_bitcount(imm) & 0x1f;
 266             if ((((1u << size) - 1u) << start) == imm)
 267                 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
 268          }
 269       }
 270
 271       if (dst.regClass() == s2) {
 272         return sop1(aco_opcode::s_mov_b64, dst, op);
 273       } else if (op.size() > 1) {
 274          return pseudo(aco_opcode::p_create_vector, dst, op);
 275       } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
 276         return vop1(aco_opcode::v_mov_b32, dst, op);
 277       } else {
 278         assert(dst.regClass() == s1);
 279         return sop1(aco_opcode::s_mov_b32, dst, op);
 280       }
 281    }
 282
 283    Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2))) {
 284       if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
 285          std::swap(a, b);
 286       assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
 287
 288       if (!carry_in.op.isUndefined())
 289          return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(s2)), a, b, carry_in);
 290       else if (program->chip_class >= GFX10 && carry_out)
 291          return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(s2), a, b);
 292       else if (program->chip_class < GFX9 || carry_out)
 293          return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(s2)), a, b);
 294       else
 295          return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
 296    }
 297
 298    Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
 299    {
 300       if (!borrow.op.isUndefined() || program->chip_class < GFX9)
 301          carry_out = true;
 302
 303       bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
 304       if (reverse)
 305          std::swap(a, b);
 306       assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
 307
 308       aco_opcode op;
 309       Temp carry;
 310       if (carry_out) {
 311          carry = tmp(s2);
 312          if (borrow.op.isUndefined())
 313             op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
 314          else
 315             op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
 316       } else {
 317          op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
 318       }
 319       bool vop3 = false;
 320       if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
 321         vop3 = true;
 322         op = aco_opcode::v_subrev_co_u32_e64;
 323       } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
 324         vop3 = true;
 325         op = aco_opcode::v_sub_co_u32_e64;
 326       }
 327
 328       int num_ops = borrow.op.isUndefined() ? 2 : 3;
 329       int num_defs = carry_out ? 2 : 1;
 330       aco_ptr<Instruction> sub;
 331       if (vop3)
 332         sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
 333       else
 334         sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
 335       sub->operands[0] = a.op;
 336       sub->operands[1] = b.op;
 337       if (!borrow.op.isUndefined())
 338          sub->operands[2] = borrow.op;
 339       sub->definitions[0] = dst;
 340       if (carry_out) {
 341          sub->definitions[1] = Definition(carry);
 342          sub->definitions[1].setHint(aco::vcc);
 343       }
 344       return insert(std::move(sub));
 345    }
 346 <%
 347 import itertools
 348 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
 349            ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
 350            ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
 351            ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
 352            ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
 353            ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
 354            ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
 355            ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
 356            ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
 357            ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 4), (1, 3), (0, 3), (1, 2)]), #TODO(pendingchaos): less shapes?
 358            ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
 359            ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
 360            ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
 361            ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
 362            ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
 363            ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
 364            ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
 365            ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
 366            ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
 367            ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
 368            ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
 369            ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
 370            ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
 371            ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
 372            ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
 373            ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
 374            ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
 375 %>\\
 376 % for name, formats, struct, shapes in formats:
 377     % for num_definitions, num_operands in shapes:
 378         <%
 379         args = ['aco_opcode opcode']
 380         for i in range(num_definitions):
 381             args.append('Definition def%d' % i)
 382         for i in range(num_operands):
 383             args.append('Op op%d' % i)
 384         for f in formats:
 385             args += f.get_builder_field_decls()
 386         %>\\
 387
 388    Result ${name}(${', '.join(args)})
 389    {
 390       ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
 391         % for i in range(num_definitions):
 392             instr->definitions[${i}] = def${i};
 393         % endfor
 394         % for i in range(num_operands):
 395             instr->operands[${i}] = op${i}.op;
 396         % endfor
 397         % for f in formats:
 398             % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
 399       instr->${dest} = ${field_name};
 400             % endfor
 401         % endfor
 402       return insert(instr);
 403    }
 404     % endfor
 405 % endfor
 406 };
 407
 408 }
 409 #endif /* _ACO_BUILDER_ */"""
 410
 411 from aco_opcodes import opcodes, Format
 412 from mako.template import Template
 413
 414 print(Template(template).render(opcodes=opcodes, Format=Format))