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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
308 if (num_components
> vec_src
.size()) {
309 if (vec_src
.type() == RegType::sgpr
) {
310 /* should still help get_alu_src() */
311 emit_split_vector(ctx
, vec_src
, vec_src
.size());
314 /* sub-dword split */
315 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
317 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
319 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
320 split
->operands
[0] = Operand(vec_src
);
321 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
322 for (unsigned i
= 0; i
< num_components
; i
++) {
323 elems
[i
] = {ctx
->program
->allocateId(), rc
};
324 split
->definitions
[i
] = Definition(elems
[i
]);
326 ctx
->block
->instructions
.emplace_back(std::move(split
));
327 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
330 /* This vector expansion uses a mask to determine which elements in the new vector
331 * come from the original vector. The other elements are undefined. */
332 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
334 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
339 Builder
bld(ctx
->program
, ctx
->block
);
340 if (num_components
== 1) {
341 if (dst
.type() == RegType::sgpr
)
342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
344 bld
.copy(Definition(dst
), vec_src
);
348 unsigned component_size
= dst
.size() / num_components
;
349 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
351 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
352 vec
->definitions
[0] = Definition(dst
);
354 for (unsigned i
= 0; i
< num_components
; i
++) {
355 if (mask
& (1 << i
)) {
356 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
357 if (dst
.type() == RegType::sgpr
)
358 src
= bld
.as_uniform(src
);
359 vec
->operands
[i
] = Operand(src
);
361 vec
->operands
[i
] = Operand(0u);
363 elems
[i
] = vec
->operands
[i
].getTemp();
365 ctx
->block
->instructions
.emplace_back(std::move(vec
));
366 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
369 /* adjust misaligned small bit size loads */
370 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
372 Builder
bld(ctx
->program
, ctx
->block
);
374 Temp select
= Temp();
375 if (offset
.isConstant()) {
376 assert(offset
.constantValue() && offset
.constantValue() < 4);
377 shift
= Operand(offset
.constantValue() * 8);
379 /* bit_offset = 8 * (offset & 0x3) */
380 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
381 select
= bld
.tmp(s1
);
382 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
385 if (vec
.size() == 1) {
386 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
387 } else if (vec
.size() == 2) {
388 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
389 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
391 emit_split_vector(ctx
, dst
, 2);
393 emit_extract_vector(ctx
, tmp
, 0, dst
);
394 } else if (vec
.size() == 4) {
395 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
396 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
397 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
398 if (select
!= Temp())
399 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
400 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
401 Temp mid
= bld
.tmp(s1
);
402 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
403 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
404 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
406 emit_split_vector(ctx
, dst
, 2);
410 /* this function trims subdword vectors:
411 * if dst is vgpr - split the src and create a shrunk version according to the mask.
412 * if dst is sgpr - split the src, but move the original to sgpr. */
413 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
415 assert(vec_src
.type() == RegType::vgpr
);
416 emit_split_vector(ctx
, vec_src
, num_components
);
418 Builder
bld(ctx
->program
, ctx
->block
);
419 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
420 unsigned component_size
= vec_src
.bytes() / num_components
;
421 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
424 for (unsigned i
= 0; i
< num_components
; i
++) {
426 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
429 if (dst
.type() == RegType::vgpr
) {
430 assert(dst
.bytes() == k
* component_size
);
431 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
432 for (unsigned i
= 0; i
< k
; i
++)
433 vec
->operands
[i
] = Operand(elems
[i
]);
434 vec
->definitions
[0] = Definition(dst
);
435 bld
.insert(std::move(vec
));
437 // TODO: alignbyte if mask doesn't start with 1?
439 assert(dst
.size() == vec_src
.size());
440 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
442 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
445 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
447 Builder
bld(ctx
->program
, ctx
->block
);
449 dst
= bld
.tmp(bld
.lm
);
451 assert(val
.regClass() == s1
);
452 assert(dst
.regClass() == bld
.lm
);
454 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
457 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
459 Builder
bld(ctx
->program
, ctx
->block
);
463 assert(val
.regClass() == bld
.lm
);
464 assert(dst
.regClass() == s1
);
466 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
467 Temp tmp
= bld
.tmp(s1
);
468 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
469 return emit_wqm(ctx
, tmp
, dst
);
472 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
474 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
475 return get_ssa_temp(ctx
, src
.src
.ssa
);
477 if (src
.src
.ssa
->num_components
== size
) {
478 bool identity_swizzle
= true;
479 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
480 if (src
.swizzle
[i
] != i
)
481 identity_swizzle
= false;
483 if (identity_swizzle
)
484 return get_ssa_temp(ctx
, src
.src
.ssa
);
487 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
488 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
489 assert(elem_size
> 0);
490 assert(vec
.bytes() % elem_size
== 0);
492 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
493 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
495 unsigned swizzle
= src
.swizzle
[0];
496 if (vec
.size() > 1) {
497 assert(src
.src
.ssa
->bit_size
== 16);
498 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
499 swizzle
= swizzle
& 1;
504 Temp dst
{ctx
->program
->allocateId(), s1
};
505 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
506 bfe
->operands
[0] = Operand(vec
);
507 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
508 bfe
->definitions
[0] = Definition(dst
);
509 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
510 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
514 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
516 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
519 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
520 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
521 for (unsigned i
= 0; i
< size
; ++i
) {
522 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
523 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
525 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
526 vec_instr
->definitions
[0] = Definition(dst
);
527 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
528 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
533 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
537 Builder
bld(ctx
->program
, ctx
->block
);
538 if (ptr
.type() == RegType::vgpr
)
539 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
540 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
541 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
544 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
546 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
547 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
548 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
549 sop2
->definitions
[0] = Definition(dst
);
551 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
552 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
555 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
556 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
558 Builder
bld(ctx
->program
, ctx
->block
);
559 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
560 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
561 if (src1
.type() == RegType::sgpr
) {
562 if (commutative
&& src0
.type() == RegType::vgpr
) {
567 src1
= as_vgpr(ctx
, src1
);
571 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
572 assert(dst
.size() == 1);
573 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
574 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
576 bld
.vop2(op
, Definition(dst
), src0
, src1
);
580 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
581 bool flush_denorms
= false)
583 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
584 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
585 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
587 /* ensure that the instruction has at most 1 sgpr operand
588 * The optimizer will inline constants for us */
589 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
590 src0
= as_vgpr(ctx
, src0
);
591 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
592 src1
= as_vgpr(ctx
, src1
);
593 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
594 src2
= as_vgpr(ctx
, src2
);
596 Builder
bld(ctx
->program
, ctx
->block
);
597 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
598 assert(dst
.size() == 1);
599 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
600 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
602 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
608 Builder
bld(ctx
->program
, ctx
->block
);
609 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
612 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
615 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
616 assert(src0
.size() == src1
.size());
618 aco_ptr
<Instruction
> vopc
;
619 if (src1
.type() == RegType::sgpr
) {
620 if (src0
.type() == RegType::vgpr
) {
621 /* to swap the operands, we might also have to change the opcode */
623 case aco_opcode::v_cmp_lt_f16
:
624 op
= aco_opcode::v_cmp_gt_f16
;
626 case aco_opcode::v_cmp_ge_f16
:
627 op
= aco_opcode::v_cmp_le_f16
;
629 case aco_opcode::v_cmp_lt_i16
:
630 op
= aco_opcode::v_cmp_gt_i16
;
632 case aco_opcode::v_cmp_ge_i16
:
633 op
= aco_opcode::v_cmp_le_i16
;
635 case aco_opcode::v_cmp_lt_u16
:
636 op
= aco_opcode::v_cmp_gt_u16
;
638 case aco_opcode::v_cmp_ge_u16
:
639 op
= aco_opcode::v_cmp_le_u16
;
641 case aco_opcode::v_cmp_lt_f32
:
642 op
= aco_opcode::v_cmp_gt_f32
;
644 case aco_opcode::v_cmp_ge_f32
:
645 op
= aco_opcode::v_cmp_le_f32
;
647 case aco_opcode::v_cmp_lt_i32
:
648 op
= aco_opcode::v_cmp_gt_i32
;
650 case aco_opcode::v_cmp_ge_i32
:
651 op
= aco_opcode::v_cmp_le_i32
;
653 case aco_opcode::v_cmp_lt_u32
:
654 op
= aco_opcode::v_cmp_gt_u32
;
656 case aco_opcode::v_cmp_ge_u32
:
657 op
= aco_opcode::v_cmp_le_u32
;
659 case aco_opcode::v_cmp_lt_f64
:
660 op
= aco_opcode::v_cmp_gt_f64
;
662 case aco_opcode::v_cmp_ge_f64
:
663 op
= aco_opcode::v_cmp_le_f64
;
665 case aco_opcode::v_cmp_lt_i64
:
666 op
= aco_opcode::v_cmp_gt_i64
;
668 case aco_opcode::v_cmp_ge_i64
:
669 op
= aco_opcode::v_cmp_le_i64
;
671 case aco_opcode::v_cmp_lt_u64
:
672 op
= aco_opcode::v_cmp_gt_u64
;
674 case aco_opcode::v_cmp_ge_u64
:
675 op
= aco_opcode::v_cmp_le_u64
;
677 default: /* eq and ne are commutative */
684 src1
= as_vgpr(ctx
, src1
);
688 Builder
bld(ctx
->program
, ctx
->block
);
689 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
692 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
694 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
695 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
696 Builder
bld(ctx
->program
, ctx
->block
);
698 assert(dst
.regClass() == bld
.lm
);
699 assert(src0
.type() == RegType::sgpr
);
700 assert(src1
.type() == RegType::sgpr
);
701 assert(src0
.regClass() == src1
.regClass());
703 /* Emit the SALU comparison instruction */
704 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
705 /* Turn the result into a per-lane bool */
706 bool_to_vector_condition(ctx
, cmp
, dst
);
709 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
710 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
712 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
713 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
714 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
715 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
717 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
718 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
719 aco_opcode op
= use_valu
? v_op
: s_op
;
720 assert(op
!= aco_opcode::num_opcodes
);
721 assert(dst
.regClass() == ctx
->program
->lane_mask
);
724 emit_vopc_instruction(ctx
, instr
, op
, dst
);
726 emit_sopc_instruction(ctx
, instr
, op
, dst
);
729 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
731 Builder
bld(ctx
->program
, ctx
->block
);
732 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
733 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
735 assert(dst
.regClass() == bld
.lm
);
736 assert(src0
.regClass() == bld
.lm
);
737 assert(src1
.regClass() == bld
.lm
);
739 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
742 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
744 Builder
bld(ctx
->program
, ctx
->block
);
745 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
746 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
747 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
749 assert(cond
.regClass() == bld
.lm
);
751 if (dst
.type() == RegType::vgpr
) {
752 aco_ptr
<Instruction
> bcsel
;
753 if (dst
.size() == 1) {
754 then
= as_vgpr(ctx
, then
);
755 els
= as_vgpr(ctx
, els
);
757 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
758 } else if (dst
.size() == 2) {
759 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
760 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
761 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
762 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
764 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
765 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
767 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
769 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
770 nir_print_instr(&instr
->instr
, stderr
);
771 fprintf(stderr
, "\n");
776 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
777 assert(dst
.regClass() == bld
.lm
);
778 assert(then
.regClass() == bld
.lm
);
779 assert(els
.regClass() == bld
.lm
);
782 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
783 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
784 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
785 assert(dst
.size() == then
.size());
786 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
787 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
789 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
790 nir_print_instr(&instr
->instr
, stderr
);
791 fprintf(stderr
, "\n");
796 /* divergent boolean bcsel
797 * this implements bcsel on bools: dst = s0 ? s1 : s2
798 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
799 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
801 if (cond
.id() != then
.id())
802 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
804 if (cond
.id() == els
.id())
805 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
807 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
808 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
811 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
812 aco_opcode op
, uint32_t undo
)
814 /* multiply by 16777216 to handle denormals */
815 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
816 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
817 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
818 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
819 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
821 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
823 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
826 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
828 if (ctx
->block
->fp_mode
.denorm32
== 0) {
829 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
833 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
836 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
838 if (ctx
->block
->fp_mode
.denorm32
== 0) {
839 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
843 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
846 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
848 if (ctx
->block
->fp_mode
.denorm32
== 0) {
849 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
853 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
856 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
858 if (ctx
->block
->fp_mode
.denorm32
== 0) {
859 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
863 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
866 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
868 if (ctx
->options
->chip_class
>= GFX7
)
869 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
871 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
872 /* TODO: create more efficient code! */
873 if (val
.type() == RegType::sgpr
)
874 val
= as_vgpr(ctx
, val
);
876 /* Split the input value. */
877 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
880 /* Extract the exponent and compute the unbiased value. */
881 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
882 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
884 /* Extract the fractional part. */
885 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
886 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
888 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
889 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
891 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
892 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
893 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
894 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
895 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
897 /* Get the sign bit. */
898 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
900 /* Decide the operation to apply depending on the unbiased exponent. */
901 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
902 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
903 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
904 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
905 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
906 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
908 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
911 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
913 if (ctx
->options
->chip_class
>= GFX7
)
914 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
916 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
917 Temp src0
= as_vgpr(ctx
, val
);
919 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
920 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
922 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
923 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
924 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
926 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
927 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
928 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
929 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
931 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
932 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
934 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
936 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
937 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
939 return add
->definitions
[0].getTemp();
942 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
944 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
945 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
947 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
950 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
951 return bld
.copy(Definition(dst
), src
);
952 else if (dst
.bytes() < src
.bytes())
953 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
957 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
960 } else if (src
.regClass() == s1
) {
962 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
964 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
966 assert(src_bits
!= 8 || src
.regClass() == v1b
);
967 assert(src_bits
!= 16 || src
.regClass() == v2b
);
968 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
969 sdwa
->operands
[0] = Operand(src
);
970 sdwa
->definitions
[0] = Definition(tmp
);
972 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
974 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
975 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
976 bld
.insert(std::move(sdwa
));
979 if (dst_bits
== 64) {
980 if (is_signed
&& dst
.regClass() == s2
) {
981 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
982 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
983 } else if (is_signed
&& dst
.regClass() == v2
) {
984 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
987 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
994 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
996 if (!instr
->dest
.dest
.is_ssa
) {
997 fprintf(stderr
, "nir alu dst not in ssa: ");
998 nir_print_instr(&instr
->instr
, stderr
);
999 fprintf(stderr
, "\n");
1002 Builder
bld(ctx
->program
, ctx
->block
);
1003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1008 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1009 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1010 for (unsigned i
= 0; i
< num
; ++i
)
1011 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1013 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1014 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1015 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1016 for (unsigned i
= 0; i
< num
; ++i
) {
1017 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1018 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1020 vec
->operands
[i
] = Operand
{elems
[i
]};
1022 vec
->definitions
[0] = Definition(dst
);
1023 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1024 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1026 // TODO: that is a bit suboptimal..
1027 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1028 for (unsigned i
= 0; i
< num
- 1; ++i
)
1029 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1030 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1031 for (unsigned i
= 0; i
< num
; ++i
) {
1032 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1033 if (bit
% 32 == 0) {
1034 elems
[bit
/ 32] = elems
[i
];
1036 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1037 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1038 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1041 if (dst
.size() == 1)
1042 bld
.copy(Definition(dst
), elems
[0]);
1044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1049 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1050 aco_ptr
<Instruction
> mov
;
1051 if (dst
.type() == RegType::sgpr
) {
1052 if (src
.type() == RegType::vgpr
)
1053 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1054 else if (src
.regClass() == s1
)
1055 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1056 else if (src
.regClass() == s2
)
1057 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1059 unreachable("wrong src register class for nir_op_imov");
1060 } else if (dst
.regClass() == v1
) {
1061 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1062 } else if (dst
.regClass() == v2
) {
1063 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1065 nir_print_instr(&instr
->instr
, stderr
);
1066 unreachable("Should have been lowered to scalar.");
1071 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1072 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1073 assert(src
.regClass() == bld
.lm
);
1074 assert(dst
.regClass() == bld
.lm
);
1075 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1076 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1077 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1078 } else if (dst
.regClass() == v1
) {
1079 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1080 } else if (dst
.type() == RegType::sgpr
) {
1081 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1082 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1084 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1085 nir_print_instr(&instr
->instr
, stderr
);
1086 fprintf(stderr
, "\n");
1091 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1092 if (dst
.regClass() == v1
) {
1093 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1094 } else if (dst
.regClass() == s1
) {
1095 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1096 } else if (dst
.size() == 2) {
1097 Temp src0
= bld
.tmp(dst
.type(), 1);
1098 Temp src1
= bld
.tmp(dst
.type(), 1);
1099 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1101 if (dst
.regClass() == s2
) {
1102 Temp carry
= bld
.tmp(s1
);
1103 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1104 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1105 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1107 Temp lower
= bld
.tmp(v1
);
1108 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1109 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1110 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == s1
) {
1121 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1122 } else if (dst
.regClass() == v1
) {
1123 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1124 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1126 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1127 nir_print_instr(&instr
->instr
, stderr
);
1128 fprintf(stderr
, "\n");
1132 case nir_op_isign
: {
1133 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1134 if (dst
.regClass() == s1
) {
1135 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1136 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1137 } else if (dst
.regClass() == s2
) {
1138 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1140 if (ctx
->program
->chip_class
>= GFX8
)
1141 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1143 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1144 /* SCC gets zero-extended to 64 bit */
1145 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1146 } else if (dst
.regClass() == v1
) {
1147 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1148 } else if (dst
.regClass() == v2
) {
1149 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1150 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1151 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1152 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1153 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1154 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1156 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1157 nir_print_instr(&instr
->instr
, stderr
);
1158 fprintf(stderr
, "\n");
1163 if (dst
.regClass() == v1
) {
1164 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1165 } else if (dst
.regClass() == s1
) {
1166 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1168 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1169 nir_print_instr(&instr
->instr
, stderr
);
1170 fprintf(stderr
, "\n");
1175 if (dst
.regClass() == v1
) {
1176 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1177 } else if (dst
.regClass() == s1
) {
1178 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1180 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1181 nir_print_instr(&instr
->instr
, stderr
);
1182 fprintf(stderr
, "\n");
1187 if (dst
.regClass() == v1
) {
1188 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1189 } else if (dst
.regClass() == s1
) {
1190 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1192 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1193 nir_print_instr(&instr
->instr
, stderr
);
1194 fprintf(stderr
, "\n");
1199 if (dst
.regClass() == v1
) {
1200 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1201 } else if (dst
.regClass() == s1
) {
1202 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1204 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1205 nir_print_instr(&instr
->instr
, stderr
);
1206 fprintf(stderr
, "\n");
1211 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1212 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1213 } else if (dst
.regClass() == v1
) {
1214 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1215 } else if (dst
.regClass() == s1
) {
1216 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1217 } else if (dst
.regClass() == s2
) {
1218 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1220 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1221 nir_print_instr(&instr
->instr
, stderr
);
1222 fprintf(stderr
, "\n");
1227 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1228 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1229 } else if (dst
.regClass() == v1
) {
1230 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1231 } else if (dst
.regClass() == s1
) {
1232 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1233 } else if (dst
.regClass() == s2
) {
1234 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1236 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1237 nir_print_instr(&instr
->instr
, stderr
);
1238 fprintf(stderr
, "\n");
1243 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1244 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1245 } else if (dst
.regClass() == v1
) {
1246 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1247 } else if (dst
.regClass() == s1
) {
1248 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1249 } else if (dst
.regClass() == s2
) {
1250 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1252 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1253 nir_print_instr(&instr
->instr
, stderr
);
1254 fprintf(stderr
, "\n");
1259 if (dst
.regClass() == v1
) {
1260 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1261 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1262 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1263 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1264 } else if (dst
.regClass() == v2
) {
1265 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1266 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1267 } else if (dst
.regClass() == s2
) {
1268 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1269 } else if (dst
.regClass() == s1
) {
1270 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1273 nir_print_instr(&instr
->instr
, stderr
);
1274 fprintf(stderr
, "\n");
1279 if (dst
.regClass() == v1
) {
1280 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1281 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1282 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1283 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1284 } else if (dst
.regClass() == v2
) {
1285 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1286 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1287 } else if (dst
.regClass() == s1
) {
1288 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1289 } else if (dst
.regClass() == s2
) {
1290 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1292 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1293 nir_print_instr(&instr
->instr
, stderr
);
1294 fprintf(stderr
, "\n");
1299 if (dst
.regClass() == v1
) {
1300 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1301 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1302 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1303 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1304 } else if (dst
.regClass() == v2
) {
1305 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1306 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1307 } else if (dst
.regClass() == s1
) {
1308 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1309 } else if (dst
.regClass() == s2
) {
1310 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1312 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1313 nir_print_instr(&instr
->instr
, stderr
);
1314 fprintf(stderr
, "\n");
1318 case nir_op_find_lsb
: {
1319 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1320 if (src
.regClass() == s1
) {
1321 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1322 } else if (src
.regClass() == v1
) {
1323 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1324 } else if (src
.regClass() == s2
) {
1325 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1327 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1328 nir_print_instr(&instr
->instr
, stderr
);
1329 fprintf(stderr
, "\n");
1333 case nir_op_ufind_msb
:
1334 case nir_op_ifind_msb
: {
1335 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1336 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1337 aco_opcode op
= src
.regClass() == s2
?
1338 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1339 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1340 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1342 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1343 Operand(src
.size() * 32u - 1u), msb_rev
);
1344 Temp msb
= sub
.def(0).getTemp();
1345 Temp carry
= sub
.def(1).getTemp();
1347 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1348 } else if (src
.regClass() == v1
) {
1349 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1350 Temp msb_rev
= bld
.tmp(v1
);
1351 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1352 Temp msb
= bld
.tmp(v1
);
1353 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1354 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1356 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1357 nir_print_instr(&instr
->instr
, stderr
);
1358 fprintf(stderr
, "\n");
1362 case nir_op_bitfield_reverse
: {
1363 if (dst
.regClass() == s1
) {
1364 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1365 } else if (dst
.regClass() == v1
) {
1366 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1368 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1369 nir_print_instr(&instr
->instr
, stderr
);
1370 fprintf(stderr
, "\n");
1375 if (dst
.regClass() == s1
) {
1376 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1380 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1381 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1382 if (dst
.regClass() == v1
) {
1383 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1387 assert(src0
.size() == 2 && src1
.size() == 2);
1388 Temp src00
= bld
.tmp(src0
.type(), 1);
1389 Temp src01
= bld
.tmp(dst
.type(), 1);
1390 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1391 Temp src10
= bld
.tmp(src1
.type(), 1);
1392 Temp src11
= bld
.tmp(dst
.type(), 1);
1393 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1400 } else if (dst
.regClass() == v2
) {
1401 Temp dst0
= bld
.tmp(v1
);
1402 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1403 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1412 case nir_op_uadd_sat
: {
1413 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1414 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1415 if (dst
.regClass() == s1
) {
1416 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1417 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1419 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1420 } else if (dst
.regClass() == v1
) {
1421 if (ctx
->options
->chip_class
>= GFX9
) {
1422 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1423 add
->operands
[0] = Operand(src0
);
1424 add
->operands
[1] = Operand(src1
);
1425 add
->definitions
[0] = Definition(dst
);
1427 ctx
->block
->instructions
.emplace_back(std::move(add
));
1429 if (src1
.regClass() != v1
)
1430 std::swap(src0
, src1
);
1431 assert(src1
.regClass() == v1
);
1432 Temp tmp
= bld
.tmp(v1
);
1433 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1434 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1437 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1438 nir_print_instr(&instr
->instr
, stderr
);
1439 fprintf(stderr
, "\n");
1443 case nir_op_uadd_carry
: {
1444 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1445 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1446 if (dst
.regClass() == s1
) {
1447 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1450 if (dst
.regClass() == v1
) {
1451 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1452 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1456 Temp src00
= bld
.tmp(src0
.type(), 1);
1457 Temp src01
= bld
.tmp(dst
.type(), 1);
1458 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1459 Temp src10
= bld
.tmp(src1
.type(), 1);
1460 Temp src11
= bld
.tmp(dst
.type(), 1);
1461 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1462 if (dst
.regClass() == s2
) {
1463 Temp carry
= bld
.tmp(s1
);
1464 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1465 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1466 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1467 } else if (dst
.regClass() == v2
) {
1468 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1469 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1470 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1471 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1473 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1474 nir_print_instr(&instr
->instr
, stderr
);
1475 fprintf(stderr
, "\n");
1480 if (dst
.regClass() == s1
) {
1481 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1485 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1486 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1487 if (dst
.regClass() == v1
) {
1488 bld
.vsub32(Definition(dst
), src0
, src1
);
1492 Temp src00
= bld
.tmp(src0
.type(), 1);
1493 Temp src01
= bld
.tmp(dst
.type(), 1);
1494 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1495 Temp src10
= bld
.tmp(src1
.type(), 1);
1496 Temp src11
= bld
.tmp(dst
.type(), 1);
1497 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1498 if (dst
.regClass() == s2
) {
1499 Temp carry
= bld
.tmp(s1
);
1500 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1501 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1502 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1503 } else if (dst
.regClass() == v2
) {
1504 Temp lower
= bld
.tmp(v1
);
1505 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1506 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1507 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1509 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1510 nir_print_instr(&instr
->instr
, stderr
);
1511 fprintf(stderr
, "\n");
1515 case nir_op_usub_borrow
: {
1516 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1517 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1518 if (dst
.regClass() == s1
) {
1519 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1521 } else if (dst
.regClass() == v1
) {
1522 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1523 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1527 Temp src00
= bld
.tmp(src0
.type(), 1);
1528 Temp src01
= bld
.tmp(dst
.type(), 1);
1529 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1530 Temp src10
= bld
.tmp(src1
.type(), 1);
1531 Temp src11
= bld
.tmp(dst
.type(), 1);
1532 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1533 if (dst
.regClass() == s2
) {
1534 Temp borrow
= bld
.tmp(s1
);
1535 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1536 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1537 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1538 } else if (dst
.regClass() == v2
) {
1539 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1540 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1541 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1544 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1545 nir_print_instr(&instr
->instr
, stderr
);
1546 fprintf(stderr
, "\n");
1551 if (dst
.regClass() == v1
) {
1552 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1553 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1554 } else if (dst
.regClass() == s1
) {
1555 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1557 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1558 nir_print_instr(&instr
->instr
, stderr
);
1559 fprintf(stderr
, "\n");
1563 case nir_op_umul_high
: {
1564 if (dst
.regClass() == v1
) {
1565 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1566 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1567 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1568 } else if (dst
.regClass() == s1
) {
1569 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1570 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1571 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1573 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1574 nir_print_instr(&instr
->instr
, stderr
);
1575 fprintf(stderr
, "\n");
1579 case nir_op_imul_high
: {
1580 if (dst
.regClass() == v1
) {
1581 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1582 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1583 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1584 } else if (dst
.regClass() == s1
) {
1585 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1586 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1587 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1589 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1590 nir_print_instr(&instr
->instr
, stderr
);
1591 fprintf(stderr
, "\n");
1596 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1597 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1598 if (dst
.regClass() == v2b
) {
1599 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1600 } else if (dst
.regClass() == v1
) {
1601 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1602 } else if (dst
.regClass() == v2
) {
1603 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1613 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1614 if (dst
.regClass() == v2b
) {
1615 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1616 } else if (dst
.regClass() == v1
) {
1617 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1618 } else if (dst
.regClass() == v2
) {
1619 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1628 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1629 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1630 if (dst
.regClass() == v2b
) {
1631 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1632 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1634 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1635 } else if (dst
.regClass() == v1
) {
1636 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1637 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1639 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1640 } else if (dst
.regClass() == v2
) {
1641 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1642 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1643 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1646 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1647 nir_print_instr(&instr
->instr
, stderr
);
1648 fprintf(stderr
, "\n");
1653 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1654 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1655 if (dst
.regClass() == v2b
) {
1656 // TODO: check fp_mode.must_flush_denorms16_64
1657 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1658 } else if (dst
.regClass() == v1
) {
1659 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1660 } else if (dst
.regClass() == v2
) {
1661 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1662 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1663 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1665 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1668 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1669 nir_print_instr(&instr
->instr
, stderr
);
1670 fprintf(stderr
, "\n");
1675 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1676 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1677 if (dst
.regClass() == v2b
) {
1678 // TODO: check fp_mode.must_flush_denorms16_64
1679 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1680 } else if (dst
.regClass() == v1
) {
1681 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1682 } else if (dst
.regClass() == v2
) {
1683 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1684 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1685 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1687 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1690 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1691 nir_print_instr(&instr
->instr
, stderr
);
1692 fprintf(stderr
, "\n");
1696 case nir_op_fmax3
: {
1697 if (dst
.regClass() == v2b
) {
1698 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1699 } else if (dst
.regClass() == v1
) {
1700 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1702 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1703 nir_print_instr(&instr
->instr
, stderr
);
1704 fprintf(stderr
, "\n");
1708 case nir_op_fmin3
: {
1709 if (dst
.regClass() == v2b
) {
1710 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1711 } else if (dst
.regClass() == v1
) {
1712 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1714 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1715 nir_print_instr(&instr
->instr
, stderr
);
1716 fprintf(stderr
, "\n");
1720 case nir_op_fmed3
: {
1721 if (dst
.regClass() == v2b
) {
1722 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1723 } else if (dst
.regClass() == v1
) {
1724 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1727 nir_print_instr(&instr
->instr
, stderr
);
1728 fprintf(stderr
, "\n");
1732 case nir_op_umax3
: {
1733 if (dst
.size() == 1) {
1734 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1736 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1737 nir_print_instr(&instr
->instr
, stderr
);
1738 fprintf(stderr
, "\n");
1742 case nir_op_umin3
: {
1743 if (dst
.size() == 1) {
1744 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1746 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1747 nir_print_instr(&instr
->instr
, stderr
);
1748 fprintf(stderr
, "\n");
1752 case nir_op_umed3
: {
1753 if (dst
.size() == 1) {
1754 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1756 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1757 nir_print_instr(&instr
->instr
, stderr
);
1758 fprintf(stderr
, "\n");
1762 case nir_op_imax3
: {
1763 if (dst
.size() == 1) {
1764 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1766 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1767 nir_print_instr(&instr
->instr
, stderr
);
1768 fprintf(stderr
, "\n");
1772 case nir_op_imin3
: {
1773 if (dst
.size() == 1) {
1774 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1776 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1777 nir_print_instr(&instr
->instr
, stderr
);
1778 fprintf(stderr
, "\n");
1782 case nir_op_imed3
: {
1783 if (dst
.size() == 1) {
1784 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1786 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1787 nir_print_instr(&instr
->instr
, stderr
);
1788 fprintf(stderr
, "\n");
1792 case nir_op_cube_face_coord
: {
1793 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1794 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1795 emit_extract_vector(ctx
, in
, 1, v1
),
1796 emit_extract_vector(ctx
, in
, 2, v1
) };
1797 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1798 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1799 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1800 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1801 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1802 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1803 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1806 case nir_op_cube_face_index
: {
1807 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1808 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1809 emit_extract_vector(ctx
, in
, 1, v1
),
1810 emit_extract_vector(ctx
, in
, 2, v1
) };
1811 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1814 case nir_op_bcsel
: {
1815 emit_bcsel(ctx
, instr
, dst
);
1819 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1820 if (dst
.regClass() == v2b
) {
1821 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1822 } else if (dst
.regClass() == v1
) {
1823 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1824 } else if (dst
.regClass() == v2
) {
1825 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1827 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1828 nir_print_instr(&instr
->instr
, stderr
);
1829 fprintf(stderr
, "\n");
1834 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1835 if (dst
.regClass() == v2b
) {
1836 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1837 } else if (dst
.regClass() == v1
) {
1838 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1839 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1840 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1841 } else if (dst
.regClass() == v2
) {
1842 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1843 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1844 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1845 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1846 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1847 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1849 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1850 nir_print_instr(&instr
->instr
, stderr
);
1851 fprintf(stderr
, "\n");
1856 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1857 if (dst
.regClass() == v2b
) {
1858 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1859 } else if (dst
.regClass() == v1
) {
1860 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1861 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1862 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1863 } else if (dst
.regClass() == v2
) {
1864 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1865 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1866 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1867 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1868 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1872 nir_print_instr(&instr
->instr
, stderr
);
1873 fprintf(stderr
, "\n");
1878 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1879 if (dst
.regClass() == v2b
) {
1880 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1881 } else if (dst
.regClass() == v1
) {
1882 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1883 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1884 // TODO: confirm that this holds under any circumstances
1885 } else if (dst
.regClass() == v2
) {
1886 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1887 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1890 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1891 nir_print_instr(&instr
->instr
, stderr
);
1892 fprintf(stderr
, "\n");
1896 case nir_op_flog2
: {
1897 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1898 if (dst
.regClass() == v2b
) {
1899 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1900 } else if (dst
.regClass() == v1
) {
1901 emit_log2(ctx
, bld
, Definition(dst
), src
);
1903 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1904 nir_print_instr(&instr
->instr
, stderr
);
1905 fprintf(stderr
, "\n");
1910 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1911 if (dst
.regClass() == v2b
) {
1912 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1913 } else if (dst
.regClass() == v1
) {
1914 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1915 } else if (dst
.regClass() == v2
) {
1916 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1918 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1919 nir_print_instr(&instr
->instr
, stderr
);
1920 fprintf(stderr
, "\n");
1924 case nir_op_fexp2
: {
1925 if (dst
.regClass() == v2b
) {
1926 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1927 } else if (dst
.regClass() == v1
) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1930 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1931 nir_print_instr(&instr
->instr
, stderr
);
1932 fprintf(stderr
, "\n");
1936 case nir_op_fsqrt
: {
1937 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1938 if (dst
.regClass() == v2b
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1940 } else if (dst
.regClass() == v1
) {
1941 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1942 } else if (dst
.regClass() == v2
) {
1943 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1945 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1946 nir_print_instr(&instr
->instr
, stderr
);
1947 fprintf(stderr
, "\n");
1951 case nir_op_ffract
: {
1952 if (dst
.regClass() == v2b
) {
1953 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1954 } else if (dst
.regClass() == v1
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1956 } else if (dst
.regClass() == v2
) {
1957 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_ffloor
: {
1966 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1969 } else if (dst
.regClass() == v1
) {
1970 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1971 } else if (dst
.regClass() == v2
) {
1972 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1974 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1975 nir_print_instr(&instr
->instr
, stderr
);
1976 fprintf(stderr
, "\n");
1980 case nir_op_fceil
: {
1981 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1982 if (dst
.regClass() == v2b
) {
1983 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1984 } else if (dst
.regClass() == v1
) {
1985 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1986 } else if (dst
.regClass() == v2
) {
1987 if (ctx
->options
->chip_class
>= GFX7
) {
1988 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1990 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1991 /* trunc = trunc(src0)
1992 * if (src0 > 0.0 && src0 != trunc)
1995 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1996 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1997 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1998 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1999 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2000 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2001 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2004 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2005 nir_print_instr(&instr
->instr
, stderr
);
2006 fprintf(stderr
, "\n");
2010 case nir_op_ftrunc
: {
2011 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2012 if (dst
.regClass() == v2b
) {
2013 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2014 } else if (dst
.regClass() == v1
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2016 } else if (dst
.regClass() == v2
) {
2017 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2019 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2020 nir_print_instr(&instr
->instr
, stderr
);
2021 fprintf(stderr
, "\n");
2025 case nir_op_fround_even
: {
2026 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2027 if (dst
.regClass() == v2b
) {
2028 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2029 } else if (dst
.regClass() == v1
) {
2030 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2031 } else if (dst
.regClass() == v2
) {
2032 if (ctx
->options
->chip_class
>= GFX7
) {
2033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2035 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2036 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2037 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2039 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2040 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2041 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2042 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2043 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2044 tmp
= sub
->definitions
[0].getTemp();
2046 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2047 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2048 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2049 Temp cond
= vop3
->definitions
[0].getTemp();
2051 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2052 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2053 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2054 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2056 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2059 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2060 nir_print_instr(&instr
->instr
, stderr
);
2061 fprintf(stderr
, "\n");
2067 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2068 aco_ptr
<Instruction
> norm
;
2069 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2070 if (dst
.regClass() == v2b
) {
2071 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2072 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2073 bld
.vop1(opcode
, Definition(dst
), tmp
);
2074 } else if (dst
.regClass() == v1
) {
2075 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2077 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2078 if (ctx
->options
->chip_class
< GFX9
)
2079 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2081 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2082 bld
.vop1(opcode
, Definition(dst
), tmp
);
2084 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2085 nir_print_instr(&instr
->instr
, stderr
);
2086 fprintf(stderr
, "\n");
2090 case nir_op_ldexp
: {
2091 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2092 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2093 if (dst
.regClass() == v2b
) {
2094 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2095 } else if (dst
.regClass() == v1
) {
2096 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2097 } else if (dst
.regClass() == v2
) {
2098 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2100 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2101 nir_print_instr(&instr
->instr
, stderr
);
2102 fprintf(stderr
, "\n");
2106 case nir_op_frexp_sig
: {
2107 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2108 if (dst
.regClass() == v2b
) {
2109 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2110 } else if (dst
.regClass() == v1
) {
2111 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2112 } else if (dst
.regClass() == v2
) {
2113 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2115 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2116 nir_print_instr(&instr
->instr
, stderr
);
2117 fprintf(stderr
, "\n");
2121 case nir_op_frexp_exp
: {
2122 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2123 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2124 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2125 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2126 convert_int(bld
, tmp
, 8, 32, true, dst
);
2127 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2128 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2129 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2130 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_fsign
: {
2139 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2140 if (dst
.regClass() == v2b
) {
2141 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2142 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2143 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2144 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2145 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2147 } else if (dst
.regClass() == v1
) {
2148 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2149 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2150 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2151 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2152 } else if (dst
.regClass() == v2
) {
2153 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2154 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2155 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2157 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2158 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2159 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2161 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2163 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2164 nir_print_instr(&instr
->instr
, stderr
);
2165 fprintf(stderr
, "\n");
2170 case nir_op_f2f16_rtne
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2173 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2174 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2177 case nir_op_f2f16_rtz
: {
2178 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2180 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2181 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2184 case nir_op_f2f32
: {
2185 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2186 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2187 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2188 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2190 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2191 nir_print_instr(&instr
->instr
, stderr
);
2192 fprintf(stderr
, "\n");
2196 case nir_op_f2f64
: {
2197 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2198 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2199 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2200 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2203 case nir_op_i2f16
: {
2204 assert(dst
.regClass() == v2b
);
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2207 src
= convert_int(bld
, src
, 8, 16, true);
2208 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2211 case nir_op_i2f32
: {
2212 assert(dst
.size() == 1);
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2215 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2216 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2219 case nir_op_i2f64
: {
2220 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2221 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2222 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2223 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2224 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2225 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2226 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2227 RegClass rc
= RegClass(src
.type(), 1);
2228 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2229 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2230 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2231 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2232 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2233 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2236 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2237 nir_print_instr(&instr
->instr
, stderr
);
2238 fprintf(stderr
, "\n");
2242 case nir_op_u2f16
: {
2243 assert(dst
.regClass() == v2b
);
2244 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2245 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2246 src
= convert_int(bld
, src
, 8, 16, false);
2247 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2250 case nir_op_u2f32
: {
2251 assert(dst
.size() == 1);
2252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2253 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2254 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2255 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2257 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2258 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2259 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2263 case nir_op_u2f64
: {
2264 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2265 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2266 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2267 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2268 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2269 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2270 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2271 RegClass rc
= RegClass(src
.type(), 1);
2272 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2273 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2274 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2275 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2276 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2277 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2279 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2280 nir_print_instr(&instr
->instr
, stderr
);
2281 fprintf(stderr
, "\n");
2286 case nir_op_f2i16
: {
2287 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2288 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2289 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2290 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2291 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2293 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2295 if (dst
.type() == RegType::vgpr
)
2296 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2298 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2302 case nir_op_f2u16
: {
2303 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2304 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2305 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2306 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2307 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2309 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2311 if (dst
.type() == RegType::vgpr
)
2312 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2314 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2317 case nir_op_f2i32
: {
2318 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2319 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2320 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2321 if (dst
.type() == RegType::vgpr
) {
2322 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2324 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2325 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2327 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2328 if (dst
.type() == RegType::vgpr
)
2329 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2331 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2332 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2334 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2335 if (dst
.type() == RegType::vgpr
)
2336 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2338 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2339 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2342 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2343 nir_print_instr(&instr
->instr
, stderr
);
2344 fprintf(stderr
, "\n");
2348 case nir_op_f2u32
: {
2349 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2350 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2351 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2352 if (dst
.type() == RegType::vgpr
) {
2353 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2355 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2356 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2358 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2359 if (dst
.type() == RegType::vgpr
)
2360 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2362 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2363 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2365 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2366 if (dst
.type() == RegType::vgpr
)
2367 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2373 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2374 nir_print_instr(&instr
->instr
, stderr
);
2375 fprintf(stderr
, "\n");
2379 case nir_op_f2i64
: {
2380 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2381 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2382 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2384 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2385 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2386 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2387 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2388 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2389 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2390 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2391 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2392 Temp new_exponent
= bld
.tmp(v1
);
2393 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2394 if (ctx
->program
->chip_class
>= GFX8
)
2395 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2397 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2398 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2399 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2400 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2401 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2402 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2403 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2404 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2405 Temp new_lower
= bld
.tmp(v1
);
2406 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2407 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2408 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2410 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2411 if (src
.type() == RegType::vgpr
)
2412 src
= bld
.as_uniform(src
);
2413 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2414 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2415 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2416 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2417 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2418 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2419 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2420 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2421 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2422 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2423 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2424 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2425 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2426 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2427 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2428 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2429 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2430 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2431 Temp borrow
= bld
.tmp(s1
);
2432 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2433 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2434 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2436 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2437 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2438 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2439 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2440 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2441 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2442 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2443 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2444 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2445 if (dst
.type() == RegType::sgpr
) {
2446 lower
= bld
.as_uniform(lower
);
2447 upper
= bld
.as_uniform(upper
);
2449 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2452 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2453 nir_print_instr(&instr
->instr
, stderr
);
2454 fprintf(stderr
, "\n");
2458 case nir_op_f2u64
: {
2459 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2460 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2461 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2463 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2464 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2465 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2466 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2467 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2468 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2469 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2470 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2471 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2472 Temp new_exponent
= bld
.tmp(v1
);
2473 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2474 if (ctx
->program
->chip_class
>= GFX8
)
2475 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2477 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2478 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2479 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2480 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2481 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2482 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2483 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2484 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2486 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2487 if (src
.type() == RegType::vgpr
)
2488 src
= bld
.as_uniform(src
);
2489 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2490 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2491 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2492 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2493 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2494 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2495 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2496 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2497 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2498 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2499 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2500 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2501 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2502 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2503 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2504 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2505 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2506 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2508 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2509 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2510 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2511 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2512 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2513 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2514 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2515 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2516 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2517 if (dst
.type() == RegType::sgpr
) {
2518 lower
= bld
.as_uniform(lower
);
2519 upper
= bld
.as_uniform(upper
);
2521 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2524 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2525 nir_print_instr(&instr
->instr
, stderr
);
2526 fprintf(stderr
, "\n");
2530 case nir_op_b2f16
: {
2531 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2532 assert(src
.regClass() == bld
.lm
);
2534 if (dst
.regClass() == s1
) {
2535 src
= bool_to_scalar_condition(ctx
, src
);
2536 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2537 } else if (dst
.regClass() == v2b
) {
2538 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2539 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2541 unreachable("Wrong destination register class for nir_op_b2f16.");
2545 case nir_op_b2f32
: {
2546 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2547 assert(src
.regClass() == bld
.lm
);
2549 if (dst
.regClass() == s1
) {
2550 src
= bool_to_scalar_condition(ctx
, src
);
2551 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2552 } else if (dst
.regClass() == v1
) {
2553 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2555 unreachable("Wrong destination register class for nir_op_b2f32.");
2559 case nir_op_b2f64
: {
2560 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2561 assert(src
.regClass() == bld
.lm
);
2563 if (dst
.regClass() == s2
) {
2564 src
= bool_to_scalar_condition(ctx
, src
);
2565 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2566 } else if (dst
.regClass() == v2
) {
2567 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2568 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2569 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2571 unreachable("Wrong destination register class for nir_op_b2f64.");
2578 case nir_op_i2i64
: {
2579 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2580 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2586 case nir_op_u2u64
: {
2587 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2588 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2592 case nir_op_b2i32
: {
2593 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2594 assert(src
.regClass() == bld
.lm
);
2596 if (dst
.regClass() == s1
) {
2597 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2598 bool_to_scalar_condition(ctx
, src
, dst
);
2599 } else if (dst
.regClass() == v1
) {
2600 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2602 unreachable("Invalid register class for b2i32");
2608 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2609 assert(dst
.regClass() == bld
.lm
);
2611 if (src
.type() == RegType::vgpr
) {
2612 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2613 assert(dst
.regClass() == bld
.lm
);
2614 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2615 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2617 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2619 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2620 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2622 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2623 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2625 bool_to_vector_condition(ctx
, tmp
, dst
);
2629 case nir_op_pack_64_2x32_split
: {
2630 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2631 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2633 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2636 case nir_op_unpack_64_2x32_split_x
:
2637 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2639 case nir_op_unpack_64_2x32_split_y
:
2640 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2642 case nir_op_unpack_32_2x16_split_x
:
2643 if (dst
.type() == RegType::vgpr
) {
2644 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2646 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2649 case nir_op_unpack_32_2x16_split_y
:
2650 if (dst
.type() == RegType::vgpr
) {
2651 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2653 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2656 case nir_op_pack_32_2x16_split
: {
2657 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2658 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2659 if (dst
.regClass() == v1
) {
2660 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2661 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2662 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2664 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2665 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2666 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2670 case nir_op_pack_half_2x16
: {
2671 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2673 if (dst
.regClass() == v1
) {
2674 Temp src0
= bld
.tmp(v1
);
2675 Temp src1
= bld
.tmp(v1
);
2676 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2677 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2678 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2680 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2681 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2682 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2684 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2685 nir_print_instr(&instr
->instr
, stderr
);
2686 fprintf(stderr
, "\n");
2690 case nir_op_unpack_half_2x16_split_x
: {
2691 if (dst
.regClass() == v1
) {
2692 Builder
bld(ctx
->program
, ctx
->block
);
2693 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2696 nir_print_instr(&instr
->instr
, stderr
);
2697 fprintf(stderr
, "\n");
2701 case nir_op_unpack_half_2x16_split_y
: {
2702 if (dst
.regClass() == v1
) {
2703 Builder
bld(ctx
->program
, ctx
->block
);
2704 /* TODO: use SDWA here */
2705 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2706 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2708 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2709 nir_print_instr(&instr
->instr
, stderr
);
2710 fprintf(stderr
, "\n");
2714 case nir_op_fquantize2f16
: {
2715 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2716 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2719 if (ctx
->program
->chip_class
>= GFX8
) {
2720 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2721 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2722 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2724 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2725 * so compare the result and flush to 0 if it's smaller.
2727 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2728 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2729 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2730 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2731 cmp_res
= vop3
->definitions
[0].getTemp();
2734 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2735 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2736 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2738 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2743 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2744 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2746 if (dst
.regClass() == s1
) {
2747 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2748 } else if (dst
.regClass() == v1
) {
2749 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2751 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2752 nir_print_instr(&instr
->instr
, stderr
);
2753 fprintf(stderr
, "\n");
2757 case nir_op_bitfield_select
: {
2758 /* (mask & insert) | (~mask & base) */
2759 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2760 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2761 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2763 /* dst = (insert & bitmask) | (base & ~bitmask) */
2764 if (dst
.regClass() == s1
) {
2765 aco_ptr
<Instruction
> sop2
;
2766 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2767 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2769 if (const_insert
&& const_bitmask
) {
2770 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2772 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2773 lhs
= Operand(insert
);
2777 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2778 if (const_base
&& const_bitmask
) {
2779 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2781 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2782 rhs
= Operand(base
);
2785 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2787 } else if (dst
.regClass() == v1
) {
2788 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2789 base
= as_vgpr(ctx
, base
);
2790 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2791 insert
= as_vgpr(ctx
, insert
);
2793 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2796 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2797 nir_print_instr(&instr
->instr
, stderr
);
2798 fprintf(stderr
, "\n");
2804 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2805 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2806 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2808 if (dst
.type() == RegType::sgpr
) {
2810 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2811 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2812 if (const_offset
&& const_bits
) {
2813 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2814 extract
= Operand(const_extract
);
2818 width
= Operand(const_bits
->u32
<< 16);
2820 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2822 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2826 if (dst
.regClass() == s1
) {
2827 if (instr
->op
== nir_op_ubfe
)
2828 opcode
= aco_opcode::s_bfe_u32
;
2830 opcode
= aco_opcode::s_bfe_i32
;
2831 } else if (dst
.regClass() == s2
) {
2832 if (instr
->op
== nir_op_ubfe
)
2833 opcode
= aco_opcode::s_bfe_u64
;
2835 opcode
= aco_opcode::s_bfe_i64
;
2837 unreachable("Unsupported BFE bit size");
2840 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2844 if (dst
.regClass() == v1
) {
2845 if (instr
->op
== nir_op_ubfe
)
2846 opcode
= aco_opcode::v_bfe_u32
;
2848 opcode
= aco_opcode::v_bfe_i32
;
2850 unreachable("Unsupported BFE bit size");
2853 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2857 case nir_op_bit_count
: {
2858 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2859 if (src
.regClass() == s1
) {
2860 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2861 } else if (src
.regClass() == v1
) {
2862 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2863 } else if (src
.regClass() == v2
) {
2864 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2865 emit_extract_vector(ctx
, src
, 1, v1
),
2866 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2867 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2868 } else if (src
.regClass() == s2
) {
2869 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2872 nir_print_instr(&instr
->instr
, stderr
);
2873 fprintf(stderr
, "\n");
2878 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2882 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2886 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2890 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2894 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2898 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2902 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2903 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2905 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2906 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2910 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2911 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2913 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2914 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2918 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2922 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2927 case nir_op_fddx_fine
:
2928 case nir_op_fddy_fine
:
2929 case nir_op_fddx_coarse
:
2930 case nir_op_fddy_coarse
: {
2931 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2932 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2933 if (instr
->op
== nir_op_fddx_fine
) {
2934 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2935 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2936 } else if (instr
->op
== nir_op_fddy_fine
) {
2937 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2938 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2940 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2941 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2942 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2944 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2948 if (ctx
->program
->chip_class
>= GFX8
) {
2949 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2950 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2952 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2953 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2954 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2956 emit_wqm(ctx
, tmp
, dst
, true);
2960 fprintf(stderr
, "Unknown NIR ALU instr: ");
2961 nir_print_instr(&instr
->instr
, stderr
);
2962 fprintf(stderr
, "\n");
2966 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2968 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2970 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2971 // which get truncated the lsb if double and msb if int
2972 // for now, we only use s_mov_b64 with 64bit inline constants
2973 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2974 assert(dst
.type() == RegType::sgpr
);
2976 Builder
bld(ctx
->program
, ctx
->block
);
2978 if (instr
->def
.bit_size
== 1) {
2979 assert(dst
.regClass() == bld
.lm
);
2980 int val
= instr
->value
[0].b
? -1 : 0;
2981 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2982 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2983 } else if (instr
->def
.bit_size
== 8) {
2984 /* ensure that the value is correctly represented in the low byte of the register */
2985 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2986 } else if (instr
->def
.bit_size
== 16) {
2987 /* ensure that the value is correctly represented in the low half of the register */
2988 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2989 } else if (dst
.size() == 1) {
2990 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2992 assert(dst
.size() != 1);
2993 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2994 if (instr
->def
.bit_size
== 64)
2995 for (unsigned i
= 0; i
< dst
.size(); i
++)
2996 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2998 for (unsigned i
= 0; i
< dst
.size(); i
++)
2999 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3001 vec
->definitions
[0] = Definition(dst
);
3002 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3006 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3008 uint32_t new_mask
= 0;
3009 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3010 if (mask
& (1u << i
))
3011 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3015 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3017 Builder
bld(ctx
->program
, ctx
->block
);
3018 if (offset
.isTemp()) {
3019 Temp tmp
[3] = {vec
, vec
, vec
};
3021 if (vec
.size() == 3) {
3022 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3023 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3024 } else if (vec
.size() == 2) {
3025 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3026 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3028 for (unsigned i
= 0; i
< dst
.size(); i
++)
3029 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3032 if (dst
.size() == 2)
3033 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3035 offset
= Operand(0u);
3038 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3039 bld
.copy(Definition(dst
), vec
);
3041 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3044 struct LoadEmitInfo
{
3047 unsigned num_components
;
3048 unsigned component_size
;
3049 Temp resource
= Temp(0, s1
);
3050 unsigned component_stride
= 0;
3051 unsigned const_offset
= 0;
3052 unsigned align_mul
= 0;
3053 unsigned align_offset
= 0;
3056 unsigned swizzle_component_size
= 0;
3057 barrier_interaction barrier
= barrier_none
;
3058 bool can_reorder
= true;
3059 Temp soffset
= Temp(0, s1
);
3062 using LoadCallback
= Temp(*)(
3063 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3064 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3066 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3067 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3069 unsigned load_size
= info
->num_components
* info
->component_size
;
3070 unsigned component_size
= info
->component_size
;
3072 unsigned num_vals
= 0;
3073 Temp vals
[info
->dst
.bytes()];
3075 unsigned const_offset
= info
->const_offset
;
3077 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3078 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3080 unsigned bytes_read
= 0;
3081 while (bytes_read
< load_size
) {
3082 unsigned bytes_needed
= load_size
- bytes_read
;
3084 /* add buffer for unaligned loads */
3085 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3088 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3089 if (info
->component_stride
) {
3090 assert(supports_8bit_16bit_loads
&& "unimplemented");
3094 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3095 bytes_needed
= align(bytes_needed
, 4);
3102 if (info
->swizzle_component_size
)
3103 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3104 if (info
->component_stride
)
3105 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3107 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3109 /* reduce constant offset */
3110 Operand offset
= info
->offset
;
3111 unsigned reduced_const_offset
= const_offset
;
3112 bool remove_const_offset_completely
= need_to_align_offset
;
3113 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3114 unsigned to_add
= const_offset
;
3115 if (remove_const_offset_completely
) {
3116 reduced_const_offset
= 0;
3118 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3119 reduced_const_offset
%= max_const_offset_plus_one
;
3121 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3122 if (offset
.isConstant()) {
3123 offset
= Operand(offset
.constantValue() + to_add
);
3124 } else if (offset_tmp
.regClass() == s1
) {
3125 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3126 offset_tmp
, Operand(to_add
));
3127 } else if (offset_tmp
.regClass() == v1
) {
3128 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3130 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3131 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3132 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3134 if (offset_tmp
.regClass() == s2
) {
3135 Temp carry
= bld
.tmp(s1
);
3136 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3137 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3138 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3140 Temp new_lo
= bld
.tmp(v1
);
3141 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3142 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3143 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3148 /* align offset down if needed */
3149 Operand aligned_offset
= offset
;
3150 if (need_to_align_offset
) {
3151 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3152 if (offset
.isConstant()) {
3153 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3154 } else if (offset_tmp
.regClass() == s1
) {
3155 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3156 } else if (offset_tmp
.regClass() == s2
) {
3157 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3158 } else if (offset_tmp
.regClass() == v1
) {
3159 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3160 } else if (offset_tmp
.regClass() == v2
) {
3161 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3162 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3163 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3164 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3167 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3168 bld
.copy(bld
.def(s1
), aligned_offset
);
3170 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3171 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3172 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3174 /* shift result right if needed */
3176 Operand
align((uint32_t)byte_align
);
3177 if (byte_align
== -1) {
3178 if (offset
.isConstant())
3179 align
= Operand(offset
.constantValue() % 4u);
3180 else if (offset
.size() == 2)
3181 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3186 if (align
.isTemp() || align
.constantValue()) {
3187 assert(val
.bytes() >= load_size
&& "unimplemented");
3188 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3189 if (val
.type() == RegType::sgpr
)
3190 byte_align_scalar(ctx
, val
, align
, new_val
);
3192 byte_align_vector(ctx
, val
, align
, new_val
);
3197 /* add result to list and advance */
3198 if (info
->component_stride
) {
3199 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3200 const_offset
+= info
->component_stride
;
3201 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3203 const_offset
+= val
.bytes();
3204 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3206 bytes_read
+= val
.bytes();
3207 vals
[num_vals
++] = val
;
3210 /* the callback wrote directly to dst */
3211 if (vals
[0] == info
->dst
) {
3212 assert(num_vals
== 1);
3213 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3217 /* create array of components */
3218 unsigned components_split
= 0;
3219 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3220 bool has_vgprs
= false;
3221 for (unsigned i
= 0; i
< num_vals
;) {
3223 unsigned num_tmps
= 0;
3224 unsigned tmp_size
= 0;
3225 RegType reg_type
= RegType::sgpr
;
3226 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3227 if (vals
[i
].type() == RegType::vgpr
)
3228 reg_type
= RegType::vgpr
;
3229 tmp_size
+= vals
[i
].bytes();
3230 tmp
[num_tmps
++] = vals
[i
++];
3233 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3234 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3235 for (unsigned i
= 0; i
< num_vals
; i
++)
3236 vec
->operands
[i
] = Operand(tmp
[i
]);
3237 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3238 vec
->definitions
[0] = Definition(tmp
[0]);
3239 bld
.insert(std::move(vec
));
3242 if (tmp
[0].bytes() % component_size
) {
3244 assert(i
== num_vals
);
3245 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3246 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3249 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3251 unsigned start
= components_split
;
3253 if (tmp_size
== elem_rc
.bytes()) {
3254 allocated_vec
[components_split
++] = tmp
[0];
3256 assert(tmp_size
% elem_rc
.bytes() == 0);
3257 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3258 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3259 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3260 Temp component
= bld
.tmp(elem_rc
);
3261 allocated_vec
[components_split
++] = component
;
3262 split
->definitions
[i
] = Definition(component
);
3264 split
->operands
[0] = Operand(tmp
[0]);
3265 bld
.insert(std::move(split
));
3268 /* try to p_as_uniform early so we can create more optimizable code and
3269 * also update allocated_vec */
3270 for (unsigned j
= start
; j
< components_split
; j
++) {
3271 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3272 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3273 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3277 /* concatenate components and p_as_uniform() result if needed */
3278 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3279 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3281 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3283 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3284 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3285 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3286 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3288 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3289 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3290 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3291 vec
->definitions
[0] = Definition(tmp
);
3292 bld
.insert(std::move(vec
));
3293 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3295 vec
->definitions
[0] = Definition(info
->dst
);
3296 bld
.insert(std::move(vec
));
3300 Operand
load_lds_size_m0(Builder
& bld
)
3302 /* TODO: m0 does not need to be initialized on GFX9+ */
3303 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3306 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3307 Temp offset
, unsigned bytes_needed
,
3308 unsigned align
, unsigned const_offset
,
3311 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3313 Operand m
= load_lds_size_m0(bld
);
3315 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3316 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3321 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3322 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3324 op
= aco_opcode::ds_read_b128
;
3325 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3328 op
= aco_opcode::ds_read2_b64
;
3329 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3331 op
= aco_opcode::ds_read_b96
;
3332 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3334 op
= aco_opcode::ds_read_b64
;
3335 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3338 op
= aco_opcode::ds_read2_b32
;
3339 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3341 op
= aco_opcode::ds_read_b32
;
3342 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3344 op
= aco_opcode::ds_read_u16
;
3347 op
= aco_opcode::ds_read_u8
;
3350 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3351 if (const_offset
>= max_offset_plus_one
) {
3352 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3353 const_offset
%= max_offset_plus_one
;
3357 const_offset
/= (size
/ 2u);
3359 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3360 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3362 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3364 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3367 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3372 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3374 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3375 Temp offset
, unsigned bytes_needed
,
3376 unsigned align
, unsigned const_offset
,
3381 if (bytes_needed
<= 4) {
3383 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3384 } else if (bytes_needed
<= 8) {
3386 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3387 } else if (bytes_needed
<= 16) {
3389 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3390 } else if (bytes_needed
<= 32) {
3392 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3395 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3397 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3398 if (info
->resource
.id()) {
3399 load
->operands
[0] = Operand(info
->resource
);
3400 load
->operands
[1] = Operand(offset
);
3402 load
->operands
[0] = Operand(offset
);
3403 load
->operands
[1] = Operand(0u);
3405 RegClass
rc(RegType::sgpr
, size
);
3406 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3407 load
->definitions
[0] = Definition(val
);
3408 load
->glc
= info
->glc
;
3409 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3410 load
->barrier
= info
->barrier
;
3411 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3412 bld
.insert(std::move(load
));
3416 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3418 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3419 Temp offset
, unsigned bytes_needed
,
3420 unsigned align_
, unsigned const_offset
,
3423 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3424 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3426 if (info
->soffset
.id()) {
3427 if (soffset
.isTemp())
3428 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3429 soffset
= Operand(info
->soffset
);
3432 unsigned bytes_size
= 0;
3434 if (bytes_needed
== 1) {
3436 op
= aco_opcode::buffer_load_ubyte
;
3437 } else if (bytes_needed
== 2) {
3439 op
= aco_opcode::buffer_load_ushort
;
3440 } else if (bytes_needed
<= 4) {
3442 op
= aco_opcode::buffer_load_dword
;
3443 } else if (bytes_needed
<= 8) {
3445 op
= aco_opcode::buffer_load_dwordx2
;
3446 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3448 op
= aco_opcode::buffer_load_dwordx3
;
3451 op
= aco_opcode::buffer_load_dwordx4
;
3453 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3454 mubuf
->operands
[0] = Operand(info
->resource
);
3455 mubuf
->operands
[1] = vaddr
;
3456 mubuf
->operands
[2] = soffset
;
3457 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3458 mubuf
->glc
= info
->glc
;
3459 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3460 mubuf
->barrier
= info
->barrier
;
3461 mubuf
->can_reorder
= info
->can_reorder
;
3462 mubuf
->offset
= const_offset
;
3463 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3464 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3465 mubuf
->definitions
[0] = Definition(val
);
3466 bld
.insert(std::move(mubuf
));
3469 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3474 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3476 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3478 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3479 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3481 if (addr
.type() == RegType::vgpr
)
3482 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3483 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3486 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3487 Temp offset
, unsigned bytes_needed
,
3488 unsigned align_
, unsigned const_offset
,
3491 unsigned bytes_size
= 0;
3492 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3493 bool global
= bld
.program
->chip_class
>= GFX9
;
3495 if (bytes_needed
== 1) {
3497 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3498 } else if (bytes_needed
== 2) {
3500 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3501 } else if (bytes_needed
<= 4) {
3503 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3504 } else if (bytes_needed
<= 8) {
3506 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3507 } else if (bytes_needed
<= 12 && !mubuf
) {
3509 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3512 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3514 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3515 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3517 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3518 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3519 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3520 mubuf
->operands
[2] = Operand(0u);
3521 mubuf
->glc
= info
->glc
;
3524 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3525 mubuf
->disable_wqm
= false;
3526 mubuf
->barrier
= info
->barrier
;
3527 mubuf
->definitions
[0] = Definition(val
);
3528 bld
.insert(std::move(mubuf
));
3530 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3532 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3533 flat
->operands
[0] = Operand(offset
);
3534 flat
->operands
[1] = Operand(s1
);
3535 flat
->glc
= info
->glc
;
3536 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3537 flat
->barrier
= info
->barrier
;
3539 flat
->definitions
[0] = Definition(val
);
3540 bld
.insert(std::move(flat
));
3544 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3549 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3551 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3552 Temp address
, unsigned base_offset
, unsigned align
)
3554 assert(util_is_power_of_two_nonzero(align
));
3556 Builder
bld(ctx
->program
, ctx
->block
);
3558 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3559 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3560 info
.align_mul
= align
;
3561 info
.align_offset
= 0;
3562 info
.barrier
= barrier_shared
;
3563 info
.can_reorder
= false;
3564 info
.const_offset
= base_offset
;
3565 emit_lds_load(ctx
, bld
, &info
);
3570 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3575 Builder
bld(ctx
->program
, ctx
->block
);
3577 ASSERTED
bool is_subdword
= false;
3578 for (unsigned i
= 0; i
< count
; i
++)
3579 is_subdword
|= offsets
[i
] % 4;
3580 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3581 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3583 /* count == 1 fast path */
3585 if (dst_type
== RegType::sgpr
)
3586 dst
[0] = bld
.as_uniform(src
);
3588 dst
[0] = as_vgpr(ctx
, src
);
3592 for (unsigned i
= 0; i
< count
- 1; i
++)
3593 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3594 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3596 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3597 src
= as_vgpr(ctx
, src
);
3599 /* use allocated_vec if possible */
3600 auto it
= ctx
->allocated_vec
.find(src
.id());
3601 if (it
!= ctx
->allocated_vec
.end()) {
3602 unsigned total_size
= 0;
3603 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3604 total_size
+= it
->second
[i
].bytes();
3605 if (total_size
!= src
.bytes())
3608 unsigned elem_size
= it
->second
[0].bytes();
3610 for (unsigned i
= 0; i
< count
; i
++) {
3611 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3615 for (unsigned i
= 0; i
< count
; i
++) {
3616 unsigned start_idx
= offsets
[i
] / elem_size
;
3617 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3618 if (op_count
== 1) {
3619 if (dst_type
== RegType::sgpr
)
3620 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3622 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3626 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3627 for (unsigned j
= 0; j
< op_count
; j
++) {
3628 Temp tmp
= it
->second
[start_idx
+ j
];
3629 if (dst_type
== RegType::sgpr
)
3630 tmp
= bld
.as_uniform(tmp
);
3631 vec
->operands
[j
] = Operand(tmp
);
3633 vec
->definitions
[0] = Definition(dst
[i
]);
3634 bld
.insert(std::move(vec
));
3640 if (dst_type
== RegType::sgpr
)
3641 src
= bld
.as_uniform(src
);
3645 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3646 split
->operands
[0] = Operand(src
);
3647 for (unsigned i
= 0; i
< count
; i
++)
3648 split
->definitions
[i
] = Definition(dst
[i
]);
3649 bld
.insert(std::move(split
));
3652 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3653 int *start
, int *count
)
3655 unsigned start_elem
= ffs(todo_mask
) - 1;
3656 bool skip
= !(mask
& (1 << start_elem
));
3658 mask
= ~mask
& todo_mask
;
3662 u_bit_scan_consecutive_range(&mask
, start
, count
);
3667 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3669 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3672 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3673 Temp address
, unsigned base_offset
, unsigned align
)
3675 assert(util_is_power_of_two_nonzero(align
));
3676 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3678 Builder
bld(ctx
->program
, ctx
->block
);
3679 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3680 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3682 unsigned write_count
= 0;
3683 Temp write_datas
[32];
3684 unsigned offsets
[32];
3685 aco_opcode opcodes
[32];
3687 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3689 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3692 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3693 offsets
[write_count
] = offset
;
3694 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3696 advance_write_mask(&todo
, offset
, bytes
);
3700 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3701 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3702 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3703 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3705 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3706 aco_opcode op
= aco_opcode::num_opcodes
;
3707 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3708 op
= aco_opcode::ds_write_b128
;
3710 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3711 op
= aco_opcode::ds_write_b96
;
3713 } else if (bytes
>= 8 && aligned8
) {
3714 op
= aco_opcode::ds_write_b64
;
3716 } else if (bytes
>= 4 && aligned4
) {
3717 op
= aco_opcode::ds_write_b32
;
3719 } else if (bytes
>= 2 && aligned2
) {
3720 op
= aco_opcode::ds_write_b16
;
3722 } else if (bytes
>= 1) {
3723 op
= aco_opcode::ds_write_b8
;
3729 offsets
[write_count
] = offset
;
3730 opcodes
[write_count
] = op
;
3732 advance_write_mask(&todo
, offset
, bytes
);
3735 Operand m
= load_lds_size_m0(bld
);
3737 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3739 for (unsigned i
= 0; i
< write_count
; i
++) {
3740 aco_opcode op
= opcodes
[i
];
3741 if (op
== aco_opcode::num_opcodes
)
3744 Temp data
= write_datas
[i
];
3746 unsigned second
= write_count
;
3747 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3748 for (second
= i
+ 1; second
< write_count
; second
++) {
3749 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3750 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3751 opcodes
[second
] = aco_opcode::num_opcodes
;
3757 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3758 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3760 unsigned inline_offset
= base_offset
+ offsets
[i
];
3761 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3762 Temp address_offset
= address
;
3763 if (inline_offset
> max_offset
) {
3764 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3765 inline_offset
= offsets
[i
];
3767 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3770 Temp second_data
= write_datas
[second
];
3771 inline_offset
/= data
.bytes();
3772 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3774 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3779 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3781 unsigned align
= 16;
3783 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3789 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3794 return aco_opcode::buffer_store_byte
;
3797 return aco_opcode::buffer_store_short
;
3799 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3801 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3804 return aco_opcode::buffer_store_dwordx3
;
3806 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3808 unreachable("Unexpected store size");
3809 return aco_opcode::num_opcodes
;
3812 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3813 Temp data
, unsigned writemask
, int swizzle_element_size
,
3814 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3816 unsigned write_count_with_skips
= 0;
3819 /* determine how to split the data */
3820 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3823 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3824 offsets
[write_count_with_skips
] = offset
;
3825 if (skips
[write_count_with_skips
]) {
3826 advance_write_mask(&todo
, offset
, bytes
);
3827 write_count_with_skips
++;
3831 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3832 * larger than swizzle_element_size */
3833 bytes
= MIN2(bytes
, swizzle_element_size
);
3835 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3837 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3838 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3841 /* dword or larger stores have to be dword-aligned */
3842 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3843 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3844 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3845 if (bytes
>= 4 && !dword_aligned
)
3846 bytes
= MIN2(bytes
, 2);
3848 advance_write_mask(&todo
, offset
, bytes
);
3849 write_count_with_skips
++;
3852 /* actually split data */
3853 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3856 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3859 write_datas
[*write_count
] = write_datas
[i
];
3860 offsets
[*write_count
] = offsets
[i
];
3865 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3866 unsigned split_cnt
= 0u, Temp dst
= Temp())
3868 Builder
bld(ctx
->program
, ctx
->block
);
3869 unsigned dword_size
= elem_size_bytes
/ 4;
3872 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3874 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3875 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3876 instr
->definitions
[0] = Definition(dst
);
3878 for (unsigned i
= 0; i
< cnt
; ++i
) {
3880 assert(arr
[i
].size() == dword_size
);
3881 allocated_vec
[i
] = arr
[i
];
3882 instr
->operands
[i
] = Operand(arr
[i
]);
3884 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3885 allocated_vec
[i
] = zero
;
3886 instr
->operands
[i
] = Operand(zero
);
3890 bld
.insert(std::move(instr
));
3893 emit_split_vector(ctx
, dst
, split_cnt
);
3895 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3900 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3902 if (const_offset
>= 4096) {
3903 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3904 const_offset
%= 4096u;
3907 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3908 else if (unlikely(voffset
.regClass() == s1
))
3909 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3910 else if (likely(voffset
.regClass() == v1
))
3911 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3913 unreachable("Unsupported register class of voffset");
3916 return const_offset
;
3919 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3920 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3923 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3924 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3926 Builder
bld(ctx
->program
, ctx
->block
);
3927 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3928 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3930 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3931 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3932 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3933 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3934 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3936 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3939 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3940 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3941 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3943 Builder
bld(ctx
->program
, ctx
->block
);
3944 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3946 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3948 unsigned write_count
= 0;
3949 Temp write_datas
[32];
3950 unsigned offsets
[32];
3951 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3952 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3954 for (unsigned i
= 0; i
< write_count
; i
++) {
3955 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3956 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3960 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3961 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3962 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3964 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3965 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3966 assert(!!stride
!= allow_combining
);
3968 Builder
bld(ctx
->program
, ctx
->block
);
3970 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3971 info
.component_stride
= allow_combining
? 0 : stride
;
3973 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3974 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3975 info
.align_offset
= 0;
3976 info
.soffset
= soffset
;
3977 info
.const_offset
= base_const_offset
;
3978 emit_mubuf_load(ctx
, bld
, &info
);
3981 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3983 Builder
bld(ctx
->program
, ctx
->block
);
3984 Temp offset
= base_offset
.first
;
3985 unsigned const_offset
= base_offset
.second
;
3987 if (!nir_src_is_const(*off_src
)) {
3988 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3991 /* Calculate indirect offset with stride */
3992 if (likely(indirect_offset_arg
.regClass() == v1
))
3993 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3994 else if (indirect_offset_arg
.regClass() == s1
)
3995 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3997 unreachable("Unsupported register class of indirect offset");
3999 /* Add to the supplied base offset */
4000 if (offset
.id() == 0)
4001 offset
= with_stride
;
4002 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4003 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4004 else if (offset
.size() == 1 && with_stride
.size() == 1)
4005 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4007 unreachable("Unsupported register class of indirect offset");
4009 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4010 const_offset
+= const_offset_arg
* stride
;
4013 return std::make_pair(offset
, const_offset
);
4016 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4018 Builder
bld(ctx
->program
, ctx
->block
);
4021 if (off1
.first
.id() && off2
.first
.id()) {
4022 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4023 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4024 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4025 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4027 unreachable("Unsupported register class of indirect offset");
4029 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4032 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4035 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4037 Builder
bld(ctx
->program
, ctx
->block
);
4038 unsigned const_offset
= offs
.second
* multiplier
;
4040 if (!offs
.first
.id())
4041 return std::make_pair(offs
.first
, const_offset
);
4043 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4044 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4045 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4047 return std::make_pair(offset
, const_offset
);
4050 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4052 Builder
bld(ctx
->program
, ctx
->block
);
4054 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4055 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4056 /* component is in bytes */
4057 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4059 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4060 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4061 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4064 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4066 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4069 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4071 Builder
bld(ctx
->program
, ctx
->block
);
4073 switch (ctx
->shader
->info
.stage
) {
4074 case MESA_SHADER_TESS_CTRL
:
4075 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4076 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4077 case MESA_SHADER_TESS_EVAL
:
4078 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4080 unreachable("Unsupported stage in get_tess_rel_patch_id");
4084 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4086 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4087 Builder
bld(ctx
->program
, ctx
->block
);
4089 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4090 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4092 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4094 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4095 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4097 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4098 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4099 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4101 return offset_mul(ctx
, offs
, 4u);
4104 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4106 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4107 Builder
bld(ctx
->program
, ctx
->block
);
4109 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4110 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4111 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4112 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4114 std::pair
<Temp
, unsigned> offs
= instr
4115 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4116 : std::make_pair(Temp(), 0u);
4118 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4119 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4124 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4125 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4127 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4128 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4130 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4131 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4137 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4139 Builder
bld(ctx
->program
, ctx
->block
);
4141 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4142 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4144 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4146 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4147 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4148 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4150 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4151 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4156 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4158 Builder
bld(ctx
->program
, ctx
->block
);
4160 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4161 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4162 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4163 unsigned attr_stride
= ctx
->tcs_num_patches
;
4165 std::pair
<Temp
, unsigned> offs
= instr
4166 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4167 : std::make_pair(Temp(), 0u);
4169 if (const_base_offset
)
4170 offs
.second
+= const_base_offset
* attr_stride
;
4172 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4173 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4174 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4179 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4181 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4186 unsigned drv_loc
= nir_intrinsic_base(instr
);
4187 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4189 if (!nir_src_is_const(*off_src
)) {
4195 uint64_t slot
= per_vertex
4196 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4197 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4198 return (((uint64_t) 1) << slot
) & mask
;
4201 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4203 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4204 unsigned component
= nir_intrinsic_component(instr
);
4205 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4207 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4208 if (off_instr
->type
!= nir_instr_type_load_const
)
4211 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4212 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4214 if (instr
->src
[0].ssa
->bit_size
== 64)
4215 write_mask
= widen_mask(write_mask
, 2);
4217 for (unsigned i
= 0; i
< 8; ++i
) {
4218 if (write_mask
& (1 << i
)) {
4219 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4220 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4228 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4230 /* Only TCS per-vertex inputs are supported by this function.
4231 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4233 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4236 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4237 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4238 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4239 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4240 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4241 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4246 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4247 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4248 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4253 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4255 Builder
bld(ctx
->program
, ctx
->block
);
4257 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4258 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4259 bool indirect_write
;
4260 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4261 if (temp_only_input
&& !indirect_write
)
4265 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4266 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4267 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4268 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4270 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4271 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4272 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4273 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4274 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4278 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4279 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4280 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4281 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4282 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4283 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4284 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4285 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4286 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4287 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4288 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4289 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4290 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4292 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4293 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4295 unreachable("Invalid LS or ES stage");
4298 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4299 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4300 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4304 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4309 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4310 return off
== ctx
->tcs_tess_lvl_out_loc
||
4311 off
== ctx
->tcs_tess_lvl_in_loc
;
4315 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4317 uint64_t mask
= per_vertex
4318 ? ctx
->program
->info
->tcs
.tes_inputs_read
4319 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4321 bool indirect_write
= false;
4322 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4323 return indirect_write
|| output_read_by_tes
;
4326 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4328 uint64_t mask
= per_vertex
4329 ? ctx
->shader
->info
.outputs_read
4330 : ctx
->shader
->info
.patch_outputs_read
;
4332 bool indirect_write
= false;
4333 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4334 return indirect_write
|| output_read
;
4337 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4339 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4340 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4342 Builder
bld(ctx
->program
, ctx
->block
);
4344 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4345 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4346 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4348 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4349 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4350 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4352 if (write_to_vmem
) {
4353 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4354 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4355 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4357 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4358 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4359 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4363 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4364 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4365 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4369 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4371 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4372 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4374 Builder
bld(ctx
->program
, ctx
->block
);
4376 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4377 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4378 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4379 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4381 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4384 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4386 if (ctx
->stage
== vertex_vs
||
4387 ctx
->stage
== tess_eval_vs
||
4388 ctx
->stage
== fragment_fs
||
4389 ctx
->stage
== ngg_vertex_gs
||
4390 ctx
->stage
== ngg_tess_eval_gs
||
4391 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4392 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4393 if (!stored_to_temps
) {
4394 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4395 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4396 fprintf(stderr
, "\n");
4399 } else if (ctx
->stage
== vertex_es
||
4400 ctx
->stage
== vertex_ls
||
4401 ctx
->stage
== tess_eval_es
||
4402 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4403 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4404 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4405 visit_store_ls_or_es_output(ctx
, instr
);
4406 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4407 visit_store_tcs_output(ctx
, instr
, false);
4409 unreachable("Shader stage not implemented");
4413 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4415 visit_load_tcs_output(ctx
, instr
, false);
4418 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4420 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4421 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4423 Builder
bld(ctx
->program
, ctx
->block
);
4424 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4425 if (ctx
->program
->has_16bank_lds
)
4426 interp_p1
.instr
->operands
[0].setLateKill(true);
4427 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4430 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4432 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4433 for (unsigned i
= 0; i
< num_components
; i
++)
4434 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4435 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4436 assert(num_components
== 4);
4437 Builder
bld(ctx
->program
, ctx
->block
);
4438 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4441 for (Operand
& op
: vec
->operands
)
4442 op
= op
.isUndefined() ? Operand(0u) : op
;
4444 vec
->definitions
[0] = Definition(dst
);
4445 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4446 emit_split_vector(ctx
, dst
, num_components
);
4450 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4452 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4453 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4454 unsigned idx
= nir_intrinsic_base(instr
);
4455 unsigned component
= nir_intrinsic_component(instr
);
4456 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4458 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4460 assert(offset
->u32
== 0);
4462 /* the lower 15bit of the prim_mask contain the offset into LDS
4463 * while the upper bits contain the number of prims */
4464 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4465 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4466 Builder
bld(ctx
->program
, ctx
->block
);
4467 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4468 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4469 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4470 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4471 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4474 if (instr
->dest
.ssa
.num_components
== 1) {
4475 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4477 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4478 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4480 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4481 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4482 vec
->operands
[i
] = Operand(tmp
);
4484 vec
->definitions
[0] = Definition(dst
);
4485 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4489 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4490 unsigned offset
, unsigned stride
, unsigned channels
)
4492 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4493 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4495 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4496 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4499 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4500 unsigned offset
, unsigned stride
, unsigned *channels
)
4502 if (!vtx_info
->chan_byte_size
) {
4503 *channels
= vtx_info
->num_channels
;
4504 return vtx_info
->chan_format
;
4507 unsigned num_channels
= *channels
;
4508 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4509 unsigned new_channels
= num_channels
+ 1;
4510 /* first, assume more loads is worse and try using a larger data format */
4511 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4513 /* don't make the attribute potentially out-of-bounds */
4514 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4518 if (new_channels
== 5) {
4519 /* then try decreasing load size (at the cost of more loads) */
4520 new_channels
= *channels
;
4521 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4525 if (new_channels
< *channels
)
4526 *channels
= new_channels
;
4527 num_channels
= new_channels
;
4530 switch (vtx_info
->chan_format
) {
4531 case V_008F0C_BUF_DATA_FORMAT_8
:
4532 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4533 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4534 case V_008F0C_BUF_DATA_FORMAT_16
:
4535 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4536 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4537 case V_008F0C_BUF_DATA_FORMAT_32
:
4538 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4539 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4541 unreachable("shouldn't reach here");
4542 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4545 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4546 * so we may need to fix it up. */
4547 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4549 Builder
bld(ctx
->program
, ctx
->block
);
4551 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4552 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4554 /* For the integer-like cases, do a natural sign extension.
4556 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4557 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4560 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4561 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4563 /* Convert back to the right type. */
4564 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4565 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4566 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4567 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4568 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4569 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4575 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4577 Builder
bld(ctx
->program
, ctx
->block
);
4578 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4579 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4581 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4582 if (off_instr
->type
!= nir_instr_type_load_const
) {
4583 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4584 nir_print_instr(off_instr
, stderr
);
4585 fprintf(stderr
, "\n");
4587 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4589 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4591 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4592 unsigned component
= nir_intrinsic_component(instr
);
4593 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4594 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4595 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4596 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4598 unsigned dfmt
= attrib_format
& 0xf;
4599 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4600 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4602 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4603 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4604 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4605 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4607 num_channels
= MAX2(num_channels
, 3);
4609 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4610 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4613 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4614 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4615 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4617 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4619 Temp divided
= bld
.tmp(v1
);
4620 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4621 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4623 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4626 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4629 index
= bld
.vadd32(bld
.def(v1
),
4630 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4631 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4634 Temp channels
[num_channels
];
4635 unsigned channel_start
= 0;
4636 bool direct_fetch
= false;
4638 /* skip unused channels at the start */
4639 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4640 channel_start
= ffs(mask
) - 1;
4641 for (unsigned i
= 0; i
< channel_start
; i
++)
4642 channels
[i
] = Temp(0, s1
);
4643 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4644 num_channels
= 3 - (ffs(mask
) - 1);
4648 while (channel_start
< num_channels
) {
4649 unsigned fetch_size
= num_channels
- channel_start
;
4650 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4651 bool expanded
= false;
4653 /* use MUBUF when possible to avoid possible alignment issues */
4654 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4655 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4656 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4657 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4658 vtx_info
->chan_byte_size
== 4;
4659 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4661 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4663 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4664 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4670 Temp fetch_index
= index
;
4671 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4672 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4673 fetch_offset
= fetch_offset
% attrib_stride
;
4676 Operand
soffset(0u);
4677 if (fetch_offset
>= 4096) {
4678 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4679 fetch_offset
%= 4096;
4683 switch (fetch_size
) {
4685 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4688 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4691 assert(ctx
->options
->chip_class
>= GFX7
||
4692 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4693 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4696 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4699 unreachable("Unimplemented load_input vector size");
4703 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4704 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4705 num_channels
<= 3)) {
4706 direct_fetch
= true;
4709 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4713 Instruction
*mubuf
= bld
.mubuf(opcode
,
4714 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4715 fetch_offset
, false, true).instr
;
4716 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4718 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4719 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4720 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4721 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4724 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4726 if (fetch_size
== 1) {
4727 channels
[channel_start
] = fetch_dst
;
4729 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4730 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4733 channel_start
+= fetch_size
;
4736 if (!direct_fetch
) {
4737 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4738 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4740 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4741 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4742 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4744 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4745 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4746 unsigned num_temp
= 0;
4747 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4748 unsigned idx
= i
+ component
;
4749 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4750 Temp channel
= channels
[swizzle
[idx
]];
4751 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4752 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4753 vec
->operands
[i
] = Operand(channel
);
4757 } else if (is_float
&& idx
== 3) {
4758 vec
->operands
[i
] = Operand(0x3f800000u
);
4759 } else if (!is_float
&& idx
== 3) {
4760 vec
->operands
[i
] = Operand(1u);
4762 vec
->operands
[i
] = Operand(0u);
4765 vec
->definitions
[0] = Definition(dst
);
4766 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4767 emit_split_vector(ctx
, dst
, dst
.size());
4769 if (num_temp
== dst
.size())
4770 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4772 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4773 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4774 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4775 if (off_instr
->type
!= nir_instr_type_load_const
||
4776 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4777 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4778 nir_print_instr(off_instr
, stderr
);
4779 fprintf(stderr
, "\n");
4782 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4783 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4785 assert(offset
->u32
== 0);
4787 /* the lower 15bit of the prim_mask contain the offset into LDS
4788 * while the upper bits contain the number of prims */
4789 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4790 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4791 Builder
bld(ctx
->program
, ctx
->block
);
4792 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4793 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4794 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4795 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4796 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4799 unsigned idx
= nir_intrinsic_base(instr
);
4800 unsigned component
= nir_intrinsic_component(instr
);
4801 unsigned vertex_id
= 2; /* P0 */
4803 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4804 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4805 switch (src0
->u32
) {
4807 vertex_id
= 2; /* P0 */
4810 vertex_id
= 0; /* P10 */
4813 vertex_id
= 1; /* P20 */
4816 unreachable("invalid vertex index");
4820 if (dst
.size() == 1) {
4821 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4823 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4824 for (unsigned i
= 0; i
< dst
.size(); i
++)
4825 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4826 vec
->definitions
[0] = Definition(dst
);
4827 bld
.insert(std::move(vec
));
4830 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4831 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4832 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4833 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4834 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4836 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4838 unreachable("Shader stage not implemented");
4842 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4844 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4846 Builder
bld(ctx
->program
, ctx
->block
);
4847 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4850 if (!nir_src_is_const(*vertex_src
)) {
4851 /* better code could be created, but this case probably doesn't happen
4852 * much in practice */
4853 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4854 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4857 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4858 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4860 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4862 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4865 if (vertex_offset
.id()) {
4866 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4867 Operand(i
), indirect_vertex
);
4868 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4870 vertex_offset
= elem
;
4874 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4875 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4877 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4878 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4879 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4880 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4881 Operand((vertex
% 2u) * 16u), Operand(16u));
4883 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4886 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4887 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4888 return offset_mul(ctx
, offs
, 4u);
4891 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4893 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4895 Builder
bld(ctx
->program
, ctx
->block
);
4896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4897 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4899 if (ctx
->stage
== geometry_gs
) {
4900 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4901 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4902 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4903 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4904 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4905 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4906 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4908 unreachable("Unsupported GS stage.");
4912 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4914 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4916 Builder
bld(ctx
->program
, ctx
->block
);
4917 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4919 if (load_input_from_temps(ctx
, instr
, dst
))
4922 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4923 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4924 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4926 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4929 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4931 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4933 Builder
bld(ctx
->program
, ctx
->block
);
4935 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4936 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4937 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4939 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4940 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4942 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4945 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4947 switch (ctx
->shader
->info
.stage
) {
4948 case MESA_SHADER_GEOMETRY
:
4949 visit_load_gs_per_vertex_input(ctx
, instr
);
4951 case MESA_SHADER_TESS_CTRL
:
4952 visit_load_tcs_per_vertex_input(ctx
, instr
);
4954 case MESA_SHADER_TESS_EVAL
:
4955 visit_load_tes_per_vertex_input(ctx
, instr
);
4958 unreachable("Unimplemented shader stage");
4962 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4964 visit_load_tcs_output(ctx
, instr
, true);
4967 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4969 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4970 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4972 visit_store_tcs_output(ctx
, instr
, true);
4975 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4977 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4979 Builder
bld(ctx
->program
, ctx
->block
);
4980 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4982 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4983 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4986 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4987 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4988 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4989 tes_w
= Operand(tmp
);
4992 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4993 emit_split_vector(ctx
, tess_coord
, 3);
4996 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4998 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4999 Builder
bld(ctx
->program
, ctx
->block
);
5000 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5001 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5002 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5005 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5009 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5011 Builder
bld(ctx
->program
, ctx
->block
);
5012 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5013 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
5014 index
= bld
.as_uniform(index
);
5015 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5016 unsigned binding
= nir_intrinsic_binding(instr
);
5019 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5020 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5021 unsigned offset
= layout
->binding
[binding
].offset
;
5023 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5024 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5025 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5026 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5027 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5030 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5031 stride
= layout
->binding
[binding
].size
;
5034 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5035 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5037 if (nir_const_index
) {
5038 const_index
= const_index
* stride
;
5039 } else if (index
.type() == RegType::vgpr
) {
5040 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5041 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5043 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5047 if (nir_const_index
) {
5048 const_index
= const_index
+ offset
;
5049 } else if (index
.type() == RegType::vgpr
) {
5050 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5052 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5056 if (nir_const_index
&& const_index
== 0) {
5058 } else if (index
.type() == RegType::vgpr
) {
5059 index
= bld
.vadd32(bld
.def(v1
),
5060 nir_const_index
? Operand(const_index
) : Operand(index
),
5063 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5064 nir_const_index
? Operand(const_index
) : Operand(index
),
5068 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5071 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5072 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5073 bool glc
=false, bool readonly
=true)
5075 Builder
bld(ctx
->program
, ctx
->block
);
5077 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5079 offset
= bld
.as_uniform(offset
);
5081 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5083 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5084 info
.can_reorder
= readonly
;
5085 info
.align_mul
= align_mul
;
5086 info
.align_offset
= align_offset
;
5088 emit_smem_load(ctx
, bld
, &info
);
5090 emit_mubuf_load(ctx
, bld
, &info
);
5093 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5095 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5096 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5098 Builder
bld(ctx
->program
, ctx
->block
);
5100 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5101 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5102 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5103 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5105 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5106 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5107 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5108 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5109 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5110 if (ctx
->options
->chip_class
>= GFX10
) {
5111 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5112 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5113 S_008F0C_RESOURCE_LEVEL(1);
5115 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5116 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5118 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5119 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5120 Operand(0xFFFFFFFFu
),
5121 Operand(desc_type
));
5122 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5123 rsrc
, upper_dwords
);
5125 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5126 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5128 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5129 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5130 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5133 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5135 Builder
bld(ctx
->program
, ctx
->block
);
5136 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5137 unsigned offset
= nir_intrinsic_base(instr
);
5138 unsigned count
= instr
->dest
.ssa
.num_components
;
5139 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5141 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5142 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5143 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5144 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5145 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5146 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5147 for (unsigned i
= 0; i
< count
; ++i
) {
5148 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5149 vec
->operands
[i
] = Operand
{elems
[i
]};
5151 vec
->definitions
[0] = Definition(dst
);
5152 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5153 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5158 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5159 if (offset
!= 0) // TODO check if index != 0 as well
5160 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5161 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5164 bool aligned
= true;
5166 if (instr
->dest
.ssa
.bit_size
== 8) {
5167 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5168 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5170 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5171 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5172 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5174 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5179 switch (vec
.size()) {
5181 op
= aco_opcode::s_load_dword
;
5184 op
= aco_opcode::s_load_dwordx2
;
5190 op
= aco_opcode::s_load_dwordx4
;
5196 op
= aco_opcode::s_load_dwordx8
;
5199 unreachable("unimplemented or forbidden load_push_constant.");
5202 bld
.smem(op
, Definition(vec
), ptr
, index
);
5205 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5206 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5211 emit_split_vector(ctx
, vec
, 4);
5212 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5213 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5214 emit_extract_vector(ctx
, vec
, 0, rc
),
5215 emit_extract_vector(ctx
, vec
, 1, rc
),
5216 emit_extract_vector(ctx
, vec
, 2, rc
));
5219 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5222 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5224 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5226 Builder
bld(ctx
->program
, ctx
->block
);
5228 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5229 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5230 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5231 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5232 if (ctx
->options
->chip_class
>= GFX10
) {
5233 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5234 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5235 S_008F0C_RESOURCE_LEVEL(1);
5237 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5238 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5241 unsigned base
= nir_intrinsic_base(instr
);
5242 unsigned range
= nir_intrinsic_range(instr
);
5244 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5245 if (base
&& offset
.type() == RegType::sgpr
)
5246 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5247 else if (base
&& offset
.type() == RegType::vgpr
)
5248 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5250 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5251 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5252 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5253 Operand(desc_type
));
5254 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5255 // TODO: get alignment information for subdword constants
5256 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5259 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5261 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5262 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5264 ctx
->program
->needs_exact
= true;
5266 // TODO: optimize uniform conditions
5267 Builder
bld(ctx
->program
, ctx
->block
);
5268 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5269 assert(src
.regClass() == bld
.lm
);
5270 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5271 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5272 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5276 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5278 Builder
bld(ctx
->program
, ctx
->block
);
5280 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5281 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5283 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5284 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5286 if (ctx
->block
->loop_nest_depth
&&
5287 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5288 /* we handle discards the same way as jump instructions */
5289 append_logical_end(ctx
->block
);
5291 /* in loops, discard behaves like break */
5292 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5293 ctx
->block
->kind
|= block_kind_discard
;
5296 /* uniform discard - loop ends here */
5297 assert(nir_instr_is_last(&instr
->instr
));
5298 ctx
->block
->kind
|= block_kind_uniform
;
5299 ctx
->cf_info
.has_branch
= true;
5300 bld
.branch(aco_opcode::p_branch
);
5301 add_linear_edge(ctx
->block
->index
, linear_target
);
5305 /* we add a break right behind the discard() instructions */
5306 ctx
->block
->kind
|= block_kind_break
;
5307 unsigned idx
= ctx
->block
->index
;
5309 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5310 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5312 /* remove critical edges from linear CFG */
5313 bld
.branch(aco_opcode::p_branch
);
5314 Block
* break_block
= ctx
->program
->create_and_insert_block();
5315 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5316 break_block
->kind
|= block_kind_uniform
;
5317 add_linear_edge(idx
, break_block
);
5318 add_linear_edge(break_block
->index
, linear_target
);
5319 bld
.reset(break_block
);
5320 bld
.branch(aco_opcode::p_branch
);
5322 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5323 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5324 add_linear_edge(idx
, continue_block
);
5325 append_logical_start(continue_block
);
5326 ctx
->block
= continue_block
;
5331 /* it can currently happen that NIR doesn't remove the unreachable code */
5332 if (!nir_instr_is_last(&instr
->instr
)) {
5333 ctx
->program
->needs_exact
= true;
5334 /* save exec somewhere temporarily so that it doesn't get
5335 * overwritten before the discard from outer exec masks */
5336 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5337 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5338 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5342 /* This condition is incorrect for uniformly branched discards in a loop
5343 * predicated by a divergent condition, but the above code catches that case
5344 * and the discard would end up turning into a discard_if.
5354 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5355 /* program just ends here */
5356 ctx
->block
->kind
|= block_kind_uniform
;
5357 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5358 0 /* enabled mask */, 9 /* dest */,
5359 false /* compressed */, true/* done */, true /* valid mask */);
5360 bld
.sopp(aco_opcode::s_endpgm
);
5361 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5363 ctx
->block
->kind
|= block_kind_discard
;
5364 /* branch and linear edge is added by visit_if() */
5368 enum aco_descriptor_type
{
5379 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5380 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5382 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5383 return dim
== ac_image_cube
||
5384 dim
== ac_image_1darray
||
5385 dim
== ac_image_2darray
||
5386 dim
== ac_image_2darraymsaa
;
5389 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5390 enum aco_descriptor_type desc_type
,
5391 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5393 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5394 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5395 if (it != ctx->tex_desc.end())
5398 Temp index
= Temp();
5399 bool index_set
= false;
5400 unsigned constant_index
= 0;
5401 unsigned descriptor_set
;
5402 unsigned base_index
;
5403 Builder
bld(ctx
->program
, ctx
->block
);
5406 assert(tex_instr
&& !image
);
5408 base_index
= tex_instr
->sampler_index
;
5410 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5411 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5415 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5416 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5418 constant_index
+= array_size
* const_value
->u32
;
5420 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5421 if (indirect
.type() == RegType::vgpr
)
5422 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5424 if (array_size
!= 1)
5425 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5431 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5435 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5437 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5438 base_index
= deref_instr
->var
->data
.binding
;
5441 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5442 list
= convert_pointer_to_64_bit(ctx
, list
);
5444 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5445 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5446 unsigned offset
= binding
->offset
;
5447 unsigned stride
= binding
->size
;
5451 assert(base_index
< layout
->binding_count
);
5453 switch (desc_type
) {
5454 case ACO_DESC_IMAGE
:
5456 opcode
= aco_opcode::s_load_dwordx8
;
5458 case ACO_DESC_FMASK
:
5460 opcode
= aco_opcode::s_load_dwordx8
;
5463 case ACO_DESC_SAMPLER
:
5465 opcode
= aco_opcode::s_load_dwordx4
;
5466 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5467 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5469 case ACO_DESC_BUFFER
:
5471 opcode
= aco_opcode::s_load_dwordx4
;
5473 case ACO_DESC_PLANE_0
:
5474 case ACO_DESC_PLANE_1
:
5476 opcode
= aco_opcode::s_load_dwordx8
;
5477 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5479 case ACO_DESC_PLANE_2
:
5481 opcode
= aco_opcode::s_load_dwordx4
;
5485 unreachable("invalid desc_type\n");
5488 offset
+= constant_index
* stride
;
5490 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5491 (!index_set
|| binding
->immutable_samplers_equal
)) {
5492 if (binding
->immutable_samplers_equal
)
5495 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5496 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5497 Operand(samplers
[constant_index
* 4 + 0]),
5498 Operand(samplers
[constant_index
* 4 + 1]),
5499 Operand(samplers
[constant_index
* 4 + 2]),
5500 Operand(samplers
[constant_index
* 4 + 3]));
5505 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5507 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5508 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5511 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5513 if (desc_type
== ACO_DESC_PLANE_2
) {
5515 for (unsigned i
= 0; i
< 8; i
++)
5516 components
[i
] = bld
.tmp(s1
);
5517 bld
.pseudo(aco_opcode::p_split_vector
,
5518 Definition(components
[0]),
5519 Definition(components
[1]),
5520 Definition(components
[2]),
5521 Definition(components
[3]),
5524 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5525 bld
.pseudo(aco_opcode::p_split_vector
,
5526 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5527 Definition(components
[4]),
5528 Definition(components
[5]),
5529 Definition(components
[6]),
5530 Definition(components
[7]),
5533 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5534 components
[0], components
[1], components
[2], components
[3],
5535 components
[4], components
[5], components
[6], components
[7]);
5541 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5544 case GLSL_SAMPLER_DIM_BUF
:
5546 case GLSL_SAMPLER_DIM_1D
:
5547 return array
? 2 : 1;
5548 case GLSL_SAMPLER_DIM_2D
:
5549 return array
? 3 : 2;
5550 case GLSL_SAMPLER_DIM_MS
:
5551 return array
? 4 : 3;
5552 case GLSL_SAMPLER_DIM_3D
:
5553 case GLSL_SAMPLER_DIM_CUBE
:
5555 case GLSL_SAMPLER_DIM_RECT
:
5556 case GLSL_SAMPLER_DIM_SUBPASS
:
5558 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5567 /* Adjust the sample index according to FMASK.
5569 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5570 * which is the identity mapping. Each nibble says which physical sample
5571 * should be fetched to get that sample.
5573 * For example, 0x11111100 means there are only 2 samples stored and
5574 * the second sample covers 3/4 of the pixel. When reading samples 0
5575 * and 1, return physical sample 0 (determined by the first two 0s
5576 * in FMASK), otherwise return physical sample 1.
5578 * The sample index should be adjusted as follows:
5579 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5581 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5583 Builder
bld(ctx
->program
, ctx
->block
);
5584 Temp fmask
= bld
.tmp(v1
);
5585 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5586 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5589 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5590 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5591 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5592 load
->operands
[0] = Operand(fmask_desc_ptr
);
5593 load
->operands
[1] = Operand(s4
); /* no sampler */
5594 load
->operands
[2] = Operand(coord
);
5595 load
->definitions
[0] = Definition(fmask
);
5602 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5603 ctx
->block
->instructions
.emplace_back(std::move(load
));
5605 Operand sample_index4
;
5606 if (sample_index
.isConstant()) {
5607 if (sample_index
.constantValue() < 16) {
5608 sample_index4
= Operand(sample_index
.constantValue() << 2);
5610 sample_index4
= Operand(0u);
5612 } else if (sample_index
.regClass() == s1
) {
5613 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5615 assert(sample_index
.regClass() == v1
);
5616 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5620 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5621 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5622 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5623 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5625 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5627 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5628 * resource descriptor is 0 (invalid),
5630 Temp compare
= bld
.tmp(bld
.lm
);
5631 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5632 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5634 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5636 /* Replace the MSAA sample index. */
5637 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5640 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5643 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5644 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5645 bool is_array
= glsl_sampler_type_is_array(type
);
5646 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5647 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5648 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5649 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5650 int count
= image_type_to_components_count(dim
, is_array
);
5651 std::vector
<Temp
> coords(count
);
5652 Builder
bld(ctx
->program
, ctx
->block
);
5656 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5657 /* get sample index */
5658 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5659 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5660 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5661 std::vector
<Temp
> fmask_load_address
;
5662 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5663 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5665 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5666 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5668 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5673 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5674 coords
.resize(coords
.size() + 1);
5675 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5677 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5679 for (int i
= 0; i
< count
; i
++)
5680 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5683 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5684 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5685 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5686 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5689 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5692 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5693 for (unsigned i
= 0; i
< coords
.size(); i
++)
5694 vec
->operands
[i
] = Operand(coords
[i
]);
5695 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5696 vec
->definitions
[0] = Definition(res
);
5697 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5702 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5704 Builder
bld(ctx
->program
, ctx
->block
);
5705 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5706 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5707 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5708 bool is_array
= glsl_sampler_type_is_array(type
);
5709 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5711 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5712 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5713 unsigned num_channels
= util_last_bit(mask
);
5714 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5715 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5718 switch (num_channels
) {
5720 opcode
= aco_opcode::buffer_load_format_x
;
5723 opcode
= aco_opcode::buffer_load_format_xy
;
5726 opcode
= aco_opcode::buffer_load_format_xyz
;
5729 opcode
= aco_opcode::buffer_load_format_xyzw
;
5732 unreachable(">4 channel buffer image load");
5734 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5735 load
->operands
[0] = Operand(rsrc
);
5736 load
->operands
[1] = Operand(vindex
);
5737 load
->operands
[2] = Operand((uint32_t) 0);
5739 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5742 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5743 load
->definitions
[0] = Definition(tmp
);
5745 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5746 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5747 load
->barrier
= barrier_image
;
5748 ctx
->block
->instructions
.emplace_back(std::move(load
));
5750 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5754 Temp coords
= get_image_coords(ctx
, instr
, type
);
5755 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5757 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5758 unsigned num_components
= util_bitcount(dmask
);
5760 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5763 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5765 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5766 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5768 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5769 load
->operands
[0] = Operand(resource
);
5770 load
->operands
[1] = Operand(s4
); /* no sampler */
5771 load
->operands
[2] = Operand(coords
);
5772 load
->definitions
[0] = Definition(tmp
);
5773 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5774 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5775 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5776 load
->dmask
= dmask
;
5778 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5779 load
->barrier
= barrier_image
;
5780 ctx
->block
->instructions
.emplace_back(std::move(load
));
5782 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5786 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5788 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5789 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5790 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5791 bool is_array
= glsl_sampler_type_is_array(type
);
5792 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5794 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5796 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5797 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5798 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5800 switch (data
.size()) {
5802 opcode
= aco_opcode::buffer_store_format_x
;
5805 opcode
= aco_opcode::buffer_store_format_xy
;
5808 opcode
= aco_opcode::buffer_store_format_xyz
;
5811 opcode
= aco_opcode::buffer_store_format_xyzw
;
5814 unreachable(">4 channel buffer image store");
5816 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5817 store
->operands
[0] = Operand(rsrc
);
5818 store
->operands
[1] = Operand(vindex
);
5819 store
->operands
[2] = Operand((uint32_t) 0);
5820 store
->operands
[3] = Operand(data
);
5821 store
->idxen
= true;
5824 store
->disable_wqm
= true;
5825 store
->barrier
= barrier_image
;
5826 ctx
->program
->needs_exact
= true;
5827 ctx
->block
->instructions
.emplace_back(std::move(store
));
5831 assert(data
.type() == RegType::vgpr
);
5832 Temp coords
= get_image_coords(ctx
, instr
, type
);
5833 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5835 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5836 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5838 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5839 store
->operands
[0] = Operand(resource
);
5840 store
->operands
[1] = Operand(data
);
5841 store
->operands
[2] = Operand(coords
);
5844 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5845 store
->dmask
= (1 << data
.size()) - 1;
5847 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5848 store
->disable_wqm
= true;
5849 store
->barrier
= barrier_image
;
5850 ctx
->program
->needs_exact
= true;
5851 ctx
->block
->instructions
.emplace_back(std::move(store
));
5855 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5857 /* return the previous value if dest is ever used */
5858 bool return_previous
= false;
5859 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5860 return_previous
= true;
5863 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5864 return_previous
= true;
5868 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5869 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5870 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5871 bool is_array
= glsl_sampler_type_is_array(type
);
5872 Builder
bld(ctx
->program
, ctx
->block
);
5874 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5875 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5877 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5878 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5880 aco_opcode buf_op
, image_op
;
5881 switch (instr
->intrinsic
) {
5882 case nir_intrinsic_image_deref_atomic_add
:
5883 buf_op
= aco_opcode::buffer_atomic_add
;
5884 image_op
= aco_opcode::image_atomic_add
;
5886 case nir_intrinsic_image_deref_atomic_umin
:
5887 buf_op
= aco_opcode::buffer_atomic_umin
;
5888 image_op
= aco_opcode::image_atomic_umin
;
5890 case nir_intrinsic_image_deref_atomic_imin
:
5891 buf_op
= aco_opcode::buffer_atomic_smin
;
5892 image_op
= aco_opcode::image_atomic_smin
;
5894 case nir_intrinsic_image_deref_atomic_umax
:
5895 buf_op
= aco_opcode::buffer_atomic_umax
;
5896 image_op
= aco_opcode::image_atomic_umax
;
5898 case nir_intrinsic_image_deref_atomic_imax
:
5899 buf_op
= aco_opcode::buffer_atomic_smax
;
5900 image_op
= aco_opcode::image_atomic_smax
;
5902 case nir_intrinsic_image_deref_atomic_and
:
5903 buf_op
= aco_opcode::buffer_atomic_and
;
5904 image_op
= aco_opcode::image_atomic_and
;
5906 case nir_intrinsic_image_deref_atomic_or
:
5907 buf_op
= aco_opcode::buffer_atomic_or
;
5908 image_op
= aco_opcode::image_atomic_or
;
5910 case nir_intrinsic_image_deref_atomic_xor
:
5911 buf_op
= aco_opcode::buffer_atomic_xor
;
5912 image_op
= aco_opcode::image_atomic_xor
;
5914 case nir_intrinsic_image_deref_atomic_exchange
:
5915 buf_op
= aco_opcode::buffer_atomic_swap
;
5916 image_op
= aco_opcode::image_atomic_swap
;
5918 case nir_intrinsic_image_deref_atomic_comp_swap
:
5919 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5920 image_op
= aco_opcode::image_atomic_cmpswap
;
5923 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5926 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5928 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5929 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5930 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5931 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5932 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5933 mubuf
->operands
[0] = Operand(resource
);
5934 mubuf
->operands
[1] = Operand(vindex
);
5935 mubuf
->operands
[2] = Operand((uint32_t)0);
5936 mubuf
->operands
[3] = Operand(data
);
5937 if (return_previous
)
5938 mubuf
->definitions
[0] = Definition(dst
);
5940 mubuf
->idxen
= true;
5941 mubuf
->glc
= return_previous
;
5942 mubuf
->dlc
= false; /* Not needed for atomics */
5943 mubuf
->disable_wqm
= true;
5944 mubuf
->barrier
= barrier_image
;
5945 ctx
->program
->needs_exact
= true;
5946 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5950 Temp coords
= get_image_coords(ctx
, instr
, type
);
5951 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5952 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5953 mimg
->operands
[0] = Operand(resource
);
5954 mimg
->operands
[1] = Operand(data
);
5955 mimg
->operands
[2] = Operand(coords
);
5956 if (return_previous
)
5957 mimg
->definitions
[0] = Definition(dst
);
5958 mimg
->glc
= return_previous
;
5959 mimg
->dlc
= false; /* Not needed for atomics */
5960 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5961 mimg
->dmask
= (1 << data
.size()) - 1;
5963 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5964 mimg
->disable_wqm
= true;
5965 mimg
->barrier
= barrier_image
;
5966 ctx
->program
->needs_exact
= true;
5967 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5971 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5973 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5974 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5975 Builder
bld(ctx
->program
, ctx
->block
);
5977 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5979 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5980 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5982 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5983 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5985 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5986 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5988 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5989 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5990 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5991 if (dst
.type() == RegType::vgpr
)
5992 bld
.copy(Definition(dst
), shr_dst
);
5994 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5996 emit_extract_vector(ctx
, desc
, 2, dst
);
6000 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6002 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6003 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6004 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6005 bool is_array
= glsl_sampler_type_is_array(type
);
6006 Builder
bld(ctx
->program
, ctx
->block
);
6008 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6009 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6010 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6014 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6017 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6019 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6021 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6022 mimg
->operands
[0] = Operand(resource
);
6023 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6024 mimg
->operands
[2] = Operand(lod
);
6025 uint8_t& dmask
= mimg
->dmask
;
6026 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6027 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6028 mimg
->da
= glsl_sampler_type_is_array(type
);
6029 mimg
->can_reorder
= true;
6030 Definition
& def
= mimg
->definitions
[0];
6031 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6033 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6034 glsl_sampler_type_is_array(type
)) {
6036 assert(instr
->dest
.ssa
.num_components
== 3);
6037 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6038 def
= Definition(tmp
);
6039 emit_split_vector(ctx
, tmp
, 3);
6041 /* divide 3rd value by 6 by multiplying with magic number */
6042 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6043 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6045 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6046 emit_extract_vector(ctx
, tmp
, 0, v1
),
6047 emit_extract_vector(ctx
, tmp
, 1, v1
),
6050 } else if (ctx
->options
->chip_class
== GFX9
&&
6051 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6052 glsl_sampler_type_is_array(type
)) {
6053 assert(instr
->dest
.ssa
.num_components
== 2);
6054 def
= Definition(dst
);
6057 def
= Definition(dst
);
6060 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6063 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6065 Builder
bld(ctx
->program
, ctx
->block
);
6066 unsigned num_components
= instr
->num_components
;
6068 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6069 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6070 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6072 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6073 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6074 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6075 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6078 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6080 Builder
bld(ctx
->program
, ctx
->block
);
6081 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6082 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6083 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6084 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6086 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6087 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6089 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6090 ctx
->options
->chip_class
>= GFX8
&&
6091 elem_size_bytes
>= 4;
6093 offset
= bld
.as_uniform(offset
);
6094 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6096 unsigned write_count
= 0;
6097 Temp write_datas
[32];
6098 unsigned offsets
[32];
6099 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6100 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6102 for (unsigned i
= 0; i
< write_count
; i
++) {
6103 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6104 if (smem
&& ctx
->stage
== fragment_fs
)
6105 op
= aco_opcode::p_fs_buffer_store_smem
;
6108 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6109 store
->operands
[0] = Operand(rsrc
);
6111 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6112 offset
, Operand(offsets
[i
]));
6113 store
->operands
[1] = Operand(off
);
6115 store
->operands
[1] = Operand(offset
);
6117 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6118 store
->operands
[1].setFixed(m0
);
6119 store
->operands
[2] = Operand(write_datas
[i
]);
6120 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6122 store
->disable_wqm
= true;
6123 store
->barrier
= barrier_buffer
;
6124 ctx
->block
->instructions
.emplace_back(std::move(store
));
6125 ctx
->program
->wb_smem_l1_on_end
= true;
6126 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6127 ctx
->block
->kind
|= block_kind_needs_lowering
;
6128 ctx
->program
->needs_exact
= true;
6131 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6132 store
->operands
[0] = Operand(rsrc
);
6133 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6134 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6135 store
->operands
[3] = Operand(write_datas
[i
]);
6136 store
->offset
= offsets
[i
];
6137 store
->offen
= (offset
.type() == RegType::vgpr
);
6138 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6140 store
->disable_wqm
= true;
6141 store
->barrier
= barrier_buffer
;
6142 ctx
->program
->needs_exact
= true;
6143 ctx
->block
->instructions
.emplace_back(std::move(store
));
6148 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6150 /* return the previous value if dest is ever used */
6151 bool return_previous
= false;
6152 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6153 return_previous
= true;
6156 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6157 return_previous
= true;
6161 Builder
bld(ctx
->program
, ctx
->block
);
6162 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6164 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6165 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6166 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6168 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6169 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6170 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6172 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6174 aco_opcode op32
, op64
;
6175 switch (instr
->intrinsic
) {
6176 case nir_intrinsic_ssbo_atomic_add
:
6177 op32
= aco_opcode::buffer_atomic_add
;
6178 op64
= aco_opcode::buffer_atomic_add_x2
;
6180 case nir_intrinsic_ssbo_atomic_imin
:
6181 op32
= aco_opcode::buffer_atomic_smin
;
6182 op64
= aco_opcode::buffer_atomic_smin_x2
;
6184 case nir_intrinsic_ssbo_atomic_umin
:
6185 op32
= aco_opcode::buffer_atomic_umin
;
6186 op64
= aco_opcode::buffer_atomic_umin_x2
;
6188 case nir_intrinsic_ssbo_atomic_imax
:
6189 op32
= aco_opcode::buffer_atomic_smax
;
6190 op64
= aco_opcode::buffer_atomic_smax_x2
;
6192 case nir_intrinsic_ssbo_atomic_umax
:
6193 op32
= aco_opcode::buffer_atomic_umax
;
6194 op64
= aco_opcode::buffer_atomic_umax_x2
;
6196 case nir_intrinsic_ssbo_atomic_and
:
6197 op32
= aco_opcode::buffer_atomic_and
;
6198 op64
= aco_opcode::buffer_atomic_and_x2
;
6200 case nir_intrinsic_ssbo_atomic_or
:
6201 op32
= aco_opcode::buffer_atomic_or
;
6202 op64
= aco_opcode::buffer_atomic_or_x2
;
6204 case nir_intrinsic_ssbo_atomic_xor
:
6205 op32
= aco_opcode::buffer_atomic_xor
;
6206 op64
= aco_opcode::buffer_atomic_xor_x2
;
6208 case nir_intrinsic_ssbo_atomic_exchange
:
6209 op32
= aco_opcode::buffer_atomic_swap
;
6210 op64
= aco_opcode::buffer_atomic_swap_x2
;
6212 case nir_intrinsic_ssbo_atomic_comp_swap
:
6213 op32
= aco_opcode::buffer_atomic_cmpswap
;
6214 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6217 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6219 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6220 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6221 mubuf
->operands
[0] = Operand(rsrc
);
6222 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6223 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6224 mubuf
->operands
[3] = Operand(data
);
6225 if (return_previous
)
6226 mubuf
->definitions
[0] = Definition(dst
);
6228 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6229 mubuf
->glc
= return_previous
;
6230 mubuf
->dlc
= false; /* Not needed for atomics */
6231 mubuf
->disable_wqm
= true;
6232 mubuf
->barrier
= barrier_buffer
;
6233 ctx
->program
->needs_exact
= true;
6234 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6237 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6239 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6240 Builder
bld(ctx
->program
, ctx
->block
);
6241 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6242 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6245 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6247 Builder
bld(ctx
->program
, ctx
->block
);
6248 unsigned num_components
= instr
->num_components
;
6249 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6251 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6252 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6253 num_components
, component_size
};
6254 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6255 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6256 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6257 info
.barrier
= barrier_buffer
;
6258 info
.can_reorder
= false;
6259 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6260 * it's safe to use SMEM */
6261 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6262 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6263 emit_global_load(ctx
, bld
, &info
);
6265 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6266 emit_smem_load(ctx
, bld
, &info
);
6270 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6272 Builder
bld(ctx
->program
, ctx
->block
);
6273 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6274 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6276 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6277 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6278 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6280 if (ctx
->options
->chip_class
>= GFX7
)
6281 addr
= as_vgpr(ctx
, addr
);
6283 unsigned write_count
= 0;
6284 Temp write_datas
[32];
6285 unsigned offsets
[32];
6286 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6287 16, &write_count
, write_datas
, offsets
);
6289 for (unsigned i
= 0; i
< write_count
; i
++) {
6290 if (ctx
->options
->chip_class
>= GFX7
) {
6291 unsigned offset
= offsets
[i
];
6292 Temp store_addr
= addr
;
6293 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6294 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6295 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6296 Temp carry
= bld
.tmp(bld
.lm
);
6297 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6299 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6300 Operand(offset
), addr0
);
6301 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6303 carry
).def(1).setHint(vcc
);
6305 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6310 bool global
= ctx
->options
->chip_class
>= GFX9
;
6312 switch (write_datas
[i
].bytes()) {
6314 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6317 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6320 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6323 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6326 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6329 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6332 unreachable("store_global not implemented for this size.");
6335 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6336 flat
->operands
[0] = Operand(store_addr
);
6337 flat
->operands
[1] = Operand(s1
);
6338 flat
->operands
[2] = Operand(write_datas
[i
]);
6341 flat
->offset
= offset
;
6342 flat
->disable_wqm
= true;
6343 flat
->barrier
= barrier_buffer
;
6344 ctx
->program
->needs_exact
= true;
6345 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6347 assert(ctx
->options
->chip_class
== GFX6
);
6349 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6351 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6353 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6354 mubuf
->operands
[0] = Operand(rsrc
);
6355 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6356 mubuf
->operands
[2] = Operand(0u);
6357 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6360 mubuf
->offset
= offsets
[i
];
6361 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6362 mubuf
->disable_wqm
= true;
6363 mubuf
->barrier
= barrier_buffer
;
6364 ctx
->program
->needs_exact
= true;
6365 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6370 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6372 /* return the previous value if dest is ever used */
6373 bool return_previous
= false;
6374 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6375 return_previous
= true;
6378 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6379 return_previous
= true;
6383 Builder
bld(ctx
->program
, ctx
->block
);
6384 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6385 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6387 if (ctx
->options
->chip_class
>= GFX7
)
6388 addr
= as_vgpr(ctx
, addr
);
6390 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6391 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6392 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6394 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6396 aco_opcode op32
, op64
;
6398 if (ctx
->options
->chip_class
>= GFX7
) {
6399 bool global
= ctx
->options
->chip_class
>= GFX9
;
6400 switch (instr
->intrinsic
) {
6401 case nir_intrinsic_global_atomic_add
:
6402 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6403 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6405 case nir_intrinsic_global_atomic_imin
:
6406 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6407 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6409 case nir_intrinsic_global_atomic_umin
:
6410 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6411 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6413 case nir_intrinsic_global_atomic_imax
:
6414 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6415 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6417 case nir_intrinsic_global_atomic_umax
:
6418 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6419 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6421 case nir_intrinsic_global_atomic_and
:
6422 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6423 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6425 case nir_intrinsic_global_atomic_or
:
6426 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6427 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6429 case nir_intrinsic_global_atomic_xor
:
6430 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6431 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6433 case nir_intrinsic_global_atomic_exchange
:
6434 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6435 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6437 case nir_intrinsic_global_atomic_comp_swap
:
6438 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6439 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6442 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6445 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6446 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6447 flat
->operands
[0] = Operand(addr
);
6448 flat
->operands
[1] = Operand(s1
);
6449 flat
->operands
[2] = Operand(data
);
6450 if (return_previous
)
6451 flat
->definitions
[0] = Definition(dst
);
6452 flat
->glc
= return_previous
;
6453 flat
->dlc
= false; /* Not needed for atomics */
6455 flat
->disable_wqm
= true;
6456 flat
->barrier
= barrier_buffer
;
6457 ctx
->program
->needs_exact
= true;
6458 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6460 assert(ctx
->options
->chip_class
== GFX6
);
6462 switch (instr
->intrinsic
) {
6463 case nir_intrinsic_global_atomic_add
:
6464 op32
= aco_opcode::buffer_atomic_add
;
6465 op64
= aco_opcode::buffer_atomic_add_x2
;
6467 case nir_intrinsic_global_atomic_imin
:
6468 op32
= aco_opcode::buffer_atomic_smin
;
6469 op64
= aco_opcode::buffer_atomic_smin_x2
;
6471 case nir_intrinsic_global_atomic_umin
:
6472 op32
= aco_opcode::buffer_atomic_umin
;
6473 op64
= aco_opcode::buffer_atomic_umin_x2
;
6475 case nir_intrinsic_global_atomic_imax
:
6476 op32
= aco_opcode::buffer_atomic_smax
;
6477 op64
= aco_opcode::buffer_atomic_smax_x2
;
6479 case nir_intrinsic_global_atomic_umax
:
6480 op32
= aco_opcode::buffer_atomic_umax
;
6481 op64
= aco_opcode::buffer_atomic_umax_x2
;
6483 case nir_intrinsic_global_atomic_and
:
6484 op32
= aco_opcode::buffer_atomic_and
;
6485 op64
= aco_opcode::buffer_atomic_and_x2
;
6487 case nir_intrinsic_global_atomic_or
:
6488 op32
= aco_opcode::buffer_atomic_or
;
6489 op64
= aco_opcode::buffer_atomic_or_x2
;
6491 case nir_intrinsic_global_atomic_xor
:
6492 op32
= aco_opcode::buffer_atomic_xor
;
6493 op64
= aco_opcode::buffer_atomic_xor_x2
;
6495 case nir_intrinsic_global_atomic_exchange
:
6496 op32
= aco_opcode::buffer_atomic_swap
;
6497 op64
= aco_opcode::buffer_atomic_swap_x2
;
6499 case nir_intrinsic_global_atomic_comp_swap
:
6500 op32
= aco_opcode::buffer_atomic_cmpswap
;
6501 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6504 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6507 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6509 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6511 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6512 mubuf
->operands
[0] = Operand(rsrc
);
6513 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6514 mubuf
->operands
[2] = Operand(0u);
6515 mubuf
->operands
[3] = Operand(data
);
6516 if (return_previous
)
6517 mubuf
->definitions
[0] = Definition(dst
);
6518 mubuf
->glc
= return_previous
;
6521 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6522 mubuf
->disable_wqm
= true;
6523 mubuf
->barrier
= barrier_buffer
;
6524 ctx
->program
->needs_exact
= true;
6525 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6529 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6530 Builder
bld(ctx
->program
, ctx
->block
);
6531 switch(instr
->intrinsic
) {
6532 case nir_intrinsic_group_memory_barrier
:
6533 case nir_intrinsic_memory_barrier
:
6534 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6536 case nir_intrinsic_memory_barrier_buffer
:
6537 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6539 case nir_intrinsic_memory_barrier_image
:
6540 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6542 case nir_intrinsic_memory_barrier_tcs_patch
:
6543 case nir_intrinsic_memory_barrier_shared
:
6544 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6547 unreachable("Unimplemented memory barrier intrinsic");
6552 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6554 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6555 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6556 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6557 Builder
bld(ctx
->program
, ctx
->block
);
6559 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6560 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6561 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6564 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6566 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6567 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6568 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6569 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6571 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6572 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6575 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6577 unsigned offset
= nir_intrinsic_base(instr
);
6578 Builder
bld(ctx
->program
, ctx
->block
);
6579 Operand m
= load_lds_size_m0(bld
);
6580 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6581 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6583 unsigned num_operands
= 3;
6584 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6585 switch(instr
->intrinsic
) {
6586 case nir_intrinsic_shared_atomic_add
:
6587 op32
= aco_opcode::ds_add_u32
;
6588 op64
= aco_opcode::ds_add_u64
;
6589 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6590 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6592 case nir_intrinsic_shared_atomic_imin
:
6593 op32
= aco_opcode::ds_min_i32
;
6594 op64
= aco_opcode::ds_min_i64
;
6595 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6596 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6598 case nir_intrinsic_shared_atomic_umin
:
6599 op32
= aco_opcode::ds_min_u32
;
6600 op64
= aco_opcode::ds_min_u64
;
6601 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6602 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6604 case nir_intrinsic_shared_atomic_imax
:
6605 op32
= aco_opcode::ds_max_i32
;
6606 op64
= aco_opcode::ds_max_i64
;
6607 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6608 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6610 case nir_intrinsic_shared_atomic_umax
:
6611 op32
= aco_opcode::ds_max_u32
;
6612 op64
= aco_opcode::ds_max_u64
;
6613 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6614 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6616 case nir_intrinsic_shared_atomic_and
:
6617 op32
= aco_opcode::ds_and_b32
;
6618 op64
= aco_opcode::ds_and_b64
;
6619 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6620 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6622 case nir_intrinsic_shared_atomic_or
:
6623 op32
= aco_opcode::ds_or_b32
;
6624 op64
= aco_opcode::ds_or_b64
;
6625 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6626 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6628 case nir_intrinsic_shared_atomic_xor
:
6629 op32
= aco_opcode::ds_xor_b32
;
6630 op64
= aco_opcode::ds_xor_b64
;
6631 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6632 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6634 case nir_intrinsic_shared_atomic_exchange
:
6635 op32
= aco_opcode::ds_write_b32
;
6636 op64
= aco_opcode::ds_write_b64
;
6637 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6638 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6640 case nir_intrinsic_shared_atomic_comp_swap
:
6641 op32
= aco_opcode::ds_cmpst_b32
;
6642 op64
= aco_opcode::ds_cmpst_b64
;
6643 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6644 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6648 unreachable("Unhandled shared atomic intrinsic");
6651 /* return the previous value if dest is ever used */
6652 bool return_previous
= false;
6653 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6654 return_previous
= true;
6657 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6658 return_previous
= true;
6663 if (data
.size() == 1) {
6664 assert(instr
->dest
.ssa
.bit_size
== 32);
6665 op
= return_previous
? op32_rtn
: op32
;
6667 assert(instr
->dest
.ssa
.bit_size
== 64);
6668 op
= return_previous
? op64_rtn
: op64
;
6671 if (offset
> 65535) {
6672 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6676 aco_ptr
<DS_instruction
> ds
;
6677 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6678 ds
->operands
[0] = Operand(address
);
6679 ds
->operands
[1] = Operand(data
);
6680 if (num_operands
== 4)
6681 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6682 ds
->operands
[num_operands
- 1] = m
;
6683 ds
->offset0
= offset
;
6684 if (return_previous
)
6685 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6686 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6689 Temp
get_scratch_resource(isel_context
*ctx
)
6691 Builder
bld(ctx
->program
, ctx
->block
);
6692 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6693 if (ctx
->stage
!= compute_cs
)
6694 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6696 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6697 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6699 if (ctx
->program
->chip_class
>= GFX10
) {
6700 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6701 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6702 S_008F0C_RESOURCE_LEVEL(1);
6703 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6704 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6705 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6708 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6709 if (ctx
->program
->chip_class
<= GFX8
)
6710 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6712 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6715 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6716 Builder
bld(ctx
->program
, ctx
->block
);
6717 Temp rsrc
= get_scratch_resource(ctx
);
6718 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6719 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6721 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6722 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6723 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6724 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6725 info
.swizzle_component_size
= 16;
6726 info
.can_reorder
= false;
6727 info
.soffset
= ctx
->program
->scratch_offset
;
6728 emit_mubuf_load(ctx
, bld
, &info
);
6731 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6732 Builder
bld(ctx
->program
, ctx
->block
);
6733 Temp rsrc
= get_scratch_resource(ctx
);
6734 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6735 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6737 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6738 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6740 unsigned write_count
= 0;
6741 Temp write_datas
[32];
6742 unsigned offsets
[32];
6743 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6744 16, &write_count
, write_datas
, offsets
);
6746 for (unsigned i
= 0; i
< write_count
; i
++) {
6747 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6748 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6752 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6753 uint8_t log2_ps_iter_samples
;
6754 if (ctx
->program
->info
->ps
.force_persample
) {
6755 log2_ps_iter_samples
=
6756 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6758 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6761 /* The bit pattern matches that used by fixed function fragment
6763 static const unsigned ps_iter_masks
[] = {
6764 0xffff, /* not used */
6770 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6772 Builder
bld(ctx
->program
, ctx
->block
);
6774 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6775 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6776 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6777 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6778 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6779 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6782 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6783 Builder
bld(ctx
->program
, ctx
->block
);
6785 unsigned stream
= nir_intrinsic_stream_id(instr
);
6786 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6787 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6788 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6791 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6793 unsigned num_components
=
6794 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6795 assert(num_components
);
6797 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6798 unsigned stream_offset
= 0;
6799 for (unsigned i
= 0; i
< stream
; i
++) {
6800 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6801 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6804 /* Limit on the stride field for <= GFX7. */
6805 assert(stride
< (1 << 14));
6807 Temp gsvs_dwords
[4];
6808 for (unsigned i
= 0; i
< 4; i
++)
6809 gsvs_dwords
[i
] = bld
.tmp(s1
);
6810 bld
.pseudo(aco_opcode::p_split_vector
,
6811 Definition(gsvs_dwords
[0]),
6812 Definition(gsvs_dwords
[1]),
6813 Definition(gsvs_dwords
[2]),
6814 Definition(gsvs_dwords
[3]),
6817 if (stream_offset
) {
6818 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6820 Temp carry
= bld
.tmp(s1
);
6821 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6822 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6825 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6826 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6828 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6829 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6831 unsigned offset
= 0;
6832 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6833 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6836 for (unsigned j
= 0; j
< 4; j
++) {
6837 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6840 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6841 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6842 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6843 if (const_offset
>= 4096u) {
6844 if (vaddr_offset
.isUndefined())
6845 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6847 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6848 const_offset
%= 4096u;
6851 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6852 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6853 mtbuf
->operands
[1] = vaddr_offset
;
6854 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6855 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6856 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6857 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6858 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6859 mtbuf
->offset
= const_offset
;
6862 mtbuf
->barrier
= barrier_gs_data
;
6863 mtbuf
->can_reorder
= true;
6864 bld
.insert(std::move(mtbuf
));
6867 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6870 /* outputs for the next vertex are undefined and keeping them around can
6871 * create invalid IR with control flow */
6872 ctx
->outputs
.mask
[i
] = 0;
6875 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6878 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6880 Builder
bld(ctx
->program
, ctx
->block
);
6882 if (cluster_size
== 1) {
6884 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6885 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6886 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6887 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6888 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6889 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6890 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6891 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6892 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6893 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6894 //subgroupAnd(val) -> (exec & ~val) == 0
6895 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6896 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6897 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6898 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6899 //subgroupOr(val) -> (val & exec) != 0
6900 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6901 return bool_to_vector_condition(ctx
, tmp
);
6902 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6903 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6904 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6905 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6906 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6907 return bool_to_vector_condition(ctx
, tmp
);
6909 //subgroupClustered{And,Or,Xor}(val, n) ->
6910 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6911 //cluster_offset = ~(n - 1) & lane_id
6912 //cluster_mask = ((1 << n) - 1)
6913 //subgroupClusteredAnd():
6914 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6915 //subgroupClusteredOr():
6916 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6917 //subgroupClusteredXor():
6918 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6919 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6920 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6923 if (op
== nir_op_iand
)
6924 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6926 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6928 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6930 if (ctx
->program
->chip_class
<= GFX7
)
6931 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6932 else if (ctx
->program
->wave_size
== 64)
6933 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6935 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6936 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6937 if (cluster_mask
!= 0xffffffff)
6938 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6940 Definition cmp_def
= Definition();
6941 if (op
== nir_op_iand
) {
6942 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6943 } else if (op
== nir_op_ior
) {
6944 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6945 } else if (op
== nir_op_ixor
) {
6946 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6947 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6948 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6950 cmp_def
.setHint(vcc
);
6951 return cmp_def
.getTemp();
6955 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6957 Builder
bld(ctx
->program
, ctx
->block
);
6959 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6960 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6961 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6963 if (op
== nir_op_iand
)
6964 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6966 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6968 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6969 Temp lo
= lohi
.def(0).getTemp();
6970 Temp hi
= lohi
.def(1).getTemp();
6971 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6973 Definition cmp_def
= Definition();
6974 if (op
== nir_op_iand
)
6975 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6976 else if (op
== nir_op_ior
)
6977 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6978 else if (op
== nir_op_ixor
)
6979 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6980 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6981 cmp_def
.setHint(vcc
);
6982 return cmp_def
.getTemp();
6985 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6987 Builder
bld(ctx
->program
, ctx
->block
);
6989 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6990 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6991 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6992 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6993 if (op
== nir_op_iand
)
6994 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6995 else if (op
== nir_op_ior
)
6996 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6997 else if (op
== nir_op_ixor
)
6998 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7004 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7006 Builder
bld(ctx
->program
, ctx
->block
);
7007 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7008 if (src
.regClass().type() == RegType::vgpr
) {
7009 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7010 } else if (src
.regClass() == s1
) {
7011 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7012 } else if (src
.regClass() == s2
) {
7013 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7015 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7016 nir_print_instr(&instr
->instr
, stderr
);
7017 fprintf(stderr
, "\n");
7021 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7023 Builder
bld(ctx
->program
, ctx
->block
);
7024 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7025 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7026 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7028 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7029 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7030 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7031 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7034 if (ctx
->program
->chip_class
>= GFX8
) {
7035 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7036 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7037 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7038 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7039 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7040 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7042 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7043 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7044 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7045 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7046 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7047 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7048 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7049 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7050 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7051 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7054 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7055 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7056 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7057 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7058 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7059 Temp wqm1
= bld
.tmp(v1
);
7060 emit_wqm(ctx
, tmp1
, wqm1
, true);
7061 Temp wqm2
= bld
.tmp(v1
);
7062 emit_wqm(ctx
, tmp2
, wqm2
, true);
7063 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7067 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7069 Builder
bld(ctx
->program
, ctx
->block
);
7070 switch(instr
->intrinsic
) {
7071 case nir_intrinsic_load_barycentric_sample
:
7072 case nir_intrinsic_load_barycentric_pixel
:
7073 case nir_intrinsic_load_barycentric_centroid
: {
7074 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7075 Temp bary
= Temp(0, s2
);
7077 case INTERP_MODE_SMOOTH
:
7078 case INTERP_MODE_NONE
:
7079 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7080 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7081 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7082 bary
= ctx
->persp_centroid
;
7083 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7084 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7086 case INTERP_MODE_NOPERSPECTIVE
:
7087 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7088 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7089 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7090 bary
= ctx
->linear_centroid
;
7091 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7092 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7097 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7098 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7099 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7100 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7101 Operand(p1
), Operand(p2
));
7102 emit_split_vector(ctx
, dst
, 2);
7105 case nir_intrinsic_load_barycentric_model
: {
7106 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7108 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7109 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7110 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7111 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7112 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7113 Operand(p1
), Operand(p2
), Operand(p3
));
7114 emit_split_vector(ctx
, dst
, 3);
7117 case nir_intrinsic_load_barycentric_at_sample
: {
7118 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7119 switch (ctx
->options
->key
.fs
.num_samples
) {
7120 case 2: sample_pos_offset
+= 1 << 3; break;
7121 case 4: sample_pos_offset
+= 3 << 3; break;
7122 case 8: sample_pos_offset
+= 7 << 3; break;
7126 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7127 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7128 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7129 if (addr
.type() == RegType::sgpr
) {
7132 sample_pos_offset
+= const_addr
->u32
<< 3;
7133 offset
= Operand(sample_pos_offset
);
7134 } else if (ctx
->options
->chip_class
>= GFX9
) {
7135 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7137 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7138 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7141 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7142 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7144 } else if (ctx
->options
->chip_class
>= GFX9
) {
7145 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7146 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7147 } else if (ctx
->options
->chip_class
>= GFX7
) {
7148 /* addr += private_segment_buffer + sample_pos_offset */
7149 Temp tmp0
= bld
.tmp(s1
);
7150 Temp tmp1
= bld
.tmp(s1
);
7151 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7152 Definition scc_tmp
= bld
.def(s1
, scc
);
7153 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7154 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7155 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7156 Temp pck0
= bld
.tmp(v1
);
7157 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7158 tmp1
= as_vgpr(ctx
, tmp1
);
7159 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7160 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7162 /* sample_pos = flat_load_dwordx2 addr */
7163 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7165 assert(ctx
->options
->chip_class
== GFX6
);
7167 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7168 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7169 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7171 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7172 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7174 sample_pos
= bld
.tmp(v2
);
7176 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7177 load
->definitions
[0] = Definition(sample_pos
);
7178 load
->operands
[0] = Operand(rsrc
);
7179 load
->operands
[1] = Operand(addr
);
7180 load
->operands
[2] = Operand(0u);
7181 load
->offset
= sample_pos_offset
;
7183 load
->addr64
= true;
7186 load
->disable_wqm
= false;
7187 load
->barrier
= barrier_none
;
7188 load
->can_reorder
= true;
7189 ctx
->block
->instructions
.emplace_back(std::move(load
));
7192 /* sample_pos -= 0.5 */
7193 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7194 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7195 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7196 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7197 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7199 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7202 case nir_intrinsic_load_barycentric_at_offset
: {
7203 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7204 RegClass rc
= RegClass(offset
.type(), 1);
7205 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7206 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7207 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7210 case nir_intrinsic_load_front_face
: {
7211 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7212 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7215 case nir_intrinsic_load_view_index
: {
7216 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7217 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7218 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7224 case nir_intrinsic_load_layer_id
: {
7225 unsigned idx
= nir_intrinsic_base(instr
);
7226 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7227 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7230 case nir_intrinsic_load_frag_coord
: {
7231 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7234 case nir_intrinsic_load_sample_pos
: {
7235 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7236 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7237 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7238 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7239 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7242 case nir_intrinsic_load_tess_coord
:
7243 visit_load_tess_coord(ctx
, instr
);
7245 case nir_intrinsic_load_interpolated_input
:
7246 visit_load_interpolated_input(ctx
, instr
);
7248 case nir_intrinsic_store_output
:
7249 visit_store_output(ctx
, instr
);
7251 case nir_intrinsic_load_input
:
7252 case nir_intrinsic_load_input_vertex
:
7253 visit_load_input(ctx
, instr
);
7255 case nir_intrinsic_load_output
:
7256 visit_load_output(ctx
, instr
);
7258 case nir_intrinsic_load_per_vertex_input
:
7259 visit_load_per_vertex_input(ctx
, instr
);
7261 case nir_intrinsic_load_per_vertex_output
:
7262 visit_load_per_vertex_output(ctx
, instr
);
7264 case nir_intrinsic_store_per_vertex_output
:
7265 visit_store_per_vertex_output(ctx
, instr
);
7267 case nir_intrinsic_load_ubo
:
7268 visit_load_ubo(ctx
, instr
);
7270 case nir_intrinsic_load_push_constant
:
7271 visit_load_push_constant(ctx
, instr
);
7273 case nir_intrinsic_load_constant
:
7274 visit_load_constant(ctx
, instr
);
7276 case nir_intrinsic_vulkan_resource_index
:
7277 visit_load_resource(ctx
, instr
);
7279 case nir_intrinsic_discard
:
7280 visit_discard(ctx
, instr
);
7282 case nir_intrinsic_discard_if
:
7283 visit_discard_if(ctx
, instr
);
7285 case nir_intrinsic_load_shared
:
7286 visit_load_shared(ctx
, instr
);
7288 case nir_intrinsic_store_shared
:
7289 visit_store_shared(ctx
, instr
);
7291 case nir_intrinsic_shared_atomic_add
:
7292 case nir_intrinsic_shared_atomic_imin
:
7293 case nir_intrinsic_shared_atomic_umin
:
7294 case nir_intrinsic_shared_atomic_imax
:
7295 case nir_intrinsic_shared_atomic_umax
:
7296 case nir_intrinsic_shared_atomic_and
:
7297 case nir_intrinsic_shared_atomic_or
:
7298 case nir_intrinsic_shared_atomic_xor
:
7299 case nir_intrinsic_shared_atomic_exchange
:
7300 case nir_intrinsic_shared_atomic_comp_swap
:
7301 visit_shared_atomic(ctx
, instr
);
7303 case nir_intrinsic_image_deref_load
:
7304 visit_image_load(ctx
, instr
);
7306 case nir_intrinsic_image_deref_store
:
7307 visit_image_store(ctx
, instr
);
7309 case nir_intrinsic_image_deref_atomic_add
:
7310 case nir_intrinsic_image_deref_atomic_umin
:
7311 case nir_intrinsic_image_deref_atomic_imin
:
7312 case nir_intrinsic_image_deref_atomic_umax
:
7313 case nir_intrinsic_image_deref_atomic_imax
:
7314 case nir_intrinsic_image_deref_atomic_and
:
7315 case nir_intrinsic_image_deref_atomic_or
:
7316 case nir_intrinsic_image_deref_atomic_xor
:
7317 case nir_intrinsic_image_deref_atomic_exchange
:
7318 case nir_intrinsic_image_deref_atomic_comp_swap
:
7319 visit_image_atomic(ctx
, instr
);
7321 case nir_intrinsic_image_deref_size
:
7322 visit_image_size(ctx
, instr
);
7324 case nir_intrinsic_load_ssbo
:
7325 visit_load_ssbo(ctx
, instr
);
7327 case nir_intrinsic_store_ssbo
:
7328 visit_store_ssbo(ctx
, instr
);
7330 case nir_intrinsic_load_global
:
7331 visit_load_global(ctx
, instr
);
7333 case nir_intrinsic_store_global
:
7334 visit_store_global(ctx
, instr
);
7336 case nir_intrinsic_global_atomic_add
:
7337 case nir_intrinsic_global_atomic_imin
:
7338 case nir_intrinsic_global_atomic_umin
:
7339 case nir_intrinsic_global_atomic_imax
:
7340 case nir_intrinsic_global_atomic_umax
:
7341 case nir_intrinsic_global_atomic_and
:
7342 case nir_intrinsic_global_atomic_or
:
7343 case nir_intrinsic_global_atomic_xor
:
7344 case nir_intrinsic_global_atomic_exchange
:
7345 case nir_intrinsic_global_atomic_comp_swap
:
7346 visit_global_atomic(ctx
, instr
);
7348 case nir_intrinsic_ssbo_atomic_add
:
7349 case nir_intrinsic_ssbo_atomic_imin
:
7350 case nir_intrinsic_ssbo_atomic_umin
:
7351 case nir_intrinsic_ssbo_atomic_imax
:
7352 case nir_intrinsic_ssbo_atomic_umax
:
7353 case nir_intrinsic_ssbo_atomic_and
:
7354 case nir_intrinsic_ssbo_atomic_or
:
7355 case nir_intrinsic_ssbo_atomic_xor
:
7356 case nir_intrinsic_ssbo_atomic_exchange
:
7357 case nir_intrinsic_ssbo_atomic_comp_swap
:
7358 visit_atomic_ssbo(ctx
, instr
);
7360 case nir_intrinsic_load_scratch
:
7361 visit_load_scratch(ctx
, instr
);
7363 case nir_intrinsic_store_scratch
:
7364 visit_store_scratch(ctx
, instr
);
7366 case nir_intrinsic_get_buffer_size
:
7367 visit_get_buffer_size(ctx
, instr
);
7369 case nir_intrinsic_control_barrier
: {
7370 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7371 /* GFX6 only (thanks to a hw bug workaround):
7372 * The real barrier instruction isn’t needed, because an entire patch
7373 * always fits into a single wave.
7378 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7379 bld
.sopp(aco_opcode::s_barrier
);
7383 case nir_intrinsic_memory_barrier_tcs_patch
:
7384 case nir_intrinsic_group_memory_barrier
:
7385 case nir_intrinsic_memory_barrier
:
7386 case nir_intrinsic_memory_barrier_buffer
:
7387 case nir_intrinsic_memory_barrier_image
:
7388 case nir_intrinsic_memory_barrier_shared
:
7389 emit_memory_barrier(ctx
, instr
);
7391 case nir_intrinsic_load_num_work_groups
: {
7392 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7393 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7394 emit_split_vector(ctx
, dst
, 3);
7397 case nir_intrinsic_load_local_invocation_id
: {
7398 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7399 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7400 emit_split_vector(ctx
, dst
, 3);
7403 case nir_intrinsic_load_work_group_id
: {
7404 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7405 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7406 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7407 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7408 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7409 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7410 emit_split_vector(ctx
, dst
, 3);
7413 case nir_intrinsic_load_local_invocation_index
: {
7414 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7416 /* The tg_size bits [6:11] contain the subgroup id,
7417 * we need this multiplied by the wave size, and then OR the thread id to it.
7419 if (ctx
->program
->wave_size
== 64) {
7420 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7421 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7422 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7423 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7425 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7426 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7427 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7428 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7432 case nir_intrinsic_load_subgroup_id
: {
7433 if (ctx
->stage
== compute_cs
) {
7434 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7435 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7437 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7441 case nir_intrinsic_load_subgroup_invocation
: {
7442 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7445 case nir_intrinsic_load_num_subgroups
: {
7446 if (ctx
->stage
== compute_cs
)
7447 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7448 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7450 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7453 case nir_intrinsic_ballot
: {
7454 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7455 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7456 Definition tmp
= bld
.def(dst
.regClass());
7457 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7458 if (instr
->src
[0].ssa
->bit_size
== 1) {
7459 assert(src
.regClass() == bld
.lm
);
7460 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7461 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7462 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7463 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7464 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7467 nir_print_instr(&instr
->instr
, stderr
);
7468 fprintf(stderr
, "\n");
7470 if (dst
.size() != bld
.lm
.size()) {
7471 /* Wave32 with ballot size set to 64 */
7472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7474 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7477 case nir_intrinsic_shuffle
:
7478 case nir_intrinsic_read_invocation
: {
7479 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7480 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7481 emit_uniform_subgroup(ctx
, instr
, src
);
7483 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7484 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7485 tid
= bld
.as_uniform(tid
);
7486 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7487 if (src
.regClass() == v1
) {
7488 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7489 } else if (src
.regClass() == v2
) {
7490 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7491 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7492 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7493 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7495 emit_split_vector(ctx
, dst
, 2);
7496 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7497 assert(src
.regClass() == bld
.lm
);
7498 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7499 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7500 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7501 assert(src
.regClass() == bld
.lm
);
7503 if (ctx
->program
->chip_class
<= GFX7
)
7504 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7505 else if (ctx
->program
->wave_size
== 64)
7506 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7508 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7509 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7510 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7511 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7513 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7514 nir_print_instr(&instr
->instr
, stderr
);
7515 fprintf(stderr
, "\n");
7520 case nir_intrinsic_load_sample_id
: {
7521 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7522 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7525 case nir_intrinsic_load_sample_mask_in
: {
7526 visit_load_sample_mask_in(ctx
, instr
);
7529 case nir_intrinsic_read_first_invocation
: {
7530 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7531 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7532 if (src
.regClass() == v1
) {
7534 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7536 } else if (src
.regClass() == v2
) {
7537 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7538 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7539 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7540 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7542 emit_split_vector(ctx
, dst
, 2);
7543 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7544 assert(src
.regClass() == bld
.lm
);
7545 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7546 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7547 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7548 } else if (src
.regClass() == s1
) {
7549 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7550 } else if (src
.regClass() == s2
) {
7551 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7553 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7554 nir_print_instr(&instr
->instr
, stderr
);
7555 fprintf(stderr
, "\n");
7559 case nir_intrinsic_vote_all
: {
7560 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7561 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7562 assert(src
.regClass() == bld
.lm
);
7563 assert(dst
.regClass() == bld
.lm
);
7565 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7566 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7567 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7570 case nir_intrinsic_vote_any
: {
7571 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7572 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7573 assert(src
.regClass() == bld
.lm
);
7574 assert(dst
.regClass() == bld
.lm
);
7576 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7577 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7580 case nir_intrinsic_reduce
:
7581 case nir_intrinsic_inclusive_scan
:
7582 case nir_intrinsic_exclusive_scan
: {
7583 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7584 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7585 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7586 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7587 nir_intrinsic_cluster_size(instr
) : 0;
7588 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7590 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7591 emit_uniform_subgroup(ctx
, instr
, src
);
7592 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7593 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7595 else if (op
== nir_op_iadd
)
7597 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7599 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7601 switch (instr
->intrinsic
) {
7602 case nir_intrinsic_reduce
:
7603 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7605 case nir_intrinsic_exclusive_scan
:
7606 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7608 case nir_intrinsic_inclusive_scan
:
7609 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7614 } else if (cluster_size
== 1) {
7615 bld
.copy(Definition(dst
), src
);
7617 src
= as_vgpr(ctx
, src
);
7621 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7636 unreachable("unknown reduction op");
7641 switch (instr
->intrinsic
) {
7642 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7643 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7644 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7646 unreachable("unknown reduce intrinsic");
7649 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7650 reduce
->operands
[0] = Operand(src
);
7651 // filled in by aco_reduce_assign.cpp, used internally as part of the
7653 assert(dst
.size() == 1 || dst
.size() == 2);
7654 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7655 reduce
->operands
[2] = Operand(v1
.as_linear());
7657 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7658 reduce
->definitions
[0] = Definition(tmp_dst
);
7659 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7660 reduce
->definitions
[2] = Definition();
7661 reduce
->definitions
[3] = Definition(scc
, s1
);
7662 reduce
->definitions
[4] = Definition();
7663 reduce
->reduce_op
= reduce_op
;
7664 reduce
->cluster_size
= cluster_size
;
7665 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7667 emit_wqm(ctx
, tmp_dst
, dst
);
7671 case nir_intrinsic_quad_broadcast
: {
7672 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7673 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7674 emit_uniform_subgroup(ctx
, instr
, src
);
7676 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7677 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7678 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7680 if (instr
->dest
.ssa
.bit_size
== 1) {
7681 assert(src
.regClass() == bld
.lm
);
7682 assert(dst
.regClass() == bld
.lm
);
7683 uint32_t half_mask
= 0x11111111u
<< lane
;
7684 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7685 Temp tmp
= bld
.tmp(bld
.lm
);
7686 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7687 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7688 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7689 emit_wqm(ctx
, tmp
, dst
);
7690 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7691 if (ctx
->program
->chip_class
>= GFX8
)
7692 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7694 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7695 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7696 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7697 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7698 if (ctx
->program
->chip_class
>= GFX8
) {
7699 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7700 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7702 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7703 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7705 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7706 emit_split_vector(ctx
, dst
, 2);
7708 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7709 nir_print_instr(&instr
->instr
, stderr
);
7710 fprintf(stderr
, "\n");
7715 case nir_intrinsic_quad_swap_horizontal
:
7716 case nir_intrinsic_quad_swap_vertical
:
7717 case nir_intrinsic_quad_swap_diagonal
:
7718 case nir_intrinsic_quad_swizzle_amd
: {
7719 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7720 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7721 emit_uniform_subgroup(ctx
, instr
, src
);
7724 uint16_t dpp_ctrl
= 0;
7725 switch (instr
->intrinsic
) {
7726 case nir_intrinsic_quad_swap_horizontal
:
7727 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7729 case nir_intrinsic_quad_swap_vertical
:
7730 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7732 case nir_intrinsic_quad_swap_diagonal
:
7733 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7735 case nir_intrinsic_quad_swizzle_amd
:
7736 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7741 if (ctx
->program
->chip_class
< GFX8
)
7742 dpp_ctrl
|= (1 << 15);
7744 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7745 if (instr
->dest
.ssa
.bit_size
== 1) {
7746 assert(src
.regClass() == bld
.lm
);
7747 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7748 if (ctx
->program
->chip_class
>= GFX8
)
7749 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7751 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7752 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7753 emit_wqm(ctx
, tmp
, dst
);
7754 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7756 if (ctx
->program
->chip_class
>= GFX8
)
7757 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7759 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7760 emit_wqm(ctx
, tmp
, dst
);
7761 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7762 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7763 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7764 if (ctx
->program
->chip_class
>= GFX8
) {
7765 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7766 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7768 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7769 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7771 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7772 emit_split_vector(ctx
, dst
, 2);
7774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7775 nir_print_instr(&instr
->instr
, stderr
);
7776 fprintf(stderr
, "\n");
7780 case nir_intrinsic_masked_swizzle_amd
: {
7781 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7782 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7783 emit_uniform_subgroup(ctx
, instr
, src
);
7786 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7787 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7788 if (dst
.regClass() == v1
) {
7790 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7792 } else if (dst
.regClass() == v2
) {
7793 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7794 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7795 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7796 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7797 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7798 emit_split_vector(ctx
, dst
, 2);
7800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7801 nir_print_instr(&instr
->instr
, stderr
);
7802 fprintf(stderr
, "\n");
7806 case nir_intrinsic_write_invocation_amd
: {
7807 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7808 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7809 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7810 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7811 if (dst
.regClass() == v1
) {
7812 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7813 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7814 } else if (dst
.regClass() == v2
) {
7815 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7816 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7817 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7818 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7819 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7820 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7821 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7822 emit_split_vector(ctx
, dst
, 2);
7824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7825 nir_print_instr(&instr
->instr
, stderr
);
7826 fprintf(stderr
, "\n");
7830 case nir_intrinsic_mbcnt_amd
: {
7831 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7832 RegClass rc
= RegClass(src
.type(), 1);
7833 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7835 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7836 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7837 emit_wqm(ctx
, wqm_tmp
, dst
);
7840 case nir_intrinsic_load_helper_invocation
: {
7841 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7842 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7843 ctx
->block
->kind
|= block_kind_needs_lowering
;
7844 ctx
->program
->needs_exact
= true;
7847 case nir_intrinsic_is_helper_invocation
: {
7848 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7849 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7850 ctx
->block
->kind
|= block_kind_needs_lowering
;
7851 ctx
->program
->needs_exact
= true;
7854 case nir_intrinsic_demote
:
7855 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7857 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7858 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7859 ctx
->block
->kind
|= block_kind_uses_demote
;
7860 ctx
->program
->needs_exact
= true;
7862 case nir_intrinsic_demote_if
: {
7863 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7864 assert(src
.regClass() == bld
.lm
);
7865 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7866 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7868 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7869 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7870 ctx
->block
->kind
|= block_kind_uses_demote
;
7871 ctx
->program
->needs_exact
= true;
7874 case nir_intrinsic_first_invocation
: {
7875 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7876 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7879 case nir_intrinsic_shader_clock
:
7880 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7881 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7883 case nir_intrinsic_load_vertex_id_zero_base
: {
7884 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7885 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7888 case nir_intrinsic_load_first_vertex
: {
7889 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7890 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7893 case nir_intrinsic_load_base_instance
: {
7894 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7895 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7898 case nir_intrinsic_load_instance_id
: {
7899 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7900 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7903 case nir_intrinsic_load_draw_id
: {
7904 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7905 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7908 case nir_intrinsic_load_invocation_id
: {
7909 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7911 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7912 if (ctx
->options
->chip_class
>= GFX10
)
7913 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7915 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7916 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7917 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7918 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7920 unreachable("Unsupported stage for load_invocation_id");
7925 case nir_intrinsic_load_primitive_id
: {
7926 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7928 switch (ctx
->shader
->info
.stage
) {
7929 case MESA_SHADER_GEOMETRY
:
7930 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7932 case MESA_SHADER_TESS_CTRL
:
7933 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7935 case MESA_SHADER_TESS_EVAL
:
7936 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7939 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7944 case nir_intrinsic_load_patch_vertices_in
: {
7945 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7946 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7948 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7949 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7952 case nir_intrinsic_emit_vertex_with_counter
: {
7953 visit_emit_vertex_with_counter(ctx
, instr
);
7956 case nir_intrinsic_end_primitive_with_counter
: {
7957 unsigned stream
= nir_intrinsic_stream_id(instr
);
7958 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7961 case nir_intrinsic_set_vertex_count
: {
7962 /* unused, the HW keeps track of this for us */
7966 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7967 nir_print_instr(&instr
->instr
, stderr
);
7968 fprintf(stderr
, "\n");
7976 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7977 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7978 enum glsl_base_type
*stype
)
7980 nir_deref_instr
*texture_deref_instr
= NULL
;
7981 nir_deref_instr
*sampler_deref_instr
= NULL
;
7984 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7985 switch (instr
->src
[i
].src_type
) {
7986 case nir_tex_src_texture_deref
:
7987 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7989 case nir_tex_src_sampler_deref
:
7990 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7992 case nir_tex_src_plane
:
7993 plane
= nir_src_as_int(instr
->src
[i
].src
);
8000 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8002 if (!sampler_deref_instr
)
8003 sampler_deref_instr
= texture_deref_instr
;
8006 assert(instr
->op
!= nir_texop_txf_ms
&&
8007 instr
->op
!= nir_texop_samples_identical
);
8008 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8009 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8010 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8011 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8012 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8013 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8015 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8018 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8020 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8021 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8022 Builder
bld(ctx
->program
, ctx
->block
);
8024 /* to avoid unnecessary moves, we split and recombine sampler and image */
8025 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8026 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8027 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8028 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8029 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8030 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8031 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8032 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8034 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8035 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8036 img
[0], img
[1], img
[2], img
[3],
8037 img
[4], img
[5], img
[6], img
[7]);
8038 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8039 samp
[0], samp
[1], samp
[2], samp
[3]);
8042 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8043 instr
->op
== nir_texop_samples_identical
))
8044 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8047 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8048 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8050 Builder
bld(ctx
->program
, ctx
->block
);
8052 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8053 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8054 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8056 Operand
neg_one(0xbf800000u
);
8057 Operand
one(0x3f800000u
);
8058 Operand
two(0x40000000u
);
8059 Operand
four(0x40800000u
);
8061 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8062 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8063 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8065 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8066 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8067 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8068 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8071 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8072 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8073 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8075 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8078 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8079 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8080 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8083 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8084 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8086 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8087 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8090 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8092 Builder
bld(ctx
->program
, ctx
->block
);
8093 Temp ma
, tc
, sc
, id
;
8096 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8098 // see comment in ac_prepare_cube_coords()
8099 if (ctx
->options
->chip_class
<= GFX8
)
8100 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8103 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8105 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8106 vop3a
->operands
[0] = Operand(ma
);
8107 vop3a
->abs
[0] = true;
8108 Temp invma
= bld
.tmp(v1
);
8109 vop3a
->definitions
[0] = Definition(invma
);
8110 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8112 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8114 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8116 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8118 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8120 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8123 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8124 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8126 for (unsigned i
= 0; i
< 2; i
++) {
8127 // see comment in ac_prepare_cube_coords()
8129 Temp deriv_sc
, deriv_tc
;
8130 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8131 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8133 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8135 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8136 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8137 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8138 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8139 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8140 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8141 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8144 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8145 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8149 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8156 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8158 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8160 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8161 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8164 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8165 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8166 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8170 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8172 Builder
bld(ctx
->program
, ctx
->block
);
8173 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8174 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8175 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8176 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8177 std::vector
<Temp
> coords
;
8178 std::vector
<Temp
> derivs
;
8179 nir_const_value
*sample_index_cv
= NULL
;
8180 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8181 enum glsl_base_type stype
;
8182 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8184 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8185 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8186 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8187 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8189 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8190 switch (instr
->src
[i
].src_type
) {
8191 case nir_tex_src_coord
: {
8192 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8193 for (unsigned i
= 0; i
< coord
.size(); i
++)
8194 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8197 case nir_tex_src_bias
:
8198 if (instr
->op
== nir_texop_txb
) {
8199 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8203 case nir_tex_src_lod
: {
8204 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8206 if (val
&& val
->f32
<= 0.0) {
8209 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8214 case nir_tex_src_comparator
:
8215 if (instr
->is_shadow
) {
8216 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8220 case nir_tex_src_offset
:
8221 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8222 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8225 case nir_tex_src_ddx
:
8226 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8229 case nir_tex_src_ddy
:
8230 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8233 case nir_tex_src_ms_index
:
8234 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8235 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8236 has_sample_index
= true;
8238 case nir_tex_src_texture_offset
:
8239 case nir_tex_src_sampler_offset
:
8245 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8246 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8248 if (instr
->op
== nir_texop_texture_samples
) {
8249 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8251 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8252 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8253 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8255 Operand default_sample
= Operand(1u);
8256 if (ctx
->options
->robust_buffer_access
) {
8257 /* Extract the second dword of the descriptor, if it's
8258 * all zero, then it's a null descriptor.
8260 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8261 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8262 default_sample
= Operand(is_non_null_descriptor
);
8265 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8266 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8267 samples
, default_sample
, bld
.scc(is_msaa
));
8271 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8272 aco_ptr
<Instruction
> tmp_instr
;
8273 Temp acc
, pack
= Temp();
8275 uint32_t pack_const
= 0;
8276 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8277 if (!const_offset
[i
])
8279 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8282 if (offset
.type() == RegType::sgpr
) {
8283 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8284 if (const_offset
[i
])
8287 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8288 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8291 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8294 if (pack
== Temp()) {
8297 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8301 if (pack_const
&& pack
!= Temp())
8302 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8304 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8305 if (const_offset
[i
])
8308 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8309 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8312 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8315 if (pack
== Temp()) {
8318 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8322 if (pack_const
&& pack
!= Temp())
8323 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8325 if (pack_const
&& pack
== Temp())
8326 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8327 else if (pack
== Temp())
8333 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8334 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8336 /* pack derivatives */
8337 if (has_ddx
|| has_ddy
) {
8338 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8339 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8340 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8341 derivs
= {ddx
, zero
, ddy
, zero
};
8343 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8344 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8345 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8346 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8351 if (instr
->coord_components
> 1 &&
8352 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8354 instr
->op
!= nir_texop_txf
)
8355 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8357 if (instr
->coord_components
> 2 &&
8358 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8359 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8360 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8361 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8363 instr
->op
!= nir_texop_txf
&&
8364 instr
->op
!= nir_texop_txf_ms
&&
8365 instr
->op
!= nir_texop_fragment_fetch
&&
8366 instr
->op
!= nir_texop_fragment_mask_fetch
)
8367 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8369 if (ctx
->options
->chip_class
== GFX9
&&
8370 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8371 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8372 assert(coords
.size() > 0 && coords
.size() < 3);
8374 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8375 Operand((uint32_t) 0) :
8376 Operand((uint32_t) 0x3f000000)));
8379 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8381 if (instr
->op
== nir_texop_samples_identical
)
8382 resource
= fmask_ptr
;
8384 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8385 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8386 instr
->op
!= nir_texop_txs
&&
8387 instr
->op
!= nir_texop_fragment_fetch
&&
8388 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8389 assert(has_sample_index
);
8390 Operand
op(sample_index
);
8391 if (sample_index_cv
)
8392 op
= Operand(sample_index_cv
->u32
);
8393 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8396 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8397 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8398 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8399 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8404 /* Build tex instruction */
8405 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8406 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8407 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8409 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8412 /* gather4 selects the component by dmask and always returns vec4 */
8413 if (instr
->op
== nir_texop_tg4
) {
8414 assert(instr
->dest
.ssa
.num_components
== 4);
8415 if (instr
->is_shadow
)
8418 dmask
= 1 << instr
->component
;
8419 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8420 tmp_dst
= bld
.tmp(v4
);
8421 } else if (instr
->op
== nir_texop_samples_identical
) {
8422 tmp_dst
= bld
.tmp(v1
);
8423 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8424 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8427 aco_ptr
<MIMG_instruction
> tex
;
8428 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8430 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8432 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8433 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8436 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8437 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8439 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8440 tex
->operands
[0] = Operand(resource
);
8441 tex
->operands
[1] = Operand(s4
); /* no sampler */
8442 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8443 if (ctx
->options
->chip_class
== GFX9
&&
8444 instr
->op
== nir_texop_txs
&&
8445 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8447 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8448 } else if (instr
->op
== nir_texop_query_levels
) {
8449 tex
->dmask
= 1 << 3;
8454 tex
->definitions
[0] = Definition(tmp_dst
);
8456 tex
->can_reorder
= true;
8457 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8460 /* divide 3rd value by 6 by multiplying with magic number */
8461 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8462 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8463 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8464 assert(instr
->dest
.ssa
.num_components
== 3);
8465 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8466 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8467 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8468 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8473 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8477 Temp tg4_compare_cube_wa64
= Temp();
8479 if (tg4_integer_workarounds
) {
8480 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8481 tex
->operands
[0] = Operand(resource
);
8482 tex
->operands
[1] = Operand(s4
); /* no sampler */
8483 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8487 Temp size
= bld
.tmp(v2
);
8488 tex
->definitions
[0] = Definition(size
);
8489 tex
->can_reorder
= true;
8490 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8491 emit_split_vector(ctx
, size
, size
.size());
8494 for (unsigned i
= 0; i
< 2; i
++) {
8495 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8496 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8497 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8498 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8501 Temp new_coords
[2] = {
8502 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8503 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8506 if (tg4_integer_cube_workaround
) {
8507 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8508 Temp desc
[resource
.size()];
8509 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8510 Format::PSEUDO
, 1, resource
.size())};
8511 split
->operands
[0] = Operand(resource
);
8512 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8513 desc
[i
] = bld
.tmp(s1
);
8514 split
->definitions
[i
] = Definition(desc
[i
]);
8516 ctx
->block
->instructions
.emplace_back(std::move(split
));
8518 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8519 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8520 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8523 if (stype
== GLSL_TYPE_UINT
) {
8524 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8525 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8526 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8527 bld
.scc(compare_cube_wa
));
8529 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8530 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8531 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8532 bld
.scc(compare_cube_wa
));
8534 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8535 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8537 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8539 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8540 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8541 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8543 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8544 Format::PSEUDO
, resource
.size(), 1)};
8545 for (unsigned i
= 0; i
< resource
.size(); i
++)
8546 vec
->operands
[i
] = Operand(desc
[i
]);
8547 resource
= bld
.tmp(resource
.regClass());
8548 vec
->definitions
[0] = Definition(resource
);
8549 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8551 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8552 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8553 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8554 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8556 coords
[0] = new_coords
[0];
8557 coords
[1] = new_coords
[1];
8560 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8561 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8563 assert(coords
.size() == 1);
8564 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8568 op
= aco_opcode::buffer_load_format_x
; break;
8570 op
= aco_opcode::buffer_load_format_xy
; break;
8572 op
= aco_opcode::buffer_load_format_xyz
; break;
8574 op
= aco_opcode::buffer_load_format_xyzw
; break;
8576 unreachable("Tex instruction loads more than 4 components.");
8579 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8580 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8583 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8585 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8586 mubuf
->operands
[0] = Operand(resource
);
8587 mubuf
->operands
[1] = Operand(coords
[0]);
8588 mubuf
->operands
[2] = Operand((uint32_t) 0);
8589 mubuf
->definitions
[0] = Definition(tmp_dst
);
8590 mubuf
->idxen
= true;
8591 mubuf
->can_reorder
= true;
8592 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8594 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8598 /* gather MIMG address components */
8599 std::vector
<Temp
> args
;
8601 args
.emplace_back(offset
);
8603 args
.emplace_back(bias
);
8605 args
.emplace_back(compare
);
8607 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8609 args
.insert(args
.end(), coords
.begin(), coords
.end());
8610 if (has_sample_index
)
8611 args
.emplace_back(sample_index
);
8613 args
.emplace_back(lod
);
8615 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8616 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8617 vec
->definitions
[0] = Definition(arg
);
8618 for (unsigned i
= 0; i
< args
.size(); i
++)
8619 vec
->operands
[i
] = Operand(args
[i
]);
8620 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8623 if (instr
->op
== nir_texop_txf
||
8624 instr
->op
== nir_texop_txf_ms
||
8625 instr
->op
== nir_texop_samples_identical
||
8626 instr
->op
== nir_texop_fragment_fetch
||
8627 instr
->op
== nir_texop_fragment_mask_fetch
) {
8628 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8629 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8630 tex
->operands
[0] = Operand(resource
);
8631 tex
->operands
[1] = Operand(s4
); /* no sampler */
8632 tex
->operands
[2] = Operand(arg
);
8637 tex
->definitions
[0] = Definition(tmp_dst
);
8638 tex
->can_reorder
= true;
8639 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8641 if (instr
->op
== nir_texop_samples_identical
) {
8642 assert(dmask
== 1 && dst
.regClass() == v1
);
8643 assert(dst
.id() != tmp_dst
.id());
8645 Temp tmp
= bld
.tmp(bld
.lm
);
8646 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8647 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8650 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8655 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8656 aco_opcode opcode
= aco_opcode::image_sample
;
8657 if (has_offset
) { /* image_sample_*_o */
8659 opcode
= aco_opcode::image_sample_c_o
;
8661 opcode
= aco_opcode::image_sample_c_d_o
;
8663 opcode
= aco_opcode::image_sample_c_b_o
;
8665 opcode
= aco_opcode::image_sample_c_lz_o
;
8667 opcode
= aco_opcode::image_sample_c_l_o
;
8669 opcode
= aco_opcode::image_sample_o
;
8671 opcode
= aco_opcode::image_sample_d_o
;
8673 opcode
= aco_opcode::image_sample_b_o
;
8675 opcode
= aco_opcode::image_sample_lz_o
;
8677 opcode
= aco_opcode::image_sample_l_o
;
8679 } else { /* no offset */
8681 opcode
= aco_opcode::image_sample_c
;
8683 opcode
= aco_opcode::image_sample_c_d
;
8685 opcode
= aco_opcode::image_sample_c_b
;
8687 opcode
= aco_opcode::image_sample_c_lz
;
8689 opcode
= aco_opcode::image_sample_c_l
;
8691 opcode
= aco_opcode::image_sample
;
8693 opcode
= aco_opcode::image_sample_d
;
8695 opcode
= aco_opcode::image_sample_b
;
8697 opcode
= aco_opcode::image_sample_lz
;
8699 opcode
= aco_opcode::image_sample_l
;
8703 if (instr
->op
== nir_texop_tg4
) {
8705 opcode
= aco_opcode::image_gather4_lz_o
;
8707 opcode
= aco_opcode::image_gather4_c_lz_o
;
8709 opcode
= aco_opcode::image_gather4_lz
;
8711 opcode
= aco_opcode::image_gather4_c_lz
;
8713 } else if (instr
->op
== nir_texop_lod
) {
8714 opcode
= aco_opcode::image_get_lod
;
8717 /* we don't need the bias, sample index, compare value or offset to be
8718 * computed in WQM but if the p_create_vector copies the coordinates, then it
8719 * needs to be in WQM */
8720 if (ctx
->stage
== fragment_fs
&&
8721 !has_derivs
&& !has_lod
&& !level_zero
&&
8722 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8723 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8724 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8726 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8727 tex
->operands
[0] = Operand(resource
);
8728 tex
->operands
[1] = Operand(sampler
);
8729 tex
->operands
[2] = Operand(arg
);
8733 tex
->definitions
[0] = Definition(tmp_dst
);
8734 tex
->can_reorder
= true;
8735 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8737 if (tg4_integer_cube_workaround
) {
8738 assert(tmp_dst
.id() != dst
.id());
8739 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8741 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8743 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8744 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8746 if (stype
== GLSL_TYPE_UINT
)
8747 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8749 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8750 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8752 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8753 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8754 val
[0], val
[1], val
[2], val
[3]);
8756 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8757 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8762 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8764 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8765 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8766 return Operand(tmp
.regClass());
8768 return Operand(tmp
);
8771 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8773 aco_ptr
<Pseudo_instruction
> phi
;
8774 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8775 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8777 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8778 logical
|= ctx
->block
->kind
& block_kind_merge
;
8779 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8781 /* we want a sorted list of sources, since the predecessor list is also sorted */
8782 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8783 nir_foreach_phi_src(src
, instr
)
8784 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8786 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8787 unsigned num_operands
= 0;
8788 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8789 unsigned num_defined
= 0;
8790 unsigned cur_pred_idx
= 0;
8791 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8792 if (cur_pred_idx
< preds
.size()) {
8793 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8794 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8795 unsigned skipped
= 0;
8796 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8798 if (cur_pred_idx
+ skipped
< preds
.size()) {
8799 for (unsigned i
= 0; i
< skipped
; i
++)
8800 operands
[num_operands
++] = Operand(dst
.regClass());
8801 cur_pred_idx
+= skipped
;
8806 /* Handle missing predecessors at the end. This shouldn't happen with loop
8807 * headers and we can't ignore these sources for loop header phis. */
8808 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8811 Operand op
= get_phi_operand(ctx
, src
.second
);
8812 operands
[num_operands
++] = op
;
8813 num_defined
+= !op
.isUndefined();
8815 /* handle block_kind_continue_or_break at loop exit blocks */
8816 while (cur_pred_idx
++ < preds
.size())
8817 operands
[num_operands
++] = Operand(dst
.regClass());
8819 /* If the loop ends with a break, still add a linear continue edge in case
8820 * that break is divergent or continue_or_break is used. We'll either remove
8821 * this operand later in visit_loop() if it's not necessary or replace the
8822 * undef with something correct. */
8823 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8824 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8825 nir_block
*last
= nir_loop_last_block(loop
);
8826 if (last
->successors
[0] != instr
->instr
.block
)
8827 operands
[num_operands
++] = Operand(RegClass());
8830 if (num_defined
== 0) {
8831 Builder
bld(ctx
->program
, ctx
->block
);
8832 if (dst
.regClass() == s1
) {
8833 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8834 } else if (dst
.regClass() == v1
) {
8835 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8837 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8838 for (unsigned i
= 0; i
< dst
.size(); i
++)
8839 vec
->operands
[i
] = Operand(0u);
8840 vec
->definitions
[0] = Definition(dst
);
8841 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8846 /* we can use a linear phi in some cases if one src is undef */
8847 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8848 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8850 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8851 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8852 assert(invert
->kind
& block_kind_invert
);
8854 unsigned then_block
= invert
->linear_preds
[0];
8856 Block
* insert_block
= NULL
;
8857 for (unsigned i
= 0; i
< num_operands
; i
++) {
8858 Operand op
= operands
[i
];
8859 if (op
.isUndefined())
8861 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8862 phi
->operands
[0] = op
;
8865 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8866 phi
->operands
[1] = Operand(dst
.regClass());
8867 phi
->definitions
[0] = Definition(dst
);
8868 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8872 /* try to scalarize vector phis */
8873 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8874 // TODO: scalarize linear phis on divergent ifs
8875 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8876 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8877 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8878 Operand src
= operands
[i
];
8879 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8880 can_scalarize
= false;
8882 if (can_scalarize
) {
8883 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8884 assert(dst
.size() % num_components
== 0);
8885 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8887 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8888 for (unsigned k
= 0; k
< num_components
; k
++) {
8889 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8890 for (unsigned i
= 0; i
< num_operands
; i
++) {
8891 Operand src
= operands
[i
];
8892 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8894 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8895 phi
->definitions
[0] = Definition(phi_dst
);
8896 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8897 new_vec
[k
] = phi_dst
;
8898 vec
->operands
[k
] = Operand(phi_dst
);
8900 vec
->definitions
[0] = Definition(dst
);
8901 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8902 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8907 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8908 for (unsigned i
= 0; i
< num_operands
; i
++)
8909 phi
->operands
[i
] = operands
[i
];
8910 phi
->definitions
[0] = Definition(dst
);
8911 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8915 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8917 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8919 assert(dst
.type() == RegType::sgpr
);
8921 if (dst
.size() == 1) {
8922 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8924 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8925 for (unsigned i
= 0; i
< dst
.size(); i
++)
8926 vec
->operands
[i
] = Operand(0u);
8927 vec
->definitions
[0] = Definition(dst
);
8928 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8932 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8934 Builder
bld(ctx
->program
, ctx
->block
);
8935 Block
*logical_target
;
8936 append_logical_end(ctx
->block
);
8937 unsigned idx
= ctx
->block
->index
;
8939 switch (instr
->type
) {
8940 case nir_jump_break
:
8941 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8942 add_logical_edge(idx
, logical_target
);
8943 ctx
->block
->kind
|= block_kind_break
;
8945 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8946 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8947 /* uniform break - directly jump out of the loop */
8948 ctx
->block
->kind
|= block_kind_uniform
;
8949 ctx
->cf_info
.has_branch
= true;
8950 bld
.branch(aco_opcode::p_branch
);
8951 add_linear_edge(idx
, logical_target
);
8954 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8955 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8957 case nir_jump_continue
:
8958 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8959 add_logical_edge(idx
, logical_target
);
8960 ctx
->block
->kind
|= block_kind_continue
;
8962 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8963 /* for potential uniform breaks after this continue,
8964 we must ensure that they are handled correctly */
8965 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8966 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8967 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8969 /* uniform continue - directly jump to the loop header */
8970 ctx
->block
->kind
|= block_kind_uniform
;
8971 ctx
->cf_info
.has_branch
= true;
8972 bld
.branch(aco_opcode::p_branch
);
8973 add_linear_edge(idx
, logical_target
);
8978 fprintf(stderr
, "Unknown NIR jump instr: ");
8979 nir_print_instr(&instr
->instr
, stderr
);
8980 fprintf(stderr
, "\n");
8984 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8985 ctx
->cf_info
.exec_potentially_empty_break
= true;
8986 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8989 /* remove critical edges from linear CFG */
8990 bld
.branch(aco_opcode::p_branch
);
8991 Block
* break_block
= ctx
->program
->create_and_insert_block();
8992 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8993 break_block
->kind
|= block_kind_uniform
;
8994 add_linear_edge(idx
, break_block
);
8995 /* the loop_header pointer might be invalidated by this point */
8996 if (instr
->type
== nir_jump_continue
)
8997 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8998 add_linear_edge(break_block
->index
, logical_target
);
8999 bld
.reset(break_block
);
9000 bld
.branch(aco_opcode::p_branch
);
9002 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9003 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9004 add_linear_edge(idx
, continue_block
);
9005 append_logical_start(continue_block
);
9006 ctx
->block
= continue_block
;
9010 void visit_block(isel_context
*ctx
, nir_block
*block
)
9012 nir_foreach_instr(instr
, block
) {
9013 switch (instr
->type
) {
9014 case nir_instr_type_alu
:
9015 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9017 case nir_instr_type_load_const
:
9018 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9020 case nir_instr_type_intrinsic
:
9021 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9023 case nir_instr_type_tex
:
9024 visit_tex(ctx
, nir_instr_as_tex(instr
));
9026 case nir_instr_type_phi
:
9027 visit_phi(ctx
, nir_instr_as_phi(instr
));
9029 case nir_instr_type_ssa_undef
:
9030 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9032 case nir_instr_type_deref
:
9034 case nir_instr_type_jump
:
9035 visit_jump(ctx
, nir_instr_as_jump(instr
));
9038 fprintf(stderr
, "Unknown NIR instr type: ");
9039 nir_print_instr(instr
, stderr
);
9040 fprintf(stderr
, "\n");
9045 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9046 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9051 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9052 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9054 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9055 RegClass rc
= vals
[0].regClass();
9057 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9059 unsigned next_pred
= 1;
9061 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9062 Block
& block
= ctx
->program
->blocks
[idx
];
9063 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9064 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9068 if (block
.kind
& block_kind_continue
) {
9069 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9074 bool all_same
= true;
9075 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9076 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9080 val
= vals
[block
.linear_preds
[0] - first
];
9082 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9083 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9084 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9085 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9086 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9087 phi
->definitions
[0] = Definition(val
.getTemp());
9088 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9090 vals
[idx
- first
] = val
;
9093 return vals
[last
- first
];
9096 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9098 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9099 append_logical_end(ctx
->block
);
9100 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9101 Builder
bld(ctx
->program
, ctx
->block
);
9102 bld
.branch(aco_opcode::p_branch
);
9103 unsigned loop_preheader_idx
= ctx
->block
->index
;
9105 Block loop_exit
= Block();
9106 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9107 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9109 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9110 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9111 loop_header
->kind
|= block_kind_loop_header
;
9112 add_edge(loop_preheader_idx
, loop_header
);
9113 ctx
->block
= loop_header
;
9115 /* emit loop body */
9116 unsigned loop_header_idx
= loop_header
->index
;
9117 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9118 append_logical_start(ctx
->block
);
9119 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9121 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9122 if (!ctx
->cf_info
.has_branch
) {
9123 append_logical_end(ctx
->block
);
9124 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9125 /* Discards can result in code running with an empty exec mask.
9126 * This would result in divergent breaks not ever being taken. As a
9127 * workaround, break the loop when the loop mask is empty instead of
9128 * always continuing. */
9129 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9130 unsigned block_idx
= ctx
->block
->index
;
9132 /* create helper blocks to avoid critical edges */
9133 Block
*break_block
= ctx
->program
->create_and_insert_block();
9134 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9135 break_block
->kind
= block_kind_uniform
;
9136 bld
.reset(break_block
);
9137 bld
.branch(aco_opcode::p_branch
);
9138 add_linear_edge(block_idx
, break_block
);
9139 add_linear_edge(break_block
->index
, &loop_exit
);
9141 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9142 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9143 continue_block
->kind
= block_kind_uniform
;
9144 bld
.reset(continue_block
);
9145 bld
.branch(aco_opcode::p_branch
);
9146 add_linear_edge(block_idx
, continue_block
);
9147 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9149 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9150 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9151 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9153 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9154 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9155 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9157 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9160 bld
.reset(ctx
->block
);
9161 bld
.branch(aco_opcode::p_branch
);
9164 /* Fixup phis in loop header from unreachable blocks.
9165 * has_branch/has_divergent_branch also indicates if the loop ends with a
9166 * break/continue instruction, but we don't emit those if unreachable=true */
9168 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9169 bool linear
= ctx
->cf_info
.has_branch
;
9170 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9171 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9172 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9173 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9174 /* the last operand should be the one that needs to be removed */
9175 instr
->operands
.pop_back();
9176 } else if (!is_phi(instr
)) {
9182 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9183 * and the previous one shouldn't both happen at once because a break in the
9184 * merge block would get CSE'd */
9185 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9186 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9187 Operand vals
[num_vals
];
9188 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9189 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9190 if (ctx
->cf_info
.has_branch
)
9191 instr
->operands
.pop_back();
9193 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9194 } else if (!is_phi(instr
)) {
9200 ctx
->cf_info
.has_branch
= false;
9202 // TODO: if the loop has not a single exit, we must add one °°
9203 /* emit loop successor block */
9204 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9205 append_logical_start(ctx
->block
);
9208 // TODO: check if it is beneficial to not branch on continues
9209 /* trim linear phis in loop header */
9210 for (auto&& instr
: loop_entry
->instructions
) {
9211 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9212 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9213 new_phi
->definitions
[0] = instr
->definitions
[0];
9214 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9215 new_phi
->operands
[i
] = instr
->operands
[i
];
9216 /* check that the remaining operands are all the same */
9217 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9218 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9219 instr
.swap(new_phi
);
9220 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9229 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9233 append_logical_end(ctx
->block
);
9234 ctx
->block
->kind
|= block_kind_branch
;
9236 /* branch to linear then block */
9237 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9238 aco_ptr
<Pseudo_branch_instruction
> branch
;
9239 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9240 branch
->operands
[0] = Operand(cond
);
9241 ctx
->block
->instructions
.push_back(std::move(branch
));
9243 ic
->BB_if_idx
= ctx
->block
->index
;
9244 ic
->BB_invert
= Block();
9245 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9246 /* Invert blocks are intentionally not marked as top level because they
9247 * are not part of the logical cfg. */
9248 ic
->BB_invert
.kind
|= block_kind_invert
;
9249 ic
->BB_endif
= Block();
9250 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9251 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9253 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9254 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9255 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9256 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9257 ctx
->cf_info
.parent_if
.is_divergent
= true;
9259 /* divergent branches use cbranch_execz */
9260 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9261 ctx
->cf_info
.exec_potentially_empty_break
= false;
9262 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9264 /** emit logical then block */
9265 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9266 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9267 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9268 ctx
->block
= BB_then_logical
;
9269 append_logical_start(BB_then_logical
);
9272 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9274 Block
*BB_then_logical
= ctx
->block
;
9275 append_logical_end(BB_then_logical
);
9276 /* branch from logical then block to invert block */
9277 aco_ptr
<Pseudo_branch_instruction
> branch
;
9278 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9279 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9280 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9281 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9282 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9283 BB_then_logical
->kind
|= block_kind_uniform
;
9284 assert(!ctx
->cf_info
.has_branch
);
9285 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9286 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9288 /** emit linear then block */
9289 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9290 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9291 BB_then_linear
->kind
|= block_kind_uniform
;
9292 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9293 /* branch from linear then block to invert block */
9294 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9295 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9296 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9298 /** emit invert merge block */
9299 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9300 ic
->invert_idx
= ctx
->block
->index
;
9302 /* branch to linear else block (skip else) */
9303 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9304 branch
->operands
[0] = Operand(ic
->cond
);
9305 ctx
->block
->instructions
.push_back(std::move(branch
));
9307 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9308 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9309 ic
->exec_potentially_empty_break_depth_old
=
9310 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9311 /* divergent branches use cbranch_execz */
9312 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9313 ctx
->cf_info
.exec_potentially_empty_break
= false;
9314 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9316 /** emit logical else block */
9317 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9318 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9319 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9320 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9321 ctx
->block
= BB_else_logical
;
9322 append_logical_start(BB_else_logical
);
9325 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9327 Block
*BB_else_logical
= ctx
->block
;
9328 append_logical_end(BB_else_logical
);
9330 /* branch from logical else block to endif block */
9331 aco_ptr
<Pseudo_branch_instruction
> branch
;
9332 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9333 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9334 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9335 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9336 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9337 BB_else_logical
->kind
|= block_kind_uniform
;
9339 assert(!ctx
->cf_info
.has_branch
);
9340 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9343 /** emit linear else block */
9344 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9345 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9346 BB_else_linear
->kind
|= block_kind_uniform
;
9347 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9349 /* branch from linear else block to endif block */
9350 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9351 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9352 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9355 /** emit endif merge block */
9356 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9357 append_logical_start(ctx
->block
);
9360 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9361 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9362 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9363 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9364 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9365 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9366 !ctx
->cf_info
.parent_if
.is_divergent
) {
9367 ctx
->cf_info
.exec_potentially_empty_break
= false;
9368 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9370 /* uniform control flow never has an empty exec-mask */
9371 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9372 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9373 ctx
->cf_info
.exec_potentially_empty_break
= false;
9374 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9378 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9380 assert(cond
.regClass() == s1
);
9382 append_logical_end(ctx
->block
);
9383 ctx
->block
->kind
|= block_kind_uniform
;
9385 aco_ptr
<Pseudo_branch_instruction
> branch
;
9386 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9387 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9388 branch
->operands
[0] = Operand(cond
);
9389 branch
->operands
[0].setFixed(scc
);
9390 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9392 ic
->BB_if_idx
= ctx
->block
->index
;
9393 ic
->BB_endif
= Block();
9394 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9395 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9397 ctx
->cf_info
.has_branch
= false;
9398 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9400 /** emit then block */
9401 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9402 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9403 add_edge(ic
->BB_if_idx
, BB_then
);
9404 append_logical_start(BB_then
);
9405 ctx
->block
= BB_then
;
9408 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9410 Block
*BB_then
= ctx
->block
;
9412 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9413 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9415 if (!ic
->uniform_has_then_branch
) {
9416 append_logical_end(BB_then
);
9417 /* branch from then block to endif block */
9418 aco_ptr
<Pseudo_branch_instruction
> branch
;
9419 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9420 BB_then
->instructions
.emplace_back(std::move(branch
));
9421 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9422 if (!ic
->then_branch_divergent
)
9423 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9424 BB_then
->kind
|= block_kind_uniform
;
9427 ctx
->cf_info
.has_branch
= false;
9428 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9430 /** emit else block */
9431 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9432 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9433 add_edge(ic
->BB_if_idx
, BB_else
);
9434 append_logical_start(BB_else
);
9435 ctx
->block
= BB_else
;
9438 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9440 Block
*BB_else
= ctx
->block
;
9442 if (!ctx
->cf_info
.has_branch
) {
9443 append_logical_end(BB_else
);
9444 /* branch from then block to endif block */
9445 aco_ptr
<Pseudo_branch_instruction
> branch
;
9446 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9447 BB_else
->instructions
.emplace_back(std::move(branch
));
9448 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9449 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9450 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9451 BB_else
->kind
|= block_kind_uniform
;
9454 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9455 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9457 /** emit endif merge block */
9458 if (!ctx
->cf_info
.has_branch
) {
9459 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9460 append_logical_start(ctx
->block
);
9464 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9466 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9467 Builder
bld(ctx
->program
, ctx
->block
);
9468 aco_ptr
<Pseudo_branch_instruction
> branch
;
9471 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9473 * Uniform conditionals are represented in the following way*) :
9475 * The linear and logical CFG:
9478 * BB_THEN (logical) BB_ELSE (logical)
9482 * *) Exceptions may be due to break and continue statements within loops
9483 * If a break/continue happens within uniform control flow, it branches
9484 * to the loop exit/entry block. Otherwise, it branches to the next
9488 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9489 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9490 cond
= bool_to_scalar_condition(ctx
, cond
);
9492 begin_uniform_if_then(ctx
, &ic
, cond
);
9493 visit_cf_list(ctx
, &if_stmt
->then_list
);
9495 begin_uniform_if_else(ctx
, &ic
);
9496 visit_cf_list(ctx
, &if_stmt
->else_list
);
9498 end_uniform_if(ctx
, &ic
);
9499 } else { /* non-uniform condition */
9501 * To maintain a logical and linear CFG without critical edges,
9502 * non-uniform conditionals are represented in the following way*) :
9507 * BB_THEN (logical) BB_THEN (linear)
9509 * BB_INVERT (linear)
9511 * BB_ELSE (logical) BB_ELSE (linear)
9518 * BB_THEN (logical) BB_ELSE (logical)
9522 * *) Exceptions may be due to break and continue statements within loops
9525 begin_divergent_if_then(ctx
, &ic
, cond
);
9526 visit_cf_list(ctx
, &if_stmt
->then_list
);
9528 begin_divergent_if_else(ctx
, &ic
);
9529 visit_cf_list(ctx
, &if_stmt
->else_list
);
9531 end_divergent_if(ctx
, &ic
);
9534 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9537 static bool visit_cf_list(isel_context
*ctx
,
9538 struct exec_list
*list
)
9540 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9541 switch (node
->type
) {
9542 case nir_cf_node_block
:
9543 visit_block(ctx
, nir_cf_node_as_block(node
));
9545 case nir_cf_node_if
:
9546 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9549 case nir_cf_node_loop
:
9550 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9553 unreachable("unimplemented cf list type");
9559 static void create_null_export(isel_context
*ctx
)
9561 /* Some shader stages always need to have exports.
9562 * So when there is none, we need to add a null export.
9565 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9566 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9567 Builder
bld(ctx
->program
, ctx
->block
);
9568 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9569 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9572 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9574 assert(ctx
->stage
== vertex_vs
||
9575 ctx
->stage
== tess_eval_vs
||
9576 ctx
->stage
== gs_copy_vs
||
9577 ctx
->stage
== ngg_vertex_gs
||
9578 ctx
->stage
== ngg_tess_eval_gs
);
9580 int offset
= (ctx
->stage
& sw_tes
)
9581 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9582 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9583 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9584 if (!is_pos
&& !mask
)
9586 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9588 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9589 exp
->enabled_mask
= mask
;
9590 for (unsigned i
= 0; i
< 4; ++i
) {
9591 if (mask
& (1 << i
))
9592 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9594 exp
->operands
[i
] = Operand(v1
);
9596 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9597 * Setting valid_mask=1 prevents it and has no other effect.
9599 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9601 exp
->compressed
= false;
9603 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9605 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9606 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9611 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9613 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9614 exp
->enabled_mask
= 0;
9615 for (unsigned i
= 0; i
< 4; ++i
)
9616 exp
->operands
[i
] = Operand(v1
);
9617 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9618 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9619 exp
->enabled_mask
|= 0x1;
9621 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9622 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9623 exp
->enabled_mask
|= 0x4;
9625 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9626 if (ctx
->options
->chip_class
< GFX9
) {
9627 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9628 exp
->enabled_mask
|= 0x8;
9630 Builder
bld(ctx
->program
, ctx
->block
);
9632 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9633 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9634 if (exp
->operands
[2].isTemp())
9635 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9637 exp
->operands
[2] = Operand(out
);
9638 exp
->enabled_mask
|= 0x4;
9641 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9643 exp
->compressed
= false;
9644 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9645 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9648 static void create_export_phis(isel_context
*ctx
)
9650 /* Used when exports are needed, but the output temps are defined in a preceding block.
9651 * This function will set up phis in order to access the outputs in the next block.
9654 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9655 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9656 ctx
->block
->instructions
.pop_back();
9658 Builder
bld(ctx
->program
, ctx
->block
);
9660 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9661 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9662 for (unsigned i
= 0; i
< 4; ++i
) {
9663 if (!(mask
& (1 << i
)))
9666 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9667 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9668 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9672 bld
.insert(std::move(logical_start
));
9675 static void create_vs_exports(isel_context
*ctx
)
9677 assert(ctx
->stage
== vertex_vs
||
9678 ctx
->stage
== tess_eval_vs
||
9679 ctx
->stage
== gs_copy_vs
||
9680 ctx
->stage
== ngg_vertex_gs
||
9681 ctx
->stage
== ngg_tess_eval_gs
);
9683 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9684 ? &ctx
->program
->info
->tes
.outinfo
9685 : &ctx
->program
->info
->vs
.outinfo
;
9687 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9688 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9689 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9692 if (ctx
->options
->key
.has_multiview_view_index
) {
9693 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9694 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9697 /* the order these position exports are created is important */
9699 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9700 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9701 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9702 exported_pos
= true;
9704 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9705 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9706 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9707 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9709 if (ctx
->export_clip_dists
) {
9710 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9711 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9712 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9713 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9716 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9717 if (i
< VARYING_SLOT_VAR0
&&
9718 i
!= VARYING_SLOT_LAYER
&&
9719 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9720 i
!= VARYING_SLOT_VIEWPORT
)
9723 export_vs_varying(ctx
, i
, false, NULL
);
9727 create_null_export(ctx
);
9730 static bool export_fs_mrt_z(isel_context
*ctx
)
9732 Builder
bld(ctx
->program
, ctx
->block
);
9733 unsigned enabled_channels
= 0;
9737 for (unsigned i
= 0; i
< 4; ++i
) {
9738 values
[i
] = Operand(v1
);
9741 /* Both stencil and sample mask only need 16-bits. */
9742 if (!ctx
->program
->info
->ps
.writes_z
&&
9743 (ctx
->program
->info
->ps
.writes_stencil
||
9744 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9745 compr
= true; /* COMPR flag */
9747 if (ctx
->program
->info
->ps
.writes_stencil
) {
9748 /* Stencil should be in X[23:16]. */
9749 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9750 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9751 enabled_channels
|= 0x3;
9754 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9755 /* SampleMask should be in Y[15:0]. */
9756 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9757 enabled_channels
|= 0xc;
9760 if (ctx
->program
->info
->ps
.writes_z
) {
9761 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9762 enabled_channels
|= 0x1;
9765 if (ctx
->program
->info
->ps
.writes_stencil
) {
9766 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9767 enabled_channels
|= 0x2;
9770 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9771 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9772 enabled_channels
|= 0x4;
9776 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9777 * writemask component.
9779 if (ctx
->options
->chip_class
== GFX6
&&
9780 ctx
->options
->family
!= CHIP_OLAND
&&
9781 ctx
->options
->family
!= CHIP_HAINAN
) {
9782 enabled_channels
|= 0x1;
9785 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9786 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9791 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9793 Builder
bld(ctx
->program
, ctx
->block
);
9794 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9797 for (unsigned i
= 0; i
< 4; ++i
) {
9798 if (write_mask
& (1 << i
)) {
9799 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9801 values
[i
] = Operand(v1
);
9805 unsigned target
, col_format
;
9806 unsigned enabled_channels
= 0;
9807 aco_opcode compr_op
= (aco_opcode
)0;
9809 slot
-= FRAG_RESULT_DATA0
;
9810 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9811 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9813 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9814 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9818 case V_028714_SPI_SHADER_ZERO
:
9819 enabled_channels
= 0; /* writemask */
9820 target
= V_008DFC_SQ_EXP_NULL
;
9823 case V_028714_SPI_SHADER_32_R
:
9824 enabled_channels
= 1;
9827 case V_028714_SPI_SHADER_32_GR
:
9828 enabled_channels
= 0x3;
9831 case V_028714_SPI_SHADER_32_AR
:
9832 if (ctx
->options
->chip_class
>= GFX10
) {
9833 /* Special case: on GFX10, the outputs are different for 32_AR */
9834 enabled_channels
= 0x3;
9835 values
[1] = values
[3];
9836 values
[3] = Operand(v1
);
9838 enabled_channels
= 0x9;
9842 case V_028714_SPI_SHADER_FP16_ABGR
:
9843 enabled_channels
= 0x5;
9844 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9847 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9848 enabled_channels
= 0x5;
9849 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9852 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9853 enabled_channels
= 0x5;
9854 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9857 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9858 enabled_channels
= 0x5;
9859 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9860 if (is_int8
|| is_int10
) {
9862 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9863 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9865 for (unsigned i
= 0; i
< 4; i
++) {
9866 if ((write_mask
>> i
) & 1) {
9867 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9868 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9876 case V_028714_SPI_SHADER_SINT16_ABGR
:
9877 enabled_channels
= 0x5;
9878 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9879 if (is_int8
|| is_int10
) {
9881 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9882 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9883 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9884 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9886 for (unsigned i
= 0; i
< 4; i
++) {
9887 if ((write_mask
>> i
) & 1) {
9888 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9889 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9891 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9892 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9899 case V_028714_SPI_SHADER_32_ABGR
:
9900 enabled_channels
= 0xF;
9907 if (target
== V_008DFC_SQ_EXP_NULL
)
9910 if ((bool) compr_op
) {
9911 for (int i
= 0; i
< 2; i
++) {
9912 /* check if at least one of the values to be compressed is enabled */
9913 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9915 enabled_channels
|= enabled
<< (i
*2);
9916 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9917 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9918 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9920 values
[i
] = Operand(v1
);
9923 values
[2] = Operand(v1
);
9924 values
[3] = Operand(v1
);
9926 for (int i
= 0; i
< 4; i
++)
9927 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9930 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9931 enabled_channels
, target
, (bool) compr_op
);
9935 static void create_fs_exports(isel_context
*ctx
)
9937 bool exported
= false;
9939 /* Export depth, stencil and sample mask. */
9940 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9941 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9942 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9943 exported
|= export_fs_mrt_z(ctx
);
9945 /* Export all color render targets. */
9946 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9947 if (ctx
->outputs
.mask
[i
])
9948 exported
|= export_fs_mrt_color(ctx
, i
);
9951 create_null_export(ctx
);
9954 static void write_tcs_tess_factors(isel_context
*ctx
)
9956 unsigned outer_comps
;
9957 unsigned inner_comps
;
9959 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9976 Builder
bld(ctx
->program
, ctx
->block
);
9978 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9979 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9980 bld
.sopp(aco_opcode::s_barrier
);
9982 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9983 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9985 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9986 if_context ic_invocation_id_is_zero
;
9987 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9988 bld
.reset(ctx
->block
);
9990 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9992 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9993 unsigned stride
= inner_comps
+ outer_comps
;
9994 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9998 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10000 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10002 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10003 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10004 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10006 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10007 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10009 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10010 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10011 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10012 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10015 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10016 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10017 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10018 unsigned tf_const_offset
= 0;
10020 if (ctx
->program
->chip_class
<= GFX8
) {
10021 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10022 if_context ic_rel_patch_id_is_zero
;
10023 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10024 bld
.reset(ctx
->block
);
10026 /* Store the dynamic HS control word. */
10027 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10028 bld
.mubuf(aco_opcode::buffer_store_dword
,
10029 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10030 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10031 /* disable_wqm */ false, /* glc */ true);
10032 tf_const_offset
+= 4;
10034 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10035 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10036 bld
.reset(ctx
->block
);
10039 assert(stride
== 2 || stride
== 4 || stride
== 6);
10040 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10041 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10043 /* Store to offchip for TES to read - only if TES reads them */
10044 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10045 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10046 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10048 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10049 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10051 if (likely(inner_comps
)) {
10052 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10053 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10057 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10058 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10061 static void emit_stream_output(isel_context
*ctx
,
10062 Temp
const *so_buffers
,
10063 Temp
const *so_write_offset
,
10064 const struct radv_stream_output
*output
)
10066 unsigned num_comps
= util_bitcount(output
->component_mask
);
10067 unsigned writemask
= (1 << num_comps
) - 1;
10068 unsigned loc
= output
->location
;
10069 unsigned buf
= output
->buffer
;
10071 assert(num_comps
&& num_comps
<= 4);
10072 if (!num_comps
|| num_comps
> 4)
10075 unsigned start
= ffs(output
->component_mask
) - 1;
10078 bool all_undef
= true;
10079 assert(ctx
->stage
& hw_vs
);
10080 for (unsigned i
= 0; i
< num_comps
; i
++) {
10081 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10082 all_undef
= all_undef
&& !out
[i
].id();
10087 while (writemask
) {
10089 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10090 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10091 /* GFX6 doesn't support storing vec3, split it. */
10092 writemask
|= 1u << (start
+ 2);
10096 unsigned offset
= output
->offset
+ start
* 4;
10098 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10099 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10100 for (int i
= 0; i
< count
; ++i
)
10101 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10102 vec
->definitions
[0] = Definition(write_data
);
10103 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10108 opcode
= aco_opcode::buffer_store_dword
;
10111 opcode
= aco_opcode::buffer_store_dwordx2
;
10114 opcode
= aco_opcode::buffer_store_dwordx3
;
10117 opcode
= aco_opcode::buffer_store_dwordx4
;
10120 unreachable("Unsupported dword count.");
10123 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10124 store
->operands
[0] = Operand(so_buffers
[buf
]);
10125 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10126 store
->operands
[2] = Operand((uint32_t) 0);
10127 store
->operands
[3] = Operand(write_data
);
10128 if (offset
> 4095) {
10129 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10130 Builder
bld(ctx
->program
, ctx
->block
);
10131 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10133 store
->offset
= offset
;
10135 store
->offen
= true;
10137 store
->dlc
= false;
10139 store
->can_reorder
= true;
10140 ctx
->block
->instructions
.emplace_back(std::move(store
));
10144 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10146 Builder
bld(ctx
->program
, ctx
->block
);
10148 Temp so_buffers
[4];
10149 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10150 for (unsigned i
= 0; i
< 4; i
++) {
10151 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10155 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10156 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10159 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10160 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10162 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10164 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10167 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10169 bld
.reset(ctx
->block
);
10171 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10173 Temp so_write_offset
[4];
10175 for (unsigned i
= 0; i
< 4; i
++) {
10176 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10181 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10182 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10183 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10184 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10186 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10188 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10189 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10190 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10191 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10195 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10196 struct radv_stream_output
*output
=
10197 &ctx
->program
->info
->so
.outputs
[i
];
10198 if (stream
!= output
->stream
)
10201 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10204 begin_divergent_if_else(ctx
, &ic
);
10205 end_divergent_if(ctx
, &ic
);
10208 } /* end namespace */
10210 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10212 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10213 Builder
bld(ctx
->program
, ctx
->block
);
10214 constexpr unsigned hs_idx
= 1u;
10215 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10216 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10217 Operand((8u << 16) | (hs_idx
* 8u)));
10218 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10220 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10222 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10223 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10224 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10225 ls_has_nonzero_hs_threads
);
10226 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10227 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10228 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10229 ls_has_nonzero_hs_threads
);
10230 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10231 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10232 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10233 ls_has_nonzero_hs_threads
);
10235 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10236 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10237 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10240 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10242 /* Split all arguments except for the first (ring_offsets) and the last
10243 * (exec) so that the dead channels don't stay live throughout the program.
10245 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10246 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10247 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10248 startpgm
->definitions
[i
].regClass().size());
10253 void handle_bc_optimize(isel_context
*ctx
)
10255 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10256 Builder
bld(ctx
->program
, ctx
->block
);
10257 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10258 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10259 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10260 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10261 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10262 if (uses_center
&& uses_centroid
) {
10263 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10264 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10266 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10268 for (unsigned i
= 0; i
< 2; i
++) {
10269 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10270 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10271 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10272 persp_centroid
, persp_center
, sel
);
10274 ctx
->persp_centroid
= bld
.tmp(v2
);
10275 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10276 Operand(new_coord
[0]), Operand(new_coord
[1]));
10277 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10280 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10282 for (unsigned i
= 0; i
< 2; i
++) {
10283 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10284 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10285 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10286 linear_centroid
, linear_center
, sel
);
10288 ctx
->linear_centroid
= bld
.tmp(v2
);
10289 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10290 Operand(new_coord
[0]), Operand(new_coord
[1]));
10291 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10296 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10298 Program
*program
= ctx
->program
;
10300 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10302 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10303 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10304 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10305 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10306 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10308 program
->next_fp_mode
.must_flush_denorms32
=
10309 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10310 program
->next_fp_mode
.must_flush_denorms16_64
=
10311 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10312 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10314 program
->next_fp_mode
.care_about_round32
=
10315 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10317 program
->next_fp_mode
.care_about_round16_64
=
10318 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10319 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10321 /* default to preserving fp16 and fp64 denorms, since it's free */
10322 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10323 program
->next_fp_mode
.denorm16_64
= 0;
10325 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10327 /* preserving fp32 denorms is expensive, so only do it if asked */
10328 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10329 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10331 program
->next_fp_mode
.denorm32
= 0;
10333 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10334 program
->next_fp_mode
.round32
= fp_round_tz
;
10336 program
->next_fp_mode
.round32
= fp_round_ne
;
10338 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10339 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10341 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10343 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10346 void cleanup_cfg(Program
*program
)
10348 /* create linear_succs/logical_succs */
10349 for (Block
& BB
: program
->blocks
) {
10350 for (unsigned idx
: BB
.linear_preds
)
10351 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10352 for (unsigned idx
: BB
.logical_preds
)
10353 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10357 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10359 Builder
bld(ctx
->program
, ctx
->block
);
10361 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10362 Temp count
= i
== 0
10363 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10364 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10365 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10367 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10370 if (ctx
->program
->wave_size
== 64) {
10371 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10372 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10373 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10375 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10376 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10382 bool ngg_early_prim_export(isel_context
*ctx
)
10384 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10388 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10390 Builder
bld(ctx
->program
, ctx
->block
);
10392 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10393 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10395 /* Get the id of the current wave within the threadgroup (workgroup) */
10396 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10397 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10399 /* Execute the following code only on the first wave (wave id 0),
10400 * use the SCC def to tell if the wave id is zero or not.
10402 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10404 begin_uniform_if_then(ctx
, &ic
, cond
);
10405 begin_uniform_if_else(ctx
, &ic
);
10406 bld
.reset(ctx
->block
);
10408 /* Number of vertices output by VS/TES */
10409 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10410 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10411 /* Number of primitives output by VS/TES */
10412 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10413 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10415 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10416 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10417 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10419 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10420 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10422 end_uniform_if(ctx
, &ic
);
10424 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10425 bld
.reset(ctx
->block
);
10426 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10429 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10431 Builder
bld(ctx
->program
, ctx
->block
);
10433 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10434 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10437 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10440 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10441 assert(vtxindex
[i
].id());
10444 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10448 /* The initial edge flag is always false in tess eval shaders. */
10449 if (ctx
->stage
== ngg_vertex_gs
) {
10450 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10451 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10455 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10460 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10462 Builder
bld(ctx
->program
, ctx
->block
);
10463 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10465 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10466 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10467 false /* compressed */, true/* done */, false /* valid mask */);
10470 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10472 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10473 * These must always come before VS exports.
10475 * It is recommended to do these as early as possible. They can be at the beginning when
10476 * there is no SW GS and the shader doesn't write edge flags.
10480 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10481 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10483 Builder
bld(ctx
->program
, ctx
->block
);
10484 constexpr unsigned max_vertices_per_primitive
= 3;
10485 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10487 if (ctx
->stage
== ngg_vertex_gs
) {
10488 /* TODO: optimize for points & lines */
10489 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10490 if (ctx
->shader
->info
.tess
.point_mode
)
10491 num_vertices_per_primitive
= 1;
10492 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10493 num_vertices_per_primitive
= 2;
10495 unreachable("Unsupported NGG shader stage");
10498 Temp vtxindex
[max_vertices_per_primitive
];
10499 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10500 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10501 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10502 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10503 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10504 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10505 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10506 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10508 /* Export primitive data to the index buffer. */
10509 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10511 /* Export primitive ID. */
10512 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10513 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10514 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10515 Temp provoking_vtx_index
= vtxindex
[0];
10516 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10518 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10521 begin_divergent_if_else(ctx
, &ic
);
10522 end_divergent_if(ctx
, &ic
);
10525 void ngg_emit_nogs_output(isel_context
*ctx
)
10527 /* Emits NGG GS output, for stages that don't have SW GS. */
10530 Builder
bld(ctx
->program
, ctx
->block
);
10531 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10533 /* NGG streamout is currently disabled by default. */
10534 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10536 if (late_prim_export
) {
10537 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10538 create_export_phis(ctx
);
10539 /* Do what we need to do in the GS threads. */
10540 ngg_emit_nogs_gsthreads(ctx
);
10542 /* What comes next should be executed on ES threads. */
10543 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10544 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10545 bld
.reset(ctx
->block
);
10548 /* Export VS outputs */
10549 ctx
->block
->kind
|= block_kind_export_end
;
10550 create_vs_exports(ctx
);
10552 /* Export primitive ID */
10553 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10556 if (ctx
->stage
== ngg_vertex_gs
) {
10557 /* Wait for GS threads to store primitive ID in LDS. */
10558 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10559 bld
.sopp(aco_opcode::s_barrier
);
10561 /* Calculate LDS address where the GS threads stored the primitive ID. */
10562 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10563 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10564 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10565 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10566 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10567 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10569 /* Load primitive ID from LDS. */
10570 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10571 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10572 /* TES: Just use the patch ID as the primitive ID. */
10573 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10575 unreachable("unsupported NGG shader stage.");
10578 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10579 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10581 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10584 if (late_prim_export
) {
10585 begin_divergent_if_else(ctx
, &ic
);
10586 end_divergent_if(ctx
, &ic
);
10587 bld
.reset(ctx
->block
);
10591 void select_program(Program
*program
,
10592 unsigned shader_count
,
10593 struct nir_shader
*const *shaders
,
10594 ac_shader_config
* config
,
10595 struct radv_shader_args
*args
)
10597 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10598 if_context ic_merged_wave_info
;
10599 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10601 for (unsigned i
= 0; i
< shader_count
; i
++) {
10602 nir_shader
*nir
= shaders
[i
];
10603 init_context(&ctx
, nir
);
10605 setup_fp_mode(&ctx
, nir
);
10608 /* needs to be after init_context() for FS */
10609 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10610 append_logical_start(ctx
.block
);
10612 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10613 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10615 split_arguments(&ctx
, startpgm
);
10619 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10621 if (ngg_early_prim_export(&ctx
))
10622 ngg_emit_nogs_gsthreads(&ctx
);
10625 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10626 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10627 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10628 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10629 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10630 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10631 ctx
.stage
== tess_eval_geometry_gs
));
10633 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10634 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10635 if (check_merged_wave_info
) {
10636 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10637 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10641 Builder
bld(ctx
.program
, ctx
.block
);
10643 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10644 bld
.sopp(aco_opcode::s_barrier
);
10646 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10647 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10649 } else if (ctx
.stage
== geometry_gs
)
10650 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10652 if (ctx
.stage
== fragment_fs
)
10653 handle_bc_optimize(&ctx
);
10655 visit_cf_list(&ctx
, &func
->body
);
10657 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10658 emit_streamout(&ctx
, 0);
10660 if (ctx
.stage
& hw_vs
) {
10661 create_vs_exports(&ctx
);
10662 ctx
.block
->kind
|= block_kind_export_end
;
10663 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10664 ngg_emit_nogs_output(&ctx
);
10665 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10666 Builder
bld(ctx
.program
, ctx
.block
);
10667 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10668 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10669 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10670 write_tcs_tess_factors(&ctx
);
10673 if (ctx
.stage
== fragment_fs
) {
10674 create_fs_exports(&ctx
);
10675 ctx
.block
->kind
|= block_kind_export_end
;
10678 if (endif_merged_wave_info
) {
10679 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10680 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10683 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10684 ngg_emit_nogs_output(&ctx
);
10686 ralloc_free(ctx
.divergent_vals
);
10688 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10689 /* Outputs of the previous stage are inputs to the next stage */
10690 ctx
.inputs
= ctx
.outputs
;
10691 ctx
.outputs
= shader_io_state();
10695 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10697 append_logical_end(ctx
.block
);
10698 ctx
.block
->kind
|= block_kind_uniform
;
10699 Builder
bld(ctx
.program
, ctx
.block
);
10700 if (ctx
.program
->wb_smem_l1_on_end
)
10701 bld
.smem(aco_opcode::s_dcache_wb
, false);
10702 bld
.sopp(aco_opcode::s_endpgm
);
10704 cleanup_cfg(program
);
10707 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10708 ac_shader_config
* config
,
10709 struct radv_shader_args
*args
)
10711 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10713 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10714 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10715 program
->next_fp_mode
.must_flush_denorms32
= false;
10716 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10717 program
->next_fp_mode
.care_about_round32
= false;
10718 program
->next_fp_mode
.care_about_round16_64
= false;
10719 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10720 program
->next_fp_mode
.denorm32
= 0;
10721 program
->next_fp_mode
.round32
= fp_round_ne
;
10722 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10723 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10725 add_startpgm(&ctx
);
10726 append_logical_start(ctx
.block
);
10728 Builder
bld(ctx
.program
, ctx
.block
);
10730 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10732 Operand
stream_id(0u);
10733 if (args
->shader_info
->so
.num_outputs
)
10734 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10735 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10737 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10739 std::stack
<Block
> endif_blocks
;
10741 for (unsigned stream
= 0; stream
< 4; stream
++) {
10742 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10745 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10746 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10749 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10751 unsigned BB_if_idx
= ctx
.block
->index
;
10752 Block BB_endif
= Block();
10753 if (!stream_id
.isConstant()) {
10755 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10756 append_logical_end(ctx
.block
);
10757 ctx
.block
->kind
|= block_kind_uniform
;
10758 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10760 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10762 ctx
.block
= ctx
.program
->create_and_insert_block();
10763 add_edge(BB_if_idx
, ctx
.block
);
10764 bld
.reset(ctx
.block
);
10765 append_logical_start(ctx
.block
);
10768 unsigned offset
= 0;
10769 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10770 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10773 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10774 unsigned length
= util_last_bit(output_usage_mask
);
10775 for (unsigned j
= 0; j
< length
; ++j
) {
10776 if (!(output_usage_mask
& (1 << j
)))
10779 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10780 Temp voffset
= vtx_offset
;
10781 if (const_offset
>= 4096u) {
10782 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10783 const_offset
%= 4096u;
10786 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10787 mubuf
->definitions
[0] = bld
.def(v1
);
10788 mubuf
->operands
[0] = Operand(gsvs_ring
);
10789 mubuf
->operands
[1] = Operand(voffset
);
10790 mubuf
->operands
[2] = Operand(0u);
10791 mubuf
->offen
= true;
10792 mubuf
->offset
= const_offset
;
10795 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10796 mubuf
->barrier
= barrier_none
;
10797 mubuf
->can_reorder
= true;
10799 ctx
.outputs
.mask
[i
] |= 1 << j
;
10800 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10802 bld
.insert(std::move(mubuf
));
10808 if (args
->shader_info
->so
.num_outputs
) {
10809 emit_streamout(&ctx
, stream
);
10810 bld
.reset(ctx
.block
);
10814 create_vs_exports(&ctx
);
10815 ctx
.block
->kind
|= block_kind_export_end
;
10818 if (!stream_id
.isConstant()) {
10819 append_logical_end(ctx
.block
);
10821 /* branch from then block to endif block */
10822 bld
.branch(aco_opcode::p_branch
);
10823 add_edge(ctx
.block
->index
, &BB_endif
);
10824 ctx
.block
->kind
|= block_kind_uniform
;
10826 /* emit else block */
10827 ctx
.block
= ctx
.program
->create_and_insert_block();
10828 add_edge(BB_if_idx
, ctx
.block
);
10829 bld
.reset(ctx
.block
);
10830 append_logical_start(ctx
.block
);
10832 endif_blocks
.push(std::move(BB_endif
));
10836 while (!endif_blocks
.empty()) {
10837 Block BB_endif
= std::move(endif_blocks
.top());
10838 endif_blocks
.pop();
10840 Block
*BB_else
= ctx
.block
;
10842 append_logical_end(BB_else
);
10843 /* branch from else block to endif block */
10844 bld
.branch(aco_opcode::p_branch
);
10845 add_edge(BB_else
->index
, &BB_endif
);
10846 BB_else
->kind
|= block_kind_uniform
;
10848 /** emit endif merge block */
10849 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10850 bld
.reset(ctx
.block
);
10851 append_logical_start(ctx
.block
);
10854 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10856 append_logical_end(ctx
.block
);
10857 ctx
.block
->kind
|= block_kind_uniform
;
10858 bld
.sopp(aco_opcode::s_endpgm
);
10860 cleanup_cfg(program
);