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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 unreachable("Not implemented yet on GFX6-7"); /* TODO */
175 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
176 /* GFX10 wave64 mode: emulate full-wave bpermute */
177 if (!ctx
->has_gfx10_wave64_bpermute
) {
178 ctx
->has_gfx10_wave64_bpermute
= true;
179 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
180 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
183 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
184 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
185 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
186 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
187 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
188 Operand
input_data(data
);
190 index_x4
.setLateKill(true);
191 input_data
.setLateKill(true);
192 same_half
.setLateKill(true);
194 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
196 /* GFX8-9 or GFX10 wave32: bpermute works normally */
197 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
198 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
202 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
204 if (val
.type() == RegType::sgpr
) {
205 Builder
bld(ctx
->program
, ctx
->block
);
206 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
208 assert(val
.type() == RegType::vgpr
);
212 //assumes a != 0xffffffff
213 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
216 Builder
bld(ctx
->program
, ctx
->block
);
218 if (util_is_power_of_two_or_zero(b
)) {
219 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
223 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
225 assert(info
.multiplier
<= 0xffffffff);
227 bool pre_shift
= info
.pre_shift
!= 0;
228 bool increment
= info
.increment
!= 0;
229 bool multiply
= true;
230 bool post_shift
= info
.post_shift
!= 0;
232 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
233 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
237 Temp pre_shift_dst
= a
;
239 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
240 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
243 Temp increment_dst
= pre_shift_dst
;
245 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
246 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
249 Temp multiply_dst
= increment_dst
;
251 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
252 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
253 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
261 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
263 Builder
bld(ctx
->program
, ctx
->block
);
264 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
268 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
270 /* no need to extract the whole vector */
271 if (src
.regClass() == dst_rc
) {
276 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
277 Builder
bld(ctx
->program
, ctx
->block
);
278 auto it
= ctx
->allocated_vec
.find(src
.id());
279 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
280 if (it
->second
[idx
].regClass() == dst_rc
) {
281 return it
->second
[idx
];
283 assert(!dst_rc
.is_subdword());
284 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
285 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
289 if (dst_rc
.is_subdword())
290 src
= as_vgpr(ctx
, src
);
292 if (src
.bytes() == dst_rc
.bytes()) {
294 return bld
.copy(bld
.def(dst_rc
), src
);
296 Temp dst
= bld
.tmp(dst_rc
);
297 emit_extract_vector(ctx
, src
, idx
, dst
);
302 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
304 if (num_components
== 1)
306 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
309 if (num_components
> vec_src
.size()) {
310 if (vec_src
.type() == RegType::sgpr
) {
311 /* should still help get_alu_src() */
312 emit_split_vector(ctx
, vec_src
, vec_src
.size());
315 /* sub-dword split */
316 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
318 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
320 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
321 split
->operands
[0] = Operand(vec_src
);
322 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
323 for (unsigned i
= 0; i
< num_components
; i
++) {
324 elems
[i
] = {ctx
->program
->allocateId(), rc
};
325 split
->definitions
[i
] = Definition(elems
[i
]);
327 ctx
->block
->instructions
.emplace_back(std::move(split
));
328 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
331 /* This vector expansion uses a mask to determine which elements in the new vector
332 * come from the original vector. The other elements are undefined. */
333 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
335 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
340 Builder
bld(ctx
->program
, ctx
->block
);
341 if (num_components
== 1) {
342 if (dst
.type() == RegType::sgpr
)
343 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
345 bld
.copy(Definition(dst
), vec_src
);
349 unsigned component_size
= dst
.size() / num_components
;
350 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
352 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
353 vec
->definitions
[0] = Definition(dst
);
355 for (unsigned i
= 0; i
< num_components
; i
++) {
356 if (mask
& (1 << i
)) {
357 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
358 if (dst
.type() == RegType::sgpr
)
359 src
= bld
.as_uniform(src
);
360 vec
->operands
[i
] = Operand(src
);
362 vec
->operands
[i
] = Operand(0u);
364 elems
[i
] = vec
->operands
[i
].getTemp();
366 ctx
->block
->instructions
.emplace_back(std::move(vec
));
367 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
370 /* adjust misaligned small bit size loads */
371 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
373 Builder
bld(ctx
->program
, ctx
->block
);
375 Temp select
= Temp();
376 if (offset
.isConstant()) {
377 assert(offset
.constantValue() && offset
.constantValue() < 4);
378 shift
= Operand(offset
.constantValue() * 8);
380 /* bit_offset = 8 * (offset & 0x3) */
381 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
382 select
= bld
.tmp(s1
);
383 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
386 if (vec
.size() == 1) {
387 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
388 } else if (vec
.size() == 2) {
389 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
390 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
392 emit_split_vector(ctx
, dst
, 2);
394 emit_extract_vector(ctx
, tmp
, 0, dst
);
395 } else if (vec
.size() == 4) {
396 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
397 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
398 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
399 if (select
!= Temp())
400 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
401 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
402 Temp mid
= bld
.tmp(s1
);
403 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
404 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
405 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
406 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
407 emit_split_vector(ctx
, dst
, 2);
411 /* this function trims subdword vectors:
412 * if dst is vgpr - split the src and create a shrunk version according to the mask.
413 * if dst is sgpr - split the src, but move the original to sgpr. */
414 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
416 assert(vec_src
.type() == RegType::vgpr
);
417 emit_split_vector(ctx
, vec_src
, num_components
);
419 Builder
bld(ctx
->program
, ctx
->block
);
420 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
421 unsigned component_size
= vec_src
.bytes() / num_components
;
422 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
425 for (unsigned i
= 0; i
< num_components
; i
++) {
427 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
430 if (dst
.type() == RegType::vgpr
) {
431 assert(dst
.bytes() == k
* component_size
);
432 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
433 for (unsigned i
= 0; i
< k
; i
++)
434 vec
->operands
[i
] = Operand(elems
[i
]);
435 vec
->definitions
[0] = Definition(dst
);
436 bld
.insert(std::move(vec
));
438 // TODO: alignbyte if mask doesn't start with 1?
440 assert(dst
.size() == vec_src
.size());
441 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
443 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
446 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
448 Builder
bld(ctx
->program
, ctx
->block
);
450 dst
= bld
.tmp(bld
.lm
);
452 assert(val
.regClass() == s1
);
453 assert(dst
.regClass() == bld
.lm
);
455 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
458 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
460 Builder
bld(ctx
->program
, ctx
->block
);
464 assert(val
.regClass() == bld
.lm
);
465 assert(dst
.regClass() == s1
);
467 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
468 Temp tmp
= bld
.tmp(s1
);
469 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
470 return emit_wqm(ctx
, tmp
, dst
);
473 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
475 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
476 return get_ssa_temp(ctx
, src
.src
.ssa
);
478 if (src
.src
.ssa
->num_components
== size
) {
479 bool identity_swizzle
= true;
480 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
481 if (src
.swizzle
[i
] != i
)
482 identity_swizzle
= false;
484 if (identity_swizzle
)
485 return get_ssa_temp(ctx
, src
.src
.ssa
);
488 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
489 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
490 assert(elem_size
> 0);
491 assert(vec
.bytes() % elem_size
== 0);
493 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
494 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
496 unsigned swizzle
= src
.swizzle
[0];
497 if (vec
.size() > 1) {
498 assert(src
.src
.ssa
->bit_size
== 16);
499 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
500 swizzle
= swizzle
& 1;
505 Temp dst
{ctx
->program
->allocateId(), s1
};
506 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
507 bfe
->operands
[0] = Operand(vec
);
508 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
509 bfe
->definitions
[0] = Definition(dst
);
510 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
511 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
515 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
517 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
520 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
521 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
522 for (unsigned i
= 0; i
< size
; ++i
) {
523 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
524 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
526 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
527 vec_instr
->definitions
[0] = Definition(dst
);
528 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
529 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
534 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
538 Builder
bld(ctx
->program
, ctx
->block
);
539 if (ptr
.type() == RegType::vgpr
)
540 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
541 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
542 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
545 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
547 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
548 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
549 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
550 sop2
->definitions
[0] = Definition(dst
);
552 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
553 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
556 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
557 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
559 Builder
bld(ctx
->program
, ctx
->block
);
560 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
561 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
562 if (src1
.type() == RegType::sgpr
) {
563 if (commutative
&& src0
.type() == RegType::vgpr
) {
568 src1
= as_vgpr(ctx
, src1
);
572 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
573 assert(dst
.size() == 1);
574 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
575 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
577 bld
.vop2(op
, Definition(dst
), src0
, src1
);
581 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
582 bool flush_denorms
= false)
584 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
585 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
586 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
588 /* ensure that the instruction has at most 1 sgpr operand
589 * The optimizer will inline constants for us */
590 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
591 src0
= as_vgpr(ctx
, src0
);
592 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
593 src1
= as_vgpr(ctx
, src1
);
594 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
595 src2
= as_vgpr(ctx
, src2
);
597 Builder
bld(ctx
->program
, ctx
->block
);
598 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
599 assert(dst
.size() == 1);
600 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
601 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
603 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
607 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
609 Builder
bld(ctx
->program
, ctx
->block
);
610 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
613 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
615 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
616 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
617 assert(src0
.size() == src1
.size());
619 aco_ptr
<Instruction
> vopc
;
620 if (src1
.type() == RegType::sgpr
) {
621 if (src0
.type() == RegType::vgpr
) {
622 /* to swap the operands, we might also have to change the opcode */
624 case aco_opcode::v_cmp_lt_f16
:
625 op
= aco_opcode::v_cmp_gt_f16
;
627 case aco_opcode::v_cmp_ge_f16
:
628 op
= aco_opcode::v_cmp_le_f16
;
630 case aco_opcode::v_cmp_lt_i16
:
631 op
= aco_opcode::v_cmp_gt_i16
;
633 case aco_opcode::v_cmp_ge_i16
:
634 op
= aco_opcode::v_cmp_le_i16
;
636 case aco_opcode::v_cmp_lt_u16
:
637 op
= aco_opcode::v_cmp_gt_u16
;
639 case aco_opcode::v_cmp_ge_u16
:
640 op
= aco_opcode::v_cmp_le_u16
;
642 case aco_opcode::v_cmp_lt_f32
:
643 op
= aco_opcode::v_cmp_gt_f32
;
645 case aco_opcode::v_cmp_ge_f32
:
646 op
= aco_opcode::v_cmp_le_f32
;
648 case aco_opcode::v_cmp_lt_i32
:
649 op
= aco_opcode::v_cmp_gt_i32
;
651 case aco_opcode::v_cmp_ge_i32
:
652 op
= aco_opcode::v_cmp_le_i32
;
654 case aco_opcode::v_cmp_lt_u32
:
655 op
= aco_opcode::v_cmp_gt_u32
;
657 case aco_opcode::v_cmp_ge_u32
:
658 op
= aco_opcode::v_cmp_le_u32
;
660 case aco_opcode::v_cmp_lt_f64
:
661 op
= aco_opcode::v_cmp_gt_f64
;
663 case aco_opcode::v_cmp_ge_f64
:
664 op
= aco_opcode::v_cmp_le_f64
;
666 case aco_opcode::v_cmp_lt_i64
:
667 op
= aco_opcode::v_cmp_gt_i64
;
669 case aco_opcode::v_cmp_ge_i64
:
670 op
= aco_opcode::v_cmp_le_i64
;
672 case aco_opcode::v_cmp_lt_u64
:
673 op
= aco_opcode::v_cmp_gt_u64
;
675 case aco_opcode::v_cmp_ge_u64
:
676 op
= aco_opcode::v_cmp_le_u64
;
678 default: /* eq and ne are commutative */
685 src1
= as_vgpr(ctx
, src1
);
689 Builder
bld(ctx
->program
, ctx
->block
);
690 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
693 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
695 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
696 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
697 Builder
bld(ctx
->program
, ctx
->block
);
699 assert(dst
.regClass() == bld
.lm
);
700 assert(src0
.type() == RegType::sgpr
);
701 assert(src1
.type() == RegType::sgpr
);
702 assert(src0
.regClass() == src1
.regClass());
704 /* Emit the SALU comparison instruction */
705 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
706 /* Turn the result into a per-lane bool */
707 bool_to_vector_condition(ctx
, cmp
, dst
);
710 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
711 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
713 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
714 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
715 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
716 nir_dest_is_divergent(instr
->dest
.dest
) ||
717 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
718 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
719 aco_opcode op
= use_valu
? v_op
: s_op
;
720 assert(op
!= aco_opcode::num_opcodes
);
721 assert(dst
.regClass() == ctx
->program
->lane_mask
);
724 emit_vopc_instruction(ctx
, instr
, op
, dst
);
726 emit_sopc_instruction(ctx
, instr
, op
, dst
);
729 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
731 Builder
bld(ctx
->program
, ctx
->block
);
732 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
733 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
735 assert(dst
.regClass() == bld
.lm
);
736 assert(src0
.regClass() == bld
.lm
);
737 assert(src1
.regClass() == bld
.lm
);
739 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
742 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
744 Builder
bld(ctx
->program
, ctx
->block
);
745 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
746 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
747 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
749 assert(cond
.regClass() == bld
.lm
);
751 if (dst
.type() == RegType::vgpr
) {
752 aco_ptr
<Instruction
> bcsel
;
753 if (dst
.size() == 1) {
754 then
= as_vgpr(ctx
, then
);
755 els
= as_vgpr(ctx
, els
);
757 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
758 } else if (dst
.size() == 2) {
759 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
760 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
761 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
762 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
764 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
765 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
767 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
769 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
770 nir_print_instr(&instr
->instr
, stderr
);
771 fprintf(stderr
, "\n");
776 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
777 assert(dst
.regClass() == bld
.lm
);
778 assert(then
.regClass() == bld
.lm
);
779 assert(els
.regClass() == bld
.lm
);
782 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
783 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
784 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
785 assert(dst
.size() == then
.size());
786 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
787 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
789 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
790 nir_print_instr(&instr
->instr
, stderr
);
791 fprintf(stderr
, "\n");
796 /* divergent boolean bcsel
797 * this implements bcsel on bools: dst = s0 ? s1 : s2
798 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
799 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
801 if (cond
.id() != then
.id())
802 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
804 if (cond
.id() == els
.id())
805 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
807 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
808 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
811 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
812 aco_opcode op
, uint32_t undo
)
814 /* multiply by 16777216 to handle denormals */
815 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
816 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
817 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
818 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
819 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
821 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
823 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
826 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
828 if (ctx
->block
->fp_mode
.denorm32
== 0) {
829 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
833 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
836 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
838 if (ctx
->block
->fp_mode
.denorm32
== 0) {
839 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
843 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
846 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
848 if (ctx
->block
->fp_mode
.denorm32
== 0) {
849 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
853 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
856 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
858 if (ctx
->block
->fp_mode
.denorm32
== 0) {
859 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
863 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
866 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
868 if (ctx
->options
->chip_class
>= GFX7
)
869 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
871 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
872 /* TODO: create more efficient code! */
873 if (val
.type() == RegType::sgpr
)
874 val
= as_vgpr(ctx
, val
);
876 /* Split the input value. */
877 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
880 /* Extract the exponent and compute the unbiased value. */
881 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
882 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
884 /* Extract the fractional part. */
885 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
886 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
888 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
889 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
891 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
892 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
893 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
894 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
895 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
897 /* Get the sign bit. */
898 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
900 /* Decide the operation to apply depending on the unbiased exponent. */
901 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
902 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
903 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
904 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
905 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
906 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
908 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
911 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
913 if (ctx
->options
->chip_class
>= GFX7
)
914 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
916 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
917 Temp src0
= as_vgpr(ctx
, val
);
919 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
920 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
922 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
923 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
924 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
926 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
927 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
928 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
929 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
931 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
932 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
934 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
936 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
937 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
939 return add
->definitions
[0].getTemp();
942 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
944 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
945 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
947 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
950 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
951 return bld
.copy(Definition(dst
), src
);
952 else if (dst
.bytes() < src
.bytes())
953 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
957 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
960 } else if (src
.regClass() == s1
) {
962 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
964 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
966 assert(src_bits
!= 8 || src
.regClass() == v1b
);
967 assert(src_bits
!= 16 || src
.regClass() == v2b
);
968 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
969 sdwa
->operands
[0] = Operand(src
);
970 sdwa
->definitions
[0] = Definition(tmp
);
972 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
974 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
975 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
976 bld
.insert(std::move(sdwa
));
979 if (dst_bits
== 64) {
980 if (is_signed
&& dst
.regClass() == s2
) {
981 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
982 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
983 } else if (is_signed
&& dst
.regClass() == v2
) {
984 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
987 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
994 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
996 if (!instr
->dest
.dest
.is_ssa
) {
997 fprintf(stderr
, "nir alu dst not in ssa: ");
998 nir_print_instr(&instr
->instr
, stderr
);
999 fprintf(stderr
, "\n");
1002 Builder
bld(ctx
->program
, ctx
->block
);
1003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1008 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1009 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1010 for (unsigned i
= 0; i
< num
; ++i
)
1011 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1013 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1014 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1015 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1016 for (unsigned i
= 0; i
< num
; ++i
) {
1017 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1018 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1020 vec
->operands
[i
] = Operand
{elems
[i
]};
1022 vec
->definitions
[0] = Definition(dst
);
1023 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1024 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1026 // TODO: that is a bit suboptimal..
1027 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1028 for (unsigned i
= 0; i
< num
- 1; ++i
)
1029 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1030 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1031 for (unsigned i
= 0; i
< num
; ++i
) {
1032 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1033 if (bit
% 32 == 0) {
1034 elems
[bit
/ 32] = elems
[i
];
1036 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1037 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1038 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1041 if (dst
.size() == 1)
1042 bld
.copy(Definition(dst
), elems
[0]);
1044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1049 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1050 aco_ptr
<Instruction
> mov
;
1051 if (dst
.type() == RegType::sgpr
) {
1052 if (src
.type() == RegType::vgpr
)
1053 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1054 else if (src
.regClass() == s1
)
1055 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1056 else if (src
.regClass() == s2
)
1057 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1059 unreachable("wrong src register class for nir_op_imov");
1061 if (dst
.regClass() == v1
)
1062 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1063 else if (dst
.regClass() == v1b
||
1064 dst
.regClass() == v2b
||
1065 dst
.regClass() == v2
)
1066 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1068 unreachable("wrong src register class for nir_op_imov");
1073 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1074 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1075 assert(src
.regClass() == bld
.lm
);
1076 assert(dst
.regClass() == bld
.lm
);
1077 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1078 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1079 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1080 } else if (dst
.regClass() == v1
) {
1081 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1082 } else if (dst
.type() == RegType::sgpr
) {
1083 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1084 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1086 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1087 nir_print_instr(&instr
->instr
, stderr
);
1088 fprintf(stderr
, "\n");
1093 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1094 if (dst
.regClass() == v1
) {
1095 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1096 } else if (dst
.regClass() == s1
) {
1097 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1098 } else if (dst
.size() == 2) {
1099 Temp src0
= bld
.tmp(dst
.type(), 1);
1100 Temp src1
= bld
.tmp(dst
.type(), 1);
1101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1103 if (dst
.regClass() == s2
) {
1104 Temp carry
= bld
.tmp(s1
);
1105 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1106 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1107 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1109 Temp lower
= bld
.tmp(v1
);
1110 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1111 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1112 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1115 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1116 nir_print_instr(&instr
->instr
, stderr
);
1117 fprintf(stderr
, "\n");
1122 if (dst
.regClass() == s1
) {
1123 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1124 } else if (dst
.regClass() == v1
) {
1125 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1126 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1128 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1129 nir_print_instr(&instr
->instr
, stderr
);
1130 fprintf(stderr
, "\n");
1134 case nir_op_isign
: {
1135 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1136 if (dst
.regClass() == s1
) {
1137 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1138 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1139 } else if (dst
.regClass() == s2
) {
1140 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1142 if (ctx
->program
->chip_class
>= GFX8
)
1143 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1145 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1146 /* SCC gets zero-extended to 64 bit */
1147 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1148 } else if (dst
.regClass() == v1
) {
1149 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1150 } else if (dst
.regClass() == v2
) {
1151 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1152 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1153 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1154 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1155 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1156 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1158 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1159 nir_print_instr(&instr
->instr
, stderr
);
1160 fprintf(stderr
, "\n");
1165 if (dst
.regClass() == v1
) {
1166 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1167 } else if (dst
.regClass() == s1
) {
1168 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1170 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1171 nir_print_instr(&instr
->instr
, stderr
);
1172 fprintf(stderr
, "\n");
1177 if (dst
.regClass() == v1
) {
1178 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1179 } else if (dst
.regClass() == s1
) {
1180 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1182 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1183 nir_print_instr(&instr
->instr
, stderr
);
1184 fprintf(stderr
, "\n");
1189 if (dst
.regClass() == v1
) {
1190 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1191 } else if (dst
.regClass() == s1
) {
1192 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1194 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1195 nir_print_instr(&instr
->instr
, stderr
);
1196 fprintf(stderr
, "\n");
1201 if (dst
.regClass() == v1
) {
1202 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1203 } else if (dst
.regClass() == s1
) {
1204 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1206 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1207 nir_print_instr(&instr
->instr
, stderr
);
1208 fprintf(stderr
, "\n");
1213 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1214 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1215 } else if (dst
.regClass() == v1
) {
1216 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1217 } else if (dst
.regClass() == s1
) {
1218 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1219 } else if (dst
.regClass() == s2
) {
1220 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1222 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1223 nir_print_instr(&instr
->instr
, stderr
);
1224 fprintf(stderr
, "\n");
1229 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1230 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1231 } else if (dst
.regClass() == v1
) {
1232 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1233 } else if (dst
.regClass() == s1
) {
1234 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1235 } else if (dst
.regClass() == s2
) {
1236 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1238 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1239 nir_print_instr(&instr
->instr
, stderr
);
1240 fprintf(stderr
, "\n");
1245 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1246 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1247 } else if (dst
.regClass() == v1
) {
1248 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1249 } else if (dst
.regClass() == s1
) {
1250 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1251 } else if (dst
.regClass() == s2
) {
1252 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1254 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1255 nir_print_instr(&instr
->instr
, stderr
);
1256 fprintf(stderr
, "\n");
1261 if (dst
.regClass() == v1
) {
1262 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1263 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1264 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1265 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1266 } else if (dst
.regClass() == v2
) {
1267 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1268 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1269 } else if (dst
.regClass() == s2
) {
1270 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1271 } else if (dst
.regClass() == s1
) {
1272 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1274 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1275 nir_print_instr(&instr
->instr
, stderr
);
1276 fprintf(stderr
, "\n");
1281 if (dst
.regClass() == v1
) {
1282 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1283 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1284 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1285 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1286 } else if (dst
.regClass() == v2
) {
1287 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1288 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1289 } else if (dst
.regClass() == s1
) {
1290 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1291 } else if (dst
.regClass() == s2
) {
1292 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1294 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1295 nir_print_instr(&instr
->instr
, stderr
);
1296 fprintf(stderr
, "\n");
1301 if (dst
.regClass() == v1
) {
1302 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1303 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1304 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1305 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1306 } else if (dst
.regClass() == v2
) {
1307 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1308 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1309 } else if (dst
.regClass() == s1
) {
1310 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1311 } else if (dst
.regClass() == s2
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1314 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1315 nir_print_instr(&instr
->instr
, stderr
);
1316 fprintf(stderr
, "\n");
1320 case nir_op_find_lsb
: {
1321 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1322 if (src
.regClass() == s1
) {
1323 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1324 } else if (src
.regClass() == v1
) {
1325 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1326 } else if (src
.regClass() == s2
) {
1327 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1329 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1330 nir_print_instr(&instr
->instr
, stderr
);
1331 fprintf(stderr
, "\n");
1335 case nir_op_ufind_msb
:
1336 case nir_op_ifind_msb
: {
1337 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1338 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1339 aco_opcode op
= src
.regClass() == s2
?
1340 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1341 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1342 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1344 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1345 Operand(src
.size() * 32u - 1u), msb_rev
);
1346 Temp msb
= sub
.def(0).getTemp();
1347 Temp carry
= sub
.def(1).getTemp();
1349 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1350 } else if (src
.regClass() == v1
) {
1351 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1352 Temp msb_rev
= bld
.tmp(v1
);
1353 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1354 Temp msb
= bld
.tmp(v1
);
1355 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1356 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1358 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1359 nir_print_instr(&instr
->instr
, stderr
);
1360 fprintf(stderr
, "\n");
1364 case nir_op_bitfield_reverse
: {
1365 if (dst
.regClass() == s1
) {
1366 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1367 } else if (dst
.regClass() == v1
) {
1368 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1377 if (dst
.regClass() == s1
) {
1378 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1382 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1383 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1384 if (dst
.regClass() == v1
) {
1385 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1389 assert(src0
.size() == 2 && src1
.size() == 2);
1390 Temp src00
= bld
.tmp(src0
.type(), 1);
1391 Temp src01
= bld
.tmp(dst
.type(), 1);
1392 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1393 Temp src10
= bld
.tmp(src1
.type(), 1);
1394 Temp src11
= bld
.tmp(dst
.type(), 1);
1395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1397 if (dst
.regClass() == s2
) {
1398 Temp carry
= bld
.tmp(s1
);
1399 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1400 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1401 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1402 } else if (dst
.regClass() == v2
) {
1403 Temp dst0
= bld
.tmp(v1
);
1404 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1405 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1406 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1408 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1409 nir_print_instr(&instr
->instr
, stderr
);
1410 fprintf(stderr
, "\n");
1414 case nir_op_uadd_sat
: {
1415 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1416 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1417 if (dst
.regClass() == s1
) {
1418 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1419 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1421 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1422 } else if (dst
.regClass() == v1
) {
1423 if (ctx
->options
->chip_class
>= GFX9
) {
1424 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1425 add
->operands
[0] = Operand(src0
);
1426 add
->operands
[1] = Operand(src1
);
1427 add
->definitions
[0] = Definition(dst
);
1429 ctx
->block
->instructions
.emplace_back(std::move(add
));
1431 if (src1
.regClass() != v1
)
1432 std::swap(src0
, src1
);
1433 assert(src1
.regClass() == v1
);
1434 Temp tmp
= bld
.tmp(v1
);
1435 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1436 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1439 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1440 nir_print_instr(&instr
->instr
, stderr
);
1441 fprintf(stderr
, "\n");
1445 case nir_op_uadd_carry
: {
1446 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1447 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1448 if (dst
.regClass() == s1
) {
1449 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1452 if (dst
.regClass() == v1
) {
1453 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1454 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1458 Temp src00
= bld
.tmp(src0
.type(), 1);
1459 Temp src01
= bld
.tmp(dst
.type(), 1);
1460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1461 Temp src10
= bld
.tmp(src1
.type(), 1);
1462 Temp src11
= bld
.tmp(dst
.type(), 1);
1463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1464 if (dst
.regClass() == s2
) {
1465 Temp carry
= bld
.tmp(s1
);
1466 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1467 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1468 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1469 } else if (dst
.regClass() == v2
) {
1470 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1471 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1472 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1475 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1476 nir_print_instr(&instr
->instr
, stderr
);
1477 fprintf(stderr
, "\n");
1482 if (dst
.regClass() == s1
) {
1483 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1487 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1488 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1489 if (dst
.regClass() == v1
) {
1490 bld
.vsub32(Definition(dst
), src0
, src1
);
1494 Temp src00
= bld
.tmp(src0
.type(), 1);
1495 Temp src01
= bld
.tmp(dst
.type(), 1);
1496 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1497 Temp src10
= bld
.tmp(src1
.type(), 1);
1498 Temp src11
= bld
.tmp(dst
.type(), 1);
1499 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1500 if (dst
.regClass() == s2
) {
1501 Temp carry
= bld
.tmp(s1
);
1502 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1503 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1504 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1505 } else if (dst
.regClass() == v2
) {
1506 Temp lower
= bld
.tmp(v1
);
1507 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1508 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1509 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1511 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1512 nir_print_instr(&instr
->instr
, stderr
);
1513 fprintf(stderr
, "\n");
1517 case nir_op_usub_borrow
: {
1518 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1519 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1520 if (dst
.regClass() == s1
) {
1521 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1523 } else if (dst
.regClass() == v1
) {
1524 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1525 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1529 Temp src00
= bld
.tmp(src0
.type(), 1);
1530 Temp src01
= bld
.tmp(dst
.type(), 1);
1531 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1532 Temp src10
= bld
.tmp(src1
.type(), 1);
1533 Temp src11
= bld
.tmp(dst
.type(), 1);
1534 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1535 if (dst
.regClass() == s2
) {
1536 Temp borrow
= bld
.tmp(s1
);
1537 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1538 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1539 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1540 } else if (dst
.regClass() == v2
) {
1541 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1542 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1543 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 if (dst
.regClass() == v1
) {
1554 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1555 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1556 } else if (dst
.regClass() == s1
) {
1557 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1560 nir_print_instr(&instr
->instr
, stderr
);
1561 fprintf(stderr
, "\n");
1565 case nir_op_umul_high
: {
1566 if (dst
.regClass() == v1
) {
1567 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1568 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1569 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1570 } else if (dst
.regClass() == s1
) {
1571 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1572 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1573 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1575 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1576 nir_print_instr(&instr
->instr
, stderr
);
1577 fprintf(stderr
, "\n");
1581 case nir_op_imul_high
: {
1582 if (dst
.regClass() == v1
) {
1583 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1584 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1585 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1586 } else if (dst
.regClass() == s1
) {
1587 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1588 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1589 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1591 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1592 nir_print_instr(&instr
->instr
, stderr
);
1593 fprintf(stderr
, "\n");
1598 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1599 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1600 if (dst
.regClass() == v2b
) {
1601 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1602 } else if (dst
.regClass() == v1
) {
1603 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1604 } else if (dst
.regClass() == v2
) {
1605 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1607 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1608 nir_print_instr(&instr
->instr
, stderr
);
1609 fprintf(stderr
, "\n");
1614 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1615 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1616 if (dst
.regClass() == v2b
) {
1617 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1618 } else if (dst
.regClass() == v1
) {
1619 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1620 } else if (dst
.regClass() == v2
) {
1621 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1623 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1624 nir_print_instr(&instr
->instr
, stderr
);
1625 fprintf(stderr
, "\n");
1630 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1631 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1632 if (dst
.regClass() == v2b
) {
1633 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1634 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1636 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1637 } else if (dst
.regClass() == v1
) {
1638 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1639 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1641 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1642 } else if (dst
.regClass() == v2
) {
1643 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1644 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1645 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1648 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1649 nir_print_instr(&instr
->instr
, stderr
);
1650 fprintf(stderr
, "\n");
1655 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1656 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1657 if (dst
.regClass() == v2b
) {
1658 // TODO: check fp_mode.must_flush_denorms16_64
1659 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1660 } else if (dst
.regClass() == v1
) {
1661 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1662 } else if (dst
.regClass() == v2
) {
1663 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1664 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1665 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1667 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1670 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1671 nir_print_instr(&instr
->instr
, stderr
);
1672 fprintf(stderr
, "\n");
1677 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1678 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1679 if (dst
.regClass() == v2b
) {
1680 // TODO: check fp_mode.must_flush_denorms16_64
1681 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1682 } else if (dst
.regClass() == v1
) {
1683 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1684 } else if (dst
.regClass() == v2
) {
1685 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1686 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1687 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1689 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1692 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1693 nir_print_instr(&instr
->instr
, stderr
);
1694 fprintf(stderr
, "\n");
1698 case nir_op_fmax3
: {
1699 if (dst
.regClass() == v2b
) {
1700 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1701 } else if (dst
.regClass() == v1
) {
1702 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1704 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1705 nir_print_instr(&instr
->instr
, stderr
);
1706 fprintf(stderr
, "\n");
1710 case nir_op_fmin3
: {
1711 if (dst
.regClass() == v2b
) {
1712 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1713 } else if (dst
.regClass() == v1
) {
1714 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1716 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1717 nir_print_instr(&instr
->instr
, stderr
);
1718 fprintf(stderr
, "\n");
1722 case nir_op_fmed3
: {
1723 if (dst
.regClass() == v2b
) {
1724 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1725 } else if (dst
.regClass() == v1
) {
1726 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1728 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1729 nir_print_instr(&instr
->instr
, stderr
);
1730 fprintf(stderr
, "\n");
1734 case nir_op_umax3
: {
1735 if (dst
.size() == 1) {
1736 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1739 nir_print_instr(&instr
->instr
, stderr
);
1740 fprintf(stderr
, "\n");
1744 case nir_op_umin3
: {
1745 if (dst
.size() == 1) {
1746 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1748 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1749 nir_print_instr(&instr
->instr
, stderr
);
1750 fprintf(stderr
, "\n");
1754 case nir_op_umed3
: {
1755 if (dst
.size() == 1) {
1756 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1758 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1759 nir_print_instr(&instr
->instr
, stderr
);
1760 fprintf(stderr
, "\n");
1764 case nir_op_imax3
: {
1765 if (dst
.size() == 1) {
1766 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1769 nir_print_instr(&instr
->instr
, stderr
);
1770 fprintf(stderr
, "\n");
1774 case nir_op_imin3
: {
1775 if (dst
.size() == 1) {
1776 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1778 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1779 nir_print_instr(&instr
->instr
, stderr
);
1780 fprintf(stderr
, "\n");
1784 case nir_op_imed3
: {
1785 if (dst
.size() == 1) {
1786 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1788 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1789 nir_print_instr(&instr
->instr
, stderr
);
1790 fprintf(stderr
, "\n");
1794 case nir_op_cube_face_coord
: {
1795 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1796 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1797 emit_extract_vector(ctx
, in
, 1, v1
),
1798 emit_extract_vector(ctx
, in
, 2, v1
) };
1799 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1800 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1801 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1802 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1803 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1804 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1805 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1808 case nir_op_cube_face_index
: {
1809 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1810 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1811 emit_extract_vector(ctx
, in
, 1, v1
),
1812 emit_extract_vector(ctx
, in
, 2, v1
) };
1813 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1816 case nir_op_bcsel
: {
1817 emit_bcsel(ctx
, instr
, dst
);
1821 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1822 if (dst
.regClass() == v2b
) {
1823 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1824 } else if (dst
.regClass() == v1
) {
1825 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1826 } else if (dst
.regClass() == v2
) {
1827 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1829 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1830 nir_print_instr(&instr
->instr
, stderr
);
1831 fprintf(stderr
, "\n");
1836 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1837 if (dst
.regClass() == v2b
) {
1838 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1839 } else if (dst
.regClass() == v1
) {
1840 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1841 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1842 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1843 } else if (dst
.regClass() == v2
) {
1844 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1845 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1846 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1847 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1848 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1849 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1852 nir_print_instr(&instr
->instr
, stderr
);
1853 fprintf(stderr
, "\n");
1858 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1859 if (dst
.regClass() == v2b
) {
1860 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1861 } else if (dst
.regClass() == v1
) {
1862 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1863 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1864 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1865 } else if (dst
.regClass() == v2
) {
1866 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1867 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1868 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1869 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1870 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1871 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1873 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1874 nir_print_instr(&instr
->instr
, stderr
);
1875 fprintf(stderr
, "\n");
1880 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1881 if (dst
.regClass() == v2b
) {
1882 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1883 } else if (dst
.regClass() == v1
) {
1884 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1885 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1886 // TODO: confirm that this holds under any circumstances
1887 } else if (dst
.regClass() == v2
) {
1888 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1889 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1892 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1893 nir_print_instr(&instr
->instr
, stderr
);
1894 fprintf(stderr
, "\n");
1898 case nir_op_flog2
: {
1899 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1900 if (dst
.regClass() == v2b
) {
1901 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1902 } else if (dst
.regClass() == v1
) {
1903 emit_log2(ctx
, bld
, Definition(dst
), src
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1912 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1913 if (dst
.regClass() == v2b
) {
1914 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1915 } else if (dst
.regClass() == v1
) {
1916 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1917 } else if (dst
.regClass() == v2
) {
1918 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1920 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1921 nir_print_instr(&instr
->instr
, stderr
);
1922 fprintf(stderr
, "\n");
1926 case nir_op_fexp2
: {
1927 if (dst
.regClass() == v2b
) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1929 } else if (dst
.regClass() == v1
) {
1930 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1932 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1933 nir_print_instr(&instr
->instr
, stderr
);
1934 fprintf(stderr
, "\n");
1938 case nir_op_fsqrt
: {
1939 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1940 if (dst
.regClass() == v2b
) {
1941 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1942 } else if (dst
.regClass() == v1
) {
1943 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1944 } else if (dst
.regClass() == v2
) {
1945 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1947 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1948 nir_print_instr(&instr
->instr
, stderr
);
1949 fprintf(stderr
, "\n");
1953 case nir_op_ffract
: {
1954 if (dst
.regClass() == v2b
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1956 } else if (dst
.regClass() == v1
) {
1957 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1958 } else if (dst
.regClass() == v2
) {
1959 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1961 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1962 nir_print_instr(&instr
->instr
, stderr
);
1963 fprintf(stderr
, "\n");
1967 case nir_op_ffloor
: {
1968 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1969 if (dst
.regClass() == v2b
) {
1970 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1971 } else if (dst
.regClass() == v1
) {
1972 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1973 } else if (dst
.regClass() == v2
) {
1974 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1976 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1977 nir_print_instr(&instr
->instr
, stderr
);
1978 fprintf(stderr
, "\n");
1982 case nir_op_fceil
: {
1983 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1984 if (dst
.regClass() == v2b
) {
1985 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1986 } else if (dst
.regClass() == v1
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1988 } else if (dst
.regClass() == v2
) {
1989 if (ctx
->options
->chip_class
>= GFX7
) {
1990 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1992 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1993 /* trunc = trunc(src0)
1994 * if (src0 > 0.0 && src0 != trunc)
1997 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1998 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1999 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2000 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2001 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2002 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2003 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_ftrunc
: {
2013 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2016 } else if (dst
.regClass() == v1
) {
2017 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2018 } else if (dst
.regClass() == v2
) {
2019 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2021 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2022 nir_print_instr(&instr
->instr
, stderr
);
2023 fprintf(stderr
, "\n");
2027 case nir_op_fround_even
: {
2028 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2029 if (dst
.regClass() == v2b
) {
2030 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2031 } else if (dst
.regClass() == v1
) {
2032 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2033 } else if (dst
.regClass() == v2
) {
2034 if (ctx
->options
->chip_class
>= GFX7
) {
2035 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2037 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2038 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2039 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2041 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2042 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2043 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2044 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2045 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2046 tmp
= sub
->definitions
[0].getTemp();
2048 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2049 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2050 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2051 Temp cond
= vop3
->definitions
[0].getTemp();
2053 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2054 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2055 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2056 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2058 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2061 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2062 nir_print_instr(&instr
->instr
, stderr
);
2063 fprintf(stderr
, "\n");
2069 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2070 aco_ptr
<Instruction
> norm
;
2071 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2072 if (dst
.regClass() == v2b
) {
2073 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2074 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2075 bld
.vop1(opcode
, Definition(dst
), tmp
);
2076 } else if (dst
.regClass() == v1
) {
2077 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2079 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2080 if (ctx
->options
->chip_class
< GFX9
)
2081 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2083 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2084 bld
.vop1(opcode
, Definition(dst
), tmp
);
2086 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2087 nir_print_instr(&instr
->instr
, stderr
);
2088 fprintf(stderr
, "\n");
2092 case nir_op_ldexp
: {
2093 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2094 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2095 if (dst
.regClass() == v2b
) {
2096 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2097 } else if (dst
.regClass() == v1
) {
2098 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2099 } else if (dst
.regClass() == v2
) {
2100 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2102 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2103 nir_print_instr(&instr
->instr
, stderr
);
2104 fprintf(stderr
, "\n");
2108 case nir_op_frexp_sig
: {
2109 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2110 if (dst
.regClass() == v2b
) {
2111 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2112 } else if (dst
.regClass() == v1
) {
2113 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2114 } else if (dst
.regClass() == v2
) {
2115 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2117 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2118 nir_print_instr(&instr
->instr
, stderr
);
2119 fprintf(stderr
, "\n");
2123 case nir_op_frexp_exp
: {
2124 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2125 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2126 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2127 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2128 convert_int(bld
, tmp
, 8, 32, true, dst
);
2129 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2130 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2131 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2132 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2134 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2135 nir_print_instr(&instr
->instr
, stderr
);
2136 fprintf(stderr
, "\n");
2140 case nir_op_fsign
: {
2141 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2142 if (dst
.regClass() == v2b
) {
2143 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2144 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2145 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2147 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2148 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2149 } else if (dst
.regClass() == v1
) {
2150 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2151 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2152 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2153 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2154 } else if (dst
.regClass() == v2
) {
2155 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2156 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2157 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2159 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2160 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2161 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2163 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2166 nir_print_instr(&instr
->instr
, stderr
);
2167 fprintf(stderr
, "\n");
2172 case nir_op_f2f16_rtne
: {
2173 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2174 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2175 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2176 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2179 case nir_op_f2f16_rtz
: {
2180 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2181 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2182 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2183 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2186 case nir_op_f2f32
: {
2187 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2188 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2189 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2190 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2192 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2193 nir_print_instr(&instr
->instr
, stderr
);
2194 fprintf(stderr
, "\n");
2198 case nir_op_f2f64
: {
2199 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2200 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2201 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2202 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2205 case nir_op_i2f16
: {
2206 assert(dst
.regClass() == v2b
);
2207 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2208 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2209 src
= convert_int(bld
, src
, 8, 16, true);
2210 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2213 case nir_op_i2f32
: {
2214 assert(dst
.size() == 1);
2215 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2216 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2217 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2218 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2221 case nir_op_i2f64
: {
2222 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2223 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2224 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2225 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2226 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2227 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2228 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2229 RegClass rc
= RegClass(src
.type(), 1);
2230 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2231 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2232 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2233 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2234 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2235 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2238 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2239 nir_print_instr(&instr
->instr
, stderr
);
2240 fprintf(stderr
, "\n");
2244 case nir_op_u2f16
: {
2245 assert(dst
.regClass() == v2b
);
2246 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2247 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2248 src
= convert_int(bld
, src
, 8, 16, false);
2249 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2252 case nir_op_u2f32
: {
2253 assert(dst
.size() == 1);
2254 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2255 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2256 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2257 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2259 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2260 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2261 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2265 case nir_op_u2f64
: {
2266 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2267 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2268 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2269 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2270 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2271 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2272 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2273 RegClass rc
= RegClass(src
.type(), 1);
2274 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2275 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2276 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2277 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2278 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2279 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2281 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2282 nir_print_instr(&instr
->instr
, stderr
);
2283 fprintf(stderr
, "\n");
2288 case nir_op_f2i16
: {
2289 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2290 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2291 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2292 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2293 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2295 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2297 if (dst
.type() == RegType::vgpr
)
2298 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2300 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2304 case nir_op_f2u16
: {
2305 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2306 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2307 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2308 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2309 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2311 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2313 if (dst
.type() == RegType::vgpr
)
2314 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2316 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2319 case nir_op_f2i32
: {
2320 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2321 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2322 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2323 if (dst
.type() == RegType::vgpr
) {
2324 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2326 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2327 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2329 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2330 if (dst
.type() == RegType::vgpr
)
2331 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2333 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2334 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2336 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2337 if (dst
.type() == RegType::vgpr
)
2338 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2340 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2341 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2344 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2345 nir_print_instr(&instr
->instr
, stderr
);
2346 fprintf(stderr
, "\n");
2350 case nir_op_f2u32
: {
2351 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2352 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2353 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2354 if (dst
.type() == RegType::vgpr
) {
2355 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2357 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2358 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2360 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2361 if (dst
.type() == RegType::vgpr
)
2362 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2364 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2365 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2367 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2368 if (dst
.type() == RegType::vgpr
)
2369 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2371 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2372 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2375 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2376 nir_print_instr(&instr
->instr
, stderr
);
2377 fprintf(stderr
, "\n");
2381 case nir_op_f2i64
: {
2382 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2383 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2384 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2386 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2387 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2388 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2389 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2390 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2391 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2392 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2393 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2394 Temp new_exponent
= bld
.tmp(v1
);
2395 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2396 if (ctx
->program
->chip_class
>= GFX8
)
2397 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2399 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2400 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2401 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2403 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2404 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2405 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2406 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2407 Temp new_lower
= bld
.tmp(v1
);
2408 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2409 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2410 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2412 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2413 if (src
.type() == RegType::vgpr
)
2414 src
= bld
.as_uniform(src
);
2415 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2416 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2417 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2418 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2419 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2420 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2421 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2422 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2423 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2424 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2425 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2426 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2427 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2428 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2429 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2431 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2432 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2433 Temp borrow
= bld
.tmp(s1
);
2434 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2435 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2436 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2438 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2439 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2440 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2441 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2442 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2443 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2444 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2445 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2446 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2447 if (dst
.type() == RegType::sgpr
) {
2448 lower
= bld
.as_uniform(lower
);
2449 upper
= bld
.as_uniform(upper
);
2451 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2454 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2455 nir_print_instr(&instr
->instr
, stderr
);
2456 fprintf(stderr
, "\n");
2460 case nir_op_f2u64
: {
2461 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2462 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2463 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2465 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2466 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2467 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2468 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2469 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2470 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2471 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2472 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2473 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2474 Temp new_exponent
= bld
.tmp(v1
);
2475 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2476 if (ctx
->program
->chip_class
>= GFX8
)
2477 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2479 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2480 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2481 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2482 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2483 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2484 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2485 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2486 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2488 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2489 if (src
.type() == RegType::vgpr
)
2490 src
= bld
.as_uniform(src
);
2491 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2492 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2493 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2494 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2495 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2496 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2497 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2498 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2499 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2500 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2501 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2502 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2503 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2504 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2505 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2506 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2507 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2508 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2510 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2511 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2512 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2513 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2514 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2515 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2516 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2517 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2518 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2519 if (dst
.type() == RegType::sgpr
) {
2520 lower
= bld
.as_uniform(lower
);
2521 upper
= bld
.as_uniform(upper
);
2523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2526 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2527 nir_print_instr(&instr
->instr
, stderr
);
2528 fprintf(stderr
, "\n");
2532 case nir_op_b2f16
: {
2533 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2534 assert(src
.regClass() == bld
.lm
);
2536 if (dst
.regClass() == s1
) {
2537 src
= bool_to_scalar_condition(ctx
, src
);
2538 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2539 } else if (dst
.regClass() == v2b
) {
2540 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2541 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2543 unreachable("Wrong destination register class for nir_op_b2f16.");
2547 case nir_op_b2f32
: {
2548 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2549 assert(src
.regClass() == bld
.lm
);
2551 if (dst
.regClass() == s1
) {
2552 src
= bool_to_scalar_condition(ctx
, src
);
2553 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2554 } else if (dst
.regClass() == v1
) {
2555 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2557 unreachable("Wrong destination register class for nir_op_b2f32.");
2561 case nir_op_b2f64
: {
2562 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2563 assert(src
.regClass() == bld
.lm
);
2565 if (dst
.regClass() == s2
) {
2566 src
= bool_to_scalar_condition(ctx
, src
);
2567 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2568 } else if (dst
.regClass() == v2
) {
2569 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2570 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2571 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2573 unreachable("Wrong destination register class for nir_op_b2f64.");
2580 case nir_op_i2i64
: {
2581 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2582 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2588 case nir_op_u2u64
: {
2589 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2590 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2594 case nir_op_b2i32
: {
2595 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2596 assert(src
.regClass() == bld
.lm
);
2598 if (dst
.regClass() == s1
) {
2599 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2600 bool_to_scalar_condition(ctx
, src
, dst
);
2601 } else if (dst
.regClass() == v1
) {
2602 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2604 unreachable("Invalid register class for b2i32");
2610 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2611 assert(dst
.regClass() == bld
.lm
);
2613 if (src
.type() == RegType::vgpr
) {
2614 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2615 assert(dst
.regClass() == bld
.lm
);
2616 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2617 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2619 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2621 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2622 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2624 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2625 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2627 bool_to_vector_condition(ctx
, tmp
, dst
);
2631 case nir_op_pack_64_2x32_split
: {
2632 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2633 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2635 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2638 case nir_op_unpack_64_2x32_split_x
:
2639 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2641 case nir_op_unpack_64_2x32_split_y
:
2642 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2644 case nir_op_unpack_32_2x16_split_x
:
2645 if (dst
.type() == RegType::vgpr
) {
2646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2648 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2651 case nir_op_unpack_32_2x16_split_y
:
2652 if (dst
.type() == RegType::vgpr
) {
2653 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2655 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2658 case nir_op_pack_32_2x16_split
: {
2659 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2660 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2661 if (dst
.regClass() == v1
) {
2662 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2663 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2664 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2666 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2667 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2668 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2672 case nir_op_pack_half_2x16
: {
2673 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2675 if (dst
.regClass() == v1
) {
2676 Temp src0
= bld
.tmp(v1
);
2677 Temp src1
= bld
.tmp(v1
);
2678 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2679 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2680 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2682 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2683 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2684 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2686 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2687 nir_print_instr(&instr
->instr
, stderr
);
2688 fprintf(stderr
, "\n");
2692 case nir_op_unpack_half_2x16_split_x
: {
2693 if (dst
.regClass() == v1
) {
2694 Builder
bld(ctx
->program
, ctx
->block
);
2695 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2697 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2698 nir_print_instr(&instr
->instr
, stderr
);
2699 fprintf(stderr
, "\n");
2703 case nir_op_unpack_half_2x16_split_y
: {
2704 if (dst
.regClass() == v1
) {
2705 Builder
bld(ctx
->program
, ctx
->block
);
2706 /* TODO: use SDWA here */
2707 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2708 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2710 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2711 nir_print_instr(&instr
->instr
, stderr
);
2712 fprintf(stderr
, "\n");
2716 case nir_op_fquantize2f16
: {
2717 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2718 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2721 if (ctx
->program
->chip_class
>= GFX8
) {
2722 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2723 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2724 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2726 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2727 * so compare the result and flush to 0 if it's smaller.
2729 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2730 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2731 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2732 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2733 cmp_res
= vop3
->definitions
[0].getTemp();
2736 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2737 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2738 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2740 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2745 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2746 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2748 if (dst
.regClass() == s1
) {
2749 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2750 } else if (dst
.regClass() == v1
) {
2751 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2753 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2754 nir_print_instr(&instr
->instr
, stderr
);
2755 fprintf(stderr
, "\n");
2759 case nir_op_bitfield_select
: {
2760 /* (mask & insert) | (~mask & base) */
2761 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2762 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2763 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2765 /* dst = (insert & bitmask) | (base & ~bitmask) */
2766 if (dst
.regClass() == s1
) {
2767 aco_ptr
<Instruction
> sop2
;
2768 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2769 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2771 if (const_insert
&& const_bitmask
) {
2772 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2774 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2775 lhs
= Operand(insert
);
2779 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2780 if (const_base
&& const_bitmask
) {
2781 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2783 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2784 rhs
= Operand(base
);
2787 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2789 } else if (dst
.regClass() == v1
) {
2790 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2791 base
= as_vgpr(ctx
, base
);
2792 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2793 insert
= as_vgpr(ctx
, insert
);
2795 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2798 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2799 nir_print_instr(&instr
->instr
, stderr
);
2800 fprintf(stderr
, "\n");
2806 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2807 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2808 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2810 if (dst
.type() == RegType::sgpr
) {
2812 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2813 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2814 if (const_offset
&& const_bits
) {
2815 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2816 extract
= Operand(const_extract
);
2820 width
= Operand(const_bits
->u32
<< 16);
2822 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2824 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2828 if (dst
.regClass() == s1
) {
2829 if (instr
->op
== nir_op_ubfe
)
2830 opcode
= aco_opcode::s_bfe_u32
;
2832 opcode
= aco_opcode::s_bfe_i32
;
2833 } else if (dst
.regClass() == s2
) {
2834 if (instr
->op
== nir_op_ubfe
)
2835 opcode
= aco_opcode::s_bfe_u64
;
2837 opcode
= aco_opcode::s_bfe_i64
;
2839 unreachable("Unsupported BFE bit size");
2842 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2846 if (dst
.regClass() == v1
) {
2847 if (instr
->op
== nir_op_ubfe
)
2848 opcode
= aco_opcode::v_bfe_u32
;
2850 opcode
= aco_opcode::v_bfe_i32
;
2852 unreachable("Unsupported BFE bit size");
2855 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2859 case nir_op_bit_count
: {
2860 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2861 if (src
.regClass() == s1
) {
2862 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2863 } else if (src
.regClass() == v1
) {
2864 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2865 } else if (src
.regClass() == v2
) {
2866 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2867 emit_extract_vector(ctx
, src
, 1, v1
),
2868 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2869 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2870 } else if (src
.regClass() == s2
) {
2871 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2873 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2874 nir_print_instr(&instr
->instr
, stderr
);
2875 fprintf(stderr
, "\n");
2880 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2884 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2888 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2892 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2896 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2900 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2904 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2905 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2907 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2908 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2912 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2913 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2915 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2916 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2920 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2929 case nir_op_fddx_fine
:
2930 case nir_op_fddy_fine
:
2931 case nir_op_fddx_coarse
:
2932 case nir_op_fddy_coarse
: {
2933 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2934 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2935 if (instr
->op
== nir_op_fddx_fine
) {
2936 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2937 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2938 } else if (instr
->op
== nir_op_fddy_fine
) {
2939 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2940 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2942 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2943 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2944 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2946 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2950 if (ctx
->program
->chip_class
>= GFX8
) {
2951 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2952 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2954 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2955 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2956 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2958 emit_wqm(ctx
, tmp
, dst
, true);
2962 fprintf(stderr
, "Unknown NIR ALU instr: ");
2963 nir_print_instr(&instr
->instr
, stderr
);
2964 fprintf(stderr
, "\n");
2968 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2970 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2972 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2973 // which get truncated the lsb if double and msb if int
2974 // for now, we only use s_mov_b64 with 64bit inline constants
2975 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2976 assert(dst
.type() == RegType::sgpr
);
2978 Builder
bld(ctx
->program
, ctx
->block
);
2980 if (instr
->def
.bit_size
== 1) {
2981 assert(dst
.regClass() == bld
.lm
);
2982 int val
= instr
->value
[0].b
? -1 : 0;
2983 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2984 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2985 } else if (instr
->def
.bit_size
== 8) {
2986 /* ensure that the value is correctly represented in the low byte of the register */
2987 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2988 } else if (instr
->def
.bit_size
== 16) {
2989 /* ensure that the value is correctly represented in the low half of the register */
2990 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2991 } else if (dst
.size() == 1) {
2992 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2994 assert(dst
.size() != 1);
2995 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2996 if (instr
->def
.bit_size
== 64)
2997 for (unsigned i
= 0; i
< dst
.size(); i
++)
2998 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3000 for (unsigned i
= 0; i
< dst
.size(); i
++)
3001 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3003 vec
->definitions
[0] = Definition(dst
);
3004 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3008 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3010 uint32_t new_mask
= 0;
3011 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3012 if (mask
& (1u << i
))
3013 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3017 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3019 Builder
bld(ctx
->program
, ctx
->block
);
3020 if (offset
.isTemp()) {
3021 Temp tmp
[3] = {vec
, vec
, vec
};
3023 if (vec
.size() == 3) {
3024 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3026 } else if (vec
.size() == 2) {
3027 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3028 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3030 for (unsigned i
= 0; i
< dst
.size(); i
++)
3031 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3034 if (dst
.size() == 2)
3035 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3037 offset
= Operand(0u);
3040 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3041 bld
.copy(Definition(dst
), vec
);
3043 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3046 struct LoadEmitInfo
{
3049 unsigned num_components
;
3050 unsigned component_size
;
3051 Temp resource
= Temp(0, s1
);
3052 unsigned component_stride
= 0;
3053 unsigned const_offset
= 0;
3054 unsigned align_mul
= 0;
3055 unsigned align_offset
= 0;
3058 unsigned swizzle_component_size
= 0;
3059 barrier_interaction barrier
= barrier_none
;
3060 bool can_reorder
= true;
3061 Temp soffset
= Temp(0, s1
);
3064 using LoadCallback
= Temp(*)(
3065 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3066 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3068 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3069 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3071 unsigned load_size
= info
->num_components
* info
->component_size
;
3072 unsigned component_size
= info
->component_size
;
3074 unsigned num_vals
= 0;
3075 Temp vals
[info
->dst
.bytes()];
3077 unsigned const_offset
= info
->const_offset
;
3079 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3080 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3082 unsigned bytes_read
= 0;
3083 while (bytes_read
< load_size
) {
3084 unsigned bytes_needed
= load_size
- bytes_read
;
3086 /* add buffer for unaligned loads */
3087 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3090 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3091 if (info
->component_stride
) {
3092 assert(supports_8bit_16bit_loads
&& "unimplemented");
3096 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3097 bytes_needed
= align(bytes_needed
, 4);
3104 if (info
->swizzle_component_size
)
3105 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3106 if (info
->component_stride
)
3107 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3109 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3111 /* reduce constant offset */
3112 Operand offset
= info
->offset
;
3113 unsigned reduced_const_offset
= const_offset
;
3114 bool remove_const_offset_completely
= need_to_align_offset
;
3115 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3116 unsigned to_add
= const_offset
;
3117 if (remove_const_offset_completely
) {
3118 reduced_const_offset
= 0;
3120 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3121 reduced_const_offset
%= max_const_offset_plus_one
;
3123 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3124 if (offset
.isConstant()) {
3125 offset
= Operand(offset
.constantValue() + to_add
);
3126 } else if (offset_tmp
.regClass() == s1
) {
3127 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3128 offset_tmp
, Operand(to_add
));
3129 } else if (offset_tmp
.regClass() == v1
) {
3130 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3132 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3133 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3134 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3136 if (offset_tmp
.regClass() == s2
) {
3137 Temp carry
= bld
.tmp(s1
);
3138 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3139 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3140 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3142 Temp new_lo
= bld
.tmp(v1
);
3143 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3144 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3145 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3150 /* align offset down if needed */
3151 Operand aligned_offset
= offset
;
3152 if (need_to_align_offset
) {
3153 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3154 if (offset
.isConstant()) {
3155 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3156 } else if (offset_tmp
.regClass() == s1
) {
3157 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3158 } else if (offset_tmp
.regClass() == s2
) {
3159 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3160 } else if (offset_tmp
.regClass() == v1
) {
3161 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3162 } else if (offset_tmp
.regClass() == v2
) {
3163 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3164 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3165 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3166 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3169 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3170 bld
.copy(bld
.def(s1
), aligned_offset
);
3172 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3173 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3174 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3176 /* shift result right if needed */
3178 Operand
align((uint32_t)byte_align
);
3179 if (byte_align
== -1) {
3180 if (offset
.isConstant())
3181 align
= Operand(offset
.constantValue() % 4u);
3182 else if (offset
.size() == 2)
3183 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3188 if (align
.isTemp() || align
.constantValue()) {
3189 assert(val
.bytes() >= load_size
&& "unimplemented");
3190 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3191 if (val
.type() == RegType::sgpr
)
3192 byte_align_scalar(ctx
, val
, align
, new_val
);
3194 byte_align_vector(ctx
, val
, align
, new_val
);
3199 /* add result to list and advance */
3200 if (info
->component_stride
) {
3201 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3202 const_offset
+= info
->component_stride
;
3203 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3205 const_offset
+= val
.bytes();
3206 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3208 bytes_read
+= val
.bytes();
3209 vals
[num_vals
++] = val
;
3212 /* the callback wrote directly to dst */
3213 if (vals
[0] == info
->dst
) {
3214 assert(num_vals
== 1);
3215 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3219 /* create array of components */
3220 unsigned components_split
= 0;
3221 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3222 bool has_vgprs
= false;
3223 for (unsigned i
= 0; i
< num_vals
;) {
3225 unsigned num_tmps
= 0;
3226 unsigned tmp_size
= 0;
3227 RegType reg_type
= RegType::sgpr
;
3228 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3229 if (vals
[i
].type() == RegType::vgpr
)
3230 reg_type
= RegType::vgpr
;
3231 tmp_size
+= vals
[i
].bytes();
3232 tmp
[num_tmps
++] = vals
[i
++];
3235 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3236 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3237 for (unsigned i
= 0; i
< num_vals
; i
++)
3238 vec
->operands
[i
] = Operand(tmp
[i
]);
3239 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3240 vec
->definitions
[0] = Definition(tmp
[0]);
3241 bld
.insert(std::move(vec
));
3244 if (tmp
[0].bytes() % component_size
) {
3246 assert(i
== num_vals
);
3247 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3248 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3251 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3253 unsigned start
= components_split
;
3255 if (tmp_size
== elem_rc
.bytes()) {
3256 allocated_vec
[components_split
++] = tmp
[0];
3258 assert(tmp_size
% elem_rc
.bytes() == 0);
3259 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3260 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3261 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3262 Temp component
= bld
.tmp(elem_rc
);
3263 allocated_vec
[components_split
++] = component
;
3264 split
->definitions
[i
] = Definition(component
);
3266 split
->operands
[0] = Operand(tmp
[0]);
3267 bld
.insert(std::move(split
));
3270 /* try to p_as_uniform early so we can create more optimizable code and
3271 * also update allocated_vec */
3272 for (unsigned j
= start
; j
< components_split
; j
++) {
3273 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3274 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3275 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3279 /* concatenate components and p_as_uniform() result if needed */
3280 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3281 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3283 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3285 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3286 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3287 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3288 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3290 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3291 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3292 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3293 vec
->definitions
[0] = Definition(tmp
);
3294 bld
.insert(std::move(vec
));
3295 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3297 vec
->definitions
[0] = Definition(info
->dst
);
3298 bld
.insert(std::move(vec
));
3302 Operand
load_lds_size_m0(Builder
& bld
)
3304 /* TODO: m0 does not need to be initialized on GFX9+ */
3305 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3308 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3309 Temp offset
, unsigned bytes_needed
,
3310 unsigned align
, unsigned const_offset
,
3313 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3315 Operand m
= load_lds_size_m0(bld
);
3317 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3318 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3323 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3324 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3326 op
= aco_opcode::ds_read_b128
;
3327 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3330 op
= aco_opcode::ds_read2_b64
;
3331 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3333 op
= aco_opcode::ds_read_b96
;
3334 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3336 op
= aco_opcode::ds_read_b64
;
3337 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3340 op
= aco_opcode::ds_read2_b32
;
3341 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3343 op
= aco_opcode::ds_read_b32
;
3344 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3346 op
= aco_opcode::ds_read_u16
;
3349 op
= aco_opcode::ds_read_u8
;
3352 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3353 if (const_offset
>= max_offset_plus_one
) {
3354 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3355 const_offset
%= max_offset_plus_one
;
3359 const_offset
/= (size
/ 2u);
3361 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3362 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3364 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3366 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3369 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3374 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3376 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3377 Temp offset
, unsigned bytes_needed
,
3378 unsigned align
, unsigned const_offset
,
3383 if (bytes_needed
<= 4) {
3385 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3386 } else if (bytes_needed
<= 8) {
3388 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3389 } else if (bytes_needed
<= 16) {
3391 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3392 } else if (bytes_needed
<= 32) {
3394 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3397 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3399 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3400 if (info
->resource
.id()) {
3401 load
->operands
[0] = Operand(info
->resource
);
3402 load
->operands
[1] = Operand(offset
);
3404 load
->operands
[0] = Operand(offset
);
3405 load
->operands
[1] = Operand(0u);
3407 RegClass
rc(RegType::sgpr
, size
);
3408 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3409 load
->definitions
[0] = Definition(val
);
3410 load
->glc
= info
->glc
;
3411 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3412 load
->barrier
= info
->barrier
;
3413 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3414 bld
.insert(std::move(load
));
3418 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3420 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3421 Temp offset
, unsigned bytes_needed
,
3422 unsigned align_
, unsigned const_offset
,
3425 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3426 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3428 if (info
->soffset
.id()) {
3429 if (soffset
.isTemp())
3430 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3431 soffset
= Operand(info
->soffset
);
3434 unsigned bytes_size
= 0;
3436 if (bytes_needed
== 1) {
3438 op
= aco_opcode::buffer_load_ubyte
;
3439 } else if (bytes_needed
== 2) {
3441 op
= aco_opcode::buffer_load_ushort
;
3442 } else if (bytes_needed
<= 4) {
3444 op
= aco_opcode::buffer_load_dword
;
3445 } else if (bytes_needed
<= 8) {
3447 op
= aco_opcode::buffer_load_dwordx2
;
3448 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3450 op
= aco_opcode::buffer_load_dwordx3
;
3453 op
= aco_opcode::buffer_load_dwordx4
;
3455 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3456 mubuf
->operands
[0] = Operand(info
->resource
);
3457 mubuf
->operands
[1] = vaddr
;
3458 mubuf
->operands
[2] = soffset
;
3459 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3460 mubuf
->glc
= info
->glc
;
3461 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3462 mubuf
->barrier
= info
->barrier
;
3463 mubuf
->can_reorder
= info
->can_reorder
;
3464 mubuf
->offset
= const_offset
;
3465 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3466 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3467 mubuf
->definitions
[0] = Definition(val
);
3468 bld
.insert(std::move(mubuf
));
3471 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3476 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3478 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3480 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3481 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3483 if (addr
.type() == RegType::vgpr
)
3484 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3485 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3488 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3489 Temp offset
, unsigned bytes_needed
,
3490 unsigned align_
, unsigned const_offset
,
3493 unsigned bytes_size
= 0;
3494 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3495 bool global
= bld
.program
->chip_class
>= GFX9
;
3497 if (bytes_needed
== 1) {
3499 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3500 } else if (bytes_needed
== 2) {
3502 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3503 } else if (bytes_needed
<= 4) {
3505 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3506 } else if (bytes_needed
<= 8) {
3508 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3509 } else if (bytes_needed
<= 12 && !mubuf
) {
3511 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3514 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3516 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3517 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3519 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3520 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3521 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3522 mubuf
->operands
[2] = Operand(0u);
3523 mubuf
->glc
= info
->glc
;
3526 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3527 mubuf
->disable_wqm
= false;
3528 mubuf
->barrier
= info
->barrier
;
3529 mubuf
->definitions
[0] = Definition(val
);
3530 bld
.insert(std::move(mubuf
));
3532 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3534 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3535 flat
->operands
[0] = Operand(offset
);
3536 flat
->operands
[1] = Operand(s1
);
3537 flat
->glc
= info
->glc
;
3538 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3539 flat
->barrier
= info
->barrier
;
3541 flat
->definitions
[0] = Definition(val
);
3542 bld
.insert(std::move(flat
));
3546 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3551 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3553 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3554 Temp address
, unsigned base_offset
, unsigned align
)
3556 assert(util_is_power_of_two_nonzero(align
));
3558 Builder
bld(ctx
->program
, ctx
->block
);
3560 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3561 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3562 info
.align_mul
= align
;
3563 info
.align_offset
= 0;
3564 info
.barrier
= barrier_shared
;
3565 info
.can_reorder
= false;
3566 info
.const_offset
= base_offset
;
3567 emit_lds_load(ctx
, bld
, &info
);
3572 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3577 Builder
bld(ctx
->program
, ctx
->block
);
3579 ASSERTED
bool is_subdword
= false;
3580 for (unsigned i
= 0; i
< count
; i
++)
3581 is_subdword
|= offsets
[i
] % 4;
3582 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3583 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3585 /* count == 1 fast path */
3587 if (dst_type
== RegType::sgpr
)
3588 dst
[0] = bld
.as_uniform(src
);
3590 dst
[0] = as_vgpr(ctx
, src
);
3594 for (unsigned i
= 0; i
< count
- 1; i
++)
3595 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3596 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3598 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3599 src
= as_vgpr(ctx
, src
);
3601 /* use allocated_vec if possible */
3602 auto it
= ctx
->allocated_vec
.find(src
.id());
3603 if (it
!= ctx
->allocated_vec
.end()) {
3604 unsigned total_size
= 0;
3605 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3606 total_size
+= it
->second
[i
].bytes();
3607 if (total_size
!= src
.bytes())
3610 unsigned elem_size
= it
->second
[0].bytes();
3612 for (unsigned i
= 0; i
< count
; i
++) {
3613 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3617 for (unsigned i
= 0; i
< count
; i
++) {
3618 unsigned start_idx
= offsets
[i
] / elem_size
;
3619 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3620 if (op_count
== 1) {
3621 if (dst_type
== RegType::sgpr
)
3622 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3624 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3628 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3629 for (unsigned j
= 0; j
< op_count
; j
++) {
3630 Temp tmp
= it
->second
[start_idx
+ j
];
3631 if (dst_type
== RegType::sgpr
)
3632 tmp
= bld
.as_uniform(tmp
);
3633 vec
->operands
[j
] = Operand(tmp
);
3635 vec
->definitions
[0] = Definition(dst
[i
]);
3636 bld
.insert(std::move(vec
));
3642 if (dst_type
== RegType::sgpr
)
3643 src
= bld
.as_uniform(src
);
3647 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3648 split
->operands
[0] = Operand(src
);
3649 for (unsigned i
= 0; i
< count
; i
++)
3650 split
->definitions
[i
] = Definition(dst
[i
]);
3651 bld
.insert(std::move(split
));
3654 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3655 int *start
, int *count
)
3657 unsigned start_elem
= ffs(todo_mask
) - 1;
3658 bool skip
= !(mask
& (1 << start_elem
));
3660 mask
= ~mask
& todo_mask
;
3664 u_bit_scan_consecutive_range(&mask
, start
, count
);
3669 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3671 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3674 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3675 Temp address
, unsigned base_offset
, unsigned align
)
3677 assert(util_is_power_of_two_nonzero(align
));
3678 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3680 Builder
bld(ctx
->program
, ctx
->block
);
3681 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3682 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3684 unsigned write_count
= 0;
3685 Temp write_datas
[32];
3686 unsigned offsets
[32];
3687 aco_opcode opcodes
[32];
3689 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3691 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3694 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3695 offsets
[write_count
] = offset
;
3696 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3698 advance_write_mask(&todo
, offset
, bytes
);
3702 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3703 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3704 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3705 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3707 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3708 aco_opcode op
= aco_opcode::num_opcodes
;
3709 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3710 op
= aco_opcode::ds_write_b128
;
3712 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3713 op
= aco_opcode::ds_write_b96
;
3715 } else if (bytes
>= 8 && aligned8
) {
3716 op
= aco_opcode::ds_write_b64
;
3718 } else if (bytes
>= 4 && aligned4
) {
3719 op
= aco_opcode::ds_write_b32
;
3721 } else if (bytes
>= 2 && aligned2
) {
3722 op
= aco_opcode::ds_write_b16
;
3724 } else if (bytes
>= 1) {
3725 op
= aco_opcode::ds_write_b8
;
3731 offsets
[write_count
] = offset
;
3732 opcodes
[write_count
] = op
;
3734 advance_write_mask(&todo
, offset
, bytes
);
3737 Operand m
= load_lds_size_m0(bld
);
3739 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3741 for (unsigned i
= 0; i
< write_count
; i
++) {
3742 aco_opcode op
= opcodes
[i
];
3743 if (op
== aco_opcode::num_opcodes
)
3746 Temp data
= write_datas
[i
];
3748 unsigned second
= write_count
;
3749 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3750 for (second
= i
+ 1; second
< write_count
; second
++) {
3751 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3752 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3753 opcodes
[second
] = aco_opcode::num_opcodes
;
3759 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3760 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3762 unsigned inline_offset
= base_offset
+ offsets
[i
];
3763 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3764 Temp address_offset
= address
;
3765 if (inline_offset
> max_offset
) {
3766 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3767 inline_offset
= offsets
[i
];
3769 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3772 Temp second_data
= write_datas
[second
];
3773 inline_offset
/= data
.bytes();
3774 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3776 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3781 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3783 unsigned align
= 16;
3785 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3791 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3796 return aco_opcode::buffer_store_byte
;
3799 return aco_opcode::buffer_store_short
;
3801 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3803 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3806 return aco_opcode::buffer_store_dwordx3
;
3808 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3810 unreachable("Unexpected store size");
3811 return aco_opcode::num_opcodes
;
3814 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3815 Temp data
, unsigned writemask
, int swizzle_element_size
,
3816 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3818 unsigned write_count_with_skips
= 0;
3821 /* determine how to split the data */
3822 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3825 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3826 offsets
[write_count_with_skips
] = offset
;
3827 if (skips
[write_count_with_skips
]) {
3828 advance_write_mask(&todo
, offset
, bytes
);
3829 write_count_with_skips
++;
3833 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3834 * larger than swizzle_element_size */
3835 bytes
= MIN2(bytes
, swizzle_element_size
);
3837 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3839 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3840 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3843 /* dword or larger stores have to be dword-aligned */
3844 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3845 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3846 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3847 if (bytes
>= 4 && !dword_aligned
)
3848 bytes
= MIN2(bytes
, 2);
3850 advance_write_mask(&todo
, offset
, bytes
);
3851 write_count_with_skips
++;
3854 /* actually split data */
3855 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3858 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3861 write_datas
[*write_count
] = write_datas
[i
];
3862 offsets
[*write_count
] = offsets
[i
];
3867 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3868 unsigned split_cnt
= 0u, Temp dst
= Temp())
3870 Builder
bld(ctx
->program
, ctx
->block
);
3871 unsigned dword_size
= elem_size_bytes
/ 4;
3874 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3876 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3877 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3878 instr
->definitions
[0] = Definition(dst
);
3880 for (unsigned i
= 0; i
< cnt
; ++i
) {
3882 assert(arr
[i
].size() == dword_size
);
3883 allocated_vec
[i
] = arr
[i
];
3884 instr
->operands
[i
] = Operand(arr
[i
]);
3886 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3887 allocated_vec
[i
] = zero
;
3888 instr
->operands
[i
] = Operand(zero
);
3892 bld
.insert(std::move(instr
));
3895 emit_split_vector(ctx
, dst
, split_cnt
);
3897 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3902 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3904 if (const_offset
>= 4096) {
3905 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3906 const_offset
%= 4096u;
3909 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3910 else if (unlikely(voffset
.regClass() == s1
))
3911 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3912 else if (likely(voffset
.regClass() == v1
))
3913 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3915 unreachable("Unsupported register class of voffset");
3918 return const_offset
;
3921 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3922 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3925 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3926 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3928 Builder
bld(ctx
->program
, ctx
->block
);
3929 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3930 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3932 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3933 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3934 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3935 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3936 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3938 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3941 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3942 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3943 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3945 Builder
bld(ctx
->program
, ctx
->block
);
3946 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3948 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3950 unsigned write_count
= 0;
3951 Temp write_datas
[32];
3952 unsigned offsets
[32];
3953 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3954 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3956 for (unsigned i
= 0; i
< write_count
; i
++) {
3957 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3958 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3962 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3963 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3964 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3966 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3967 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3968 assert(!!stride
!= allow_combining
);
3970 Builder
bld(ctx
->program
, ctx
->block
);
3972 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3973 info
.component_stride
= allow_combining
? 0 : stride
;
3975 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3976 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3977 info
.align_offset
= 0;
3978 info
.soffset
= soffset
;
3979 info
.const_offset
= base_const_offset
;
3980 emit_mubuf_load(ctx
, bld
, &info
);
3983 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3985 Builder
bld(ctx
->program
, ctx
->block
);
3986 Temp offset
= base_offset
.first
;
3987 unsigned const_offset
= base_offset
.second
;
3989 if (!nir_src_is_const(*off_src
)) {
3990 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3993 /* Calculate indirect offset with stride */
3994 if (likely(indirect_offset_arg
.regClass() == v1
))
3995 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3996 else if (indirect_offset_arg
.regClass() == s1
)
3997 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3999 unreachable("Unsupported register class of indirect offset");
4001 /* Add to the supplied base offset */
4002 if (offset
.id() == 0)
4003 offset
= with_stride
;
4004 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4005 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4006 else if (offset
.size() == 1 && with_stride
.size() == 1)
4007 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4009 unreachable("Unsupported register class of indirect offset");
4011 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4012 const_offset
+= const_offset_arg
* stride
;
4015 return std::make_pair(offset
, const_offset
);
4018 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4020 Builder
bld(ctx
->program
, ctx
->block
);
4023 if (off1
.first
.id() && off2
.first
.id()) {
4024 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4025 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4026 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4027 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4029 unreachable("Unsupported register class of indirect offset");
4031 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4034 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4037 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4039 Builder
bld(ctx
->program
, ctx
->block
);
4040 unsigned const_offset
= offs
.second
* multiplier
;
4042 if (!offs
.first
.id())
4043 return std::make_pair(offs
.first
, const_offset
);
4045 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4046 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4047 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4049 return std::make_pair(offset
, const_offset
);
4052 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4054 Builder
bld(ctx
->program
, ctx
->block
);
4056 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4057 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4058 /* component is in bytes */
4059 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4061 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4062 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4063 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4066 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4068 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4071 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4073 Builder
bld(ctx
->program
, ctx
->block
);
4075 switch (ctx
->shader
->info
.stage
) {
4076 case MESA_SHADER_TESS_CTRL
:
4077 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4078 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4079 case MESA_SHADER_TESS_EVAL
:
4080 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4082 unreachable("Unsupported stage in get_tess_rel_patch_id");
4086 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4088 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4089 Builder
bld(ctx
->program
, ctx
->block
);
4091 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4092 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4094 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4096 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4097 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4099 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4100 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4101 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4103 return offset_mul(ctx
, offs
, 4u);
4106 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4108 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4109 Builder
bld(ctx
->program
, ctx
->block
);
4111 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4112 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4113 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4114 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4116 std::pair
<Temp
, unsigned> offs
= instr
4117 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4118 : std::make_pair(Temp(), 0u);
4120 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4121 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4126 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4127 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4129 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4130 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4132 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4133 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4139 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4141 Builder
bld(ctx
->program
, ctx
->block
);
4143 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4144 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4146 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4148 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4149 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4150 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4152 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4153 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4158 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4160 Builder
bld(ctx
->program
, ctx
->block
);
4162 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4163 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4164 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4165 unsigned attr_stride
= ctx
->tcs_num_patches
;
4167 std::pair
<Temp
, unsigned> offs
= instr
4168 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4169 : std::make_pair(Temp(), 0u);
4171 if (const_base_offset
)
4172 offs
.second
+= const_base_offset
* attr_stride
;
4174 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4175 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4176 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4181 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4183 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4188 unsigned drv_loc
= nir_intrinsic_base(instr
);
4189 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4191 if (!nir_src_is_const(*off_src
)) {
4197 uint64_t slot
= per_vertex
4198 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4199 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4200 return (((uint64_t) 1) << slot
) & mask
;
4203 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4205 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4206 unsigned component
= nir_intrinsic_component(instr
);
4207 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4209 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4210 if (off_instr
->type
!= nir_instr_type_load_const
)
4213 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4214 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4216 if (instr
->src
[0].ssa
->bit_size
== 64)
4217 write_mask
= widen_mask(write_mask
, 2);
4219 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4221 for (unsigned i
= 0; i
< 8; ++i
) {
4222 if (write_mask
& (1 << i
)) {
4223 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4224 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4232 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4234 /* Only TCS per-vertex inputs are supported by this function.
4235 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4237 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4240 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4241 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4242 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4243 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4244 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4245 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4250 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4251 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4252 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4257 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4259 Builder
bld(ctx
->program
, ctx
->block
);
4261 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4262 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4263 bool indirect_write
;
4264 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4265 if (temp_only_input
&& !indirect_write
)
4269 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4270 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4271 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4272 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4274 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4275 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4276 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4277 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4278 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4282 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4283 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4284 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4285 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4286 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4287 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4288 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4289 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4290 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4291 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4292 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4293 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4294 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4296 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4297 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4299 unreachable("Invalid LS or ES stage");
4302 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4303 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4304 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4308 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4313 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4314 return off
== ctx
->tcs_tess_lvl_out_loc
||
4315 off
== ctx
->tcs_tess_lvl_in_loc
;
4319 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4321 uint64_t mask
= per_vertex
4322 ? ctx
->program
->info
->tcs
.tes_inputs_read
4323 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4325 bool indirect_write
= false;
4326 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4327 return indirect_write
|| output_read_by_tes
;
4330 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4332 uint64_t mask
= per_vertex
4333 ? ctx
->shader
->info
.outputs_read
4334 : ctx
->shader
->info
.patch_outputs_read
;
4336 bool indirect_write
= false;
4337 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4338 return indirect_write
|| output_read
;
4341 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4343 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4344 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4346 Builder
bld(ctx
->program
, ctx
->block
);
4348 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4349 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4350 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4352 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4353 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4354 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4356 if (write_to_vmem
) {
4357 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4358 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4359 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4361 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4362 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4363 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4367 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4368 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4369 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4373 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4375 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4376 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4378 Builder
bld(ctx
->program
, ctx
->block
);
4380 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4381 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4382 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4383 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4385 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4388 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4390 if (ctx
->stage
== vertex_vs
||
4391 ctx
->stage
== tess_eval_vs
||
4392 ctx
->stage
== fragment_fs
||
4393 ctx
->stage
== ngg_vertex_gs
||
4394 ctx
->stage
== ngg_tess_eval_gs
||
4395 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4396 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4397 if (!stored_to_temps
) {
4398 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4399 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4400 fprintf(stderr
, "\n");
4403 } else if (ctx
->stage
== vertex_es
||
4404 ctx
->stage
== vertex_ls
||
4405 ctx
->stage
== tess_eval_es
||
4406 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4407 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4408 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4409 visit_store_ls_or_es_output(ctx
, instr
);
4410 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4411 visit_store_tcs_output(ctx
, instr
, false);
4413 unreachable("Shader stage not implemented");
4417 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4419 visit_load_tcs_output(ctx
, instr
, false);
4422 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4424 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4425 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4427 Builder
bld(ctx
->program
, ctx
->block
);
4429 if (dst
.regClass() == v2b
) {
4430 if (ctx
->program
->has_16bank_lds
) {
4431 assert(ctx
->options
->chip_class
<= GFX8
);
4432 Builder::Result interp_p1
=
4433 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4434 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4435 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4436 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4437 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4438 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4440 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4442 if (ctx
->options
->chip_class
== GFX8
)
4443 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4445 Builder::Result interp_p1
=
4446 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4447 coord1
, bld
.m0(prim_mask
), idx
, component
);
4448 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4449 interp_p1
, idx
, component
);
4452 Builder::Result interp_p1
=
4453 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4454 bld
.m0(prim_mask
), idx
, component
);
4456 if (ctx
->program
->has_16bank_lds
)
4457 interp_p1
.instr
->operands
[0].setLateKill(true);
4459 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4460 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4464 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4466 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4467 for (unsigned i
= 0; i
< num_components
; i
++)
4468 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4469 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4470 assert(num_components
== 4);
4471 Builder
bld(ctx
->program
, ctx
->block
);
4472 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4475 for (Operand
& op
: vec
->operands
)
4476 op
= op
.isUndefined() ? Operand(0u) : op
;
4478 vec
->definitions
[0] = Definition(dst
);
4479 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4480 emit_split_vector(ctx
, dst
, num_components
);
4484 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4486 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4487 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4488 unsigned idx
= nir_intrinsic_base(instr
);
4489 unsigned component
= nir_intrinsic_component(instr
);
4490 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4492 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4494 assert(offset
->u32
== 0);
4496 /* the lower 15bit of the prim_mask contain the offset into LDS
4497 * while the upper bits contain the number of prims */
4498 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4499 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4500 Builder
bld(ctx
->program
, ctx
->block
);
4501 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4502 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4503 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4504 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4505 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4508 if (instr
->dest
.ssa
.num_components
== 1) {
4509 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4511 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4512 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4514 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4515 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4516 vec
->operands
[i
] = Operand(tmp
);
4518 vec
->definitions
[0] = Definition(dst
);
4519 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4523 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4524 unsigned offset
, unsigned stride
, unsigned channels
)
4526 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4527 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4529 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4530 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4533 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4534 unsigned offset
, unsigned stride
, unsigned *channels
)
4536 if (!vtx_info
->chan_byte_size
) {
4537 *channels
= vtx_info
->num_channels
;
4538 return vtx_info
->chan_format
;
4541 unsigned num_channels
= *channels
;
4542 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4543 unsigned new_channels
= num_channels
+ 1;
4544 /* first, assume more loads is worse and try using a larger data format */
4545 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4547 /* don't make the attribute potentially out-of-bounds */
4548 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4552 if (new_channels
== 5) {
4553 /* then try decreasing load size (at the cost of more loads) */
4554 new_channels
= *channels
;
4555 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4559 if (new_channels
< *channels
)
4560 *channels
= new_channels
;
4561 num_channels
= new_channels
;
4564 switch (vtx_info
->chan_format
) {
4565 case V_008F0C_BUF_DATA_FORMAT_8
:
4566 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4567 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4568 case V_008F0C_BUF_DATA_FORMAT_16
:
4569 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4570 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4571 case V_008F0C_BUF_DATA_FORMAT_32
:
4572 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4573 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4575 unreachable("shouldn't reach here");
4576 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4579 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4580 * so we may need to fix it up. */
4581 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4583 Builder
bld(ctx
->program
, ctx
->block
);
4585 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4586 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4588 /* For the integer-like cases, do a natural sign extension.
4590 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4591 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4594 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4595 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4597 /* Convert back to the right type. */
4598 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4599 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4600 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4601 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4602 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4603 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4609 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4611 Builder
bld(ctx
->program
, ctx
->block
);
4612 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4613 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4615 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4616 if (off_instr
->type
!= nir_instr_type_load_const
) {
4617 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4618 nir_print_instr(off_instr
, stderr
);
4619 fprintf(stderr
, "\n");
4621 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4623 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4625 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4626 unsigned component
= nir_intrinsic_component(instr
);
4627 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4628 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4629 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4630 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4631 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4633 unsigned dfmt
= attrib_format
& 0xf;
4634 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4635 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4637 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4638 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4639 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4640 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4642 num_channels
= MAX2(num_channels
, 3);
4644 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4645 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4648 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4649 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4650 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4652 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4654 Temp divided
= bld
.tmp(v1
);
4655 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4656 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4658 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4661 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4664 index
= bld
.vadd32(bld
.def(v1
),
4665 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4666 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4669 Temp channels
[num_channels
];
4670 unsigned channel_start
= 0;
4671 bool direct_fetch
= false;
4673 /* skip unused channels at the start */
4674 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4675 channel_start
= ffs(mask
) - 1;
4676 for (unsigned i
= 0; i
< channel_start
; i
++)
4677 channels
[i
] = Temp(0, s1
);
4678 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4679 num_channels
= 3 - (ffs(mask
) - 1);
4683 while (channel_start
< num_channels
) {
4684 unsigned fetch_component
= num_channels
- channel_start
;
4685 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4686 bool expanded
= false;
4688 /* use MUBUF when possible to avoid possible alignment issues */
4689 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4690 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4691 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4692 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4693 vtx_info
->chan_byte_size
== 4;
4694 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4696 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4698 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4699 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4700 fetch_component
= 4;
4705 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4707 Temp fetch_index
= index
;
4708 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4709 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4710 fetch_offset
= fetch_offset
% attrib_stride
;
4713 Operand
soffset(0u);
4714 if (fetch_offset
>= 4096) {
4715 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4716 fetch_offset
%= 4096;
4720 switch (fetch_bytes
) {
4722 assert(!use_mubuf
&& bitsize
== 16);
4723 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4726 if (bitsize
== 16) {
4728 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4730 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4734 assert(!use_mubuf
&& bitsize
== 16);
4735 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4738 if (bitsize
== 16) {
4740 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4742 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4746 assert(ctx
->options
->chip_class
>= GFX7
||
4747 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4748 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4751 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4754 unreachable("Unimplemented load_input vector size");
4758 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4759 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4760 num_channels
<= 3)) {
4761 direct_fetch
= true;
4764 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4768 Instruction
*mubuf
= bld
.mubuf(opcode
,
4769 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4770 fetch_offset
, false, true).instr
;
4771 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4773 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4774 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4775 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4776 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4779 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4781 if (fetch_component
== 1) {
4782 channels
[channel_start
] = fetch_dst
;
4784 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4785 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4786 bitsize
== 16 ? v2b
: v1
);
4789 channel_start
+= fetch_component
;
4792 if (!direct_fetch
) {
4793 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4794 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4796 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4797 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4798 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4800 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4801 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4802 unsigned num_temp
= 0;
4803 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4804 unsigned idx
= i
+ component
;
4805 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4806 Temp channel
= channels
[swizzle
[idx
]];
4807 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4808 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4809 vec
->operands
[i
] = Operand(channel
);
4813 } else if (is_float
&& idx
== 3) {
4814 vec
->operands
[i
] = Operand(0x3f800000u
);
4815 } else if (!is_float
&& idx
== 3) {
4816 vec
->operands
[i
] = Operand(1u);
4818 vec
->operands
[i
] = Operand(0u);
4821 vec
->definitions
[0] = Definition(dst
);
4822 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4823 emit_split_vector(ctx
, dst
, dst
.size());
4825 if (num_temp
== dst
.size())
4826 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4828 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4829 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4830 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4831 if (off_instr
->type
!= nir_instr_type_load_const
||
4832 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4833 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4834 nir_print_instr(off_instr
, stderr
);
4835 fprintf(stderr
, "\n");
4838 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4839 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4841 assert(offset
->u32
== 0);
4843 /* the lower 15bit of the prim_mask contain the offset into LDS
4844 * while the upper bits contain the number of prims */
4845 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4846 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4847 Builder
bld(ctx
->program
, ctx
->block
);
4848 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4849 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4850 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4851 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4852 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4855 unsigned idx
= nir_intrinsic_base(instr
);
4856 unsigned component
= nir_intrinsic_component(instr
);
4857 unsigned vertex_id
= 2; /* P0 */
4859 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4860 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4861 switch (src0
->u32
) {
4863 vertex_id
= 2; /* P0 */
4866 vertex_id
= 0; /* P10 */
4869 vertex_id
= 1; /* P20 */
4872 unreachable("invalid vertex index");
4876 if (dst
.size() == 1) {
4877 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4879 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4880 for (unsigned i
= 0; i
< dst
.size(); i
++)
4881 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4882 vec
->definitions
[0] = Definition(dst
);
4883 bld
.insert(std::move(vec
));
4886 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4887 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4888 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4889 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4890 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4892 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4894 unreachable("Shader stage not implemented");
4898 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4900 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4902 Builder
bld(ctx
->program
, ctx
->block
);
4903 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4906 if (!nir_src_is_const(*vertex_src
)) {
4907 /* better code could be created, but this case probably doesn't happen
4908 * much in practice */
4909 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4910 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4913 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4914 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4916 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4918 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4921 if (vertex_offset
.id()) {
4922 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4923 Operand(i
), indirect_vertex
);
4924 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4926 vertex_offset
= elem
;
4930 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4931 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4933 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4934 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4935 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4936 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4937 Operand((vertex
% 2u) * 16u), Operand(16u));
4939 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4942 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4943 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4944 return offset_mul(ctx
, offs
, 4u);
4947 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4949 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4951 Builder
bld(ctx
->program
, ctx
->block
);
4952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4953 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4955 if (ctx
->stage
== geometry_gs
) {
4956 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4957 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4958 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4959 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4960 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4961 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4962 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4964 unreachable("Unsupported GS stage.");
4968 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4970 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4972 Builder
bld(ctx
->program
, ctx
->block
);
4973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4975 if (load_input_from_temps(ctx
, instr
, dst
))
4978 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4979 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4980 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4982 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4985 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4987 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4989 Builder
bld(ctx
->program
, ctx
->block
);
4991 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4992 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4993 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4995 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4996 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4998 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5001 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5003 switch (ctx
->shader
->info
.stage
) {
5004 case MESA_SHADER_GEOMETRY
:
5005 visit_load_gs_per_vertex_input(ctx
, instr
);
5007 case MESA_SHADER_TESS_CTRL
:
5008 visit_load_tcs_per_vertex_input(ctx
, instr
);
5010 case MESA_SHADER_TESS_EVAL
:
5011 visit_load_tes_per_vertex_input(ctx
, instr
);
5014 unreachable("Unimplemented shader stage");
5018 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5020 visit_load_tcs_output(ctx
, instr
, true);
5023 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5025 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5026 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5028 visit_store_tcs_output(ctx
, instr
, true);
5031 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5033 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5035 Builder
bld(ctx
->program
, ctx
->block
);
5036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5038 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5039 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5042 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5043 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5044 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5045 tes_w
= Operand(tmp
);
5048 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5049 emit_split_vector(ctx
, tess_coord
, 3);
5052 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5054 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5055 Builder
bld(ctx
->program
, ctx
->block
);
5056 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5057 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5058 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5061 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5065 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5067 Builder
bld(ctx
->program
, ctx
->block
);
5068 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5069 if (!nir_dest_is_divergent(instr
->dest
))
5070 index
= bld
.as_uniform(index
);
5071 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5072 unsigned binding
= nir_intrinsic_binding(instr
);
5075 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5076 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5077 unsigned offset
= layout
->binding
[binding
].offset
;
5079 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5080 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5081 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5082 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5083 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5086 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5087 stride
= layout
->binding
[binding
].size
;
5090 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5091 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5093 if (nir_const_index
) {
5094 const_index
= const_index
* stride
;
5095 } else if (index
.type() == RegType::vgpr
) {
5096 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5097 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5099 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5103 if (nir_const_index
) {
5104 const_index
= const_index
+ offset
;
5105 } else if (index
.type() == RegType::vgpr
) {
5106 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5108 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5112 if (nir_const_index
&& const_index
== 0) {
5114 } else if (index
.type() == RegType::vgpr
) {
5115 index
= bld
.vadd32(bld
.def(v1
),
5116 nir_const_index
? Operand(const_index
) : Operand(index
),
5119 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5120 nir_const_index
? Operand(const_index
) : Operand(index
),
5124 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5127 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5128 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5129 bool glc
=false, bool readonly
=true)
5131 Builder
bld(ctx
->program
, ctx
->block
);
5133 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5135 offset
= bld
.as_uniform(offset
);
5137 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5139 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5140 info
.can_reorder
= readonly
;
5141 info
.align_mul
= align_mul
;
5142 info
.align_offset
= align_offset
;
5144 emit_smem_load(ctx
, bld
, &info
);
5146 emit_mubuf_load(ctx
, bld
, &info
);
5149 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5151 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5152 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5154 Builder
bld(ctx
->program
, ctx
->block
);
5156 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5157 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5158 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5159 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5161 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5162 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5163 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5164 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5165 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5166 if (ctx
->options
->chip_class
>= GFX10
) {
5167 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5168 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5169 S_008F0C_RESOURCE_LEVEL(1);
5171 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5174 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5175 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5176 Operand(0xFFFFFFFFu
),
5177 Operand(desc_type
));
5178 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5179 rsrc
, upper_dwords
);
5181 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5182 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5184 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5185 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5186 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5189 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5191 Builder
bld(ctx
->program
, ctx
->block
);
5192 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5193 unsigned offset
= nir_intrinsic_base(instr
);
5194 unsigned count
= instr
->dest
.ssa
.num_components
;
5195 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5197 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5198 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5199 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5200 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5201 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5202 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5203 for (unsigned i
= 0; i
< count
; ++i
) {
5204 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5205 vec
->operands
[i
] = Operand
{elems
[i
]};
5207 vec
->definitions
[0] = Definition(dst
);
5208 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5209 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5214 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5215 if (offset
!= 0) // TODO check if index != 0 as well
5216 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5217 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5220 bool aligned
= true;
5222 if (instr
->dest
.ssa
.bit_size
== 8) {
5223 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5224 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5226 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5227 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5228 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5230 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5235 switch (vec
.size()) {
5237 op
= aco_opcode::s_load_dword
;
5240 op
= aco_opcode::s_load_dwordx2
;
5246 op
= aco_opcode::s_load_dwordx4
;
5252 op
= aco_opcode::s_load_dwordx8
;
5255 unreachable("unimplemented or forbidden load_push_constant.");
5258 bld
.smem(op
, Definition(vec
), ptr
, index
);
5261 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5262 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5267 emit_split_vector(ctx
, vec
, 4);
5268 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5269 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5270 emit_extract_vector(ctx
, vec
, 0, rc
),
5271 emit_extract_vector(ctx
, vec
, 1, rc
),
5272 emit_extract_vector(ctx
, vec
, 2, rc
));
5275 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5278 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5280 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5282 Builder
bld(ctx
->program
, ctx
->block
);
5284 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5285 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5286 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5287 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5288 if (ctx
->options
->chip_class
>= GFX10
) {
5289 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5290 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5291 S_008F0C_RESOURCE_LEVEL(1);
5293 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5294 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5297 unsigned base
= nir_intrinsic_base(instr
);
5298 unsigned range
= nir_intrinsic_range(instr
);
5300 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5301 if (base
&& offset
.type() == RegType::sgpr
)
5302 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5303 else if (base
&& offset
.type() == RegType::vgpr
)
5304 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5306 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5307 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5308 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5309 Operand(desc_type
));
5310 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5311 // TODO: get alignment information for subdword constants
5312 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5315 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5317 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5318 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5320 ctx
->program
->needs_exact
= true;
5322 // TODO: optimize uniform conditions
5323 Builder
bld(ctx
->program
, ctx
->block
);
5324 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5325 assert(src
.regClass() == bld
.lm
);
5326 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5327 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5328 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5332 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5334 Builder
bld(ctx
->program
, ctx
->block
);
5336 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5337 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5339 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5340 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5342 if (ctx
->block
->loop_nest_depth
&&
5343 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5344 /* we handle discards the same way as jump instructions */
5345 append_logical_end(ctx
->block
);
5347 /* in loops, discard behaves like break */
5348 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5349 ctx
->block
->kind
|= block_kind_discard
;
5352 /* uniform discard - loop ends here */
5353 assert(nir_instr_is_last(&instr
->instr
));
5354 ctx
->block
->kind
|= block_kind_uniform
;
5355 ctx
->cf_info
.has_branch
= true;
5356 bld
.branch(aco_opcode::p_branch
);
5357 add_linear_edge(ctx
->block
->index
, linear_target
);
5361 /* we add a break right behind the discard() instructions */
5362 ctx
->block
->kind
|= block_kind_break
;
5363 unsigned idx
= ctx
->block
->index
;
5365 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5366 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5368 /* remove critical edges from linear CFG */
5369 bld
.branch(aco_opcode::p_branch
);
5370 Block
* break_block
= ctx
->program
->create_and_insert_block();
5371 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5372 break_block
->kind
|= block_kind_uniform
;
5373 add_linear_edge(idx
, break_block
);
5374 add_linear_edge(break_block
->index
, linear_target
);
5375 bld
.reset(break_block
);
5376 bld
.branch(aco_opcode::p_branch
);
5378 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5379 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5380 add_linear_edge(idx
, continue_block
);
5381 append_logical_start(continue_block
);
5382 ctx
->block
= continue_block
;
5387 /* it can currently happen that NIR doesn't remove the unreachable code */
5388 if (!nir_instr_is_last(&instr
->instr
)) {
5389 ctx
->program
->needs_exact
= true;
5390 /* save exec somewhere temporarily so that it doesn't get
5391 * overwritten before the discard from outer exec masks */
5392 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5393 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5394 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5398 /* This condition is incorrect for uniformly branched discards in a loop
5399 * predicated by a divergent condition, but the above code catches that case
5400 * and the discard would end up turning into a discard_if.
5410 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5411 /* program just ends here */
5412 ctx
->block
->kind
|= block_kind_uniform
;
5413 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5414 0 /* enabled mask */, 9 /* dest */,
5415 false /* compressed */, true/* done */, true /* valid mask */);
5416 bld
.sopp(aco_opcode::s_endpgm
);
5417 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5419 ctx
->block
->kind
|= block_kind_discard
;
5420 /* branch and linear edge is added by visit_if() */
5424 enum aco_descriptor_type
{
5435 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5436 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5438 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5439 return dim
== ac_image_cube
||
5440 dim
== ac_image_1darray
||
5441 dim
== ac_image_2darray
||
5442 dim
== ac_image_2darraymsaa
;
5445 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5446 enum aco_descriptor_type desc_type
,
5447 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5449 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5450 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5451 if (it != ctx->tex_desc.end())
5454 Temp index
= Temp();
5455 bool index_set
= false;
5456 unsigned constant_index
= 0;
5457 unsigned descriptor_set
;
5458 unsigned base_index
;
5459 Builder
bld(ctx
->program
, ctx
->block
);
5462 assert(tex_instr
&& !image
);
5464 base_index
= tex_instr
->sampler_index
;
5466 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5467 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5471 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5472 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5474 constant_index
+= array_size
* const_value
->u32
;
5476 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5477 if (indirect
.type() == RegType::vgpr
)
5478 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5480 if (array_size
!= 1)
5481 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5487 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5491 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5493 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5494 base_index
= deref_instr
->var
->data
.binding
;
5497 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5498 list
= convert_pointer_to_64_bit(ctx
, list
);
5500 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5501 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5502 unsigned offset
= binding
->offset
;
5503 unsigned stride
= binding
->size
;
5507 assert(base_index
< layout
->binding_count
);
5509 switch (desc_type
) {
5510 case ACO_DESC_IMAGE
:
5512 opcode
= aco_opcode::s_load_dwordx8
;
5514 case ACO_DESC_FMASK
:
5516 opcode
= aco_opcode::s_load_dwordx8
;
5519 case ACO_DESC_SAMPLER
:
5521 opcode
= aco_opcode::s_load_dwordx4
;
5522 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5523 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5525 case ACO_DESC_BUFFER
:
5527 opcode
= aco_opcode::s_load_dwordx4
;
5529 case ACO_DESC_PLANE_0
:
5530 case ACO_DESC_PLANE_1
:
5532 opcode
= aco_opcode::s_load_dwordx8
;
5533 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5535 case ACO_DESC_PLANE_2
:
5537 opcode
= aco_opcode::s_load_dwordx4
;
5541 unreachable("invalid desc_type\n");
5544 offset
+= constant_index
* stride
;
5546 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5547 (!index_set
|| binding
->immutable_samplers_equal
)) {
5548 if (binding
->immutable_samplers_equal
)
5551 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5552 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5553 Operand(samplers
[constant_index
* 4 + 0]),
5554 Operand(samplers
[constant_index
* 4 + 1]),
5555 Operand(samplers
[constant_index
* 4 + 2]),
5556 Operand(samplers
[constant_index
* 4 + 3]));
5561 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5563 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5564 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5567 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5569 if (desc_type
== ACO_DESC_PLANE_2
) {
5571 for (unsigned i
= 0; i
< 8; i
++)
5572 components
[i
] = bld
.tmp(s1
);
5573 bld
.pseudo(aco_opcode::p_split_vector
,
5574 Definition(components
[0]),
5575 Definition(components
[1]),
5576 Definition(components
[2]),
5577 Definition(components
[3]),
5580 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5581 bld
.pseudo(aco_opcode::p_split_vector
,
5582 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5583 Definition(components
[4]),
5584 Definition(components
[5]),
5585 Definition(components
[6]),
5586 Definition(components
[7]),
5589 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5590 components
[0], components
[1], components
[2], components
[3],
5591 components
[4], components
[5], components
[6], components
[7]);
5597 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5600 case GLSL_SAMPLER_DIM_BUF
:
5602 case GLSL_SAMPLER_DIM_1D
:
5603 return array
? 2 : 1;
5604 case GLSL_SAMPLER_DIM_2D
:
5605 return array
? 3 : 2;
5606 case GLSL_SAMPLER_DIM_MS
:
5607 return array
? 4 : 3;
5608 case GLSL_SAMPLER_DIM_3D
:
5609 case GLSL_SAMPLER_DIM_CUBE
:
5611 case GLSL_SAMPLER_DIM_RECT
:
5612 case GLSL_SAMPLER_DIM_SUBPASS
:
5614 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5623 /* Adjust the sample index according to FMASK.
5625 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5626 * which is the identity mapping. Each nibble says which physical sample
5627 * should be fetched to get that sample.
5629 * For example, 0x11111100 means there are only 2 samples stored and
5630 * the second sample covers 3/4 of the pixel. When reading samples 0
5631 * and 1, return physical sample 0 (determined by the first two 0s
5632 * in FMASK), otherwise return physical sample 1.
5634 * The sample index should be adjusted as follows:
5635 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5637 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5639 Builder
bld(ctx
->program
, ctx
->block
);
5640 Temp fmask
= bld
.tmp(v1
);
5641 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5642 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5645 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5646 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5647 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5648 load
->operands
[0] = Operand(fmask_desc_ptr
);
5649 load
->operands
[1] = Operand(s4
); /* no sampler */
5650 load
->operands
[2] = Operand(coord
);
5651 load
->definitions
[0] = Definition(fmask
);
5658 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5659 ctx
->block
->instructions
.emplace_back(std::move(load
));
5661 Operand sample_index4
;
5662 if (sample_index
.isConstant()) {
5663 if (sample_index
.constantValue() < 16) {
5664 sample_index4
= Operand(sample_index
.constantValue() << 2);
5666 sample_index4
= Operand(0u);
5668 } else if (sample_index
.regClass() == s1
) {
5669 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5671 assert(sample_index
.regClass() == v1
);
5672 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5676 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5677 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5678 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5679 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5681 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5683 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5684 * resource descriptor is 0 (invalid),
5686 Temp compare
= bld
.tmp(bld
.lm
);
5687 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5688 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5690 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5692 /* Replace the MSAA sample index. */
5693 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5696 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5699 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5700 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5701 bool is_array
= glsl_sampler_type_is_array(type
);
5702 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5703 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5704 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5705 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5706 int count
= image_type_to_components_count(dim
, is_array
);
5707 std::vector
<Temp
> coords(count
);
5708 Builder
bld(ctx
->program
, ctx
->block
);
5712 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5713 /* get sample index */
5714 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5715 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5716 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5717 std::vector
<Temp
> fmask_load_address
;
5718 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5719 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5721 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5722 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5724 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5729 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5730 coords
.resize(coords
.size() + 1);
5731 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5733 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5735 for (int i
= 0; i
< count
; i
++)
5736 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5739 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5740 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5741 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5742 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5745 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5748 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5749 for (unsigned i
= 0; i
< coords
.size(); i
++)
5750 vec
->operands
[i
] = Operand(coords
[i
]);
5751 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5752 vec
->definitions
[0] = Definition(res
);
5753 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5758 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5760 Builder
bld(ctx
->program
, ctx
->block
);
5761 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5762 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5763 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5764 bool is_array
= glsl_sampler_type_is_array(type
);
5765 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5767 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5768 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5769 unsigned num_channels
= util_last_bit(mask
);
5770 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5771 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5774 switch (num_channels
) {
5776 opcode
= aco_opcode::buffer_load_format_x
;
5779 opcode
= aco_opcode::buffer_load_format_xy
;
5782 opcode
= aco_opcode::buffer_load_format_xyz
;
5785 opcode
= aco_opcode::buffer_load_format_xyzw
;
5788 unreachable(">4 channel buffer image load");
5790 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5791 load
->operands
[0] = Operand(rsrc
);
5792 load
->operands
[1] = Operand(vindex
);
5793 load
->operands
[2] = Operand((uint32_t) 0);
5795 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5798 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5799 load
->definitions
[0] = Definition(tmp
);
5801 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5802 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5803 load
->barrier
= barrier_image
;
5804 ctx
->block
->instructions
.emplace_back(std::move(load
));
5806 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5810 Temp coords
= get_image_coords(ctx
, instr
, type
);
5811 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5813 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5814 unsigned num_components
= util_bitcount(dmask
);
5816 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5819 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5821 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5822 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5824 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5825 load
->operands
[0] = Operand(resource
);
5826 load
->operands
[1] = Operand(s4
); /* no sampler */
5827 load
->operands
[2] = Operand(coords
);
5828 load
->definitions
[0] = Definition(tmp
);
5829 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5830 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5831 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5832 load
->dmask
= dmask
;
5834 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5835 load
->barrier
= barrier_image
;
5836 ctx
->block
->instructions
.emplace_back(std::move(load
));
5838 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5842 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5844 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5845 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5846 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5847 bool is_array
= glsl_sampler_type_is_array(type
);
5848 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5850 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5852 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5853 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5854 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5856 switch (data
.size()) {
5858 opcode
= aco_opcode::buffer_store_format_x
;
5861 opcode
= aco_opcode::buffer_store_format_xy
;
5864 opcode
= aco_opcode::buffer_store_format_xyz
;
5867 opcode
= aco_opcode::buffer_store_format_xyzw
;
5870 unreachable(">4 channel buffer image store");
5872 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5873 store
->operands
[0] = Operand(rsrc
);
5874 store
->operands
[1] = Operand(vindex
);
5875 store
->operands
[2] = Operand((uint32_t) 0);
5876 store
->operands
[3] = Operand(data
);
5877 store
->idxen
= true;
5880 store
->disable_wqm
= true;
5881 store
->barrier
= barrier_image
;
5882 ctx
->program
->needs_exact
= true;
5883 ctx
->block
->instructions
.emplace_back(std::move(store
));
5887 assert(data
.type() == RegType::vgpr
);
5888 Temp coords
= get_image_coords(ctx
, instr
, type
);
5889 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5891 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5892 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5894 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5895 store
->operands
[0] = Operand(resource
);
5896 store
->operands
[1] = Operand(data
);
5897 store
->operands
[2] = Operand(coords
);
5900 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5901 store
->dmask
= (1 << data
.size()) - 1;
5903 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5904 store
->disable_wqm
= true;
5905 store
->barrier
= barrier_image
;
5906 ctx
->program
->needs_exact
= true;
5907 ctx
->block
->instructions
.emplace_back(std::move(store
));
5911 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5913 /* return the previous value if dest is ever used */
5914 bool return_previous
= false;
5915 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5916 return_previous
= true;
5919 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5920 return_previous
= true;
5924 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5925 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5926 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5927 bool is_array
= glsl_sampler_type_is_array(type
);
5928 Builder
bld(ctx
->program
, ctx
->block
);
5930 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5931 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5933 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5934 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5936 aco_opcode buf_op
, image_op
;
5937 switch (instr
->intrinsic
) {
5938 case nir_intrinsic_image_deref_atomic_add
:
5939 buf_op
= aco_opcode::buffer_atomic_add
;
5940 image_op
= aco_opcode::image_atomic_add
;
5942 case nir_intrinsic_image_deref_atomic_umin
:
5943 buf_op
= aco_opcode::buffer_atomic_umin
;
5944 image_op
= aco_opcode::image_atomic_umin
;
5946 case nir_intrinsic_image_deref_atomic_imin
:
5947 buf_op
= aco_opcode::buffer_atomic_smin
;
5948 image_op
= aco_opcode::image_atomic_smin
;
5950 case nir_intrinsic_image_deref_atomic_umax
:
5951 buf_op
= aco_opcode::buffer_atomic_umax
;
5952 image_op
= aco_opcode::image_atomic_umax
;
5954 case nir_intrinsic_image_deref_atomic_imax
:
5955 buf_op
= aco_opcode::buffer_atomic_smax
;
5956 image_op
= aco_opcode::image_atomic_smax
;
5958 case nir_intrinsic_image_deref_atomic_and
:
5959 buf_op
= aco_opcode::buffer_atomic_and
;
5960 image_op
= aco_opcode::image_atomic_and
;
5962 case nir_intrinsic_image_deref_atomic_or
:
5963 buf_op
= aco_opcode::buffer_atomic_or
;
5964 image_op
= aco_opcode::image_atomic_or
;
5966 case nir_intrinsic_image_deref_atomic_xor
:
5967 buf_op
= aco_opcode::buffer_atomic_xor
;
5968 image_op
= aco_opcode::image_atomic_xor
;
5970 case nir_intrinsic_image_deref_atomic_exchange
:
5971 buf_op
= aco_opcode::buffer_atomic_swap
;
5972 image_op
= aco_opcode::image_atomic_swap
;
5974 case nir_intrinsic_image_deref_atomic_comp_swap
:
5975 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5976 image_op
= aco_opcode::image_atomic_cmpswap
;
5979 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5982 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5984 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5985 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5986 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5987 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5988 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5989 mubuf
->operands
[0] = Operand(resource
);
5990 mubuf
->operands
[1] = Operand(vindex
);
5991 mubuf
->operands
[2] = Operand((uint32_t)0);
5992 mubuf
->operands
[3] = Operand(data
);
5993 if (return_previous
)
5994 mubuf
->definitions
[0] = Definition(dst
);
5996 mubuf
->idxen
= true;
5997 mubuf
->glc
= return_previous
;
5998 mubuf
->dlc
= false; /* Not needed for atomics */
5999 mubuf
->disable_wqm
= true;
6000 mubuf
->barrier
= barrier_image
;
6001 ctx
->program
->needs_exact
= true;
6002 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6006 Temp coords
= get_image_coords(ctx
, instr
, type
);
6007 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6008 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6009 mimg
->operands
[0] = Operand(resource
);
6010 mimg
->operands
[1] = Operand(data
);
6011 mimg
->operands
[2] = Operand(coords
);
6012 if (return_previous
)
6013 mimg
->definitions
[0] = Definition(dst
);
6014 mimg
->glc
= return_previous
;
6015 mimg
->dlc
= false; /* Not needed for atomics */
6016 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6017 mimg
->dmask
= (1 << data
.size()) - 1;
6019 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6020 mimg
->disable_wqm
= true;
6021 mimg
->barrier
= barrier_image
;
6022 ctx
->program
->needs_exact
= true;
6023 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6027 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6029 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6030 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6031 Builder
bld(ctx
->program
, ctx
->block
);
6033 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6035 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6036 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6038 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6039 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6041 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6042 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6044 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6045 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6046 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6047 if (dst
.type() == RegType::vgpr
)
6048 bld
.copy(Definition(dst
), shr_dst
);
6050 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6052 emit_extract_vector(ctx
, desc
, 2, dst
);
6056 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6058 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6059 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6060 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6061 bool is_array
= glsl_sampler_type_is_array(type
);
6062 Builder
bld(ctx
->program
, ctx
->block
);
6064 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6065 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6066 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6070 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6073 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6075 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6077 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6078 mimg
->operands
[0] = Operand(resource
);
6079 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6080 mimg
->operands
[2] = Operand(lod
);
6081 uint8_t& dmask
= mimg
->dmask
;
6082 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6083 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6084 mimg
->da
= glsl_sampler_type_is_array(type
);
6085 mimg
->can_reorder
= true;
6086 Definition
& def
= mimg
->definitions
[0];
6087 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6089 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6090 glsl_sampler_type_is_array(type
)) {
6092 assert(instr
->dest
.ssa
.num_components
== 3);
6093 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6094 def
= Definition(tmp
);
6095 emit_split_vector(ctx
, tmp
, 3);
6097 /* divide 3rd value by 6 by multiplying with magic number */
6098 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6099 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6101 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6102 emit_extract_vector(ctx
, tmp
, 0, v1
),
6103 emit_extract_vector(ctx
, tmp
, 1, v1
),
6106 } else if (ctx
->options
->chip_class
== GFX9
&&
6107 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6108 glsl_sampler_type_is_array(type
)) {
6109 assert(instr
->dest
.ssa
.num_components
== 2);
6110 def
= Definition(dst
);
6113 def
= Definition(dst
);
6116 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6119 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6121 Builder
bld(ctx
->program
, ctx
->block
);
6122 unsigned num_components
= instr
->num_components
;
6124 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6125 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6126 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6128 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6129 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6130 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6131 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6134 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6136 Builder
bld(ctx
->program
, ctx
->block
);
6137 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6138 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6139 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6140 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6142 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6143 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6145 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6146 ctx
->options
->chip_class
>= GFX8
&&
6147 elem_size_bytes
>= 4;
6149 offset
= bld
.as_uniform(offset
);
6150 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6152 unsigned write_count
= 0;
6153 Temp write_datas
[32];
6154 unsigned offsets
[32];
6155 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6156 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6158 for (unsigned i
= 0; i
< write_count
; i
++) {
6159 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6160 if (smem
&& ctx
->stage
== fragment_fs
)
6161 op
= aco_opcode::p_fs_buffer_store_smem
;
6164 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6165 store
->operands
[0] = Operand(rsrc
);
6167 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6168 offset
, Operand(offsets
[i
]));
6169 store
->operands
[1] = Operand(off
);
6171 store
->operands
[1] = Operand(offset
);
6173 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6174 store
->operands
[1].setFixed(m0
);
6175 store
->operands
[2] = Operand(write_datas
[i
]);
6176 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6178 store
->disable_wqm
= true;
6179 store
->barrier
= barrier_buffer
;
6180 ctx
->block
->instructions
.emplace_back(std::move(store
));
6181 ctx
->program
->wb_smem_l1_on_end
= true;
6182 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6183 ctx
->block
->kind
|= block_kind_needs_lowering
;
6184 ctx
->program
->needs_exact
= true;
6187 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6188 store
->operands
[0] = Operand(rsrc
);
6189 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6190 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6191 store
->operands
[3] = Operand(write_datas
[i
]);
6192 store
->offset
= offsets
[i
];
6193 store
->offen
= (offset
.type() == RegType::vgpr
);
6194 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6196 store
->disable_wqm
= true;
6197 store
->barrier
= barrier_buffer
;
6198 ctx
->program
->needs_exact
= true;
6199 ctx
->block
->instructions
.emplace_back(std::move(store
));
6204 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6206 /* return the previous value if dest is ever used */
6207 bool return_previous
= false;
6208 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6209 return_previous
= true;
6212 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6213 return_previous
= true;
6217 Builder
bld(ctx
->program
, ctx
->block
);
6218 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6220 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6221 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6222 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6224 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6225 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6226 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6228 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6230 aco_opcode op32
, op64
;
6231 switch (instr
->intrinsic
) {
6232 case nir_intrinsic_ssbo_atomic_add
:
6233 op32
= aco_opcode::buffer_atomic_add
;
6234 op64
= aco_opcode::buffer_atomic_add_x2
;
6236 case nir_intrinsic_ssbo_atomic_imin
:
6237 op32
= aco_opcode::buffer_atomic_smin
;
6238 op64
= aco_opcode::buffer_atomic_smin_x2
;
6240 case nir_intrinsic_ssbo_atomic_umin
:
6241 op32
= aco_opcode::buffer_atomic_umin
;
6242 op64
= aco_opcode::buffer_atomic_umin_x2
;
6244 case nir_intrinsic_ssbo_atomic_imax
:
6245 op32
= aco_opcode::buffer_atomic_smax
;
6246 op64
= aco_opcode::buffer_atomic_smax_x2
;
6248 case nir_intrinsic_ssbo_atomic_umax
:
6249 op32
= aco_opcode::buffer_atomic_umax
;
6250 op64
= aco_opcode::buffer_atomic_umax_x2
;
6252 case nir_intrinsic_ssbo_atomic_and
:
6253 op32
= aco_opcode::buffer_atomic_and
;
6254 op64
= aco_opcode::buffer_atomic_and_x2
;
6256 case nir_intrinsic_ssbo_atomic_or
:
6257 op32
= aco_opcode::buffer_atomic_or
;
6258 op64
= aco_opcode::buffer_atomic_or_x2
;
6260 case nir_intrinsic_ssbo_atomic_xor
:
6261 op32
= aco_opcode::buffer_atomic_xor
;
6262 op64
= aco_opcode::buffer_atomic_xor_x2
;
6264 case nir_intrinsic_ssbo_atomic_exchange
:
6265 op32
= aco_opcode::buffer_atomic_swap
;
6266 op64
= aco_opcode::buffer_atomic_swap_x2
;
6268 case nir_intrinsic_ssbo_atomic_comp_swap
:
6269 op32
= aco_opcode::buffer_atomic_cmpswap
;
6270 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6273 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6275 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6276 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6277 mubuf
->operands
[0] = Operand(rsrc
);
6278 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6279 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6280 mubuf
->operands
[3] = Operand(data
);
6281 if (return_previous
)
6282 mubuf
->definitions
[0] = Definition(dst
);
6284 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6285 mubuf
->glc
= return_previous
;
6286 mubuf
->dlc
= false; /* Not needed for atomics */
6287 mubuf
->disable_wqm
= true;
6288 mubuf
->barrier
= barrier_buffer
;
6289 ctx
->program
->needs_exact
= true;
6290 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6293 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6295 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6296 Builder
bld(ctx
->program
, ctx
->block
);
6297 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6298 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6301 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6303 Builder
bld(ctx
->program
, ctx
->block
);
6304 unsigned num_components
= instr
->num_components
;
6305 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6307 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6308 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6309 num_components
, component_size
};
6310 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6311 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6312 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6313 info
.barrier
= barrier_buffer
;
6314 info
.can_reorder
= false;
6315 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6316 * it's safe to use SMEM */
6317 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6318 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6319 emit_global_load(ctx
, bld
, &info
);
6321 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6322 emit_smem_load(ctx
, bld
, &info
);
6326 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6328 Builder
bld(ctx
->program
, ctx
->block
);
6329 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6330 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6332 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6333 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6334 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6336 if (ctx
->options
->chip_class
>= GFX7
)
6337 addr
= as_vgpr(ctx
, addr
);
6339 unsigned write_count
= 0;
6340 Temp write_datas
[32];
6341 unsigned offsets
[32];
6342 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6343 16, &write_count
, write_datas
, offsets
);
6345 for (unsigned i
= 0; i
< write_count
; i
++) {
6346 if (ctx
->options
->chip_class
>= GFX7
) {
6347 unsigned offset
= offsets
[i
];
6348 Temp store_addr
= addr
;
6349 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6350 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6351 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6352 Temp carry
= bld
.tmp(bld
.lm
);
6353 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6355 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6356 Operand(offset
), addr0
);
6357 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6359 carry
).def(1).setHint(vcc
);
6361 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6366 bool global
= ctx
->options
->chip_class
>= GFX9
;
6368 switch (write_datas
[i
].bytes()) {
6370 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6373 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6376 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6379 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6382 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6385 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6388 unreachable("store_global not implemented for this size.");
6391 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6392 flat
->operands
[0] = Operand(store_addr
);
6393 flat
->operands
[1] = Operand(s1
);
6394 flat
->operands
[2] = Operand(write_datas
[i
]);
6397 flat
->offset
= offset
;
6398 flat
->disable_wqm
= true;
6399 flat
->barrier
= barrier_buffer
;
6400 ctx
->program
->needs_exact
= true;
6401 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6403 assert(ctx
->options
->chip_class
== GFX6
);
6405 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6407 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6409 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6410 mubuf
->operands
[0] = Operand(rsrc
);
6411 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6412 mubuf
->operands
[2] = Operand(0u);
6413 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6416 mubuf
->offset
= offsets
[i
];
6417 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6418 mubuf
->disable_wqm
= true;
6419 mubuf
->barrier
= barrier_buffer
;
6420 ctx
->program
->needs_exact
= true;
6421 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6426 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6428 /* return the previous value if dest is ever used */
6429 bool return_previous
= false;
6430 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6431 return_previous
= true;
6434 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6435 return_previous
= true;
6439 Builder
bld(ctx
->program
, ctx
->block
);
6440 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6441 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6443 if (ctx
->options
->chip_class
>= GFX7
)
6444 addr
= as_vgpr(ctx
, addr
);
6446 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6447 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6448 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6450 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6452 aco_opcode op32
, op64
;
6454 if (ctx
->options
->chip_class
>= GFX7
) {
6455 bool global
= ctx
->options
->chip_class
>= GFX9
;
6456 switch (instr
->intrinsic
) {
6457 case nir_intrinsic_global_atomic_add
:
6458 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6459 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6461 case nir_intrinsic_global_atomic_imin
:
6462 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6463 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6465 case nir_intrinsic_global_atomic_umin
:
6466 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6467 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6469 case nir_intrinsic_global_atomic_imax
:
6470 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6471 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6473 case nir_intrinsic_global_atomic_umax
:
6474 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6475 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6477 case nir_intrinsic_global_atomic_and
:
6478 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6479 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6481 case nir_intrinsic_global_atomic_or
:
6482 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6483 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6485 case nir_intrinsic_global_atomic_xor
:
6486 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6487 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6489 case nir_intrinsic_global_atomic_exchange
:
6490 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6491 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6493 case nir_intrinsic_global_atomic_comp_swap
:
6494 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6495 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6498 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6501 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6502 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6503 flat
->operands
[0] = Operand(addr
);
6504 flat
->operands
[1] = Operand(s1
);
6505 flat
->operands
[2] = Operand(data
);
6506 if (return_previous
)
6507 flat
->definitions
[0] = Definition(dst
);
6508 flat
->glc
= return_previous
;
6509 flat
->dlc
= false; /* Not needed for atomics */
6511 flat
->disable_wqm
= true;
6512 flat
->barrier
= barrier_buffer
;
6513 ctx
->program
->needs_exact
= true;
6514 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6516 assert(ctx
->options
->chip_class
== GFX6
);
6518 switch (instr
->intrinsic
) {
6519 case nir_intrinsic_global_atomic_add
:
6520 op32
= aco_opcode::buffer_atomic_add
;
6521 op64
= aco_opcode::buffer_atomic_add_x2
;
6523 case nir_intrinsic_global_atomic_imin
:
6524 op32
= aco_opcode::buffer_atomic_smin
;
6525 op64
= aco_opcode::buffer_atomic_smin_x2
;
6527 case nir_intrinsic_global_atomic_umin
:
6528 op32
= aco_opcode::buffer_atomic_umin
;
6529 op64
= aco_opcode::buffer_atomic_umin_x2
;
6531 case nir_intrinsic_global_atomic_imax
:
6532 op32
= aco_opcode::buffer_atomic_smax
;
6533 op64
= aco_opcode::buffer_atomic_smax_x2
;
6535 case nir_intrinsic_global_atomic_umax
:
6536 op32
= aco_opcode::buffer_atomic_umax
;
6537 op64
= aco_opcode::buffer_atomic_umax_x2
;
6539 case nir_intrinsic_global_atomic_and
:
6540 op32
= aco_opcode::buffer_atomic_and
;
6541 op64
= aco_opcode::buffer_atomic_and_x2
;
6543 case nir_intrinsic_global_atomic_or
:
6544 op32
= aco_opcode::buffer_atomic_or
;
6545 op64
= aco_opcode::buffer_atomic_or_x2
;
6547 case nir_intrinsic_global_atomic_xor
:
6548 op32
= aco_opcode::buffer_atomic_xor
;
6549 op64
= aco_opcode::buffer_atomic_xor_x2
;
6551 case nir_intrinsic_global_atomic_exchange
:
6552 op32
= aco_opcode::buffer_atomic_swap
;
6553 op64
= aco_opcode::buffer_atomic_swap_x2
;
6555 case nir_intrinsic_global_atomic_comp_swap
:
6556 op32
= aco_opcode::buffer_atomic_cmpswap
;
6557 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6560 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6563 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6565 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6567 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6568 mubuf
->operands
[0] = Operand(rsrc
);
6569 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6570 mubuf
->operands
[2] = Operand(0u);
6571 mubuf
->operands
[3] = Operand(data
);
6572 if (return_previous
)
6573 mubuf
->definitions
[0] = Definition(dst
);
6574 mubuf
->glc
= return_previous
;
6577 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6578 mubuf
->disable_wqm
= true;
6579 mubuf
->barrier
= barrier_buffer
;
6580 ctx
->program
->needs_exact
= true;
6581 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6585 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6586 Builder
bld(ctx
->program
, ctx
->block
);
6587 switch(instr
->intrinsic
) {
6588 case nir_intrinsic_group_memory_barrier
:
6589 case nir_intrinsic_memory_barrier
:
6590 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6592 case nir_intrinsic_memory_barrier_buffer
:
6593 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6595 case nir_intrinsic_memory_barrier_image
:
6596 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6598 case nir_intrinsic_memory_barrier_tcs_patch
:
6599 case nir_intrinsic_memory_barrier_shared
:
6600 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6603 unreachable("Unimplemented memory barrier intrinsic");
6608 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6610 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6611 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6612 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6613 Builder
bld(ctx
->program
, ctx
->block
);
6615 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6616 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6617 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6620 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6622 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6623 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6624 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6625 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6627 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6628 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6631 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6633 unsigned offset
= nir_intrinsic_base(instr
);
6634 Builder
bld(ctx
->program
, ctx
->block
);
6635 Operand m
= load_lds_size_m0(bld
);
6636 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6637 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6639 unsigned num_operands
= 3;
6640 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6641 switch(instr
->intrinsic
) {
6642 case nir_intrinsic_shared_atomic_add
:
6643 op32
= aco_opcode::ds_add_u32
;
6644 op64
= aco_opcode::ds_add_u64
;
6645 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6646 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6648 case nir_intrinsic_shared_atomic_imin
:
6649 op32
= aco_opcode::ds_min_i32
;
6650 op64
= aco_opcode::ds_min_i64
;
6651 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6652 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6654 case nir_intrinsic_shared_atomic_umin
:
6655 op32
= aco_opcode::ds_min_u32
;
6656 op64
= aco_opcode::ds_min_u64
;
6657 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6658 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6660 case nir_intrinsic_shared_atomic_imax
:
6661 op32
= aco_opcode::ds_max_i32
;
6662 op64
= aco_opcode::ds_max_i64
;
6663 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6664 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6666 case nir_intrinsic_shared_atomic_umax
:
6667 op32
= aco_opcode::ds_max_u32
;
6668 op64
= aco_opcode::ds_max_u64
;
6669 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6670 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6672 case nir_intrinsic_shared_atomic_and
:
6673 op32
= aco_opcode::ds_and_b32
;
6674 op64
= aco_opcode::ds_and_b64
;
6675 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6676 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6678 case nir_intrinsic_shared_atomic_or
:
6679 op32
= aco_opcode::ds_or_b32
;
6680 op64
= aco_opcode::ds_or_b64
;
6681 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6682 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6684 case nir_intrinsic_shared_atomic_xor
:
6685 op32
= aco_opcode::ds_xor_b32
;
6686 op64
= aco_opcode::ds_xor_b64
;
6687 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6688 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6690 case nir_intrinsic_shared_atomic_exchange
:
6691 op32
= aco_opcode::ds_write_b32
;
6692 op64
= aco_opcode::ds_write_b64
;
6693 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6694 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6696 case nir_intrinsic_shared_atomic_comp_swap
:
6697 op32
= aco_opcode::ds_cmpst_b32
;
6698 op64
= aco_opcode::ds_cmpst_b64
;
6699 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6700 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6704 unreachable("Unhandled shared atomic intrinsic");
6707 /* return the previous value if dest is ever used */
6708 bool return_previous
= false;
6709 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6710 return_previous
= true;
6713 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6714 return_previous
= true;
6719 if (data
.size() == 1) {
6720 assert(instr
->dest
.ssa
.bit_size
== 32);
6721 op
= return_previous
? op32_rtn
: op32
;
6723 assert(instr
->dest
.ssa
.bit_size
== 64);
6724 op
= return_previous
? op64_rtn
: op64
;
6727 if (offset
> 65535) {
6728 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6732 aco_ptr
<DS_instruction
> ds
;
6733 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6734 ds
->operands
[0] = Operand(address
);
6735 ds
->operands
[1] = Operand(data
);
6736 if (num_operands
== 4)
6737 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6738 ds
->operands
[num_operands
- 1] = m
;
6739 ds
->offset0
= offset
;
6740 if (return_previous
)
6741 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6742 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6745 Temp
get_scratch_resource(isel_context
*ctx
)
6747 Builder
bld(ctx
->program
, ctx
->block
);
6748 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6749 if (ctx
->stage
!= compute_cs
)
6750 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6752 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6753 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6755 if (ctx
->program
->chip_class
>= GFX10
) {
6756 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6757 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6758 S_008F0C_RESOURCE_LEVEL(1);
6759 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6760 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6761 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6764 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6765 if (ctx
->program
->chip_class
<= GFX8
)
6766 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6768 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6771 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6772 Builder
bld(ctx
->program
, ctx
->block
);
6773 Temp rsrc
= get_scratch_resource(ctx
);
6774 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6775 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6777 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6778 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6779 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6780 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6781 info
.swizzle_component_size
= 16;
6782 info
.can_reorder
= false;
6783 info
.soffset
= ctx
->program
->scratch_offset
;
6784 emit_mubuf_load(ctx
, bld
, &info
);
6787 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6788 Builder
bld(ctx
->program
, ctx
->block
);
6789 Temp rsrc
= get_scratch_resource(ctx
);
6790 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6791 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6793 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6794 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6796 unsigned write_count
= 0;
6797 Temp write_datas
[32];
6798 unsigned offsets
[32];
6799 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6800 16, &write_count
, write_datas
, offsets
);
6802 for (unsigned i
= 0; i
< write_count
; i
++) {
6803 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6804 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6808 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6809 uint8_t log2_ps_iter_samples
;
6810 if (ctx
->program
->info
->ps
.force_persample
) {
6811 log2_ps_iter_samples
=
6812 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6814 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6817 /* The bit pattern matches that used by fixed function fragment
6819 static const unsigned ps_iter_masks
[] = {
6820 0xffff, /* not used */
6826 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6828 Builder
bld(ctx
->program
, ctx
->block
);
6830 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6831 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6832 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6833 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6834 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6835 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6838 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6839 Builder
bld(ctx
->program
, ctx
->block
);
6841 unsigned stream
= nir_intrinsic_stream_id(instr
);
6842 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6843 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6844 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6847 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6849 unsigned num_components
=
6850 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6851 assert(num_components
);
6853 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6854 unsigned stream_offset
= 0;
6855 for (unsigned i
= 0; i
< stream
; i
++) {
6856 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6857 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6860 /* Limit on the stride field for <= GFX7. */
6861 assert(stride
< (1 << 14));
6863 Temp gsvs_dwords
[4];
6864 for (unsigned i
= 0; i
< 4; i
++)
6865 gsvs_dwords
[i
] = bld
.tmp(s1
);
6866 bld
.pseudo(aco_opcode::p_split_vector
,
6867 Definition(gsvs_dwords
[0]),
6868 Definition(gsvs_dwords
[1]),
6869 Definition(gsvs_dwords
[2]),
6870 Definition(gsvs_dwords
[3]),
6873 if (stream_offset
) {
6874 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6876 Temp carry
= bld
.tmp(s1
);
6877 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6878 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6881 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6882 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6884 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6885 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6887 unsigned offset
= 0;
6888 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6889 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6892 for (unsigned j
= 0; j
< 4; j
++) {
6893 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6896 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6897 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6898 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6899 if (const_offset
>= 4096u) {
6900 if (vaddr_offset
.isUndefined())
6901 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6903 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6904 const_offset
%= 4096u;
6907 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6908 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6909 mtbuf
->operands
[1] = vaddr_offset
;
6910 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6911 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6912 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6913 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6914 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6915 mtbuf
->offset
= const_offset
;
6918 mtbuf
->barrier
= barrier_gs_data
;
6919 mtbuf
->can_reorder
= true;
6920 bld
.insert(std::move(mtbuf
));
6923 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6926 /* outputs for the next vertex are undefined and keeping them around can
6927 * create invalid IR with control flow */
6928 ctx
->outputs
.mask
[i
] = 0;
6931 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6934 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6936 Builder
bld(ctx
->program
, ctx
->block
);
6938 if (cluster_size
== 1) {
6940 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6941 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6942 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6943 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6944 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6945 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6946 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6947 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6948 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6949 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6950 //subgroupAnd(val) -> (exec & ~val) == 0
6951 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6952 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6953 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6954 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6955 //subgroupOr(val) -> (val & exec) != 0
6956 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6957 return bool_to_vector_condition(ctx
, tmp
);
6958 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6959 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6960 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6961 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6962 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6963 return bool_to_vector_condition(ctx
, tmp
);
6965 //subgroupClustered{And,Or,Xor}(val, n) ->
6966 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6967 //cluster_offset = ~(n - 1) & lane_id
6968 //cluster_mask = ((1 << n) - 1)
6969 //subgroupClusteredAnd():
6970 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6971 //subgroupClusteredOr():
6972 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6973 //subgroupClusteredXor():
6974 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6975 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6976 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6979 if (op
== nir_op_iand
)
6980 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6982 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6984 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6986 if (ctx
->program
->chip_class
<= GFX7
)
6987 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6988 else if (ctx
->program
->wave_size
== 64)
6989 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6991 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6992 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6993 if (cluster_mask
!= 0xffffffff)
6994 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6996 Definition cmp_def
= Definition();
6997 if (op
== nir_op_iand
) {
6998 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6999 } else if (op
== nir_op_ior
) {
7000 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7001 } else if (op
== nir_op_ixor
) {
7002 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7003 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7004 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7006 cmp_def
.setHint(vcc
);
7007 return cmp_def
.getTemp();
7011 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7013 Builder
bld(ctx
->program
, ctx
->block
);
7015 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7016 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7017 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7019 if (op
== nir_op_iand
)
7020 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7022 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7024 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7025 Temp lo
= lohi
.def(0).getTemp();
7026 Temp hi
= lohi
.def(1).getTemp();
7027 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7029 Definition cmp_def
= Definition();
7030 if (op
== nir_op_iand
)
7031 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7032 else if (op
== nir_op_ior
)
7033 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7034 else if (op
== nir_op_ixor
)
7035 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7036 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7037 cmp_def
.setHint(vcc
);
7038 return cmp_def
.getTemp();
7041 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7043 Builder
bld(ctx
->program
, ctx
->block
);
7045 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7046 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7047 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7048 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7049 if (op
== nir_op_iand
)
7050 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7051 else if (op
== nir_op_ior
)
7052 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7053 else if (op
== nir_op_ixor
)
7054 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7060 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7062 Builder
bld(ctx
->program
, ctx
->block
);
7063 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7064 if (src
.regClass().type() == RegType::vgpr
) {
7065 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7066 } else if (src
.regClass() == s1
) {
7067 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7068 } else if (src
.regClass() == s2
) {
7069 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7071 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7072 nir_print_instr(&instr
->instr
, stderr
);
7073 fprintf(stderr
, "\n");
7077 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7079 Builder
bld(ctx
->program
, ctx
->block
);
7080 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7081 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7082 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7084 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7085 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7086 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7087 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7090 if (ctx
->program
->chip_class
>= GFX8
) {
7091 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7092 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7093 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7094 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7095 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7096 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7098 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7099 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7100 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7101 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7102 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7103 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7104 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7105 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7106 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7107 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7110 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7111 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7112 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7113 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7114 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7115 Temp wqm1
= bld
.tmp(v1
);
7116 emit_wqm(ctx
, tmp1
, wqm1
, true);
7117 Temp wqm2
= bld
.tmp(v1
);
7118 emit_wqm(ctx
, tmp2
, wqm2
, true);
7119 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7123 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7125 Builder
bld(ctx
->program
, ctx
->block
);
7126 switch(instr
->intrinsic
) {
7127 case nir_intrinsic_load_barycentric_sample
:
7128 case nir_intrinsic_load_barycentric_pixel
:
7129 case nir_intrinsic_load_barycentric_centroid
: {
7130 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7131 Temp bary
= Temp(0, s2
);
7133 case INTERP_MODE_SMOOTH
:
7134 case INTERP_MODE_NONE
:
7135 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7136 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7137 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7138 bary
= ctx
->persp_centroid
;
7139 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7140 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7142 case INTERP_MODE_NOPERSPECTIVE
:
7143 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7144 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7145 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7146 bary
= ctx
->linear_centroid
;
7147 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7148 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7153 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7154 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7155 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7156 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7157 Operand(p1
), Operand(p2
));
7158 emit_split_vector(ctx
, dst
, 2);
7161 case nir_intrinsic_load_barycentric_model
: {
7162 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7164 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7165 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7166 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7167 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7168 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7169 Operand(p1
), Operand(p2
), Operand(p3
));
7170 emit_split_vector(ctx
, dst
, 3);
7173 case nir_intrinsic_load_barycentric_at_sample
: {
7174 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7175 switch (ctx
->options
->key
.fs
.num_samples
) {
7176 case 2: sample_pos_offset
+= 1 << 3; break;
7177 case 4: sample_pos_offset
+= 3 << 3; break;
7178 case 8: sample_pos_offset
+= 7 << 3; break;
7182 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7183 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7184 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7185 if (addr
.type() == RegType::sgpr
) {
7188 sample_pos_offset
+= const_addr
->u32
<< 3;
7189 offset
= Operand(sample_pos_offset
);
7190 } else if (ctx
->options
->chip_class
>= GFX9
) {
7191 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7193 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7194 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7197 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7198 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7200 } else if (ctx
->options
->chip_class
>= GFX9
) {
7201 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7202 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7203 } else if (ctx
->options
->chip_class
>= GFX7
) {
7204 /* addr += private_segment_buffer + sample_pos_offset */
7205 Temp tmp0
= bld
.tmp(s1
);
7206 Temp tmp1
= bld
.tmp(s1
);
7207 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7208 Definition scc_tmp
= bld
.def(s1
, scc
);
7209 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7210 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7211 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7212 Temp pck0
= bld
.tmp(v1
);
7213 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7214 tmp1
= as_vgpr(ctx
, tmp1
);
7215 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7216 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7218 /* sample_pos = flat_load_dwordx2 addr */
7219 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7221 assert(ctx
->options
->chip_class
== GFX6
);
7223 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7224 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7225 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7227 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7228 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7230 sample_pos
= bld
.tmp(v2
);
7232 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7233 load
->definitions
[0] = Definition(sample_pos
);
7234 load
->operands
[0] = Operand(rsrc
);
7235 load
->operands
[1] = Operand(addr
);
7236 load
->operands
[2] = Operand(0u);
7237 load
->offset
= sample_pos_offset
;
7239 load
->addr64
= true;
7242 load
->disable_wqm
= false;
7243 load
->barrier
= barrier_none
;
7244 load
->can_reorder
= true;
7245 ctx
->block
->instructions
.emplace_back(std::move(load
));
7248 /* sample_pos -= 0.5 */
7249 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7250 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7252 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7253 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7255 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7258 case nir_intrinsic_load_barycentric_at_offset
: {
7259 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7260 RegClass rc
= RegClass(offset
.type(), 1);
7261 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7262 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7263 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7266 case nir_intrinsic_load_front_face
: {
7267 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7268 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7271 case nir_intrinsic_load_view_index
: {
7272 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7273 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7274 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7280 case nir_intrinsic_load_layer_id
: {
7281 unsigned idx
= nir_intrinsic_base(instr
);
7282 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7283 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7286 case nir_intrinsic_load_frag_coord
: {
7287 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7290 case nir_intrinsic_load_sample_pos
: {
7291 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7292 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7293 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7294 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7295 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7298 case nir_intrinsic_load_tess_coord
:
7299 visit_load_tess_coord(ctx
, instr
);
7301 case nir_intrinsic_load_interpolated_input
:
7302 visit_load_interpolated_input(ctx
, instr
);
7304 case nir_intrinsic_store_output
:
7305 visit_store_output(ctx
, instr
);
7307 case nir_intrinsic_load_input
:
7308 case nir_intrinsic_load_input_vertex
:
7309 visit_load_input(ctx
, instr
);
7311 case nir_intrinsic_load_output
:
7312 visit_load_output(ctx
, instr
);
7314 case nir_intrinsic_load_per_vertex_input
:
7315 visit_load_per_vertex_input(ctx
, instr
);
7317 case nir_intrinsic_load_per_vertex_output
:
7318 visit_load_per_vertex_output(ctx
, instr
);
7320 case nir_intrinsic_store_per_vertex_output
:
7321 visit_store_per_vertex_output(ctx
, instr
);
7323 case nir_intrinsic_load_ubo
:
7324 visit_load_ubo(ctx
, instr
);
7326 case nir_intrinsic_load_push_constant
:
7327 visit_load_push_constant(ctx
, instr
);
7329 case nir_intrinsic_load_constant
:
7330 visit_load_constant(ctx
, instr
);
7332 case nir_intrinsic_vulkan_resource_index
:
7333 visit_load_resource(ctx
, instr
);
7335 case nir_intrinsic_discard
:
7336 visit_discard(ctx
, instr
);
7338 case nir_intrinsic_discard_if
:
7339 visit_discard_if(ctx
, instr
);
7341 case nir_intrinsic_load_shared
:
7342 visit_load_shared(ctx
, instr
);
7344 case nir_intrinsic_store_shared
:
7345 visit_store_shared(ctx
, instr
);
7347 case nir_intrinsic_shared_atomic_add
:
7348 case nir_intrinsic_shared_atomic_imin
:
7349 case nir_intrinsic_shared_atomic_umin
:
7350 case nir_intrinsic_shared_atomic_imax
:
7351 case nir_intrinsic_shared_atomic_umax
:
7352 case nir_intrinsic_shared_atomic_and
:
7353 case nir_intrinsic_shared_atomic_or
:
7354 case nir_intrinsic_shared_atomic_xor
:
7355 case nir_intrinsic_shared_atomic_exchange
:
7356 case nir_intrinsic_shared_atomic_comp_swap
:
7357 visit_shared_atomic(ctx
, instr
);
7359 case nir_intrinsic_image_deref_load
:
7360 visit_image_load(ctx
, instr
);
7362 case nir_intrinsic_image_deref_store
:
7363 visit_image_store(ctx
, instr
);
7365 case nir_intrinsic_image_deref_atomic_add
:
7366 case nir_intrinsic_image_deref_atomic_umin
:
7367 case nir_intrinsic_image_deref_atomic_imin
:
7368 case nir_intrinsic_image_deref_atomic_umax
:
7369 case nir_intrinsic_image_deref_atomic_imax
:
7370 case nir_intrinsic_image_deref_atomic_and
:
7371 case nir_intrinsic_image_deref_atomic_or
:
7372 case nir_intrinsic_image_deref_atomic_xor
:
7373 case nir_intrinsic_image_deref_atomic_exchange
:
7374 case nir_intrinsic_image_deref_atomic_comp_swap
:
7375 visit_image_atomic(ctx
, instr
);
7377 case nir_intrinsic_image_deref_size
:
7378 visit_image_size(ctx
, instr
);
7380 case nir_intrinsic_load_ssbo
:
7381 visit_load_ssbo(ctx
, instr
);
7383 case nir_intrinsic_store_ssbo
:
7384 visit_store_ssbo(ctx
, instr
);
7386 case nir_intrinsic_load_global
:
7387 visit_load_global(ctx
, instr
);
7389 case nir_intrinsic_store_global
:
7390 visit_store_global(ctx
, instr
);
7392 case nir_intrinsic_global_atomic_add
:
7393 case nir_intrinsic_global_atomic_imin
:
7394 case nir_intrinsic_global_atomic_umin
:
7395 case nir_intrinsic_global_atomic_imax
:
7396 case nir_intrinsic_global_atomic_umax
:
7397 case nir_intrinsic_global_atomic_and
:
7398 case nir_intrinsic_global_atomic_or
:
7399 case nir_intrinsic_global_atomic_xor
:
7400 case nir_intrinsic_global_atomic_exchange
:
7401 case nir_intrinsic_global_atomic_comp_swap
:
7402 visit_global_atomic(ctx
, instr
);
7404 case nir_intrinsic_ssbo_atomic_add
:
7405 case nir_intrinsic_ssbo_atomic_imin
:
7406 case nir_intrinsic_ssbo_atomic_umin
:
7407 case nir_intrinsic_ssbo_atomic_imax
:
7408 case nir_intrinsic_ssbo_atomic_umax
:
7409 case nir_intrinsic_ssbo_atomic_and
:
7410 case nir_intrinsic_ssbo_atomic_or
:
7411 case nir_intrinsic_ssbo_atomic_xor
:
7412 case nir_intrinsic_ssbo_atomic_exchange
:
7413 case nir_intrinsic_ssbo_atomic_comp_swap
:
7414 visit_atomic_ssbo(ctx
, instr
);
7416 case nir_intrinsic_load_scratch
:
7417 visit_load_scratch(ctx
, instr
);
7419 case nir_intrinsic_store_scratch
:
7420 visit_store_scratch(ctx
, instr
);
7422 case nir_intrinsic_get_buffer_size
:
7423 visit_get_buffer_size(ctx
, instr
);
7425 case nir_intrinsic_control_barrier
: {
7426 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7427 /* GFX6 only (thanks to a hw bug workaround):
7428 * The real barrier instruction isn’t needed, because an entire patch
7429 * always fits into a single wave.
7434 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7435 bld
.sopp(aco_opcode::s_barrier
);
7439 case nir_intrinsic_memory_barrier_tcs_patch
:
7440 case nir_intrinsic_group_memory_barrier
:
7441 case nir_intrinsic_memory_barrier
:
7442 case nir_intrinsic_memory_barrier_buffer
:
7443 case nir_intrinsic_memory_barrier_image
:
7444 case nir_intrinsic_memory_barrier_shared
:
7445 emit_memory_barrier(ctx
, instr
);
7447 case nir_intrinsic_load_num_work_groups
: {
7448 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7449 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7450 emit_split_vector(ctx
, dst
, 3);
7453 case nir_intrinsic_load_local_invocation_id
: {
7454 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7455 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7456 emit_split_vector(ctx
, dst
, 3);
7459 case nir_intrinsic_load_work_group_id
: {
7460 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7461 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7462 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7463 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7464 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7465 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7466 emit_split_vector(ctx
, dst
, 3);
7469 case nir_intrinsic_load_local_invocation_index
: {
7470 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7472 /* The tg_size bits [6:11] contain the subgroup id,
7473 * we need this multiplied by the wave size, and then OR the thread id to it.
7475 if (ctx
->program
->wave_size
== 64) {
7476 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7477 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7478 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7479 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7481 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7482 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7483 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7484 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7488 case nir_intrinsic_load_subgroup_id
: {
7489 if (ctx
->stage
== compute_cs
) {
7490 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7491 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7493 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7497 case nir_intrinsic_load_subgroup_invocation
: {
7498 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7501 case nir_intrinsic_load_num_subgroups
: {
7502 if (ctx
->stage
== compute_cs
)
7503 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7504 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7506 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7509 case nir_intrinsic_ballot
: {
7510 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7511 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7512 Definition tmp
= bld
.def(dst
.regClass());
7513 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7514 if (instr
->src
[0].ssa
->bit_size
== 1) {
7515 assert(src
.regClass() == bld
.lm
);
7516 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7517 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7518 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7519 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7520 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7523 nir_print_instr(&instr
->instr
, stderr
);
7524 fprintf(stderr
, "\n");
7526 if (dst
.size() != bld
.lm
.size()) {
7527 /* Wave32 with ballot size set to 64 */
7528 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7530 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7533 case nir_intrinsic_shuffle
:
7534 case nir_intrinsic_read_invocation
: {
7535 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7536 if (!nir_src_is_divergent(instr
->src
[0])) {
7537 emit_uniform_subgroup(ctx
, instr
, src
);
7539 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7540 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7541 tid
= bld
.as_uniform(tid
);
7542 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7543 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7544 Temp tmp
= bld
.tmp(v1
);
7545 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7546 if (dst
.type() == RegType::vgpr
)
7547 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7549 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7550 } else if (src
.regClass() == v1
) {
7551 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7552 } else if (src
.regClass() == v2
) {
7553 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7554 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7555 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7556 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7557 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7558 emit_split_vector(ctx
, dst
, 2);
7559 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7560 assert(src
.regClass() == bld
.lm
);
7561 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7562 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7563 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7564 assert(src
.regClass() == bld
.lm
);
7566 if (ctx
->program
->chip_class
<= GFX7
)
7567 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7568 else if (ctx
->program
->wave_size
== 64)
7569 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7571 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7572 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7573 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7574 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7576 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7577 nir_print_instr(&instr
->instr
, stderr
);
7578 fprintf(stderr
, "\n");
7583 case nir_intrinsic_load_sample_id
: {
7584 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7585 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7588 case nir_intrinsic_load_sample_mask_in
: {
7589 visit_load_sample_mask_in(ctx
, instr
);
7592 case nir_intrinsic_read_first_invocation
: {
7593 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7594 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7595 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7597 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7599 } else if (src
.regClass() == v2
) {
7600 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7601 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7602 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7603 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7604 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7605 emit_split_vector(ctx
, dst
, 2);
7606 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7607 assert(src
.regClass() == bld
.lm
);
7608 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7609 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7610 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7611 } else if (src
.regClass() == s1
) {
7612 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7613 } else if (src
.regClass() == s2
) {
7614 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7616 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7617 nir_print_instr(&instr
->instr
, stderr
);
7618 fprintf(stderr
, "\n");
7622 case nir_intrinsic_vote_all
: {
7623 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7624 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7625 assert(src
.regClass() == bld
.lm
);
7626 assert(dst
.regClass() == bld
.lm
);
7628 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7629 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7630 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7633 case nir_intrinsic_vote_any
: {
7634 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7635 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7636 assert(src
.regClass() == bld
.lm
);
7637 assert(dst
.regClass() == bld
.lm
);
7639 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7640 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7643 case nir_intrinsic_reduce
:
7644 case nir_intrinsic_inclusive_scan
:
7645 case nir_intrinsic_exclusive_scan
: {
7646 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7647 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7648 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7649 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7650 nir_intrinsic_cluster_size(instr
) : 0;
7651 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7653 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7654 emit_uniform_subgroup(ctx
, instr
, src
);
7655 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7656 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7658 else if (op
== nir_op_iadd
)
7660 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7662 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7664 switch (instr
->intrinsic
) {
7665 case nir_intrinsic_reduce
:
7666 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7668 case nir_intrinsic_exclusive_scan
:
7669 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7671 case nir_intrinsic_inclusive_scan
:
7672 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7677 } else if (cluster_size
== 1) {
7678 bld
.copy(Definition(dst
), src
);
7680 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7682 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7686 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7687 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7702 unreachable("unknown reduction op");
7708 switch (instr
->intrinsic
) {
7709 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7710 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7711 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7713 unreachable("unknown reduce intrinsic");
7716 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7717 reduce
->operands
[0] = Operand(src
);
7718 // filled in by aco_reduce_assign.cpp, used internally as part of the
7720 assert(dst
.size() == 1 || dst
.size() == 2);
7721 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7722 reduce
->operands
[2] = Operand(v1
.as_linear());
7724 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7725 reduce
->definitions
[0] = Definition(tmp_dst
);
7726 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7727 reduce
->definitions
[2] = Definition();
7728 reduce
->definitions
[3] = Definition(scc
, s1
);
7729 reduce
->definitions
[4] = Definition();
7730 reduce
->reduce_op
= reduce_op
;
7731 reduce
->cluster_size
= cluster_size
;
7732 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7734 emit_wqm(ctx
, tmp_dst
, dst
);
7738 case nir_intrinsic_quad_broadcast
: {
7739 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7740 if (!nir_dest_is_divergent(instr
->dest
)) {
7741 emit_uniform_subgroup(ctx
, instr
, src
);
7743 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7744 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7745 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7747 if (instr
->dest
.ssa
.bit_size
== 1) {
7748 assert(src
.regClass() == bld
.lm
);
7749 assert(dst
.regClass() == bld
.lm
);
7750 uint32_t half_mask
= 0x11111111u
<< lane
;
7751 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7752 Temp tmp
= bld
.tmp(bld
.lm
);
7753 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7754 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7755 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7756 emit_wqm(ctx
, tmp
, dst
);
7757 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7758 Temp tmp
= bld
.tmp(v1
);
7759 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7760 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7761 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7762 Temp tmp
= bld
.tmp(v1
);
7763 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7765 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7766 if (ctx
->program
->chip_class
>= GFX8
)
7767 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7769 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7770 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7771 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7773 if (ctx
->program
->chip_class
>= GFX8
) {
7774 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7775 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7777 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7778 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7780 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7781 emit_split_vector(ctx
, dst
, 2);
7783 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7784 nir_print_instr(&instr
->instr
, stderr
);
7785 fprintf(stderr
, "\n");
7790 case nir_intrinsic_quad_swap_horizontal
:
7791 case nir_intrinsic_quad_swap_vertical
:
7792 case nir_intrinsic_quad_swap_diagonal
:
7793 case nir_intrinsic_quad_swizzle_amd
: {
7794 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7795 if (!nir_dest_is_divergent(instr
->dest
)) {
7796 emit_uniform_subgroup(ctx
, instr
, src
);
7799 uint16_t dpp_ctrl
= 0;
7800 switch (instr
->intrinsic
) {
7801 case nir_intrinsic_quad_swap_horizontal
:
7802 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7804 case nir_intrinsic_quad_swap_vertical
:
7805 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7807 case nir_intrinsic_quad_swap_diagonal
:
7808 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7810 case nir_intrinsic_quad_swizzle_amd
:
7811 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7816 if (ctx
->program
->chip_class
< GFX8
)
7817 dpp_ctrl
|= (1 << 15);
7819 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7820 if (instr
->dest
.ssa
.bit_size
== 1) {
7821 assert(src
.regClass() == bld
.lm
);
7822 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7823 if (ctx
->program
->chip_class
>= GFX8
)
7824 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7826 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7827 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7828 emit_wqm(ctx
, tmp
, dst
);
7829 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7830 Temp tmp
= bld
.tmp(v1
);
7831 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7832 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7833 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7834 Temp tmp
= bld
.tmp(v1
);
7835 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7837 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7839 if (ctx
->program
->chip_class
>= GFX8
)
7840 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7842 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7843 emit_wqm(ctx
, tmp
, dst
);
7844 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7845 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7846 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7847 if (ctx
->program
->chip_class
>= GFX8
) {
7848 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7849 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7851 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7852 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7854 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7855 emit_split_vector(ctx
, dst
, 2);
7857 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7858 nir_print_instr(&instr
->instr
, stderr
);
7859 fprintf(stderr
, "\n");
7863 case nir_intrinsic_masked_swizzle_amd
: {
7864 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7865 if (!nir_dest_is_divergent(instr
->dest
)) {
7866 emit_uniform_subgroup(ctx
, instr
, src
);
7869 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7870 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7871 if (dst
.regClass() == v1
) {
7873 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7875 } else if (dst
.regClass() == v2
) {
7876 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7878 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7879 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7880 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7881 emit_split_vector(ctx
, dst
, 2);
7883 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7884 nir_print_instr(&instr
->instr
, stderr
);
7885 fprintf(stderr
, "\n");
7889 case nir_intrinsic_write_invocation_amd
: {
7890 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7891 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7892 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7893 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7894 if (dst
.regClass() == v1
) {
7895 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7896 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7897 } else if (dst
.regClass() == v2
) {
7898 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7899 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7901 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7902 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7903 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7904 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7905 emit_split_vector(ctx
, dst
, 2);
7907 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7908 nir_print_instr(&instr
->instr
, stderr
);
7909 fprintf(stderr
, "\n");
7913 case nir_intrinsic_mbcnt_amd
: {
7914 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7915 RegClass rc
= RegClass(src
.type(), 1);
7916 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7917 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7918 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7919 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7920 emit_wqm(ctx
, wqm_tmp
, dst
);
7923 case nir_intrinsic_load_helper_invocation
: {
7924 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7925 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7926 ctx
->block
->kind
|= block_kind_needs_lowering
;
7927 ctx
->program
->needs_exact
= true;
7930 case nir_intrinsic_is_helper_invocation
: {
7931 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7932 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7933 ctx
->block
->kind
|= block_kind_needs_lowering
;
7934 ctx
->program
->needs_exact
= true;
7937 case nir_intrinsic_demote
:
7938 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7940 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7941 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7942 ctx
->block
->kind
|= block_kind_uses_demote
;
7943 ctx
->program
->needs_exact
= true;
7945 case nir_intrinsic_demote_if
: {
7946 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7947 assert(src
.regClass() == bld
.lm
);
7948 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7949 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7951 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7952 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7953 ctx
->block
->kind
|= block_kind_uses_demote
;
7954 ctx
->program
->needs_exact
= true;
7957 case nir_intrinsic_first_invocation
: {
7958 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7959 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7962 case nir_intrinsic_shader_clock
: {
7964 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7965 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7966 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7967 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7970 case nir_intrinsic_load_vertex_id_zero_base
: {
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7975 case nir_intrinsic_load_first_vertex
: {
7976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7977 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7980 case nir_intrinsic_load_base_instance
: {
7981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7985 case nir_intrinsic_load_instance_id
: {
7986 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7987 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7990 case nir_intrinsic_load_draw_id
: {
7991 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7992 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7995 case nir_intrinsic_load_invocation_id
: {
7996 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7998 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7999 if (ctx
->options
->chip_class
>= GFX10
)
8000 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8002 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8003 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8004 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8005 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8007 unreachable("Unsupported stage for load_invocation_id");
8012 case nir_intrinsic_load_primitive_id
: {
8013 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8015 switch (ctx
->shader
->info
.stage
) {
8016 case MESA_SHADER_GEOMETRY
:
8017 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8019 case MESA_SHADER_TESS_CTRL
:
8020 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8022 case MESA_SHADER_TESS_EVAL
:
8023 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8026 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8031 case nir_intrinsic_load_patch_vertices_in
: {
8032 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8033 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8035 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8036 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8039 case nir_intrinsic_emit_vertex_with_counter
: {
8040 visit_emit_vertex_with_counter(ctx
, instr
);
8043 case nir_intrinsic_end_primitive_with_counter
: {
8044 unsigned stream
= nir_intrinsic_stream_id(instr
);
8045 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8048 case nir_intrinsic_set_vertex_count
: {
8049 /* unused, the HW keeps track of this for us */
8053 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8054 nir_print_instr(&instr
->instr
, stderr
);
8055 fprintf(stderr
, "\n");
8063 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8064 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8065 enum glsl_base_type
*stype
)
8067 nir_deref_instr
*texture_deref_instr
= NULL
;
8068 nir_deref_instr
*sampler_deref_instr
= NULL
;
8071 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8072 switch (instr
->src
[i
].src_type
) {
8073 case nir_tex_src_texture_deref
:
8074 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8076 case nir_tex_src_sampler_deref
:
8077 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8079 case nir_tex_src_plane
:
8080 plane
= nir_src_as_int(instr
->src
[i
].src
);
8087 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8089 if (!sampler_deref_instr
)
8090 sampler_deref_instr
= texture_deref_instr
;
8093 assert(instr
->op
!= nir_texop_txf_ms
&&
8094 instr
->op
!= nir_texop_samples_identical
);
8095 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8096 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8097 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8098 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8099 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8100 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8102 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8105 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8107 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8108 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8109 Builder
bld(ctx
->program
, ctx
->block
);
8111 /* to avoid unnecessary moves, we split and recombine sampler and image */
8112 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8113 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8114 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8115 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8116 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8117 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8118 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8119 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8121 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8122 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8123 img
[0], img
[1], img
[2], img
[3],
8124 img
[4], img
[5], img
[6], img
[7]);
8125 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8126 samp
[0], samp
[1], samp
[2], samp
[3]);
8129 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8130 instr
->op
== nir_texop_samples_identical
))
8131 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8134 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8135 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8137 Builder
bld(ctx
->program
, ctx
->block
);
8139 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8140 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8141 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8143 Operand
neg_one(0xbf800000u
);
8144 Operand
one(0x3f800000u
);
8145 Operand
two(0x40000000u
);
8146 Operand
four(0x40800000u
);
8148 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8149 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8150 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8152 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8153 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8154 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8155 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8158 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8159 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8160 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8162 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8165 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8166 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8167 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8170 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8171 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8173 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8174 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8177 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8179 Builder
bld(ctx
->program
, ctx
->block
);
8180 Temp ma
, tc
, sc
, id
;
8183 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8185 // see comment in ac_prepare_cube_coords()
8186 if (ctx
->options
->chip_class
<= GFX8
)
8187 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8190 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8192 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8193 vop3a
->operands
[0] = Operand(ma
);
8194 vop3a
->abs
[0] = true;
8195 Temp invma
= bld
.tmp(v1
);
8196 vop3a
->definitions
[0] = Definition(invma
);
8197 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8199 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8201 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8203 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8205 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8207 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8210 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8211 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8213 for (unsigned i
= 0; i
< 2; i
++) {
8214 // see comment in ac_prepare_cube_coords()
8216 Temp deriv_sc
, deriv_tc
;
8217 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8218 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8220 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8222 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8223 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8224 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8225 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8226 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8227 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8228 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8231 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8232 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8236 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8243 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8245 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8247 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8248 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8251 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8252 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8253 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8257 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8259 Builder
bld(ctx
->program
, ctx
->block
);
8260 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8261 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8262 has_clamped_lod
= false;
8263 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8264 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8265 clamped_lod
= Temp();
8266 std::vector
<Temp
> coords
;
8267 std::vector
<Temp
> derivs
;
8268 nir_const_value
*sample_index_cv
= NULL
;
8269 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8270 enum glsl_base_type stype
;
8271 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8273 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8274 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8275 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8276 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8278 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8279 switch (instr
->src
[i
].src_type
) {
8280 case nir_tex_src_coord
: {
8281 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8282 for (unsigned i
= 0; i
< coord
.size(); i
++)
8283 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8286 case nir_tex_src_bias
:
8287 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8290 case nir_tex_src_lod
: {
8291 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8293 if (val
&& val
->f32
<= 0.0) {
8296 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8301 case nir_tex_src_min_lod
:
8302 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8303 has_clamped_lod
= true;
8305 case nir_tex_src_comparator
:
8306 if (instr
->is_shadow
) {
8307 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8311 case nir_tex_src_offset
:
8312 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8313 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8316 case nir_tex_src_ddx
:
8317 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8320 case nir_tex_src_ddy
:
8321 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8324 case nir_tex_src_ms_index
:
8325 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8326 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8327 has_sample_index
= true;
8329 case nir_tex_src_texture_offset
:
8330 case nir_tex_src_sampler_offset
:
8336 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8337 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8339 if (instr
->op
== nir_texop_texture_samples
) {
8340 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8342 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8343 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8344 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8346 Operand default_sample
= Operand(1u);
8347 if (ctx
->options
->robust_buffer_access
) {
8348 /* Extract the second dword of the descriptor, if it's
8349 * all zero, then it's a null descriptor.
8351 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8352 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8353 default_sample
= Operand(is_non_null_descriptor
);
8356 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8357 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8358 samples
, default_sample
, bld
.scc(is_msaa
));
8362 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8363 aco_ptr
<Instruction
> tmp_instr
;
8364 Temp acc
, pack
= Temp();
8366 uint32_t pack_const
= 0;
8367 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8368 if (!const_offset
[i
])
8370 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8373 if (offset
.type() == RegType::sgpr
) {
8374 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8375 if (const_offset
[i
])
8378 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8379 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8382 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8385 if (pack
== Temp()) {
8388 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8392 if (pack_const
&& pack
!= Temp())
8393 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8395 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8396 if (const_offset
[i
])
8399 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8400 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8403 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8406 if (pack
== Temp()) {
8409 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8413 if (pack_const
&& pack
!= Temp())
8414 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8416 if (pack_const
&& pack
== Temp())
8417 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8418 else if (pack
== Temp())
8424 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8425 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8427 /* pack derivatives */
8428 if (has_ddx
|| has_ddy
) {
8429 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8430 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8431 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8432 derivs
= {ddx
, zero
, ddy
, zero
};
8434 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8435 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8436 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8437 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8442 if (instr
->coord_components
> 1 &&
8443 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8445 instr
->op
!= nir_texop_txf
)
8446 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8448 if (instr
->coord_components
> 2 &&
8449 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8450 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8451 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8452 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8454 instr
->op
!= nir_texop_txf
&&
8455 instr
->op
!= nir_texop_txf_ms
&&
8456 instr
->op
!= nir_texop_fragment_fetch
&&
8457 instr
->op
!= nir_texop_fragment_mask_fetch
)
8458 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8460 if (ctx
->options
->chip_class
== GFX9
&&
8461 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8462 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8463 assert(coords
.size() > 0 && coords
.size() < 3);
8465 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8466 Operand((uint32_t) 0) :
8467 Operand((uint32_t) 0x3f000000)));
8470 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8472 if (instr
->op
== nir_texop_samples_identical
)
8473 resource
= fmask_ptr
;
8475 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8476 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8477 instr
->op
!= nir_texop_txs
&&
8478 instr
->op
!= nir_texop_fragment_fetch
&&
8479 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8480 assert(has_sample_index
);
8481 Operand
op(sample_index
);
8482 if (sample_index_cv
)
8483 op
= Operand(sample_index_cv
->u32
);
8484 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8487 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8488 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8489 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8490 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8495 /* Build tex instruction */
8496 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8497 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8498 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8500 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8503 /* gather4 selects the component by dmask and always returns vec4 */
8504 if (instr
->op
== nir_texop_tg4
) {
8505 assert(instr
->dest
.ssa
.num_components
== 4);
8506 if (instr
->is_shadow
)
8509 dmask
= 1 << instr
->component
;
8510 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8511 tmp_dst
= bld
.tmp(v4
);
8512 } else if (instr
->op
== nir_texop_samples_identical
) {
8513 tmp_dst
= bld
.tmp(v1
);
8514 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8515 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8518 aco_ptr
<MIMG_instruction
> tex
;
8519 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8521 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8523 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8524 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8527 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8528 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8530 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8531 tex
->operands
[0] = Operand(resource
);
8532 tex
->operands
[1] = Operand(s4
); /* no sampler */
8533 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8534 if (ctx
->options
->chip_class
== GFX9
&&
8535 instr
->op
== nir_texop_txs
&&
8536 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8538 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8539 } else if (instr
->op
== nir_texop_query_levels
) {
8540 tex
->dmask
= 1 << 3;
8545 tex
->definitions
[0] = Definition(tmp_dst
);
8547 tex
->can_reorder
= true;
8548 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8551 /* divide 3rd value by 6 by multiplying with magic number */
8552 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8553 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8554 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8555 assert(instr
->dest
.ssa
.num_components
== 3);
8556 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8557 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8558 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8559 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8564 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8568 Temp tg4_compare_cube_wa64
= Temp();
8570 if (tg4_integer_workarounds
) {
8571 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8572 tex
->operands
[0] = Operand(resource
);
8573 tex
->operands
[1] = Operand(s4
); /* no sampler */
8574 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8578 Temp size
= bld
.tmp(v2
);
8579 tex
->definitions
[0] = Definition(size
);
8580 tex
->can_reorder
= true;
8581 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8582 emit_split_vector(ctx
, size
, size
.size());
8585 for (unsigned i
= 0; i
< 2; i
++) {
8586 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8587 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8588 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8589 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8592 Temp new_coords
[2] = {
8593 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8594 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8597 if (tg4_integer_cube_workaround
) {
8598 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8599 Temp desc
[resource
.size()];
8600 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8601 Format::PSEUDO
, 1, resource
.size())};
8602 split
->operands
[0] = Operand(resource
);
8603 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8604 desc
[i
] = bld
.tmp(s1
);
8605 split
->definitions
[i
] = Definition(desc
[i
]);
8607 ctx
->block
->instructions
.emplace_back(std::move(split
));
8609 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8610 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8611 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8614 if (stype
== GLSL_TYPE_UINT
) {
8615 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8616 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8617 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8618 bld
.scc(compare_cube_wa
));
8620 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8621 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8622 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8623 bld
.scc(compare_cube_wa
));
8625 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8626 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8628 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8630 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8631 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8632 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8634 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8635 Format::PSEUDO
, resource
.size(), 1)};
8636 for (unsigned i
= 0; i
< resource
.size(); i
++)
8637 vec
->operands
[i
] = Operand(desc
[i
]);
8638 resource
= bld
.tmp(resource
.regClass());
8639 vec
->definitions
[0] = Definition(resource
);
8640 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8642 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8643 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8644 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8645 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8647 coords
[0] = new_coords
[0];
8648 coords
[1] = new_coords
[1];
8651 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8652 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8654 assert(coords
.size() == 1);
8655 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8659 op
= aco_opcode::buffer_load_format_x
; break;
8661 op
= aco_opcode::buffer_load_format_xy
; break;
8663 op
= aco_opcode::buffer_load_format_xyz
; break;
8665 op
= aco_opcode::buffer_load_format_xyzw
; break;
8667 unreachable("Tex instruction loads more than 4 components.");
8670 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8671 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8674 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8676 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8677 mubuf
->operands
[0] = Operand(resource
);
8678 mubuf
->operands
[1] = Operand(coords
[0]);
8679 mubuf
->operands
[2] = Operand((uint32_t) 0);
8680 mubuf
->definitions
[0] = Definition(tmp_dst
);
8681 mubuf
->idxen
= true;
8682 mubuf
->can_reorder
= true;
8683 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8685 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8689 /* gather MIMG address components */
8690 std::vector
<Temp
> args
;
8692 args
.emplace_back(offset
);
8694 args
.emplace_back(bias
);
8696 args
.emplace_back(compare
);
8698 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8700 args
.insert(args
.end(), coords
.begin(), coords
.end());
8701 if (has_sample_index
)
8702 args
.emplace_back(sample_index
);
8704 args
.emplace_back(lod
);
8705 if (has_clamped_lod
)
8706 args
.emplace_back(clamped_lod
);
8708 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8709 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8710 vec
->definitions
[0] = Definition(arg
);
8711 for (unsigned i
= 0; i
< args
.size(); i
++)
8712 vec
->operands
[i
] = Operand(args
[i
]);
8713 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8716 if (instr
->op
== nir_texop_txf
||
8717 instr
->op
== nir_texop_txf_ms
||
8718 instr
->op
== nir_texop_samples_identical
||
8719 instr
->op
== nir_texop_fragment_fetch
||
8720 instr
->op
== nir_texop_fragment_mask_fetch
) {
8721 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8722 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8723 tex
->operands
[0] = Operand(resource
);
8724 tex
->operands
[1] = Operand(s4
); /* no sampler */
8725 tex
->operands
[2] = Operand(arg
);
8730 tex
->definitions
[0] = Definition(tmp_dst
);
8731 tex
->can_reorder
= true;
8732 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8734 if (instr
->op
== nir_texop_samples_identical
) {
8735 assert(dmask
== 1 && dst
.regClass() == v1
);
8736 assert(dst
.id() != tmp_dst
.id());
8738 Temp tmp
= bld
.tmp(bld
.lm
);
8739 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8740 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8743 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8748 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8749 aco_opcode opcode
= aco_opcode::image_sample
;
8750 if (has_offset
) { /* image_sample_*_o */
8751 if (has_clamped_lod
) {
8753 opcode
= aco_opcode::image_sample_c_cl_o
;
8755 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8757 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8759 opcode
= aco_opcode::image_sample_cl_o
;
8761 opcode
= aco_opcode::image_sample_d_cl_o
;
8763 opcode
= aco_opcode::image_sample_b_cl_o
;
8765 } else if (has_compare
) {
8766 opcode
= aco_opcode::image_sample_c_o
;
8768 opcode
= aco_opcode::image_sample_c_d_o
;
8770 opcode
= aco_opcode::image_sample_c_b_o
;
8772 opcode
= aco_opcode::image_sample_c_lz_o
;
8774 opcode
= aco_opcode::image_sample_c_l_o
;
8776 opcode
= aco_opcode::image_sample_o
;
8778 opcode
= aco_opcode::image_sample_d_o
;
8780 opcode
= aco_opcode::image_sample_b_o
;
8782 opcode
= aco_opcode::image_sample_lz_o
;
8784 opcode
= aco_opcode::image_sample_l_o
;
8786 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8788 opcode
= aco_opcode::image_sample_c_cl
;
8790 opcode
= aco_opcode::image_sample_c_d_cl
;
8792 opcode
= aco_opcode::image_sample_c_b_cl
;
8794 opcode
= aco_opcode::image_sample_cl
;
8796 opcode
= aco_opcode::image_sample_d_cl
;
8798 opcode
= aco_opcode::image_sample_b_cl
;
8800 } else { /* no offset */
8802 opcode
= aco_opcode::image_sample_c
;
8804 opcode
= aco_opcode::image_sample_c_d
;
8806 opcode
= aco_opcode::image_sample_c_b
;
8808 opcode
= aco_opcode::image_sample_c_lz
;
8810 opcode
= aco_opcode::image_sample_c_l
;
8812 opcode
= aco_opcode::image_sample
;
8814 opcode
= aco_opcode::image_sample_d
;
8816 opcode
= aco_opcode::image_sample_b
;
8818 opcode
= aco_opcode::image_sample_lz
;
8820 opcode
= aco_opcode::image_sample_l
;
8824 if (instr
->op
== nir_texop_tg4
) {
8825 if (has_offset
) { /* image_gather4_*_o */
8827 opcode
= aco_opcode::image_gather4_c_lz_o
;
8829 opcode
= aco_opcode::image_gather4_c_l_o
;
8831 opcode
= aco_opcode::image_gather4_c_b_o
;
8833 opcode
= aco_opcode::image_gather4_lz_o
;
8835 opcode
= aco_opcode::image_gather4_l_o
;
8837 opcode
= aco_opcode::image_gather4_b_o
;
8841 opcode
= aco_opcode::image_gather4_c_lz
;
8843 opcode
= aco_opcode::image_gather4_c_l
;
8845 opcode
= aco_opcode::image_gather4_c_b
;
8847 opcode
= aco_opcode::image_gather4_lz
;
8849 opcode
= aco_opcode::image_gather4_l
;
8851 opcode
= aco_opcode::image_gather4_b
;
8854 } else if (instr
->op
== nir_texop_lod
) {
8855 opcode
= aco_opcode::image_get_lod
;
8858 /* we don't need the bias, sample index, compare value or offset to be
8859 * computed in WQM but if the p_create_vector copies the coordinates, then it
8860 * needs to be in WQM */
8861 if (ctx
->stage
== fragment_fs
&&
8862 !has_derivs
&& !has_lod
&& !level_zero
&&
8863 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8864 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8865 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8867 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8868 tex
->operands
[0] = Operand(resource
);
8869 tex
->operands
[1] = Operand(sampler
);
8870 tex
->operands
[2] = Operand(arg
);
8874 tex
->definitions
[0] = Definition(tmp_dst
);
8875 tex
->can_reorder
= true;
8876 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8878 if (tg4_integer_cube_workaround
) {
8879 assert(tmp_dst
.id() != dst
.id());
8880 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8882 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8884 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8885 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8887 if (stype
== GLSL_TYPE_UINT
)
8888 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8890 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8891 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8893 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8894 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8895 val
[0], val
[1], val
[2], val
[3]);
8897 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8898 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8903 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8905 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8906 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8907 return Operand(tmp
.regClass());
8909 return Operand(tmp
);
8912 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8914 aco_ptr
<Pseudo_instruction
> phi
;
8915 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8916 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8918 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8919 logical
|= ctx
->block
->kind
& block_kind_merge
;
8920 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8922 /* we want a sorted list of sources, since the predecessor list is also sorted */
8923 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8924 nir_foreach_phi_src(src
, instr
)
8925 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8927 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8928 unsigned num_operands
= 0;
8929 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8930 unsigned num_defined
= 0;
8931 unsigned cur_pred_idx
= 0;
8932 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8933 if (cur_pred_idx
< preds
.size()) {
8934 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8935 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8936 unsigned skipped
= 0;
8937 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8939 if (cur_pred_idx
+ skipped
< preds
.size()) {
8940 for (unsigned i
= 0; i
< skipped
; i
++)
8941 operands
[num_operands
++] = Operand(dst
.regClass());
8942 cur_pred_idx
+= skipped
;
8947 /* Handle missing predecessors at the end. This shouldn't happen with loop
8948 * headers and we can't ignore these sources for loop header phis. */
8949 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8952 Operand op
= get_phi_operand(ctx
, src
.second
);
8953 operands
[num_operands
++] = op
;
8954 num_defined
+= !op
.isUndefined();
8956 /* handle block_kind_continue_or_break at loop exit blocks */
8957 while (cur_pred_idx
++ < preds
.size())
8958 operands
[num_operands
++] = Operand(dst
.regClass());
8960 /* If the loop ends with a break, still add a linear continue edge in case
8961 * that break is divergent or continue_or_break is used. We'll either remove
8962 * this operand later in visit_loop() if it's not necessary or replace the
8963 * undef with something correct. */
8964 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8965 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8966 nir_block
*last
= nir_loop_last_block(loop
);
8967 if (last
->successors
[0] != instr
->instr
.block
)
8968 operands
[num_operands
++] = Operand(RegClass());
8971 if (num_defined
== 0) {
8972 Builder
bld(ctx
->program
, ctx
->block
);
8973 if (dst
.regClass() == s1
) {
8974 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8975 } else if (dst
.regClass() == v1
) {
8976 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8978 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8979 for (unsigned i
= 0; i
< dst
.size(); i
++)
8980 vec
->operands
[i
] = Operand(0u);
8981 vec
->definitions
[0] = Definition(dst
);
8982 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8987 /* we can use a linear phi in some cases if one src is undef */
8988 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8989 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8991 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8992 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8993 assert(invert
->kind
& block_kind_invert
);
8995 unsigned then_block
= invert
->linear_preds
[0];
8997 Block
* insert_block
= NULL
;
8998 for (unsigned i
= 0; i
< num_operands
; i
++) {
8999 Operand op
= operands
[i
];
9000 if (op
.isUndefined())
9002 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9003 phi
->operands
[0] = op
;
9006 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9007 phi
->operands
[1] = Operand(dst
.regClass());
9008 phi
->definitions
[0] = Definition(dst
);
9009 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9013 /* try to scalarize vector phis */
9014 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9015 // TODO: scalarize linear phis on divergent ifs
9016 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9017 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9018 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9019 Operand src
= operands
[i
];
9020 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9021 can_scalarize
= false;
9023 if (can_scalarize
) {
9024 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9025 assert(dst
.size() % num_components
== 0);
9026 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9028 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9029 for (unsigned k
= 0; k
< num_components
; k
++) {
9030 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9031 for (unsigned i
= 0; i
< num_operands
; i
++) {
9032 Operand src
= operands
[i
];
9033 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9035 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9036 phi
->definitions
[0] = Definition(phi_dst
);
9037 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9038 new_vec
[k
] = phi_dst
;
9039 vec
->operands
[k
] = Operand(phi_dst
);
9041 vec
->definitions
[0] = Definition(dst
);
9042 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9043 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9048 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9049 for (unsigned i
= 0; i
< num_operands
; i
++)
9050 phi
->operands
[i
] = operands
[i
];
9051 phi
->definitions
[0] = Definition(dst
);
9052 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9056 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9058 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9060 assert(dst
.type() == RegType::sgpr
);
9062 if (dst
.size() == 1) {
9063 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9065 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9066 for (unsigned i
= 0; i
< dst
.size(); i
++)
9067 vec
->operands
[i
] = Operand(0u);
9068 vec
->definitions
[0] = Definition(dst
);
9069 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9073 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9075 Builder
bld(ctx
->program
, ctx
->block
);
9076 Block
*logical_target
;
9077 append_logical_end(ctx
->block
);
9078 unsigned idx
= ctx
->block
->index
;
9080 switch (instr
->type
) {
9081 case nir_jump_break
:
9082 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9083 add_logical_edge(idx
, logical_target
);
9084 ctx
->block
->kind
|= block_kind_break
;
9086 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9087 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9088 /* uniform break - directly jump out of the loop */
9089 ctx
->block
->kind
|= block_kind_uniform
;
9090 ctx
->cf_info
.has_branch
= true;
9091 bld
.branch(aco_opcode::p_branch
);
9092 add_linear_edge(idx
, logical_target
);
9095 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9096 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9098 case nir_jump_continue
:
9099 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9100 add_logical_edge(idx
, logical_target
);
9101 ctx
->block
->kind
|= block_kind_continue
;
9103 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9104 /* for potential uniform breaks after this continue,
9105 we must ensure that they are handled correctly */
9106 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9107 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9108 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9110 /* uniform continue - directly jump to the loop header */
9111 ctx
->block
->kind
|= block_kind_uniform
;
9112 ctx
->cf_info
.has_branch
= true;
9113 bld
.branch(aco_opcode::p_branch
);
9114 add_linear_edge(idx
, logical_target
);
9119 fprintf(stderr
, "Unknown NIR jump instr: ");
9120 nir_print_instr(&instr
->instr
, stderr
);
9121 fprintf(stderr
, "\n");
9125 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9126 ctx
->cf_info
.exec_potentially_empty_break
= true;
9127 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9130 /* remove critical edges from linear CFG */
9131 bld
.branch(aco_opcode::p_branch
);
9132 Block
* break_block
= ctx
->program
->create_and_insert_block();
9133 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9134 break_block
->kind
|= block_kind_uniform
;
9135 add_linear_edge(idx
, break_block
);
9136 /* the loop_header pointer might be invalidated by this point */
9137 if (instr
->type
== nir_jump_continue
)
9138 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9139 add_linear_edge(break_block
->index
, logical_target
);
9140 bld
.reset(break_block
);
9141 bld
.branch(aco_opcode::p_branch
);
9143 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9144 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9145 add_linear_edge(idx
, continue_block
);
9146 append_logical_start(continue_block
);
9147 ctx
->block
= continue_block
;
9151 void visit_block(isel_context
*ctx
, nir_block
*block
)
9153 nir_foreach_instr(instr
, block
) {
9154 switch (instr
->type
) {
9155 case nir_instr_type_alu
:
9156 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9158 case nir_instr_type_load_const
:
9159 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9161 case nir_instr_type_intrinsic
:
9162 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9164 case nir_instr_type_tex
:
9165 visit_tex(ctx
, nir_instr_as_tex(instr
));
9167 case nir_instr_type_phi
:
9168 visit_phi(ctx
, nir_instr_as_phi(instr
));
9170 case nir_instr_type_ssa_undef
:
9171 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9173 case nir_instr_type_deref
:
9175 case nir_instr_type_jump
:
9176 visit_jump(ctx
, nir_instr_as_jump(instr
));
9179 fprintf(stderr
, "Unknown NIR instr type: ");
9180 nir_print_instr(instr
, stderr
);
9181 fprintf(stderr
, "\n");
9186 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9187 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9192 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9193 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9195 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9196 RegClass rc
= vals
[0].regClass();
9198 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9200 unsigned next_pred
= 1;
9202 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9203 Block
& block
= ctx
->program
->blocks
[idx
];
9204 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9205 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9209 if (block
.kind
& block_kind_continue
) {
9210 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9215 bool all_same
= true;
9216 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9217 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9221 val
= vals
[block
.linear_preds
[0] - first
];
9223 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9224 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9225 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9226 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9227 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9228 phi
->definitions
[0] = Definition(val
.getTemp());
9229 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9231 vals
[idx
- first
] = val
;
9234 return vals
[last
- first
];
9237 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9239 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9240 append_logical_end(ctx
->block
);
9241 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9242 Builder
bld(ctx
->program
, ctx
->block
);
9243 bld
.branch(aco_opcode::p_branch
);
9244 unsigned loop_preheader_idx
= ctx
->block
->index
;
9246 Block loop_exit
= Block();
9247 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9248 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9250 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9251 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9252 loop_header
->kind
|= block_kind_loop_header
;
9253 add_edge(loop_preheader_idx
, loop_header
);
9254 ctx
->block
= loop_header
;
9256 /* emit loop body */
9257 unsigned loop_header_idx
= loop_header
->index
;
9258 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9259 append_logical_start(ctx
->block
);
9260 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9262 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9263 if (!ctx
->cf_info
.has_branch
) {
9264 append_logical_end(ctx
->block
);
9265 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9266 /* Discards can result in code running with an empty exec mask.
9267 * This would result in divergent breaks not ever being taken. As a
9268 * workaround, break the loop when the loop mask is empty instead of
9269 * always continuing. */
9270 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9271 unsigned block_idx
= ctx
->block
->index
;
9273 /* create helper blocks to avoid critical edges */
9274 Block
*break_block
= ctx
->program
->create_and_insert_block();
9275 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9276 break_block
->kind
= block_kind_uniform
;
9277 bld
.reset(break_block
);
9278 bld
.branch(aco_opcode::p_branch
);
9279 add_linear_edge(block_idx
, break_block
);
9280 add_linear_edge(break_block
->index
, &loop_exit
);
9282 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9283 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9284 continue_block
->kind
= block_kind_uniform
;
9285 bld
.reset(continue_block
);
9286 bld
.branch(aco_opcode::p_branch
);
9287 add_linear_edge(block_idx
, continue_block
);
9288 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9290 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9291 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9292 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9294 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9295 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9296 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9298 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9301 bld
.reset(ctx
->block
);
9302 bld
.branch(aco_opcode::p_branch
);
9305 /* Fixup phis in loop header from unreachable blocks.
9306 * has_branch/has_divergent_branch also indicates if the loop ends with a
9307 * break/continue instruction, but we don't emit those if unreachable=true */
9309 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9310 bool linear
= ctx
->cf_info
.has_branch
;
9311 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9312 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9313 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9314 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9315 /* the last operand should be the one that needs to be removed */
9316 instr
->operands
.pop_back();
9317 } else if (!is_phi(instr
)) {
9323 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9324 * and the previous one shouldn't both happen at once because a break in the
9325 * merge block would get CSE'd */
9326 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9327 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9328 Operand vals
[num_vals
];
9329 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9330 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9331 if (ctx
->cf_info
.has_branch
)
9332 instr
->operands
.pop_back();
9334 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9335 } else if (!is_phi(instr
)) {
9341 ctx
->cf_info
.has_branch
= false;
9343 // TODO: if the loop has not a single exit, we must add one °°
9344 /* emit loop successor block */
9345 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9346 append_logical_start(ctx
->block
);
9349 // TODO: check if it is beneficial to not branch on continues
9350 /* trim linear phis in loop header */
9351 for (auto&& instr
: loop_entry
->instructions
) {
9352 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9353 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9354 new_phi
->definitions
[0] = instr
->definitions
[0];
9355 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9356 new_phi
->operands
[i
] = instr
->operands
[i
];
9357 /* check that the remaining operands are all the same */
9358 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9359 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9360 instr
.swap(new_phi
);
9361 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9370 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9374 append_logical_end(ctx
->block
);
9375 ctx
->block
->kind
|= block_kind_branch
;
9377 /* branch to linear then block */
9378 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9379 aco_ptr
<Pseudo_branch_instruction
> branch
;
9380 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9381 branch
->operands
[0] = Operand(cond
);
9382 ctx
->block
->instructions
.push_back(std::move(branch
));
9384 ic
->BB_if_idx
= ctx
->block
->index
;
9385 ic
->BB_invert
= Block();
9386 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9387 /* Invert blocks are intentionally not marked as top level because they
9388 * are not part of the logical cfg. */
9389 ic
->BB_invert
.kind
|= block_kind_invert
;
9390 ic
->BB_endif
= Block();
9391 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9392 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9394 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9395 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9396 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9397 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9398 ctx
->cf_info
.parent_if
.is_divergent
= true;
9400 /* divergent branches use cbranch_execz */
9401 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9402 ctx
->cf_info
.exec_potentially_empty_break
= false;
9403 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9405 /** emit logical then block */
9406 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9407 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9408 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9409 ctx
->block
= BB_then_logical
;
9410 append_logical_start(BB_then_logical
);
9413 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9415 Block
*BB_then_logical
= ctx
->block
;
9416 append_logical_end(BB_then_logical
);
9417 /* branch from logical then block to invert block */
9418 aco_ptr
<Pseudo_branch_instruction
> branch
;
9419 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9420 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9421 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9422 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9423 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9424 BB_then_logical
->kind
|= block_kind_uniform
;
9425 assert(!ctx
->cf_info
.has_branch
);
9426 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9427 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9429 /** emit linear then block */
9430 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9431 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9432 BB_then_linear
->kind
|= block_kind_uniform
;
9433 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9434 /* branch from linear then block to invert block */
9435 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9436 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9437 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9439 /** emit invert merge block */
9440 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9441 ic
->invert_idx
= ctx
->block
->index
;
9443 /* branch to linear else block (skip else) */
9444 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9445 branch
->operands
[0] = Operand(ic
->cond
);
9446 ctx
->block
->instructions
.push_back(std::move(branch
));
9448 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9449 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9450 ic
->exec_potentially_empty_break_depth_old
=
9451 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9452 /* divergent branches use cbranch_execz */
9453 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9454 ctx
->cf_info
.exec_potentially_empty_break
= false;
9455 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9457 /** emit logical else block */
9458 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9459 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9460 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9461 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9462 ctx
->block
= BB_else_logical
;
9463 append_logical_start(BB_else_logical
);
9466 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9468 Block
*BB_else_logical
= ctx
->block
;
9469 append_logical_end(BB_else_logical
);
9471 /* branch from logical else block to endif block */
9472 aco_ptr
<Pseudo_branch_instruction
> branch
;
9473 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9474 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9475 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9476 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9477 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9478 BB_else_logical
->kind
|= block_kind_uniform
;
9480 assert(!ctx
->cf_info
.has_branch
);
9481 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9484 /** emit linear else block */
9485 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9486 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9487 BB_else_linear
->kind
|= block_kind_uniform
;
9488 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9490 /* branch from linear else block to endif block */
9491 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9492 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9493 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9496 /** emit endif merge block */
9497 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9498 append_logical_start(ctx
->block
);
9501 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9502 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9503 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9504 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9505 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9506 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9507 !ctx
->cf_info
.parent_if
.is_divergent
) {
9508 ctx
->cf_info
.exec_potentially_empty_break
= false;
9509 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9511 /* uniform control flow never has an empty exec-mask */
9512 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9513 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9514 ctx
->cf_info
.exec_potentially_empty_break
= false;
9515 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9519 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9521 assert(cond
.regClass() == s1
);
9523 append_logical_end(ctx
->block
);
9524 ctx
->block
->kind
|= block_kind_uniform
;
9526 aco_ptr
<Pseudo_branch_instruction
> branch
;
9527 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9528 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9529 branch
->operands
[0] = Operand(cond
);
9530 branch
->operands
[0].setFixed(scc
);
9531 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9533 ic
->BB_if_idx
= ctx
->block
->index
;
9534 ic
->BB_endif
= Block();
9535 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9536 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9538 ctx
->cf_info
.has_branch
= false;
9539 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9541 /** emit then block */
9542 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9543 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9544 add_edge(ic
->BB_if_idx
, BB_then
);
9545 append_logical_start(BB_then
);
9546 ctx
->block
= BB_then
;
9549 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9551 Block
*BB_then
= ctx
->block
;
9553 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9554 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9556 if (!ic
->uniform_has_then_branch
) {
9557 append_logical_end(BB_then
);
9558 /* branch from then block to endif block */
9559 aco_ptr
<Pseudo_branch_instruction
> branch
;
9560 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9561 BB_then
->instructions
.emplace_back(std::move(branch
));
9562 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9563 if (!ic
->then_branch_divergent
)
9564 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9565 BB_then
->kind
|= block_kind_uniform
;
9568 ctx
->cf_info
.has_branch
= false;
9569 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9571 /** emit else block */
9572 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9573 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9574 add_edge(ic
->BB_if_idx
, BB_else
);
9575 append_logical_start(BB_else
);
9576 ctx
->block
= BB_else
;
9579 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9581 Block
*BB_else
= ctx
->block
;
9583 if (!ctx
->cf_info
.has_branch
) {
9584 append_logical_end(BB_else
);
9585 /* branch from then block to endif block */
9586 aco_ptr
<Pseudo_branch_instruction
> branch
;
9587 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9588 BB_else
->instructions
.emplace_back(std::move(branch
));
9589 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9590 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9591 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9592 BB_else
->kind
|= block_kind_uniform
;
9595 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9596 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9598 /** emit endif merge block */
9599 if (!ctx
->cf_info
.has_branch
) {
9600 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9601 append_logical_start(ctx
->block
);
9605 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9607 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9608 Builder
bld(ctx
->program
, ctx
->block
);
9609 aco_ptr
<Pseudo_branch_instruction
> branch
;
9612 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9614 * Uniform conditionals are represented in the following way*) :
9616 * The linear and logical CFG:
9619 * BB_THEN (logical) BB_ELSE (logical)
9623 * *) Exceptions may be due to break and continue statements within loops
9624 * If a break/continue happens within uniform control flow, it branches
9625 * to the loop exit/entry block. Otherwise, it branches to the next
9629 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9630 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9631 cond
= bool_to_scalar_condition(ctx
, cond
);
9633 begin_uniform_if_then(ctx
, &ic
, cond
);
9634 visit_cf_list(ctx
, &if_stmt
->then_list
);
9636 begin_uniform_if_else(ctx
, &ic
);
9637 visit_cf_list(ctx
, &if_stmt
->else_list
);
9639 end_uniform_if(ctx
, &ic
);
9640 } else { /* non-uniform condition */
9642 * To maintain a logical and linear CFG without critical edges,
9643 * non-uniform conditionals are represented in the following way*) :
9648 * BB_THEN (logical) BB_THEN (linear)
9650 * BB_INVERT (linear)
9652 * BB_ELSE (logical) BB_ELSE (linear)
9659 * BB_THEN (logical) BB_ELSE (logical)
9663 * *) Exceptions may be due to break and continue statements within loops
9666 begin_divergent_if_then(ctx
, &ic
, cond
);
9667 visit_cf_list(ctx
, &if_stmt
->then_list
);
9669 begin_divergent_if_else(ctx
, &ic
);
9670 visit_cf_list(ctx
, &if_stmt
->else_list
);
9672 end_divergent_if(ctx
, &ic
);
9675 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9678 static bool visit_cf_list(isel_context
*ctx
,
9679 struct exec_list
*list
)
9681 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9682 switch (node
->type
) {
9683 case nir_cf_node_block
:
9684 visit_block(ctx
, nir_cf_node_as_block(node
));
9686 case nir_cf_node_if
:
9687 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9690 case nir_cf_node_loop
:
9691 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9694 unreachable("unimplemented cf list type");
9700 static void create_null_export(isel_context
*ctx
)
9702 /* Some shader stages always need to have exports.
9703 * So when there is none, we need to add a null export.
9706 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9707 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9708 Builder
bld(ctx
->program
, ctx
->block
);
9709 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9710 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9713 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9715 assert(ctx
->stage
== vertex_vs
||
9716 ctx
->stage
== tess_eval_vs
||
9717 ctx
->stage
== gs_copy_vs
||
9718 ctx
->stage
== ngg_vertex_gs
||
9719 ctx
->stage
== ngg_tess_eval_gs
);
9721 int offset
= (ctx
->stage
& sw_tes
)
9722 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9723 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9724 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9725 if (!is_pos
&& !mask
)
9727 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9729 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9730 exp
->enabled_mask
= mask
;
9731 for (unsigned i
= 0; i
< 4; ++i
) {
9732 if (mask
& (1 << i
))
9733 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9735 exp
->operands
[i
] = Operand(v1
);
9737 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9738 * Setting valid_mask=1 prevents it and has no other effect.
9740 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9742 exp
->compressed
= false;
9744 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9746 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9747 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9752 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9754 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9755 exp
->enabled_mask
= 0;
9756 for (unsigned i
= 0; i
< 4; ++i
)
9757 exp
->operands
[i
] = Operand(v1
);
9758 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9759 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9760 exp
->enabled_mask
|= 0x1;
9762 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9763 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9764 exp
->enabled_mask
|= 0x4;
9766 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9767 if (ctx
->options
->chip_class
< GFX9
) {
9768 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9769 exp
->enabled_mask
|= 0x8;
9771 Builder
bld(ctx
->program
, ctx
->block
);
9773 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9774 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9775 if (exp
->operands
[2].isTemp())
9776 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9778 exp
->operands
[2] = Operand(out
);
9779 exp
->enabled_mask
|= 0x4;
9782 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9784 exp
->compressed
= false;
9785 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9786 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9789 static void create_export_phis(isel_context
*ctx
)
9791 /* Used when exports are needed, but the output temps are defined in a preceding block.
9792 * This function will set up phis in order to access the outputs in the next block.
9795 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9796 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9797 ctx
->block
->instructions
.pop_back();
9799 Builder
bld(ctx
->program
, ctx
->block
);
9801 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9802 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9803 for (unsigned i
= 0; i
< 4; ++i
) {
9804 if (!(mask
& (1 << i
)))
9807 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9808 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9809 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9813 bld
.insert(std::move(logical_start
));
9816 static void create_vs_exports(isel_context
*ctx
)
9818 assert(ctx
->stage
== vertex_vs
||
9819 ctx
->stage
== tess_eval_vs
||
9820 ctx
->stage
== gs_copy_vs
||
9821 ctx
->stage
== ngg_vertex_gs
||
9822 ctx
->stage
== ngg_tess_eval_gs
);
9824 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9825 ? &ctx
->program
->info
->tes
.outinfo
9826 : &ctx
->program
->info
->vs
.outinfo
;
9828 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9829 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9830 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9833 if (ctx
->options
->key
.has_multiview_view_index
) {
9834 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9835 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9838 /* the order these position exports are created is important */
9840 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9841 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9842 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9843 exported_pos
= true;
9845 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9846 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9847 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9848 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9850 if (ctx
->export_clip_dists
) {
9851 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9852 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9853 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9854 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9857 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9858 if (i
< VARYING_SLOT_VAR0
&&
9859 i
!= VARYING_SLOT_LAYER
&&
9860 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9861 i
!= VARYING_SLOT_VIEWPORT
)
9864 export_vs_varying(ctx
, i
, false, NULL
);
9868 create_null_export(ctx
);
9871 static bool export_fs_mrt_z(isel_context
*ctx
)
9873 Builder
bld(ctx
->program
, ctx
->block
);
9874 unsigned enabled_channels
= 0;
9878 for (unsigned i
= 0; i
< 4; ++i
) {
9879 values
[i
] = Operand(v1
);
9882 /* Both stencil and sample mask only need 16-bits. */
9883 if (!ctx
->program
->info
->ps
.writes_z
&&
9884 (ctx
->program
->info
->ps
.writes_stencil
||
9885 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9886 compr
= true; /* COMPR flag */
9888 if (ctx
->program
->info
->ps
.writes_stencil
) {
9889 /* Stencil should be in X[23:16]. */
9890 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9891 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9892 enabled_channels
|= 0x3;
9895 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9896 /* SampleMask should be in Y[15:0]. */
9897 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9898 enabled_channels
|= 0xc;
9901 if (ctx
->program
->info
->ps
.writes_z
) {
9902 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9903 enabled_channels
|= 0x1;
9906 if (ctx
->program
->info
->ps
.writes_stencil
) {
9907 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9908 enabled_channels
|= 0x2;
9911 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9912 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9913 enabled_channels
|= 0x4;
9917 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9918 * writemask component.
9920 if (ctx
->options
->chip_class
== GFX6
&&
9921 ctx
->options
->family
!= CHIP_OLAND
&&
9922 ctx
->options
->family
!= CHIP_HAINAN
) {
9923 enabled_channels
|= 0x1;
9926 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9927 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9932 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9934 Builder
bld(ctx
->program
, ctx
->block
);
9935 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9938 for (unsigned i
= 0; i
< 4; ++i
) {
9939 if (write_mask
& (1 << i
)) {
9940 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9942 values
[i
] = Operand(v1
);
9946 unsigned target
, col_format
;
9947 unsigned enabled_channels
= 0;
9948 aco_opcode compr_op
= (aco_opcode
)0;
9950 slot
-= FRAG_RESULT_DATA0
;
9951 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9952 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9954 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9955 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9956 bool is_16bit
= values
[0].regClass() == v2b
;
9960 case V_028714_SPI_SHADER_ZERO
:
9961 enabled_channels
= 0; /* writemask */
9962 target
= V_008DFC_SQ_EXP_NULL
;
9965 case V_028714_SPI_SHADER_32_R
:
9966 enabled_channels
= 1;
9969 case V_028714_SPI_SHADER_32_GR
:
9970 enabled_channels
= 0x3;
9973 case V_028714_SPI_SHADER_32_AR
:
9974 if (ctx
->options
->chip_class
>= GFX10
) {
9975 /* Special case: on GFX10, the outputs are different for 32_AR */
9976 enabled_channels
= 0x3;
9977 values
[1] = values
[3];
9978 values
[3] = Operand(v1
);
9980 enabled_channels
= 0x9;
9984 case V_028714_SPI_SHADER_FP16_ABGR
:
9985 enabled_channels
= 0x5;
9986 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9988 if (ctx
->options
->chip_class
>= GFX9
) {
9989 /* Pack the FP16 values together instead of converting them to
9990 * FP32 and back to FP16.
9991 * TODO: use p_create_vector and let the compiler optimizes.
9993 compr_op
= aco_opcode::v_pack_b32_f16
;
9995 for (unsigned i
= 0; i
< 4; i
++) {
9996 if ((write_mask
>> i
) & 1)
9997 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10003 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10004 enabled_channels
= 0x5;
10005 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10006 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10008 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10012 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10013 enabled_channels
= 0x5;
10014 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10015 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10017 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10021 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10022 enabled_channels
= 0x5;
10023 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10024 if (is_int8
|| is_int10
) {
10026 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10027 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10029 for (unsigned i
= 0; i
< 4; i
++) {
10030 if ((write_mask
>> i
) & 1) {
10031 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10032 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10036 } else if (is_16bit
) {
10037 for (unsigned i
= 0; i
< 4; i
++) {
10038 if ((write_mask
>> i
) & 1) {
10039 Temp tmp
= convert_int(bld
, values
[i
].getTemp(), 16, 32, false);
10040 values
[i
] = Operand(tmp
);
10047 case V_028714_SPI_SHADER_SINT16_ABGR
:
10048 enabled_channels
= 0x5;
10049 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10050 if (is_int8
|| is_int10
) {
10052 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10053 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10054 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10055 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10057 for (unsigned i
= 0; i
< 4; i
++) {
10058 if ((write_mask
>> i
) & 1) {
10059 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10060 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10062 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10063 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10067 } else if (is_16bit
) {
10068 for (unsigned i
= 0; i
< 4; i
++) {
10069 if ((write_mask
>> i
) & 1) {
10070 Temp tmp
= convert_int(bld
, values
[i
].getTemp(), 16, 32, true);
10071 values
[i
] = Operand(tmp
);
10077 case V_028714_SPI_SHADER_32_ABGR
:
10078 enabled_channels
= 0xF;
10085 if (target
== V_008DFC_SQ_EXP_NULL
)
10088 if ((bool) compr_op
) {
10089 for (int i
= 0; i
< 2; i
++) {
10090 /* check if at least one of the values to be compressed is enabled */
10091 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10093 enabled_channels
|= enabled
<< (i
*2);
10094 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10095 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10096 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10098 values
[i
] = Operand(v1
);
10101 values
[2] = Operand(v1
);
10102 values
[3] = Operand(v1
);
10104 for (int i
= 0; i
< 4; i
++)
10105 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10108 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10109 enabled_channels
, target
, (bool) compr_op
);
10113 static void create_fs_exports(isel_context
*ctx
)
10115 bool exported
= false;
10117 /* Export depth, stencil and sample mask. */
10118 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10119 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10120 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10121 exported
|= export_fs_mrt_z(ctx
);
10123 /* Export all color render targets. */
10124 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10125 if (ctx
->outputs
.mask
[i
])
10126 exported
|= export_fs_mrt_color(ctx
, i
);
10129 create_null_export(ctx
);
10132 static void write_tcs_tess_factors(isel_context
*ctx
)
10134 unsigned outer_comps
;
10135 unsigned inner_comps
;
10137 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10154 Builder
bld(ctx
->program
, ctx
->block
);
10156 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10157 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10158 bld
.sopp(aco_opcode::s_barrier
);
10160 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10161 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10163 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10164 if_context ic_invocation_id_is_zero
;
10165 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10166 bld
.reset(ctx
->block
);
10168 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10170 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10171 unsigned stride
= inner_comps
+ outer_comps
;
10172 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10176 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10178 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10180 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10181 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10182 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10184 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10185 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10187 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10188 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10189 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10190 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10193 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10194 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10195 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10196 unsigned tf_const_offset
= 0;
10198 if (ctx
->program
->chip_class
<= GFX8
) {
10199 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10200 if_context ic_rel_patch_id_is_zero
;
10201 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10202 bld
.reset(ctx
->block
);
10204 /* Store the dynamic HS control word. */
10205 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10206 bld
.mubuf(aco_opcode::buffer_store_dword
,
10207 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10208 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10209 /* disable_wqm */ false, /* glc */ true);
10210 tf_const_offset
+= 4;
10212 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10213 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10214 bld
.reset(ctx
->block
);
10217 assert(stride
== 2 || stride
== 4 || stride
== 6);
10218 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10219 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10221 /* Store to offchip for TES to read - only if TES reads them */
10222 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10223 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10224 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10226 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10227 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10229 if (likely(inner_comps
)) {
10230 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10231 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10235 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10236 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10239 static void emit_stream_output(isel_context
*ctx
,
10240 Temp
const *so_buffers
,
10241 Temp
const *so_write_offset
,
10242 const struct radv_stream_output
*output
)
10244 unsigned num_comps
= util_bitcount(output
->component_mask
);
10245 unsigned writemask
= (1 << num_comps
) - 1;
10246 unsigned loc
= output
->location
;
10247 unsigned buf
= output
->buffer
;
10249 assert(num_comps
&& num_comps
<= 4);
10250 if (!num_comps
|| num_comps
> 4)
10253 unsigned start
= ffs(output
->component_mask
) - 1;
10256 bool all_undef
= true;
10257 assert(ctx
->stage
& hw_vs
);
10258 for (unsigned i
= 0; i
< num_comps
; i
++) {
10259 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10260 all_undef
= all_undef
&& !out
[i
].id();
10265 while (writemask
) {
10267 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10268 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10269 /* GFX6 doesn't support storing vec3, split it. */
10270 writemask
|= 1u << (start
+ 2);
10274 unsigned offset
= output
->offset
+ start
* 4;
10276 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10277 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10278 for (int i
= 0; i
< count
; ++i
)
10279 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10280 vec
->definitions
[0] = Definition(write_data
);
10281 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10286 opcode
= aco_opcode::buffer_store_dword
;
10289 opcode
= aco_opcode::buffer_store_dwordx2
;
10292 opcode
= aco_opcode::buffer_store_dwordx3
;
10295 opcode
= aco_opcode::buffer_store_dwordx4
;
10298 unreachable("Unsupported dword count.");
10301 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10302 store
->operands
[0] = Operand(so_buffers
[buf
]);
10303 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10304 store
->operands
[2] = Operand((uint32_t) 0);
10305 store
->operands
[3] = Operand(write_data
);
10306 if (offset
> 4095) {
10307 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10308 Builder
bld(ctx
->program
, ctx
->block
);
10309 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10311 store
->offset
= offset
;
10313 store
->offen
= true;
10315 store
->dlc
= false;
10317 store
->can_reorder
= true;
10318 ctx
->block
->instructions
.emplace_back(std::move(store
));
10322 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10324 Builder
bld(ctx
->program
, ctx
->block
);
10326 Temp so_buffers
[4];
10327 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10328 for (unsigned i
= 0; i
< 4; i
++) {
10329 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10333 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10334 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10337 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10338 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10340 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10342 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10345 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10347 bld
.reset(ctx
->block
);
10349 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10351 Temp so_write_offset
[4];
10353 for (unsigned i
= 0; i
< 4; i
++) {
10354 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10359 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10360 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10361 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10362 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10364 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10366 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10367 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10368 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10369 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10373 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10374 struct radv_stream_output
*output
=
10375 &ctx
->program
->info
->so
.outputs
[i
];
10376 if (stream
!= output
->stream
)
10379 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10382 begin_divergent_if_else(ctx
, &ic
);
10383 end_divergent_if(ctx
, &ic
);
10386 } /* end namespace */
10388 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10390 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10391 Builder
bld(ctx
->program
, ctx
->block
);
10392 constexpr unsigned hs_idx
= 1u;
10393 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10394 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10395 Operand((8u << 16) | (hs_idx
* 8u)));
10396 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10398 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10400 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10401 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10402 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10403 ls_has_nonzero_hs_threads
);
10404 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10405 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10406 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10407 ls_has_nonzero_hs_threads
);
10408 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10409 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10410 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10411 ls_has_nonzero_hs_threads
);
10413 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10414 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10415 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10418 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10420 /* Split all arguments except for the first (ring_offsets) and the last
10421 * (exec) so that the dead channels don't stay live throughout the program.
10423 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10424 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10425 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10426 startpgm
->definitions
[i
].regClass().size());
10431 void handle_bc_optimize(isel_context
*ctx
)
10433 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10434 Builder
bld(ctx
->program
, ctx
->block
);
10435 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10436 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10437 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10438 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10439 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10440 if (uses_center
&& uses_centroid
) {
10441 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10442 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10444 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10446 for (unsigned i
= 0; i
< 2; i
++) {
10447 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10448 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10449 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10450 persp_centroid
, persp_center
, sel
);
10452 ctx
->persp_centroid
= bld
.tmp(v2
);
10453 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10454 Operand(new_coord
[0]), Operand(new_coord
[1]));
10455 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10458 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10460 for (unsigned i
= 0; i
< 2; i
++) {
10461 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10462 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10463 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10464 linear_centroid
, linear_center
, sel
);
10466 ctx
->linear_centroid
= bld
.tmp(v2
);
10467 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10468 Operand(new_coord
[0]), Operand(new_coord
[1]));
10469 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10474 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10476 Program
*program
= ctx
->program
;
10478 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10480 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10481 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10482 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10483 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10484 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10486 program
->next_fp_mode
.must_flush_denorms32
=
10487 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10488 program
->next_fp_mode
.must_flush_denorms16_64
=
10489 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10490 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10492 program
->next_fp_mode
.care_about_round32
=
10493 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10495 program
->next_fp_mode
.care_about_round16_64
=
10496 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10497 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10499 /* default to preserving fp16 and fp64 denorms, since it's free */
10500 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10501 program
->next_fp_mode
.denorm16_64
= 0;
10503 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10505 /* preserving fp32 denorms is expensive, so only do it if asked */
10506 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10507 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10509 program
->next_fp_mode
.denorm32
= 0;
10511 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10512 program
->next_fp_mode
.round32
= fp_round_tz
;
10514 program
->next_fp_mode
.round32
= fp_round_ne
;
10516 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10517 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10519 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10521 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10524 void cleanup_cfg(Program
*program
)
10526 /* create linear_succs/logical_succs */
10527 for (Block
& BB
: program
->blocks
) {
10528 for (unsigned idx
: BB
.linear_preds
)
10529 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10530 for (unsigned idx
: BB
.logical_preds
)
10531 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10535 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10537 Builder
bld(ctx
->program
, ctx
->block
);
10539 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10540 Temp count
= i
== 0
10541 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10542 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10543 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10545 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10548 if (ctx
->program
->wave_size
== 64) {
10549 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10550 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10551 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10553 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10554 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10560 bool ngg_early_prim_export(isel_context
*ctx
)
10562 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10566 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10568 Builder
bld(ctx
->program
, ctx
->block
);
10570 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10571 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10573 /* Get the id of the current wave within the threadgroup (workgroup) */
10574 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10575 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10577 /* Execute the following code only on the first wave (wave id 0),
10578 * use the SCC def to tell if the wave id is zero or not.
10580 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10582 begin_uniform_if_then(ctx
, &ic
, cond
);
10583 begin_uniform_if_else(ctx
, &ic
);
10584 bld
.reset(ctx
->block
);
10586 /* Number of vertices output by VS/TES */
10587 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10588 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10589 /* Number of primitives output by VS/TES */
10590 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10591 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10593 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10594 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10595 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10597 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10598 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10600 end_uniform_if(ctx
, &ic
);
10602 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10603 bld
.reset(ctx
->block
);
10604 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10607 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10609 Builder
bld(ctx
->program
, ctx
->block
);
10611 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10612 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10615 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10618 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10619 assert(vtxindex
[i
].id());
10622 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10626 /* The initial edge flag is always false in tess eval shaders. */
10627 if (ctx
->stage
== ngg_vertex_gs
) {
10628 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10629 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10633 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10638 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10640 Builder
bld(ctx
->program
, ctx
->block
);
10641 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10643 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10644 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10645 false /* compressed */, true/* done */, false /* valid mask */);
10648 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10650 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10651 * These must always come before VS exports.
10653 * It is recommended to do these as early as possible. They can be at the beginning when
10654 * there is no SW GS and the shader doesn't write edge flags.
10658 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10659 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10661 Builder
bld(ctx
->program
, ctx
->block
);
10662 constexpr unsigned max_vertices_per_primitive
= 3;
10663 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10665 if (ctx
->stage
== ngg_vertex_gs
) {
10666 /* TODO: optimize for points & lines */
10667 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10668 if (ctx
->shader
->info
.tess
.point_mode
)
10669 num_vertices_per_primitive
= 1;
10670 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10671 num_vertices_per_primitive
= 2;
10673 unreachable("Unsupported NGG shader stage");
10676 Temp vtxindex
[max_vertices_per_primitive
];
10677 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10678 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10679 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10680 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10681 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10682 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10683 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10684 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10686 /* Export primitive data to the index buffer. */
10687 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10689 /* Export primitive ID. */
10690 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10691 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10692 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10693 Temp provoking_vtx_index
= vtxindex
[0];
10694 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10696 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10699 begin_divergent_if_else(ctx
, &ic
);
10700 end_divergent_if(ctx
, &ic
);
10703 void ngg_emit_nogs_output(isel_context
*ctx
)
10705 /* Emits NGG GS output, for stages that don't have SW GS. */
10708 Builder
bld(ctx
->program
, ctx
->block
);
10709 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10711 /* NGG streamout is currently disabled by default. */
10712 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10714 if (late_prim_export
) {
10715 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10716 create_export_phis(ctx
);
10717 /* Do what we need to do in the GS threads. */
10718 ngg_emit_nogs_gsthreads(ctx
);
10720 /* What comes next should be executed on ES threads. */
10721 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10722 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10723 bld
.reset(ctx
->block
);
10726 /* Export VS outputs */
10727 ctx
->block
->kind
|= block_kind_export_end
;
10728 create_vs_exports(ctx
);
10730 /* Export primitive ID */
10731 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10734 if (ctx
->stage
== ngg_vertex_gs
) {
10735 /* Wait for GS threads to store primitive ID in LDS. */
10736 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10737 bld
.sopp(aco_opcode::s_barrier
);
10739 /* Calculate LDS address where the GS threads stored the primitive ID. */
10740 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10741 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10742 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10743 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10744 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10745 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10747 /* Load primitive ID from LDS. */
10748 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10749 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10750 /* TES: Just use the patch ID as the primitive ID. */
10751 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10753 unreachable("unsupported NGG shader stage.");
10756 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10757 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10759 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10762 if (late_prim_export
) {
10763 begin_divergent_if_else(ctx
, &ic
);
10764 end_divergent_if(ctx
, &ic
);
10765 bld
.reset(ctx
->block
);
10769 void select_program(Program
*program
,
10770 unsigned shader_count
,
10771 struct nir_shader
*const *shaders
,
10772 ac_shader_config
* config
,
10773 struct radv_shader_args
*args
)
10775 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10776 if_context ic_merged_wave_info
;
10777 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10779 for (unsigned i
= 0; i
< shader_count
; i
++) {
10780 nir_shader
*nir
= shaders
[i
];
10781 init_context(&ctx
, nir
);
10783 setup_fp_mode(&ctx
, nir
);
10786 /* needs to be after init_context() for FS */
10787 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10788 append_logical_start(ctx
.block
);
10790 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10791 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10793 split_arguments(&ctx
, startpgm
);
10797 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10799 if (ngg_early_prim_export(&ctx
))
10800 ngg_emit_nogs_gsthreads(&ctx
);
10803 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10804 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10805 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10806 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10807 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10808 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10809 ctx
.stage
== tess_eval_geometry_gs
));
10811 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10812 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10813 if (check_merged_wave_info
) {
10814 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10815 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10819 Builder
bld(ctx
.program
, ctx
.block
);
10821 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10822 bld
.sopp(aco_opcode::s_barrier
);
10824 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10825 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10827 } else if (ctx
.stage
== geometry_gs
)
10828 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10830 if (ctx
.stage
== fragment_fs
)
10831 handle_bc_optimize(&ctx
);
10833 visit_cf_list(&ctx
, &func
->body
);
10835 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10836 emit_streamout(&ctx
, 0);
10838 if (ctx
.stage
& hw_vs
) {
10839 create_vs_exports(&ctx
);
10840 ctx
.block
->kind
|= block_kind_export_end
;
10841 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10842 ngg_emit_nogs_output(&ctx
);
10843 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10844 Builder
bld(ctx
.program
, ctx
.block
);
10845 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10846 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10847 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10848 write_tcs_tess_factors(&ctx
);
10851 if (ctx
.stage
== fragment_fs
) {
10852 create_fs_exports(&ctx
);
10853 ctx
.block
->kind
|= block_kind_export_end
;
10856 if (endif_merged_wave_info
) {
10857 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10858 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10861 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10862 ngg_emit_nogs_output(&ctx
);
10864 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10865 /* Outputs of the previous stage are inputs to the next stage */
10866 ctx
.inputs
= ctx
.outputs
;
10867 ctx
.outputs
= shader_io_state();
10871 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10873 append_logical_end(ctx
.block
);
10874 ctx
.block
->kind
|= block_kind_uniform
;
10875 Builder
bld(ctx
.program
, ctx
.block
);
10876 if (ctx
.program
->wb_smem_l1_on_end
)
10877 bld
.smem(aco_opcode::s_dcache_wb
, false);
10878 bld
.sopp(aco_opcode::s_endpgm
);
10880 cleanup_cfg(program
);
10883 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10884 ac_shader_config
* config
,
10885 struct radv_shader_args
*args
)
10887 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10889 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10890 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10891 program
->next_fp_mode
.must_flush_denorms32
= false;
10892 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10893 program
->next_fp_mode
.care_about_round32
= false;
10894 program
->next_fp_mode
.care_about_round16_64
= false;
10895 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10896 program
->next_fp_mode
.denorm32
= 0;
10897 program
->next_fp_mode
.round32
= fp_round_ne
;
10898 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10899 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10901 add_startpgm(&ctx
);
10902 append_logical_start(ctx
.block
);
10904 Builder
bld(ctx
.program
, ctx
.block
);
10906 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10908 Operand
stream_id(0u);
10909 if (args
->shader_info
->so
.num_outputs
)
10910 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10911 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10913 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10915 std::stack
<Block
> endif_blocks
;
10917 for (unsigned stream
= 0; stream
< 4; stream
++) {
10918 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10921 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10922 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10925 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10927 unsigned BB_if_idx
= ctx
.block
->index
;
10928 Block BB_endif
= Block();
10929 if (!stream_id
.isConstant()) {
10931 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10932 append_logical_end(ctx
.block
);
10933 ctx
.block
->kind
|= block_kind_uniform
;
10934 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10936 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10938 ctx
.block
= ctx
.program
->create_and_insert_block();
10939 add_edge(BB_if_idx
, ctx
.block
);
10940 bld
.reset(ctx
.block
);
10941 append_logical_start(ctx
.block
);
10944 unsigned offset
= 0;
10945 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10946 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10949 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10950 unsigned length
= util_last_bit(output_usage_mask
);
10951 for (unsigned j
= 0; j
< length
; ++j
) {
10952 if (!(output_usage_mask
& (1 << j
)))
10955 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10956 Temp voffset
= vtx_offset
;
10957 if (const_offset
>= 4096u) {
10958 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10959 const_offset
%= 4096u;
10962 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10963 mubuf
->definitions
[0] = bld
.def(v1
);
10964 mubuf
->operands
[0] = Operand(gsvs_ring
);
10965 mubuf
->operands
[1] = Operand(voffset
);
10966 mubuf
->operands
[2] = Operand(0u);
10967 mubuf
->offen
= true;
10968 mubuf
->offset
= const_offset
;
10971 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10972 mubuf
->barrier
= barrier_none
;
10973 mubuf
->can_reorder
= true;
10975 ctx
.outputs
.mask
[i
] |= 1 << j
;
10976 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10978 bld
.insert(std::move(mubuf
));
10984 if (args
->shader_info
->so
.num_outputs
) {
10985 emit_streamout(&ctx
, stream
);
10986 bld
.reset(ctx
.block
);
10990 create_vs_exports(&ctx
);
10991 ctx
.block
->kind
|= block_kind_export_end
;
10994 if (!stream_id
.isConstant()) {
10995 append_logical_end(ctx
.block
);
10997 /* branch from then block to endif block */
10998 bld
.branch(aco_opcode::p_branch
);
10999 add_edge(ctx
.block
->index
, &BB_endif
);
11000 ctx
.block
->kind
|= block_kind_uniform
;
11002 /* emit else block */
11003 ctx
.block
= ctx
.program
->create_and_insert_block();
11004 add_edge(BB_if_idx
, ctx
.block
);
11005 bld
.reset(ctx
.block
);
11006 append_logical_start(ctx
.block
);
11008 endif_blocks
.push(std::move(BB_endif
));
11012 while (!endif_blocks
.empty()) {
11013 Block BB_endif
= std::move(endif_blocks
.top());
11014 endif_blocks
.pop();
11016 Block
*BB_else
= ctx
.block
;
11018 append_logical_end(BB_else
);
11019 /* branch from else block to endif block */
11020 bld
.branch(aco_opcode::p_branch
);
11021 add_edge(BB_else
->index
, &BB_endif
);
11022 BB_else
->kind
|= block_kind_uniform
;
11024 /** emit endif merge block */
11025 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11026 bld
.reset(ctx
.block
);
11027 append_logical_start(ctx
.block
);
11030 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11032 append_logical_end(ctx
.block
);
11033 ctx
.block
->kind
|= block_kind_uniform
;
11034 bld
.sopp(aco_opcode::s_endpgm
);
11036 cleanup_cfg(program
);