src/amd/compiler/aco_live_var_analysis.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
  26  *    Bas Nieuwenhuizen (bas@basnieuwenhuizen.nl)
  27  *
  28  */
  29
  30 #include "aco_ir.h"
  31 #include "util/u_math.h"
  32
  33 #include <set>
  34 #include <vector>
  35
  36 #include "vulkan/radv_shader.h"
  37
  38 namespace aco {
  39 RegisterDemand get_live_changes(aco_ptr<Instruction>& instr)
  40 {
  41    RegisterDemand changes;
  42    for (const Definition& def : instr->definitions) {
  43       if (!def.isTemp() || def.isKill())
  44          continue;
  45       changes += def.getTemp();
  46    }
  47
  48    for (const Operand& op : instr->operands) {
  49       if (!op.isTemp() || !op.isFirstKill())
  50          continue;
  51       changes -= op.getTemp();
  52    }
  53
  54    return changes;
  55 }
  56
  57 RegisterDemand get_temp_registers(aco_ptr<Instruction>& instr)
  58 {
  59    RegisterDemand temp_registers;
  60    for (Definition def : instr->definitions) {
  61       if (!def.isTemp())
  62          continue;
  63       if (def.isKill())
  64          temp_registers += def.getTemp();
  65    }
  66    return temp_registers;
  67 }
  68
  69 RegisterDemand get_demand_before(RegisterDemand demand, aco_ptr<Instruction>& instr, aco_ptr<Instruction>& instr_before)
  70 {
  71    demand -= get_live_changes(instr);
  72    demand -= get_temp_registers(instr);
  73    if (instr_before)
  74       demand += get_temp_registers(instr_before);
  75    return demand;
  76 }
  77
  78 namespace {
  79 void process_live_temps_per_block(Program *program, live& lives, Block* block,
  80                                   std::set<unsigned>& worklist, std::vector<uint16_t>& phi_sgpr_ops)
  81 {
  82    std::vector<RegisterDemand>& register_demand = lives.register_demand[block->index];
  83    RegisterDemand new_demand;
  84
  85    register_demand.resize(block->instructions.size());
  86    block->register_demand = RegisterDemand();
  87
  88    std::set<Temp> live_sgprs;
  89    std::set<Temp> live_vgprs;
  90
  91    /* add the live_out_exec to live */
  92    bool exec_live = false;
  93    if (block->live_out_exec != Temp()) {
  94       live_sgprs.insert(block->live_out_exec);
  95       new_demand.sgpr += program->lane_mask.size();
  96       exec_live = true;
  97    }
  98
  99    /* split the live-outs from this block into the temporary sets */
 100    std::vector<std::set<Temp>>& live_temps = lives.live_out;
 101    for (const Temp temp : live_temps[block->index]) {
 102       const bool inserted = temp.is_linear()
 103                           ? live_sgprs.insert(temp).second
 104                           : live_vgprs.insert(temp).second;
 105       if (inserted) {
 106          new_demand += temp;
 107       }
 108    }
 109    new_demand.sgpr -= phi_sgpr_ops[block->index];
 110
 111    /* traverse the instructions backwards */
 112    int idx;
 113    for (idx = block->instructions.size() -1; idx >= 0; idx--) {
 114       Instruction *insn = block->instructions[idx].get();
 115       if (is_phi(insn))
 116          break;
 117
 118       /* substract the 1 or 2 sgprs from exec */
 119       if (exec_live)
 120          assert(new_demand.sgpr >= (int16_t) program->lane_mask.size());
 121       register_demand[idx] = RegisterDemand(new_demand.vgpr, new_demand.sgpr - (exec_live ? program->lane_mask.size() : 0));
 122
 123       /* KILL */
 124       for (Definition& definition : insn->definitions) {
 125          if (!definition.isTemp()) {
 126             continue;
 127          }
 128          if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc)
 129             program->needs_vcc = true;
 130
 131          const Temp temp = definition.getTemp();
 132          size_t n = 0;
 133          if (temp.is_linear())
 134             n = live_sgprs.erase(temp);
 135          else
 136             n = live_vgprs.erase(temp);
 137
 138          if (n) {
 139             new_demand -= temp;
 140             definition.setKill(false);
 141          } else {
 142             definition.setKill(true);
 143          }
 144
 145          if (definition.isFixed() && definition.physReg() == exec)
 146             exec_live = false;
 147       }
 148
 149       /* GEN */
 150       if (insn->opcode == aco_opcode::p_logical_end) {
 151          new_demand.sgpr += phi_sgpr_ops[block->index];
 152       } else {
 153          /* we need to do this in a separate loop because the next one can
 154           * setKill() for several operands at once and we don't want to
 155           * overwrite that in a later iteration */
 156          for (Operand& op : insn->operands)
 157             op.setKill(false);
 158
 159          for (unsigned i = 0; i < insn->operands.size(); ++i)
 160          {
 161             Operand& operand = insn->operands[i];
 162             if (!operand.isTemp())
 163                continue;
 164             if (operand.isFixed() && operand.physReg() == vcc)
 165                program->needs_vcc = true;
 166             const Temp temp = operand.getTemp();
 167             const bool inserted = temp.is_linear()
 168                                 ? live_sgprs.insert(temp).second
 169                                 : live_vgprs.insert(temp).second;
 170             if (inserted) {
 171                operand.setFirstKill(true);
 172                for (unsigned j = i + 1; j < insn->operands.size(); ++j) {
 173                   if (insn->operands[j].isTemp() && insn->operands[j].tempId() == operand.tempId()) {
 174                      insn->operands[j].setFirstKill(false);
 175                      insn->operands[j].setKill(true);
 176                   }
 177                }
 178                new_demand += temp;
 179             }
 180
 181             if (operand.isFixed() && operand.physReg() == exec)
 182                exec_live = true;
 183          }
 184       }
 185
 186       register_demand[idx] += get_temp_registers(block->instructions[idx]);
 187
 188       block->register_demand.update(register_demand[idx]);
 189    }
 190
 191    /* update block's register demand for a last time */
 192    if (exec_live)
 193       assert(new_demand.sgpr >= (int16_t) program->lane_mask.size());
 194    new_demand.sgpr -= exec_live ? program->lane_mask.size() : 0;
 195    block->register_demand.update(new_demand);
 196
 197    /* handle phi definitions */
 198    int phi_idx = idx;
 199    while (phi_idx >= 0) {
 200       register_demand[phi_idx] = new_demand;
 201       Instruction *insn = block->instructions[phi_idx].get();
 202
 203       assert(is_phi(insn));
 204       assert(insn->definitions.size() == 1 && insn->definitions[0].isTemp());
 205       Definition& definition = insn->definitions[0];
 206       if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc)
 207          program->needs_vcc = true;
 208       const Temp temp = definition.getTemp();
 209       size_t n = 0;
 210
 211       if (temp.is_linear())
 212          n = live_sgprs.erase(temp);
 213       else
 214          n = live_vgprs.erase(temp);
 215
 216       if (n)
 217          definition.setKill(false);
 218       else
 219          definition.setKill(true);
 220
 221       phi_idx--;
 222    }
 223
 224    /* now, we have the live-in sets and need to merge them into the live-out sets */
 225    for (unsigned pred_idx : block->logical_preds) {
 226       for (Temp vgpr : live_vgprs) {
 227          auto it = live_temps[pred_idx].insert(vgpr);
 228          if (it.second)
 229             worklist.insert(pred_idx);
 230       }
 231    }
 232
 233    for (unsigned pred_idx : block->linear_preds) {
 234       for (Temp sgpr : live_sgprs) {
 235          auto it = live_temps[pred_idx].insert(sgpr);
 236          if (it.second)
 237             worklist.insert(pred_idx);
 238       }
 239    }
 240
 241    /* handle phi operands */
 242    phi_idx = idx;
 243    while (phi_idx >= 0) {
 244       Instruction *insn = block->instructions[phi_idx].get();
 245       assert(is_phi(insn));
 246       /* directly insert into the predecessors live-out set */
 247       std::vector<unsigned>& preds = insn->opcode == aco_opcode::p_phi
 248                                    ? block->logical_preds
 249                                    : block->linear_preds;
 250       for (unsigned i = 0; i < preds.size(); ++i) {
 251          Operand &operand = insn->operands[i];
 252          if (!operand.isTemp())
 253             continue;
 254          if (operand.isFixed() && operand.physReg() == vcc)
 255             program->needs_vcc = true;
 256          /* check if we changed an already processed block */
 257          const bool inserted = live_temps[preds[i]].insert(operand.getTemp()).second;
 258          if (inserted) {
 259             operand.setKill(true);
 260             worklist.insert(preds[i]);
 261             if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr)
 262                phi_sgpr_ops[preds[i]] += operand.size();
 263          }
 264       }
 265       phi_idx--;
 266    }
 267
 268    if ((block->logical_preds.empty() && !live_vgprs.empty()) ||
 269        (block->linear_preds.empty() && !live_sgprs.empty())) {
 270       aco_print_program(program, stderr);
 271       fprintf(stderr, "These temporaries are never defined or are defined after use:\n");
 272       for (Temp vgpr : live_vgprs)
 273          fprintf(stderr, "%%%d\n", vgpr.id());
 274       for (Temp sgpr : live_sgprs)
 275          fprintf(stderr, "%%%d\n", sgpr.id());
 276       abort();
 277    }
 278
 279    assert(block->index != 0 || new_demand == RegisterDemand());
 280 }
 281
 282 unsigned calc_waves_per_workgroup(Program *program)
 283 {
 284    unsigned workgroup_size = program->wave_size;
 285    if (program->stage == compute_cs) {
 286       unsigned* bsize = program->info->cs.block_size;
 287       workgroup_size = bsize[0] * bsize[1] * bsize[2];
 288    }
 289    return align(workgroup_size, program->wave_size) / program->wave_size;
 290 }
 291 } /* end namespace */
 292
 293 uint16_t get_extra_sgprs(Program *program)
 294 {
 295    if (program->chip_class >= GFX10) {
 296       assert(!program->needs_flat_scr);
 297       assert(!program->needs_xnack_mask);
 298       return 2;
 299    } else if (program->chip_class >= GFX8) {
 300       if (program->needs_flat_scr)
 301          return 6;
 302       else if (program->needs_xnack_mask)
 303          return 4;
 304       else if (program->needs_vcc)
 305          return 2;
 306       else
 307          return 0;
 308    } else {
 309       assert(!program->needs_xnack_mask);
 310       if (program->needs_flat_scr)
 311          return 4;
 312       else if (program->needs_vcc)
 313          return 2;
 314       else
 315          return 0;
 316    }
 317 }
 318
 319 uint16_t get_sgpr_alloc(Program *program, uint16_t addressable_sgprs)
 320 {
 321    assert(addressable_sgprs <= program->sgpr_limit);
 322    uint16_t sgprs = addressable_sgprs + get_extra_sgprs(program);
 323    uint16_t granule = program->sgpr_alloc_granule + 1;
 324    return align(std::max(sgprs, granule), granule);
 325 }
 326
 327 uint16_t get_vgpr_alloc(Program *program, uint16_t addressable_vgprs)
 328 {
 329    assert(addressable_vgprs <= program->vgpr_limit);
 330    uint16_t granule = program->vgpr_alloc_granule + 1;
 331    return align(std::max(addressable_vgprs, granule), granule);
 332 }
 333
 334 uint16_t get_addr_sgpr_from_waves(Program *program, uint16_t max_waves)
 335 {
 336     uint16_t sgprs = program->physical_sgprs / max_waves & ~program->sgpr_alloc_granule;
 337     sgprs -= get_extra_sgprs(program);
 338     return std::min(sgprs, program->sgpr_limit);
 339 }
 340
 341 uint16_t get_addr_vgpr_from_waves(Program *program, uint16_t max_waves)
 342 {
 343     uint16_t vgprs = 256 / max_waves & ~program->vgpr_alloc_granule;
 344     return std::min(vgprs, program->vgpr_limit);
 345 }
 346
 347 void calc_min_waves(Program* program)
 348 {
 349    unsigned waves_per_workgroup = calc_waves_per_workgroup(program);
 350    /* currently min_waves is in wave64 waves */
 351    if (program->wave_size == 32)
 352       waves_per_workgroup = DIV_ROUND_UP(waves_per_workgroup, 2);
 353
 354    unsigned simd_per_cu = 4; /* TODO: different on Navi */
 355    bool wgp = program->chip_class >= GFX10; /* assume WGP is used on Navi */
 356    unsigned simd_per_cu_wgp = wgp ? simd_per_cu * 2 : simd_per_cu;
 357
 358    program->min_waves = DIV_ROUND_UP(waves_per_workgroup, simd_per_cu_wgp);
 359 }
 360
 361 void update_vgpr_sgpr_demand(Program* program, const RegisterDemand new_demand)
 362 {
 363    /* TODO: max_waves_per_simd, simd_per_cu and the number of physical vgprs for Navi */
 364    unsigned max_waves_per_simd = 10;
 365    unsigned simd_per_cu = 4;
 366
 367    bool wgp = program->chip_class >= GFX10; /* assume WGP is used on Navi */
 368    unsigned simd_per_cu_wgp = wgp ? simd_per_cu * 2 : simd_per_cu;
 369    unsigned lds_limit = wgp ? program->lds_limit * 2 : program->lds_limit;
 370
 371    /* this won't compile, register pressure reduction necessary */
 372    if (new_demand.vgpr > program->vgpr_limit || new_demand.sgpr > program->sgpr_limit) {
 373       program->num_waves = 0;
 374       program->max_reg_demand = new_demand;
 375    } else {
 376       program->num_waves = program->physical_sgprs / get_sgpr_alloc(program, new_demand.sgpr);
 377       program->num_waves = std::min<uint16_t>(program->num_waves, 256 / get_vgpr_alloc(program, new_demand.vgpr));
 378       program->max_waves = max_waves_per_simd;
 379
 380       /* adjust max_waves for workgroup and LDS limits */
 381       unsigned waves_per_workgroup = calc_waves_per_workgroup(program);
 382       unsigned workgroups_per_cu_wgp = max_waves_per_simd * simd_per_cu_wgp / waves_per_workgroup;
 383       if (program->config->lds_size) {
 384          unsigned lds = program->config->lds_size * program->lds_alloc_granule;
 385          workgroups_per_cu_wgp = std::min(workgroups_per_cu_wgp, lds_limit / lds);
 386       }
 387       if (waves_per_workgroup > 1 && program->chip_class < GFX10)
 388          workgroups_per_cu_wgp = std::min(workgroups_per_cu_wgp, 16u); /* TODO: is this a SI-only limit? what about Navi? */
 389
 390       /* in cases like waves_per_workgroup=3 or lds=65536 and
 391        * waves_per_workgroup=1, we want the maximum possible number of waves per
 392        * SIMD and not the minimum. so DIV_ROUND_UP is used */
 393       program->max_waves = std::min<uint16_t>(program->max_waves, DIV_ROUND_UP(workgroups_per_cu_wgp * waves_per_workgroup, simd_per_cu_wgp));
 394
 395       /* incorporate max_waves and calculate max_reg_demand */
 396       program->num_waves = std::min<uint16_t>(program->num_waves, program->max_waves);
 397       program->max_reg_demand.vgpr = get_addr_vgpr_from_waves(program, program->num_waves);
 398       program->max_reg_demand.sgpr = get_addr_sgpr_from_waves(program, program->num_waves);
 399    }
 400 }
 401
 402 live live_var_analysis(Program* program,
 403                        const struct radv_nir_compiler_options *options)
 404 {
 405    live result;
 406    result.live_out.resize(program->blocks.size());
 407    result.register_demand.resize(program->blocks.size());
 408    std::set<unsigned> worklist;
 409    std::vector<uint16_t> phi_sgpr_ops(program->blocks.size());
 410    RegisterDemand new_demand;
 411
 412    program->needs_vcc = false;
 413
 414    /* this implementation assumes that the block idx corresponds to the block's position in program->blocks vector */
 415    for (Block& block : program->blocks)
 416       worklist.insert(block.index);
 417    while (!worklist.empty()) {
 418       std::set<unsigned>::reverse_iterator b_it = worklist.rbegin();
 419       unsigned block_idx = *b_it;
 420       worklist.erase(block_idx);
 421       process_live_temps_per_block(program, result, &program->blocks[block_idx], worklist, phi_sgpr_ops);
 422       new_demand.update(program->blocks[block_idx].register_demand);
 423    }
 424
 425    /* calculate the program's register demand and number of waves */
 426    update_vgpr_sgpr_demand(program, new_demand);
 427
 428    return result;
 429 }
 430
 431 }
 432