src/amd/compiler/aco_live_var_analysis.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
  26  *    Bas Nieuwenhuizen (bas@basnieuwenhuizen.nl)
  27  *
  28  */
  29
  30 #include "aco_ir.h"
  31 #include "util/u_math.h"
  32
  33 #include <set>
  34 #include <vector>
  35
  36 #include "vulkan/radv_shader.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 void process_live_temps_per_block(Program *program, live& lives, Block* block,
  42                                   std::set<unsigned>& worklist, std::vector<uint16_t>& phi_sgpr_ops)
  43 {
  44    std::vector<RegisterDemand>& register_demand = lives.register_demand[block->index];
  45    RegisterDemand new_demand;
  46
  47    register_demand.resize(block->instructions.size());
  48    block->register_demand = RegisterDemand();
  49
  50    std::set<Temp> live_sgprs;
  51    std::set<Temp> live_vgprs;
  52
  53    /* add the live_out_exec to live */
  54    bool exec_live = false;
  55    if (block->live_out_exec != Temp()) {
  56       live_sgprs.insert(block->live_out_exec);
  57       new_demand.sgpr += 2;
  58       exec_live = true;
  59    }
  60
  61    /* split the live-outs from this block into the temporary sets */
  62    std::vector<std::set<Temp>>& live_temps = lives.live_out;
  63    for (const Temp temp : live_temps[block->index]) {
  64       const bool inserted = temp.is_linear()
  65                           ? live_sgprs.insert(temp).second
  66                           : live_vgprs.insert(temp).second;
  67       if (inserted) {
  68          new_demand += temp;
  69       }
  70    }
  71    new_demand.sgpr -= phi_sgpr_ops[block->index];
  72
  73    /* traverse the instructions backwards */
  74    for (int idx = block->instructions.size() -1; idx >= 0; idx--)
  75    {
  76       /* substract the 2 sgprs from exec */
  77       if (exec_live)
  78          assert(new_demand.sgpr >= 2);
  79       register_demand[idx] = RegisterDemand(new_demand.vgpr, new_demand.sgpr - (exec_live ? 2 : 0));
  80
  81       Instruction *insn = block->instructions[idx].get();
  82       /* KILL */
  83       for (Definition& definition : insn->definitions) {
  84          if (!definition.isTemp()) {
  85             continue;
  86          }
  87
  88          const Temp temp = definition.getTemp();
  89          size_t n = 0;
  90          if (temp.is_linear())
  91             n = live_sgprs.erase(temp);
  92          else
  93             n = live_vgprs.erase(temp);
  94
  95          if (n) {
  96             new_demand -= temp;
  97             definition.setKill(false);
  98          } else {
  99             register_demand[idx] += temp;
 100             definition.setKill(true);
 101          }
 102
 103          if (definition.isFixed() && definition.physReg() == exec)
 104             exec_live = false;
 105       }
 106
 107       /* GEN */
 108       if (insn->opcode == aco_opcode::p_phi ||
 109           insn->opcode == aco_opcode::p_linear_phi) {
 110          /* directly insert into the predecessors live-out set */
 111          std::vector<unsigned>& preds = insn->opcode == aco_opcode::p_phi
 112                                       ? block->logical_preds
 113                                       : block->linear_preds;
 114          for (unsigned i = 0; i < preds.size(); ++i)
 115          {
 116             Operand &operand = insn->operands[i];
 117             if (!operand.isTemp()) {
 118                continue;
 119             }
 120             /* check if we changed an already processed block */
 121             const bool inserted = live_temps[preds[i]].insert(operand.getTemp()).second;
 122             if (inserted) {
 123                operand.setFirstKill(true);
 124                worklist.insert(preds[i]);
 125                if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr)
 126                   phi_sgpr_ops[preds[i]] += operand.size();
 127             }
 128          }
 129       } else if (insn->opcode == aco_opcode::p_logical_end) {
 130          new_demand.sgpr += phi_sgpr_ops[block->index];
 131       } else {
 132          for (unsigned i = 0; i < insn->operands.size(); ++i)
 133          {
 134             Operand& operand = insn->operands[i];
 135             if (!operand.isTemp()) {
 136                continue;
 137             }
 138             const Temp temp = operand.getTemp();
 139             const bool inserted = temp.is_linear()
 140                                 ? live_sgprs.insert(temp).second
 141                                 : live_vgprs.insert(temp).second;
 142             if (inserted) {
 143                operand.setFirstKill(true);
 144                for (unsigned j = i + 1; j < insn->operands.size(); ++j) {
 145                   if (insn->operands[j].isTemp() && insn->operands[j].tempId() == operand.tempId()) {
 146                      insn->operands[j].setFirstKill(false);
 147                      insn->operands[j].setKill(true);
 148                   }
 149                }
 150                new_demand += temp;
 151             } else {
 152                operand.setKill(false);
 153             }
 154
 155             if (operand.isFixed() && operand.physReg() == exec)
 156                exec_live = true;
 157          }
 158       }
 159
 160       block->register_demand.update(register_demand[idx]);
 161    }
 162
 163    /* now, we have the live-in sets and need to merge them into the live-out sets */
 164    for (unsigned pred_idx : block->logical_preds) {
 165       for (Temp vgpr : live_vgprs) {
 166          auto it = live_temps[pred_idx].insert(vgpr);
 167          if (it.second)
 168             worklist.insert(pred_idx);
 169       }
 170    }
 171
 172    for (unsigned pred_idx : block->linear_preds) {
 173       for (Temp sgpr : live_sgprs) {
 174          auto it = live_temps[pred_idx].insert(sgpr);
 175          if (it.second)
 176             worklist.insert(pred_idx);
 177       }
 178    }
 179
 180    if (!(block->index != 0 || (live_vgprs.empty() && live_sgprs.empty()))) {
 181       aco_print_program(program, stderr);
 182       fprintf(stderr, "These temporaries are never defined or are defined after use:\n");
 183       for (Temp vgpr : live_vgprs)
 184          fprintf(stderr, "%%%d\n", vgpr.id());
 185       for (Temp sgpr : live_sgprs)
 186          fprintf(stderr, "%%%d\n", sgpr.id());
 187       abort();
 188    }
 189
 190    assert(block->index != 0 || new_demand == RegisterDemand());
 191 }
 192 } /* end namespace */
 193
 194 uint16_t get_extra_sgprs(Program *program)
 195 {
 196    if (program->chip_class >= GFX10) {
 197       assert(!program->needs_flat_scr);
 198       assert(!program->needs_xnack_mask);
 199       return 2;
 200    } else if (program->chip_class >= GFX8) {
 201       if (program->needs_flat_scr)
 202          return 6;
 203       else if (program->needs_xnack_mask)
 204          return 4;
 205       else if (program->needs_vcc)
 206          return 2;
 207       else
 208          return 0;
 209    } else {
 210       assert(!program->needs_xnack_mask);
 211       if (program->needs_flat_scr)
 212          return 4;
 213       else if (program->needs_vcc)
 214          return 2;
 215       else
 216          return 0;
 217    }
 218 }
 219
 220 uint16_t get_sgpr_alloc(Program *program, uint16_t addressable_sgprs)
 221 {
 222    assert(addressable_sgprs <= program->sgpr_limit);
 223    uint16_t sgprs = addressable_sgprs + get_extra_sgprs(program);
 224    uint16_t granule = program->sgpr_alloc_granule + 1;
 225    return align(std::max(sgprs, granule), granule);
 226 }
 227
 228 uint16_t get_addr_sgpr_from_waves(Program *program, uint16_t max_waves)
 229 {
 230     uint16_t sgprs = program->physical_sgprs / max_waves & ~program->sgpr_alloc_granule;
 231     sgprs -= get_extra_sgprs(program);
 232     return std::min(sgprs, program->sgpr_limit);
 233 }
 234
 235 void update_vgpr_sgpr_demand(Program* program, const RegisterDemand new_demand)
 236 {
 237    /* TODO: max_waves_per_simd, simd_per_cu and the number of physical vgprs for Navi */
 238    unsigned max_waves_per_simd = 10;
 239    unsigned simd_per_cu = 4;
 240
 241    bool wgp = program->chip_class >= GFX10; /* assume WGP is used on Navi */
 242    unsigned simd_per_cu_wgp = wgp ? simd_per_cu * 2 : simd_per_cu;
 243    unsigned lds_limit = wgp ? program->lds_limit * 2 : program->lds_limit;
 244
 245    const int16_t vgpr_alloc = std::max<int16_t>(4, (new_demand.vgpr + 3) & ~3);
 246    /* this won't compile, register pressure reduction necessary */
 247    if (new_demand.vgpr > 256 || new_demand.sgpr > program->sgpr_limit) {
 248       program->num_waves = 0;
 249       program->max_reg_demand = new_demand;
 250    } else {
 251       program->num_waves = program->physical_sgprs / get_sgpr_alloc(program, new_demand.sgpr);
 252       program->num_waves = std::min<uint16_t>(program->num_waves, 256 / vgpr_alloc);
 253       program->max_waves = max_waves_per_simd;
 254
 255       /* adjust max_waves for workgroup and LDS limits */
 256       unsigned workgroup_size = program->wave_size;
 257       if (program->stage == compute_cs) {
 258          unsigned* bsize = program->info->cs.block_size;
 259          workgroup_size = bsize[0] * bsize[1] * bsize[2];
 260       }
 261       unsigned waves_per_workgroup = align(workgroup_size, program->wave_size) / program->wave_size;
 262
 263       unsigned workgroups_per_cu_wgp = max_waves_per_simd * simd_per_cu_wgp / waves_per_workgroup;
 264       if (program->config->lds_size) {
 265          unsigned lds = program->config->lds_size * program->lds_alloc_granule;
 266          workgroups_per_cu_wgp = std::min(workgroups_per_cu_wgp, lds_limit / lds);
 267       }
 268       if (waves_per_workgroup > 1 && program->chip_class < GFX10)
 269          workgroups_per_cu_wgp = std::min(workgroups_per_cu_wgp, 16u); /* TODO: is this a SI-only limit? what about Navi? */
 270
 271       /* in cases like waves_per_workgroup=3 or lds=65536 and
 272        * waves_per_workgroup=1, we want the maximum possible number of waves per
 273        * SIMD and not the minimum. so DIV_ROUND_UP is used */
 274       program->max_waves = std::min<uint16_t>(program->max_waves, DIV_ROUND_UP(workgroups_per_cu_wgp * waves_per_workgroup, simd_per_cu_wgp));
 275
 276       /* incorporate max_waves and calculate max_reg_demand */
 277       program->num_waves = std::min<uint16_t>(program->num_waves, program->max_waves);
 278       program->max_reg_demand.vgpr = int16_t((256 / program->num_waves) & ~3);
 279       program->max_reg_demand.sgpr = get_addr_sgpr_from_waves(program, program->num_waves);
 280    }
 281 }
 282
 283 live live_var_analysis(Program* program,
 284                        const struct radv_nir_compiler_options *options)
 285 {
 286    live result;
 287    result.live_out.resize(program->blocks.size());
 288    result.register_demand.resize(program->blocks.size());
 289    std::set<unsigned> worklist;
 290    std::vector<uint16_t> phi_sgpr_ops(program->blocks.size());
 291    RegisterDemand new_demand;
 292
 293    /* this implementation assumes that the block idx corresponds to the block's position in program->blocks vector */
 294    for (Block& block : program->blocks)
 295       worklist.insert(block.index);
 296    while (!worklist.empty()) {
 297       std::set<unsigned>::reverse_iterator b_it = worklist.rbegin();
 298       unsigned block_idx = *b_it;
 299       worklist.erase(block_idx);
 300       process_live_temps_per_block(program, result, &program->blocks[block_idx], worklist, phi_sgpr_ops);
 301       new_demand.update(program->blocks[block_idx].register_demand);
 302    }
 303
 304    /* calculate the program's register demand and number of waves */
 305    update_vgpr_sgpr_demand(program, new_demand);
 306
 307    return result;
 308 }
 309
 310 }
 311