2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
96 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
97 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
98 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
99 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
100 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
110 ssa_info() : label(0) {}
112 void add_label(Label new_label
)
114 /* Since all labels which use "instr" use it for the same thing
115 * (indicating the defining instruction), there is no need to clear
116 * any other instr labels. */
117 if (new_label
& instr_labels
)
118 label
&= ~temp_labels
; /* instr and temp alias */
120 if (new_label
& temp_labels
) {
121 label
&= ~temp_labels
;
122 label
&= ~instr_labels
; /* instr and temp alias */
125 if (new_label
& val_labels
)
126 label
&= ~val_labels
;
131 void set_vec(Instruction
* vec
)
133 add_label(label_vec
);
139 return label
& label_vec
;
142 void set_constant(uint32_t constant
)
144 add_label(label_constant
);
150 return label
& label_constant
;
153 void set_constant_64bit(uint32_t constant
)
155 add_label(label_constant_64bit
);
159 bool is_constant_64bit()
161 return label
& label_constant_64bit
;
164 void set_abs(Temp abs_temp
)
166 add_label(label_abs
);
172 return label
& label_abs
;
175 void set_neg(Temp neg_temp
)
177 add_label(label_neg
);
183 return label
& label_neg
;
186 void set_neg_abs(Temp neg_abs_temp
)
188 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
192 void set_mul(Instruction
* mul
)
194 add_label(label_mul
);
200 return label
& label_mul
;
203 void set_temp(Temp tmp
)
205 add_label(label_temp
);
211 return label
& label_temp
;
214 void set_literal(uint32_t lit
)
216 add_label(label_literal
);
222 return label
& label_literal
;
225 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
227 add_label(label_mad
);
234 return label
& label_mad
;
237 void set_omod2(Temp def
)
239 add_label(label_omod2
);
245 return label
& label_omod2
;
248 void set_omod4(Temp def
)
250 add_label(label_omod4
);
256 return label
& label_omod4
;
259 void set_omod5(Temp def
)
261 add_label(label_omod5
);
267 return label
& label_omod5
;
270 void set_omod_success(Instruction
* omod_instr
)
272 add_label(label_omod_success
);
276 bool is_omod_success()
278 return label
& label_omod_success
;
281 void set_clamp(Temp def
)
283 add_label(label_clamp
);
289 return label
& label_clamp
;
292 void set_clamp_success(Instruction
* clamp_instr
)
294 add_label(label_clamp_success
);
298 bool is_clamp_success()
300 return label
& label_clamp_success
;
305 add_label(label_undefined
);
310 return label
& label_undefined
;
313 void set_vcc(Temp vcc
)
315 add_label(label_vcc
);
321 return label
& label_vcc
;
324 bool is_constant_or_literal()
326 return is_constant() || is_literal();
329 void set_b2f(Temp val
)
331 add_label(label_b2f
);
337 return label
& label_b2f
;
340 void set_add_sub(Instruction
*add_sub_instr
)
342 add_label(label_add_sub
);
343 instr
= add_sub_instr
;
348 return label
& label_add_sub
;
351 void set_bitwise(Instruction
*bitwise_instr
)
353 add_label(label_bitwise
);
354 instr
= bitwise_instr
;
359 return label
& label_bitwise
;
362 void set_uniform_bitwise()
364 add_label(label_uniform_bitwise
);
367 bool is_uniform_bitwise()
369 return label
& label_uniform_bitwise
;
372 void set_minmax(Instruction
*minmax_instr
)
374 add_label(label_minmax
);
375 instr
= minmax_instr
;
380 return label
& label_minmax
;
383 void set_fcmp(Instruction
*fcmp_instr
)
385 add_label(label_fcmp
);
391 return label
& label_fcmp
;
394 void set_scc_needed()
396 add_label(label_scc_needed
);
401 return label
& label_scc_needed
;
404 void set_scc_invert(Temp scc_inv
)
406 add_label(label_scc_invert
);
412 return label
& label_scc_invert
;
415 void set_uniform_bool(Temp uniform_bool
)
417 add_label(label_uniform_bool
);
421 bool is_uniform_bool()
423 return label
& label_uniform_bool
;
428 add_label(label_vcc_hint
);
433 return label
& label_vcc_hint
;
436 void set_b2i(Temp val
)
438 add_label(label_b2i
);
444 return label
& label_b2i
;
451 std::vector
<aco_ptr
<Instruction
>> instructions
;
453 std::pair
<uint32_t,Temp
> last_literal
;
454 std::vector
<mad_info
> mad_infos
;
455 std::vector
<uint16_t> uses
;
458 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
460 if (instr
->operands
[0].isConstant() ||
461 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
464 switch (instr
->opcode
) {
465 case aco_opcode::v_add_f32
:
466 case aco_opcode::v_mul_f32
:
467 case aco_opcode::v_or_b32
:
468 case aco_opcode::v_and_b32
:
469 case aco_opcode::v_xor_b32
:
470 case aco_opcode::v_max_f32
:
471 case aco_opcode::v_min_f32
:
472 case aco_opcode::v_max_i32
:
473 case aco_opcode::v_min_i32
:
474 case aco_opcode::v_max_u32
:
475 case aco_opcode::v_min_u32
:
476 case aco_opcode::v_cmp_eq_f32
:
477 case aco_opcode::v_cmp_lg_f32
:
479 case aco_opcode::v_sub_f32
:
480 instr
->opcode
= aco_opcode::v_subrev_f32
;
482 case aco_opcode::v_cmp_lt_f32
:
483 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
485 case aco_opcode::v_cmp_ge_f32
:
486 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
488 case aco_opcode::v_cmp_lt_i32
:
489 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
496 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
501 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
504 if (instr
->isDPP() || instr
->isSDWA())
507 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
508 instr
->opcode
!= aco_opcode::v_madak_f32
&&
509 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
510 instr
->opcode
!= aco_opcode::v_madak_f16
&&
511 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
512 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
513 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
514 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
515 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
516 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
517 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
520 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
522 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
523 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
524 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
525 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
526 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
529 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
534 aco_ptr
<Instruction
> tmp
= std::move(instr
);
535 Format format
= asVOP3(tmp
->format
);
536 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
537 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
538 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
539 instr
->definitions
[i
] = tmp
->definitions
[i
];
540 if (instr
->definitions
[i
].isTemp()) {
541 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
542 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
543 info
.instr
= instr
.get();
548 /* only covers special cases */
549 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
552 case aco_opcode::v_interp_p2_f32
:
553 case aco_opcode::v_mac_f32
:
554 case aco_opcode::v_writelane_b32
:
555 case aco_opcode::v_writelane_b32_e64
:
556 case aco_opcode::v_cndmask_b32
:
558 case aco_opcode::s_addk_i32
:
559 case aco_opcode::s_mulk_i32
:
560 case aco_opcode::p_wqm
:
561 case aco_opcode::p_extract_vector
:
562 case aco_opcode::p_split_vector
:
563 case aco_opcode::v_readlane_b32
:
564 case aco_opcode::v_readlane_b32_e64
:
565 case aco_opcode::v_readfirstlane_b32
:
572 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
574 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
575 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
580 /* check constant bus and literal limitations */
581 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
583 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
584 Operand
literal32(s1
);
585 Operand
literal64(s2
);
586 unsigned num_sgprs
= 0;
587 unsigned sgpr
[] = {0, 0};
589 for (unsigned i
= 0; i
< num_operands
; i
++) {
590 Operand op
= operands
[i
];
592 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
593 /* two reads of the same SGPR count as 1 to the limit */
594 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
596 sgpr
[num_sgprs
++] = op
.tempId();
601 } else if (op
.isLiteral()) {
602 if (ctx
.program
->chip_class
< GFX10
)
605 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
607 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
610 /* Any number of 32-bit literals counts as only 1 to the limit. Same
611 * (but separately) for 64-bit literals. */
612 if (op
.size() == 1 && literal32
.isUndefined()) {
615 } else if (op
.size() == 2 && literal64
.isUndefined()) {
628 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
630 Operand op
= instr
->operands
[op_index
];
634 Temp tmp
= op
.getTemp();
635 if (!ctx
.info
[tmp
.id()].is_add_sub())
638 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
640 switch (add_instr
->opcode
) {
641 case aco_opcode::v_add_u32
:
642 case aco_opcode::v_add_co_u32
:
643 case aco_opcode::v_add_co_u32_e64
:
644 case aco_opcode::s_add_i32
:
645 case aco_opcode::s_add_u32
:
651 if (add_instr
->usesModifiers())
654 for (unsigned i
= 0; i
< 2; i
++) {
655 if (add_instr
->operands
[i
].isConstant()) {
656 *offset
= add_instr
->operands
[i
].constantValue();
657 } else if (add_instr
->operands
[i
].isTemp() &&
658 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
659 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
663 if (!add_instr
->operands
[!i
].isTemp())
666 uint32_t offset2
= 0;
667 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
670 *base
= add_instr
->operands
[!i
].getTemp();
678 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
680 if (instr
->format
== Format::PSEUDO
)
681 return instr
->operands
[index
].bytes() * 8u;
682 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
683 return index
== 2 ? 64 : 32;
684 else if (instr
->isVALU() || instr
->isSALU())
685 return instr_info
.operand_size
[(int)instr
->opcode
];
690 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
692 // TODO: this functions shouldn't be needed if we store Operand instead of value.
693 Operand
op(val
, is64bit
);
694 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
695 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
699 bool fixed_to_exec(Operand op
)
701 return op
.isFixed() && op
.physReg() == exec
;
704 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
706 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
707 ASSERTED
bool all_const
= false;
708 for (Operand
& op
: instr
->operands
)
709 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
710 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
713 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
715 if (!instr
->operands
[i
].isTemp())
718 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
719 /* propagate undef */
720 if (info
.is_undefined() && is_phi(instr
))
721 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
722 /* propagate reg->reg of same type */
723 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
724 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
725 info
= ctx
.info
[info
.temp
.id()];
728 /* SALU / PSEUDO: propagate inline constants */
729 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
730 bool is_subdword
= false;
731 // TODO: optimize SGPR and constant propagation for subdword pseudo instructions on gfx9+
732 if (instr
->format
== Format::PSEUDO
) {
733 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
734 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
735 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
736 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
741 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
742 instr
->operands
[i
].setTemp(info
.temp
);
743 info
= ctx
.info
[info
.temp
.id()];
744 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
745 /* propagate vgpr if it can take it */
746 switch (instr
->opcode
) {
747 case aco_opcode::p_create_vector
:
748 case aco_opcode::p_split_vector
:
749 case aco_opcode::p_extract_vector
:
750 case aco_opcode::p_phi
: {
751 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
752 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
754 instr
->operands
[i
] = Operand(info
.temp
);
755 info
= ctx
.info
[info
.temp
.id()];
763 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
764 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
765 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
770 /* VALU: propagate neg, abs & inline constants */
771 else if (instr
->isVALU()) {
772 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
773 instr
->operands
[i
].setTemp(info
.temp
);
774 info
= ctx
.info
[info
.temp
.id()];
777 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
778 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
779 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
781 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
784 instr
->operands
[i
] = Operand(info
.temp
);
786 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
788 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
790 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
791 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
792 instr
->operands
[i
].setTemp(info
.temp
);
794 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
795 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
796 instr
->operands
[i
].setTemp(info
.temp
);
798 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
801 instr
->operands
[i
].setTemp(info
.temp
);
803 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
805 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
808 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
809 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
810 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
811 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
812 instr
->operands
[i
] = op
;
814 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
815 instr
->operands
[i
] = instr
->operands
[0];
816 instr
->operands
[0] = op
;
818 } else if (can_use_VOP3(ctx
, instr
)) {
820 instr
->operands
[i
] = op
;
826 /* MUBUF: propagate constants and combine additions */
827 else if (instr
->format
== Format::MUBUF
) {
828 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
831 while (info
.is_temp())
832 info
= ctx
.info
[info
.temp
.id()];
834 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
835 assert(!mubuf
->idxen
);
836 instr
->operands
[1] = Operand(v1
);
837 mubuf
->offset
+= info
.val
;
838 mubuf
->offen
= false;
840 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
841 instr
->operands
[2] = Operand((uint32_t) 0);
842 mubuf
->offset
+= info
.val
;
844 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
845 assert(!mubuf
->idxen
);
846 instr
->operands
[1].setTemp(base
);
847 mubuf
->offset
+= offset
;
849 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
850 instr
->operands
[i
].setTemp(base
);
851 mubuf
->offset
+= offset
;
856 /* DS: combine additions */
857 else if (instr
->format
== Format::DS
) {
859 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
862 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
863 if (has_usable_ds_offset
&&
864 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
865 base
.regClass() == instr
->operands
[i
].regClass() &&
866 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
867 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
868 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
869 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
870 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
872 if ((offset
& mask
) == 0 &&
873 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
874 ds
->offset1
+ (offset
>> shifts
) <= 255) {
875 instr
->operands
[i
].setTemp(base
);
876 ds
->offset0
+= offset
>> shifts
;
877 ds
->offset1
+= offset
>> shifts
;
880 if (ds
->offset0
+ offset
<= 65535) {
881 instr
->operands
[i
].setTemp(base
);
882 ds
->offset0
+= offset
;
888 /* SMEM: propagate constants and combine additions */
889 else if (instr
->format
== Format::SMEM
) {
891 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
894 if (i
== 1 && info
.is_constant_or_literal() &&
895 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
896 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
897 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
898 instr
->operands
[i
] = Operand(info
.val
);
900 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
901 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
903 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
904 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
908 smem
->operands
[1] = Operand(offset
);
909 smem
->operands
.back() = Operand(base
);
911 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
912 new_instr
->operands
[0] = smem
->operands
[0];
913 new_instr
->operands
[1] = Operand(offset
);
914 if (smem
->definitions
.empty())
915 new_instr
->operands
[2] = smem
->operands
[2];
916 new_instr
->operands
.back() = Operand(base
);
917 if (!smem
->definitions
.empty())
918 new_instr
->definitions
[0] = smem
->definitions
[0];
919 new_instr
->can_reorder
= smem
->can_reorder
;
920 new_instr
->barrier
= smem
->barrier
;
921 new_instr
->glc
= smem
->glc
;
922 new_instr
->dlc
= smem
->dlc
;
923 new_instr
->nv
= smem
->nv
;
924 new_instr
->disable_wqm
= smem
->disable_wqm
;
925 instr
.reset(new_instr
);
926 smem
= static_cast<SMEM_instruction
*>(instr
.get());
932 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
933 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
934 /* Flip the branch instruction to get rid of the scc_invert instruction */
935 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
936 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
941 /* if this instruction doesn't define anything, return */
942 if (instr
->definitions
.empty())
945 switch (instr
->opcode
) {
946 case aco_opcode::p_create_vector
: {
947 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
948 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
950 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
954 unsigned num_ops
= instr
->operands
.size();
955 for (const Operand
& op
: instr
->operands
) {
956 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
957 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
959 if (num_ops
!= instr
->operands
.size()) {
960 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
961 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
962 instr
->definitions
[0] = old_vec
->definitions
[0];
964 for (Operand
& old_op
: old_vec
->operands
) {
965 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
966 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
967 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
968 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
969 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
970 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
971 instr
->operands
[k
++] = op
;
974 instr
->operands
[k
++] = old_op
;
977 assert(k
== num_ops
);
980 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
983 case aco_opcode::p_split_vector
: {
984 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
986 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
987 unsigned split_offset
= 0;
988 unsigned vec_offset
= 0;
989 unsigned vec_index
= 0;
990 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
991 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
992 vec_offset
+= vec
->operands
[vec_index
++].bytes();
994 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
997 Operand vec_op
= vec
->operands
[vec_index
];
998 if (vec_op
.isConstant()) {
999 if (vec_op
.isLiteral())
1000 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
1001 else if (vec_op
.size() == 1)
1002 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
1003 else if (vec_op
.size() == 2)
1004 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
1005 } else if (vec_op
.isUndefined()) {
1006 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1008 assert(vec_op
.isTemp());
1009 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1014 case aco_opcode::p_extract_vector
: { /* mov */
1015 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
1018 /* check if we index directly into a vector element */
1019 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1020 const unsigned index
= instr
->operands
[1].constantValue();
1021 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1022 unsigned offset
= 0;
1024 for (const Operand
& op
: vec
->operands
) {
1025 if (offset
< dst_offset
) {
1026 offset
+= op
.bytes();
1028 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1032 /* convert this extract into a copy instruction */
1033 instr
->opcode
= aco_opcode::p_parallelcopy
;
1034 instr
->operands
.pop_back();
1035 instr
->operands
[0] = op
;
1037 if (op
.isConstant()) {
1039 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(op
.constantValue());
1040 else if (op
.size() == 1)
1041 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(op
.constantValue());
1042 else if (op
.size() == 2)
1043 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(op
.constantValue());
1044 } else if (op
.isUndefined()) {
1045 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1047 assert(op
.isTemp());
1048 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1054 case aco_opcode::s_mov_b32
: /* propagate */
1055 case aco_opcode::s_mov_b64
:
1056 case aco_opcode::v_mov_b32
:
1057 case aco_opcode::p_as_uniform
:
1058 if (instr
->definitions
[0].isFixed()) {
1059 /* don't copy-propagate copies into fixed registers */
1060 } else if (instr
->usesModifiers()) {
1062 } else if (instr
->operands
[0].isConstant()) {
1063 if (instr
->operands
[0].isLiteral())
1064 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
1065 else if (instr
->operands
[0].size() == 1)
1066 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
1067 else if (instr
->operands
[0].size() == 2)
1068 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
1069 } else if (instr
->operands
[0].isTemp()) {
1070 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1072 assert(instr
->operands
[0].isFixed());
1075 case aco_opcode::p_is_helper
:
1076 if (!ctx
.program
->needs_wqm
)
1077 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1079 case aco_opcode::s_movk_i32
: {
1080 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1081 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1082 if (v
<= 64 || v
>= 0xfffffff0)
1083 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1085 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1088 case aco_opcode::v_bfrev_b32
:
1089 case aco_opcode::s_brev_b32
: {
1090 if (instr
->operands
[0].isConstant()) {
1091 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1092 if (v
<= 64 || v
>= 0xfffffff0)
1093 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1095 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1099 case aco_opcode::s_bfm_b32
: {
1100 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1101 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1102 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1103 uint32_t v
= ((1u << size
) - 1u) << start
;
1104 if (v
<= 64 || v
>= 0xfffffff0)
1105 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1107 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1111 case aco_opcode::v_mul_f16
:
1112 case aco_opcode::v_mul_f32
: { /* omod */
1113 /* TODO: try to move the negate/abs modifier to the consumer instead */
1114 if (instr
->usesModifiers())
1117 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1119 for (unsigned i
= 0; i
< 2; i
++) {
1120 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1121 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1122 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1123 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1124 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1125 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1126 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1127 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1128 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1129 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1138 case aco_opcode::v_and_b32
: { /* abs */
1139 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1140 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1141 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1142 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1143 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1145 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1148 case aco_opcode::v_xor_b32
: { /* neg */
1149 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1150 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1151 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1152 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1153 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1154 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1155 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1156 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1157 instr
->opcode
= aco_opcode::v_or_b32
;
1158 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1160 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1164 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1168 case aco_opcode::v_med3_f16
:
1169 case aco_opcode::v_med3_f32
: { /* clamp */
1170 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1171 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1172 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1173 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1177 bool found_zero
= false, found_one
= false;
1178 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1179 for (unsigned i
= 0; i
< 3; i
++)
1181 if (instr
->operands
[i
].constantEquals(0))
1183 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1188 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1189 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1193 case aco_opcode::v_cndmask_b32
:
1194 if (instr
->operands
[0].constantEquals(0) &&
1195 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1196 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1197 else if (instr
->operands
[0].constantEquals(0) &&
1198 instr
->operands
[1].constantEquals(0x3f800000u
))
1199 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1200 else if (instr
->operands
[0].constantEquals(0) &&
1201 instr
->operands
[1].constantEquals(1))
1202 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1204 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1206 case aco_opcode::v_cmp_lg_u32
:
1207 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1208 instr
->operands
[0].constantEquals(0) &&
1209 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1210 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1212 case aco_opcode::p_phi
:
1213 case aco_opcode::p_linear_phi
: {
1214 /* lower_bool_phis() can create phis like this */
1215 bool all_same_temp
= instr
->operands
[0].isTemp();
1216 /* this check is needed when moving uniform loop counters out of a divergent loop */
1218 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1219 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1220 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1221 all_same_temp
= false;
1223 if (all_same_temp
) {
1224 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1226 bool all_undef
= instr
->operands
[0].isUndefined();
1227 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1228 if (!instr
->operands
[i
].isUndefined())
1232 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1236 case aco_opcode::v_add_u32
:
1237 case aco_opcode::v_add_co_u32
:
1238 case aco_opcode::v_add_co_u32_e64
:
1239 case aco_opcode::s_add_i32
:
1240 case aco_opcode::s_add_u32
:
1241 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1243 case aco_opcode::s_not_b32
:
1244 case aco_opcode::s_not_b64
:
1245 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1246 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1247 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1248 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1249 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1250 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1252 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1254 case aco_opcode::s_and_b32
:
1255 case aco_opcode::s_and_b64
:
1256 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1257 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1258 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1259 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1260 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1262 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1263 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1264 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1265 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1270 case aco_opcode::s_or_b32
:
1271 case aco_opcode::s_or_b64
:
1272 case aco_opcode::s_xor_b32
:
1273 case aco_opcode::s_xor_b64
:
1274 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1275 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1277 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1280 case aco_opcode::s_lshl_b32
:
1281 case aco_opcode::v_or_b32
:
1282 case aco_opcode::v_lshlrev_b32
:
1283 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1285 case aco_opcode::v_min_f32
:
1286 case aco_opcode::v_min_f16
:
1287 case aco_opcode::v_min_u32
:
1288 case aco_opcode::v_min_i32
:
1289 case aco_opcode::v_min_u16
:
1290 case aco_opcode::v_min_i16
:
1291 case aco_opcode::v_max_f32
:
1292 case aco_opcode::v_max_f16
:
1293 case aco_opcode::v_max_u32
:
1294 case aco_opcode::v_max_i32
:
1295 case aco_opcode::v_max_u16
:
1296 case aco_opcode::v_max_i16
:
1297 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1299 case aco_opcode::v_cmp_lt_f32
:
1300 case aco_opcode::v_cmp_eq_f32
:
1301 case aco_opcode::v_cmp_le_f32
:
1302 case aco_opcode::v_cmp_gt_f32
:
1303 case aco_opcode::v_cmp_lg_f32
:
1304 case aco_opcode::v_cmp_ge_f32
:
1305 case aco_opcode::v_cmp_o_f32
:
1306 case aco_opcode::v_cmp_u_f32
:
1307 case aco_opcode::v_cmp_nge_f32
:
1308 case aco_opcode::v_cmp_nlg_f32
:
1309 case aco_opcode::v_cmp_ngt_f32
:
1310 case aco_opcode::v_cmp_nle_f32
:
1311 case aco_opcode::v_cmp_neq_f32
:
1312 case aco_opcode::v_cmp_nlt_f32
:
1313 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1315 case aco_opcode::s_cselect_b64
:
1316 case aco_opcode::s_cselect_b32
:
1317 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1318 instr
->operands
[1].constantEquals(0)) {
1319 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1320 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1322 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1323 /* Flip the operands to get rid of the scc_invert instruction */
1324 std::swap(instr
->operands
[0], instr
->operands
[1]);
1325 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1328 case aco_opcode::p_wqm
:
1329 if (instr
->operands
[0].isTemp() &&
1330 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1331 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1339 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1341 *ordered
= *unordered
= op
;
1343 #define CMP(ord, unord) \
1344 case aco_opcode::v_cmp_##ord##_f32:\
1345 case aco_opcode::v_cmp_n##unord##_f32:\
1346 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1347 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1348 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1362 aco_opcode
get_ordered(aco_opcode op
)
1364 aco_opcode ordered
, unordered
, inverse
;
1365 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::num_opcodes
;
1368 aco_opcode
get_unordered(aco_opcode op
)
1370 aco_opcode ordered
, unordered
, inverse
;
1371 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::num_opcodes
;
1374 aco_opcode
get_inverse(aco_opcode op
)
1376 aco_opcode ordered
, unordered
, inverse
;
1377 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::num_opcodes
;
1380 bool is_cmp(aco_opcode op
)
1382 aco_opcode ordered
, unordered
, inverse
;
1383 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1386 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1388 if (ctx
.info
[tmp
.id()].is_temp())
1389 return ctx
.info
[tmp
.id()].temp
.id();
1394 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1396 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1397 for (const Operand
& op
: instr
->operands
) {
1399 ctx
.uses
[op
.tempId()]--;
1404 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1406 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1408 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1411 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1413 if (instr
->definitions
.size() == 2) {
1414 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1415 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1422 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1423 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1424 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1426 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1428 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1431 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1433 bool neg
[2] = {false, false};
1434 bool abs
[2] = {false, false};
1436 Instruction
*op_instr
[2];
1439 for (unsigned i
= 0; i
< 2; i
++) {
1440 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1444 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1446 if (op_instr
[i
]->opcode
!= expected_cmp
)
1448 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1451 if (op_instr
[i
]->isVOP3()) {
1452 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1453 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1455 neg
[i
] = vop3
->neg
[0];
1456 abs
[i
] = vop3
->abs
[0];
1457 opsel
|= (vop3
->opsel
& 1) << i
;
1460 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1461 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1462 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1468 if (op
[1].type() == RegType::sgpr
)
1469 std::swap(op
[0], op
[1]);
1470 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1471 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1474 ctx
.uses
[op
[0].id()]++;
1475 ctx
.uses
[op
[1].id()]++;
1476 decrease_uses(ctx
, op_instr
[0]);
1477 decrease_uses(ctx
, op_instr
[1]);
1479 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1480 Instruction
*new_instr
;
1481 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1482 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1483 for (unsigned i
= 0; i
< 2; i
++) {
1484 vop3
->neg
[i
] = neg
[i
];
1485 vop3
->abs
[i
] = abs
[i
];
1487 vop3
->opsel
= opsel
;
1488 new_instr
= static_cast<Instruction
*>(vop3
);
1490 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1492 new_instr
->operands
[0] = Operand(op
[0]);
1493 new_instr
->operands
[1] = Operand(op
[1]);
1494 new_instr
->definitions
[0] = instr
->definitions
[0];
1496 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1497 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1499 instr
.reset(new_instr
);
1504 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1505 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1506 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1508 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1510 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1513 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1514 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1516 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1517 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1518 if (!nan_test
|| !cmp
)
1521 if (cmp
->opcode
== expected_nan_test
)
1522 std::swap(nan_test
, cmp
);
1523 else if (nan_test
->opcode
!= expected_nan_test
)
1526 if (!is_cmp(cmp
->opcode
))
1529 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1531 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1534 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1535 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1536 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1537 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1538 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1540 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1543 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1544 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1545 decrease_uses(ctx
, nan_test
);
1546 decrease_uses(ctx
, cmp
);
1548 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1549 Instruction
*new_instr
;
1550 if (cmp
->isVOP3()) {
1551 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1552 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1553 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1554 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1555 new_vop3
->clamp
= cmp_vop3
->clamp
;
1556 new_vop3
->omod
= cmp_vop3
->omod
;
1557 new_vop3
->opsel
= cmp_vop3
->opsel
;
1558 new_instr
= new_vop3
;
1560 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1562 new_instr
->operands
[0] = cmp
->operands
[0];
1563 new_instr
->operands
[1] = cmp
->operands
[1];
1564 new_instr
->definitions
[0] = instr
->definitions
[0];
1566 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1567 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1569 instr
.reset(new_instr
);
1574 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1575 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1576 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1578 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1580 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1583 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1585 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1586 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1588 if (!nan_test
|| !cmp
)
1591 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1592 if (cmp
->opcode
== expected_nan_test
)
1593 std::swap(nan_test
, cmp
);
1594 else if (nan_test
->opcode
!= expected_nan_test
)
1597 if (!is_cmp(cmp
->opcode
))
1600 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1602 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1605 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1606 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1607 if (prop_nan0
!= prop_nan1
)
1610 if (nan_test
->isVOP3()) {
1611 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1612 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1616 int constant_operand
= -1;
1617 for (unsigned i
= 0; i
< 2; i
++) {
1618 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1619 constant_operand
= !i
;
1623 if (constant_operand
== -1)
1627 if (cmp
->operands
[constant_operand
].isConstant()) {
1628 constant
= cmp
->operands
[constant_operand
].constantValue();
1629 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1630 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1631 unsigned id
= original_temp_id(ctx
, tmp
);
1632 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1634 constant
= ctx
.info
[id
].val
;
1640 memcpy(&constantf
, &constant
, 4);
1641 if (isnan(constantf
))
1644 if (cmp
->operands
[0].isTemp())
1645 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1646 if (cmp
->operands
[1].isTemp())
1647 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1648 decrease_uses(ctx
, nan_test
);
1649 decrease_uses(ctx
, cmp
);
1651 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1652 Instruction
*new_instr
;
1653 if (cmp
->isVOP3()) {
1654 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1655 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1656 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1657 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1658 new_vop3
->clamp
= cmp_vop3
->clamp
;
1659 new_vop3
->omod
= cmp_vop3
->omod
;
1660 new_vop3
->opsel
= cmp_vop3
->opsel
;
1661 new_instr
= new_vop3
;
1663 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1665 new_instr
->operands
[0] = cmp
->operands
[0];
1666 new_instr
->operands
[1] = cmp
->operands
[1];
1667 new_instr
->definitions
[0] = instr
->definitions
[0];
1669 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1670 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1672 instr
.reset(new_instr
);
1677 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1678 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1680 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1682 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1684 if (!instr
->operands
[0].isTemp())
1687 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1691 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1692 if (new_opcode
== aco_opcode::num_opcodes
)
1695 if (cmp
->operands
[0].isTemp())
1696 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1697 if (cmp
->operands
[1].isTemp())
1698 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1699 decrease_uses(ctx
, cmp
);
1701 Instruction
*new_instr
;
1702 if (cmp
->isVOP3()) {
1703 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1704 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1705 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1706 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1707 new_vop3
->clamp
= cmp_vop3
->clamp
;
1708 new_vop3
->omod
= cmp_vop3
->omod
;
1709 new_vop3
->opsel
= cmp_vop3
->opsel
;
1710 new_instr
= new_vop3
;
1712 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1714 new_instr
->operands
[0] = cmp
->operands
[0];
1715 new_instr
->operands
[1] = cmp
->operands
[1];
1716 new_instr
->definitions
[0] = instr
->definitions
[0];
1718 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1719 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1721 instr
.reset(new_instr
);
1726 /* op1(op2(1, 2), 0) if swap = false
1727 * op1(0, op2(1, 2)) if swap = true */
1728 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1729 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1730 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1731 bool *op1_clamp
, uint8_t *op1_omod
,
1732 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1735 if (op1_instr
->opcode
!= op1
)
1738 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1739 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1741 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1744 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1745 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1747 /* don't support inbetween clamp/omod */
1748 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1751 /* get operands and modifiers and check inbetween modifiers */
1752 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1753 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1756 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1757 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1761 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1762 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1765 if (inbetween_opsel
)
1766 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1767 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1771 shuffle
[shuffle_str
[0] - '0'] = 0;
1772 shuffle
[shuffle_str
[1] - '0'] = 1;
1773 shuffle
[shuffle_str
[2] - '0'] = 2;
1775 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1776 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1777 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1778 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1779 *opsel
|= 1 << shuffle
[0];
1781 for (unsigned i
= 0; i
< 2; i
++) {
1782 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1783 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1784 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1785 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1786 *opsel
|= 1 << shuffle
[i
+ 1];
1789 /* check operands */
1790 if (!check_vop3_operands(ctx
, 3, operands
))
1796 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1797 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1798 bool clamp
, unsigned omod
)
1800 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1801 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1802 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1803 new_instr
->clamp
= clamp
;
1804 new_instr
->omod
= omod
;
1805 new_instr
->opsel
= opsel
;
1806 new_instr
->operands
[0] = operands
[0];
1807 new_instr
->operands
[1] = operands
[1];
1808 new_instr
->operands
[2] = operands
[2];
1809 new_instr
->definitions
[0] = instr
->definitions
[0];
1810 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1812 instr
.reset(new_instr
);
1815 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1817 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1818 (label_omod_success
| label_clamp_success
);
1820 for (unsigned swap
= 0; swap
< 2; swap
++) {
1821 if (!((1 << swap
) & ops
))
1824 Operand operands
[3];
1825 bool neg
[3], abs
[3], clamp
;
1826 uint8_t opsel
= 0, omod
= 0;
1827 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1828 instr
.get(), swap
, shuffle
,
1829 operands
, neg
, abs
, &opsel
,
1830 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1831 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1832 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1833 if (omod_clamp
& label_omod_success
)
1834 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1835 if (omod_clamp
& label_clamp_success
)
1836 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1843 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1845 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1848 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1849 (label_omod_success
| label_clamp_success
);
1851 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1852 * max(-min(a, b), c) -> max3(-a, -b, c) */
1853 for (unsigned swap
= 0; swap
< 2; swap
++) {
1854 Operand operands
[3];
1855 bool neg
[3], abs
[3], clamp
;
1856 uint8_t opsel
= 0, omod
= 0;
1858 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1859 instr
.get(), swap
, "012",
1860 operands
, neg
, abs
, &opsel
,
1861 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1863 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1866 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1867 if (omod_clamp
& label_omod_success
)
1868 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1869 if (omod_clamp
& label_clamp_success
)
1870 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1877 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1878 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1879 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1880 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1881 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1882 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1883 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1886 if (!instr
->operands
[0].isTemp())
1888 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1891 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1894 switch (op2_instr
->opcode
) {
1895 case aco_opcode::s_and_b32
:
1896 case aco_opcode::s_or_b32
:
1897 case aco_opcode::s_xor_b32
:
1898 case aco_opcode::s_and_b64
:
1899 case aco_opcode::s_or_b64
:
1900 case aco_opcode::s_xor_b64
:
1906 /* create instruction */
1907 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1908 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1909 ctx
.uses
[instr
->operands
[0].tempId()]--;
1910 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1912 switch (op2_instr
->opcode
) {
1913 case aco_opcode::s_and_b32
:
1914 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1916 case aco_opcode::s_or_b32
:
1917 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1919 case aco_opcode::s_xor_b32
:
1920 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1922 case aco_opcode::s_and_b64
:
1923 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1925 case aco_opcode::s_or_b64
:
1926 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1928 case aco_opcode::s_xor_b64
:
1929 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1938 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1939 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1940 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1941 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1942 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1944 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1947 for (unsigned i
= 0; i
< 2; i
++) {
1948 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1949 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1951 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1954 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1955 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1958 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1959 instr
->operands
[0] = instr
->operands
[!i
];
1960 instr
->operands
[1] = op2_instr
->operands
[0];
1961 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1963 switch (instr
->opcode
) {
1964 case aco_opcode::s_and_b32
:
1965 instr
->opcode
= aco_opcode::s_andn2_b32
;
1967 case aco_opcode::s_or_b32
:
1968 instr
->opcode
= aco_opcode::s_orn2_b32
;
1970 case aco_opcode::s_and_b64
:
1971 instr
->opcode
= aco_opcode::s_andn2_b64
;
1973 case aco_opcode::s_or_b64
:
1974 instr
->opcode
= aco_opcode::s_orn2_b64
;
1985 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1986 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1988 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1991 for (unsigned i
= 0; i
< 2; i
++) {
1992 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1993 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1994 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1996 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1999 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2000 if (shift
< 1 || shift
> 4)
2003 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2004 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2007 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2008 instr
->operands
[1] = instr
->operands
[!i
];
2009 instr
->operands
[0] = op2_instr
->operands
[0];
2010 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2012 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2013 aco_opcode::s_lshl2_add_u32
,
2014 aco_opcode::s_lshl3_add_u32
,
2015 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2022 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2024 if (instr
->usesModifiers())
2027 for (unsigned i
= 0; i
< 2; i
++) {
2028 if (!((1 << i
) & ops
))
2030 if (instr
->operands
[i
].isTemp() &&
2031 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2032 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2034 aco_ptr
<Instruction
> new_instr
;
2035 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2036 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2037 } else if (ctx
.program
->chip_class
>= GFX10
||
2038 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2039 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2043 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2044 new_instr
->definitions
[0] = instr
->definitions
[0];
2045 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2046 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2047 new_instr
->definitions
[1].setHint(vcc
);
2048 new_instr
->operands
[0] = Operand(0u);
2049 new_instr
->operands
[1] = instr
->operands
[!i
];
2050 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2051 instr
= std::move(new_instr
);
2052 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2060 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2063 #define MINMAX(type, gfx9) \
2064 case aco_opcode::v_min_##type:\
2065 case aco_opcode::v_max_##type:\
2066 case aco_opcode::v_med3_##type:\
2067 *min = aco_opcode::v_min_##type;\
2068 *max = aco_opcode::v_max_##type;\
2069 *med3 = aco_opcode::v_med3_##type;\
2070 *min3 = aco_opcode::v_min3_##type;\
2071 *max3 = aco_opcode::v_max3_##type;\
2072 *some_gfx9_only = gfx9;\
2086 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2087 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2088 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2089 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2091 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2092 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2093 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2094 aco_opcode other_op
;
2095 if (instr
->opcode
== min
)
2097 else if (instr
->opcode
== max
)
2102 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2103 (label_omod_success
| label_clamp_success
);
2105 for (unsigned swap
= 0; swap
< 2; swap
++) {
2106 Operand operands
[3];
2107 bool neg
[3], abs
[3], clamp
;
2108 uint8_t opsel
= 0, omod
= 0;
2109 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2110 "012", operands
, neg
, abs
, &opsel
,
2111 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2112 int const0_idx
= -1, const1_idx
= -1;
2113 uint32_t const0
= 0, const1
= 0;
2114 for (int i
= 0; i
< 3; i
++) {
2116 if (operands
[i
].isConstant()) {
2117 val
= operands
[i
].constantValue();
2118 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
2119 val
= ctx
.info
[operands
[i
].tempId()].val
;
2123 if (const0_idx
>= 0) {
2131 if (const0_idx
< 0 || const1_idx
< 0)
2134 if (opsel
& (1 << const0_idx
))
2136 if (opsel
& (1 << const1_idx
))
2139 int lower_idx
= const0_idx
;
2141 case aco_opcode::v_min_f32
:
2142 case aco_opcode::v_min_f16
: {
2143 float const0_f
, const1_f
;
2144 if (min
== aco_opcode::v_min_f32
) {
2145 memcpy(&const0_f
, &const0
, 4);
2146 memcpy(&const1_f
, &const1
, 4);
2148 const0_f
= _mesa_half_to_float(const0
);
2149 const1_f
= _mesa_half_to_float(const1
);
2151 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2152 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2153 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2154 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2155 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2158 case aco_opcode::v_min_u32
: {
2159 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2162 case aco_opcode::v_min_u16
: {
2163 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2166 case aco_opcode::v_min_i32
: {
2167 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2168 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2169 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2172 case aco_opcode::v_min_i16
: {
2173 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2174 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2175 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2181 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2183 if (instr
->opcode
== min
) {
2184 if (upper_idx
!= 0 || lower_idx
== 0)
2187 if (upper_idx
== 0 || lower_idx
!= 0)
2191 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2192 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2193 if (omod_clamp
& label_omod_success
)
2194 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2195 if (omod_clamp
& label_clamp_success
)
2196 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2206 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2208 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2209 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2210 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2212 /* find candidates and create the set of sgprs already read */
2213 unsigned sgpr_ids
[2] = {0, 0};
2214 uint32_t operand_mask
= 0;
2215 bool has_literal
= false;
2216 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2217 if (instr
->operands
[i
].isLiteral())
2219 if (!instr
->operands
[i
].isTemp())
2221 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2222 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2223 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2225 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2226 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2227 operand_mask
|= 1u << i
;
2229 unsigned max_sgprs
= 1;
2230 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2235 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2237 /* keep on applying sgprs until there is nothing left to be done */
2238 while (operand_mask
) {
2239 uint32_t sgpr_idx
= 0;
2240 uint32_t sgpr_info_id
= 0;
2241 uint32_t mask
= operand_mask
;
2244 unsigned i
= u_bit_scan(&mask
);
2245 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2246 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2248 sgpr_info_id
= instr
->operands
[i
].tempId();
2251 operand_mask
&= ~(1u << sgpr_idx
);
2253 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2254 * definitively beneficial.
2255 * TODO: this is too conservative because later the use count could be reduced to 1 */
2256 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2259 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2260 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2261 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2264 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2265 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2266 } else if (can_swap_operands(instr
)) {
2267 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2268 instr
->operands
[0] = Operand(sgpr
);
2269 /* swap bits using a 4-entry LUT */
2270 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2271 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2272 } else if (can_use_VOP3(ctx
, instr
)) {
2273 to_VOP3(ctx
, instr
);
2274 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2280 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2281 ctx
.uses
[sgpr_info_id
]--;
2282 ctx
.uses
[sgpr
.id()]++;
2286 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2288 /* check if we could apply omod on predecessor */
2289 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2290 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2291 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2293 unsigned idx
= op0
? 0 : 1;
2294 /* omod was successfully applied */
2295 /* if the omod instruction is v_mad, we also have to change the original add */
2296 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2297 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2298 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2299 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2300 add_instr
->definitions
[0] = instr
->definitions
[0];
2303 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2304 /* check if we have an additional clamp modifier */
2305 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2306 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2307 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2308 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2310 /* change definition ssa-id of modified instruction */
2311 omod_instr
->definitions
[0] = instr
->definitions
[0];
2313 /* change the definition of instr to something unused, e.g. the original omod def */
2314 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2315 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2318 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2319 /* in all other cases, label this instruction as option for multiply-add */
2320 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2324 /* check if we could apply clamp on predecessor */
2325 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2326 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2328 bool found_zero
= false, found_one
= false;
2329 for (unsigned i
= 0; i
< 3; i
++)
2331 if (instr
->operands
[i
].constantEquals(0))
2333 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2338 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2339 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2340 /* clamp was successfully applied */
2341 /* if the clamp instruction is v_mad, we also have to change the original add */
2342 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2343 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2344 add_instr
->definitions
[0] = instr
->definitions
[0];
2346 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2347 /* change definition ssa-id of modified instruction */
2348 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2350 /* change the definition of instr to something unused, e.g. the original omod def */
2351 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2352 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2357 /* omod has no effect if denormals are enabled */
2358 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2359 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2360 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2361 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2362 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2363 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2364 to_VOP3(ctx
, instr
);
2365 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2366 def_info
.set_omod_success(instr
.get());
2367 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2368 to_VOP3(ctx
, instr
);
2369 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2370 def_info
.set_omod_success(instr
.get());
2371 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2372 to_VOP3(ctx
, instr
);
2373 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2374 def_info
.set_omod_success(instr
.get());
2375 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2376 to_VOP3(ctx
, instr
);
2377 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2378 def_info
.set_clamp_success(instr
.get());
2385 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2386 // this would mean that we'd have to fix the instruction uses while value propagation
2388 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2390 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2393 if (instr
->isVALU()) {
2394 if (can_apply_sgprs(instr
))
2395 apply_sgprs(ctx
, instr
);
2396 if (apply_omod_clamp(ctx
, block
, instr
))
2400 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2401 instr
->definitions
[0].setHint(vcc
);
2404 /* TODO: There are still some peephole optimizations that could be done:
2405 * - abs(a - b) -> s_absdiff_i32
2406 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2407 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2408 * These aren't probably too interesting though.
2409 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2410 * probably more useful than the previously mentioned optimizations.
2411 * The various comparison optimizations also currently only work with 32-bit
2414 /* neg(mul(a, b)) -> mul(neg(a), b) */
2415 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2416 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2418 if (!ctx
.info
[val
.id()].is_mul())
2421 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2423 if (mul_instr
->operands
[0].isLiteral())
2425 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2428 /* convert to mul(neg(a), b) */
2429 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2430 Definition def
= instr
->definitions
[0];
2431 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2432 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2433 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2434 instr
->operands
[0] = mul_instr
->operands
[0];
2435 instr
->operands
[1] = mul_instr
->operands
[1];
2436 instr
->definitions
[0] = def
;
2437 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2438 if (mul_instr
->isVOP3()) {
2439 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2440 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2441 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2442 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2443 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2444 new_mul
->omod
= mul
->omod
;
2446 new_mul
->neg
[0] ^= true;
2447 new_mul
->clamp
= false;
2449 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2453 /* combine mul+add -> mad */
2454 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2455 instr
->opcode
== aco_opcode::v_sub_f32
||
2456 instr
->opcode
== aco_opcode::v_subrev_f32
;
2457 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2458 instr
->opcode
== aco_opcode::v_sub_f16
||
2459 instr
->opcode
== aco_opcode::v_subrev_f16
;
2460 if (mad16
|| mad32
) {
2461 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2462 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2463 if (need_fma
&& instr
->definitions
[0].isPrecise())
2465 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2468 uint32_t uses_src0
= UINT32_MAX
;
2469 uint32_t uses_src1
= UINT32_MAX
;
2470 Instruction
* mul_instr
= nullptr;
2471 unsigned add_op_idx
;
2472 /* check if any of the operands is a multiplication */
2473 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2474 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2475 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2476 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2477 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2478 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2480 /* find the 'best' mul instruction to combine with the add */
2481 if (uses_src0
< uses_src1
) {
2482 mul_instr
= op0_info
->instr
;
2484 } else if (uses_src1
< uses_src0
) {
2485 mul_instr
= op1_info
->instr
;
2487 } else if (uses_src0
!= UINT32_MAX
) {
2488 /* tiebreaker: quite random what to pick */
2489 if (op0_info
->instr
->operands
[0].isLiteral()) {
2490 mul_instr
= op1_info
->instr
;
2493 mul_instr
= op0_info
->instr
;
2498 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2499 bool neg
[3] = {false, false, false};
2500 bool abs
[3] = {false, false, false};
2503 op
[0] = mul_instr
->operands
[0];
2504 op
[1] = mul_instr
->operands
[1];
2505 op
[2] = instr
->operands
[add_op_idx
];
2506 // TODO: would be better to check this before selecting a mul instr?
2507 if (!check_vop3_operands(ctx
, 3, op
))
2510 if (mul_instr
->isVOP3()) {
2511 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2512 neg
[0] = vop3
->neg
[0];
2513 neg
[1] = vop3
->neg
[1];
2514 abs
[0] = vop3
->abs
[0];
2515 abs
[1] = vop3
->abs
[1];
2516 /* we cannot use these modifiers between mul and add */
2517 if (vop3
->clamp
|| vop3
->omod
)
2521 /* convert to mad */
2522 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2523 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2525 ctx
.uses
[op
[0].tempId()]++;
2527 ctx
.uses
[op
[1].tempId()]++;
2530 if (instr
->isVOP3()) {
2531 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2532 neg
[2] = vop3
->neg
[add_op_idx
];
2533 abs
[2] = vop3
->abs
[add_op_idx
];
2535 clamp
= vop3
->clamp
;
2536 /* abs of the multiplication result */
2537 if (vop3
->abs
[1 - add_op_idx
]) {
2543 /* neg of the multiplication result */
2544 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2546 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2547 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2548 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2549 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2551 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2553 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2554 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2556 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2557 for (unsigned i
= 0; i
< 3; i
++)
2559 mad
->operands
[i
] = op
[i
];
2560 mad
->neg
[i
] = neg
[i
];
2561 mad
->abs
[i
] = abs
[i
];
2565 mad
->definitions
[0] = instr
->definitions
[0];
2567 /* mark this ssa_def to be re-checked for profitability and literals */
2568 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2569 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2570 instr
.reset(mad
.release());
2574 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2575 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2576 for (unsigned i
= 0; i
< 2; i
++) {
2577 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2578 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2579 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2580 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2581 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2583 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2584 new_instr
->operands
[0] = Operand(0u);
2585 new_instr
->operands
[1] = instr
->operands
[!i
];
2586 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2587 new_instr
->definitions
[0] = instr
->definitions
[0];
2588 instr
.reset(new_instr
.release());
2589 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2593 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2594 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2595 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2596 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2597 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2598 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2599 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2600 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2601 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2602 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2603 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2604 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2605 else if (ctx
.program
->chip_class
>= GFX9
) {
2606 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2607 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2608 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2609 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2610 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2611 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2612 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2614 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2615 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2616 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2617 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2618 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2619 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2620 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2621 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2622 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2623 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2624 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2625 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2626 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2627 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2628 combine_salu_lshl_add(ctx
, instr
);
2629 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2630 combine_salu_not_bitwise(ctx
, instr
);
2631 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2632 if (combine_inverse_comparison(ctx
, instr
)) ;
2633 else combine_salu_not_bitwise(ctx
, instr
);
2634 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2635 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2636 if (combine_ordering_test(ctx
, instr
)) ;
2637 else if (combine_comparison_ordering(ctx
, instr
)) ;
2638 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2639 else combine_salu_n2(ctx
, instr
);
2641 aco_opcode min
, max
, min3
, max3
, med3
;
2642 bool some_gfx9_only
;
2643 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2644 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2645 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2646 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2651 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2653 switch (instr
->opcode
) {
2654 case aco_opcode::s_and_b32
:
2655 case aco_opcode::s_and_b64
:
2656 instr
->opcode
= aco_opcode::s_and_b32
;
2658 case aco_opcode::s_or_b32
:
2659 case aco_opcode::s_or_b64
:
2660 instr
->opcode
= aco_opcode::s_or_b32
;
2662 case aco_opcode::s_xor_b32
:
2663 case aco_opcode::s_xor_b64
:
2664 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2667 /* Don't transform other instructions. They are very unlikely to appear here. */
2671 for (Operand
&op
: instr
->operands
) {
2672 ctx
.uses
[op
.tempId()]--;
2674 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2675 /* Just use the uniform boolean temp. */
2676 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2677 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2678 /* Use the SCC definition of the predecessor instruction.
2679 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2680 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2682 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2683 assert(pred_instr
->definitions
.size() >= 2);
2684 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2685 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2687 unreachable("Invalid operand on uniform bitwise instruction.");
2690 ctx
.uses
[op
.tempId()]++;
2693 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2694 assert(instr
->operands
[0].regClass() == s1
);
2695 assert(instr
->operands
[1].regClass() == s1
);
2699 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2701 const uint32_t threshold
= 4;
2703 if (is_dead(ctx
.uses
, instr
.get())) {
2708 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2709 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2710 unsigned num_used
= 0;
2712 unsigned split_offset
= 0;
2713 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2714 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2717 split_offset
= offset
;
2721 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2722 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2723 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2727 for (Operand
& vec_op
: vec
->operands
) {
2728 if (off
== split_offset
) {
2732 off
+= vec_op
.bytes();
2734 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2735 ctx
.uses
[instr
->operands
[0].tempId()]--;
2736 for (Operand
& vec_op
: vec
->operands
) {
2737 if (vec_op
.isTemp())
2738 ctx
.uses
[vec_op
.tempId()]--;
2741 ctx
.uses
[op
.tempId()]++;
2743 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2744 extract
->operands
[0] = op
;
2745 extract
->definitions
[0] = instr
->definitions
[idx
];
2746 instr
.reset(extract
.release());
2752 if (!done
&& num_used
== 1 &&
2753 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2754 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2755 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2756 extract
->operands
[0] = instr
->operands
[0];
2757 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2758 extract
->definitions
[0] = instr
->definitions
[idx
];
2759 instr
.reset(extract
.release());
2763 mad_info
* mad_info
= NULL
;
2764 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2765 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2766 /* re-check mad instructions */
2767 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2768 ctx
.uses
[mad_info
->mul_temp_id
]++;
2769 if (instr
->operands
[0].isTemp())
2770 ctx
.uses
[instr
->operands
[0].tempId()]--;
2771 if (instr
->operands
[1].isTemp())
2772 ctx
.uses
[instr
->operands
[1].tempId()]--;
2773 instr
.swap(mad_info
->add_instr
);
2776 /* check literals */
2777 else if (!instr
->usesModifiers()) {
2778 /* FMA can only take literals on GFX10+ */
2779 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2780 ctx
.program
->chip_class
< GFX10
)
2783 bool sgpr_used
= false;
2784 uint32_t literal_idx
= 0;
2785 uint32_t literal_uses
= UINT32_MAX
;
2786 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2788 if (instr
->operands
[i
].isConstant() && i
> 0) {
2789 literal_uses
= UINT32_MAX
;
2792 if (!instr
->operands
[i
].isTemp())
2794 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2795 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2796 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2797 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2800 literal_uses
= UINT32_MAX
;
2803 /* don't break because we still need to check constants */
2804 } else if (!sgpr_used
&&
2805 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2806 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2807 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2812 /* Limit the number of literals to apply to not increase the code
2813 * size too much, but always apply literals for v_mad->v_madak
2814 * because both instructions are 64-bit and this doesn't increase
2816 * TODO: try to apply the literals earlier to lower the number of
2817 * uses below threshold
2819 if (literal_uses
< threshold
|| literal_idx
== 2) {
2820 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2821 mad_info
->check_literal
= true;
2822 mad_info
->literal_idx
= literal_idx
;
2828 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2829 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2830 instr
->operands
.size() &&
2831 instr
->operands
[0].isTemp()) {
2832 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2834 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2835 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2836 instr
->operands
[2].isTemp()) {
2837 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2840 /* check for literals */
2841 if (!instr
->isSALU() && !instr
->isVALU())
2844 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2845 if (instr
->definitions
.size() &&
2846 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2847 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2848 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2850 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2851 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2852 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2853 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2854 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2855 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2861 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2862 return; /* some encodings can't ever take literals */
2864 /* we do not apply the literals yet as we don't know if it is profitable */
2865 Operand
current_literal(s1
);
2867 unsigned literal_id
= 0;
2868 unsigned literal_uses
= UINT32_MAX
;
2869 Operand
literal(s1
);
2870 unsigned num_operands
= 1;
2871 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2872 num_operands
= instr
->operands
.size();
2873 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2874 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2877 unsigned sgpr_ids
[2] = {0, 0};
2878 bool is_literal_sgpr
= false;
2881 /* choose a literal to apply */
2882 for (unsigned i
= 0; i
< num_operands
; i
++) {
2883 Operand op
= instr
->operands
[i
];
2885 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2886 op
.tempId() != sgpr_ids
[0])
2887 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2889 if (op
.isLiteral()) {
2890 current_literal
= op
;
2892 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2896 if (!alu_can_accept_constant(instr
->opcode
, i
))
2899 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2900 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2902 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2903 literal_uses
= ctx
.uses
[op
.tempId()];
2904 literal_id
= op
.tempId();
2907 mask
|= (op
.tempId() == literal_id
) << i
;
2911 /* don't go over the constant bus limit */
2912 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2913 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2914 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2915 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2916 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2917 const_bus_limit
= 2;
2919 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2920 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2923 if (literal_id
&& literal_uses
< threshold
&&
2924 (current_literal
.isUndefined() ||
2925 (current_literal
.size() == literal
.size() &&
2926 current_literal
.constantValue() == literal
.constantValue()))) {
2927 /* mark the literal to be applied */
2929 unsigned i
= u_bit_scan(&mask
);
2930 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2931 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2937 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2939 /* Cleanup Dead Instructions */
2943 /* apply literals on MAD */
2944 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2945 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2946 if (info
->check_literal
&&
2947 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2948 aco_ptr
<Instruction
> new_mad
;
2950 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
2951 if (instr
->opcode
== aco_opcode::v_fma_f32
)
2952 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
2953 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
2954 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
2955 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
2956 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
2958 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
2959 if (info
->literal_idx
== 2) { /* add literal -> madak */
2960 new_mad
->operands
[0] = instr
->operands
[0];
2961 new_mad
->operands
[1] = instr
->operands
[1];
2962 } else { /* mul literal -> madmk */
2963 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2964 new_mad
->operands
[1] = instr
->operands
[2];
2966 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2967 new_mad
->definitions
[0] = instr
->definitions
[0];
2968 ctx
.instructions
.emplace_back(std::move(new_mad
));
2973 /* apply literals on other SALU/VALU */
2974 if (instr
->isSALU() || instr
->isVALU()) {
2975 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2976 Operand op
= instr
->operands
[i
];
2977 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2978 Operand
literal(ctx
.info
[op
.tempId()].val
);
2979 if (instr
->isVALU() && i
> 0)
2980 to_VOP3(ctx
, instr
);
2981 instr
->operands
[i
] = literal
;
2986 ctx
.instructions
.emplace_back(std::move(instr
));
2990 void optimize(Program
* program
)
2993 ctx
.program
= program
;
2994 std::vector
<ssa_info
> info(program
->peekAllocationId());
2995 ctx
.info
= info
.data();
2997 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2998 for (Block
& block
: program
->blocks
) {
2999 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3000 label_instruction(ctx
, block
, instr
);
3003 ctx
.uses
= dead_code_analysis(program
);
3005 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3006 for (Block
& block
: program
->blocks
) {
3007 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3008 combine_instruction(ctx
, block
, instr
);
3011 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3012 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3013 Block
* block
= &(*it
);
3014 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3015 select_instruction(ctx
, *it
);
3018 /* 4. Add literals to instructions */
3019 for (Block
& block
: program
->blocks
) {
3020 ctx
.instructions
.clear();
3021 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3022 apply_literals(ctx
, instr
);
3023 block
.instructions
.swap(ctx
.instructions
);