2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
96 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
97 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
98 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
99 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
100 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
110 ssa_info() : label(0) {}
112 void add_label(Label new_label
)
114 /* Since all labels which use "instr" use it for the same thing
115 * (indicating the defining instruction), there is no need to clear
116 * any other instr labels. */
117 if (new_label
& instr_labels
)
118 label
&= ~temp_labels
; /* instr and temp alias */
120 if (new_label
& temp_labels
) {
121 label
&= ~temp_labels
;
122 label
&= ~instr_labels
; /* instr and temp alias */
125 if (new_label
& val_labels
)
126 label
&= ~val_labels
;
131 void set_vec(Instruction
* vec
)
133 add_label(label_vec
);
139 return label
& label_vec
;
142 void set_constant(uint32_t constant
)
144 add_label(label_constant
);
150 return label
& label_constant
;
153 void set_constant_64bit(uint32_t constant
)
155 add_label(label_constant_64bit
);
159 bool is_constant_64bit()
161 return label
& label_constant_64bit
;
164 void set_abs(Temp abs_temp
)
166 add_label(label_abs
);
172 return label
& label_abs
;
175 void set_neg(Temp neg_temp
)
177 add_label(label_neg
);
183 return label
& label_neg
;
186 void set_neg_abs(Temp neg_abs_temp
)
188 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
192 void set_mul(Instruction
* mul
)
194 add_label(label_mul
);
200 return label
& label_mul
;
203 void set_temp(Temp tmp
)
205 add_label(label_temp
);
211 return label
& label_temp
;
214 void set_literal(uint32_t lit
)
216 add_label(label_literal
);
222 return label
& label_literal
;
225 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
227 add_label(label_mad
);
234 return label
& label_mad
;
237 void set_omod2(Temp def
)
239 add_label(label_omod2
);
245 return label
& label_omod2
;
248 void set_omod4(Temp def
)
250 add_label(label_omod4
);
256 return label
& label_omod4
;
259 void set_omod5(Temp def
)
261 add_label(label_omod5
);
267 return label
& label_omod5
;
270 void set_omod_success(Instruction
* omod_instr
)
272 add_label(label_omod_success
);
276 bool is_omod_success()
278 return label
& label_omod_success
;
281 void set_clamp(Temp def
)
283 add_label(label_clamp
);
289 return label
& label_clamp
;
292 void set_clamp_success(Instruction
* clamp_instr
)
294 add_label(label_clamp_success
);
298 bool is_clamp_success()
300 return label
& label_clamp_success
;
305 add_label(label_undefined
);
310 return label
& label_undefined
;
313 void set_vcc(Temp vcc
)
315 add_label(label_vcc
);
321 return label
& label_vcc
;
324 bool is_constant_or_literal()
326 return is_constant() || is_literal();
329 void set_b2f(Temp val
)
331 add_label(label_b2f
);
337 return label
& label_b2f
;
340 void set_add_sub(Instruction
*add_sub_instr
)
342 add_label(label_add_sub
);
343 instr
= add_sub_instr
;
348 return label
& label_add_sub
;
351 void set_bitwise(Instruction
*bitwise_instr
)
353 add_label(label_bitwise
);
354 instr
= bitwise_instr
;
359 return label
& label_bitwise
;
362 void set_uniform_bitwise()
364 add_label(label_uniform_bitwise
);
367 bool is_uniform_bitwise()
369 return label
& label_uniform_bitwise
;
372 void set_minmax(Instruction
*minmax_instr
)
374 add_label(label_minmax
);
375 instr
= minmax_instr
;
380 return label
& label_minmax
;
383 void set_fcmp(Instruction
*fcmp_instr
)
385 add_label(label_fcmp
);
391 return label
& label_fcmp
;
394 void set_scc_needed()
396 add_label(label_scc_needed
);
401 return label
& label_scc_needed
;
404 void set_scc_invert(Temp scc_inv
)
406 add_label(label_scc_invert
);
412 return label
& label_scc_invert
;
415 void set_uniform_bool(Temp uniform_bool
)
417 add_label(label_uniform_bool
);
421 bool is_uniform_bool()
423 return label
& label_uniform_bool
;
428 add_label(label_vcc_hint
);
433 return label
& label_vcc_hint
;
436 void set_b2i(Temp val
)
438 add_label(label_b2i
);
444 return label
& label_b2i
;
451 std::vector
<aco_ptr
<Instruction
>> instructions
;
453 std::pair
<uint32_t,Temp
> last_literal
;
454 std::vector
<mad_info
> mad_infos
;
455 std::vector
<uint16_t> uses
;
458 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
460 if (instr
->operands
[0].isConstant() ||
461 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
464 switch (instr
->opcode
) {
465 case aco_opcode::v_add_f32
:
466 case aco_opcode::v_mul_f32
:
467 case aco_opcode::v_or_b32
:
468 case aco_opcode::v_and_b32
:
469 case aco_opcode::v_xor_b32
:
470 case aco_opcode::v_max_f32
:
471 case aco_opcode::v_min_f32
:
472 case aco_opcode::v_max_i32
:
473 case aco_opcode::v_min_i32
:
474 case aco_opcode::v_max_u32
:
475 case aco_opcode::v_min_u32
:
476 case aco_opcode::v_cmp_eq_f32
:
477 case aco_opcode::v_cmp_lg_f32
:
479 case aco_opcode::v_sub_f32
:
480 instr
->opcode
= aco_opcode::v_subrev_f32
;
482 case aco_opcode::v_cmp_lt_f32
:
483 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
485 case aco_opcode::v_cmp_ge_f32
:
486 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
488 case aco_opcode::v_cmp_lt_i32
:
489 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
496 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
501 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
504 if (instr
->isDPP() || instr
->isSDWA())
507 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
508 instr
->opcode
!= aco_opcode::v_madak_f32
&&
509 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
510 instr
->opcode
!= aco_opcode::v_madak_f16
&&
511 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
512 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
513 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
514 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
515 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
516 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
517 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
520 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
522 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
523 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
524 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
525 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
526 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
529 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
534 aco_ptr
<Instruction
> tmp
= std::move(instr
);
535 Format format
= asVOP3(tmp
->format
);
536 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
537 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
538 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
539 instr
->definitions
[i
] = tmp
->definitions
[i
];
540 if (instr
->definitions
[i
].isTemp()) {
541 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
542 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
543 info
.instr
= instr
.get();
548 /* only covers special cases */
549 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
552 case aco_opcode::v_interp_p2_f32
:
553 case aco_opcode::v_mac_f32
:
554 case aco_opcode::v_writelane_b32
:
555 case aco_opcode::v_writelane_b32_e64
:
556 case aco_opcode::v_cndmask_b32
:
558 case aco_opcode::s_addk_i32
:
559 case aco_opcode::s_mulk_i32
:
560 case aco_opcode::p_wqm
:
561 case aco_opcode::p_extract_vector
:
562 case aco_opcode::p_split_vector
:
563 case aco_opcode::v_readlane_b32
:
564 case aco_opcode::v_readlane_b32_e64
:
565 case aco_opcode::v_readfirstlane_b32
:
572 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
574 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
575 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
580 /* check constant bus and literal limitations */
581 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
583 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
584 Operand
literal32(s1
);
585 Operand
literal64(s2
);
586 unsigned num_sgprs
= 0;
587 unsigned sgpr
[] = {0, 0};
589 for (unsigned i
= 0; i
< num_operands
; i
++) {
590 Operand op
= operands
[i
];
592 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
593 /* two reads of the same SGPR count as 1 to the limit */
594 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
596 sgpr
[num_sgprs
++] = op
.tempId();
601 } else if (op
.isLiteral()) {
602 if (ctx
.program
->chip_class
< GFX10
)
605 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
607 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
610 /* Any number of 32-bit literals counts as only 1 to the limit. Same
611 * (but separately) for 64-bit literals. */
612 if (op
.size() == 1 && literal32
.isUndefined()) {
615 } else if (op
.size() == 2 && literal64
.isUndefined()) {
628 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
630 Operand op
= instr
->operands
[op_index
];
634 Temp tmp
= op
.getTemp();
635 if (!ctx
.info
[tmp
.id()].is_add_sub())
638 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
640 switch (add_instr
->opcode
) {
641 case aco_opcode::v_add_u32
:
642 case aco_opcode::v_add_co_u32
:
643 case aco_opcode::v_add_co_u32_e64
:
644 case aco_opcode::s_add_i32
:
645 case aco_opcode::s_add_u32
:
651 if (add_instr
->usesModifiers())
654 for (unsigned i
= 0; i
< 2; i
++) {
655 if (add_instr
->operands
[i
].isConstant()) {
656 *offset
= add_instr
->operands
[i
].constantValue();
657 } else if (add_instr
->operands
[i
].isTemp() &&
658 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
659 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
663 if (!add_instr
->operands
[!i
].isTemp())
666 uint32_t offset2
= 0;
667 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
670 *base
= add_instr
->operands
[!i
].getTemp();
678 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
680 if (instr
->format
== Format::PSEUDO
)
681 return instr
->operands
[index
].bytes() * 8u;
682 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
683 return index
== 2 ? 64 : 32;
684 else if (instr
->isVALU() || instr
->isSALU())
685 return instr_info
.operand_size
[(int)instr
->opcode
];
690 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
692 // TODO: this functions shouldn't be needed if we store Operand instead of value.
693 Operand
op(val
, is64bit
);
694 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
695 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
699 bool fixed_to_exec(Operand op
)
701 return op
.isFixed() && op
.physReg() == exec
;
704 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
706 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
707 ASSERTED
bool all_const
= false;
708 for (Operand
& op
: instr
->operands
)
709 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
710 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
713 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
715 if (!instr
->operands
[i
].isTemp())
718 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
719 /* propagate undef */
720 if (info
.is_undefined() && is_phi(instr
))
721 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
722 /* propagate reg->reg of same type */
723 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
724 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
725 info
= ctx
.info
[info
.temp
.id()];
728 /* SALU / PSEUDO: propagate inline constants */
729 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
730 const bool is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
731 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
732 // TODO: optimize SGPR and constant propagation for subdword pseudo instructions on gfx9+
736 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
737 instr
->operands
[i
].setTemp(info
.temp
);
738 info
= ctx
.info
[info
.temp
.id()];
739 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
740 /* propagate vgpr if it can take it */
741 switch (instr
->opcode
) {
742 case aco_opcode::p_create_vector
:
743 case aco_opcode::p_split_vector
:
744 case aco_opcode::p_extract_vector
:
745 case aco_opcode::p_phi
: {
746 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
747 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
749 instr
->operands
[i
] = Operand(info
.temp
);
750 info
= ctx
.info
[info
.temp
.id()];
758 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
759 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
760 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
765 /* VALU: propagate neg, abs & inline constants */
766 else if (instr
->isVALU()) {
767 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
768 instr
->operands
[i
].setTemp(info
.temp
);
769 info
= ctx
.info
[info
.temp
.id()];
772 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
773 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
774 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
776 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
779 instr
->operands
[i
] = Operand(info
.temp
);
781 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
783 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
785 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
786 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
787 instr
->operands
[i
].setTemp(info
.temp
);
789 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
790 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
791 instr
->operands
[i
].setTemp(info
.temp
);
793 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
796 instr
->operands
[i
].setTemp(info
.temp
);
798 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
800 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
803 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
804 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
805 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
806 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
807 instr
->operands
[i
] = op
;
809 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
810 instr
->operands
[i
] = instr
->operands
[0];
811 instr
->operands
[0] = op
;
813 } else if (can_use_VOP3(ctx
, instr
)) {
815 instr
->operands
[i
] = op
;
821 /* MUBUF: propagate constants and combine additions */
822 else if (instr
->format
== Format::MUBUF
) {
823 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
826 while (info
.is_temp())
827 info
= ctx
.info
[info
.temp
.id()];
829 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
830 assert(!mubuf
->idxen
);
831 instr
->operands
[1] = Operand(v1
);
832 mubuf
->offset
+= info
.val
;
833 mubuf
->offen
= false;
835 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
836 instr
->operands
[2] = Operand((uint32_t) 0);
837 mubuf
->offset
+= info
.val
;
839 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
840 assert(!mubuf
->idxen
);
841 instr
->operands
[1].setTemp(base
);
842 mubuf
->offset
+= offset
;
844 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
845 instr
->operands
[i
].setTemp(base
);
846 mubuf
->offset
+= offset
;
851 /* DS: combine additions */
852 else if (instr
->format
== Format::DS
) {
854 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
857 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
858 if (has_usable_ds_offset
&&
859 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
860 base
.regClass() == instr
->operands
[i
].regClass() &&
861 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
862 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
863 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
864 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
865 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
867 if ((offset
& mask
) == 0 &&
868 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
869 ds
->offset1
+ (offset
>> shifts
) <= 255) {
870 instr
->operands
[i
].setTemp(base
);
871 ds
->offset0
+= offset
>> shifts
;
872 ds
->offset1
+= offset
>> shifts
;
875 if (ds
->offset0
+ offset
<= 65535) {
876 instr
->operands
[i
].setTemp(base
);
877 ds
->offset0
+= offset
;
883 /* SMEM: propagate constants and combine additions */
884 else if (instr
->format
== Format::SMEM
) {
886 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
889 if (i
== 1 && info
.is_constant_or_literal() &&
890 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
891 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
892 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
893 instr
->operands
[i
] = Operand(info
.val
);
895 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
896 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
898 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
899 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
903 smem
->operands
[1] = Operand(offset
);
904 smem
->operands
.back() = Operand(base
);
906 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
907 new_instr
->operands
[0] = smem
->operands
[0];
908 new_instr
->operands
[1] = Operand(offset
);
909 if (smem
->definitions
.empty())
910 new_instr
->operands
[2] = smem
->operands
[2];
911 new_instr
->operands
.back() = Operand(base
);
912 if (!smem
->definitions
.empty())
913 new_instr
->definitions
[0] = smem
->definitions
[0];
914 new_instr
->can_reorder
= smem
->can_reorder
;
915 new_instr
->barrier
= smem
->barrier
;
916 new_instr
->glc
= smem
->glc
;
917 new_instr
->dlc
= smem
->dlc
;
918 new_instr
->nv
= smem
->nv
;
919 new_instr
->disable_wqm
= smem
->disable_wqm
;
920 instr
.reset(new_instr
);
921 smem
= static_cast<SMEM_instruction
*>(instr
.get());
927 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
928 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
929 /* Flip the branch instruction to get rid of the scc_invert instruction */
930 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
931 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
936 /* if this instruction doesn't define anything, return */
937 if (instr
->definitions
.empty())
940 switch (instr
->opcode
) {
941 case aco_opcode::p_create_vector
: {
942 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
943 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
945 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
949 unsigned num_ops
= instr
->operands
.size();
950 for (const Operand
& op
: instr
->operands
) {
951 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
952 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
954 if (num_ops
!= instr
->operands
.size()) {
955 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
956 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
957 instr
->definitions
[0] = old_vec
->definitions
[0];
959 for (Operand
& old_op
: old_vec
->operands
) {
960 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
961 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
962 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
963 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
964 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
965 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
966 instr
->operands
[k
++] = op
;
969 instr
->operands
[k
++] = old_op
;
972 assert(k
== num_ops
);
975 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
978 case aco_opcode::p_split_vector
: {
979 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
981 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
982 unsigned split_offset
= 0;
983 unsigned vec_offset
= 0;
984 unsigned vec_index
= 0;
985 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
986 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
987 vec_offset
+= vec
->operands
[vec_index
++].bytes();
989 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
992 Operand vec_op
= vec
->operands
[vec_index
];
993 if (vec_op
.isConstant()) {
994 if (vec_op
.isLiteral())
995 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
996 else if (vec_op
.size() == 1)
997 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
998 else if (vec_op
.size() == 2)
999 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
1000 } else if (vec_op
.isUndefined()) {
1001 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1003 assert(vec_op
.isTemp());
1004 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1009 case aco_opcode::p_extract_vector
: { /* mov */
1010 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
1013 /* check if we index directly into a vector element */
1014 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1015 const unsigned index
= instr
->operands
[1].constantValue();
1016 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1017 unsigned offset
= 0;
1019 for (const Operand
& op
: vec
->operands
) {
1020 if (offset
< dst_offset
) {
1021 offset
+= op
.bytes();
1023 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1027 /* convert this extract into a copy instruction */
1028 instr
->opcode
= aco_opcode::p_parallelcopy
;
1029 instr
->operands
.pop_back();
1030 instr
->operands
[0] = op
;
1032 if (op
.isConstant()) {
1034 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(op
.constantValue());
1035 else if (op
.size() == 1)
1036 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(op
.constantValue());
1037 else if (op
.size() == 2)
1038 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(op
.constantValue());
1039 } else if (op
.isUndefined()) {
1040 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1042 assert(op
.isTemp());
1043 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1049 case aco_opcode::s_mov_b32
: /* propagate */
1050 case aco_opcode::s_mov_b64
:
1051 case aco_opcode::v_mov_b32
:
1052 case aco_opcode::p_as_uniform
:
1053 if (instr
->definitions
[0].isFixed()) {
1054 /* don't copy-propagate copies into fixed registers */
1055 } else if (instr
->usesModifiers()) {
1057 } else if (instr
->operands
[0].isConstant()) {
1058 if (instr
->operands
[0].isLiteral())
1059 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
1060 else if (instr
->operands
[0].size() == 1)
1061 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
1062 else if (instr
->operands
[0].size() == 2)
1063 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
1064 } else if (instr
->operands
[0].isTemp()) {
1065 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1067 assert(instr
->operands
[0].isFixed());
1070 case aco_opcode::p_is_helper
:
1071 if (!ctx
.program
->needs_wqm
)
1072 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1074 case aco_opcode::s_movk_i32
: {
1075 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1076 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1077 if (v
<= 64 || v
>= 0xfffffff0)
1078 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1080 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1083 case aco_opcode::v_bfrev_b32
:
1084 case aco_opcode::s_brev_b32
: {
1085 if (instr
->operands
[0].isConstant()) {
1086 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1087 if (v
<= 64 || v
>= 0xfffffff0)
1088 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1090 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1094 case aco_opcode::s_bfm_b32
: {
1095 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1096 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1097 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1098 uint32_t v
= ((1u << size
) - 1u) << start
;
1099 if (v
<= 64 || v
>= 0xfffffff0)
1100 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1102 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1106 case aco_opcode::v_mul_f16
:
1107 case aco_opcode::v_mul_f32
: { /* omod */
1108 /* TODO: try to move the negate/abs modifier to the consumer instead */
1109 if (instr
->usesModifiers())
1112 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1114 for (unsigned i
= 0; i
< 2; i
++) {
1115 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1116 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1117 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1118 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1119 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1120 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1121 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1122 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1123 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1124 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1133 case aco_opcode::v_and_b32
: { /* abs */
1134 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1135 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1136 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1137 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1138 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1140 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1143 case aco_opcode::v_xor_b32
: { /* neg */
1144 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1145 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1146 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1147 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1148 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1149 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1150 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1151 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1152 instr
->opcode
= aco_opcode::v_or_b32
;
1153 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1155 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1159 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1163 case aco_opcode::v_med3_f16
:
1164 case aco_opcode::v_med3_f32
: { /* clamp */
1165 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1166 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1167 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1168 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1172 bool found_zero
= false, found_one
= false;
1173 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1174 for (unsigned i
= 0; i
< 3; i
++)
1176 if (instr
->operands
[i
].constantEquals(0))
1178 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1183 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1184 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1188 case aco_opcode::v_cndmask_b32
:
1189 if (instr
->operands
[0].constantEquals(0) &&
1190 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1191 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1192 else if (instr
->operands
[0].constantEquals(0) &&
1193 instr
->operands
[1].constantEquals(0x3f800000u
))
1194 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1195 else if (instr
->operands
[0].constantEquals(0) &&
1196 instr
->operands
[1].constantEquals(1))
1197 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1199 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1201 case aco_opcode::v_cmp_lg_u32
:
1202 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1203 instr
->operands
[0].constantEquals(0) &&
1204 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1205 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1207 case aco_opcode::p_phi
:
1208 case aco_opcode::p_linear_phi
: {
1209 /* lower_bool_phis() can create phis like this */
1210 bool all_same_temp
= instr
->operands
[0].isTemp();
1211 /* this check is needed when moving uniform loop counters out of a divergent loop */
1213 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1214 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1215 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1216 all_same_temp
= false;
1218 if (all_same_temp
) {
1219 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1221 bool all_undef
= instr
->operands
[0].isUndefined();
1222 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1223 if (!instr
->operands
[i
].isUndefined())
1227 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1231 case aco_opcode::v_add_u32
:
1232 case aco_opcode::v_add_co_u32
:
1233 case aco_opcode::v_add_co_u32_e64
:
1234 case aco_opcode::s_add_i32
:
1235 case aco_opcode::s_add_u32
:
1236 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1238 case aco_opcode::s_not_b32
:
1239 case aco_opcode::s_not_b64
:
1240 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1241 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1242 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1243 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1244 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1245 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1247 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1249 case aco_opcode::s_and_b32
:
1250 case aco_opcode::s_and_b64
:
1251 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1252 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1253 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1254 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1255 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1257 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1258 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1259 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1260 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1265 case aco_opcode::s_or_b32
:
1266 case aco_opcode::s_or_b64
:
1267 case aco_opcode::s_xor_b32
:
1268 case aco_opcode::s_xor_b64
:
1269 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1270 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1272 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1275 case aco_opcode::s_lshl_b32
:
1276 case aco_opcode::v_or_b32
:
1277 case aco_opcode::v_lshlrev_b32
:
1278 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1280 case aco_opcode::v_min_f32
:
1281 case aco_opcode::v_min_f16
:
1282 case aco_opcode::v_min_u32
:
1283 case aco_opcode::v_min_i32
:
1284 case aco_opcode::v_min_u16
:
1285 case aco_opcode::v_min_i16
:
1286 case aco_opcode::v_max_f32
:
1287 case aco_opcode::v_max_f16
:
1288 case aco_opcode::v_max_u32
:
1289 case aco_opcode::v_max_i32
:
1290 case aco_opcode::v_max_u16
:
1291 case aco_opcode::v_max_i16
:
1292 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1294 case aco_opcode::v_cmp_lt_f32
:
1295 case aco_opcode::v_cmp_eq_f32
:
1296 case aco_opcode::v_cmp_le_f32
:
1297 case aco_opcode::v_cmp_gt_f32
:
1298 case aco_opcode::v_cmp_lg_f32
:
1299 case aco_opcode::v_cmp_ge_f32
:
1300 case aco_opcode::v_cmp_o_f32
:
1301 case aco_opcode::v_cmp_u_f32
:
1302 case aco_opcode::v_cmp_nge_f32
:
1303 case aco_opcode::v_cmp_nlg_f32
:
1304 case aco_opcode::v_cmp_ngt_f32
:
1305 case aco_opcode::v_cmp_nle_f32
:
1306 case aco_opcode::v_cmp_neq_f32
:
1307 case aco_opcode::v_cmp_nlt_f32
:
1308 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1310 case aco_opcode::s_cselect_b64
:
1311 case aco_opcode::s_cselect_b32
:
1312 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1313 instr
->operands
[1].constantEquals(0)) {
1314 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1315 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1317 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1318 /* Flip the operands to get rid of the scc_invert instruction */
1319 std::swap(instr
->operands
[0], instr
->operands
[1]);
1320 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1323 case aco_opcode::p_wqm
:
1324 if (instr
->operands
[0].isTemp() &&
1325 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1326 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1334 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1336 *ordered
= *unordered
= op
;
1338 #define CMP(ord, unord) \
1339 case aco_opcode::v_cmp_##ord##_f32:\
1340 case aco_opcode::v_cmp_n##unord##_f32:\
1341 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1342 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1343 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1357 aco_opcode
get_ordered(aco_opcode op
)
1359 aco_opcode ordered
, unordered
, inverse
;
1360 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::num_opcodes
;
1363 aco_opcode
get_unordered(aco_opcode op
)
1365 aco_opcode ordered
, unordered
, inverse
;
1366 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::num_opcodes
;
1369 aco_opcode
get_inverse(aco_opcode op
)
1371 aco_opcode ordered
, unordered
, inverse
;
1372 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::num_opcodes
;
1375 bool is_cmp(aco_opcode op
)
1377 aco_opcode ordered
, unordered
, inverse
;
1378 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1381 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1383 if (ctx
.info
[tmp
.id()].is_temp())
1384 return ctx
.info
[tmp
.id()].temp
.id();
1389 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1391 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1392 for (const Operand
& op
: instr
->operands
) {
1394 ctx
.uses
[op
.tempId()]--;
1399 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1401 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1403 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1406 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1408 if (instr
->definitions
.size() == 2) {
1409 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1410 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1417 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1418 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1419 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1421 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1423 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1426 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1428 bool neg
[2] = {false, false};
1429 bool abs
[2] = {false, false};
1431 Instruction
*op_instr
[2];
1434 for (unsigned i
= 0; i
< 2; i
++) {
1435 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1439 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1441 if (op_instr
[i
]->opcode
!= expected_cmp
)
1443 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1446 if (op_instr
[i
]->isVOP3()) {
1447 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1448 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1450 neg
[i
] = vop3
->neg
[0];
1451 abs
[i
] = vop3
->abs
[0];
1452 opsel
|= (vop3
->opsel
& 1) << i
;
1455 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1456 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1457 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1463 if (op
[1].type() == RegType::sgpr
)
1464 std::swap(op
[0], op
[1]);
1465 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1466 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1469 ctx
.uses
[op
[0].id()]++;
1470 ctx
.uses
[op
[1].id()]++;
1471 decrease_uses(ctx
, op_instr
[0]);
1472 decrease_uses(ctx
, op_instr
[1]);
1474 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1475 Instruction
*new_instr
;
1476 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1477 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1478 for (unsigned i
= 0; i
< 2; i
++) {
1479 vop3
->neg
[i
] = neg
[i
];
1480 vop3
->abs
[i
] = abs
[i
];
1482 vop3
->opsel
= opsel
;
1483 new_instr
= static_cast<Instruction
*>(vop3
);
1485 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1487 new_instr
->operands
[0] = Operand(op
[0]);
1488 new_instr
->operands
[1] = Operand(op
[1]);
1489 new_instr
->definitions
[0] = instr
->definitions
[0];
1491 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1492 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1494 instr
.reset(new_instr
);
1499 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1500 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1501 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1503 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1505 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1508 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1509 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1511 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1512 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1513 if (!nan_test
|| !cmp
)
1516 if (cmp
->opcode
== expected_nan_test
)
1517 std::swap(nan_test
, cmp
);
1518 else if (nan_test
->opcode
!= expected_nan_test
)
1521 if (!is_cmp(cmp
->opcode
))
1524 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1526 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1529 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1530 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1531 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1532 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1533 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1535 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1538 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1539 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1540 decrease_uses(ctx
, nan_test
);
1541 decrease_uses(ctx
, cmp
);
1543 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1544 Instruction
*new_instr
;
1545 if (cmp
->isVOP3()) {
1546 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1547 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1548 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1549 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1550 new_vop3
->clamp
= cmp_vop3
->clamp
;
1551 new_vop3
->omod
= cmp_vop3
->omod
;
1552 new_vop3
->opsel
= cmp_vop3
->opsel
;
1553 new_instr
= new_vop3
;
1555 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1557 new_instr
->operands
[0] = cmp
->operands
[0];
1558 new_instr
->operands
[1] = cmp
->operands
[1];
1559 new_instr
->definitions
[0] = instr
->definitions
[0];
1561 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1562 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1564 instr
.reset(new_instr
);
1569 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1570 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1571 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1573 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1575 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1578 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1580 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1581 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1583 if (!nan_test
|| !cmp
)
1586 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1587 if (cmp
->opcode
== expected_nan_test
)
1588 std::swap(nan_test
, cmp
);
1589 else if (nan_test
->opcode
!= expected_nan_test
)
1592 if (!is_cmp(cmp
->opcode
))
1595 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1597 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1600 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1601 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1602 if (prop_nan0
!= prop_nan1
)
1605 if (nan_test
->isVOP3()) {
1606 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1607 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1611 int constant_operand
= -1;
1612 for (unsigned i
= 0; i
< 2; i
++) {
1613 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1614 constant_operand
= !i
;
1618 if (constant_operand
== -1)
1622 if (cmp
->operands
[constant_operand
].isConstant()) {
1623 constant
= cmp
->operands
[constant_operand
].constantValue();
1624 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1625 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1626 unsigned id
= original_temp_id(ctx
, tmp
);
1627 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1629 constant
= ctx
.info
[id
].val
;
1635 memcpy(&constantf
, &constant
, 4);
1636 if (isnan(constantf
))
1639 if (cmp
->operands
[0].isTemp())
1640 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1641 if (cmp
->operands
[1].isTemp())
1642 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1643 decrease_uses(ctx
, nan_test
);
1644 decrease_uses(ctx
, cmp
);
1646 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1647 Instruction
*new_instr
;
1648 if (cmp
->isVOP3()) {
1649 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1650 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1651 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1652 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1653 new_vop3
->clamp
= cmp_vop3
->clamp
;
1654 new_vop3
->omod
= cmp_vop3
->omod
;
1655 new_vop3
->opsel
= cmp_vop3
->opsel
;
1656 new_instr
= new_vop3
;
1658 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1660 new_instr
->operands
[0] = cmp
->operands
[0];
1661 new_instr
->operands
[1] = cmp
->operands
[1];
1662 new_instr
->definitions
[0] = instr
->definitions
[0];
1664 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1665 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1667 instr
.reset(new_instr
);
1672 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1673 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1675 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1677 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1679 if (!instr
->operands
[0].isTemp())
1682 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1686 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1687 if (new_opcode
== aco_opcode::num_opcodes
)
1690 if (cmp
->operands
[0].isTemp())
1691 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1692 if (cmp
->operands
[1].isTemp())
1693 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1694 decrease_uses(ctx
, cmp
);
1696 Instruction
*new_instr
;
1697 if (cmp
->isVOP3()) {
1698 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1699 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1700 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1701 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1702 new_vop3
->clamp
= cmp_vop3
->clamp
;
1703 new_vop3
->omod
= cmp_vop3
->omod
;
1704 new_vop3
->opsel
= cmp_vop3
->opsel
;
1705 new_instr
= new_vop3
;
1707 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1709 new_instr
->operands
[0] = cmp
->operands
[0];
1710 new_instr
->operands
[1] = cmp
->operands
[1];
1711 new_instr
->definitions
[0] = instr
->definitions
[0];
1713 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1714 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1716 instr
.reset(new_instr
);
1721 /* op1(op2(1, 2), 0) if swap = false
1722 * op1(0, op2(1, 2)) if swap = true */
1723 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1724 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1725 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1726 bool *op1_clamp
, uint8_t *op1_omod
,
1727 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1730 if (op1_instr
->opcode
!= op1
)
1733 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1734 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1736 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1739 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1740 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1742 /* don't support inbetween clamp/omod */
1743 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1746 /* get operands and modifiers and check inbetween modifiers */
1747 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1748 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1751 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1752 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1756 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1757 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1760 if (inbetween_opsel
)
1761 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1762 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1766 shuffle
[shuffle_str
[0] - '0'] = 0;
1767 shuffle
[shuffle_str
[1] - '0'] = 1;
1768 shuffle
[shuffle_str
[2] - '0'] = 2;
1770 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1771 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1772 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1773 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1774 *opsel
|= 1 << shuffle
[0];
1776 for (unsigned i
= 0; i
< 2; i
++) {
1777 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1778 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1779 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1780 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1781 *opsel
|= 1 << shuffle
[i
+ 1];
1784 /* check operands */
1785 if (!check_vop3_operands(ctx
, 3, operands
))
1791 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1792 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1793 bool clamp
, unsigned omod
)
1795 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1796 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1797 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1798 new_instr
->clamp
= clamp
;
1799 new_instr
->omod
= omod
;
1800 new_instr
->opsel
= opsel
;
1801 new_instr
->operands
[0] = operands
[0];
1802 new_instr
->operands
[1] = operands
[1];
1803 new_instr
->operands
[2] = operands
[2];
1804 new_instr
->definitions
[0] = instr
->definitions
[0];
1805 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1807 instr
.reset(new_instr
);
1810 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1812 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1813 (label_omod_success
| label_clamp_success
);
1815 for (unsigned swap
= 0; swap
< 2; swap
++) {
1816 if (!((1 << swap
) & ops
))
1819 Operand operands
[3];
1820 bool neg
[3], abs
[3], clamp
;
1821 uint8_t opsel
= 0, omod
= 0;
1822 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1823 instr
.get(), swap
, shuffle
,
1824 operands
, neg
, abs
, &opsel
,
1825 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1826 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1827 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1828 if (omod_clamp
& label_omod_success
)
1829 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1830 if (omod_clamp
& label_clamp_success
)
1831 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1838 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1840 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1843 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1844 (label_omod_success
| label_clamp_success
);
1846 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1847 * max(-min(a, b), c) -> max3(-a, -b, c) */
1848 for (unsigned swap
= 0; swap
< 2; swap
++) {
1849 Operand operands
[3];
1850 bool neg
[3], abs
[3], clamp
;
1851 uint8_t opsel
= 0, omod
= 0;
1853 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1854 instr
.get(), swap
, "012",
1855 operands
, neg
, abs
, &opsel
,
1856 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1858 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1861 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1862 if (omod_clamp
& label_omod_success
)
1863 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1864 if (omod_clamp
& label_clamp_success
)
1865 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1872 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1873 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1874 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1875 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1876 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1877 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1878 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1881 if (!instr
->operands
[0].isTemp())
1883 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1886 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1889 switch (op2_instr
->opcode
) {
1890 case aco_opcode::s_and_b32
:
1891 case aco_opcode::s_or_b32
:
1892 case aco_opcode::s_xor_b32
:
1893 case aco_opcode::s_and_b64
:
1894 case aco_opcode::s_or_b64
:
1895 case aco_opcode::s_xor_b64
:
1901 /* create instruction */
1902 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1903 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1904 ctx
.uses
[instr
->operands
[0].tempId()]--;
1905 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1907 switch (op2_instr
->opcode
) {
1908 case aco_opcode::s_and_b32
:
1909 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1911 case aco_opcode::s_or_b32
:
1912 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1914 case aco_opcode::s_xor_b32
:
1915 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1917 case aco_opcode::s_and_b64
:
1918 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1920 case aco_opcode::s_or_b64
:
1921 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1923 case aco_opcode::s_xor_b64
:
1924 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1933 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1934 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1935 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1936 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1937 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1939 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1942 for (unsigned i
= 0; i
< 2; i
++) {
1943 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1944 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1946 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1949 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1950 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1953 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1954 instr
->operands
[0] = instr
->operands
[!i
];
1955 instr
->operands
[1] = op2_instr
->operands
[0];
1956 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1958 switch (instr
->opcode
) {
1959 case aco_opcode::s_and_b32
:
1960 instr
->opcode
= aco_opcode::s_andn2_b32
;
1962 case aco_opcode::s_or_b32
:
1963 instr
->opcode
= aco_opcode::s_orn2_b32
;
1965 case aco_opcode::s_and_b64
:
1966 instr
->opcode
= aco_opcode::s_andn2_b64
;
1968 case aco_opcode::s_or_b64
:
1969 instr
->opcode
= aco_opcode::s_orn2_b64
;
1980 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1981 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1983 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1986 for (unsigned i
= 0; i
< 2; i
++) {
1987 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1988 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1989 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1991 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1994 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1995 if (shift
< 1 || shift
> 4)
1998 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1999 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2002 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2003 instr
->operands
[1] = instr
->operands
[!i
];
2004 instr
->operands
[0] = op2_instr
->operands
[0];
2005 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2007 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2008 aco_opcode::s_lshl2_add_u32
,
2009 aco_opcode::s_lshl3_add_u32
,
2010 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2017 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2019 if (instr
->usesModifiers())
2022 for (unsigned i
= 0; i
< 2; i
++) {
2023 if (!((1 << i
) & ops
))
2025 if (instr
->operands
[i
].isTemp() &&
2026 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2027 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2029 aco_ptr
<Instruction
> new_instr
;
2030 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2031 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2032 } else if (ctx
.program
->chip_class
>= GFX10
||
2033 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2034 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2038 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2039 new_instr
->definitions
[0] = instr
->definitions
[0];
2040 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2041 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2042 new_instr
->definitions
[1].setHint(vcc
);
2043 new_instr
->operands
[0] = Operand(0u);
2044 new_instr
->operands
[1] = instr
->operands
[!i
];
2045 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2046 instr
= std::move(new_instr
);
2047 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2055 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2058 #define MINMAX(type, gfx9) \
2059 case aco_opcode::v_min_##type:\
2060 case aco_opcode::v_max_##type:\
2061 case aco_opcode::v_med3_##type:\
2062 *min = aco_opcode::v_min_##type;\
2063 *max = aco_opcode::v_max_##type;\
2064 *med3 = aco_opcode::v_med3_##type;\
2065 *min3 = aco_opcode::v_min3_##type;\
2066 *max3 = aco_opcode::v_max3_##type;\
2067 *some_gfx9_only = gfx9;\
2081 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2082 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2083 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2084 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2086 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2087 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2088 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2089 aco_opcode other_op
;
2090 if (instr
->opcode
== min
)
2092 else if (instr
->opcode
== max
)
2097 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2098 (label_omod_success
| label_clamp_success
);
2100 for (unsigned swap
= 0; swap
< 2; swap
++) {
2101 Operand operands
[3];
2102 bool neg
[3], abs
[3], clamp
;
2103 uint8_t opsel
= 0, omod
= 0;
2104 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2105 "012", operands
, neg
, abs
, &opsel
,
2106 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2107 int const0_idx
= -1, const1_idx
= -1;
2108 uint32_t const0
= 0, const1
= 0;
2109 for (int i
= 0; i
< 3; i
++) {
2111 if (operands
[i
].isConstant()) {
2112 val
= operands
[i
].constantValue();
2113 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
2114 val
= ctx
.info
[operands
[i
].tempId()].val
;
2118 if (const0_idx
>= 0) {
2126 if (const0_idx
< 0 || const1_idx
< 0)
2129 if (opsel
& (1 << const0_idx
))
2131 if (opsel
& (1 << const1_idx
))
2134 int lower_idx
= const0_idx
;
2136 case aco_opcode::v_min_f32
:
2137 case aco_opcode::v_min_f16
: {
2138 float const0_f
, const1_f
;
2139 if (min
== aco_opcode::v_min_f32
) {
2140 memcpy(&const0_f
, &const0
, 4);
2141 memcpy(&const1_f
, &const1
, 4);
2143 const0_f
= _mesa_half_to_float(const0
);
2144 const1_f
= _mesa_half_to_float(const1
);
2146 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2147 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2148 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2149 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2150 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2153 case aco_opcode::v_min_u32
: {
2154 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2157 case aco_opcode::v_min_u16
: {
2158 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2161 case aco_opcode::v_min_i32
: {
2162 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2163 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2164 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2167 case aco_opcode::v_min_i16
: {
2168 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2169 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2170 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2176 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2178 if (instr
->opcode
== min
) {
2179 if (upper_idx
!= 0 || lower_idx
== 0)
2182 if (upper_idx
== 0 || lower_idx
!= 0)
2186 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2187 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2188 if (omod_clamp
& label_omod_success
)
2189 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2190 if (omod_clamp
& label_clamp_success
)
2191 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2201 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2203 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2204 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2205 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2207 /* find candidates and create the set of sgprs already read */
2208 unsigned sgpr_ids
[2] = {0, 0};
2209 uint32_t operand_mask
= 0;
2210 bool has_literal
= false;
2211 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2212 if (instr
->operands
[i
].isLiteral())
2214 if (!instr
->operands
[i
].isTemp())
2216 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2217 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2218 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2220 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2221 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2222 operand_mask
|= 1u << i
;
2224 unsigned max_sgprs
= 1;
2225 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2230 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2232 /* keep on applying sgprs until there is nothing left to be done */
2233 while (operand_mask
) {
2234 uint32_t sgpr_idx
= 0;
2235 uint32_t sgpr_info_id
= 0;
2236 uint32_t mask
= operand_mask
;
2239 unsigned i
= u_bit_scan(&mask
);
2240 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2241 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2243 sgpr_info_id
= instr
->operands
[i
].tempId();
2246 operand_mask
&= ~(1u << sgpr_idx
);
2248 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2249 * definitively beneficial.
2250 * TODO: this is too conservative because later the use count could be reduced to 1 */
2251 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2254 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2255 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2256 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2259 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2260 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2261 } else if (can_swap_operands(instr
)) {
2262 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2263 instr
->operands
[0] = Operand(sgpr
);
2264 /* swap bits using a 4-entry LUT */
2265 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2266 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2267 } else if (can_use_VOP3(ctx
, instr
)) {
2268 to_VOP3(ctx
, instr
);
2269 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2275 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2276 ctx
.uses
[sgpr_info_id
]--;
2277 ctx
.uses
[sgpr
.id()]++;
2281 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2283 /* check if we could apply omod on predecessor */
2284 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2285 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2286 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2288 unsigned idx
= op0
? 0 : 1;
2289 /* omod was successfully applied */
2290 /* if the omod instruction is v_mad, we also have to change the original add */
2291 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2292 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2293 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2294 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2295 add_instr
->definitions
[0] = instr
->definitions
[0];
2298 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2299 /* check if we have an additional clamp modifier */
2300 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2301 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2302 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2303 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2305 /* change definition ssa-id of modified instruction */
2306 omod_instr
->definitions
[0] = instr
->definitions
[0];
2308 /* change the definition of instr to something unused, e.g. the original omod def */
2309 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2310 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2313 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2314 /* in all other cases, label this instruction as option for multiply-add */
2315 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2319 /* check if we could apply clamp on predecessor */
2320 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2321 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2323 bool found_zero
= false, found_one
= false;
2324 for (unsigned i
= 0; i
< 3; i
++)
2326 if (instr
->operands
[i
].constantEquals(0))
2328 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2333 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2334 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2335 /* clamp was successfully applied */
2336 /* if the clamp instruction is v_mad, we also have to change the original add */
2337 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2338 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2339 add_instr
->definitions
[0] = instr
->definitions
[0];
2341 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2342 /* change definition ssa-id of modified instruction */
2343 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2345 /* change the definition of instr to something unused, e.g. the original omod def */
2346 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2347 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2352 /* omod has no effect if denormals are enabled */
2353 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2354 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2355 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2356 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2357 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2358 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2359 to_VOP3(ctx
, instr
);
2360 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2361 def_info
.set_omod_success(instr
.get());
2362 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2363 to_VOP3(ctx
, instr
);
2364 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2365 def_info
.set_omod_success(instr
.get());
2366 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2367 to_VOP3(ctx
, instr
);
2368 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2369 def_info
.set_omod_success(instr
.get());
2370 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2371 to_VOP3(ctx
, instr
);
2372 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2373 def_info
.set_clamp_success(instr
.get());
2380 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2381 // this would mean that we'd have to fix the instruction uses while value propagation
2383 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2385 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2388 if (instr
->isVALU()) {
2389 if (can_apply_sgprs(instr
))
2390 apply_sgprs(ctx
, instr
);
2391 if (apply_omod_clamp(ctx
, block
, instr
))
2395 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2396 instr
->definitions
[0].setHint(vcc
);
2399 /* TODO: There are still some peephole optimizations that could be done:
2400 * - abs(a - b) -> s_absdiff_i32
2401 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2402 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2403 * These aren't probably too interesting though.
2404 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2405 * probably more useful than the previously mentioned optimizations.
2406 * The various comparison optimizations also currently only work with 32-bit
2409 /* neg(mul(a, b)) -> mul(neg(a), b) */
2410 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2411 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2413 if (!ctx
.info
[val
.id()].is_mul())
2416 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2418 if (mul_instr
->operands
[0].isLiteral())
2420 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2423 /* convert to mul(neg(a), b) */
2424 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2425 Definition def
= instr
->definitions
[0];
2426 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2427 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2428 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2429 instr
->operands
[0] = mul_instr
->operands
[0];
2430 instr
->operands
[1] = mul_instr
->operands
[1];
2431 instr
->definitions
[0] = def
;
2432 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2433 if (mul_instr
->isVOP3()) {
2434 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2435 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2436 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2437 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2438 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2439 new_mul
->omod
= mul
->omod
;
2441 new_mul
->neg
[0] ^= true;
2442 new_mul
->clamp
= false;
2444 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2448 /* combine mul+add -> mad */
2449 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2450 instr
->opcode
== aco_opcode::v_sub_f32
||
2451 instr
->opcode
== aco_opcode::v_subrev_f32
;
2452 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2453 instr
->opcode
== aco_opcode::v_sub_f16
||
2454 instr
->opcode
== aco_opcode::v_subrev_f16
;
2455 if (mad16
|| mad32
) {
2456 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2457 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2458 if (need_fma
&& instr
->definitions
[0].isPrecise())
2460 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2463 uint32_t uses_src0
= UINT32_MAX
;
2464 uint32_t uses_src1
= UINT32_MAX
;
2465 Instruction
* mul_instr
= nullptr;
2466 unsigned add_op_idx
;
2467 /* check if any of the operands is a multiplication */
2468 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2469 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2470 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2471 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2472 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2473 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2475 /* find the 'best' mul instruction to combine with the add */
2476 if (uses_src0
< uses_src1
) {
2477 mul_instr
= op0_info
->instr
;
2479 } else if (uses_src1
< uses_src0
) {
2480 mul_instr
= op1_info
->instr
;
2482 } else if (uses_src0
!= UINT32_MAX
) {
2483 /* tiebreaker: quite random what to pick */
2484 if (op0_info
->instr
->operands
[0].isLiteral()) {
2485 mul_instr
= op1_info
->instr
;
2488 mul_instr
= op0_info
->instr
;
2493 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2494 bool neg
[3] = {false, false, false};
2495 bool abs
[3] = {false, false, false};
2498 op
[0] = mul_instr
->operands
[0];
2499 op
[1] = mul_instr
->operands
[1];
2500 op
[2] = instr
->operands
[add_op_idx
];
2501 // TODO: would be better to check this before selecting a mul instr?
2502 if (!check_vop3_operands(ctx
, 3, op
))
2505 if (mul_instr
->isVOP3()) {
2506 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2507 neg
[0] = vop3
->neg
[0];
2508 neg
[1] = vop3
->neg
[1];
2509 abs
[0] = vop3
->abs
[0];
2510 abs
[1] = vop3
->abs
[1];
2511 /* we cannot use these modifiers between mul and add */
2512 if (vop3
->clamp
|| vop3
->omod
)
2516 /* convert to mad */
2517 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2518 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2520 ctx
.uses
[op
[0].tempId()]++;
2522 ctx
.uses
[op
[1].tempId()]++;
2525 if (instr
->isVOP3()) {
2526 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2527 neg
[2] = vop3
->neg
[add_op_idx
];
2528 abs
[2] = vop3
->abs
[add_op_idx
];
2530 clamp
= vop3
->clamp
;
2531 /* abs of the multiplication result */
2532 if (vop3
->abs
[1 - add_op_idx
]) {
2538 /* neg of the multiplication result */
2539 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2541 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2542 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2543 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2544 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2546 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2548 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2549 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2551 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2552 for (unsigned i
= 0; i
< 3; i
++)
2554 mad
->operands
[i
] = op
[i
];
2555 mad
->neg
[i
] = neg
[i
];
2556 mad
->abs
[i
] = abs
[i
];
2560 mad
->definitions
[0] = instr
->definitions
[0];
2562 /* mark this ssa_def to be re-checked for profitability and literals */
2563 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2564 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2565 instr
.reset(mad
.release());
2569 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2570 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2571 for (unsigned i
= 0; i
< 2; i
++) {
2572 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2573 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2574 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2575 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2576 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2578 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2579 new_instr
->operands
[0] = Operand(0u);
2580 new_instr
->operands
[1] = instr
->operands
[!i
];
2581 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2582 new_instr
->definitions
[0] = instr
->definitions
[0];
2583 instr
.reset(new_instr
.release());
2584 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2588 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2589 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2590 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2591 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2592 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2593 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2594 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2595 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2596 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2597 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2598 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2599 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2600 else if (ctx
.program
->chip_class
>= GFX9
) {
2601 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2602 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2603 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2604 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2605 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2606 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2607 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2609 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2610 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2611 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2612 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2613 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2614 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2615 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2616 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2617 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2618 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2619 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2620 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2621 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2622 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2623 combine_salu_lshl_add(ctx
, instr
);
2624 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2625 combine_salu_not_bitwise(ctx
, instr
);
2626 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2627 if (combine_inverse_comparison(ctx
, instr
)) ;
2628 else combine_salu_not_bitwise(ctx
, instr
);
2629 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2630 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2631 if (combine_ordering_test(ctx
, instr
)) ;
2632 else if (combine_comparison_ordering(ctx
, instr
)) ;
2633 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2634 else combine_salu_n2(ctx
, instr
);
2636 aco_opcode min
, max
, min3
, max3
, med3
;
2637 bool some_gfx9_only
;
2638 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2639 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2640 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2641 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2646 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2648 switch (instr
->opcode
) {
2649 case aco_opcode::s_and_b32
:
2650 case aco_opcode::s_and_b64
:
2651 instr
->opcode
= aco_opcode::s_and_b32
;
2653 case aco_opcode::s_or_b32
:
2654 case aco_opcode::s_or_b64
:
2655 instr
->opcode
= aco_opcode::s_or_b32
;
2657 case aco_opcode::s_xor_b32
:
2658 case aco_opcode::s_xor_b64
:
2659 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2662 /* Don't transform other instructions. They are very unlikely to appear here. */
2666 for (Operand
&op
: instr
->operands
) {
2667 ctx
.uses
[op
.tempId()]--;
2669 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2670 /* Just use the uniform boolean temp. */
2671 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2672 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2673 /* Use the SCC definition of the predecessor instruction.
2674 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2675 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2677 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2678 assert(pred_instr
->definitions
.size() >= 2);
2679 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2680 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2682 unreachable("Invalid operand on uniform bitwise instruction.");
2685 ctx
.uses
[op
.tempId()]++;
2688 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2689 assert(instr
->operands
[0].regClass() == s1
);
2690 assert(instr
->operands
[1].regClass() == s1
);
2694 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2696 const uint32_t threshold
= 4;
2698 if (is_dead(ctx
.uses
, instr
.get())) {
2703 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2704 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2705 unsigned num_used
= 0;
2707 unsigned split_offset
= 0;
2708 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2709 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2712 split_offset
= offset
;
2716 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2717 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2718 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2722 for (Operand
& vec_op
: vec
->operands
) {
2723 if (off
== split_offset
) {
2727 off
+= vec_op
.bytes();
2729 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2730 ctx
.uses
[instr
->operands
[0].tempId()]--;
2731 for (Operand
& vec_op
: vec
->operands
) {
2732 if (vec_op
.isTemp())
2733 ctx
.uses
[vec_op
.tempId()]--;
2736 ctx
.uses
[op
.tempId()]++;
2738 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2739 extract
->operands
[0] = op
;
2740 extract
->definitions
[0] = instr
->definitions
[idx
];
2741 instr
.reset(extract
.release());
2747 if (!done
&& num_used
== 1 &&
2748 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2749 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2750 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2751 extract
->operands
[0] = instr
->operands
[0];
2752 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2753 extract
->definitions
[0] = instr
->definitions
[idx
];
2754 instr
.reset(extract
.release());
2758 mad_info
* mad_info
= NULL
;
2759 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2760 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2761 /* re-check mad instructions */
2762 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2763 ctx
.uses
[mad_info
->mul_temp_id
]++;
2764 if (instr
->operands
[0].isTemp())
2765 ctx
.uses
[instr
->operands
[0].tempId()]--;
2766 if (instr
->operands
[1].isTemp())
2767 ctx
.uses
[instr
->operands
[1].tempId()]--;
2768 instr
.swap(mad_info
->add_instr
);
2771 /* check literals */
2772 else if (!instr
->usesModifiers()) {
2773 /* FMA can only take literals on GFX10+ */
2774 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2775 ctx
.program
->chip_class
< GFX10
)
2778 bool sgpr_used
= false;
2779 uint32_t literal_idx
= 0;
2780 uint32_t literal_uses
= UINT32_MAX
;
2781 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2783 if (instr
->operands
[i
].isConstant() && i
> 0) {
2784 literal_uses
= UINT32_MAX
;
2787 if (!instr
->operands
[i
].isTemp())
2789 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2790 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2791 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2792 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2795 literal_uses
= UINT32_MAX
;
2798 /* don't break because we still need to check constants */
2799 } else if (!sgpr_used
&&
2800 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2801 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2802 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2807 /* Limit the number of literals to apply to not increase the code
2808 * size too much, but always apply literals for v_mad->v_madak
2809 * because both instructions are 64-bit and this doesn't increase
2811 * TODO: try to apply the literals earlier to lower the number of
2812 * uses below threshold
2814 if (literal_uses
< threshold
|| literal_idx
== 2) {
2815 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2816 mad_info
->check_literal
= true;
2817 mad_info
->literal_idx
= literal_idx
;
2823 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2824 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2825 instr
->operands
.size() &&
2826 instr
->operands
[0].isTemp()) {
2827 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2829 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2830 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2831 instr
->operands
[2].isTemp()) {
2832 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2835 /* check for literals */
2836 if (!instr
->isSALU() && !instr
->isVALU())
2839 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2840 if (instr
->definitions
.size() &&
2841 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2842 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2843 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2845 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2846 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2847 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2848 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2849 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2850 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2856 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2857 return; /* some encodings can't ever take literals */
2859 /* we do not apply the literals yet as we don't know if it is profitable */
2860 Operand
current_literal(s1
);
2862 unsigned literal_id
= 0;
2863 unsigned literal_uses
= UINT32_MAX
;
2864 Operand
literal(s1
);
2865 unsigned num_operands
= 1;
2866 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2867 num_operands
= instr
->operands
.size();
2868 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2869 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2872 unsigned sgpr_ids
[2] = {0, 0};
2873 bool is_literal_sgpr
= false;
2876 /* choose a literal to apply */
2877 for (unsigned i
= 0; i
< num_operands
; i
++) {
2878 Operand op
= instr
->operands
[i
];
2880 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2881 op
.tempId() != sgpr_ids
[0])
2882 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2884 if (op
.isLiteral()) {
2885 current_literal
= op
;
2887 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2891 if (!alu_can_accept_constant(instr
->opcode
, i
))
2894 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2895 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2897 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2898 literal_uses
= ctx
.uses
[op
.tempId()];
2899 literal_id
= op
.tempId();
2902 mask
|= (op
.tempId() == literal_id
) << i
;
2906 /* don't go over the constant bus limit */
2907 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2908 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2909 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2910 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2911 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2912 const_bus_limit
= 2;
2914 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2915 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2918 if (literal_id
&& literal_uses
< threshold
&&
2919 (current_literal
.isUndefined() ||
2920 (current_literal
.size() == literal
.size() &&
2921 current_literal
.constantValue() == literal
.constantValue()))) {
2922 /* mark the literal to be applied */
2924 unsigned i
= u_bit_scan(&mask
);
2925 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2926 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2932 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2934 /* Cleanup Dead Instructions */
2938 /* apply literals on MAD */
2939 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2940 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2941 if (info
->check_literal
&&
2942 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2943 aco_ptr
<Instruction
> new_mad
;
2945 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
2946 if (instr
->opcode
== aco_opcode::v_fma_f32
)
2947 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
2948 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
2949 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
2950 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
2951 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
2953 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
2954 if (info
->literal_idx
== 2) { /* add literal -> madak */
2955 new_mad
->operands
[0] = instr
->operands
[0];
2956 new_mad
->operands
[1] = instr
->operands
[1];
2957 } else { /* mul literal -> madmk */
2958 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2959 new_mad
->operands
[1] = instr
->operands
[2];
2961 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2962 new_mad
->definitions
[0] = instr
->definitions
[0];
2963 ctx
.instructions
.emplace_back(std::move(new_mad
));
2968 /* apply literals on other SALU/VALU */
2969 if (instr
->isSALU() || instr
->isVALU()) {
2970 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2971 Operand op
= instr
->operands
[i
];
2972 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2973 Operand
literal(ctx
.info
[op
.tempId()].val
);
2974 if (instr
->isVALU() && i
> 0)
2975 to_VOP3(ctx
, instr
);
2976 instr
->operands
[i
] = literal
;
2981 ctx
.instructions
.emplace_back(std::move(instr
));
2985 void optimize(Program
* program
)
2988 ctx
.program
= program
;
2989 std::vector
<ssa_info
> info(program
->peekAllocationId());
2990 ctx
.info
= info
.data();
2992 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2993 for (Block
& block
: program
->blocks
) {
2994 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2995 label_instruction(ctx
, block
, instr
);
2998 ctx
.uses
= dead_code_analysis(program
);
3000 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3001 for (Block
& block
: program
->blocks
) {
3002 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3003 combine_instruction(ctx
, block
, instr
);
3006 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3007 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3008 Block
* block
= &(*it
);
3009 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3010 select_instruction(ctx
, *it
);
3013 /* 4. Add literals to instructions */
3014 for (Block
& block
: program
->blocks
) {
3015 ctx
.instructions
.clear();
3016 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3017 apply_literals(ctx
, instr
);
3018 block
.instructions
.swap(ctx
.instructions
);