2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant
= 1 << 1,
69 label_literal
= 1 << 6,
73 label_omod5
= 1 << 10,
74 label_omod_success
= 1 << 11,
75 label_clamp
= 1 << 12,
76 label_clamp_success
= 1 << 13,
77 label_undefined
= 1 << 14,
80 label_add_sub
= 1 << 17,
81 label_bitwise
= 1 << 18,
82 label_minmax
= 1 << 19,
84 label_uniform_bool
= 1 << 21,
85 label_constant_64bit
= 1 << 22,
86 label_uniform_bitwise
= 1 << 23,
87 label_scc_invert
= 1 << 24,
88 label_vcc_hint
= 1 << 25,
89 label_scc_needed
= 1 << 26,
92 static constexpr uint32_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
93 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_fcmp
;
94 static constexpr uint32_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
95 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
;
96 static constexpr uint32_t val_labels
= label_constant
| label_constant_64bit
| label_literal
| label_mad
;
106 ssa_info() : label(0) {}
108 void add_label(Label new_label
)
110 /* Since all labels which use "instr" use it for the same thing
111 * (indicating the defining instruction), there is no need to clear
112 * any other instr labels. */
113 if (new_label
& instr_labels
)
114 label
&= ~temp_labels
; /* instr and temp alias */
116 if (new_label
& temp_labels
) {
117 label
&= ~temp_labels
;
118 label
&= ~instr_labels
; /* instr and temp alias */
121 if (new_label
& val_labels
)
122 label
&= ~val_labels
;
127 void set_vec(Instruction
* vec
)
129 add_label(label_vec
);
135 return label
& label_vec
;
138 void set_constant(uint32_t constant
)
140 add_label(label_constant
);
146 return label
& label_constant
;
149 void set_constant_64bit(uint32_t constant
)
151 add_label(label_constant_64bit
);
155 bool is_constant_64bit()
157 return label
& label_constant_64bit
;
160 void set_abs(Temp abs_temp
)
162 add_label(label_abs
);
168 return label
& label_abs
;
171 void set_neg(Temp neg_temp
)
173 add_label(label_neg
);
179 return label
& label_neg
;
182 void set_neg_abs(Temp neg_abs_temp
)
184 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
188 void set_mul(Instruction
* mul
)
190 add_label(label_mul
);
196 return label
& label_mul
;
199 void set_temp(Temp tmp
)
201 add_label(label_temp
);
207 return label
& label_temp
;
210 void set_literal(uint32_t lit
)
212 add_label(label_literal
);
218 return label
& label_literal
;
221 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
223 add_label(label_mad
);
230 return label
& label_mad
;
233 void set_omod2(Temp def
)
235 add_label(label_omod2
);
241 return label
& label_omod2
;
244 void set_omod4(Temp def
)
246 add_label(label_omod4
);
252 return label
& label_omod4
;
255 void set_omod5(Temp def
)
257 add_label(label_omod5
);
263 return label
& label_omod5
;
266 void set_omod_success(Instruction
* omod_instr
)
268 add_label(label_omod_success
);
272 bool is_omod_success()
274 return label
& label_omod_success
;
277 void set_clamp(Temp def
)
279 add_label(label_clamp
);
285 return label
& label_clamp
;
288 void set_clamp_success(Instruction
* clamp_instr
)
290 add_label(label_clamp_success
);
294 bool is_clamp_success()
296 return label
& label_clamp_success
;
301 add_label(label_undefined
);
306 return label
& label_undefined
;
309 void set_vcc(Temp vcc
)
311 add_label(label_vcc
);
317 return label
& label_vcc
;
320 bool is_constant_or_literal()
322 return is_constant() || is_literal();
325 void set_b2f(Temp val
)
327 add_label(label_b2f
);
333 return label
& label_b2f
;
336 void set_add_sub(Instruction
*add_sub_instr
)
338 add_label(label_add_sub
);
339 instr
= add_sub_instr
;
344 return label
& label_add_sub
;
347 void set_bitwise(Instruction
*bitwise_instr
)
349 add_label(label_bitwise
);
350 instr
= bitwise_instr
;
355 return label
& label_bitwise
;
358 void set_uniform_bitwise()
360 add_label(label_uniform_bitwise
);
363 bool is_uniform_bitwise()
365 return label
& label_uniform_bitwise
;
368 void set_minmax(Instruction
*minmax_instr
)
370 add_label(label_minmax
);
371 instr
= minmax_instr
;
376 return label
& label_minmax
;
379 void set_fcmp(Instruction
*fcmp_instr
)
381 add_label(label_fcmp
);
387 return label
& label_fcmp
;
390 void set_scc_needed()
392 add_label(label_scc_needed
);
397 return label
& label_scc_needed
;
400 void set_scc_invert(Temp scc_inv
)
402 add_label(label_scc_invert
);
408 return label
& label_scc_invert
;
411 void set_uniform_bool(Temp uniform_bool
)
413 add_label(label_uniform_bool
);
417 bool is_uniform_bool()
419 return label
& label_uniform_bool
;
424 add_label(label_vcc_hint
);
429 return label
& label_vcc_hint
;
435 std::vector
<aco_ptr
<Instruction
>> instructions
;
437 std::pair
<uint32_t,Temp
> last_literal
;
438 std::vector
<mad_info
> mad_infos
;
439 std::vector
<uint16_t> uses
;
442 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
444 if (instr
->operands
[0].isConstant() ||
445 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
448 switch (instr
->opcode
) {
449 case aco_opcode::v_add_f32
:
450 case aco_opcode::v_mul_f32
:
451 case aco_opcode::v_or_b32
:
452 case aco_opcode::v_and_b32
:
453 case aco_opcode::v_xor_b32
:
454 case aco_opcode::v_max_f32
:
455 case aco_opcode::v_min_f32
:
456 case aco_opcode::v_max_i32
:
457 case aco_opcode::v_min_i32
:
458 case aco_opcode::v_max_u32
:
459 case aco_opcode::v_min_u32
:
460 case aco_opcode::v_cmp_eq_f32
:
461 case aco_opcode::v_cmp_lg_f32
:
463 case aco_opcode::v_sub_f32
:
464 instr
->opcode
= aco_opcode::v_subrev_f32
;
466 case aco_opcode::v_cmp_lt_f32
:
467 instr
->opcode
= aco_opcode::v_cmp_gt_f32
;
469 case aco_opcode::v_cmp_ge_f32
:
470 instr
->opcode
= aco_opcode::v_cmp_le_f32
;
472 case aco_opcode::v_cmp_lt_i32
:
473 instr
->opcode
= aco_opcode::v_cmp_gt_i32
;
480 bool can_use_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
485 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
488 if (instr
->isDPP() || instr
->isSDWA())
491 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
492 instr
->opcode
!= aco_opcode::v_madak_f32
&&
493 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
494 instr
->opcode
!= aco_opcode::v_madak_f16
&&
495 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
496 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
497 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
498 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
499 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
500 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
501 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
504 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
506 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
507 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
508 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
509 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
510 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
513 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
518 aco_ptr
<Instruction
> tmp
= std::move(instr
);
519 Format format
= asVOP3(tmp
->format
);
520 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
521 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
522 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
523 instr
->definitions
[i
] = tmp
->definitions
[i
];
524 if (instr
->definitions
[i
].isTemp()) {
525 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
526 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
527 info
.instr
= instr
.get();
532 /* only covers special cases */
533 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
536 case aco_opcode::v_interp_p2_f32
:
537 case aco_opcode::v_mac_f32
:
538 case aco_opcode::v_writelane_b32
:
539 case aco_opcode::v_writelane_b32_e64
:
540 case aco_opcode::v_cndmask_b32
:
542 case aco_opcode::s_addk_i32
:
543 case aco_opcode::s_mulk_i32
:
544 case aco_opcode::p_wqm
:
545 case aco_opcode::p_extract_vector
:
546 case aco_opcode::p_split_vector
:
547 case aco_opcode::v_readlane_b32
:
548 case aco_opcode::v_readlane_b32_e64
:
549 case aco_opcode::v_readfirstlane_b32
:
556 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
558 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
559 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
564 /* check constant bus and literal limitations */
565 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
567 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
568 Operand
literal32(s1
);
569 Operand
literal64(s2
);
570 unsigned num_sgprs
= 0;
571 unsigned sgpr
[] = {0, 0};
573 for (unsigned i
= 0; i
< num_operands
; i
++) {
574 Operand op
= operands
[i
];
576 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
577 /* two reads of the same SGPR count as 1 to the limit */
578 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
580 sgpr
[num_sgprs
++] = op
.tempId();
585 } else if (op
.isLiteral()) {
586 if (ctx
.program
->chip_class
< GFX10
)
589 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
591 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
594 /* Any number of 32-bit literals counts as only 1 to the limit. Same
595 * (but separately) for 64-bit literals. */
596 if (op
.size() == 1 && literal32
.isUndefined()) {
599 } else if (op
.size() == 2 && literal64
.isUndefined()) {
612 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
614 Operand op
= instr
->operands
[op_index
];
618 Temp tmp
= op
.getTemp();
619 if (!ctx
.info
[tmp
.id()].is_add_sub())
622 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
624 switch (add_instr
->opcode
) {
625 case aco_opcode::v_add_u32
:
626 case aco_opcode::v_add_co_u32
:
627 case aco_opcode::v_add_co_u32_e64
:
628 case aco_opcode::s_add_i32
:
629 case aco_opcode::s_add_u32
:
635 if (add_instr
->usesModifiers())
638 for (unsigned i
= 0; i
< 2; i
++) {
639 if (add_instr
->operands
[i
].isConstant()) {
640 *offset
= add_instr
->operands
[i
].constantValue();
641 } else if (add_instr
->operands
[i
].isTemp() &&
642 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal()) {
643 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
647 if (!add_instr
->operands
[!i
].isTemp())
650 uint32_t offset2
= 0;
651 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
654 *base
= add_instr
->operands
[!i
].getTemp();
662 Operand
get_constant_op(opt_ctx
&ctx
, uint32_t val
, bool is64bit
= false)
664 // TODO: this functions shouldn't be needed if we store Operand instead of value.
665 Operand
op(val
, is64bit
);
666 if (val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
667 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
671 bool fixed_to_exec(Operand op
)
673 return op
.isFixed() && op
.physReg() == exec
;
676 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
678 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
679 ASSERTED
bool all_const
= false;
680 for (Operand
& op
: instr
->operands
)
681 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal());
682 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
685 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
687 if (!instr
->operands
[i
].isTemp())
690 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
691 /* propagate undef */
692 if (info
.is_undefined() && is_phi(instr
))
693 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
694 /* propagate reg->reg of same type */
695 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
696 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
697 info
= ctx
.info
[info
.temp
.id()];
700 /* SALU / PSEUDO: propagate inline constants */
701 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
702 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
703 const bool is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
704 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
705 if (instr
->isSALU() || !is_subdword
) {
706 instr
->operands
[i
].setTemp(info
.temp
);
707 info
= ctx
.info
[info
.temp
.id()];
709 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
710 /* propagate vgpr if it can take it */
711 switch (instr
->opcode
) {
712 case aco_opcode::p_create_vector
:
713 case aco_opcode::p_split_vector
:
714 case aco_opcode::p_extract_vector
:
715 case aco_opcode::p_phi
: {
716 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
717 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
719 instr
->operands
[i
] = Operand(info
.temp
);
720 info
= ctx
.info
[info
.temp
.id()];
728 if ((info
.is_constant() || info
.is_constant_64bit() || (info
.is_literal() && instr
->format
== Format::PSEUDO
)) &&
729 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
730 instr
->operands
[i
] = get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
735 /* VALU: propagate neg, abs & inline constants */
736 else if (instr
->isVALU()) {
737 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
738 instr
->operands
[i
].setTemp(info
.temp
);
739 info
= ctx
.info
[info
.temp
.id()];
741 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
744 instr
->operands
[i
] = Operand(info
.temp
);
746 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
748 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
750 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
751 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
752 instr
->operands
[i
].setTemp(info
.temp
);
754 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && instr_info
.can_use_input_modifiers
[(int)instr
->opcode
]) {
757 instr
->operands
[i
].setTemp(info
.temp
);
759 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
761 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
764 if ((info
.is_constant() || info
.is_constant_64bit()) && alu_can_accept_constant(instr
->opcode
, i
)) {
765 Operand op
= get_constant_op(ctx
, info
.val
, info
.is_constant_64bit());
766 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
767 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
768 instr
->operands
[i
] = op
;
770 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
771 instr
->operands
[i
] = instr
->operands
[0];
772 instr
->operands
[0] = op
;
774 } else if (can_use_VOP3(ctx
, instr
)) {
776 instr
->operands
[i
] = op
;
782 /* MUBUF: propagate constants and combine additions */
783 else if (instr
->format
== Format::MUBUF
) {
784 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
787 while (info
.is_temp())
788 info
= ctx
.info
[info
.temp
.id()];
790 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
791 assert(!mubuf
->idxen
);
792 instr
->operands
[1] = Operand(v1
);
793 mubuf
->offset
+= info
.val
;
794 mubuf
->offen
= false;
796 } else if (i
== 2 && info
.is_constant_or_literal() && mubuf
->offset
+ info
.val
< 4096) {
797 instr
->operands
[2] = Operand((uint32_t) 0);
798 mubuf
->offset
+= info
.val
;
800 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
801 assert(!mubuf
->idxen
);
802 instr
->operands
[1].setTemp(base
);
803 mubuf
->offset
+= offset
;
805 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
806 instr
->operands
[i
].setTemp(base
);
807 mubuf
->offset
+= offset
;
812 /* DS: combine additions */
813 else if (instr
->format
== Format::DS
) {
815 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
818 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
819 if (has_usable_ds_offset
&&
820 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
821 base
.regClass() == instr
->operands
[i
].regClass() &&
822 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
823 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
824 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
825 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
826 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
828 if ((offset
& mask
) == 0 &&
829 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
830 ds
->offset1
+ (offset
>> shifts
) <= 255) {
831 instr
->operands
[i
].setTemp(base
);
832 ds
->offset0
+= offset
>> shifts
;
833 ds
->offset1
+= offset
>> shifts
;
836 if (ds
->offset0
+ offset
<= 65535) {
837 instr
->operands
[i
].setTemp(base
);
838 ds
->offset0
+= offset
;
844 /* SMEM: propagate constants and combine additions */
845 else if (instr
->format
== Format::SMEM
) {
847 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
850 if (i
== 1 && info
.is_constant_or_literal() &&
851 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
852 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
853 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
854 instr
->operands
[i
] = Operand(info
.val
);
856 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
857 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
859 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal() ||
860 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
864 smem
->operands
[1] = Operand(offset
);
865 smem
->operands
.back() = Operand(base
);
867 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
868 new_instr
->operands
[0] = smem
->operands
[0];
869 new_instr
->operands
[1] = Operand(offset
);
870 if (smem
->definitions
.empty())
871 new_instr
->operands
[2] = smem
->operands
[2];
872 new_instr
->operands
.back() = Operand(base
);
873 if (!smem
->definitions
.empty())
874 new_instr
->definitions
[0] = smem
->definitions
[0];
875 new_instr
->can_reorder
= smem
->can_reorder
;
876 new_instr
->barrier
= smem
->barrier
;
877 instr
.reset(new_instr
);
878 smem
= static_cast<SMEM_instruction
*>(instr
.get());
884 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
885 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
886 /* Flip the branch instruction to get rid of the scc_invert instruction */
887 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
888 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
893 /* if this instruction doesn't define anything, return */
894 if (instr
->definitions
.empty())
897 switch (instr
->opcode
) {
898 case aco_opcode::p_create_vector
: {
899 unsigned num_ops
= instr
->operands
.size();
900 for (const Operand
& op
: instr
->operands
) {
901 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
902 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
904 if (num_ops
!= instr
->operands
.size()) {
905 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
906 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
907 instr
->definitions
[0] = old_vec
->definitions
[0];
909 for (Operand
& old_op
: old_vec
->operands
) {
910 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
911 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
912 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
913 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
914 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
915 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
916 instr
->operands
[k
++] = op
;
919 instr
->operands
[k
++] = old_op
;
922 assert(k
== num_ops
);
924 if (instr
->operands
.size() == 1 && instr
->operands
[0].isTemp())
925 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
926 else if (instr
->definitions
[0].getTemp().size() == instr
->operands
.size())
927 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
930 case aco_opcode::p_split_vector
: {
931 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
933 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
934 if (instr
->definitions
.size() != vec
->operands
.size())
936 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
937 Operand vec_op
= vec
->operands
[i
];
938 if (vec_op
.isConstant()) {
939 if (vec_op
.isLiteral())
940 ctx
.info
[instr
->definitions
[i
].tempId()].set_literal(vec_op
.constantValue());
941 else if (vec_op
.size() == 1)
942 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(vec_op
.constantValue());
943 else if (vec_op
.size() == 2)
944 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant_64bit(vec_op
.constantValue());
946 assert(vec_op
.isTemp());
947 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
952 case aco_opcode::p_extract_vector
: { /* mov */
953 if (!ctx
.info
[instr
->operands
[0].tempId()].is_vec())
955 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
956 if (vec
->definitions
[0].getTemp().size() == vec
->operands
.size() && /* TODO: what about 64bit or other combinations? */
957 vec
->operands
[0].size() == instr
->definitions
[0].size()) {
959 /* convert this extract into a mov instruction */
960 Operand vec_op
= vec
->operands
[instr
->operands
[1].constantValue()];
961 bool is_vgpr
= instr
->definitions
[0].getTemp().type() == RegType::vgpr
;
962 aco_opcode opcode
= is_vgpr
? aco_opcode::v_mov_b32
: aco_opcode::s_mov_b32
;
963 Format format
= is_vgpr
? Format::VOP1
: Format::SOP1
;
964 instr
->opcode
= opcode
;
965 instr
->format
= format
;
966 while (instr
->operands
.size() > 1)
967 instr
->operands
.pop_back();
968 instr
->operands
[0] = vec_op
;
970 if (vec_op
.isConstant()) {
971 if (vec_op
.isLiteral())
972 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(vec_op
.constantValue());
973 else if (vec_op
.size() == 1)
974 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(vec_op
.constantValue());
975 else if (vec_op
.size() == 2)
976 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(vec_op
.constantValue());
979 assert(vec_op
.isTemp());
980 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vec_op
.getTemp());
985 case aco_opcode::s_mov_b32
: /* propagate */
986 case aco_opcode::s_mov_b64
:
987 case aco_opcode::v_mov_b32
:
988 case aco_opcode::p_as_uniform
:
989 if (instr
->definitions
[0].isFixed()) {
990 /* don't copy-propagate copies into fixed registers */
991 } else if (instr
->usesModifiers()) {
993 } else if (instr
->operands
[0].isConstant()) {
994 if (instr
->operands
[0].isLiteral())
995 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(instr
->operands
[0].constantValue());
996 else if (instr
->operands
[0].size() == 1)
997 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(instr
->operands
[0].constantValue());
998 else if (instr
->operands
[0].size() == 2)
999 ctx
.info
[instr
->definitions
[0].tempId()].set_constant_64bit(instr
->operands
[0].constantValue());
1000 } else if (instr
->operands
[0].isTemp()) {
1001 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1003 assert(instr
->operands
[0].isFixed());
1006 case aco_opcode::p_is_helper
:
1007 if (!ctx
.program
->needs_wqm
)
1008 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(0u);
1010 case aco_opcode::s_movk_i32
: {
1011 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1012 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1013 if (v
<= 64 || v
>= 0xfffffff0)
1014 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1016 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1019 case aco_opcode::v_bfrev_b32
:
1020 case aco_opcode::s_brev_b32
: {
1021 if (instr
->operands
[0].isConstant()) {
1022 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1023 if (v
<= 64 || v
>= 0xfffffff0)
1024 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1026 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1030 case aco_opcode::s_bfm_b32
: {
1031 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1032 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1033 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1034 uint32_t v
= ((1u << size
) - 1u) << start
;
1035 if (v
<= 64 || v
>= 0xfffffff0)
1036 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(v
);
1038 ctx
.info
[instr
->definitions
[0].tempId()].set_literal(v
);
1041 case aco_opcode::v_mul_f32
: { /* omod */
1042 /* TODO: try to move the negate/abs modifier to the consumer instead */
1043 if (instr
->usesModifiers())
1046 for (unsigned i
= 0; i
< 2; i
++) {
1047 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1048 if (instr
->operands
[!i
].constantValue() == 0x40000000) { /* 2.0 */
1049 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1050 } else if (instr
->operands
[!i
].constantValue() == 0x40800000) { /* 4.0 */
1051 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1052 } else if (instr
->operands
[!i
].constantValue() == 0x3f000000) { /* 0.5 */
1053 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1054 } else if (instr
->operands
[!i
].constantValue() == 0x3f800000 &&
1055 !block
.fp_mode
.must_flush_denorms32
) { /* 1.0 */
1056 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1065 case aco_opcode::v_and_b32
: /* abs */
1066 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x7FFFFFFF) &&
1067 instr
->operands
[1].isTemp() && instr
->operands
[1].getTemp().type() == RegType::vgpr
)
1068 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1070 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1072 case aco_opcode::v_xor_b32
: { /* neg */
1073 if (!instr
->usesModifiers() && instr
->operands
[0].constantEquals(0x80000000u
) && instr
->operands
[1].isTemp()) {
1074 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1075 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1076 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1077 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1078 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1079 instr
->opcode
= aco_opcode::v_or_b32
;
1080 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1082 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1086 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1090 case aco_opcode::v_med3_f32
: { /* clamp */
1091 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1092 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1093 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1094 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1098 bool found_zero
= false, found_one
= false;
1099 for (unsigned i
= 0; i
< 3; i
++)
1101 if (instr
->operands
[i
].constantEquals(0))
1103 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
1108 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1109 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1113 case aco_opcode::v_cndmask_b32
:
1114 if (instr
->operands
[0].constantEquals(0) &&
1115 instr
->operands
[1].constantEquals(0xFFFFFFFF) &&
1116 instr
->operands
[2].isTemp())
1117 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1118 else if (instr
->operands
[0].constantEquals(0) &&
1119 instr
->operands
[1].constantEquals(0x3f800000u
) &&
1120 instr
->operands
[2].isTemp())
1121 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1123 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1125 case aco_opcode::v_cmp_lg_u32
:
1126 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1127 instr
->operands
[0].constantEquals(0) &&
1128 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1129 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1131 case aco_opcode::p_phi
:
1132 case aco_opcode::p_linear_phi
: {
1133 /* lower_bool_phis() can create phis like this */
1134 bool all_same_temp
= instr
->operands
[0].isTemp();
1135 /* this check is needed when moving uniform loop counters out of a divergent loop */
1137 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1138 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1139 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1140 all_same_temp
= false;
1142 if (all_same_temp
) {
1143 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1145 bool all_undef
= instr
->operands
[0].isUndefined();
1146 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1147 if (!instr
->operands
[i
].isUndefined())
1151 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1155 case aco_opcode::v_add_u32
:
1156 case aco_opcode::v_add_co_u32
:
1157 case aco_opcode::v_add_co_u32_e64
:
1158 case aco_opcode::s_add_i32
:
1159 case aco_opcode::s_add_u32
:
1160 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1162 case aco_opcode::s_not_b32
:
1163 case aco_opcode::s_not_b64
:
1164 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1165 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1166 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1167 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1168 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1169 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1171 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1173 case aco_opcode::s_and_b32
:
1174 case aco_opcode::s_and_b64
:
1175 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1176 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1177 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1178 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1179 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1181 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1182 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1183 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1184 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1189 case aco_opcode::s_or_b32
:
1190 case aco_opcode::s_or_b64
:
1191 case aco_opcode::s_xor_b32
:
1192 case aco_opcode::s_xor_b64
:
1193 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1194 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1196 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1199 case aco_opcode::s_lshl_b32
:
1200 case aco_opcode::v_or_b32
:
1201 case aco_opcode::v_lshlrev_b32
:
1202 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1204 case aco_opcode::v_min_f32
:
1205 case aco_opcode::v_min_f16
:
1206 case aco_opcode::v_min_u32
:
1207 case aco_opcode::v_min_i32
:
1208 case aco_opcode::v_min_u16
:
1209 case aco_opcode::v_min_i16
:
1210 case aco_opcode::v_max_f32
:
1211 case aco_opcode::v_max_f16
:
1212 case aco_opcode::v_max_u32
:
1213 case aco_opcode::v_max_i32
:
1214 case aco_opcode::v_max_u16
:
1215 case aco_opcode::v_max_i16
:
1216 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1218 case aco_opcode::v_cmp_lt_f32
:
1219 case aco_opcode::v_cmp_eq_f32
:
1220 case aco_opcode::v_cmp_le_f32
:
1221 case aco_opcode::v_cmp_gt_f32
:
1222 case aco_opcode::v_cmp_lg_f32
:
1223 case aco_opcode::v_cmp_ge_f32
:
1224 case aco_opcode::v_cmp_o_f32
:
1225 case aco_opcode::v_cmp_u_f32
:
1226 case aco_opcode::v_cmp_nge_f32
:
1227 case aco_opcode::v_cmp_nlg_f32
:
1228 case aco_opcode::v_cmp_ngt_f32
:
1229 case aco_opcode::v_cmp_nle_f32
:
1230 case aco_opcode::v_cmp_neq_f32
:
1231 case aco_opcode::v_cmp_nlt_f32
:
1232 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(instr
.get());
1234 case aco_opcode::s_cselect_b64
:
1235 case aco_opcode::s_cselect_b32
:
1236 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1237 instr
->operands
[1].constantEquals(0)) {
1238 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1239 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1241 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1242 /* Flip the operands to get rid of the scc_invert instruction */
1243 std::swap(instr
->operands
[0], instr
->operands
[1]);
1244 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1247 case aco_opcode::p_wqm
:
1248 if (instr
->operands
[0].isTemp() &&
1249 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1250 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1258 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, aco_opcode
*ordered
, aco_opcode
*unordered
, aco_opcode
*inverse
)
1260 *ordered
= *unordered
= op
;
1262 #define CMP(ord, unord) \
1263 case aco_opcode::v_cmp_##ord##_f32:\
1264 case aco_opcode::v_cmp_n##unord##_f32:\
1265 *ordered = aco_opcode::v_cmp_##ord##_f32;\
1266 *unordered = aco_opcode::v_cmp_n##unord##_f32;\
1267 *inverse = op == aco_opcode::v_cmp_n##unord##_f32 ? aco_opcode::v_cmp_##unord##_f32 : aco_opcode::v_cmp_n##ord##_f32;\
1281 aco_opcode
get_ordered(aco_opcode op
)
1283 aco_opcode ordered
, unordered
, inverse
;
1284 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? ordered
: aco_opcode::last_opcode
;
1287 aco_opcode
get_unordered(aco_opcode op
)
1289 aco_opcode ordered
, unordered
, inverse
;
1290 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? unordered
: aco_opcode::last_opcode
;
1293 aco_opcode
get_inverse(aco_opcode op
)
1295 aco_opcode ordered
, unordered
, inverse
;
1296 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
) ? inverse
: aco_opcode::last_opcode
;
1299 bool is_cmp(aco_opcode op
)
1301 aco_opcode ordered
, unordered
, inverse
;
1302 return get_cmp_info(op
, &ordered
, &unordered
, &inverse
);
1305 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1307 if (ctx
.info
[tmp
.id()].is_temp())
1308 return ctx
.info
[tmp
.id()].temp
.id();
1313 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1315 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1316 for (const Operand
& op
: instr
->operands
) {
1318 ctx
.uses
[op
.tempId()]--;
1323 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1325 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1327 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1330 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1332 if (instr
->definitions
.size() == 2) {
1333 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1334 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1341 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1342 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1343 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1345 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1347 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1350 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1352 bool neg
[2] = {false, false};
1353 bool abs
[2] = {false, false};
1355 Instruction
*op_instr
[2];
1358 for (unsigned i
= 0; i
< 2; i
++) {
1359 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1363 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1365 if (op_instr
[i
]->opcode
!= expected_cmp
)
1367 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1370 if (op_instr
[i
]->isVOP3()) {
1371 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1372 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1374 neg
[i
] = vop3
->neg
[0];
1375 abs
[i
] = vop3
->abs
[0];
1376 opsel
|= (vop3
->opsel
& 1) << i
;
1379 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1380 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1381 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1387 if (op
[1].type() == RegType::sgpr
)
1388 std::swap(op
[0], op
[1]);
1389 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1390 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1393 ctx
.uses
[op
[0].id()]++;
1394 ctx
.uses
[op
[1].id()]++;
1395 decrease_uses(ctx
, op_instr
[0]);
1396 decrease_uses(ctx
, op_instr
[1]);
1398 aco_opcode new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1399 Instruction
*new_instr
;
1400 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1401 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1402 for (unsigned i
= 0; i
< 2; i
++) {
1403 vop3
->neg
[i
] = neg
[i
];
1404 vop3
->abs
[i
] = abs
[i
];
1406 vop3
->opsel
= opsel
;
1407 new_instr
= static_cast<Instruction
*>(vop3
);
1409 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1411 new_instr
->operands
[0] = Operand(op
[0]);
1412 new_instr
->operands
[1] = Operand(op
[1]);
1413 new_instr
->definitions
[0] = instr
->definitions
[0];
1415 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1416 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1418 instr
.reset(new_instr
);
1423 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1424 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1425 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1427 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1429 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1432 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1433 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1435 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1436 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1437 if (!nan_test
|| !cmp
)
1440 if (cmp
->opcode
== expected_nan_test
)
1441 std::swap(nan_test
, cmp
);
1442 else if (nan_test
->opcode
!= expected_nan_test
)
1445 if (!is_cmp(cmp
->opcode
))
1448 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1450 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1453 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1454 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1455 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1456 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1457 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1459 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1462 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1463 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1464 decrease_uses(ctx
, nan_test
);
1465 decrease_uses(ctx
, cmp
);
1467 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1468 Instruction
*new_instr
;
1469 if (cmp
->isVOP3()) {
1470 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1471 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1472 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1473 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1474 new_vop3
->clamp
= cmp_vop3
->clamp
;
1475 new_vop3
->omod
= cmp_vop3
->omod
;
1476 new_vop3
->opsel
= cmp_vop3
->opsel
;
1477 new_instr
= new_vop3
;
1479 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1481 new_instr
->operands
[0] = cmp
->operands
[0];
1482 new_instr
->operands
[1] = cmp
->operands
[1];
1483 new_instr
->definitions
[0] = instr
->definitions
[0];
1485 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1486 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1488 instr
.reset(new_instr
);
1493 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1494 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1495 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1497 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1499 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1502 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1504 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1505 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1507 if (!nan_test
|| !cmp
)
1510 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1511 if (cmp
->opcode
== expected_nan_test
)
1512 std::swap(nan_test
, cmp
);
1513 else if (nan_test
->opcode
!= expected_nan_test
)
1516 if (!is_cmp(cmp
->opcode
))
1519 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1521 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1524 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1525 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1526 if (prop_nan0
!= prop_nan1
)
1529 if (nan_test
->isVOP3()) {
1530 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1531 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1535 int constant_operand
= -1;
1536 for (unsigned i
= 0; i
< 2; i
++) {
1537 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1538 constant_operand
= !i
;
1542 if (constant_operand
== -1)
1546 if (cmp
->operands
[constant_operand
].isConstant()) {
1547 constant
= cmp
->operands
[constant_operand
].constantValue();
1548 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1549 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1550 unsigned id
= original_temp_id(ctx
, tmp
);
1551 if (!ctx
.info
[id
].is_constant() && !ctx
.info
[id
].is_literal())
1553 constant
= ctx
.info
[id
].val
;
1559 memcpy(&constantf
, &constant
, 4);
1560 if (isnan(constantf
))
1563 if (cmp
->operands
[0].isTemp())
1564 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1565 if (cmp
->operands
[1].isTemp())
1566 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1567 decrease_uses(ctx
, nan_test
);
1568 decrease_uses(ctx
, cmp
);
1570 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1571 Instruction
*new_instr
;
1572 if (cmp
->isVOP3()) {
1573 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1574 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1575 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1576 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1577 new_vop3
->clamp
= cmp_vop3
->clamp
;
1578 new_vop3
->omod
= cmp_vop3
->omod
;
1579 new_vop3
->opsel
= cmp_vop3
->opsel
;
1580 new_instr
= new_vop3
;
1582 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1584 new_instr
->operands
[0] = cmp
->operands
[0];
1585 new_instr
->operands
[1] = cmp
->operands
[1];
1586 new_instr
->definitions
[0] = instr
->definitions
[0];
1588 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1589 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1591 instr
.reset(new_instr
);
1596 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1597 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1599 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1601 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1603 if (!instr
->operands
[0].isTemp())
1606 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1610 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1611 if (new_opcode
== aco_opcode::last_opcode
)
1614 if (cmp
->operands
[0].isTemp())
1615 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1616 if (cmp
->operands
[1].isTemp())
1617 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1618 decrease_uses(ctx
, cmp
);
1620 Instruction
*new_instr
;
1621 if (cmp
->isVOP3()) {
1622 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1623 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1624 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1625 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1626 new_vop3
->clamp
= cmp_vop3
->clamp
;
1627 new_vop3
->omod
= cmp_vop3
->omod
;
1628 new_vop3
->opsel
= cmp_vop3
->opsel
;
1629 new_instr
= new_vop3
;
1631 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1633 new_instr
->operands
[0] = cmp
->operands
[0];
1634 new_instr
->operands
[1] = cmp
->operands
[1];
1635 new_instr
->definitions
[0] = instr
->definitions
[0];
1637 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1638 ctx
.info
[instr
->definitions
[0].tempId()].set_fcmp(new_instr
);
1640 instr
.reset(new_instr
);
1645 /* op1(op2(1, 2), 0) if swap = false
1646 * op1(0, op2(1, 2)) if swap = true */
1647 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1648 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1649 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1650 bool *op1_clamp
, uint8_t *op1_omod
,
1651 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1654 if (op1_instr
->opcode
!= op1
)
1657 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1658 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1660 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1663 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1664 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1666 /* don't support inbetween clamp/omod */
1667 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1670 /* get operands and modifiers and check inbetween modifiers */
1671 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1672 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1675 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1676 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1680 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1681 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1684 if (inbetween_opsel
)
1685 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1686 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1690 shuffle
[shuffle_str
[0] - '0'] = 0;
1691 shuffle
[shuffle_str
[1] - '0'] = 1;
1692 shuffle
[shuffle_str
[2] - '0'] = 2;
1694 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1695 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1696 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1697 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1698 *opsel
|= 1 << shuffle
[0];
1700 for (unsigned i
= 0; i
< 2; i
++) {
1701 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1702 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1703 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1704 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1705 *opsel
|= 1 << shuffle
[i
+ 1];
1708 /* check operands */
1709 if (!check_vop3_operands(ctx
, 3, operands
))
1715 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1716 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1717 bool clamp
, unsigned omod
)
1719 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1720 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1721 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1722 new_instr
->clamp
= clamp
;
1723 new_instr
->omod
= omod
;
1724 new_instr
->opsel
= opsel
;
1725 new_instr
->operands
[0] = operands
[0];
1726 new_instr
->operands
[1] = operands
[1];
1727 new_instr
->operands
[2] = operands
[2];
1728 new_instr
->definitions
[0] = instr
->definitions
[0];
1729 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1731 instr
.reset(new_instr
);
1734 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1736 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1737 (label_omod_success
| label_clamp_success
);
1739 for (unsigned swap
= 0; swap
< 2; swap
++) {
1740 if (!((1 << swap
) & ops
))
1743 Operand operands
[3];
1744 bool neg
[3], abs
[3], clamp
;
1745 uint8_t opsel
= 0, omod
= 0;
1746 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1747 instr
.get(), swap
, shuffle
,
1748 operands
, neg
, abs
, &opsel
,
1749 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1750 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1751 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1752 if (omod_clamp
& label_omod_success
)
1753 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1754 if (omod_clamp
& label_clamp_success
)
1755 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1762 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1764 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1767 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1768 (label_omod_success
| label_clamp_success
);
1770 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1771 * max(-min(a, b), c) -> max3(-a, -b, c) */
1772 for (unsigned swap
= 0; swap
< 2; swap
++) {
1773 Operand operands
[3];
1774 bool neg
[3], abs
[3], clamp
;
1775 uint8_t opsel
= 0, omod
= 0;
1777 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
1778 instr
.get(), swap
, "012",
1779 operands
, neg
, abs
, &opsel
,
1780 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
1782 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1785 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1786 if (omod_clamp
& label_omod_success
)
1787 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1788 if (omod_clamp
& label_clamp_success
)
1789 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1796 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
1797 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
1798 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
1799 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
1800 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
1801 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
1802 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1805 if (!instr
->operands
[0].isTemp())
1807 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1810 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
1813 switch (op2_instr
->opcode
) {
1814 case aco_opcode::s_and_b32
:
1815 case aco_opcode::s_or_b32
:
1816 case aco_opcode::s_xor_b32
:
1817 case aco_opcode::s_and_b64
:
1818 case aco_opcode::s_or_b64
:
1819 case aco_opcode::s_xor_b64
:
1825 /* create instruction */
1826 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
1827 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
1828 ctx
.uses
[instr
->operands
[0].tempId()]--;
1829 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
1831 switch (op2_instr
->opcode
) {
1832 case aco_opcode::s_and_b32
:
1833 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
1835 case aco_opcode::s_or_b32
:
1836 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
1838 case aco_opcode::s_xor_b32
:
1839 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
1841 case aco_opcode::s_and_b64
:
1842 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
1844 case aco_opcode::s_or_b64
:
1845 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
1847 case aco_opcode::s_xor_b64
:
1848 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
1857 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
1858 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
1859 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
1860 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
1861 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1863 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
1866 for (unsigned i
= 0; i
< 2; i
++) {
1867 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1868 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
1870 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
1873 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1874 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1877 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1878 instr
->operands
[0] = instr
->operands
[!i
];
1879 instr
->operands
[1] = op2_instr
->operands
[0];
1880 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1882 switch (instr
->opcode
) {
1883 case aco_opcode::s_and_b32
:
1884 instr
->opcode
= aco_opcode::s_andn2_b32
;
1886 case aco_opcode::s_or_b32
:
1887 instr
->opcode
= aco_opcode::s_orn2_b32
;
1889 case aco_opcode::s_and_b64
:
1890 instr
->opcode
= aco_opcode::s_andn2_b64
;
1892 case aco_opcode::s_or_b64
:
1893 instr
->opcode
= aco_opcode::s_orn2_b64
;
1904 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
1905 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
1907 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
1910 for (unsigned i
= 0; i
< 2; i
++) {
1911 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
1912 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
1913 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
1915 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
1918 uint32_t shift
= op2_instr
->operands
[1].constantValue();
1919 if (shift
< 1 || shift
> 4)
1922 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
1923 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
1926 ctx
.uses
[instr
->operands
[i
].tempId()]--;
1927 instr
->operands
[1] = instr
->operands
[!i
];
1928 instr
->operands
[0] = op2_instr
->operands
[0];
1929 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1931 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
1932 aco_opcode::s_lshl2_add_u32
,
1933 aco_opcode::s_lshl3_add_u32
,
1934 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
1941 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
1944 #define MINMAX(type, gfx9) \
1945 case aco_opcode::v_min_##type:\
1946 case aco_opcode::v_max_##type:\
1947 case aco_opcode::v_med3_##type:\
1948 *min = aco_opcode::v_min_##type;\
1949 *max = aco_opcode::v_max_##type;\
1950 *med3 = aco_opcode::v_med3_##type;\
1951 *min3 = aco_opcode::v_min3_##type;\
1952 *max3 = aco_opcode::v_max3_##type;\
1953 *some_gfx9_only = gfx9;\
1967 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
1968 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
1969 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
1970 aco_opcode min
, aco_opcode max
, aco_opcode med
)
1972 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
1973 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
1974 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
1975 aco_opcode other_op
;
1976 if (instr
->opcode
== min
)
1978 else if (instr
->opcode
== max
)
1983 uint32_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1984 (label_omod_success
| label_clamp_success
);
1986 for (unsigned swap
= 0; swap
< 2; swap
++) {
1987 Operand operands
[3];
1988 bool neg
[3], abs
[3], clamp
;
1989 uint8_t opsel
= 0, omod
= 0;
1990 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
1991 "012", operands
, neg
, abs
, &opsel
,
1992 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1993 int const0_idx
= -1, const1_idx
= -1;
1994 uint32_t const0
= 0, const1
= 0;
1995 for (int i
= 0; i
< 3; i
++) {
1997 if (operands
[i
].isConstant()) {
1998 val
= operands
[i
].constantValue();
1999 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal()) {
2000 val
= ctx
.info
[operands
[i
].tempId()].val
;
2004 if (const0_idx
>= 0) {
2012 if (const0_idx
< 0 || const1_idx
< 0)
2015 if (opsel
& (1 << const0_idx
))
2017 if (opsel
& (1 << const1_idx
))
2020 int lower_idx
= const0_idx
;
2022 case aco_opcode::v_min_f32
:
2023 case aco_opcode::v_min_f16
: {
2024 float const0_f
, const1_f
;
2025 if (min
== aco_opcode::v_min_f32
) {
2026 memcpy(&const0_f
, &const0
, 4);
2027 memcpy(&const1_f
, &const1
, 4);
2029 const0_f
= _mesa_half_to_float(const0
);
2030 const1_f
= _mesa_half_to_float(const1
);
2032 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2033 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2034 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2035 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2036 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2039 case aco_opcode::v_min_u32
: {
2040 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2043 case aco_opcode::v_min_u16
: {
2044 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2047 case aco_opcode::v_min_i32
: {
2048 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2049 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2050 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2053 case aco_opcode::v_min_i16
: {
2054 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2055 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2056 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2062 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2064 if (instr
->opcode
== min
) {
2065 if (upper_idx
!= 0 || lower_idx
== 0)
2068 if (upper_idx
== 0 || lower_idx
!= 0)
2072 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2073 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2074 if (omod_clamp
& label_omod_success
)
2075 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2076 if (omod_clamp
& label_clamp_success
)
2077 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2087 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2089 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2090 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2091 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2093 /* find candidates and create the set of sgprs already read */
2094 unsigned sgpr_ids
[2] = {0, 0};
2095 uint32_t operand_mask
= 0;
2096 bool has_literal
= false;
2097 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2098 if (instr
->operands
[i
].isLiteral())
2100 if (!instr
->operands
[i
].isTemp())
2102 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2103 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2104 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2106 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2107 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2108 operand_mask
|= 1u << i
;
2110 unsigned max_sgprs
= 1;
2111 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2116 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2118 /* keep on applying sgprs until there is nothing left to be done */
2119 while (operand_mask
) {
2120 uint32_t sgpr_idx
= 0;
2121 uint32_t sgpr_info_id
= 0;
2122 uint32_t mask
= operand_mask
;
2125 unsigned i
= u_bit_scan(&mask
);
2126 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2127 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2129 sgpr_info_id
= instr
->operands
[i
].tempId();
2132 operand_mask
&= ~(1u << sgpr_idx
);
2134 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2135 * definitively beneficial.
2136 * TODO: this is too conservative because later the use count could be reduced to 1 */
2137 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2140 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2141 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2142 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2145 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2146 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2147 } else if (can_swap_operands(instr
)) {
2148 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2149 instr
->operands
[0] = Operand(sgpr
);
2150 /* swap bits using a 4-entry LUT */
2151 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2152 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2153 } else if (can_use_VOP3(ctx
, instr
)) {
2154 to_VOP3(ctx
, instr
);
2155 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2161 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2162 ctx
.uses
[sgpr_info_id
]--;
2163 ctx
.uses
[sgpr
.id()]++;
2167 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2169 /* check if we could apply omod on predecessor */
2170 if (instr
->opcode
== aco_opcode::v_mul_f32
) {
2171 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2172 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2174 unsigned idx
= op0
? 0 : 1;
2175 /* omod was successfully applied */
2176 /* if the omod instruction is v_mad, we also have to change the original add */
2177 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2178 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2179 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2180 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2181 add_instr
->definitions
[0] = instr
->definitions
[0];
2184 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2185 /* check if we have an additional clamp modifier */
2186 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2187 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2188 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2189 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2191 /* change definition ssa-id of modified instruction */
2192 omod_instr
->definitions
[0] = instr
->definitions
[0];
2194 /* change the definition of instr to something unused, e.g. the original omod def */
2195 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2196 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2199 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2200 /* in all other cases, label this instruction as option for multiply-add */
2201 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2205 /* check if we could apply clamp on predecessor */
2206 if (instr
->opcode
== aco_opcode::v_med3_f32
) {
2208 bool found_zero
= false, found_one
= false;
2209 for (unsigned i
= 0; i
< 3; i
++)
2211 if (instr
->operands
[i
].constantEquals(0))
2213 else if (instr
->operands
[i
].constantEquals(0x3f800000)) /* 1.0 */
2218 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2219 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2220 /* clamp was successfully applied */
2221 /* if the clamp instruction is v_mad, we also have to change the original add */
2222 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2223 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].val
].add_instr
.get();
2224 add_instr
->definitions
[0] = instr
->definitions
[0];
2226 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2227 /* change definition ssa-id of modified instruction */
2228 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2230 /* change the definition of instr to something unused, e.g. the original omod def */
2231 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2232 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2237 /* omod has no effect if denormals are enabled */
2238 bool can_use_omod
= block
.fp_mode
.denorm32
== 0;
2240 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2241 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2242 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2243 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2244 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2245 to_VOP3(ctx
, instr
);
2246 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2247 def_info
.set_omod_success(instr
.get());
2248 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2249 to_VOP3(ctx
, instr
);
2250 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2251 def_info
.set_omod_success(instr
.get());
2252 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2253 to_VOP3(ctx
, instr
);
2254 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2255 def_info
.set_omod_success(instr
.get());
2256 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2257 to_VOP3(ctx
, instr
);
2258 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2259 def_info
.set_clamp_success(instr
.get());
2266 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2267 // this would mean that we'd have to fix the instruction uses while value propagation
2269 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2271 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2274 if (instr
->isVALU()) {
2275 if (can_apply_sgprs(instr
))
2276 apply_sgprs(ctx
, instr
);
2277 if (apply_omod_clamp(ctx
, block
, instr
))
2281 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2282 instr
->definitions
[0].setHint(vcc
);
2285 /* TODO: There are still some peephole optimizations that could be done:
2286 * - abs(a - b) -> s_absdiff_i32
2287 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2288 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2289 * These aren't probably too interesting though.
2290 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2291 * probably more useful than the previously mentioned optimizations.
2292 * The various comparison optimizations also currently only work with 32-bit
2295 /* neg(mul(a, b)) -> mul(neg(a), b) */
2296 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2297 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2299 if (!ctx
.info
[val
.id()].is_mul())
2302 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2304 if (mul_instr
->operands
[0].isLiteral())
2306 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2309 /* convert to mul(neg(a), b) */
2310 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2311 Definition def
= instr
->definitions
[0];
2312 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2313 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2314 instr
.reset(create_instruction
<VOP3A_instruction
>(aco_opcode::v_mul_f32
, asVOP3(Format::VOP2
), 2, 1));
2315 instr
->operands
[0] = mul_instr
->operands
[0];
2316 instr
->operands
[1] = mul_instr
->operands
[1];
2317 instr
->definitions
[0] = def
;
2318 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2319 if (mul_instr
->isVOP3()) {
2320 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2321 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2322 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2323 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2324 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2325 new_mul
->omod
= mul
->omod
;
2327 new_mul
->neg
[0] ^= true;
2328 new_mul
->clamp
= false;
2330 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2333 /* combine mul+add -> mad */
2334 else if ((instr
->opcode
== aco_opcode::v_add_f32
||
2335 instr
->opcode
== aco_opcode::v_sub_f32
||
2336 instr
->opcode
== aco_opcode::v_subrev_f32
) &&
2337 block
.fp_mode
.denorm32
== 0 && !block
.fp_mode
.preserve_signed_zero_inf_nan32
) {
2338 //TODO: we could use fma instead when denormals are enabled if the NIR isn't marked as precise
2340 uint32_t uses_src0
= UINT32_MAX
;
2341 uint32_t uses_src1
= UINT32_MAX
;
2342 Instruction
* mul_instr
= nullptr;
2343 unsigned add_op_idx
;
2344 /* check if any of the operands is a multiplication */
2345 if (instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_mul())
2346 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2347 if (instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_mul())
2348 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2350 /* find the 'best' mul instruction to combine with the add */
2351 if (uses_src0
< uses_src1
) {
2352 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2354 } else if (uses_src1
< uses_src0
) {
2355 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2357 } else if (uses_src0
!= UINT32_MAX
) {
2358 /* tiebreaker: quite random what to pick */
2359 if (ctx
.info
[instr
->operands
[0].tempId()].instr
->operands
[0].isLiteral()) {
2360 mul_instr
= ctx
.info
[instr
->operands
[1].tempId()].instr
;
2363 mul_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2368 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2369 bool neg
[3] = {false, false, false};
2370 bool abs
[3] = {false, false, false};
2373 op
[0] = mul_instr
->operands
[0];
2374 op
[1] = mul_instr
->operands
[1];
2375 op
[2] = instr
->operands
[add_op_idx
];
2376 // TODO: would be better to check this before selecting a mul instr?
2377 if (!check_vop3_operands(ctx
, 3, op
))
2380 if (mul_instr
->isVOP3()) {
2381 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2382 neg
[0] = vop3
->neg
[0];
2383 neg
[1] = vop3
->neg
[1];
2384 abs
[0] = vop3
->abs
[0];
2385 abs
[1] = vop3
->abs
[1];
2386 /* we cannot use these modifiers between mul and add */
2387 if (vop3
->clamp
|| vop3
->omod
)
2391 /* convert to mad */
2392 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2393 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2395 ctx
.uses
[op
[0].tempId()]++;
2397 ctx
.uses
[op
[1].tempId()]++;
2400 if (instr
->isVOP3()) {
2401 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2402 neg
[2] = vop3
->neg
[add_op_idx
];
2403 abs
[2] = vop3
->abs
[add_op_idx
];
2405 clamp
= vop3
->clamp
;
2406 /* abs of the multiplication result */
2407 if (vop3
->abs
[1 - add_op_idx
]) {
2413 /* neg of the multiplication result */
2414 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2416 if (instr
->opcode
== aco_opcode::v_sub_f32
)
2417 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2418 else if (instr
->opcode
== aco_opcode::v_subrev_f32
)
2419 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2421 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_mad_f32
, Format::VOP3A
, 3, 1)};
2422 for (unsigned i
= 0; i
< 3; i
++)
2424 mad
->operands
[i
] = op
[i
];
2425 mad
->neg
[i
] = neg
[i
];
2426 mad
->abs
[i
] = abs
[i
];
2430 mad
->definitions
[0] = instr
->definitions
[0];
2432 /* mark this ssa_def to be re-checked for profitability and literals */
2433 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2434 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2435 instr
.reset(mad
.release());
2439 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2440 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2441 for (unsigned i
= 0; i
< 2; i
++) {
2442 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2443 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2444 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2445 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2446 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2448 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2449 new_instr
->operands
[0] = Operand(0u);
2450 new_instr
->operands
[1] = instr
->operands
[!i
];
2451 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2452 new_instr
->definitions
[0] = instr
->definitions
[0];
2453 instr
.reset(new_instr
.release());
2454 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2458 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2459 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2460 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2461 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2462 } else if (instr
->opcode
== aco_opcode::v_add_u32
&& ctx
.program
->chip_class
>= GFX9
) {
2463 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2464 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2465 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2466 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2467 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2468 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2469 combine_salu_lshl_add(ctx
, instr
);
2470 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2471 combine_salu_not_bitwise(ctx
, instr
);
2472 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2473 if (combine_inverse_comparison(ctx
, instr
)) ;
2474 else combine_salu_not_bitwise(ctx
, instr
);
2475 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2476 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2477 if (combine_ordering_test(ctx
, instr
)) ;
2478 else if (combine_comparison_ordering(ctx
, instr
)) ;
2479 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2480 else combine_salu_n2(ctx
, instr
);
2482 aco_opcode min
, max
, min3
, max3
, med3
;
2483 bool some_gfx9_only
;
2484 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2485 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2486 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2487 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2492 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2494 switch (instr
->opcode
) {
2495 case aco_opcode::s_and_b32
:
2496 case aco_opcode::s_and_b64
:
2497 instr
->opcode
= aco_opcode::s_and_b32
;
2499 case aco_opcode::s_or_b32
:
2500 case aco_opcode::s_or_b64
:
2501 instr
->opcode
= aco_opcode::s_or_b32
;
2503 case aco_opcode::s_xor_b32
:
2504 case aco_opcode::s_xor_b64
:
2505 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2508 /* Don't transform other instructions. They are very unlikely to appear here. */
2512 for (Operand
&op
: instr
->operands
) {
2513 ctx
.uses
[op
.tempId()]--;
2515 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2516 /* Just use the uniform boolean temp. */
2517 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2518 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2519 /* Use the SCC definition of the predecessor instruction.
2520 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2521 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2523 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2524 assert(pred_instr
->definitions
.size() >= 2);
2525 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2526 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2528 unreachable("Invalid operand on uniform bitwise instruction.");
2531 ctx
.uses
[op
.tempId()]++;
2534 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2535 assert(instr
->operands
[0].regClass() == s1
);
2536 assert(instr
->operands
[1].regClass() == s1
);
2540 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2542 const uint32_t threshold
= 4;
2544 if (is_dead(ctx
.uses
, instr
.get())) {
2549 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2550 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2551 unsigned num_used
= 0;
2553 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
2554 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2560 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2561 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2562 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2566 for (Operand
& vec_op
: vec
->operands
) {
2567 if (off
== idx
* instr
->definitions
[0].size()) {
2571 off
+= vec_op
.size();
2573 if (off
!= instr
->operands
[0].size()) {
2574 ctx
.uses
[instr
->operands
[0].tempId()]--;
2575 for (Operand
& vec_op
: vec
->operands
) {
2576 if (vec_op
.isTemp())
2577 ctx
.uses
[vec_op
.tempId()]--;
2580 ctx
.uses
[op
.tempId()]++;
2582 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2583 extract
->operands
[0] = op
;
2584 extract
->definitions
[0] = instr
->definitions
[idx
];
2585 instr
.reset(extract
.release());
2591 if (!done
&& num_used
== 1) {
2592 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2593 extract
->operands
[0] = instr
->operands
[0];
2594 extract
->operands
[1] = Operand((uint32_t) idx
);
2595 extract
->definitions
[0] = instr
->definitions
[idx
];
2596 instr
.reset(extract
.release());
2600 mad_info
* mad_info
= NULL
;
2601 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2602 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2603 /* re-check mad instructions */
2604 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2605 ctx
.uses
[mad_info
->mul_temp_id
]++;
2606 if (instr
->operands
[0].isTemp())
2607 ctx
.uses
[instr
->operands
[0].tempId()]--;
2608 if (instr
->operands
[1].isTemp())
2609 ctx
.uses
[instr
->operands
[1].tempId()]--;
2610 instr
.swap(mad_info
->add_instr
);
2613 /* check literals */
2614 else if (!instr
->usesModifiers()) {
2615 bool sgpr_used
= false;
2616 uint32_t literal_idx
= 0;
2617 uint32_t literal_uses
= UINT32_MAX
;
2618 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2620 if (instr
->operands
[i
].isConstant() && i
> 0) {
2621 literal_uses
= UINT32_MAX
;
2624 if (!instr
->operands
[i
].isTemp())
2626 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2627 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2628 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal()) {
2629 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2632 literal_uses
= UINT32_MAX
;
2635 /* don't break because we still need to check constants */
2636 } else if (!sgpr_used
&&
2637 ctx
.info
[instr
->operands
[i
].tempId()].is_literal() &&
2638 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2639 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2644 /* Limit the number of literals to apply to not increase the code
2645 * size too much, but always apply literals for v_mad->v_madak
2646 * because both instructions are 64-bit and this doesn't increase
2648 * TODO: try to apply the literals earlier to lower the number of
2649 * uses below threshold
2651 if (literal_uses
< threshold
|| literal_idx
== 2) {
2652 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2653 mad_info
->check_literal
= true;
2654 mad_info
->literal_idx
= literal_idx
;
2660 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2661 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2662 instr
->operands
.size() &&
2663 instr
->operands
[0].isTemp()) {
2664 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2666 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2667 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2668 instr
->operands
[2].isTemp()) {
2669 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2672 /* check for literals */
2673 if (!instr
->isSALU() && !instr
->isVALU())
2676 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2677 if (instr
->definitions
.size() &&
2678 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2679 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2680 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2682 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2683 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2684 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2685 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2686 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2687 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
2693 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
2694 return; /* some encodings can't ever take literals */
2696 /* we do not apply the literals yet as we don't know if it is profitable */
2697 Operand
current_literal(s1
);
2699 unsigned literal_id
= 0;
2700 unsigned literal_uses
= UINT32_MAX
;
2701 Operand
literal(s1
);
2702 unsigned num_operands
= 1;
2703 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
2704 num_operands
= instr
->operands
.size();
2705 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
2706 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
2709 unsigned sgpr_ids
[2] = {0, 0};
2710 bool is_literal_sgpr
= false;
2713 /* choose a literal to apply */
2714 for (unsigned i
= 0; i
< num_operands
; i
++) {
2715 Operand op
= instr
->operands
[i
];
2717 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
2718 op
.tempId() != sgpr_ids
[0])
2719 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
2721 if (op
.isLiteral()) {
2722 current_literal
= op
;
2724 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal()) {
2728 if (!alu_can_accept_constant(instr
->opcode
, i
))
2731 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
2732 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
2734 literal
= Operand(ctx
.info
[op
.tempId()].val
);
2735 literal_uses
= ctx
.uses
[op
.tempId()];
2736 literal_id
= op
.tempId();
2739 mask
|= (op
.tempId() == literal_id
) << i
;
2743 /* don't go over the constant bus limit */
2744 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2745 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2746 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2747 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
2748 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2749 const_bus_limit
= 2;
2751 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2752 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
2755 if (literal_id
&& literal_uses
< threshold
&&
2756 (current_literal
.isUndefined() ||
2757 (current_literal
.size() == literal
.size() &&
2758 current_literal
.constantValue() == literal
.constantValue()))) {
2759 /* mark the literal to be applied */
2761 unsigned i
= u_bit_scan(&mask
);
2762 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
2763 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2769 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2771 /* Cleanup Dead Instructions */
2775 /* apply literals on MAD */
2776 if (instr
->opcode
== aco_opcode::v_mad_f32
&& ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2777 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].val
];
2778 if (info
->check_literal
&&
2779 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
2780 aco_ptr
<Instruction
> new_mad
;
2781 if (info
->literal_idx
== 2) { /* add literal -> madak */
2782 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madak_f32
, Format::VOP2
, 3, 1));
2783 new_mad
->operands
[0] = instr
->operands
[0];
2784 new_mad
->operands
[1] = instr
->operands
[1];
2785 } else { /* mul literal -> madmk */
2786 new_mad
.reset(create_instruction
<VOP2_instruction
>(aco_opcode::v_madmk_f32
, Format::VOP2
, 3, 1));
2787 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
2788 new_mad
->operands
[1] = instr
->operands
[2];
2790 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
2791 new_mad
->definitions
[0] = instr
->definitions
[0];
2792 ctx
.instructions
.emplace_back(std::move(new_mad
));
2797 /* apply literals on other SALU/VALU */
2798 if (instr
->isSALU() || instr
->isVALU()) {
2799 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2800 Operand op
= instr
->operands
[i
];
2801 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal() && ctx
.uses
[op
.tempId()] == 0) {
2802 Operand
literal(ctx
.info
[op
.tempId()].val
);
2803 if (instr
->isVALU() && i
> 0)
2804 to_VOP3(ctx
, instr
);
2805 instr
->operands
[i
] = literal
;
2810 ctx
.instructions
.emplace_back(std::move(instr
));
2814 void optimize(Program
* program
)
2817 ctx
.program
= program
;
2818 std::vector
<ssa_info
> info(program
->peekAllocationId());
2819 ctx
.info
= info
.data();
2821 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
2822 for (Block
& block
: program
->blocks
) {
2823 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2824 label_instruction(ctx
, block
, instr
);
2827 ctx
.uses
= std::move(dead_code_analysis(program
));
2829 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
2830 for (Block
& block
: program
->blocks
) {
2831 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2832 combine_instruction(ctx
, block
, instr
);
2835 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
2836 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
2837 Block
* block
= &(*it
);
2838 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
2839 select_instruction(ctx
, *it
);
2842 /* 4. Add literals to instructions */
2843 for (Block
& block
: program
->blocks
) {
2844 ctx
.instructions
.clear();
2845 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
2846 apply_literals(ctx
, instr
);
2847 block
.instructions
.swap(ctx
.instructions
);